diff options
234 files changed, 6733 insertions, 11162 deletions
@@ -57,6 +57,7 @@ John Linn <john.linn@amd.com> <john.linn@xilinx.com> Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyothee@xilinx.com> Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyotheeswar.reddy.mutthareddyvari@xilinx.com> Kalyani Akula <kalyani.akula@amd.com> <kalyani.akula@xilinx.com> +Masahisa Kojima <kojima.masahisa@socionext.com> <masahisa.kojima@linaro.org> Love Kumar <love.kumar@amd.com> <love.kumar@xilinx.com> Lukasz Majewski <lukma@denx.de> Marek Behún <kabel@kernel.org> <marek.behun@nic.cz> diff --git a/MAINTAINERS b/MAINTAINERS index 8b316c8550e..0462ade4ac6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -55,6 +55,7 @@ M: Simon Glass <sjg@chromium.org> S: Maintained F: board/emulation/configs/acpi.config F: cmd/acpi.c +F: include/acpi/ F: lib/acpi/ ANDROID AB @@ -1371,6 +1372,12 @@ M: Simon Glass <sjg@chromium.org> S: Maintained F: tools/patman/ +PCIe DWC IMX +M: Sumit Garg <sumit.garg@linaro.org> +S: Maintained +F: drivers/pci/pcie_dw_imx.c +F: drivers/phy/phy-imx8m-pcie.c + PCI Endpoint M: Ramon Fried <rfried.dev@gmail.com> S: Maintained @@ -3,7 +3,7 @@ VERSION = 2024 PATCHLEVEL = 04 SUBLEVEL = -EXTRAVERSION = -rc4 +EXTRAVERSION = -rc5 NAME = # *DOCUMENTATION* @@ -1300,12 +1300,17 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),$(if $(CONFIG_OF_SEPARATE),-R .bootpg -R .resetvec)) binary_size_check: u-boot-nodtb.bin FORCE - @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \ + @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{ print $$1 }') ; \ map_size=$(shell cat u-boot.map | \ - awk '/_image_copy_start/ {start = $$1} /_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print "ibase=16; " toupper(end) " - " toupper(start)}' \ - | sed 's/0X//g' \ - | bc); \ - if [ "" != "$$map_size" ]; then \ + awk ' \ + /_image_copy_start/ { start = $$1 } \ + /_image_binary_end/ { end = $$1 } \ + END { \ + if (start != "" && end != "") \ + print end " " start; \ + }' \ + | sh -c 'read end start && echo $$((end - start))'); \ + if [ -n "$$map_size" ]; then \ if test $$map_size -ne $$file_size; then \ echo "u-boot.map shows a binary size of $$map_size" >&2 ; \ echo " but u-boot-nodtb.bin shows $$file_size" >&2 ; \ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 71c96479147..a0842e19330 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -29,6 +29,7 @@ config COUNTER_FREQUENCY ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A default 100000000 if ARCH_ZYNQMP + default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5 default 0 help For platforms with ARMv8-A and ARMv7-A which features a system @@ -123,6 +124,15 @@ config GIC_V3_ITS ARM GICV3 has limitation, once the LPI table is enabled, LPI configuration table can not be re-programmed, unless GICV3 reset. +config GICV3_SUPPORT_GIC600 + bool "ARM GICV3 GIC600 SUPPORT" + help + ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, + implements a power control register in the Redistributor frame.This + register must be programmed to mark the frame as powered on, before + accessing other registers in the frame. Rest of initialization sequence + remains the same. + config STATIC_RELA bool default y if ARM64 @@ -1098,6 +1108,8 @@ config ARCH_SOCFPGA select SPL_LIBGENERIC_SUPPORT select SPL_OF_CONTROL select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 + select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64 + select SPL_SOCFPGA_DT_REG if TARGET_SOCFPGA_SOC64 select SPL_SERIAL select SPL_SYSRESET select SPL_WATCHDOG @@ -1106,7 +1118,8 @@ config ARCH_SOCFPGA select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64 + select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \ + TARGET_SOCFPGA_SOC64 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 3fe935cf283..c9e46859b4f 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -20,6 +20,7 @@ * * x0: cache level * x1: 0 clean & invalidate, 1 invalidate only + * x16: FEAT_CCIDX * x2~x9: clobbered */ .pushsection .text.__asm_dcache_level, "ax" @@ -29,8 +30,14 @@ ENTRY(__asm_dcache_level) isb /* sync change of cssidr_el1 */ mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ ubfx x2, x6, #0, #3 /* x2 <- log2(cache line size)-4 */ + cbz x16, 3f /* check for FEAT_CCIDX */ + ubfx x3, x6, #3, #21 /* x3 <- number of cache ways - 1 */ + ubfx x4, x6, #32, #24 /* x4 <- number of cache sets - 1 */ + b 4f +3: ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */ ubfx x4, x6, #13, #15 /* x4 <- number of cache sets - 1 */ +4: add x2, x2, #4 /* x2 <- log2(cache line size) */ clz w5, w3 /* bit position of #ways */ /* x12 <- cache level << 1 */ @@ -74,6 +81,8 @@ ENTRY(__asm_dcache_all) ubfx x11, x10, #24, #3 /* x11 <- loc */ cbz x11, finished /* if loc is 0, exit */ mov x15, lr + mrs x16, s3_0_c0_c7_2 /* read value of id_aa64mmfr2_el1*/ + ubfx x16, x16, #20, #4 /* save FEAT_CCIDX identifier in x16 */ mov x0, #0 /* start flush at cache level 0 */ /* x0 <- cache level */ /* x10 <- clidr_el1 */ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dabd3b91859..d85a33055c9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -546,6 +546,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex_socdk.dtb \ + socfpga_agilex5_socdk.dtb \ socfpga_arria5_secu1.dtb \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3_270_2.dtb \ @@ -1082,15 +1083,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-phg.dtb \ imx8mm-phyboard-polis-rdk.dtb \ imx8mm-phygate-tauri-l.dtb \ - imx8mm-venice.dtb \ - imx8mm-venice-gw71xx-0x.dtb \ - imx8mm-venice-gw72xx-0x.dtb \ - imx8mm-venice-gw73xx-0x.dtb \ - imx8mm-venice-gw7901.dtb \ - imx8mm-venice-gw7902.dtb \ - imx8mm-venice-gw7903.dtb \ - imx8mm-venice-gw7904.dtb \ - imx8mm-venice-gw7905-0x.dtb \ imx8mm-verdin-wifi-dev.dtb \ imx8mn-bsh-smm-s2.dtb \ imx8mn-bsh-smm-s2pro.dtb \ @@ -1098,8 +1090,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-cm.dtb \ imx8mn-evk.dtb \ imx8mn-var-som-symphony.dtb \ - imx8mn-venice.dtb \ - imx8mn-venice-gw7902.dtb \ imx8mq-evk.dtb \ imx8mm-beacon-kit.dtb \ imx8mn-beacon-kit.dtb \ @@ -1119,12 +1109,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-icore-mx8mp-edimm2.2.dtb \ imx8mp-msc-sm2s.dtb \ imx8mp-phyboard-pollux-rdk.dtb \ - imx8mp-venice.dtb \ - imx8mp-venice-gw71xx-2x.dtb \ - imx8mp-venice-gw72xx-2x.dtb \ - imx8mp-venice-gw73xx-2x.dtb \ - imx8mp-venice-gw74xx.dtb \ - imx8mp-venice-gw7905-2x.dtb \ imx8mp-verdin-wifi-dev.dtb \ imx8mq-pico-pi.dtb \ imx8mq-kontron-pitx-imx8m.dtb \ @@ -1265,6 +1249,9 @@ dtb-$(CONFIG_TARGET_OMAP4_SDP4430) += \ dtb-$(CONFIG_TARGET_SAMA7G5EK) += \ at91-sama7g5ek.dtb +dtb-$(CONFIG_TARGET_SAMA7G54_CURIOSITY) += \ + at91-sama7g54_curiosity.dtb + dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \ at91-sama5d2_ptc_ek.dtb @@ -1364,7 +1351,9 @@ dtb-$(CONFIG_BCM6878) += \ bcm96878.dtb dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb -dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb +dtb-$(CONFIG_ASPEED_AST2600) += \ + ast2600-evb.dtb \ + ast2600-x4tf.dtb dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb diff --git a/arch/arm/dts/ast2600-x4tf.dts b/arch/arm/dts/ast2600-x4tf.dts new file mode 100644 index 00000000000..4bf4b66a9ce --- /dev/null +++ b/arch/arm/dts/ast2600-x4tf.dts @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2024 ASUS Corp. +/dts-v1/; + +#include "ast2600-u-boot.dtsi" + +/ { + model = "AST2600 ASUS X4TF"; + compatible = "aspeed,ast2600-asus", "aspeed,ast2600"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + chosen { + stdout-path = &uart5; + }; + + aliases { + spi0 = &fmc; + ethernet0 = &mac2; + ethernet1 = &mac3; + }; + + cpus { + cpu@0 { + clock-frequency = <800000000>; + }; + + cpu@1 { + clock-frequency = <800000000>; + }; + }; +}; + +&uart5 { + status = "okay"; +}; + +&sdrammc { + clock-frequency = <400000000>; +}; + +&wdt1 { + status = "okay"; +}; + +&wdt2 { + status = "okay"; +}; + +&wdt3 { + status = "okay"; +}; + +&mac2 { + status = "okay"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; +}; + +&mac3 { + status = "okay"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; +}; + +&fmc { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor", "macronix,mx66l2g45g"; + status = "okay"; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; + + flash@1 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&hace { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "disabled"; +}; + +&i2c13 { + status = "disabled"; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&display_port { + status = "okay"; +}; diff --git a/arch/arm/dts/at91-sama7g54_curiosity-u-boot.dtsi b/arch/arm/dts/at91-sama7g54_curiosity-u-boot.dtsi new file mode 100644 index 00000000000..04d7d9e522d --- /dev/null +++ b/arch/arm/dts/at91-sama7g54_curiosity-u-boot.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * at91-sama7g54_curiosity-u-boot.dtsi - Device Tree file for SAMA7G5 SoC u-boot properties. + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Mihai Sain <mihai.sain@microchip.com> + * + */ + +/ { + chosen { + bootph-all; + }; +}; + +&main_rc { + bootph-all; +}; + +&main_xtal { + bootph-all; +}; + +&pioA { + bootph-all; +}; + +&pinctrl_flx3_default { + bootph-all; +}; + +&pinctrl_sdmmc1_default { + bootph-all; +}; + +&pit64b0 { + bootph-all; +}; + +&pmc { + bootph-all; +}; + +&sdmmc1 { + bootph-all; +}; + +&slow_rc_osc { + bootph-all; +}; + +&slow_xtal { + bootph-all; +}; + +&uart3 { + bootph-all; +}; diff --git a/arch/arm/dts/at91-sama7g54_curiosity.dts b/arch/arm/dts/at91-sama7g54_curiosity.dts new file mode 100644 index 00000000000..93c230be0a3 --- /dev/null +++ b/arch/arm/dts/at91-sama7g54_curiosity.dts @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama7g54_curiosity.dts - Device Tree file for SAMA7G54 CURIOSITY board + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Mihai Sain <mihai.sain@microchip.com> + * + */ +/dts-v1/; +#include "sama7g5-pinfunc.h" +#include "sama7g5.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/mfd/atmel-flexcom.h> +#include <dt-bindings/pinctrl/at91.h> + +/ { + model = "Microchip SAMA7G54 Curiosity"; + compatible = "microchip,sama7g54-curiosity", "microchip,sama7g5", "microchip,sama7"; + + aliases { + serial0 = &uart3; + i2c0 = &i2c10; + }; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait"; + stdout-path = "serial0:115200n8"; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <24000000>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + + led-red { + label = "red"; + gpios = <&pioA PIN_PD13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-green { + label = "green"; + gpios = <&pioA PIN_PD14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-blue { + label = "blue"; + gpios = <&pioA PIN_PB15 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x10000000>; // 256 MiB DDR3L-1066 16-bit + }; +}; + +&ebi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand_default>; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + }; + }; +}; + +&flx3 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; + status = "okay"; + + uart3: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx3_default>; + status = "okay"; + }; +}; + +&flx10 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; + status = "okay"; + + i2c10: i2c@600 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx10_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + + adc@1f { + compatible = "microchip,pac1934"; + reg = <0x1f>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + size = <256>; + }; + + pmic@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + }; + }; +}; + +&pioA { + pinctrl_flx3_default: flx3-default { + pinmux = <PIN_PD16__FLEXCOM3_IO0>, + <PIN_PD17__FLEXCOM3_IO1>; + bias-pull-up; + }; + + pinctrl_flx10_default: flx10-default { + pinmux = <PIN_PC30__FLEXCOM10_IO0>, + <PIN_PC31__FLEXCOM10_IO1>; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led-gpio-default { + pinmux = <PIN_PD13__GPIO>, + <PIN_PD14__GPIO>, + <PIN_PB15__GPIO>; + bias-pull-up; + }; + + pinctrl_nand_default: nand-default { + pinmux = <PIN_PD9__D0>, + <PIN_PD10__D1>, + <PIN_PD11__D2>, + <PIN_PC21__D3>, + <PIN_PC22__D4>, + <PIN_PC23__D5>, + <PIN_PC24__D6>, + <PIN_PD2__D7>, + <PIN_PD3__NANDRDY>, + <PIN_PD4__NCS3_NANDCS>, + <PIN_PD5__NWE_NWR0_NANDWE>, + <PIN_PD6__NRD_NANDOE>, + <PIN_PD7__A21_NANDALE>, + <PIN_PD8__A22_NANDCLE>; + bias-disable; + slew-rate = <0>; + }; + + pinctrl_qspi1_default: qspi1-default { + pinmux = <PIN_PB22__QSPI1_IO3>, + <PIN_PB23__QSPI1_IO2>, + <PIN_PB24__QSPI1_IO1>, + <PIN_PB25__QSPI1_IO0>, + <PIN_PB26__QSPI1_CS>, + <PIN_PB27__QSPI1_SCK>; + bias-pull-up; + slew-rate = <0>; + }; + + pinctrl_sdmmc0_default: sdmmc0-default { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_RSTN>, + <PIN_PA3__SDMMC0_DAT0>, + <PIN_PA4__SDMMC0_DAT1>, + <PIN_PA5__SDMMC0_DAT2>, + <PIN_PA6__SDMMC0_DAT3>; + bias-pull-up; + slew-rate = <0>; + }; + + pinctrl_sdmmc1_default: sdmmc1-default { + pinmux = <PIN_PB29__SDMMC1_CMD>, + <PIN_PB30__SDMMC1_CK>, + <PIN_PB31__SDMMC1_DAT0>, + <PIN_PC0__SDMMC1_DAT1>, + <PIN_PC1__SDMMC1_DAT2>, + <PIN_PC2__SDMMC1_DAT3>, + <PIN_PC4__SDMMC1_CD>; + bias-pull-up; + slew-rate = <0>; + }; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_default>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + }; +}; + +// M.2 slot for wireless card +&sdmmc0 { + bus-width = <4>; + cd-gpios = <&pioA 31 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <50000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + status = "okay"; +}; + +// micro SD socket +&sdmmc1 { + bus-width = <4>; + disable-wp; + max-frequency = <50000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi b/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi index 68142769d36..854bf2798ae 100644 --- a/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi +++ b/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi @@ -51,3 +51,7 @@ }; }; }; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8mm-venice-gw700x.dtsi b/arch/arm/dts/imx8mm-venice-gw700x.dtsi deleted file mode 100644 index c305e325d00..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw700x.dtsi +++ /dev/null @@ -1,525 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/net/ti-dp83867.h> - -/ { - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-user-pb { - label = "user_pb"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = <BTN_0>; - }; - - key-user-pb1x { - label = "user_pb1x"; - linux,code = <BTN_1>; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key_erased"; - linux,code = <BTN_2>; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - key-eeprom-wp { - label = "eeprom_wp"; - linux,code = <BTN_3>; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - key-tamper { - label = "tamper"; - linux,code = <BTN_4>; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = <BTN_5>; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; -}; - -&A53_0 { - cpu-supply = <&buck3_reg>; -}; - -&A53_1 { - cpu-supply = <&buck3_reg>; -}; - -&A53_2 { - cpu-supply = <&buck3_reg>; -}; - -&A53_3 { - cpu-supply = <&buck3_reg>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - pinctrl-0 = <&pinctrl_gsc>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@16 { - gw,mode = <4>; - reg = <0x16>; - label = "fan_tach"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vdd_vin"; - gw,voltage-divider-ohms = <22100 1000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vdd_adc1"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_adc2"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_dram"; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_1p2"; - }; - - channel@8e { - gw,mode = <2>; - reg = <0x8e>; - label = "vdd_1p0"; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_2p5"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@98 { - gw,mode = <2>; - reg = <0x98>; - label = "vdd_0p95"; - }; - - channel@9a { - gw,mode = <2>; - reg = <0x9a>; - label = "vdd_1p8"; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - - fan-controller@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "gw,gsc-fan"; - reg = <0x0a>; - }; - }; - - gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; - - pmic@69 { - compatible = "mps,mp5416"; - reg = <0x69>; - - regulators { - /* vdd_0p95: DRAM/GPU/VPU */ - buck1 { - regulator-name = "buck1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - regulator-min-microamp = <3800000>; - regulator-max-microamp = <6800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_soc */ - buck2 { - regulator-name = "buck2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-min-microamp = <2200000>; - regulator-max-microamp = <5200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_arm */ - buck3_reg: buck3 { - regulator-name = "buck3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - regulator-min-microamp = <3800000>; - regulator-max-microamp = <6800000>; - regulator-always-on; - }; - - /* vdd_1p8 */ - buck4 { - regulator-name = "buck4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-min-microamp = <2200000>; - regulator-max-microamp = <5200000>; - regulator-boot-on; - regulator-always-on; - }; - - /* nvcc_snvs_1p8 */ - ldo1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_snvs_0p8 */ - ldo2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_0p9 */ - ldo3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_1p8 */ - ldo4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; - pagesize = <32>; - }; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 - >; - }; - - pinctrl_gsc: gscgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw71xx-0x.dts b/arch/arm/dts/imx8mm-venice-gw71xx-0x.dts deleted file mode 100644 index 3f88c4ad571..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw71xx-0x.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mm.dtsi" -#include "imx8mm-venice-gw700x.dtsi" -#include "imx8mm-venice-gw71xx.dtsi" - -/ { - model = "Gateworks Venice GW71xx-0x i.MX8MM Development Kit"; - compatible = "gw,imx8mm-gw71xx-0x", "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw71xx.dtsi b/arch/arm/dts/imx8mm-venice-gw71xx.dtsi deleted file mode 100644 index c557dbf4dcd..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw71xx.dtsi +++ /dev/null @@ -1,239 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - aliases { - usb0 = &usbotg1; - usb1 = &usbotg2; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_en>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpio1 { - gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0", - "", "dio1", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio4>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* off-board header */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - over-current-active-low; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ - MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */ - MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 - >; - }; - - pinctrl_reg_usb1_en: regusb1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141 - MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw72xx-0x.dts b/arch/arm/dts/imx8mm-venice-gw72xx-0x.dts deleted file mode 100644 index 641be3af989..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw72xx-0x.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mm.dtsi" -#include "imx8mm-venice-gw700x.dtsi" -#include "imx8mm-venice-gw72xx.dtsi" - -/ { - model = "Gateworks Venice GW72xx-0x i.MX8MM Development Kit"; - compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw72xx.dtsi b/arch/arm/dts/imx8mm-venice-gw72xx.dtsi deleted file mode 100644 index 97ed34a3c58..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw72xx.dtsi +++ /dev/null @@ -1,400 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - aliases { - ethernet1 = ð1; - usb0 = &usbotg1; - usb1 = &usbotg2; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_en>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2_en>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, - <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; - - tpm@1 { - compatible = "tcg,tpm_tis-spi"; - reg = <0x1>; - spi-max-frequency = <36000000>; - }; -}; - -&gpio1 { - gpio-line-names = "rs485_term", "mipi_gpio4", "", "", - "", "", "pci_usb_sel", "dio0", - "", "dio1", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", - "mipi_gpio1", "", "", "pci_wdis#", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio4>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - status = "okay"; - - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - pcie@1,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - pcie@2,3 { - reg = <0x1800 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - eth1: pcie@5,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - local-mac-address = [00 00 00 00 00 00]; - }; - }; - }; - }; -}; - -/* off-board header */ -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* off-board header */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* RS232 */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - over-current-active-low; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - vbus-supply = <®_usb_otg2_vbus>; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */ - MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */ - MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 - >; - }; - - pinctrl_reg_usb1_en: regusb1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 - MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 - >; - }; - - pinctrl_reg_usb2_en: regusb2grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 - MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw73xx-0x.dts b/arch/arm/dts/imx8mm-venice-gw73xx-0x.dts deleted file mode 100644 index 6905437ff28..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw73xx-0x.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mm.dtsi" -#include "imx8mm-venice-gw700x.dtsi" -#include "imx8mm-venice-gw73xx.dtsi" - -/ { - model = "Gateworks Venice GW73xx-0x i.MX8MM Development Kit"; - compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw73xx.dtsi b/arch/arm/dts/imx8mm-venice-gw73xx.dtsi deleted file mode 100644 index 7b2130dbdb2..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw73xx.dtsi +++ /dev/null @@ -1,452 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - aliases { - ethernet1 = ð1; - usb0 = &usbotg1; - usb1 = &usbotg2; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_en>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2_en>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_wifi_en: regulator-wifi-en { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wl>; - compatible = "regulator-fixed"; - regulator-name = "wl"; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100>; - enable-active-high; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, - <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; - - tpm@1 { - compatible = "tcg,tpm_tis-spi"; - reg = <0x1>; - spi-max-frequency = <36000000>; - }; -}; - -&gpio1 { - gpio-line-names = "rs485_term", "mipi_gpio4", "", "", - "", "", "pci_usb_sel", "dio0", - "", "dio1", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", - "mipi_gpio1", "", "", "pci_wdis#", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio4>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - status = "okay"; - - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - pcie@1,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - pcie@2,4 { - reg = <0x2000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - eth1: pcie@6,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - local-mac-address = [00 00 00 00 00 00]; - }; - }; - }; - }; -}; - -/* off-board header */ -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* bluetooth HCI */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>; - cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; -}; - -/* RS232 */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - over-current-active-low; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - vbus-supply = <®_usb_otg2_vbus>; - status = "okay"; -}; - -/* SDIO WiFi */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wifi_en>; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */ - MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */ - MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 - >; - }; - - pinctrl_bten: btengrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 - >; - }; - - pinctrl_reg_wl: regwlgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 - >; - }; - - pinctrl_reg_usb1_en: regusb1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 - MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 - >; - }; - - pinctrl_reg_usb2_en: regusb2grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 - MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw7901.dts b/arch/arm/dts/imx8mm-venice-gw7901.dts deleted file mode 100644 index 826627bd450..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw7901.dts +++ /dev/null @@ -1,1137 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 Gateworks Corporation - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -#include "imx8mm.dtsi" - -/ { - model = "Gateworks Venice GW7901 i.MX8MM board"; - compatible = "gw,imx8mm-gw7901", "fsl,imx8mm"; - - aliases { - ethernet0 = &fec1; - ethernet1 = &lan1; - ethernet2 = &lan2; - ethernet3 = &lan3; - ethernet4 = &lan4; - usb0 = &usbotg1; - usb1 = &usbotg2; - }; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-user-pb { - label = "user_pb"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = <BTN_0>; - }; - - key-user-pb1x { - label = "user_pb1x"; - linux,code = <BTN_1>; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key_erased"; - linux,code = <BTN_2>; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - key-eeprom-wp { - label = "eeprom_wp"; - linux,code = <BTN_3>; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - key-tamper { - label = "tamper"; - linux,code = <BTN_4>; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = <BTN_5>; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - led-controller { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led01_red"; - gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led01_grn"; - gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-2 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led02_red"; - gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-3 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led02_grn"; - gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-4 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led03_red"; - gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-5 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led03_grn"; - gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-6 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led04_red"; - gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-7 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led04_grn"; - gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-8 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led05_red"; - gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-9 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led05_grn"; - gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-a { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led06_red"; - gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-b { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led06_grn"; - gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - regulator-ioexp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_ioexp>; - compatible = "regulator-fixed"; - regulator-name = "ioexp"; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - regulator-isouart { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_isouart>; - compatible = "regulator-fixed"; - regulator-name = "iso_uart"; - gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; - startup-delay-us = <100>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb2_vbus: regulator-usb2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2>; - compatible = "regulator-fixed"; - regulator-name = "usb_usb2_vbus"; - gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_wifi: regulator-wifi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wl>; - compatible = "regulator-fixed"; - regulator-name = "wifi"; - gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&disp_blk_ctrl { - status = "disabled"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - status = "okay"; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - local-mac-address = [00 00 00 00 00 00]; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gpio1 { - gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#", - "", "uart1_rs232#", "dig1_in", "dig1_out", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = "", "", "", "", - "", "", "uart3_rs232#", "uart3_rs422#", - "uart3_rs485#", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", ""; -}; - -&gpio5 { - gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "", - "", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpu_2d { - status = "disabled"; -}; - -&gpu_3d { - status = "disabled"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - pinctrl-0 = <&pinctrl_gsc>; - interrupt-parent = <&gpio4>; - interrupts = <16 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <1>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vin_aux1"; - gw,voltage-divider-ohms = <22100 1000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vin_aux2"; - gw,voltage-divider-ohms = <22100 1000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_vin"; - gw,voltage-divider-ohms = <22100 1000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_2p5"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@8e { - gw,mode = <2>; - reg = <0x8e>; - label = "vdd_0p95"; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_soc"; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_arm"; - }; - - channel@98 { - gw,mode = <2>; - reg = <0x98>; - label = "vdd_1p8"; - }; - - channel@9a { - gw,mode = <2>; - reg = <0x9a>; - label = "vdd_1p2"; - }; - - channel@9c { - gw,mode = <2>; - reg = <0x9c>; - label = "vdd_dram"; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - }; - - gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio3>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - /* vdd_soc: 0.805-0.900V (typ=0.8V) */ - BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - /* vdd_arm: 0.805-1.0V (typ=0.9V) */ - BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ - BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_3p3 */ - BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_1p8 */ - BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_dram */ - BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - /* nvcc_snvs_1p8 */ - LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_snvs_0p8 */ - LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdda_1p8 */ - LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - leds_gpio: gpio@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - switch: switch@5f { - compatible = "microchip,ksz9897"; - reg = <0x5f>; - pinctrl-0 = <&pinctrl_ksz>; - interrupt-parent = <&gpio4>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - phy-mode = "rgmii-id"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - lan1: port@0 { - reg = <0>; - label = "lan1"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - lan2: port@1 { - reg = <1>; - label = "lan2"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - lan3: port@2 { - reg = <2>; - label = "lan3"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - lan4: port@3 { - reg = <3>; - label = "lan4"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&fec1>; - phy-mode = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - - crypto@60 { - compatible = "atmel,atecc508a"; - reg = <0x60>; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - status = "okay"; -}; - -&pgc_gpu { - status = "disabled"; -}; - -&pgc_gpumix { - status = "disabled"; -}; - -&pgc_mipi { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; - rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; - cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>; - cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -/* SDIO WiFi */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wifi>; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */ - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */ - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */ - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */ - MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */ - MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */ - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */ - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */ - MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */ - >; - }; - - pinctrl_gsc: gscgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 - >; - }; - - pinctrl_ksz: kszgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41 - MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */ - >; - }; - - pinctrl_pcie0: pciegrp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */ - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 - >; - }; - - pinctrl_reg_isouart: regisouartgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 - >; - }; - - pinctrl_reg_ioexp: regioexpgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 - >; - }; - - pinctrl_reg_wl: regwlgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041 - >; - }; - - pinctrl_reg_usb2: regusb1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x41 - MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140 - MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x140 - >; - }; - - pinctrl_spi1: spi1grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140 - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140 - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140 - >; - }; - - pinctrl_uart1_gpio: uart1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */ - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */ - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140 - MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 - >; - }; - - pinctrl_uart3_gpio: uart3gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */ - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */ - MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */ - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 - MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140 - MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140 - >; - }; - - pinctrl_uart4_gpio: uart4gpiogrp { - fsl,pins = < - - MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */ - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */ - MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */ - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2-gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts deleted file mode 100644 index 11481e09c75..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw7902.dts +++ /dev/null @@ -1,1052 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2021 Gateworks Corporation - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/net/ti-dp83867.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -#include "imx8mm.dtsi" - -/ { - model = "Gateworks Venice GW7902 i.MX8MM board"; - compatible = "gw,imx8mm-gw7902", "fsl,imx8mm"; - - aliases { - ethernet1 = ð1; - usb0 = &usbotg1; - usb1 = &usbotg2; - }; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - can20m: can20m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <20000000>; - clock-output-names = "can20m"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-user-pb { - label = "user_pb"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = <BTN_0>; - }; - - key-user-pb1x { - label = "user_pb1x"; - linux,code = <BTN_1>; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key_erased"; - linux,code = <BTN_2>; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - key-eeprom-wp { - label = "eeprom_wp"; - linux,code = <BTN_3>; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - key-tamper { - label = "tamper"; - linux,code = <BTN_4>; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = <BTN_5>; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel1"; - gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel2"; - gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-2 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel3"; - gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-3 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel4"; - gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-4 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel5"; - gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb1_vbus: regulator-usb1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1>; - regulator-name = "usb_usb1_vbus"; - gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_wifi: regulator-wifi { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wl>; - regulator-name = "wifi"; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&can20m>; - interrupt-parent = <&gpio2>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - spi-max-frequency = <10000000>; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - local-mac-address = [00 00 00 00 00 00]; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; - }; -}; - -&gpio1 { - gpio-line-names = "", "", "", "", "", "", "", "", - "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = "", "", "", "", "", "", "", "", - "uart2_en#", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "", - "lte_pwr#", "lte_rst", "lte_int", "", - "amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485", - "", "uart1_term", "uart1_half", "app_gpio2", - "mipi_gpio1", "", "", ""; -}; - -&gpio5 { - gpio-line-names = "", "", "", "mipi_gpio4", - "mipi_gpio3", "mipi_gpio2", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - pinctrl-0 = <&pinctrl_gsc>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <1>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vin"; - gw,voltage-divider-ohms = <22100 1000>; - gw,voltage-offset-microvolt = <700000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vin_4p0"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_0p9"; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_soc"; - }; - - channel@8e { - gw,mode = <2>; - reg = <0x8e>; - label = "vdd_arm"; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_1p8"; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_dram"; - }; - - channel@98 { - gw,mode = <2>; - reg = <0x98>; - label = "vdd_1p0"; - }; - - channel@9a { - gw,mode = <2>; - reg = <0x9a>; - label = "vdd_2p5"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@9c { - gw,mode = <2>; - reg = <0x9c>; - label = "vdd_5p0"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - }; - - gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - /* vdd_soc: 0.805-0.900V (typ=0.8V) */ - BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - /* vdd_arm: 0.805-1.0V (typ=0.9V) */ - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ - BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_3p3 */ - BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_1p8 */ - BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_dram */ - BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - /* nvcc_snvs_1p8 */ - LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_snvs_0p8 */ - LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdda_1p8 */ - LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - accelerometer@19 { - compatible = "st,lis2de12"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio1>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -/* off-board header */ -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - status = "okay"; - - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - eth1: pcie@1,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - - local-mac-address = [00 00 00 00 00 00]; - }; - }; -}; - -/* off-board header */ -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -/* RS232/RS485/RS422 selectable */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; - rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; -}; - -/* RS232 console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* bluetooth HCI */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; - rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - }; -}; - -/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; - dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "host"; - vbus-supply = <®_usb1_vbus>; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -/* SDIO WiFi */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wifi>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ - MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ - MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */ - MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */ - MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */ - MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ - MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */ - MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */ - MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */ - MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ - MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ - MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */ - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */ - MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ - >; - }; - - pinctrl_gsc: gscgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 - MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 - MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 - MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 - MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 - >; - }; - - pinctrl_pcie0: pciegrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */ - >; - }; - - pinctrl_reg_wl: regwlgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */ - >; - }; - - pinctrl_reg_usb1: regusb1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - >; - }; - - pinctrl_spi1: spi1grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 - MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */ - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */ - MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */ - >; - }; - - pinctrl_uart1_gpio: uart1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */ - MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */ - MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3_gpio: uart3_gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */ - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */ - MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */ - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 - MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */ - MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */ - MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */ - MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */ - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */ - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */ - MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */ - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw7903.dts b/arch/arm/dts/imx8mm-venice-gw7903.dts deleted file mode 100644 index 1ec91c5c6a4..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw7903.dts +++ /dev/null @@ -1,869 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Gateworks Corporation - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -#include "imx8mm.dtsi" - -/ { - model = "Gateworks Venice GW7903 i.MX8MM board"; - compatible = "gw,imx8mm-gw7903", "fsl,imx8mm"; - - aliases { - ethernet0 = &fec1; - usb0 = &usbotg1; - }; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-user-pb { - label = "user_pb"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = <BTN_0>; - }; - - key-user-pb1x { - label = "user_pb1x"; - linux,code = <BTN_1>; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key_erased"; - linux,code = <BTN_2>; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - key-eeprom-wp { - label = "eeprom_wp"; - linux,code = <BTN_3>; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = <BTN_5>; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led01_red"; - gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led01_grn"; - gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-2 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led02_red"; - gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-3 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led02_grn"; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-4 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led03_red"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-5 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led03_grn"; - gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-6 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led04_red"; - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-7 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led04_grn"; - gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-8 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led05_red"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-9 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led05_grn"; - gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-a { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led06_red"; - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-b { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led06_grn"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - local-mac-address = [00 00 00 00 00 00]; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - rx-internal-delay-ps = <2000>; - tx-internal-delay-ps = <2500>; - }; - }; -}; - -&gpio1 { - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = "dig2_in", "dig2_out#", "dig2_ctl", "", "", "", "dig1_ctl", "", - "dig1_out#", "dig1_in", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio5 { - gpio-line-names = "", "", "", "", "", "", "", "sim1_det#", - "sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - pinctrl-0 = <&pinctrl_gsc>; - interrupt-parent = <&gpio4>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <1>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vin"; - gw,voltage-divider-ohms = <22100 1000>; - gw,voltage-offset-microvolt = <700000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vdd_5p0"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_0p9"; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_soc"; - }; - - channel@8e { - gw,mode = <2>; - reg = <0x8e>; - label = "vdd_arm"; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_1p8"; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_dram"; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - }; - - gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - /* vdd_soc: 0.805-0.900V (typ=0.8V) */ - BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - /* vdd_arm: 0.805-1.0V (typ=0.9V) */ - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ - BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_3p3 */ - BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_1p8 */ - BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_dram */ - BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - /* nvcc_snvs_1p8 */ - LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_snvs_0p8 */ - LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdda_1p8 */ - LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - status = "okay"; -}; - -&pgc_mipi { - status = "disabled"; -}; - -/* off-board RS232/RS485/RS422 */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */ - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */ - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */ - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */ - MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */ - MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40000041 /* DIG1_CTL */ - MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x40000041 /* DIG2_CTL */ - MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */ - MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */ - MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */ - MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x40000041 /* SIM2DET# */ - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000041 /* SIM2SEL */ - MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */ - MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */ - >; - }; - - pinctrl_gsc: gscgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 - MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19 - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19 - MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 - MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19 - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 - >; - }; - - pinctrl_pcie0: pciegrp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140 - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140 - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x140 - MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2-gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw7904.dts b/arch/arm/dts/imx8mm-venice-gw7904.dts deleted file mode 100644 index 93c9651c315..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw7904.dts +++ /dev/null @@ -1,928 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Gateworks Corporation - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -#include "imx8mm.dtsi" - -/ { - model = "Gateworks Venice GW7904 i.MX8MM board"; - compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-0 { - label = "user_pb"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = <BTN_0>; - }; - - key-1 { - label = "user_pb1x"; - linux,code = <BTN_1>; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-2 { - label = "key_erased"; - linux,code = <BTN_2>; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - key-3 { - label = "eeprom_wp"; - linux,code = <BTN_3>; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - key-4 { - label = "switch_hold"; - linux,code = <BTN_5>; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led01_grn"; - gpios = <&gpioled 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_YELLOW>; - label = "led01_yel"; - gpios = <&gpioled 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-2 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led02_grn"; - gpios = <&gpioled 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-3 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_YELLOW>; - label = "led02_yel"; - gpios = <&gpioled 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-4 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led03_grn"; - gpios = <&gpioled 4 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-5 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_YELLOW>; - label = "led03_yel"; - gpios = <&gpioled 5 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-6 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led04_grn"; - gpios = <&gpioled 6 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-7 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_YELLOW>; - label = "led04_yel"; - gpios = <&gpioled 7 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-8 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led05_grn"; - gpios = <&gpioled 8 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-9 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_YELLOW>; - label = "led05_yel"; - gpios = <&gpioled 9 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-10 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led06_grn"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-11 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led06_red"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-12 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led07_grn"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-13 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - label = "led07_red"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-14 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led08_grn"; - gpios = <&gpioled 10 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-15 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_YELLOW>; - label = "led08_yel"; - gpios = <&gpioled 11 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-16 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led09_grn"; - gpios = <&gpioled 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-17 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_YELLOW>; - label = "led09_yel"; - gpios = <&gpioled 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-18 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "led10_grn"; - gpios = <&gpioled 14 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-19 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_YELLOW>; - label = "led10_yel"; - gpios = <&gpioled 15 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - local-mac-address = [00 00 00 00 00 00]; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&gpio1 { - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "rs232_en#", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio5 { - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "pci_wdis#", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - pinctrl-0 = <&pinctrl_gsc>; - interrupt-parent = <&gpio4>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <1>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vin"; - gw,voltage-divider-ohms = <22100 1000>; - gw,voltage-offset-microvolt = <700000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vdd_5p0"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_0p9"; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_soc"; - }; - - channel@8e { - gw,mode = <2>; - reg = <0x8e>; - label = "vdd_arm"; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_1p8"; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_dram"; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - }; - - gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - /* vdd_soc: 0.805-0.900V (typ=0.8V) */ - BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - /* vdd_arm: 0.805-1.0V (typ=0.9V) */ - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ - BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_3p3 */ - BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_1p8 */ - BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_dram */ - BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - /* nvcc_snvs_1p8 */ - LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_snvs_0p8 */ - LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdda_1p8 */ - LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gpioled: gpio@27 { - compatible = "nxp,pca9555"; - reg = <0x27>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - status = "okay"; -}; - -&pgc_mipi { - status = "disabled"; -}; - -/* off-board RS232 */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* off-board RS232 */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */ - MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */ - MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000019 - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000019 - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000019 - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000019 - >; - }; - - pinctrl_gsc: gscgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 - >; - }; - - pinctrl_pcie0: pciegrp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2-gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw7905-0x.dts b/arch/arm/dts/imx8mm-venice-gw7905-0x.dts deleted file mode 100644 index 914753f062c..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw7905-0x.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mm.dtsi" -#include "imx8mm-venice-gw700x.dtsi" -#include "imx8mm-venice-gw7905.dtsi" - -/ { - model = "Gateworks Venice GW7905-0x i.MX8MM Development Kit"; - compatible = "gateworks,imx8mm-gw7905-0x", "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; -}; - -/* Disable SOM interfaces not used on baseboard */ -&fec1 { - status = "disabled"; -}; - -&usdhc1 { - status = "disabled"; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw7905.dtsi b/arch/arm/dts/imx8mm-venice-gw7905.dtsi deleted file mode 100644 index 9646eb9e492..00000000000 --- a/arch/arm/dts/imx8mm-venice-gw7905.dtsi +++ /dev/null @@ -1,303 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_usb2_vbus: regulator-usb2-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2_en>; - compatible = "regulator-fixed"; - regulator-name = "usb2_vbus"; - gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - compatible = "regulator-fixed"; - regulator-name = "SD2_3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpio1 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "gpioa", "gpiob", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "pci_usb_sel", - "", "", "", "pci_wdis#", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", - "gpioc", "gpiod", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; - pagesize = <32>; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* USB1 - Type C front panel SINK port J14 */ -&usbotg1 { - dr_mode = "peripheral"; - status = "okay"; -}; - -/* USB2 4-port USB3.0 HUB: - * P1 - USBC connector (host only) - * P2 - USB2 test connector - * P3 - miniPCIe full card - * P4 - miniPCIe half card - */ -&usbotg2 { - dr_mode = "host"; - vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000040 /* GPIOA */ - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x40000040 /* GPIOB */ - MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000106 /* PCI_USBSEL */ - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */ - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */ - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */ - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */ - MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x6 /* LEDR */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_pcie0: pciegrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x106 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106 - >; - }; - - pinctrl_reg_usb2_en: regusb2grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x6 /* USBHUB_RST# (ext p/u) */ - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-venice.dts b/arch/arm/dts/imx8mm-venice.dts deleted file mode 100644 index d0929908ce8..00000000000 --- a/arch/arm/dts/imx8mm-venice.dts +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2021 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mm.dtsi" - -/ { - model = "Gateworks Venice i.MX8MM board"; - compatible = "gw,imx8mm-venice", "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; - pagesize = <32>; - }; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1grp-gpio-grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mn-venice-gw7902.dts b/arch/arm/dts/imx8mn-venice-gw7902.dts deleted file mode 100644 index 97582db71ca..00000000000 --- a/arch/arm/dts/imx8mn-venice-gw7902.dts +++ /dev/null @@ -1,980 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2021 Gateworks Corporation - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/net/ti-dp83867.h> - -#include "imx8mn.dtsi" - -/ { - model = "Gateworks Venice GW7902 i.MX8MN board"; - compatible = "gw,imx8mn-gw7902", "fsl,imx8mn"; - - aliases { - usb0 = &usbotg1; - }; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - can20m: can20m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <20000000>; - clock-output-names = "can20m"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-user-pb { - label = "user_pb"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = <BTN_0>; - }; - - key-user-pb1x { - label = "user_pb1x"; - linux,code = <BTN_1>; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key_erased"; - linux,code = <BTN_2>; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - key-eeprom-wp { - label = "eeprom_wp"; - linux,code = <BTN_3>; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - key-tamper { - label = "tamper"; - linux,code = <BTN_4>; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = <BTN_5>; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel1"; - gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel2"; - gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-2 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel3"; - gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-3 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel4"; - gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led-4 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - label = "panel5"; - gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb1_vbus: regulator-usb1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1>; - regulator-name = "usb_usb1_vbus"; - gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_wifi: regulator-wifi { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wl>; - regulator-name = "wifi"; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&can20m>; - interrupt-parent = <&gpio2>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - spi-max-frequency = <10000000>; - }; -}; - -&disp_blk_ctrl { - status = "disabled"; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - local-mac-address = [00 00 00 00 00 00]; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; - }; -}; - -&gpio1 { - gpio-line-names = "", "", "", "", "", "", "", "", - "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = "", "", "", "", "", "", "", "", - "uart2_en#", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485", - "", "uart1_term", "uart1_half", "app_gpio2", - "mipi_gpio1", "", "", ""; -}; - -&gpio5 { - gpio-line-names = "", "", "", "mipi_gpio4", - "mipi_gpio3", "mipi_gpio2", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpu { - status = "disabled"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - pinctrl-0 = <&pinctrl_gsc>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <1>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vin"; - gw,voltage-divider-ohms = <22100 1000>; - gw,voltage-offset-microvolt = <700000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vin_4p0"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_0p9"; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_soc"; - }; - - channel@8e { - gw,mode = <2>; - reg = <0x8e>; - label = "vdd_arm"; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_1p8"; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_dram"; - }; - - channel@98 { - gw,mode = <2>; - reg = <0x98>; - label = "vdd_1p0"; - }; - - channel@9a { - gw,mode = <2>; - reg = <0x9a>; - label = "vdd_2p5"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@9c { - gw,mode = <2>; - reg = <0x9c>; - label = "vdd_5p0"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - }; - - gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - /* vdd_soc: 0.805-0.900V (typ=0.8V) */ - BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - /* vdd_arm: 0.805-1.0V (typ=0.9V) */ - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ - BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_3p3 */ - BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_1p8 */ - BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_dram */ - BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - /* nvcc_snvs_1p8 */ - LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdd_snvs_0p8 */ - LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* vdda_1p8 */ - LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - accelerometer@19 { - compatible = "st,lis2de12"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio1>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -/* off-board header */ -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&pgc_gpumix { - status = "disabled"; -}; - -/* off-board header */ -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MN_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -/* RS232/RS485/RS422 selectable */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; - status = "okay"; -}; - -/* RS232 console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* bluetooth HCI */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; - rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - }; -}; - -/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "host"; - vbus-supply = <®_usb1_vbus>; - disable-over-current; - status = "okay"; -}; - -/* SDIO WiFi */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wifi>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ - MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ - MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ - MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ - MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ - MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ - MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ - MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ - MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ - MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ - MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */ - MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */ - MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ - MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ - >; - }; - - pinctrl_gsc: gscgrp { - fsl,pins = < - MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 - MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 - MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 - MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 - MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 - MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 - MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 - MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */ - >; - }; - - pinctrl_reg_wl: regwlgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */ - >; - }; - - pinctrl_reg_usb1: regusb1grp { - fsl,pins = < - MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - >; - }; - - pinctrl_spi1: spi1grp { - fsl,pins = < - MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 - MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 - MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */ - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart1_gpio: uart1gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */ - MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */ - MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3_gpio: uart3_gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */ - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */ - MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */ - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 - MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mn-venice.dts b/arch/arm/dts/imx8mn-venice.dts deleted file mode 100644 index 9e31b37f249..00000000000 --- a/arch/arm/dts/imx8mn-venice.dts +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2022 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mn.dtsi" - -/ { - model = "Gateworks Venice i.MX8MM board"; - compatible = "gw,imx8mn-venice", "fsl,imx8mn"; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; - pagesize = <32>; - }; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1grp-gpio-grp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw702x.dtsi b/arch/arm/dts/imx8mp-venice-gw702x.dtsi deleted file mode 100644 index 560c68e4da6..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw702x.dtsi +++ /dev/null @@ -1,587 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/net/ti-dp83867.h> - -/ { - aliases { - ethernet0 = &eqos; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-user-pb { - label = "user_pb"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = <BTN_0>; - }; - - key-user-pb1x { - label = "user_pb1x"; - linux,code = <BTN_1>; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-erased { - label = "key_erased"; - linux,code = <BTN_2>; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - key-eeprom-wp { - label = "eeprom_wp"; - linux,code = <BTN_3>; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - key-tamper { - label = "tamper"; - linux,code = <BTN_4>; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - switch-hold { - label = "switch_hold"; - linux,code = <BTN_5>; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; -}; - -&A53_0 { - cpu-supply = <&buck3_reg>; -}; - -&A53_1 { - cpu-supply = <&buck3_reg>; -}; - -&A53_2 { - cpu-supply = <&buck3_reg>; -}; - -&A53_3 { - cpu-supply = <&buck3_reg>; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - pinctrl-0 = <&pinctrl_ethphy0>; - pinctrl-names = "default"; - reg = <0x0>; - interrupt-parent = <&gpio3>; - interrupts = <16 IRQ_TYPE_EDGE_FALLING>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - pinctrl-0 = <&pinctrl_gsc>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@8 { - gw,mode = <3>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@16 { - gw,mode = <4>; - reg = <0x16>; - label = "fan_tach"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vdd_vin"; - gw,voltage-divider-ohms = <22100 1000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vdd_adc1"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_adc2"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_1p0"; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_1p8"; - }; - - channel@8e { - gw,mode = <2>; - reg = <0x8e>; - label = "vdd_2p5"; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_dram"; - }; - - channel@98 { - gw,mode = <2>; - reg = <0x98>; - label = "vdd_soc"; - }; - - channel@9a { - gw,mode = <2>; - reg = <0x9a>; - label = "vdd_arm"; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - - fan-controller@0 { - compatible = "gw,gsc-fan"; - reg = <0x0a>; - }; - }; - - gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; - - pmic@69 { - compatible = "mps,mp5416"; - reg = <0x69>; - - regulators { - /* vdd_soc */ - buck1 { - regulator-name = "buck1"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* vdd_dram */ - buck2 { - regulator-name = "buck2"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - /* vdd_arm */ - buck3_reg: buck3 { - regulator-name = "buck3"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* vdd_1p8 */ - buck4 { - regulator-name = "buck4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - /* OUT2: nvcc_snvs_1p8 */ - ldo1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - /* OUT3: vdd_1p0 */ - ldo2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* OUT4: vdd_2p5 */ - ldo3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - regulator-boot-on; - }; - - /* OUT5: vdd_3p3 */ - ldo4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -/* off-board header */ -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; - pagesize = <32>; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -/* off-board header */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* off-board header */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* off-board */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - non-removable; - status = "okay"; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 - >; - }; - - pinctrl_ethphy0: ethphy0grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x140 /* RST# */ - MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x150 /* IRQ# */ - >; - }; - - pinctrl_gsc: gscgrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x150 /* IRQ# */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw71xx-2x.dts b/arch/arm/dts/imx8mp-venice-gw71xx-2x.dts deleted file mode 100644 index 53120fc9cd7..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw71xx-2x.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mp.dtsi" -#include "imx8mp-venice-gw702x.dtsi" -#include "imx8mp-venice-gw71xx.dtsi" - -/ { - model = "Gateworks Venice GW71xx-2x i.MX8MP Development Kit"; - compatible = "gateworks,imx8mp-gw71xx-2x", "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw71xx.dtsi b/arch/arm/dts/imx8mp-venice-gw71xx.dtsi deleted file mode 100644 index 86999f52d4b..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw71xx.dtsi +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "dio1", "", "", "dio0", - "", "", "pci_usb_sel", "", - "", "", "", "", - "", "", "", "", - "dio3", "", "dio2", "", - "pci_wdis#", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio4>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* off-board header */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* USB1 Type-C front panel */ -&usb3_0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - fsl,over-current-active-low; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb_dwc3_0 { - /* dual role is implemented but not a full featured OTG */ - adp-disable; - hnp-disable; - srp-disable; - dr_mode = "otg"; - usb-role-switch; - role-switch-default-mode = "peripheral"; - status = "okay"; - - connector { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbcon1>; - compatible = "gpio-usb-b-connector", "usb-b-connector"; - type = "micro"; - label = "Type-C"; - id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - }; -}; - -/* USB2 - MiniPCIe socket */ -&usb3_1 { - fsl,permanently-attached; - fsl,disable-port-power-control; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ - MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ - MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ - MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000146 /* DIO2 */ - MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x40000146 /* DIO3 */ - MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ - MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 - >; - }; - - pinctrl_usb1: usb1grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ - >; - }; - - pinctrl_usbcon1: usbcon1grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw72xx-2x.dts b/arch/arm/dts/imx8mp-venice-gw72xx-2x.dts deleted file mode 100644 index 255e36f66b0..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw72xx-2x.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mp.dtsi" -#include "imx8mp-venice-gw702x.dtsi" -#include "imx8mp-venice-gw72xx.dtsi" - -/ { - model = "Gateworks Venice GW72xx-2x i.MX8MP Development Kit"; - compatible = "gateworks,imx8mp-gw72xx-2x", "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw72xx.dtsi b/arch/arm/dts/imx8mp-venice-gw72xx.dtsi deleted file mode 100644 index 4e726128ccf..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw72xx.dtsi +++ /dev/null @@ -1,378 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_usb1_vbus: regulator-usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_en>; - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb2_vbus: regulator-usb2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2_en>; - compatible = "regulator-fixed"; - regulator-name = "usb2_vbus"; - gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_vmmc>; - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3_SD"; - enable-active-high; - gpio = <&gpio2 19 0>; /* SD2_RESET */ - off-on-delay-us = <12000>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - startup-delay-us = <100>; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, - <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; - tpm@1 { - compatible = "tcg,tpm_tis-spi"; - reg = <0x1>; - spi-max-frequency = <36000000>; - }; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "dio1", "", "", "dio0", - "", "", "pci_usb_sel", "", - "", "", "", "", - "", "", "rs485_en", "rs485_term", - "", "", "", "rs485_half", - "pci_wdis#", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio4>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* off-board header */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* RS232 */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -/* USB1 - OTG */ -&usb3_0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - fsl,over-current-active-low; - status = "okay"; -}; - -&usb3_phy0 { - vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usb_dwc3_0 { - /* dual role is implemented but not a full featured OTG */ - adp-disable; - hnp-disable; - srp-disable; - dr_mode = "otg"; - usb-role-switch; - role-switch-default-mode = "peripheral"; - status = "okay"; - - connector { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbcon1>; - compatible = "gpio-usb-b-connector", "usb-b-connector"; - type = "micro"; - label = "otg"; - id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - }; -}; - -/* USB2 - USB3.0 Hub */ -&usb3_1 { - fsl,permanently-attached; - fsl,disable-port-power-control; - status = "okay"; -}; - -&usb3_phy1 { - vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ - MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ - MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ - MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ - MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ - MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ - MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 - >; - }; - - pinctrl_reg_usb1_en: regusb1grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */ - >; - }; - - pinctrl_usb1: usb1grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ - >; - }; - - pinctrl_usbcon1: usbcon1grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ - >; - }; - - pinctrl_reg_usb2_en: regusb2grp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 - MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 - MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw73xx-2x.dts b/arch/arm/dts/imx8mp-venice-gw73xx-2x.dts deleted file mode 100644 index 000fd15e0c0..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw73xx-2x.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mp.dtsi" -#include "imx8mp-venice-gw702x.dtsi" -#include "imx8mp-venice-gw73xx.dtsi" - -/ { - model = "Gateworks Venice GW73xx-2x i.MX8MP Development Kit"; - compatible = "gateworks,imx8mp-gw73xx-2x", "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw73xx.dtsi b/arch/arm/dts/imx8mp-venice-gw73xx.dtsi deleted file mode 100644 index 88c3c006fa2..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw73xx.dtsi +++ /dev/null @@ -1,421 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_usb1_vbus: regulator-usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_en>; - compatible = "regulator-fixed"; - regulator-name = "usb1_vbus"; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb2_vbus: regulator-usb2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2_en>; - compatible = "regulator-fixed"; - regulator-name = "usb2_vbus"; - gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_wifi_en: regulator-wifi-en { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wl>; - compatible = "regulator-fixed"; - regulator-name = "wl"; - gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100>; - enable-active-high; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_vmmc>; - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3_SD"; - enable-active-high; - gpio = <&gpio2 19 0>; /* SD2_RESET */ - off-on-delay-us = <12000>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - startup-delay-us = <100>; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, - <&gpio1 10 GPIO_ACTIVE_LOW>; - status = "okay"; - tpm@1 { - compatible = "tcg,tpm_tis-spi"; - reg = <0x1>; - spi-max-frequency = <36000000>; - }; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "dio1", "", "", "dio0", - "", "", "pci_usb_sel", "", - "", "", "", "", - "", "", "rs485_en", "rs485_term", - "", "", "", "rs485_half", - "pci_wdis#", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - accelerometer@19 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - compatible = "st,lis2de12"; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio4>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* bluetooth HCI */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>; - cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - shutdown-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; - }; -}; - -/* RS232 */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -/* USB1 - OTG */ -&usb3_0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - fsl,over-current-active-low; - status = "okay"; -}; - -&usb3_phy0 { - vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usb_dwc3_0 { - /* dual role is implemented but not a full featured OTG */ - adp-disable; - hnp-disable; - srp-disable; - dr_mode = "otg"; - usb-role-switch; - role-switch-default-mode = "peripheral"; - status = "okay"; - - connector { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbcon1>; - compatible = "gpio-usb-b-connector", "usb-b-connector"; - type = "micro"; - label = "otg"; - id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - }; -}; - -/* USB2 - USB3.0 Hub */ -&usb3_1 { - fsl,permanently-attached; - fsl,disable-port-power-control; - status = "okay"; -}; - -&usb3_phy1 { - vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -/* SDIO WiFi */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wifi_en>; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ - MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ - MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ - MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ - MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ - MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ - >; - }; - - pinctrl_bten: btengrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x146 - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ - MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 - >; - }; - - pinctrl_reg_wl: regwlgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x146 - >; - }; - - pinctrl_reg_usb1_en: regusb1grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */ - >; - }; - - pinctrl_usb1: usb1grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ - >; - }; - - pinctrl_usbcon1: usbcon1grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ - >; - }; - - pinctrl_reg_usb2_en: regusb2grp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 - MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 - MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140 - MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 - MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw74xx.dts b/arch/arm/dts/imx8mp-venice-gw74xx.dts deleted file mode 100644 index 7eb28531573..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw74xx.dts +++ /dev/null @@ -1,1125 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2021 Gateworks Corporation - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -#include "imx8mp.dtsi" - -/ { - model = "Gateworks Venice GW74xx i.MX8MP board"; - compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp"; - - aliases { - ethernet0 = &eqos; - ethernet1 = &fec; - ethernet2 = &lan1; - ethernet3 = &lan2; - ethernet4 = &lan3; - ethernet5 = &lan4; - ethernet6 = &lan5; - }; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-0 { - label = "user_pb"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = <BTN_0>; - }; - - key-1 { - label = "user_pb1x"; - linux,code = <BTN_1>; - interrupt-parent = <&gsc>; - interrupts = <0>; - }; - - key-2 { - label = "key_erased"; - linux,code = <BTN_2>; - interrupt-parent = <&gsc>; - interrupts = <1>; - }; - - key-3 { - label = "eeprom_wp"; - linux,code = <BTN_3>; - interrupt-parent = <&gsc>; - interrupts = <2>; - }; - - key-4 { - label = "tamper"; - linux,code = <BTN_4>; - interrupt-parent = <&gsc>; - interrupts = <5>; - }; - - key-5 { - label = "switch_hold"; - linux,code = <BTN_5>; - interrupt-parent = <&gsc>; - interrupts = <7>; - }; - }; - - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_HEARTBEAT; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - reg_usb2_vbus: regulator-usb2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2>; - compatible = "regulator-fixed"; - regulator-name = "usb_usb2_vbus"; - gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_can1>; - regulator-name = "can1_stby"; - gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_can2>; - regulator-name = "can2_stby"; - gpio = <&gpio5 5 GPIO_ACTIVE_LOW>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_wifi_en: regulator-wifi-en { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wifi>; - compatible = "regulator-fixed"; - regulator-name = "wl"; - gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&A53_0 { - cpu-supply = <®_arm>; -}; - -&A53_1 { - cpu-supply = <®_arm>; -}; - -&A53_2 { - cpu-supply = <®_arm>; -}; - -&A53_3 { - cpu-supply = <®_arm>; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - tpm@0 { - compatible = "tcg,tpm_tis-spi"; - #address-cells = <0x1>; - #size-cells = <0x1>; - reg = <0x0>; - spi-max-frequency = <36000000>; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - local-mac-address = [00 00 00 00 00 00]; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; - status = "okay"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_stby>; - status = "okay"; -}; - -&gpio1 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "dio0", "", "dio1", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - "", "", "", "", "", "", "m2_pin20", "", - "", "", "", "", "", "pcie1_wdis#", "pcie3_wdis#", "", - "", "", "pcie2_wdis#", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "m2_rst", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "", "m2_off#", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "m2_wdis#", "", "", "", "", "", - "", "", "", "", "", "", "", "rs485_en"; -}; - -&gpio5 { - gpio-line-names = - "rs485_hd", "rs485_term", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - pinctrl-0 = <&pinctrl_gsc>; - interrupt-parent = <&gpio4>; - interrupts = <20 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - adc { - compatible = "gw,gsc-adc"; - #address-cells = <1>; - #size-cells = <0>; - - channel@6 { - gw,mode = <0>; - reg = <0x06>; - label = "temp"; - }; - - channel@8 { - gw,mode = <1>; - reg = <0x08>; - label = "vdd_bat"; - }; - - channel@16 { - gw,mode = <4>; - reg = <0x16>; - label = "fan_tach"; - }; - - channel@82 { - gw,mode = <2>; - reg = <0x82>; - label = "vdd_adc1"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@84 { - gw,mode = <2>; - reg = <0x84>; - label = "vdd_adc2"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@86 { - gw,mode = <2>; - reg = <0x86>; - label = "vdd_vin"; - gw,voltage-divider-ohms = <22100 1000>; - }; - - channel@88 { - gw,mode = <2>; - reg = <0x88>; - label = "vdd_3p3"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@8c { - gw,mode = <2>; - reg = <0x8c>; - label = "vdd_2p5"; - gw,voltage-divider-ohms = <10000 10000>; - }; - - channel@90 { - gw,mode = <2>; - reg = <0x90>; - label = "vdd_soc"; - }; - - channel@92 { - gw,mode = <2>; - reg = <0x92>; - label = "vdd_arm"; - }; - - channel@98 { - gw,mode = <2>; - reg = <0x98>; - label = "vdd_1p8"; - }; - - channel@9a { - gw,mode = <2>; - reg = <0x9a>; - label = "vdd_1p2"; - }; - - channel@9c { - gw,mode = <2>; - reg = <0x9c>; - label = "vdd_dram"; - }; - - channel@a2 { - gw,mode = <2>; - reg = <0xa2>; - label = "vdd_gsc"; - gw,voltage-divider-ohms = <10000 10000>; - }; - }; - - fan-controller@a { - compatible = "gw,gsc-fan"; - reg = <0x0a>; - }; - }; - - gpio: gpio@23 { - compatible = "nxp,pca9555"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gsc>; - interrupts = <4>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; - - eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - pagesize = <16>; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; - - rtc@68 { - compatible = "dallas,ds1672"; - reg = <0x68>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - accelerometer@19 { - compatible = "st,lis2de12"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - reg = <0x19>; - st,drdy-int-pin = <1>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; - }; - - switch: switch@5f { - compatible = "microchip,ksz9897"; - reg = <0x5f>; - pinctrl-0 = <&pinctrl_ksz>; - interrupt-parent = <&gpio4>; - interrupts = <29 IRQ_TYPE_EDGE_FALLING>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - lan1: port@0 { - reg = <0>; - label = "lan1"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - lan2: port@1 { - reg = <1>; - label = "lan2"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - lan3: port@2 { - reg = <2>; - label = "lan3"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - lan4: port@3 { - reg = <3>; - label = "lan4"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - lan5: port@4 { - reg = <4>; - label = "lan5"; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&fec>; - phy-mode = "rgmii-id"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pmic@25 { - compatible = "nxp,pca9450c"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio3>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - regulators { - BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - reg_arm: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1025000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - BUCK4 { - regulator-name = "BUCK4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3600000>; - regulator-boot-on; - regulator-always-on; - }; - - BUCK5 { - regulator-name = "BUCK5"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - regulator-boot-on; - regulator-always-on; - }; - - BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <1045000>; - regulator-max-microvolt = <1155000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <1890000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -/* off-board header */ -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, - <&clk IMX8MP_CLK_PCIE_ROOT>, - <&clk IMX8MP_CLK_HSIO_AXI>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; - assigned-clock-rates = <10000000>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; - status = "okay"; -}; - -/* GPS / off-board header */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* RS232 console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* bluetooth HCI */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; - cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -/* USB1 - Type C front panel */ -&usb3_0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - fsl,over-current-active-low; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb_dwc3_0 { - /* dual role is implemented but not a full featured OTG */ - adp-disable; - hnp-disable; - srp-disable; - dr_mode = "otg"; - usb-role-switch; - role-switch-default-mode = "peripheral"; - status = "okay"; - - connector { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbcon1>; - compatible = "gpio-usb-b-connector", "usb-b-connector"; - type = "micro"; - label = "Type-C"; - id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; -}; - -/* USB2 - USB3.0 Hub */ -&usb3_phy1 { - vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -&usb3_1 { - fsl,permanently-attached; - fsl,disable-port-power-control; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -/* SDIO WiFi */ -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <4>; - non-removable; - vmmc-supply = <®_wifi_en>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - wifi@0 { - compatible = "cypress,cyw4373-fmac"; - reg = <0>; - }; -}; - -/* eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */ - MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */ - MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40000040 /* M2SKT_OFF# */ - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */ - MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40000040 /* M2SKT_PIN20 */ - MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000040 /* M2SKT_PIN22 */ - MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x40000150 /* PCIE1_WDIS# */ - MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ - MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ - MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ - MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ - MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ - MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ - >; - }; - - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150 - >; - }; - - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 - MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */ - MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */ - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 - MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140 - MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 - MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 - MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 - >; - }; - - pinctrl_gsc: gscgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 - >; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3 - MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3 - MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 - MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 - >; - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3 - MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3 - >; - }; - - pinctrl_ksz: kszgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */ - MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */ - >; - }; - - pinctrl_gpio_leds: ledgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10 - MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10 - >; - }; - - pinctrl_pcie0: pciegrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x106 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 - >; - }; - - pinctrl_reg_can1: regcan1grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154 - >; - }; - - pinctrl_reg_can2: regcan2grp { - fsl,pins = < - MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 - >; - }; - - pinctrl_reg_usb2: regusb2grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140 - >; - }; - - pinctrl_reg_wifi: regwifigrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110 - >; - }; - - pinctrl_spi1: spi1grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 - MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 - MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 - MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 - MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 - MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140 - >; - }; - - pinctrl_uart3_gpio: uart3gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 - MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 - >; - }; - - pinctrl_usb1: usb1grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 - >; - }; - - pinctrl_usbcon1: usb1congrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw7905-2x.dts b/arch/arm/dts/imx8mp-venice-gw7905-2x.dts deleted file mode 100644 index 4a1bbbbe19e..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw7905-2x.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mp.dtsi" -#include "imx8mp-venice-gw702x.dtsi" -#include "imx8mp-venice-gw7905.dtsi" - -/ { - model = "Gateworks Venice GW7905-2x i.MX8MP Development Kit"; - compatible = "gateworks,imx8mp-gw7905-2x", "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; -}; - -/* Disable SOM interfaces not used on baseboard */ -&eqos { - status = "disabled"; -}; - -&usdhc1 { - status = "disabled"; -}; diff --git a/arch/arm/dts/imx8mp-venice-gw7905.dtsi b/arch/arm/dts/imx8mp-venice-gw7905.dtsi deleted file mode 100644 index 0d40cb0f05f..00000000000 --- a/arch/arm/dts/imx8mp-venice-gw7905.dtsi +++ /dev/null @@ -1,309 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Gateworks Corporation - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - led-controller { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - reg_usb2_vbus: regulator-usb2-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2_en>; - compatible = "regulator-fixed"; - regulator-name = "usb2_vbus"; - gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - compatible = "regulator-fixed"; - regulator-name = "SD2_3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -/* off-board header */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "gpioa", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpio4 { - gpio-line-names = - "", "gpiod", "", "", - "gpiob", "gpioc", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "pci_usb_sel", "", - "pci_wdis#", "", "", ""; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; - pagesize = <32>; - }; -}; - -/* off-board header */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* GPS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* USB1 - Type C front panel SINK port J14 */ -&usb3_0 { - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "peripheral"; - status = "okay"; -}; - -/* USB2 4-port USB3.0 HUB: - * P1 - USBC connector (host only) - * P2 - USB2 test connector - * P3 - miniPCIe full card - * P4 - miniPCIe half card - */ -&usb3_phy1 { - vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -&usb3_1 { - fsl,permanently-attached; - fsl,disable-port-power-control; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -/* microSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40000040 /* GPIOA */ - MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000040 /* GPIOD */ - MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x40000040 /* GPIOB */ - MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */ - MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */ - MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */ - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */ - MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6 /* LEDR */ - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_pcie0: pciegrp { - fsl,pins = < - MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 - >; - }; - - pinctrl_pps: ppsgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106 - >; - }; - - pinctrl_reg_usb2_en: regusb2grp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x6 /* USBHUB_RST# (ext p/u) */ - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 - >; - }; - - pinctrl_spi2: spi2grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-venice.dts b/arch/arm/dts/imx8mp-venice.dts deleted file mode 100644 index 372db26cc09..00000000000 --- a/arch/arm/dts/imx8mp-venice.dts +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Gateworks Corporation - */ - -/dts-v1/; - -#include "imx8mp.dtsi" - -/ { - model = "Gateworks Venice i.MX8MP board"; - compatible = "gateworks,imx8mp-venice", "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; - status = "okay"; - - gsc: gsc@20 { - compatible = "gw,gsc"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - }; - - eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - pagesize = <16>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom@52 { - compatible = "atmel,24c32"; - reg = <0x52>; - pagesize = <32>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c1_gpio: i2c1grp-gpio-grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c3 - MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 - >; - }; -}; diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi index 8bf28c2de87..6897c91f4d9 100644 --- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi +++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi @@ -121,6 +121,21 @@ bootph-some-ram; }; +/* + * Remove once USB support is added to imx93-phyboard-segin.dts upstream. + */ +&usbotg1 { + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + &usdhc1 { bootph-pre-ram; bootph-some-ram; diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts index 6b03e7405af..2b333e70f5c 100644 --- a/arch/arm/dts/k3-am625-verdin-r5.dts +++ b/arch/arm/dts/k3-am625-verdin-r5.dts @@ -23,7 +23,7 @@ */ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 20>; assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 22>; - assigned-clock-rates = <200000000>, <1000000000>, <25000000>; + assigned-clock-rates = <200000000>, <800000000>, <25000000>; clocks = <&k3_clks 61 0>; power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 60ca6d21abb..c9fee0ea99b 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -195,6 +195,10 @@ &ospi0 { bootph-all; + + flash@0 { + bootph-all; + }; }; &serdes_ln_ctrl { diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index 018faaa13b6..fb7e2e50239 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -52,7 +52,7 @@ }; &mcu_timer0 { - clock-frequency = <25000000>; + clock-frequency = <250000000>; bootph-pre-ram; }; @@ -83,3 +83,16 @@ &wkup_vtm0 { bootph-pre-ram; }; + +&ospi0 { + reg = <0x0 0x47040000 0x0 0x100>, + <0x0 0x50000000 0x0 0x8000000>; +}; + +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; diff --git a/arch/arm/dts/meson-gxbb-wetek-u-boot.dtsi b/arch/arm/dts/meson-gxbb-wetek-hub-u-boot.dtsi index 3743053eb9c..3743053eb9c 100644 --- a/arch/arm/dts/meson-gxbb-wetek-u-boot.dtsi +++ b/arch/arm/dts/meson-gxbb-wetek-hub-u-boot.dtsi diff --git a/arch/arm/dts/meson-gxbb-wetek-play2-u-boot.dtsi b/arch/arm/dts/meson-gxbb-wetek-play2-u-boot.dtsi new file mode 100644 index 00000000000..3743053eb9c --- /dev/null +++ b/arch/arm/dts/meson-gxbb-wetek-play2-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include "meson-gx-u-boot.dtsi" + +ðmac { + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; +}; diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi index 746a5ba347e..a17c58cbfcd 100644 --- a/arch/arm/dts/sama7g5.dtsi +++ b/arch/arm/dts/sama7g5.dtsi @@ -871,6 +871,30 @@ }; }; + flx10: flexcom@e2820000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe2820000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe2820000 0x800>; + status = "disabled"; + + i2c10: i2c@600 { + compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; + atmel,fifo-size = <32>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>, + <&dma0 AT91_XDMAC_DT_PERID(25)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + flx11: flexcom@e2824000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe2824000 0x200>; diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi new file mode 100644 index 00000000000..a8167e5c14a --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ + +#include "socfpga_soc64_fit-u-boot.dtsi" + +/{ + memory { + #address-cells = <2>; + #size-cells = <2>; + bootph-all; + }; +}; + +&clkmgr { + bootph-all; +}; + +&i2c0 { + reset-names = "i2c"; +}; + +&i2c1 { + reset-names = "i2c"; +}; + +&i2c2 { + reset-names = "i2c"; +}; + +&i2c3 { + reset-names = "i2c"; +}; + +&mmc { + resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&qspi { + bootph-all; +}; + +&rst { + compatible = "altr,rst-mgr"; + altr,modrst-offset = <0x24>; + bootph-all; +}; + +&sysmgr { + compatible = "altr,sys-mgr", "syscon"; + bootph-all; +}; + +&uart0 { + bootph-all; +}; + +&watchdog0 { + bootph-all; +}; diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi new file mode 100644 index 00000000000..03b55040497 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5.dtsi @@ -0,0 +1,575 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ + +/dts-v1/; +#include <dt-bindings/reset/altr,rst-mgr-agx5.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/agilex5-clock.h> + +/ { + compatible = "intel,socfpga-agilex"; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + service_reserved: svcbuffer@0 { + compatible = "shared-dma-pool"; + reg = <0x0 0x0 0x0 0x1000000>; + alignment = <0x1000>; + no-map; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x1>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a76"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a76"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x3>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 170 4>, + <0 171 4>, + <0 172 4>, + <0 173 4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + interrupt-parent = <&intc>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + intc: intc@fffc1000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1d000000 0x0 0x10000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges = <0 0 0 0xffffffff>; + + base_fpga_region { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr>; + }; + + clkmgr: clock-controller@10d10000 { + compatible = "intel,agilex5-clkmgr"; + reg = <0x10d10000 0x1000>; + #clock-cells = <1>; + }; + + clocks { + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + cb_intosc_ls_clk: cb-intosc-ls-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_free_clk: f2s-free-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + qspi_clk: qspi-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + gmac0: ethernet@10810000 { + compatible = "intel,socfpga-dwxgmac", "snps,dwxgmac-2.10", "snps,dwxgmac"; + reg = <0x10810000 0x3500>; + interrupts = <0 190 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + iommus = <&smmu 1>; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; + clocks = <&clkmgr AGILEX5_EMAC0_CLK>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + gmac1: ethernet@10820000 { + compatible = "intel,socfpga-dwxgmac", "snps,dwxgmac-2.10", "snps,dwxgmac"; + reg = <0x10820000 0x3500>; + interrupts = <0 207 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + iommus = <&smmu 2>; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + clocks = <&clkmgr AGILEX5_EMAC1_CLK>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + gmac2: ethernet@10830000 { + compatible = "intel,socfpga-dwxgmac", "snps,dwxgmac-2.10", "snps,dwxgmac"; + reg = <0x10830000 0x3500>; + interrupts = <0 224 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + iommus = <&smmu 3>; + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + clocks = <&clkmgr AGILEX5_EMAC2_CLK>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + gpio0: gpio@10c03200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x10c03200 0x80>; + resets = <&rst GPIO0_RESET>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 110 4>; + }; + }; + + gpio1: gpio@10c03300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x10c03300 0x80>; + resets = <&rst GPIO1_RESET>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 111 4>; + }; + }; + + i2c0: i2c@10c02800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02800 0x100>; + interrupts = <0 103 4>; + resets = <&rst I2C0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c1: i2c@10c02900 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02900 0x100>; + interrupts = <0 104 4>; + resets = <&rst I2C1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c2: i2c@10c02a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02a00 0x100>; + interrupts = <0 105 4>; + resets = <&rst I2C2_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c3: i2c@10c02b00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02b00 0x100>; + interrupts = <0 106 4>; + resets = <&rst I2C3_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c4: i2c@10c02c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x10c02c00 0x100>; + interrupts = <0 107 4>; + resets = <&rst I2C4_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i3c0: i3c@10da0000 { + compatible = "snps,dw-i3c-master-1.00a"; + reg = <0x10da0000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 164 4>; + resets = <&rst I3C0_RESET>; + max_devices = <11>; + clocks = <&clkmgr AGILEX5_L4_MP_CLK>; + status = "disabled"; + }; + + i3c1: i3c@10da1000 { + compatible = "snps,dw-i3c-master-1.00a"; + reg = <0x10da1000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 165 4>; + resets = <&rst I3C1_RESET>; + clocks = <&clkmgr AGILEX5_L4_MP_CLK>; + max_devices = <11>; + status = "disabled"; + }; + + combophy0: combophy@0 { + #phy-cells = <0>; + phy-type = <1>; + compatible = "cdns,combophy"; + reg = <0x10808000 0x1000>; + resets = <&rst COMBOPHY_RESET>; + reset-names = "reset"; + status = "disabled"; + }; + + mmc: mmc0@10808000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cdns,sd4hc"; + reg = <0x10808000 0x1000>; + interrupts = <0 96 4>; + phys = <&combophy0>; + phy-names = "combo-phy"; + clocks = <&clkmgr AGILEX5_L4_MP_CLK>, + <&clkmgr AGILEX5_SDMMC_CLK>; + clock-names = "biu", "ciu"; + fifo-depth = <0x800>; + resets = <&rst SDMMC_RESET>; + reset-names = "reset"; + iommus = <&smmu 5>; + status = "disabled"; + }; + + ocram: sram@00000000 { + compatible = "mmio-sram"; + reg = <0x00000000 0x200000>; + }; + + rst: rstmgr@10d11000 { + #reset-cells = <1>; + compatible = "altr,stratix10-rst-mgr"; + reg = <0x10d11000 0x1000>; + }; + + smmu: iommu@16000000 { + compatible = "arm,mmu-500", "arm,smmu-v2"; + reg = <0x16000000 0x40000>; + #global-interrupts = <2>; + #iommu-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <0 128 4>, /* Global Secure Fault */ + <0 129 4>, /* Global Non-secure Fault */ + /* Non-secure Context Interrupts (32) */ + <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, + <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, + <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, + <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, + <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, + <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, + <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, + <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; + stream-match-mask = <0x7ff0>; + status = "disabled"; + }; + + spi0: spi@10da4000 { + compatible = "intel,agilex-spi", + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10da4000 0x1000>; + interrupts = <0 99 4>; + resets = <&rst SPIM0_RESET>; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; + status = "disabled"; + }; + + spi1: spi@10da5000 { + compatible = "intel,agilex-spi", + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10da5000 0x1000>; + interrupts = <0 100 4>; + resets = <&rst SPIM1_RESET>; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; + status = "disabled"; + }; + + sysmgr: sysmgr@10d12000 { + compatible = "altr,sys-mgr-s10","altr,sys-mgr"; + reg = <0x10d12000 0x500>; + }; + + /* Local timer */ + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + timer0: timer0@10c03000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 113 4>; + reg = <0x10c03000 0x100>; + resets = <&rst SPTIMER0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + status = "disabled"; + }; + + timer1: timer1@10c03100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 114 4>; + reg = <0x10c03100 0x100>; + resets = <&rst SPTIMER1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + status = "disabled"; + }; + + timer2: timer2@10d00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 115 4>; + reg = <0x10d00000 0x100>; + resets = <&rst L4SYSTIMER0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + clock-names = "timer"; + status = "disabled"; + }; + + timer3: timer3@10d00100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 116 4>; + reg = <0x10d00100 0x100>; + resets = <&rst L4SYSTIMER1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + clock-names = "timer"; + status = "disabled"; + }; + + uart0: serial0@10c02000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10c02000 0x100>; + interrupts = <0 108 4>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART0_RESET>; + status = "disabled"; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-frequency = <100000000>; + }; + + uart1: serial1@10c02100 { + compatible = "snps,dw-apb-uart"; + reg = <0x10c02100 0x100>; + interrupts = <0 109 4>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&clkmgr AGILEX5_USB_CLK>; + status = "disabled"; + }; + + usb0: usb@10b00000 { + compatible = "snps,dwc2"; + reg = <0x10b00000 0x40000>; + interrupts = <0 93 4>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; + reset-names = "dwc2", "dwc2-ecc"; + clocks = <&clkmgr AGILEX5_USB_CLK>; + iommus = <&smmu 6>; + status = "disabled"; + }; + + usb31: usb31@11000000 { + compatible = "snps,dwc3"; + reg = <0x11000000 0x100000>; + resets = <&rst USB1_RESET>; + phys = <&usbphy0>, <&usbphy0>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + maximum-speed = "super-speed"; + snps,dis_u2_susphy_quirk; + status = "disabled"; + }; + + watchdog0: watchdog@10d00200 { + compatible = "snps,dw-wdt"; + reg = <0x10d00200 0x100>; + interrupts = <0 117 4>; + resets = <&rst WATCHDOG0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog1: watchdog@10d00300 { + compatible = "snps,dw-wdt"; + reg = <0x10d00300 0x100>; + interrupts = <0 118 4>; + resets = <&rst WATCHDOG1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog2: watchdog@10d00400 { + compatible = "snps,dw-wdt"; + reg = <0x10d00400 0x100>; + interrupts = <0 125 4>; + resets = <&rst WATCHDOG2_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog3: watchdog@10d00500 { + compatible = "snps,dw-wdt"; + reg = <0x10d00500 0x100>; + interrupts = <0 126 4>; + resets = <&rst WATCHDOG3_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog4: watchdog@10d00600 { + compatible = "snps,dw-wdt"; + reg = <0x10d00600 0x100>; + interrupts = <0 175 4>; + resets = <&rst WATCHDOG4_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + /* QSPI address not available yet */ + qspi: spi@108d2000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x108d2000 0x100>, + <0x10900000 0x100000>; + interrupts = <0 3 4>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + + status = "disabled"; + }; + + firmware { + svc { + compatible = "intel,stratix10-svc"; + method = "smc"; + memory-region = <&service_reserved>; + + fpga_mgr: fpga-mgr { + compatible = "intel,stratix10-soc-fpga-mgr"; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi new file mode 100644 index 00000000000..9eb21d65428 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ + +#include "socfpga_agilex5-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@0x20000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0x20000450 0x00000010>; + status = "disabled"; + }; + }; + + memory { + /* 8GB */ + reg = <0 0x80000000 0 0x80000000>, + <8 0x80000000 1 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc,&flash0,"/memory"; + }; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + bootph-all; + /delete-property/ cdns,read-delay; +}; + +&i3c0 { + bootph-all; +}; + +&i3c1 { + bootph-all; +}; + +&mmc { + status = "okay"; + bus-width = <4>; + sd-uhs-sdr50; + cap-mmc-highspeed; + bootph-all; +}; + +&combophy0 { + status = "okay"; + bootph-all; + cdns,phy-use-ext-lpbk-dqs = <1>; + cdns,phy-use-lpbk-dqs = <1>; + cdns,phy-use-phony-dqs = <1>; + cdns,phy-use-phony-dqs-cmd = <1>; + cdns,phy-io-mask-always-on = <0>; + cdns,phy-io-mask-end = <5>; + cdns,phy-io-mask-start = <0>; + cdns,phy-data-select-oe-end = <1>; + cdns,phy-sync-method = <1>; + cdns,phy-sw-half-cycle-shift = <0>; + cdns,phy-rd-del-sel = <52>; + cdns,phy-underrun-suppress = <1>; + cdns,phy-gate-cfg-always-on = <1>; + cdns,phy-param-dll-bypass-mode = <1>; + cdns,phy-param-phase-detect-sel = <2>; + cdns,phy-param-dll-start-point = <254>; + cdns,phy-read-dqs-cmd-delay = <0>; + cdns,phy-clk-wrdqs-delay = <0>; + cdns,phy-clk-wr-delay = <0>; + cdns,phy-read-dqs-delay = <0>; + cdns,phy-phony-dqs-timing = <0>; + cdns,hrs09-rddata-en = <1>; + cdns,hrs09-rdcmd-en = <1>; + cdns,hrs09-extended-wr-mode = <1>; + cdns,hrs09-extended-rd-mode = <1>; + cdns,hrs10-hcsdclkadj = <3>; + cdns,hrs16-wrdata1-sdclk-dly = <0>; + cdns,hrs16-wrdata0-sdclk-dly = <0>; + cdns,hrs16-wrcmd1-sdclk-dly = <0>; + cdns,hrs16-wrcmd0-sdclk-dly = <0>; + cdns,hrs16-wrdata1-dly = <0>; + cdns,hrs16-wrdata0-dly = <0>; + cdns,hrs16-wrcmd1-dly = <0>; + cdns,hrs16-wrcmd0-dly = <0>; + cdns,hrs07-rw-compensate = <10>; + cdns,hrs07-idelay-val = <0>; +}; + +&qspi { + status = "okay"; +}; + +&timer0 { + bootph-all; +}; + +&timer1 { + bootph-all; +}; + +&timer2 { + bootph-all; +}; + +&timer3 { + bootph-all; +}; + +&watchdog0 { + bootph-all; +}; + diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts new file mode 100644 index 00000000000..852e1e5ae3c --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk.dts @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex5 SoCDK"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet2 = &gmac2; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + soc { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i3c0 { + status = "okay"; +}; + +&i3c1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +}; + +&watchdog1 { + status = "okay"; +}; + +&watchdog2 { + status = "okay"; +}; + +&watchdog3 { + status = "okay"; +}; + +&watchdog4 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&qspi { + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mt25qu02g"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x04200000>; + }; + + root: partition@4200000 { + label = "root"; + reg = <0x04200000 0x0BE00000>; + }; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi index 84b91e8df09..15306db6002 100644 --- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2020 Intel Corporation <www.intel.com> + * Copyright (C) 2020-2024 Intel Corporation <www.intel.com> */ #if defined(CONFIG_FIT) @@ -21,14 +21,18 @@ description = "FIT with firmware and bootloader"; #address-cells = <1>; - images { + images: images { uboot { description = "U-Boot SoC64"; type = "standalone"; os = "U-Boot"; arch = "arm64"; compression = "none"; + #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + load = <0x80200000>; + #else load = <0x00200000>; + #endif uboot_blob: blob-ext { filename = "u-boot-nodtb.bin"; }; @@ -43,8 +47,13 @@ os = "arm-trusted-firmware"; arch = "arm64"; compression = "none"; + #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + load = <0x80000000>; + entry = <0x80000000>; + #else load = <0x00001000>; entry = <0x00001000>; + #endif atf_blob: blob-ext { filename = "bl31.bin"; }; @@ -53,11 +62,11 @@ }; }; - fdt { - description = "U-Boot SoC64 flat device-tree"; + fdt-0 { + description = "socfpga_socdk"; type = "flat_dt"; compression = "none"; - uboot_fdt_blob: blob-ext { + fdt_0_blob: blob-ext { filename = "u-boot.dtb"; }; hash { @@ -66,17 +75,18 @@ }; }; - configurations { - default = "conf"; - conf { - description = "Intel SoC64 FPGA"; + board_config: configurations { + default = "board-0"; + + board-0 { + description = "board_0"; firmware = "atf"; loadables = "uboot"; - fdt = "fdt"; + fdt = "fdt-0"; signature { algo = "crc32"; key-name-hint = "dev"; - sign-images = "atf", "fdt", "uboot"; + sign-images = "atf", "uboot", "fdt-0"; }; }; }; @@ -96,8 +106,8 @@ arch = "arm64"; os = "linux"; compression = "none"; - load = <0x4080000>; - entry = <0x4080000>; + load = <0x6000000>; + entry = <0x6000000>; kernel_blob: blob-ext { filename = "Image"; }; @@ -146,7 +156,7 @@ filename = "signed-bl31.bin"; }; -&uboot_fdt_blob { +&fdt_0_blob { filename = "signed-u-boot.dtb"; }; diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h index bd3a80cdf70..fb64ba076d7 100644 --- a/arch/arm/include/asm/gic.h +++ b/arch/arm/include/asm/gic.h @@ -57,6 +57,7 @@ #define GICR_TYPER 0x0008 #define GICR_STATUSR 0x0010 #define GICR_WAKER 0x0014 +#define GICR_PWRR 0x0024 #define GICR_SETLPIR 0x0040 #define GICR_CLRLPIR 0x0048 #define GICR_SEIR 0x0068 diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index cfd4ecebb62..a29b849d903 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -24,6 +24,7 @@ #define ELE_GET_FW_VERSION_REQ (0x9D) #define ELE_RET_LIFECYCLE_UP_REQ (0xA0) #define ELE_GET_EVENTS_REQ (0xA2) +#define ELE_COMMIT_REQ (0xA8) #define ELE_START_RNG (0xA3) #define ELE_GENERATE_DEK_BLOB (0xAF) #define ELE_ENABLE_PATCH_REQ (0xC3) @@ -142,6 +143,7 @@ int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respon int ele_release_caam(u32 core_did, u32 *response); int ele_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response); int ele_get_events(u32 *events, u32 *events_cnt, u32 *response); +int ele_commit(u16 fuse_id, u32 *response, u32 *info_type); int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_output_size); int ele_dump_buffer(u32 *buffer, u32 buffer_length); int ele_get_info(struct ele_get_info_data *info, u32 *response); diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S index 86cd882fc75..7fa48648d9d 100644 --- a/arch/arm/lib/gic_64.S +++ b/arch/arm/lib/gic_64.S @@ -92,8 +92,16 @@ ENTRY(gic_init_secure_percpu) add x9, x9, #(2 << 16) b 1b +2: +#if defined(CONFIG_GICV3_SUPPORT_GIC600) + mov w10, #0x0 /* Power on redistributor */ + str w10, [x9, GICR_PWRR] +5: ldr w10, [x9, GICR_PWRR] /* Wait until the power on state is reflected */ + tbnz w10, #1, 5b /* If RDPD == 0 then powered on */ +#endif + /* x9: ReDistributor Base Address of Current CPU */ -2: mov w10, #~0x2 + mov w10, #~0x2 ldr w11, [x9, GICR_WAKER] and w11, w11, w10 /* Clear ProcessorSleep */ str w11, [x9, GICR_WAKER] diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index c5fd8692721..8a8ac53e4f8 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -286,6 +286,15 @@ config TARGET_SAMA7G5EK select BOARD_EARLY_INIT_F select BOARD_LATE_INIT +config TARGET_SAMA7G54_CURIOSITY + bool "SAMA7G54 CURIOSITY board" + select SAMA7G5 + select CPU_V7A + help + The SAMA7G54 Curiosity embeds SAMA7G54D2G SiP (System in Package) + with 2Gbit DDR3-SDRAM, 64Mbit QSPI nor-flash with MAC-address, + 4Gbit SLC nand-flash, MCP16502 PMIC, 2 x Mikrobus connectors, + 1 x SD-Card connector, 1 x M.2 slot, 3 x USB config TARGET_TAURUS bool "Support taurus" @@ -366,6 +375,7 @@ source "board/atmel/at91sam9x5ek/Kconfig" source "board/atmel/sam9x60ek/Kconfig" source "board/atmel/sam9x60_curiosity/Kconfig" source "board/atmel/sama7g5ek/Kconfig" +source "board/atmel/sama7g54_curiosity/Kconfig" source "board/atmel/sama5d2_ptc_ek/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d27_som1_ek/Kconfig" diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 295c055ad0a..d02316ed6cb 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -625,6 +625,29 @@ static int do_ahab_return_lifecycle(struct cmd_tbl *cmdtp, int flag, int argc, c return CMD_RET_SUCCESS; } +static int do_ahab_commit(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + u32 index; + u32 resp; + u32 info_type; + + if (argc < 2) + return CMD_RET_USAGE; + + index = simple_strtoul(argv[1], NULL, 16); + printf("Commit index is 0x%x\n", index); + + if (ele_commit(index, &resp, &info_type)) { + printf("Error in AHAB commit\n"); + return -EIO; + } + + printf("Ahab commit succeeded. Information type is 0x%x\n", info_type); + + return 0; +} + U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate, "autenticate OS container via AHAB", "addr\n" @@ -657,3 +680,9 @@ U_BOOT_CMD(ahab_return_lifecycle, CONFIG_SYS_MAXARGS, 1, do_ahab_return_lifecycl "addr\n" "addr - Return lifecycle message block signed by OEM SRK\n" ); + +U_BOOT_CMD(ahab_commit, CONFIG_SYS_MAXARGS, 1, do_ahab_commit, + "commit into the fuses any new SRK revocation and FW version information\n" + "that have been found into the NXP (ELE FW) and OEM containers", + "" +); diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 328c3e38805..5db643c1958 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -119,6 +119,7 @@ config TARGET_IMX8MM_VENICE select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_KONTRON_MX8MM bool "Kontron Electronics N80xx" @@ -167,6 +168,7 @@ config TARGET_IMX8MN_VENICE select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_IMX8MP_DATA_MODUL_EDM_SBC bool "Data Modul eDM SBC i.MX8M Plus" @@ -227,6 +229,7 @@ config TARGET_IMX8MP_VENICE select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_PICO_IMX8MQ bool "Support Technexion Pico iMX8MQ" diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 39802d6a796..0c49fb9cd48 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -933,19 +933,28 @@ int disable_vpu_nodes(void *blob) { static const char * const nodes_path_8mq[] = { "/vpu@38300000", - "/soc@0/vpu@38300000" + "/soc@0/vpu@38300000", + "/soc@0/video-codec@38300000", + "/soc@0/video-codec@38310000", + "/soc@0/blk-ctrl@38320000", }; static const char * const nodes_path_8mm[] = { "/vpu_g1@38300000", "/vpu_g2@38310000", - "/vpu_h1@38320000" + "/vpu_h1@38320000", + "/soc@0/video-codec@38300000", + "/soc@0/video-codec@38310000", + "/soc@0/blk-ctrl@38330000", }; static const char * const nodes_path_8mp[] = { "/vpu_g1@38300000", "/vpu_g2@38310000", - "/vpu_vc8000e@38320000" + "/vpu_vc8000e@38320000", + "/soc@0/video-codec@38300000", + "/soc@0/video-codec@38310000", + "/soc@0/blk-ctrl@38330000", }; if (is_imx8mq()) @@ -1100,7 +1109,8 @@ int disable_gpu_nodes(void *blob) int disable_npu_nodes(void *blob) { static const char * const nodes_path_8mp[] = { - "/vipsi@38500000" + "/vipsi@38500000", + "/soc@0/npu@38500000", }; return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp)); diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c index 7309573a3fa..c02f8d33099 100644 --- a/arch/arm/mach-k3/r5/common.c +++ b/arch/arm/mach-k3/r5/common.c @@ -70,7 +70,7 @@ int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr) char *name = NULL; int size = 0; - if (!IS_ENABLED(CONFIG_FS_LOADER)) + if (!CONFIG_IS_ENABLED(FS_LOADER)) return 0; *loadaddr = 0; diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index 57917da25cf..aa0ab13d5fb 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -190,7 +190,7 @@ int load_firmware(char *name_fw, u32 *loadaddr) struct udevice *fsdev; int size = 0; - if (!IS_ENABLED(CONFIG_FS_LOADER)) + if (!CONFIG_IS_ENABLED(FS_LOADER)) return 0; if (!*loadaddr) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 114d2438129..1008232cac8 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -8,7 +8,8 @@ config NR_DRAM_BANKS config SOCFPGA_SECURE_VAB_AUTH bool "Enable boot image authentication with Secure Device Manager" - depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X + depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X || \ + TARGET_SOCFPGA_AGILEX5 select FIT_IMAGE_POST_PROCESS select SHA384 select SHA512 @@ -58,6 +59,15 @@ config TARGET_SOCFPGA_AGILEX select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64 +config TARGET_SOCFPGA_AGILEX5 + bool + select BINMAN if SPL_ATF + select CLK + select FPGA_INTEL_SDM_MAILBOX + select GICV3 + select SPL_CLK if SPL + select TARGET_SOCFPGA_SOC64 + config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 @@ -129,6 +139,10 @@ config TARGET_SOCFPGA_AGILEX_SOCDK bool "Intel SOCFPGA SoCDK (Agilex)" select TARGET_SOCFPGA_AGILEX +config TARGET_SOCFPGA_AGILEX5_SOCDK + bool "Intel SOCFPGA SoCDK (Agilex5)" + select TARGET_SOCFPGA_AGILEX5 + config TARGET_SOCFPGA_ARIES_MCVEVK bool "Aries MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -202,6 +216,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT endchoice config SYS_BOARD + default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK @@ -223,6 +238,7 @@ config SYS_BOARD default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA config SYS_VENDOR + default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK default "intel" if TARGET_SOCFPGA_N5X_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -245,6 +261,7 @@ config SYS_SOC default "socfpga" config SYS_CONFIG_NAME + default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index ec38b64dd4d..67c6a8dfec5 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -4,7 +4,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # Copyright (C) 2012-2017 Altera Corporation <www.altera.com> -# Copyright (C) 2017-2021 Intel Corporation <www.intel.com> +# Copyright (C) 2017-2024 Intel Corporation <www.intel.com> obj-y += board.o obj-y += clock_manager.o @@ -56,6 +56,15 @@ obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 +obj-y += clock_manager_agilex5.o +obj-y += mailbox_s10.o +obj-y += misc_soc64.o +obj-y += mmu-arm64_s10.o +obj-y += reset_manager_s10.o +obj-y += wrap_pll_config_soc64.o +endif + ifdef CONFIG_TARGET_SOCFPGA_N5X obj-y += clock_manager_n5x.o obj-y += lowlevel_init_soc64.o @@ -95,6 +104,9 @@ endif ifdef CONFIG_TARGET_SOCFPGA_N5X obj-y += spl_n5x.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 +obj-y += spl_soc64.o +endif else obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o obj-$(CONFIG_SPL_ATF) += smc_api.o diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 09e09192fba..616e1afe5de 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -7,9 +7,11 @@ #include <common.h> #include <asm/arch/clock_manager.h> +#include <asm/arch/mailbox_s10.h> #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/secure_vab.h> +#include <asm/arch/smc_api.h> #include <asm/global_data.h> #include <asm/io.h> #include <errno.h> @@ -23,6 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; +#define DEFAULT_JTAG_USERCODE 0xFFFFFFFF + void s_init(void) { #ifndef CONFIG_ARM64 /* @@ -92,13 +96,50 @@ int g_dnl_board_usb_cable_connected(void) } #endif -#ifdef CONFIG_SPL_BUILD -__weak int board_fit_config_name_match(const char *name) +u8 socfpga_get_board_id(void) { - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); + u8 board_id = 0; + u32 jtag_usercode; + int err; - return 0; +#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF) + err = smc_get_usercode(&jtag_usercode); +#else + u32 resp_len = 1; + + err = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_GET_USERCODE, MBOX_CMD_DIRECT, 0, + NULL, 0, &resp_len, &jtag_usercode); +#endif + + if (err) { + puts("Fail to read JTAG Usercode. Default Board ID to 0\n"); + return board_id; + } + + debug("Valid JTAG Usercode: %u\n", jtag_usercode); + + if (jtag_usercode == DEFAULT_JTAG_USERCODE) { + debug("JTAG Usercode is not set. Default Board ID to 0\n"); + } else if (jtag_usercode >= 0 && jtag_usercode <= 255) { + board_id = jtag_usercode; + debug("Valid JTAG Usercode. Set Board ID to %u\n", board_id); + } else { + puts("Board ID is not in range 0 to 255\n"); + } + + return board_id; +} + +#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +int board_fit_config_name_match(const char *name) +{ + char board_name[10]; + + sprintf(board_name, "board_%u", socfpga_get_board_id()); + + debug("Board name: %s\n", board_name); + + return strcmp(name, board_name); } #endif @@ -116,6 +157,8 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, #if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT) void board_prep_linux(struct bootm_headers *images) { + bool use_fit = false; + if (!images->fit_uname_cfg) { if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) && !IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) { @@ -127,12 +170,13 @@ void board_prep_linux(struct bootm_headers *images) hang(); } } else { + use_fit = true; /* Update fdt_addr in enviroment variable */ env_set_hex("fdt_addr", (ulong)images->ft_addr); debug("images->ft_addr = 0x%08lx\n", (ulong)images->ft_addr); } - if (IS_ENABLED(CONFIG_CADENCE_QSPI)) { + if (use_fit && IS_ENABLED(CONFIG_CADENCE_QSPI)) { if (env_get("linux_qspi_enable")) run_command(env_get("linux_qspi_enable"), 0); } diff --git a/arch/arm/mach-socfpga/clock_manager_agilex5.c b/arch/arm/mach-socfpga/clock_manager_agilex5.c new file mode 100644 index 00000000000..b92f0b3af80 --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_agilex5.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + * + */ + +#include <clk.h> +#include <config.h> +#include <dm.h> +#include <errno.h> +#include <log.h> +#include <malloc.h> +#include <stdarg.h> +#include <stdio.h> +#include <time.h> +#include <vsprintf.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/u-boot.h> +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/types.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/system_manager.h> +#include <dt-bindings/clock/agilex5-clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +static ulong cm_get_rate_dm(u32 id) +{ + struct udevice *dev; + struct clk clk; + ulong rate; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(socfpga_agilex5_clk), + &dev); + if (ret) + return 0; + + clk.id = id; + ret = clk_request(dev, &clk); + if (ret < 0) + return 0; + + rate = clk_get_rate(&clk); + + if ((rate == (unsigned long)-ENOSYS) || + (rate == (unsigned long)-ENXIO) || + (rate == (unsigned long)-EIO)) { + debug("%s id %u: clk_get_rate err: %ld\n", + __func__, id, rate); + return 0; + } + + return rate; +} + +static u32 cm_get_rate_dm_khz(u32 id) +{ + return cm_get_rate_dm(id) / 1000; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + return cm_get_rate_dm(AGILEX5_MPU_CLK); +} + +unsigned int cm_get_l4_sys_free_clk_hz(void) +{ + return cm_get_rate_dm(AGILEX5_L4_SYS_FREE_CLK); +} + +void cm_print_clock_quick_summary(void) +{ + printf("MPU %10d kHz\n", + cm_get_rate_dm_khz(AGILEX5_MPU_CLK)); + printf("L4 Main %8d kHz\n", + cm_get_rate_dm_khz(AGILEX5_L4_MAIN_CLK)); + printf("L4 sys free %8d kHz\n", + cm_get_rate_dm_khz(AGILEX5_L4_SYS_FREE_CLK)); + printf("L4 MP %8d kHz\n", + cm_get_rate_dm_khz(AGILEX5_L4_MP_CLK)); + printf("L4 SP %8d kHz\n", + cm_get_rate_dm_khz(AGILEX5_L4_SP_CLK)); + printf("SDMMC %8d kHz\n", + cm_get_rate_dm_khz(AGILEX5_SDMMC_CLK)); +} diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 3f899fcfa3a..65721098b2b 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -1,11 +1,46 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2016-2021 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2024 Intel Corporation <www.intel.com> */ #ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_ #define _SOCFPGA_SOC64_BASE_HARDWARE_H_ +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOCFPGA_CCU_ADDRESS 0x1c000000 +#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0x18001000 +#define SOCFPGA_SMMU_ADDRESS 0x16000000 +#define SOCFPGA_OCRAM_FIREWALL_ADDRESS 0x108cc400 +#define SOCFPGA_MAILBOX_ADDRESS 0x10a30000 +#define SOCFPGA_UART0_ADDRESS 0x10c02000 +#define SOCFPGA_UART1_ADDRESS 0x10c02100 +#define SOCFPGA_SPTIMER0_ADDRESS 0x10c03000 +#define SOCFPGA_SPTIMER1_ADDRESS 0x10c03100 +#define SOCFPGA_SYSTIMER0_ADDRESS 0x10d00000 +#define SOCFPGA_SYSTIMER1_ADDRESS 0x10d00100 +#define SOCFPGA_L4WD0_ADDRESS 0x10d00200 +#define SOCFPGA_L4WD1_ADDRESS 0x10d00300 +#define SOCFPGA_L4WD2_ADDRESS 0x10d00400 +#define SOCFPGA_L4WD3_ADDRESS 0x10d00500 +#define SOCFPGA_L4WD4_ADDRESS 0x10d00600 +#define SOCFPGA_GTIMER_SEC_ADDRESS 0x10d01000 +#define SOCFPGA_GTIMER_NSEC_ADDRESS 0x10d02000 +#define SOCFPGA_CLKMGR_ADDRESS 0x10d10000 +#define SOCFPGA_RSTMGR_ADDRESS 0x10d11000 +#define SOCFPGA_SYSMGR_ADDRESS 0x10d12000 +#define SOCFPGA_OCRAM_ADDRESS 0x00000000 +#define SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS 0x18000800 +#define SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS 0x18000A00 +#define SOCFPGA_FW_TBU2NOC_ADDRESS 0x18000C00 +#define SOCFPGA_FIREWALL_L4_PER 0x10d21000 +#define SOCFPGA_FIREWALL_L4_SYS 0x10d21100 +#define SOCFPGA_FIREWALL_SOC2FPGA 0x10d21200 +#define SOCFPGA_FIREWALL_LWSOC2FPGA 0x10d21300 +#define SOCFPGA_FIREWALL_TCU 0x10d21400 +#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV 0x10d24800 +#define GICD_BASE 0x1d000000 +#define GICR_BASE 0x1d060000 +#else #define SOCFPGA_CCU_ADDRESS 0xf7000000 #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 @@ -44,5 +79,6 @@ #define SOCFPGA_OCRAM_ADDRESS 0xffe00000 #define GICD_BASE 0xfffc1000 #define GICC_BASE 0xfffc2000 +#endif /* IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) */ #endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index a8cb07a1c47..6c9d32b9dd8 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> + * Copyright (C) 2013-2024 Altera Corporation <www.altera.com> */ #ifndef _CLOCK_MANAGER_H_ @@ -28,6 +28,8 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz); #include <asm/arch/clock_manager_s10.h> #elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) #include <asm/arch/clock_manager_agilex.h> +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#include <asm/arch/clock_manager_agilex5.h> #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #include <asm/arch/clock_manager_n5x.h> #endif diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h new file mode 100644 index 00000000000..1ae0a926032 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ + +#ifndef _CLOCK_MANAGER_AGILEX5_ +#define _CLOCK_MANAGER_AGILEX5_ + +#include <asm/arch/clock_manager_soc64.h> +#include "../../../../../drivers/clk/altera/clk-agilex5.h" + +#endif /* _CLOCK_MANAGER_AGILEX5_ */ diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 9b85e5865ba..d839f288411 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2016-2021 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2024 Intel Corporation <www.intel.com> * */ @@ -17,7 +17,12 @@ #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 #define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 #define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOC64_HANDOFF_MAGIC_PERI 0x50455249 +#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524d +#else #define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 +#endif #define SOC64_HANDOFF_OFFSET_LENGTH 0x4 #define SOC64_HANDOFF_OFFSET_DATA 0x10 @@ -27,6 +32,8 @@ IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) #define SOC64_HANDOFF_BASE 0xFFE3F000 #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOC64_HANDOFF_BASE 0x0007F000 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SOC64_HANDOFF_BASE 0xFFE5F000 #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630) @@ -58,13 +65,21 @@ #define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) #define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0) #define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580) +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOC64_HANDOFF_PERI (SOC64_HANDOFF_BASE + 0x620) +#define SOC64_HANDOFF_SDRAM (SOC64_HANDOFF_BASE + 0x634) +#define SOC64_HANDOFF_SDRAM_LEN 1 +#endif #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) -#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608) -#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C) +#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608) +#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C) +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x60c) +#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x610) #else -#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x5fc) -#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600) +#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x5fc) +#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600) #endif #define SOC64_HANDOFF_MUX_LEN 96 diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index fbaf11597ed..2cc7c890449 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -119,6 +119,7 @@ enum ALT_SDM_MBOX_RESP_CODE { #define MBOX_RECONFIG_DATA 8 #define MBOX_RECONFIG_STATUS 9 #define MBOX_VAB_SRC_CERT 11 +#define MBOX_GET_USERCODE 19 #define MBOX_QSPI_OPEN 50 #define MBOX_QSPI_CLOSE 51 #define MBOX_QSPI_DIRECT 59 diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c index a55b7b7cf3b..91c6d7c55f1 100644 --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2024 Intel Corporation <www.intel.com> * */ @@ -10,6 +10,62 @@ DECLARE_GLOBAL_DATA_PTR; +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +static struct mm_region socfpga_agilex5_mem_map[] = { + { + /* OCRAM 512KB */ + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x00080000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE, + }, { + /* DEVICE */ + .virt = 0x10808000UL, + .phys = 0x10808000UL, + .size = 0x0F7F8000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* FPGA 1.5GB */ + .virt = 0x20000000UL, + .phys = 0x20000000UL, + .size = 0x60000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* FPGA 15GB */ + .virt = 0x440000000UL, + .phys = 0x440000000UL, + .size = 0x3C0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* FPGA 240GB */ + .virt = 0x4400000000UL, + .phys = 0x4400000000UL, + .size = 0x3C00000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, { + /* MEM 2GB */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + /* List terminator */ + }, +}; + +struct mm_region *mem_map = socfpga_agilex5_mem_map; + +#else static struct mm_region socfpga_stratix10_mem_map[] = { { /* MEM 2GB*/ @@ -70,3 +126,4 @@ static struct mm_region socfpga_stratix10_mem_map[] = { }; struct mm_region *mem_map = socfpga_stratix10_mem_map; +#endif diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c index df0701ec85e..6aa9bb26b4e 100644 --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -11,7 +11,6 @@ #include "log.h" #ifndef __ASSEMBLY__ -#include <asm/types.h> enum endianness { LITTLE_ENDIAN = 0, BIG_ENDIAN, diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig index 1b5339993f8..54fb93aeb53 100644 --- a/arch/arm/mach-versal-net/Kconfig +++ b/arch/arm/mach-versal-net/Kconfig @@ -35,6 +35,9 @@ config SYS_MEM_RSVD_FOR_MMU config GICV3 def_bool y +config GICV3_SUPPORT_GIC600 + def_bool y + config SYS_MALLOC_LEN default 0x2000000 diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 9ee1fcb5c70..1621cc9a1ff 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -14,4 +14,4 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_GO) += boot.o obj-$(CONFIG_SPL_BUILD) += spl.o -lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o udivdi3.o diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 602741c65dc..d64209d76a9 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -431,9 +431,9 @@ LEAF(change_k0_cca) #else xor a0, a0, t0 andi a0, a0, CONF_CM_CMASK - xor a0, a0, t0 + xor t0, a0, t0 #endif - mtc0 a0, CP0_CONFIG + mtc0 t0, CP0_CONFIG jr.hb ra END(change_k0_cca) diff --git a/arch/mips/lib/udivdi3.c b/arch/mips/lib/udivdi3.c new file mode 100644 index 00000000000..4d780117cf1 --- /dev/null +++ b/arch/mips/lib/udivdi3.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#include "libgcc.h" + +#if BITS_PER_LONG == 32 + +#include <div64.h> + +long long __udivdi3(long long u, word_type b) +{ + long long ret = u; + + __div64_32(&ret, b); + return ret; +} + +#endif /* BITS_PER_LONG == 32 */ diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 8445c5823e1..ecfefa1a025 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -49,14 +49,24 @@ static inline bool supports_extension(char ext) } if (!cpu_get_desc(dev, desc, sizeof(desc))) { /* - * skip the first 4 characters (rv32|rv64) and - * check until underscore + * skip the first 4 characters (rv32|rv64) */ for (i = 4; i < sizeof(desc); i++) { - if (desc[i] == '_' || desc[i] == '\0') - break; - if (desc[i] == ext) - return true; + switch (desc[i]) { + case 's': + case 'x': + case 'z': + case '_': + case '\0': + /* + * Any of these characters mean the single + * letter extensions have all been consumed. + */ + return false; + default: + if (desc[i] == ext) + return true; + } } } diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi index 706224b384d..956237c3218 100644 --- a/arch/riscv/dts/fu740-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi @@ -77,7 +77,7 @@ 0x0 0x100b2000 0x0 0x2000 0x0 0x100b8000 0x0 0x1000>; clocks = <&prci FU740_PRCI_CLK_DDRPLL>; - clock-frequency = <933333324>; + clock-frequency = <800000004>; bootph-pre-ram; }; }; diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi index 55185314dde..3012466b305 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi @@ -112,6 +112,6 @@ u-boot-spl { }; + }; }; }; -}; diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index 2f560e7296f..c09d5c91708 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -93,6 +93,10 @@ bootph-pre-ram; }; +&pllclk { + bootph-pre-ram; +}; + &S7_0 { status = "okay"; }; diff --git a/arch/x86/lib/acpi_nhlt.c b/arch/x86/lib/acpi_nhlt.c index 6c8cd83e12d..08e13fdea67 100644 --- a/arch/x86/lib/acpi_nhlt.c +++ b/arch/x86/lib/acpi_nhlt.c @@ -409,7 +409,7 @@ int nhlt_serialise_oem_overrides(struct acpi_ctx *ctx, struct nhlt *nhlt, memcpy(header->oem_table_id, oem_table_id, oem_table_id_len); } header->oem_revision = oem_revision; - memcpy(header->aslc_id, ASLC_ID, 4); + memcpy(header->creator_id, ASLC_ID, 4); cur.buf = (void *)(header + 1); cur.start = (void *)header; diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 5ecd3d4b651..a5683132b01 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -253,7 +253,7 @@ static int acpi_write_tpm2(struct acpi_ctx *ctx, /* Fill out header fields. */ acpi_fill_header(header, "TPM2"); - memcpy(header->aslc_id, ASLC_ID, 4); + memcpy(header->creator_id, ASLC_ID, 4); header->length = sizeof(struct acpi_tpm2); header->revision = acpi_get_table_revision(ACPITAB_TPM2); @@ -479,7 +479,7 @@ static int acpi_create_hpet(struct acpi_hpet *hpet) /* Fill out header fields. */ acpi_fill_header(header, "HPET"); - header->aslc_revision = ASL_REVISION; + header->creator_revision = ASL_REVISION; header->length = sizeof(struct acpi_hpet); header->revision = acpi_get_table_revision(ACPITAB_HPET); @@ -569,8 +569,8 @@ void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs, header->revision = 4; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, OEM_TABLE_ID, 8); - memcpy(header->aslc_id, ASLC_ID, 4); - header->aslc_revision = 1; + memcpy(header->creator_id, ASLC_ID, 4); + header->creator_revision = 1; fadt->x_firmware_ctrl = map_to_sysmem(facs); fadt->x_dsdt = map_to_sysmem(dsdt); diff --git a/board/amlogic/beelink-s922x/beelink-s922x.c b/board/amlogic/beelink-s922x/beelink-s922x.c index adae27fc7e7..c2776310a3d 100644 --- a/board/amlogic/beelink-s922x/beelink-s922x.c +++ b/board/amlogic/beelink-s922x/beelink-s922x.c @@ -20,7 +20,7 @@ int misc_init_r(void) { - u8 mac_addr[MAC_ADDR_LEN]; + u8 mac_addr[MAC_ADDR_LEN + 1]; char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3]; ssize_t len; @@ -41,6 +41,7 @@ int misc_init_r(void) tmp[2] = '\0'; mac_addr[i] = hextoul(tmp, NULL); } + mac_addr[MAC_ADDR_LEN] = '\0'; if (is_valid_ethaddr(mac_addr)) eth_env_set_enetaddr("ethaddr", mac_addr); diff --git a/board/amlogic/jethub-j100/jethub-j100.c b/board/amlogic/jethub-j100/jethub-j100.c index 6a2c4ad4c3c..010fc0df7d1 100644 --- a/board/amlogic/jethub-j100/jethub-j100.c +++ b/board/amlogic/jethub-j100/jethub-j100.c @@ -17,7 +17,7 @@ int misc_init_r(void) { - u8 mac_addr[ARP_HLEN]; + u8 mac_addr[ARP_HLEN + 1]; char serial[SM_SERIAL_SIZE]; u32 sid; @@ -34,6 +34,7 @@ int misc_init_r(void) mac_addr[3] = (sid >> 16) & 0xff; mac_addr[4] = (sid >> 8) & 0xff; mac_addr[5] = (sid >> 0) & 0xff; + mac_addr[ARP_HLEN] = '\0'; eth_env_set_enetaddr("ethaddr", mac_addr); } diff --git a/board/amlogic/jethub-j80/jethub-j80.c b/board/amlogic/jethub-j80/jethub-j80.c index 185880de139..0b781666e98 100644 --- a/board/amlogic/jethub-j80/jethub-j80.c +++ b/board/amlogic/jethub-j80/jethub-j80.c @@ -27,9 +27,9 @@ int misc_init_r(void) { - u8 mac_addr[EFUSE_MAC_SIZE]; - char serial[EFUSE_SN_SIZE]; - char usid[EFUSE_USID_SIZE]; + u8 mac_addr[EFUSE_MAC_SIZE + 1]; + char serial[EFUSE_SN_SIZE + 1]; + char usid[EFUSE_USID_SIZE + 1]; ssize_t len; unsigned int adcval; int ret; @@ -37,6 +37,7 @@ int misc_init_r(void) if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, mac_addr, EFUSE_MAC_SIZE); + mac_addr[len] = '\0'; if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) eth_env_set_enetaddr("ethaddr", mac_addr); else @@ -46,6 +47,7 @@ int misc_init_r(void) if (!env_get("serial")) { len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, EFUSE_SN_SIZE); + serial[len] = '\0'; if (len == EFUSE_SN_SIZE) env_set("serial", serial); } @@ -53,6 +55,7 @@ int misc_init_r(void) if (!env_get("usid")) { len = meson_sm_read_efuse(EFUSE_USID_OFFSET, usid, EFUSE_USID_SIZE); + usid[len] = '\0'; if (len == EFUSE_USID_SIZE) env_set("usid", usid); } diff --git a/board/amlogic/odroid-n2/odroid-n2.c b/board/amlogic/odroid-n2/odroid-n2.c index 2135457edd9..a4bcc62174a 100644 --- a/board/amlogic/odroid-n2/odroid-n2.c +++ b/board/amlogic/odroid-n2/odroid-n2.c @@ -107,7 +107,7 @@ static int odroid_detect_variant(void) int misc_init_r(void) { - u8 mac_addr[MAC_ADDR_LEN]; + u8 mac_addr[MAC_ADDR_LEN + 1]; char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3]; ssize_t len; @@ -128,6 +128,7 @@ int misc_init_r(void) tmp[2] = '\0'; mac_addr[i] = hextoul(tmp, NULL); } + mac_addr[MAC_ADDR_LEN] = '\0'; if (is_valid_ethaddr(mac_addr)) eth_env_set_enetaddr("ethaddr", mac_addr); diff --git a/board/amlogic/p200/p200.c b/board/amlogic/p200/p200.c index 7c432f9d281..754242e4a9f 100644 --- a/board/amlogic/p200/p200.c +++ b/board/amlogic/p200/p200.c @@ -21,20 +21,24 @@ int misc_init_r(void) { - u8 mac_addr[EFUSE_MAC_SIZE]; - char serial[EFUSE_SN_SIZE]; + u8 mac_addr[EFUSE_MAC_SIZE + 1]; + char serial[EFUSE_SN_SIZE + 1]; ssize_t len; if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, mac_addr, EFUSE_MAC_SIZE); + mac_addr[len] = '\0'; if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) eth_env_set_enetaddr("ethaddr", mac_addr); + else + meson_generate_serial_ethaddr(); } if (!env_get("serial#")) { len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, EFUSE_SN_SIZE); + serial[len] = '\0'; if (len == EFUSE_SN_SIZE) env_set("serial#", serial); } diff --git a/board/amlogic/p201/p201.c b/board/amlogic/p201/p201.c index 7c432f9d281..769e2735d27 100644 --- a/board/amlogic/p201/p201.c +++ b/board/amlogic/p201/p201.c @@ -21,13 +21,14 @@ int misc_init_r(void) { - u8 mac_addr[EFUSE_MAC_SIZE]; - char serial[EFUSE_SN_SIZE]; + u8 mac_addr[EFUSE_MAC_SIZE + 1]; + char serial[EFUSE_SN_SIZE + 1]; ssize_t len; if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, mac_addr, EFUSE_MAC_SIZE); + mac_addr[len] = '\0'; if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) eth_env_set_enetaddr("ethaddr", mac_addr); } @@ -35,6 +36,7 @@ int misc_init_r(void) if (!env_get("serial#")) { len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, EFUSE_SN_SIZE); + serial[len] = '\0'; if (len == EFUSE_SN_SIZE) env_set("serial#", serial); } diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c index fcef90bce56..f6e60ae3af1 100644 --- a/board/amlogic/p212/p212.c +++ b/board/amlogic/p212/p212.c @@ -22,13 +22,14 @@ int misc_init_r(void) { - u8 mac_addr[EFUSE_MAC_SIZE]; - char serial[EFUSE_SN_SIZE]; + u8 mac_addr[EFUSE_MAC_SIZE + 1]; + char serial[EFUSE_SN_SIZE + 1]; ssize_t len; if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, mac_addr, EFUSE_MAC_SIZE); + mac_addr[len] = '\0'; if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) eth_env_set_enetaddr("ethaddr", mac_addr); else @@ -38,6 +39,7 @@ int misc_init_r(void) if (!env_get("serial#")) { len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, EFUSE_SN_SIZE); + serial[len] = '\0'; if (len == EFUSE_SN_SIZE) env_set("serial#", serial); } diff --git a/board/amlogic/q200/q200.c b/board/amlogic/q200/q200.c index 3aa6d8f200e..47f1566a9d3 100644 --- a/board/amlogic/q200/q200.c +++ b/board/amlogic/q200/q200.c @@ -22,13 +22,14 @@ int misc_init_r(void) { - u8 mac_addr[EFUSE_MAC_SIZE]; - char serial[EFUSE_SN_SIZE]; + u8 mac_addr[EFUSE_MAC_SIZE + 1]; + char serial[EFUSE_SN_SIZE + 1]; ssize_t len; if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, mac_addr, EFUSE_MAC_SIZE); + mac_addr[len] = '\0'; if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) eth_env_set_enetaddr("ethaddr", mac_addr); else @@ -38,6 +39,7 @@ int misc_init_r(void) if (!env_get("serial#")) { len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, EFUSE_SN_SIZE); + serial[len] = '\0'; if (len == EFUSE_SN_SIZE) env_set("serial#", serial); } diff --git a/board/amlogic/vim3/vim3.c b/board/amlogic/vim3/vim3.c index 8bdfb302f72..43d7a8e84f6 100644 --- a/board/amlogic/vim3/vim3.c +++ b/board/amlogic/vim3/vim3.c @@ -151,7 +151,7 @@ int meson_ft_board_setup(void *blob, struct bd_info *bd) int misc_init_r(void) { - u8 mac_addr[MAC_ADDR_LEN]; + u8 mac_addr[MAC_ADDR_LEN + 1]; char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3]; char serial_string[EFUSE_MAC_SIZE + 1]; ssize_t len; @@ -169,6 +169,7 @@ int misc_init_r(void) tmp[2] = '\0'; mac_addr[i] = hextoul(tmp, NULL); } + mac_addr[MAC_ADDR_LEN] = '\0'; if (is_valid_ethaddr(mac_addr)) eth_env_set_enetaddr("ethaddr", mac_addr); diff --git a/board/atmel/sama7g54_curiosity/Kconfig b/board/atmel/sama7g54_curiosity/Kconfig new file mode 100644 index 00000000000..3e60d96712f --- /dev/null +++ b/board/atmel/sama7g54_curiosity/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA7G54_CURIOSITY + +config SYS_BOARD + default "sama7g54_curiosity" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama7g54_curiosity" + +endif diff --git a/board/atmel/sama7g54_curiosity/MAINTAINERS b/board/atmel/sama7g54_curiosity/MAINTAINERS new file mode 100644 index 00000000000..b9f1a271c09 --- /dev/null +++ b/board/atmel/sama7g54_curiosity/MAINTAINERS @@ -0,0 +1,9 @@ +SAMA7G54 CURIOSITY BOARD +M: Mihai Sain <mihai.sain@microchip.com> +S: Maintained +F: board/atmel/sama7g54_curiosity.c +F: include/configs/sama7g54_curiosity.h +F: configs/sama7g54_curiosity_mmc_defconfig +F: configs/sama7g54_curiosity_nandflash_defconfig +F: configs/sama7g54_curiosity_qspiflash_defconfig +F: arch/arm/dts/at91-sama7g54_curiosity* diff --git a/board/atmel/sama7g54_curiosity/Makefile b/board/atmel/sama7g54_curiosity/Makefile new file mode 100644 index 00000000000..bc77655f354 --- /dev/null +++ b/board/atmel/sama7g54_curiosity/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries +# +# Author: Mihai Sain <mihai.sain@microchip.com> + +obj-y += sama7g54_curiosity.o diff --git a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c new file mode 100644 index 00000000000..33cd0903d25 --- /dev/null +++ b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Mihai Sain <mihai.sain@microchip.com> + * + */ + +#include <common.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama7g5.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + // Address of boot parameters + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + return 0; +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index 0902a1da3e2..f54f1186b68 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -25,12 +25,13 @@ int board_phys_sdram_size(phys_size_t *size) return 0; } -int board_fit_config_name_match(const char *name) +int board_fit_config_name_match(const char *path) { - int i = 0; - const char *dtb; + const char *name = path + strlen("freescale/"); static char init; + const char *dtb; char buf[32]; + int i = 0; do { dtb = eeprom_get_dtb_name(i++, buf, sizeof(buf)); diff --git a/board/intel/agilex5-socdk/MAINTAINERS b/board/intel/agilex5-socdk/MAINTAINERS new file mode 100644 index 00000000000..b696f788c81 --- /dev/null +++ b/board/intel/agilex5-socdk/MAINTAINERS @@ -0,0 +1,8 @@ +SOCFPGA BOARD +M: Tien Fong Chee <tien.fong.chee@intel.com> +M: Teik Heng Chong <teik.heng.chong@intel.com> +M: Jit Loon Lim <jit.loon.lim@intel.com> +S: Maintained +F: board/intel/agilex5-socdk/ +F: include/configs/socfpga_agilex5_socdk.h +F: configs/socfpga_agilex5_defconfig diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index f9607b018de..a56e0f60d62 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -248,4 +248,9 @@ u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data) return PHYTEC_EEPROM_INVAL; } +u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + #endif /* IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) */ diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env b/board/phytec/phycore_imx8mp/phycore_imx8mp.env new file mode 100644 index 00000000000..7f6c5fd2c76 --- /dev/null +++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env @@ -0,0 +1,62 @@ +#include <env/phytec/rauc.env> + +bootcmd= + if test ${dofastboot} = 1; then + fastboot 0; + fi; + mmc dev ${mmcdev}; + if mmc rescan; then + if test ${doraucboot} = 1; then + run raucinit; + fi; + if run loadimage; then + run mmcboot; + else + run netboot; + fi; + fi; +console=ttymxc0,115200 +dofastboot=0 +emmc_dev=2 +fastboot_raw_partition_all=0 4194304 +fastboot_raw_partition_bootloader=64 8128 +fdt_addr=0x48000000 +fdt_file=CONFIG_DEFAULT_FDT_FILE +image=Image +ip_dyn=yes +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +mmcargs= + setenv bootargs console=${console} + root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw +mmcautodetect=yes +mmcboot= + echo Booting from mmc ...; + run mmcargs; + if run loadfdt; then + booti ${loadaddr} - ${fdt_addr}; + else + echo WARN: Cannot load the DT; + fi; +mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcpart=1 +mmcroot=2 +netargs= + setenv bootargs console=${console} root=/dev/nfs ip=dhcp + nfsroot=${serverip}:${nfsroot},v3,tcp +netboot= + echo Booting from net ...; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${loadaddr} ${image}; + run netargs; + if ${get_cmd} ${fdt_addr} ${fdt_file}; then + booti ${loadaddr} - ${fdt_addr}; + else + echo WARN: Cannot load the DT; + fi; +nfsroot=/srv/nfs +sd_dev=1 diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS index 600ff9575b8..d7f638f9b41 100644 --- a/board/starfive/visionfive2/MAINTAINERS +++ b/board/starfive/visionfive2/MAINTAINERS @@ -1,7 +1,8 @@ STARFIVE JH7110 VISIONFIVE2 BOARD -M: Yanhong Wang <yanhong.wang@starfivetech.com> +M: Minda Chen <minda.chen@starfivetech.com> S: Maintained F: arch/riscv/include/asm/arch-jh7110/ F: board/starfive/visionfive2/ F: include/configs/starfive-visionfive2.h F: configs/starfive_visionfive2_defconfig +F: drivers/pci/pcie_starfive_jh7110.c diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 2483a63c673..49719f2f553 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -133,7 +133,7 @@ void board_mem_get_layout(u64 *phys_sdram_1_start, struct tdx_user_fuses tdxramfuses; int scierr = sc_misc_otp_fuse_read(-1, 6, &val); - if (scierr) { + if (!scierr) { /* QP has one A72 core disabled */ is_quadplus = ((val >> 4) & 0x3) != 0x0; } diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index 2c673a4a6b0..6fc8076163c 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -46,7 +46,7 @@ static int is_imx8dx(void) u32 val = 0; int sc_err = sc_misc_otp_fuse_read(-1, 6, &val); - if (sc_err) { + if (!sc_err) { /* DX has two A35 cores disabled */ return (val & 0xf) != 0x0; } diff --git a/cmd/acpi.c b/cmd/acpi.c index 65caaa5c98e..928e5dc525e 100644 --- a/cmd/acpi.c +++ b/cmd/acpi.c @@ -32,7 +32,7 @@ static void dump_hdr(struct acpi_table_header *hdr) if (has_hdr) { printf(" v%02d %.6s %.8s %x %.4s %x\n", hdr->revision, hdr->oem_id, hdr->oem_table_id, hdr->oem_revision, - hdr->aslc_id, hdr->aslc_revision); + hdr->creator_id, hdr->creator_revision); } else { printf("\n"); } diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 9cf9027bf40..578dbb19a7e 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -154,9 +154,7 @@ static int do_bootefi(struct cmd_tbl *cmdtp, int flag, int argc, !strcmp(argv[1], "bootmgr")) { ret = efi_bootmgr_run(fdt); - if (ret == EFI_INVALID_PARAMETER) - return CMD_RET_USAGE; - else if (ret) + if (ret != EFI_SUCCESS) return CMD_RET_FAILURE; return CMD_RET_SUCCESS; @@ -173,9 +171,7 @@ static int do_bootefi(struct cmd_tbl *cmdtp, int flag, int argc, } ret = efi_install_fdt(fdt); - if (ret == EFI_INVALID_PARAMETER) - return CMD_RET_USAGE; - else if (ret != EFI_SUCCESS) + if (ret != EFI_SUCCESS) return CMD_RET_FAILURE; return do_efi_selftest(); @@ -218,9 +214,7 @@ static int do_bootefi(struct cmd_tbl *cmdtp, int flag, int argc, ret = efi_binary_run(image_buf, size, fdt); - if (ret == EFI_INVALID_PARAMETER) - return CMD_RET_USAGE; - else if (ret) + if (ret != EFI_SUCCESS) return CMD_RET_FAILURE; return CMD_RET_SUCCESS; diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index 9daf0e247ad..bd9d9c4765d 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -81,6 +81,7 @@ static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, break; switch (impl_id) { case 1: /* OpenSBI */ + case 8: /* PolarFire Hart Software Services */ printf("%ld.%ld", vers >> 16, vers & 0xffff); break; @@ -99,7 +100,7 @@ static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, } } if (i == ARRAY_SIZE(implementations)) - printf("Unknown implementation ID %ld", ret); + printf("\nUnknown implementation ID 0x%x", impl_id); } printf("\nMachine:\n"); ret = sbi_get_mvendorid(&mvendorid); diff --git a/cmd/smbios.c b/cmd/smbios.c index 66f6b761378..d3bd8b12a67 100644 --- a/cmd/smbios.c +++ b/cmd/smbios.c @@ -14,6 +14,18 @@ DECLARE_GLOBAL_DATA_PTR; +static const char * const wakeup_type_strings[] = { + "Reserved", /* 0x00 */ + "Other", /* 0x01 */ + "Unknown", /* 0x02 */ + "APM Timer", /* 0x03 */ + "Modem Ring", /* 0x04 */ + "Lan Remote", /* 0x05 */ + "Power Switch", /* 0x06 */ + "PCI PME#", /* 0x07 */ + "AC Power Restored", /* 0x08 */ +}; + /** * smbios_get_string() - get SMBIOS string from table * @@ -72,6 +84,14 @@ void smbios_print_str(const char *label, void *table, u8 index) printf("\t%s: %s\n", label, smbios_get_string(table, index)); } +const char *smbios_wakeup_type_str(u8 wakeup_type) +{ + if (wakeup_type >= ARRAY_SIZE(wakeup_type_strings)) + /* Values over 0x08 are reserved. */ + wakeup_type = 0; + return wakeup_type_strings[wakeup_type]; +} + static void smbios_print_type1(struct smbios_type1 *table) { printf("System Information\n"); @@ -81,11 +101,12 @@ static void smbios_print_type1(struct smbios_type1 *table) smbios_print_str("Serial Number", table, table->serial_number); if (table->length >= 0x19) { printf("\tUUID: %pUl\n", table->uuid); - smbios_print_str("Wake Up Type", table, table->serial_number); + printf("\tWake-up Type: %s\n", + smbios_wakeup_type_str(table->wakeup_type)); } if (table->length >= 0x1b) { - smbios_print_str("Serial Number", table, table->serial_number); smbios_print_str("SKU Number", table, table->sku_number); + smbios_print_str("Family", table, table->family); } } diff --git a/common/button_cmd.c b/common/button_cmd.c index b6a8434d6f2..8642c26735c 100644 --- a/common/button_cmd.c +++ b/common/button_cmd.c @@ -33,7 +33,7 @@ struct button_cmd { static int get_button_cmd(int n, struct button_cmd *cmd) { const char *cmd_str; - struct udevice *btn; + struct udevice *btn = NULL; char buf[24]; snprintf(buf, sizeof(buf), "button_cmd_%d_name", n); diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 872df0c0fe8..e5195d460c4 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -550,7 +550,12 @@ static void *spl_get_fit_load_buffer(size_t size) buf = malloc_cache_aligned(size); if (!buf) { pr_err("Could not get FIT buffer of %lu bytes\n", (ulong)size); - pr_err("\tcheck CONFIG_SPL_SYS_MALLOC_SIZE\n"); + + if (IS_ENABLED(CONFIG_SPL_SYS_MALLOC)) + pr_err("\tcheck CONFIG_SPL_SYS_MALLOC_SIZE\n"); + else + pr_err("\tcheck CONFIG_SPL_SYS_MALLOC_F_LEN\n"); + buf = spl_get_load_buffer(0, size); } return buf; diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig index 88784505c30..d9751bca666 100644 --- a/configs/am62x_beagleplay_a53_defconfig +++ b/configs/am62x_beagleplay_a53_defconfig @@ -88,9 +88,9 @@ CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y -CONFIG_PHY_FIXED=y CONFIG_TI_AM65_CPSW_NUSS=y CONFIG_PHY=y +CONFIG_DM_ETH_PHY=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 58eb4317857..0c6a272ddfc 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -98,10 +98,12 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_RN5T567=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y +CONFIG_IMX_WATCHDOG=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_WDT=y CONFIG_CI_UDC=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 3382371d40d..9d4423cd0d6 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -85,10 +85,12 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_RN5T567=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y +CONFIG_IMX_WATCHDOG=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_WDT=y CONFIG_CI_UDC=y diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 97507db2e99..cb6b97d097c 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3f0000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mm-venice" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-venice-gw71xx-0x" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MM_VENICE=y CONFIG_OF_LIBFDT_OVERLAY=y @@ -73,7 +73,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="imx8mm-venice imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901 imx8mm-venice-gw7902 imx8mm-venice-gw7903 imx8mm-venice-gw7904 imx8mm-venice-gw7905-0x" +CONFIG_OF_LIST="freescale/imx8mm-venice-gw71xx-0x freescale/imx8mm-venice-gw72xx-0x freescale/imx8mm-venice-gw73xx-0x freescale/imx8mm-venice-gw7901 freescale/imx8mm-venice-gw7902 freescale/imx8mm-venice-gw7903 freescale/imx8mm-venice-gw7904 freescale/imx8mm-venice-gw7905-0x" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_MMC_ENV_DEV=2 diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index dcf50350cdf..0a4fba5f1ca 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3f0000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mn-venice" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-venice-gw7902" CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_TARGET_IMX8MN_VENICE=y CONFIG_OF_LIBFDT_OVERLAY=y @@ -76,7 +76,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="imx8mn-venice imx8mn-venice-gw7902" +CONFIG_OF_LIST="freescale/imx8mn-venice-gw7902" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_MMC_ENV_DEV=2 diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index ecb08ca6bd0..6e4addc7728 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -8,10 +8,11 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3f0000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mp-venice" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-venice-gw71xx-2x" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_IMX8MP_VENICE=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y @@ -21,6 +22,7 @@ CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3f8000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_PCI=y CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_FIT=y @@ -63,6 +65,7 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CACHE=y @@ -75,7 +78,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="imx8mp-venice imx8mp-venice-gw71xx-2x imx8mp-venice-gw72xx-2x imx8mp-venice-gw73xx-2x imx8mp-venice-gw74xx imx8mp-venice-gw7905-2x" +CONFIG_OF_LIST="freescale/imx8mp-venice-gw71xx-2x freescale/imx8mp-venice-gw72xx-2x freescale/imx8mp-venice-gw73xx-2x freescale/imx8mp-venice-gw74xx freescale/imx8mp-venice-gw7905-2x" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_MMC_ENV_DEV=2 @@ -84,6 +87,8 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y CONFIG_GPIO_HOG=y @@ -112,7 +117,10 @@ CONFIG_FEC_MXC=y CONFIG_KSZ9477=y CONFIG_RGMII=y CONFIG_MII=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_IMX=y CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PHY_IMX8M_PCIE=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y diff --git a/configs/imx93-phyboard-segin_defconfig b/configs/imx93-phyboard-segin_defconfig index 24f9bd553aa..54215c51c08 100644 --- a/configs/imx93-phyboard-segin_defconfig +++ b/configs/imx93-phyboard-segin_defconfig @@ -67,6 +67,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y CONFIG_CMD_SNTP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y @@ -93,6 +94,12 @@ CONFIG_SPL_CLK_IMX93=y CONFIG_CLK_IMX93=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_GPIO_HOG=y CONFIG_IMX_RGPIO2P=y CONFIG_DM_I2C=y @@ -132,6 +139,13 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y CONFIG_ULP_WATCHDOG=y CONFIG_LZO=y CONFIG_BZIP2=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 743d090b935..0f2e83dfeec 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -10,6 +10,8 @@ CONFIG_SOC_K3_J721E=y CONFIG_TARGET_J7200_A72_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 +CONFIG_SF_DEFAULT_SPEED=25000000 +CONFIG_SF_DEFAULT_MODE=0 CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y @@ -60,7 +62,7 @@ CONFIG_SPL_RAM_DEVICE=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x300000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y @@ -139,7 +141,11 @@ CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y CONFIG_MULTIPLEXER=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index 8a238f4d2b5..d5b44e37f01 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -10,6 +10,8 @@ CONFIG_K3_EARLY_CONS=y CONFIG_TARGET_J7200_R5_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf5bfc +CONFIG_SF_DEFAULT_SPEED=25000000 +CONFIG_SF_DEFAULT_MODE=0 CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y @@ -60,7 +62,7 @@ CONFIG_SPL_REMOTEPROC=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_DFU=y @@ -116,7 +118,10 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y -CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index b3a7bbd79bb..6c67f14b555 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -19,14 +19,13 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x960000 CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x3e0000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="if test ${dofastboot} = 1; then fastboot 0; fi; mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 @@ -79,6 +78,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/sama7g54_curiosity_mmc_defconfig b/configs/sama7g54_curiosity_mmc_defconfig new file mode 100644 index 00000000000..fa3636828eb --- /dev/null +++ b/configs/sama7g54_curiosity_mmc_defconfig @@ -0,0 +1,123 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TEXT_BASE=0x66f00000 +CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_SYS_MALLOC_F_LEN=0x40000 +CONFIG_TARGET_SAMA7G54_CURIOSITY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60044000 +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama7g54_curiosity" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_SYS_LOAD_ADDR=0x62000000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x68000000 +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +# CONFIG_BOOTSTD is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_NAND_BOOT=y +CONFIG_QSPI_BOOT=y +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="fatload mmc 1:1 0x61000000 at91-sama7g54_curiosity.dtb; fatload mmc 1:1 0x62000000 zImage; bootz 0x62000000 - 0x61000000" +CONFIG_LOGLEVEL=6 +CONFIG_BOARD_TYPES=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEM_SEARCH=y +CONFIG_CMD_MX_CYCLIC=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_STRINGS=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_CMD_NAND_TORTURE=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_CAT=y +CONFIG_CMD_XXD=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_MTDPARTS_SPREAD=y +CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y +CONFIG_MTDIDS_DEFAULT="nand0=nand0,nor0=nor0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=nand0:256k(bootstrap-nand)ro,1M(u-boot-nand)ro,256k(env-nand)ro,512k(dtb-nand)ro,6M(kernel-nand)ro,-(rootfs-nand)ro;nor0:256k(bootstrap-nor)ro,1M(u-boot-nor)ro,256k(env-nor)ro,512k(dtb-nor)ro,6M(kernel-nor)ro" +CONFIG_OF_CONTROL=y +# CONFIG_OF_TAG_MIGRATE is not set +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="SAMA7G54" +CONFIG_VERSION_VARIABLE=y +# CONFIG_NET is not set +CONFIG_CLK=y +CONFIG_CLK_CCF=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_AT91_SAM9X60_PLL=y +CONFIG_CPU=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_AT91=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_ATMEL_EBI=y +CONFIG_MFD_ATMEL_SMC=y +CONFIG_I2C_EEPROM=y +CONFIG_MICROCHIP_FLEXCOM=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_NAND_ATMEL=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SST=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_RESET_AT91=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_AT91=y +CONFIG_TIMER=y +CONFIG_MCHP_PIT64B_TIMER=y +CONFIG_FAT_WRITE=y +CONFIG_CMD_DHRYSTONE=y +# CONFIG_EFI_LOADER is not set +CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/configs/sama7g54_curiosity_nandflash_defconfig b/configs/sama7g54_curiosity_nandflash_defconfig new file mode 100644 index 00000000000..331bb8d0fec --- /dev/null +++ b/configs/sama7g54_curiosity_nandflash_defconfig @@ -0,0 +1,122 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TEXT_BASE=0x66f00000 +CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_SYS_MALLOC_F_LEN=0x40000 +CONFIG_TARGET_SAMA7G54_CURIOSITY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60044000 +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama7g54_curiosity" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_SYS_LOAD_ADDR=0x62000000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x68000000 +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +# CONFIG_BOOTSTD is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_NAND_BOOT=y +CONFIG_QSPI_BOOT=y +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="nand read 0x61000000 0x180000 0x80000; nand read 0x62000000 0x200000 0x600000; bootz 0x62000000 - 0x61000000" +CONFIG_LOGLEVEL=6 +CONFIG_BOARD_TYPES=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEM_SEARCH=y +CONFIG_CMD_MX_CYCLIC=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_STRINGS=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_CMD_NAND_TORTURE=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_CAT=y +CONFIG_CMD_XXD=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_MTDPARTS_SPREAD=y +CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y +CONFIG_MTDIDS_DEFAULT="nand0=nand0,nor0=nor0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=nand0:256k(bootstrap-nand)ro,1M(u-boot-nand)ro,256k(env-nand)ro,512k(dtb-nand)ro,6M(kernel-nand)ro,-(rootfs-nand)ro;nor0:256k(bootstrap-nor)ro,1M(u-boot-nor)ro,256k(env-nor)ro,512k(dtb-nor)ro,6M(kernel-nor)ro" +CONFIG_OF_CONTROL=y +# CONFIG_OF_TAG_MIGRATE is not set +CONFIG_ENV_IS_IN_NAND=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="SAMA7G54" +CONFIG_VERSION_VARIABLE=y +# CONFIG_NET is not set +CONFIG_CLK=y +CONFIG_CLK_CCF=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_AT91_SAM9X60_PLL=y +CONFIG_CPU=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_AT91=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_ATMEL_EBI=y +CONFIG_MFD_ATMEL_SMC=y +CONFIG_I2C_EEPROM=y +CONFIG_MICROCHIP_FLEXCOM=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_NAND_ATMEL=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SST=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_RESET_AT91=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_AT91=y +CONFIG_TIMER=y +CONFIG_MCHP_PIT64B_TIMER=y +CONFIG_FAT_WRITE=y +CONFIG_CMD_DHRYSTONE=y +# CONFIG_EFI_LOADER is not set +CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/configs/sama7g54_curiosity_qspiflash_defconfig b/configs/sama7g54_curiosity_qspiflash_defconfig new file mode 100644 index 00000000000..00e5362a1fa --- /dev/null +++ b/configs/sama7g54_curiosity_qspiflash_defconfig @@ -0,0 +1,122 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TEXT_BASE=0x66f00000 +CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_SYS_MALLOC_F_LEN=0x40000 +CONFIG_TARGET_SAMA7G54_CURIOSITY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60044000 +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama7g54_curiosity" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_SYS_LOAD_ADDR=0x62000000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x68000000 +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +# CONFIG_BOOTSTD is not set +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_NAND_BOOT=y +CONFIG_QSPI_BOOT=y +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x61000000 0x180000 0x80000; sf read 0x62000000 0x200000 0x600000; bootz 0x62000000 - 0x61000000" +CONFIG_LOGLEVEL=6 +CONFIG_BOARD_TYPES=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEM_SEARCH=y +CONFIG_CMD_MX_CYCLIC=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_STRINGS=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_CMD_NAND_TORTURE=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_CAT=y +CONFIG_CMD_XXD=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_MTDPARTS_SPREAD=y +CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y +CONFIG_MTDIDS_DEFAULT="nand0=nand0,nor0=nor0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=nand0:256k(bootstrap-nand)ro,1M(u-boot-nand)ro,256k(env-nand)ro,512k(dtb-nand)ro,6M(kernel-nand)ro,-(rootfs-nand)ro;nor0:256k(bootstrap-nor)ro,1M(u-boot-nor)ro,256k(env-nor)ro,512k(dtb-nor)ro,6M(kernel-nor)ro" +CONFIG_OF_CONTROL=y +# CONFIG_OF_TAG_MIGRATE is not set +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="SAMA7G54" +CONFIG_VERSION_VARIABLE=y +# CONFIG_NET is not set +CONFIG_CLK=y +CONFIG_CLK_CCF=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_AT91_SAM9X60_PLL=y +CONFIG_CPU=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_AT91=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_ATMEL_EBI=y +CONFIG_MFD_ATMEL_SMC=y +CONFIG_I2C_EEPROM=y +CONFIG_MICROCHIP_FLEXCOM=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_NAND_ATMEL=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SST=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_RESET_AT91=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_AT91=y +CONFIG_TIMER=y +CONFIG_MCHP_PIT64B_TIMER=y +CONFIG_FAT_WRITE=y +CONFIG_CMD_DHRYSTONE=y +# CONFIG_EFI_LOADER is not set +CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 3be9a00a857..a62faf77248 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -11,6 +11,7 @@ CONFIG_SANDBOX64=y CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x00100000 CONFIG_SYS_MEMTEST_END=0x00101000 +CONFIG_BUTTON_CMD=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 4ad10363e91..93b52f2de5c 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -10,6 +10,7 @@ CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x00100000 CONFIG_SYS_MEMTEST_END=0x00101000 +CONFIG_BUTTON_CMD=y CONFIG_FIT=y CONFIG_FIT_RSASSA_PSS=y CONFIG_FIT_CIPHER=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 03901862752..6bf8874e722 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -8,6 +8,7 @@ CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x00100000 CONFIG_SYS_MEMTEST_END=0x00101000 +CONFIG_BUTTON_CMD=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig new file mode 100644 index 00000000000..f39954aea88 --- /dev/null +++ b/configs/socfpga_agilex5_defconfig @@ -0,0 +1,116 @@ +CONFIG_ARM=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000 +CONFIG_ARCH_SOCFPGA=y +CONFIG_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x04100000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk" +CONFIG_TARGET_SOCFPGA_AGILEX5_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex5" +CONFIG_SPL_FS_FAT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x82000000 +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe" +CONFIG_LEGACY_IMAGE_FORMAT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_CRC32=y +CONFIG_SPL_CACHE=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX5 # " +CONFIG_CMD_NVEDIT_SELECT=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_DOS_PARTITION=y +CONFIG_SPL_DOS_PARTITION=y +CONFIG_SPL_SYS_DISABLE_DCACHE_OPS=y +CONFIG_CMD_MTD=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_SPL_SPI_FLASH_MTD=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBIFS=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_LIST="" +CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_UBI_PART="root" +CONFIG_ENV_UBI_VOLUME="env" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_MISC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_UBI_SILENCE_MSG=y +CONFIG_DM_ETH=y +CONFIG_RGMII=y +CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_XHCI_HCD=y +CONFIG_UBIFS_SILENCE_MSG=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_WDT=y +CONFIG_CMD_WDT=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_SPL_WDT=y +CONFIG_WATCHDOG_AUTOSTART=n +CONFIG_TIMER=y +CONFIG_DESIGNWARE_APB_TIMER=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000 +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xbff00000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x7f000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xbfa00000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x500000 +CONFIG_SPL_BSS_MAX_SIZE=0x100000 +# CONFIG_EFI_LOADER is not set +CONFIG_I3C=y +CONFIG_DW_I3C_MASTER=y +CONFIG_CMD_I3C=y +CONFIG_SYS_MAXARGS=32 +CONFIG_CMD_TIMER=y +# CONFIG_BOOTFILE="Image" is not set for CONFIG_SPL_ATF=y +CONFIG_USE_BOOTFILE=y +CONFIG_BOOTFILE="kernel.itb" diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index c68f3c2def5..7a3f1d4dbdf 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -30,8 +30,8 @@ CONFIG_RISCV_SMODE=y # CONFIG_OF_BOARD_FIXUP is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y +CONFIG_BOOTSTD_DEFAULTS=y CONFIG_SYS_BOOTM_LEN=0x4000000 -CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTSTAGE=y CONFIG_QSPI_BOOT=y CONFIG_SD_BOOT=y diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig index a3febdcb694..5b4b81c925a 100644 --- a/configs/verdin-am62_r5_defconfig +++ b/configs/verdin-am62_r5_defconfig @@ -35,7 +35,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 7ac5e65642c..b6194404baa 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -16,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx8mp-verdin-wifi-dev" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_VERDIN_IMX8MP=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y @@ -26,6 +27,7 @@ CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x48200000 +CONFIG_PCI=y CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_REMAKE_ELF=y @@ -76,6 +78,7 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_READ=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y @@ -145,8 +148,11 @@ CONFIG_DWC_ETH_QOS_IMX=y CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_IMX=y CONFIG_PHY=y CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PHY_IMX8M_PCIE=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst index 1d641a78cf8..bc6d5246694 100644 --- a/doc/board/phytec/phycore-am62x.rst +++ b/doc/board/phytec/phycore-am62x.rst @@ -92,9 +92,9 @@ Assuming the uSD card is `/dev/mmcblk0`: To boot from a micro SD card on a HSFS device simply copy the following artifacts to the FAT partition: -* tiboot3.bin from R5 build as tiboot3.bin -* tispl.bin_unsigned from Cortex-A build as tispl.bin -* u-boot.img_unsigned from Cortex-A build as u-boot.img +* tiboot3.bin from R5 build +* tispl.bin from Cortex-A build +* u-boot.img from Cortex-A build Boot ---- diff --git a/doc/board/toradex/apalis-imx8.rst b/doc/board/toradex/apalis-imx8.rst index ffc4c7d222a..069d86ccd8c 100644 --- a/doc/board/toradex/apalis-imx8.rst +++ b/doc/board/toradex/apalis-imx8.rst @@ -20,36 +20,36 @@ Quick Start Get and Build the ARM Trusted Firmware -------------------------------------- +Download the imx-atf repository: + +.. code-block:: bash + + $ git clone -b lf_v2.6 https://github.com/nxp-imx/imx-atf.git + +Compile it with an aarch64 toolchain: + .. code-block:: bash - $ git clone -b imx_4.14.78_1.0.0_ga https://github.com/nxp-imx/imx-atf $ cd imx-atf/ $ make PLAT=imx8qm bl31 Get scfw_tcm.bin and ahab-container.img --------------------------------------- -.. code-block:: bash - - $ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes- - bsp/imx-sc-firmware/files/mx8qm-apalis-scfw-tcm.bin?raw=true - $ mv mx8qm-apalis-scfw-tcm.bin\?raw\=true mx8qm-apalis-scfw-tcm.bin - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin - $ chmod +x firmware-imx-8.0.bin - $ ./firmware-imx-8.0.bin - -Copy the following binaries to the U-Boot folder: +Download imx-seco firmware and extract it: .. code-block:: bash - $ cp imx-atf/build/imx8qm/release/bl31.bin . - $ cp u-boot/u-boot.bin . + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-5.8.7.bin + $ sh imx-seco-5.8.7.bin --auto-accept -Copy the following firmware to the U-Boot folder: +Copy the following binaries to the U-Boot folder: .. code-block:: bash - $ cp firmware-imx-8.0/firmware/seco/ahab-container.img . + $ wget https://github.com/toradex/i.MX-System-Controller-Firmware/raw/master/src/scfw_export_mx8qm_b0/build_mx8qm_b0/mx8qm-apalis-scfw-tcm.bin + $ cp ../imx-atf/build/imx8qm/release/bl31.bin . + $ cp ../imx-seco-5.8.7/firmware/seco/mx8qmb0-ahab-container.img mx8qm-ahab-container.img Build U-Boot ------------ @@ -64,7 +64,7 @@ Load the U-Boot Binary Using UUU Get the latest version of the universal update utility (uuu) aka ``mfgtools 3.0``: -https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases +https://github.com/nxp-imx/mfgtools/releases Put the module into USB recovery aka serial downloader mode, connect the USB device to your host and execute ``uuu``: diff --git a/doc/board/toradex/colibri-imx8x.rst b/doc/board/toradex/colibri-imx8x.rst index 9e61d98c6b1..378b259abd0 100644 --- a/doc/board/toradex/colibri-imx8x.rst +++ b/doc/board/toradex/colibri-imx8x.rst @@ -20,26 +20,35 @@ Quick Start Get and Build the ARM Trusted Firmware -------------------------------------- +Download the imx-atf repository: + +.. code-block:: bash + + $ git clone -b lf_v2.6 https://github.com/nxp-imx/imx-atf.git + +Compile it with an aarch64 toolchain: + .. code-block:: bash - $ git clone -b toradex_imx_5.4.70_2.3.0 http://git.toradex.com/cgit/imx-atf.git/ $ make PLAT=imx8qx bl31 -C imx-atf Get scfw_tcm.bin and ahab-container.img --------------------------------------- +Download imx-seco firmware and extract it: + .. code-block:: bash - $ wget https://github.com/toradex/i.MX-System-Controller-Firmware/raw/master/src/scfw_export_mx8qx_b0/build_mx8qx_b0/mx8qx-colibri-scfw-tcm.bin - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.8.1.bin - $ sh imx-seco-3.8.1.bin --auto-accept + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-5.8.7.bin + $ sh imx-seco-5.8.7.bin --auto-accept Copy the following firmware to the U-Boot folder: .. code-block:: bash - $ cp imx-atf/build/imx8qx/release/bl31.bin . - $ cp imx-seco-3.8.1/firmware/seco/mx8qxc0-ahab-container.img mx8qx-ahab-container.img + $ wget https://github.com/toradex/i.MX-System-Controller-Firmware/raw/master/src/scfw_export_mx8qx_b0/build_mx8qx_b0/mx8qx-colibri-scfw-tcm.bin + $ cp ../imx-atf/build/imx8qx/release/bl31.bin . + $ cp ../imx-seco-5.8.7/firmware/seco/mx8qxc0-ahab-container.img mx8qx-ahab-container.img Build U-Boot ------------ @@ -54,7 +63,7 @@ Load the U-Boot Binary Using UUU Get the latest version of the universal update utility (uuu) aka ``mfgtools 3.0``: -https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases +https://github.com/nxp-imx/mfgtools/releases Put the module into USB recovery aka serial downloader mode, connect the USB device to your host and execute ``uuu``: diff --git a/doc/develop/commands.rst b/doc/develop/commands.rst index ede880d248c..5ad4e59c838 100644 --- a/doc/develop/commands.rst +++ b/doc/develop/commands.rst @@ -88,7 +88,7 @@ The command function pointer has to be of type .. code-block:: c - int (*cmd)(struct cmd_tbl *cmdtp, int flag, int argc, const char *argv[]); + int (*cmd)(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); cmdtp Table entry describing the command (see above). diff --git a/doc/develop/devicetree/control.rst b/doc/develop/devicetree/control.rst index c94d84192b7..4cc1457d4ea 100644 --- a/doc/develop/devicetree/control.rst +++ b/doc/develop/devicetree/control.rst @@ -36,10 +36,10 @@ What is a Flattened Devicetree? ------------------------------- An fdt can be specified in source format as a text file. To read about -the fdt syntax, take a look at the specification (dtspec_). +the fdt syntax, take a look at `the devicetree specification`_. -There is also a mailing list (dtlist_) for the compiler and associated -tools. +There is also a `devicetree compiler mailing list`_ for the compiler and +associated tools. In case you are wondering, OF stands for Open Firmware. This follows the convention used in Linux. @@ -89,7 +89,7 @@ Failing that, you could write one from scratch yourself! Resyncing with devicetree-rebasing ---------------------------------- -The devicetee-rebasing repository (dtrepo_) maintains a fork cum mirror copy of +The `devicetree-rebasing repository`_ maintains a fork cum mirror copy of devicetree files along with the bindings synced at every Linux kernel major release or intermediate release candidates. The U-Boot maintainers regularly sync the `dts/upstream/` subtree from the devicetree-rebasing repo whenever @@ -118,7 +118,7 @@ as `arch/<arch>/dts/<name>.dts`. To select that add `# CONFIG_OF_UPSTREAM is not set` and set `DEFAULT_DEVICE_TREE=<name>` when prompted by Kconfig. This should include your CPU or SoC's devicetree file. On top of that any U-Boot -specific tweaks (see: dttweaks_) can be made for your board. +specific tweaks (see: :ref:`dttweaks`) can be made for your board. If `OF_EMBED` is selected by Kconfig, then it will be picked up and built into the U-Boot image (including u-boot.bin). This is suitable for debugging @@ -243,7 +243,7 @@ Dependencies The DT schema project must be installed in order to validate the DT schema binding documents and validate DTS files using the DT schema. For installation -instructions, refer to the DT schema project page (dtschema_). +instructions, refer to the `DT schema project page`_. Several executables (dt-doc-validate, dt-mk-schema, dt-validate) will be installed. Ensure they are in your PATH (~/.local/bin by default). @@ -333,10 +333,10 @@ used it before Linux (e.g. snow). The two projects developed in parallel and there are still some differences in the bindings for certain boards. While there has been discussion of having a separate repository for devicetree files, in practice the Linux kernel Git repository has become the place where -these are stored, with U-Boot taking copies via devicetree-rebasing repo -(see: dtrepo_) and adding tweaks with u-boot.dtsi files. +these are stored, with U-Boot taking copies via +`devicetree-rebasing repository`_ and adding tweaks with u-boot.dtsi files. -.. _dtspec: https://www.devicetree.org/specifications/ -.. _dtlist: https://www.spinics.net/lists/devicetree-compiler/ -.. _dtrepo: https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git -.. _dtschema: https://github.com/devicetree-org/dt-schema/tree/main +.. _the devicetree specification: https://www.devicetree.org/specifications/ +.. _devicetree compiler mailing list: https://www.spinics.net/lists/devicetree-compiler/ +.. _devicetree-rebasing repository: https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git +.. _DT schema project page: https://github.com/devicetree-org/dt-schema/tree/main diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index db936a8b48e..7cfc2012c42 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -64,15 +64,15 @@ Future Releases For the next scheduled release, release candidates were made on:: -* U-Boot v2024.01-rc1 was released on Mon 29 January 2024. +* U-Boot v2024.04-rc1 was released on Mon 29 January 2024. -* U-Boot v2024.01-rc2 was released on Tue 13 February 2024. +* U-Boot v2024.04-rc2 was released on Tue 13 February 2024. -* U-Boot v2024.01-rc3 was released on Mon 26 February 2024. +* U-Boot v2024.04-rc3 was released on Mon 26 February 2024. -* U-Boot v2024.01-rc4 was released on Mon 11 March 2024. +* U-Boot v2024.04-rc4 was released on Mon 11 March 2024. -.. * U-Boot v2024.01-rc5 was released on Mon 25 March 2024. +* U-Boot v2024.04-rc5 was released on Mon 25 March 2024. Please note that the following dates are planned only and may be deviated from as needed. diff --git a/doc/device-tree-bindings/misc/socfpga_dtreg.txt b/doc/device-tree-bindings/misc/socfpga_dtreg.txt new file mode 100644 index 00000000000..cf40fdd2da8 --- /dev/null +++ b/doc/device-tree-bindings/misc/socfpga_dtreg.txt @@ -0,0 +1,80 @@ +* Firewall and privilege register settings in device tree + +Required properties: +-------------------- + +- compatible: should contain "intel,socfpga-dtreg" +- reg: Physical base address and size of block register. +- intel,offset-settings: 32-bit offset address of block register, + followed by 32-bit value settings and + the masking bits, only masking bit + set to 1 allows modification. + +The device tree node which describes secure and privilege register access +configuration in compile time. + +Most of these registers are expected to work except for the case which some +registers configuration are required for granting access to some other +registers, for example CCU registers have to be properly configured before +allowing register configuration access to fpga2sdram firewall as shown in +below example. + +Some registers depend on runtime data for proper configuration are expected +to be part of driver that generating these data for example configuration for +soc_noc_fw_ddr_mpu_inst_0_ddr_scr block register depend on DDR size parsed from +memory device tree node. + +Please refer details of tested examples below for both fpga2sdram and QoS +configuration with default reset value and the comments. + +Example: +-------- + +Configuration for multiple dtreg node support in device tree: + + socfpga_dtreg0: socfpga-dtreg0 { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 { + reg = <0xf7100200 0x00000014>; + intel,offset-settings = + /* + * Disable ocram security at CCU for + * non secure access + */ + <0x0000004 0x8000ffff 0xe007ffff>, + <0x0000008 0x8000ffff 0xe007ffff>, + <0x000000c 0x8000ffff 0xe007ffff>, + <0x0000010 0x8000ffff 0xe007ffff>; + bootph-all; + }; + }; + + socfpga_dtreg1: socfpga-dtreg1 { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { + reg = <0xf8020000 0x0000001c>; + intel,offset-settings = + /* Disable MPFE firewall for SMMU */ + <0x00000000 0x00010101 0x00010101>, + /* + * Disable MPFE firewall for HMC + * adapter + */ + <0x00000004 0x00000001 0x00010101>; + bootph-all; + }; + }; + +To call the nodes use: + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-dtreg0", &dev); + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-dtreg1", &dev); + diff --git a/doc/sphinx/cdomain.py b/doc/sphinx/cdomain.py index 014a5229e57..491a7ed5f47 100644 --- a/doc/sphinx/cdomain.py +++ b/doc/sphinx/cdomain.py @@ -93,7 +93,7 @@ def markup_ctype_refs(match): # RE_expr = re.compile(r':c:(expr|texpr):`([^\`]+)`') def markup_c_expr(match): - return '\ ``' + match.group(2) + '``\ ' + return '\\ ``' + match.group(2) + '``\\ ' # # Parse Sphinx 3.x C markups, replacing them by backward-compatible ones diff --git a/doc/sphinx/kernel_abi.py b/doc/sphinx/kernel_abi.py index f3da859c987..32c50e496b5 100644 --- a/doc/sphinx/kernel_abi.py +++ b/doc/sphinx/kernel_abi.py @@ -147,7 +147,7 @@ class KernelCmd(Directive): code_block += "\n " + l lines = code_block + "\n\n" - line_regex = re.compile("^#define LINENO (\S+)\#([0-9]+)$") + line_regex = re.compile(r"^#define LINENO (\S+)\#([0-9]+)$") ln = 0 n = 0 f = fname diff --git a/doc/sphinx/kerneldoc.py b/doc/sphinx/kerneldoc.py index 01a55429c57..bc8bb9e5125 100644 --- a/doc/sphinx/kerneldoc.py +++ b/doc/sphinx/kerneldoc.py @@ -130,7 +130,7 @@ class KernelDocDirective(Directive): result = ViewList() lineoffset = 0; - line_regex = re.compile("^#define LINENO ([0-9]+)$") + line_regex = re.compile(r"^#define LINENO ([0-9]+)$") for line in lines: match = line_regex.search(line) if match: diff --git a/doc/sphinx/maintainers_include.py b/doc/sphinx/maintainers_include.py index dc8fed48d3c..13557d3d3c2 100755 --- a/doc/sphinx/maintainers_include.py +++ b/doc/sphinx/maintainers_include.py @@ -78,8 +78,8 @@ class MaintainersInclude(Include): # Drop needless input whitespace. line = line.rstrip() - # Linkify all non-wildcard refs to ReST files in Documentation/. - pat = '(Documentation/([^\s\?\*]*)\.rst)' + # Linkify all non-wildcard refs to ReST files in doc/. + pat = r'(doc/([^\s\?\*]*)\.rst)' m = re.search(pat, line) if m: # maintainers.rst is in a subdirectory, so include "../". @@ -92,11 +92,11 @@ class MaintainersInclude(Include): output = "| %s" % (line.replace("\\", "\\\\")) # Look for and record field letter to field name mappings: # R: Designated *reviewer*: FullName <address@domain> - m = re.search("\s(\S):\s", line) + m = re.search(r"\s(\S):\s", line) if m: field_letter = m.group(1) if field_letter and not field_letter in fields: - m = re.search("\*([^\*]+)\*", line) + m = re.search(r"\*([^\*]+)\*", line) if m: fields[field_letter] = m.group(1) elif subsystems: @@ -114,7 +114,7 @@ class MaintainersInclude(Include): field_content = "" # Collapse whitespace in subsystem name. - heading = re.sub("\s+", " ", line) + heading = re.sub(r"\s+", " ", line) output = output + "%s\n%s" % (heading, "~" * len(heading)) field_prev = "" else: @@ -177,11 +177,11 @@ class MaintainersInclude(Include): if not self.state.document.settings.file_insertion_enabled: raise self.warning('"%s" directive disabled.' % self.name) - # Walk up source path directories to find Documentation/../ + # Walk up source path directories to find doc/../ path = self.state_machine.document.attributes['source'] path = os.path.realpath(path) tail = path - while tail != "Documentation" and tail != "": + while tail != "doc" and tail != "": (path, tail) = os.path.split(path) # Append "MAINTAINERS" diff --git a/doc/usage/cmd/acpi.rst b/doc/usage/cmd/acpi.rst index a630f1ec5e3..9f30972fe53 100644 --- a/doc/usage/cmd/acpi.rst +++ b/doc/usage/cmd/acpi.rst @@ -6,8 +6,8 @@ acpi command ============ -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/bootdev.rst b/doc/usage/cmd/bootdev.rst index 658020e7c7f..f759abab354 100644 --- a/doc/usage/cmd/bootdev.rst +++ b/doc/usage/cmd/bootdev.rst @@ -6,8 +6,8 @@ bootdev command =============== -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/bootflow.rst b/doc/usage/cmd/bootflow.rst index 16ba986dc8a..6519e4880a9 100644 --- a/doc/usage/cmd/bootflow.rst +++ b/doc/usage/cmd/bootflow.rst @@ -6,8 +6,8 @@ bootflow command ================ -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/bootmeth.rst b/doc/usage/cmd/bootmeth.rst index 95651fdc7c5..2903977ee54 100644 --- a/doc/usage/cmd/bootmeth.rst +++ b/doc/usage/cmd/bootmeth.rst @@ -6,8 +6,8 @@ bootmeth command ================ -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/cbsysinfo.rst b/doc/usage/cmd/cbsysinfo.rst index 8c03a85169d..80d8ba1b662 100644 --- a/doc/usage/cmd/cbsysinfo.rst +++ b/doc/usage/cmd/cbsysinfo.rst @@ -3,8 +3,8 @@ cbsysinfo ========= -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/cedit.rst b/doc/usage/cmd/cedit.rst index b39d708281d..5670805a00e 100644 --- a/doc/usage/cmd/cedit.rst +++ b/doc/usage/cmd/cedit.rst @@ -6,8 +6,8 @@ cedit command ============= -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/cli.rst b/doc/usage/cmd/cli.rst index 81487722f69..23e5ee7a902 100644 --- a/doc/usage/cmd/cli.rst +++ b/doc/usage/cmd/cli.rst @@ -6,8 +6,8 @@ cli command =========== -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/dm.rst b/doc/usage/cmd/dm.rst index 9bef2eeaed8..7651507937a 100644 --- a/doc/usage/cmd/dm.rst +++ b/doc/usage/cmd/dm.rst @@ -6,8 +6,8 @@ dm command ========== -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/env.rst b/doc/usage/cmd/env.rst index a859e32798c..a7e21693a67 100644 --- a/doc/usage/cmd/env.rst +++ b/doc/usage/cmd/env.rst @@ -350,7 +350,7 @@ edit exists CONFIG_CMD_ENV_EXISTS -flsgs +flags CONFIG_CMD_ENV_FLAGS erase diff --git a/doc/usage/cmd/fdt.rst b/doc/usage/cmd/fdt.rst index 3e8c32cdea3..71a9fc627e5 100644 --- a/doc/usage/cmd/fdt.rst +++ b/doc/usage/cmd/fdt.rst @@ -6,8 +6,8 @@ fdt command =========== -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/font.rst b/doc/usage/cmd/font.rst index adcd5126d0a..a8782546333 100644 --- a/doc/usage/cmd/font.rst +++ b/doc/usage/cmd/font.rst @@ -6,8 +6,8 @@ font command ============ -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/for.rst b/doc/usage/cmd/for.rst index 4c98419b28f..729bd4db43c 100644 --- a/doc/usage/cmd/for.rst +++ b/doc/usage/cmd/for.rst @@ -4,8 +4,8 @@ for command =========== -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/history.rst b/doc/usage/cmd/history.rst index 564a1596655..b52b5b220ae 100644 --- a/doc/usage/cmd/history.rst +++ b/doc/usage/cmd/history.rst @@ -6,8 +6,8 @@ history command =============== -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/host.rst b/doc/usage/cmd/host.rst index 072497db903..a70a432b6f2 100644 --- a/doc/usage/cmd/host.rst +++ b/doc/usage/cmd/host.rst @@ -6,8 +6,8 @@ host command ============ -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/if.rst b/doc/usage/cmd/if.rst new file mode 100644 index 00000000000..6b3dbe7b0a0 --- /dev/null +++ b/doc/usage/cmd/if.rst @@ -0,0 +1,72 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +.. index:: + single: if (command) + +if command +========== + +Synopsis +-------- + +:: + + if <test statement> + then + <statements> + fi + + if <test statement> + then + <statements> + else + <statements> + fi + +Description +----------- + +The if command is used to conditionally execute statements. + +test statement + Any command. The test statement set the $? variable. If the value of + $? becomes 0 (true) the statements after the **then** statement will + be executed. Otherwise the statements after the **else** statement. + +Example +------- + +The examples shows how the value of a numeric variable can be tested with +**itest**. + +:: + + => a=1; if itest $a == 0; then echo true; else echo false; fi + false + => a=0; if itest $a == 0; then echo true; else echo false; fi + true + +In the following example we try to load an EFI binary via TFTP. If loading +succeeds, the binary is executed. + +:: + + if tftp $kernel_addr_r shellriscv64.efi; then bootefi $kernel_addr_r; fi + +Return value +------------ + +The value of $? is the return value of the last executed statement. + +:: + + => if true; then true; else true; fi; echo $? + 0 + => if false; then true; else true; fi; echo $? + 0 + => if false; then false; else false; fi; echo $? + 1 + => if true; then false; else false; fi; echo $? + 1 + => if false; then true; fi; echo $? + 1 diff --git a/doc/usage/cmd/md.rst b/doc/usage/cmd/md.rst index 9ea148a8dca..9a9919f9ad0 100644 --- a/doc/usage/cmd/md.rst +++ b/doc/usage/cmd/md.rst @@ -6,8 +6,8 @@ md command ========== -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/mtrr.rst b/doc/usage/cmd/mtrr.rst index c65618950bc..3c5c3ba3d43 100644 --- a/doc/usage/cmd/mtrr.rst +++ b/doc/usage/cmd/mtrr.rst @@ -6,8 +6,8 @@ mtrr command ============ -Synopis -------- +Synopsis +-------- mtrr [list] mtrr set <reg> <type> <start> <size> diff --git a/doc/usage/cmd/panic.rst b/doc/usage/cmd/panic.rst index ba5ea626108..39d32adbc99 100644 --- a/doc/usage/cmd/panic.rst +++ b/doc/usage/cmd/panic.rst @@ -6,8 +6,8 @@ panic command ============= -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/part.rst b/doc/usage/cmd/part.rst index 58be38781e3..e7faeccbb09 100644 --- a/doc/usage/cmd/part.rst +++ b/doc/usage/cmd/part.rst @@ -6,8 +6,8 @@ part command ============ -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/sf.rst b/doc/usage/cmd/sf.rst index 24d5dc692db..dfdca46e66c 100644 --- a/doc/usage/cmd/sf.rst +++ b/doc/usage/cmd/sf.rst @@ -6,8 +6,8 @@ sf command ========== -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/sm.rst b/doc/usage/cmd/sm.rst index b767647d772..e828fddc519 100644 --- a/doc/usage/cmd/sm.rst +++ b/doc/usage/cmd/sm.rst @@ -6,8 +6,8 @@ sm command ========== -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/trace.rst b/doc/usage/cmd/trace.rst index ad6db123942..e798b2bbc6b 100644 --- a/doc/usage/cmd/trace.rst +++ b/doc/usage/cmd/trace.rst @@ -6,8 +6,8 @@ trace command ============= -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/cmd/ut.rst b/doc/usage/cmd/ut.rst index ddc48ec42dd..45bc9ffbdc5 100644 --- a/doc/usage/cmd/ut.rst +++ b/doc/usage/cmd/ut.rst @@ -6,8 +6,8 @@ ut command ========== -Synopis -------- +Synopsis +-------- :: diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 0d174eefaa5..66d73e70cc4 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -71,6 +71,7 @@ Shell commands cmd/gpt cmd/history cmd/host + cmd/if cmd/imxtract cmd/load cmd/loadb diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index 33db092918a..61ffa4179a0 100644 --- a/drivers/clk/altera/Makefile +++ b/drivers/clk/altera/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o +obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += clk-agilex5.o diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c new file mode 100644 index 00000000000..92f2abdaf93 --- /dev/null +++ b/drivers/clk/altera/clk-agilex5.c @@ -0,0 +1,745 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ + +#include <clk-uclass.h> +#include <config.h> +#include <errno.h> +#include <dm.h> +#include <log.h> +#include <stdarg.h> +#include <stdio.h> +#include <time.h> +#include <vsprintf.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/system.h> +#include <asm/u-boot.h> +#include <dm/lists.h> +#include <dm/util.h> +#include <linux/bitops.h> +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/types.h> +#include <asm/arch/clock_manager.h> +#include <dt-bindings/clock/agilex5-clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct socfpga_clk_plat { + void __iomem *regs; +}; + +/* + * function to write the bypass register which requires a poll of the + * busy bit + */ +static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val) +{ + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS); + cm_wait_for_fsm(); +} + +static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val) +{ + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS); + cm_wait_for_fsm(); +} + +/* function to write the ctrl register which requires a poll of the busy bit */ +static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val) +{ + CM_REG_WRITEL(plat, val, CLKMGR_CTRL); + cm_wait_for_fsm(); +} + +static const struct { + u32 reg; + u32 val; + u32 mask; +} membus_pll[] = { + { + MEMBUS_CLKSLICE_REG, + /* + * BIT[7:7] + * Enable source synchronous mode + */ + BIT(7), + BIT(7) + }, + { + MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG, + /* + * BIT[0:0] + * Sets synthcalfosc_init_centerfreq=1 to limit overshoot + * frequency during lock + */ + BIT(0), + BIT(0) + }, + { + MEMBUS_SYNTHPPM_WATCHDOGTMR_VF01_REG, + /* + * BIT[0:0] + * Sets synthppm_watchdogtmr_vf0=1 to give the pll more time + * to settle before lock is asserted. + */ + BIT(0), + BIT(0) + }, + { + MEMBUS_CALCLKSLICE0_DUTY_LOCOVR_REG, + /* + * BIT[6:0] + * Centering duty cycle for clkslice0 output + */ + 0x4a, + GENMASK(6, 0) + }, + { + MEMBUS_CALCLKSLICE1_DUTY_LOCOVR_REG, + /* + * BIT[6:0] + * Centering duty cycle for clkslice1 output + */ + 0x4a, + GENMASK(6, 0) + }, +}; + +static int membus_wait_for_req(struct socfpga_clk_plat *plat, u32 pll, + int timeout) +{ + int cnt = 0; + u32 req_status; + + if (pll == MEMBUS_MAINPLL) + req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM); + else + req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM); + + while ((cnt < timeout) && (req_status & CLKMGR_MEM_REQ_SET_MSK)) { + if (pll == MEMBUS_MAINPLL) + req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM); + else + req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM); + cnt++; + } + + if (cnt >= timeout) + return -ETIMEDOUT; + + return 0; +} + +static int membus_write_pll(struct socfpga_clk_plat *plat, u32 pll, + u32 addr_offset, u32 wdat, int timeout) +{ + u32 addr; + u32 val; + + addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK); + + val = (CLKMGR_MEM_REQ_SET_MSK | CLKMGR_MEM_WR_SET_MSK | + (wdat << CLKMGR_MEM_WDAT_LSB_OFFSET) | addr); + + if (pll == MEMBUS_MAINPLL) + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM); + else + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM); + + debug("MEMBUS: Write 0x%08x to addr = 0x%08x\n", wdat, addr); + + return membus_wait_for_req(plat, pll, timeout); +} + +static int membus_read_pll(struct socfpga_clk_plat *plat, u32 pll, + u32 addr_offset, u32 *rdata, int timeout) +{ + u32 addr; + u32 val; + + addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK); + + val = ((CLKMGR_MEM_REQ_SET_MSK & ~CLKMGR_MEM_WR_SET_MSK) | addr); + + if (pll == MEMBUS_MAINPLL) + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM); + else + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM); + + *rdata = 0; + + if (membus_wait_for_req(plat, pll, timeout)) + return -ETIMEDOUT; + + if (pll == MEMBUS_MAINPLL) + *rdata = CM_REG_READL(plat, CLKMGR_MAINPLL_MEMSTAT); + else + *rdata = CM_REG_READL(plat, CLKMGR_PERPLL_MEMSTAT); + + debug("MEMBUS: Read 0x%08x from addr = 0x%08x\n", *rdata, addr); + + return 0; +} + +static void membus_pll_configs(struct socfpga_clk_plat *plat, u32 pll) +{ + int i; + u32 rdata; + + for (i = 0; i < ARRAY_SIZE(membus_pll); i++) { + membus_read_pll(plat, pll, membus_pll[i].reg, + &rdata, MEMBUS_TIMEOUT); + membus_write_pll(plat, pll, membus_pll[i].reg, + ((rdata & ~membus_pll[i].mask) | + membus_pll[i].val), + MEMBUS_TIMEOUT); + } +} + +static u32 calc_vocalib_pll(u32 pllm, u32 pllglob) +{ + u32 mdiv, refclkdiv, arefclkdiv, drefclkdiv, mscnt, hscnt, vcocalib; + + mdiv = pllm & CLKMGR_PLLM_MDIV_MASK; + arefclkdiv = (pllglob & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >> + CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET; + drefclkdiv = (pllglob & CLKMGR_PLLGLOB_DREFCLKDIV_MASK) >> + CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET; + refclkdiv = (pllglob & CLKMGR_PLLGLOB_REFCLKDIV_MASK) >> + CLKMGR_PLLGLOB_REFCLKDIV_OFFSET; + mscnt = CLKMGR_VCOCALIB_MSCNT_CONST / (mdiv * BIT(drefclkdiv)); + if (!mscnt) + mscnt = 1; + hscnt = (mdiv * mscnt * BIT(drefclkdiv) / refclkdiv) - + CLKMGR_VCOCALIB_HSCNT_CONST; + vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) | + ((mscnt << CLKMGR_VCOCALIB_MSCNT_OFFSET) & + CLKMGR_VCOCALIB_MSCNT_MASK); + + /* Dump all the pll calibration settings for debug purposes */ + debug("mdiv : %d\n", mdiv); + debug("arefclkdiv : %d\n", arefclkdiv); + debug("drefclkdiv : %d\n", drefclkdiv); + debug("refclkdiv : %d\n", refclkdiv); + debug("mscnt : %d\n", mscnt); + debug("hscnt : %d\n", hscnt); + debug("vcocalib : 0x%08x\n", vcocalib); + + return vcocalib; +} + +/* + * Setup clocks while making no assumptions about previous state of the clocks. + */ +static void clk_basic_init(struct udevice *dev, + const struct cm_config * const cfg) +{ + struct socfpga_clk_plat *plat = dev_get_plat(dev); + u32 vcocalib; + + if (!cfg) + return; + + if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU)) { + /* Take both PLL out of reset and power up */ + CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + + cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK); + + /* Put both PLLs in bypass */ + clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL); + clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL); + + /* Take all PLLs out of bypass */ + clk_write_bypass_mainpll(plat, 0); + clk_write_bypass_perpll(plat, 0); + + /* Out of boot mode */ + clk_write_ctrl(plat, + CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE); + } else { +#ifdef CONFIG_SPL_BUILD + /* Always force clock manager into boot mode before any configuration */ + clk_write_ctrl(plat, + CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE); +#else + /* Skip clock configuration in SSBL if it's not in boot mode */ + if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE)) + return; +#endif + + /* Put both PLLs in bypass */ + clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL); + clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL); + + /* Put both PLLs in Reset and Power Down */ + CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + + /* setup main PLL dividers where calculate the vcocalib value */ + vcocalib = calc_vocalib_pll(cfg->main_pll_pllm, cfg->main_pll_pllglob); + CM_REG_WRITEL(plat, cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK, + CLKMGR_MAINPLL_PLLGLOB); + CM_REG_WRITEL(plat, cfg->main_pll_fdbck, CLKMGR_MAINPLL_FDBCK); + CM_REG_WRITEL(plat, vcocalib, CLKMGR_MAINPLL_VCOCALIB); + CM_REG_WRITEL(plat, cfg->main_pll_pllc0, CLKMGR_MAINPLL_PLLC0); + CM_REG_WRITEL(plat, cfg->main_pll_pllc1, CLKMGR_MAINPLL_PLLC1); + CM_REG_WRITEL(plat, cfg->main_pll_pllc2, CLKMGR_MAINPLL_PLLC2); + CM_REG_WRITEL(plat, cfg->main_pll_pllc3, CLKMGR_MAINPLL_PLLC3); + CM_REG_WRITEL(plat, cfg->main_pll_pllm, CLKMGR_MAINPLL_PLLM); + CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK); + CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV); + + /* setup peripheral PLL dividers where calculate the vcocalib value */ + vcocalib = calc_vocalib_pll(cfg->per_pll_pllm, cfg->per_pll_pllglob); + CM_REG_WRITEL(plat, cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK, + CLKMGR_PERPLL_PLLGLOB); + CM_REG_WRITEL(plat, cfg->per_pll_fdbck, CLKMGR_PERPLL_FDBCK); + CM_REG_WRITEL(plat, vcocalib, CLKMGR_PERPLL_VCOCALIB); + CM_REG_WRITEL(plat, cfg->per_pll_pllc0, CLKMGR_PERPLL_PLLC0); + CM_REG_WRITEL(plat, cfg->per_pll_pllc1, CLKMGR_PERPLL_PLLC1); + CM_REG_WRITEL(plat, cfg->per_pll_pllc2, CLKMGR_PERPLL_PLLC2); + CM_REG_WRITEL(plat, cfg->per_pll_pllc3, CLKMGR_PERPLL_PLLC3); + CM_REG_WRITEL(plat, cfg->per_pll_pllm, CLKMGR_PERPLL_PLLM); + CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL); + CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV); + + /* Configure ping pong counters in control group */ + CM_REG_WRITEL(plat, cfg->ctl_emacactr, CLKMGR_CTL_EMACACTR); + CM_REG_WRITEL(plat, cfg->ctl_emacbctr, CLKMGR_CTL_EMACBCTR); + CM_REG_WRITEL(plat, cfg->ctl_emacptpctr, CLKMGR_CTL_EMACPTPCTR); + CM_REG_WRITEL(plat, cfg->ctl_gpiodbctr, CLKMGR_CTL_GPIODBCTR); + CM_REG_WRITEL(plat, cfg->ctl_s2fuser0ctr, CLKMGR_CTL_S2FUSER0CTR); + CM_REG_WRITEL(plat, cfg->ctl_s2fuser1ctr, CLKMGR_CTL_S2FUSER1CTR); + CM_REG_WRITEL(plat, cfg->ctl_psirefctr, CLKMGR_CTL_PSIREFCTR); + CM_REG_WRITEL(plat, cfg->ctl_usb31ctr, CLKMGR_CTL_USB31CTR); + CM_REG_WRITEL(plat, cfg->ctl_dsuctr, CLKMGR_CTL_DSUCTR); + CM_REG_WRITEL(plat, cfg->ctl_core01ctr, CLKMGR_CTL_CORE01CTR); + CM_REG_WRITEL(plat, cfg->ctl_core23ctr, CLKMGR_CTL_CORE23CTR); + CM_REG_WRITEL(plat, cfg->ctl_core2ctr, CLKMGR_CTL_CORE2CTR); + CM_REG_WRITEL(plat, cfg->ctl_core3ctr, CLKMGR_CTL_CORE3CTR); + + /* Take both PLL out of reset and power up */ + CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + + /* Membus programming for mainpll */ + membus_pll_configs(plat, MEMBUS_MAINPLL); + /* Membus programming for peripll */ + membus_pll_configs(plat, MEMBUS_PERPLL); + + /* Enable Main pll clkslices */ + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC0) | + CLKMGR_PLLCX_EN_SET_MSK, + CLKMGR_MAINPLL_PLLC0); + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC1) | + CLKMGR_PLLCX_EN_SET_MSK, + CLKMGR_MAINPLL_PLLC1); + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC2) | + CLKMGR_PLLCX_EN_SET_MSK, + CLKMGR_MAINPLL_PLLC2); + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC3) | + CLKMGR_PLLCX_EN_SET_MSK, + CLKMGR_MAINPLL_PLLC3); + + /* Enable Periph pll clkslices */ + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLC0) | + CLKMGR_PLLCX_EN_SET_MSK, + CLKMGR_PERPLL_PLLC0); + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLC1) | + CLKMGR_PLLCX_EN_SET_MSK, + CLKMGR_PERPLL_PLLC1); + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLC2) | + CLKMGR_PLLCX_EN_SET_MSK, + CLKMGR_PERPLL_PLLC2); + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLC3) | + CLKMGR_PLLCX_EN_SET_MSK, + CLKMGR_PERPLL_PLLC3); + + cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK); + + CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK); + CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK); + + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) | + CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK, + CLKMGR_MAINPLL_PLLGLOB); + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) | + CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK, + CLKMGR_PERPLL_PLLGLOB); + + /* Take all PLLs out of bypass */ + clk_write_bypass_mainpll(plat, 0); + clk_write_bypass_perpll(plat, 0); + + /* Clear the loss of lock bits (write 1 to clear) */ + CM_REG_CLRBITS(plat, CLKMGR_INTRCLR, + CLKMGR_INTER_PERPLLLOST_MASK | + CLKMGR_INTER_MAINPLLLOST_MASK); + + /* Take all ping pong counters out of reset */ + CM_REG_CLRBITS(plat, CLKMGR_CTL_EXTCNTRST, + CLKMGR_CTL_EXTCNTRST_ALLCNTRST); + +#ifdef COUNTER_FREQUENCY_REAL + u32 cntfrq = COUNTER_FREQUENCY_REAL; + u32 counter_freq = 0; + + /* Update with accurate clock frequency */ + if (current_el() == 3) { + asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); + asm volatile("mrs %0, cntfrq_el0" : "=r" (counter_freq)); + debug("Counter freq = 0x%x\n", counter_freq); + } +#endif + + /* Out of boot mode */ + clk_write_ctrl(plat, + CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE); + } +} + +static u64 clk_get_vco_clk_hz(struct socfpga_clk_plat *plat, + u32 pllglob_reg, u32 pllm_reg) +{ + u64 fref, arefdiv, mdiv, reg, vco; + + reg = CM_REG_READL(plat, pllglob_reg); + + fref = (reg & CLKMGR_PLLGLOB_VCO_PSRC_MASK) >> + CLKMGR_PLLGLOB_VCO_PSRC_OFFSET; + + switch (fref) { + case CLKMGR_VCO_PSRC_EOSC1: + fref = cm_get_osc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_INTOSC: + fref = cm_get_intosc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_F2S: + fref = cm_get_fpga_clk_hz(); + break; + } + + arefdiv = (reg & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >> + CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET; + + mdiv = CM_REG_READL(plat, pllm_reg) & CLKMGR_PLLM_MDIV_MASK; + + vco = fref / arefdiv; + vco = vco * mdiv; + + return vco; +} + +static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_plat *plat) +{ + return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB, + CLKMGR_MAINPLL_PLLM); +} + +static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_plat *plat) +{ + return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB, + CLKMGR_PERPLL_PLLM); +} + +static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u64 reg) +{ + u32 clksrc = CM_REG_READL(plat, reg); + + return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET; +} + +static u64 clk_get_clksrc_hz(struct socfpga_clk_plat *plat, u32 clksrc_reg, + u32 main_reg, u32 per_reg) +{ + u64 clock; + u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg); + + switch (clklsrc) { + case CLKMGR_CLKSRC_MAIN: + clock = clk_get_main_vco_clk_hz(plat); + clock /= (CM_REG_READL(plat, main_reg) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_PER: + clock = clk_get_per_vco_clk_hz(plat); + clock /= (CM_REG_READL(plat, per_reg) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + default: + return 0; + } + + return clock; +} + +static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat) +{ + u64 clock; + u32 ctr_reg; + u32 cpu = ((read_mpidr() >> MPIDR_AFF1_OFFSET) & MPIDR_AFF1_OFFSET); + + if (cpu > CORE1) { + ctr_reg = CLKMGR_CTL_CORE23CTR; + + clock = clk_get_clksrc_hz(plat, ctr_reg, + CLKMGR_MAINPLL_PLLC0, + CLKMGR_PERPLL_PLLC0); + } else { + ctr_reg = CLKMGR_CTL_CORE01CTR; + + clock = clk_get_clksrc_hz(plat, ctr_reg, + CLKMGR_MAINPLL_PLLC1, + CLKMGR_PERPLL_PLLC0); + } + + if (cpu == CORE3) + ctr_reg = CLKMGR_CTL_CORE3CTR; + else if (cpu == CORE2) + ctr_reg = CLKMGR_CTL_CORE2CTR; + else + ctr_reg = CLKMGR_CTL_CORE01CTR; + + clock /= 1 + (CM_REG_READL(plat, ctr_reg) & + CLKMGR_CLKCNT_MSK); + + return clock; +} + +static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat) +{ + return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK, + CLKMGR_MAINPLL_PLLC3, + CLKMGR_PERPLL_PLLC1); +} + +static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_plat *plat) +{ + u64 clock = clk_get_l3_main_clk_hz(plat); + + return clock; +} + +static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat) +{ + u64 clock = clk_get_l3_main_clk_hz(plat); + + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> + CLKMGR_NOCDIV_L4SPCLK_OFFSET) & + CLKMGR_NOCDIV_DIVIDER_MASK); + + return clock; +} + +static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_plat *plat) +{ + u64 clock = clk_get_l3_main_clk_hz(plat); + + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> + CLKMGR_NOCDIV_L4MPCLK_OFFSET) & + CLKMGR_NOCDIV_DIVIDER_MASK); + + return clock; +} + +static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat) +{ + u64 clock = clk_get_l4_mp_clk_hz(plat); + + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> + CLKMGR_NOCDIV_SOFTPHY_OFFSET) & + CLKMGR_NOCDIV_DIVIDER_MASK); + + return clock; +} + +static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat) +{ + if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE) + return clk_get_l3_main_clk_hz(plat) / 2; + + return clk_get_l3_main_clk_hz(plat) / 4; +} + +static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id) +{ + u32 ctl; + u32 ctr_reg; + u32 clock; + u32 div; + u32 reg; + + if (emac_id == AGILEX5_EMAC_PTP_CLK) { + reg = CM_REG_READL(plat, CLKMGR_CTL_EMACPTPCTR); + ctr_reg = CLKMGR_CTL_EMACPTPCTR; + } else { + reg = CM_REG_READL(plat, CLKMGR_CTL_EMACACTR); + ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL); + if (emac_id == AGILEX5_EMAC0_CLK) + ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK) >> + CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET; + else if (emac_id == AGILEX5_EMAC1_CLK) + ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK) >> + CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET; + else if (emac_id == AGILEX5_EMAC2_CLK) + ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK) >> + CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET; + else + return 0; + + if (ctl) { + /* EMAC B source */ + ctr_reg = CLKMGR_CTL_EMACBCTR; + } else { + /* EMAC A source */ + ctr_reg = CLKMGR_CTL_EMACACTR; + } + } + /* Get EMAC clock source */ + clock = (reg & CLKMGR_CTL_EMACCTR_SRC_MASK) + >> CLKMGR_CTL_EMACCTR_SRC_OFFSET; + + reg = CM_REG_READL(plat, ctr_reg); + div = (reg & CLKMGR_CTL_EMACCTR_CNT_MASK) + >> CLKMGR_CTL_EMACCTR_CNT_OFFSET; + + switch (clock) { + case CLKMGR_CLKSRC_MAIN: + clock = clk_get_main_vco_clk_hz(plat); + + if (emac_id == AGILEX5_EMAC_PTP_CLK) { + clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC3) & + CLKMGR_CLKCNT_MSK); + } else { + clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC1) & + CLKMGR_CLKCNT_MSK); + } + break; + + case CLKMGR_CLKSRC_PER: + clock = clk_get_per_vco_clk_hz(plat); + + clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC3) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + } + + clock /= 1 + div; + + return clock; +} + +static ulong socfpga_clk_get_rate(struct clk *clk) +{ + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev); + + switch (clk->id) { + case AGILEX5_MPU_CLK: + return clk_get_mpu_clk_hz(plat); + case AGILEX5_L4_MAIN_CLK: + return clk_get_l4_main_clk_hz(plat); + case AGILEX5_L4_SYS_FREE_CLK: + return clk_get_l4_sys_free_clk_hz(plat); + case AGILEX5_L4_MP_CLK: + return clk_get_l4_mp_clk_hz(plat); + case AGILEX5_L4_SP_CLK: + return clk_get_l4_sp_clk_hz(plat); + case AGILEX5_SDMMC_CLK: + case AGILEX5_NAND_CLK: + return clk_get_sdmmc_clk_hz(plat); + case AGILEX5_EMAC0_CLK: + case AGILEX5_EMAC1_CLK: + case AGILEX5_EMAC2_CLK: + case AGILEX5_EMAC_PTP_CLK: + return clk_get_emac_clk_hz(plat, clk->id); + case AGILEX5_USB_CLK: + case AGILEX5_NAND_X_CLK: + return clk_get_l4_mp_clk_hz(plat); + default: + return -ENXIO; + } +} + +static int socfpga_clk_enable(struct clk *clk) +{ + return 0; +} + +static int socfpga_clk_probe(struct udevice *dev) +{ + const struct cm_config *cm_default_cfg = cm_get_default_config(); + + clk_basic_init(dev, cm_default_cfg); + + return 0; +} + +static int socfpga_clk_of_to_plat(struct udevice *dev) +{ + struct socfpga_clk_plat *plat = dev_get_plat(dev); + fdt_addr_t addr; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->regs = (void __iomem *)addr; + + return 0; +} + +static struct clk_ops socfpga_clk_ops = { + .enable = socfpga_clk_enable, + .get_rate = socfpga_clk_get_rate, +}; + +static const struct udevice_id socfpga_clk_match[] = { + { .compatible = "intel,agilex5-clkmgr" }, + {} +}; + +U_BOOT_DRIVER(socfpga_agilex5_clk) = { + .name = "clk-agilex5", + .id = UCLASS_CLK, + .of_match = socfpga_clk_match, + .ops = &socfpga_clk_ops, + .probe = socfpga_clk_probe, + .of_to_plat = socfpga_clk_of_to_plat, + .plat_auto = sizeof(struct socfpga_clk_plat), +}; diff --git a/drivers/clk/altera/clk-agilex5.h b/drivers/clk/altera/clk-agilex5.h new file mode 100644 index 00000000000..a4ddc1a60dd --- /dev/null +++ b/drivers/clk/altera/clk-agilex5.h @@ -0,0 +1,284 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ + +#ifndef _CLK_AGILEX5_ +#define _CLK_AGILEX5_ + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#endif + +#define CORE0 1 +#define CORE1 2 +#define CORE2 3 +#define CORE3 4 + +/* Derived from l4_main_clk (PSS clock) */ +#define COUNTER_FREQUENCY_REAL 400000000 + +#define CM_REG_READL(plat, reg) \ + readl((plat)->regs + (reg)) + +#define CM_REG_WRITEL(plat, data, reg) \ + writel(data, (plat)->regs + (reg)) + +#define CM_REG_CLRBITS(plat, reg, clear) \ + clrbits_le32((plat)->regs + (reg), (clear)) + +#define CM_REG_SETBITS(plat, reg, set) \ + setbits_le32((plat)->regs + (reg), (set)) + +struct cm_config { + /* main group */ + u32 main_pll_nocclk; + u32 main_pll_nocdiv; + u32 main_pll_pllglob; + u32 main_pll_fdbck; + u32 main_pll_pllc0; + u32 main_pll_pllc1; + u32 main_pll_pllc2; + u32 main_pll_pllc3; + u32 main_pll_pllm; + + /* peripheral group */ + u32 per_pll_emacctl; + u32 per_pll_gpiodiv; + u32 per_pll_pllglob; + u32 per_pll_fdbck; + u32 per_pll_pllc0; + u32 per_pll_pllc1; + u32 per_pll_pllc2; + u32 per_pll_pllc3; + u32 per_pll_pllm; + + /* control group */ + u32 ctl_emacactr; + u32 ctl_emacbctr; + u32 ctl_emacptpctr; + u32 ctl_gpiodbctr; + u32 ctl_s2fuser0ctr; + u32 ctl_s2fuser1ctr; + u32 ctl_psirefctr; + u32 ctl_usb31ctr; + u32 ctl_dsuctr; + u32 ctl_core01ctr; + u32 ctl_core23ctr; + u32 ctl_core2ctr; + u32 ctl_core3ctr; + + /* incoming clock */ + u32 hps_osc_clk_hz; + u32 fpga_clk_hz; + u32 spare[3]; +}; + +/* Clock Manager registers */ +#define CLKMGR_CTRL 0 +#define CLKMGR_STAT 4 +#define CLKMGR_TESTIOCTRL 8 +#define CLKMGR_INTRGEN 0x0c +#define CLKMGR_INTRMSK 0x10 +#define CLKMGR_INTRCLR 0x14 +#define CLKMGR_INTRSTS 0x18 +#define CLKMGR_INTRSTK 0x1c +#define CLKMGR_INTRRAW 0x20 + +/* Clock Manager Main PPL group registers */ +#define CLKMGR_MAINPLL_EN 0x24 +#define CLKMGR_MAINPLL_ENS 0x28 +#define CLKMGR_MAINPLL_ENR 0x2c +#define CLKMGR_MAINPLL_BYPASS 0x30 +#define CLKMGR_MAINPLL_BYPASSS 0x34 +#define CLKMGR_MAINPLL_BYPASSR 0x38 +#define CLKMGR_MAINPLL_NOCCLK 0x40 +#define CLKMGR_MAINPLL_NOCDIV 0x44 +#define CLKMGR_MAINPLL_PLLGLOB 0x48 +#define CLKMGR_MAINPLL_FDBCK 0x4c +#define CLKMGR_MAINPLL_MEM 0x50 +#define CLKMGR_MAINPLL_MEMSTAT 0x54 +#define CLKMGR_MAINPLL_VCOCALIB 0x58 +#define CLKMGR_MAINPLL_PLLC0 0x5c +#define CLKMGR_MAINPLL_PLLC1 0x60 +#define CLKMGR_MAINPLL_PLLC2 0x64 +#define CLKMGR_MAINPLL_PLLC3 0x68 +#define CLKMGR_MAINPLL_PLLM 0x6c +#define CLKMGR_MAINPLL_FHOP 0x70 +#define CLKMGR_MAINPLL_SSC 0x74 +#define CLKMGR_MAINPLL_LOSTLOCK 0x78 + +/* Clock Manager Peripheral PPL group registers */ +#define CLKMGR_PERPLL_EN 0x7c +#define CLKMGR_PERPLL_ENS 0x80 +#define CLKMGR_PERPLL_ENR 0x84 +#define CLKMGR_PERPLL_BYPASS 0x88 +#define CLKMGR_PERPLL_BYPASSS 0x8c +#define CLKMGR_PERPLL_BYPASSR 0x90 +#define CLKMGR_PERPLL_EMACCTL 0x94 +#define CLKMGR_PERPLL_GPIODIV 0x98 +#define CLKMGR_PERPLL_PLLGLOB 0x9c +#define CLKMGR_PERPLL_FDBCK 0xa0 +#define CLKMGR_PERPLL_MEM 0xa4 +#define CLKMGR_PERPLL_MEMSTAT 0xa8 +#define CLKMGR_PERPLL_VCOCALIB 0xac +#define CLKMGR_PERPLL_PLLC0 0xb0 +#define CLKMGR_PERPLL_PLLC1 0xb4 +#define CLKMGR_PERPLL_PLLC2 0xb8 +#define CLKMGR_PERPLL_PLLC3 0xbc +#define CLKMGR_PERPLL_PLLM 0xc0 +#define CLKMGR_PERPLL_FHOP 0xc4 +#define CLKMGR_PERPLL_SSC 0xc8 +#define CLKMGR_PERPLL_LOSTLOCK 0xcc + +/* Clock Manager Control group registers */ +#define CLKMGR_CTL_JTAG 0xd0 +#define CLKMGR_CTL_EMACACTR 0xd4 +#define CLKMGR_CTL_EMACBCTR 0xd8 +#define CLKMGR_CTL_EMACPTPCTR 0xdc +#define CLKMGR_CTL_GPIODBCTR 0xe0 +#define CLKMGR_CTL_S2FUSER0CTR 0xe8 +#define CLKMGR_CTL_S2FUSER1CTR 0xec +#define CLKMGR_CTL_PSIREFCTR 0xf0 +#define CLKMGR_CTL_EXTCNTRST 0xf4 +#define CLKMGR_CTL_USB31CTR 0xf8 +#define CLKMGR_CTL_DSUCTR 0xfc +#define CLKMGR_CTL_CORE01CTR 0x100 +#define CLKMGR_CTL_CORE23CTR 0x104 +#define CLKMGR_CTL_CORE2CTR 0x108 +#define CLKMGR_CTL_CORE3CTR 0x10C + +#define CLKMGR_CTRL_BOOTMODE BIT(0) + +#define CLKMGR_STAT_BUSY BIT(0) +#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8) +#define CLKMGR_STAT_MAIN_TRANS BIT(9) +#define CLKMGR_STAT_PERPLL_LOCKED BIT(16) +#define CLKMGR_STAT_PERF_TRANS BIT(17) +#define CLKMGR_STAT_BOOTMODE BIT(24) +#define CLKMGR_STAT_BOOTCLKSRC BIT(25) + +#define CLKMGR_STAT_ALLPLL_LOCKED_MASK \ + (CLKMGR_STAT_MAINPLL_LOCKED | CLKMGR_STAT_PERPLL_LOCKED) + +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002 +#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004 +#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008 + +#define CLKMGR_CLKSRC_MASK GENMASK(18, 16) +#define CLKMGR_CLKSRC_OFFSET 16 +#define CLKMGR_CLKSRC_MAIN 0 +#define CLKMGR_CLKSRC_PER 1 +#define CLKMGR_CLKSRC_OSC1 2 +#define CLKMGR_CLKSRC_INTOSC 3 +#define CLKMGR_CLKSRC_FPGA 4 +#define CLKMGR_CLKCNT_MSK GENMASK(10, 0) + +#define CLKMGR_BYPASS_MAINPLL_ALL 0xf6 +#define CLKMGR_BYPASS_PERPLL_ALL 0xef + +#define CLKMGR_NOCDIV_SOFTPHY_DIV_ONE 0 +#define CLKMGR_NOCDIV_SOFTPHY_DIV_TWO 1 +#define CLKMGR_NOCDIV_SOFTPHY_DIV_FOUR 2 +#define CLKMGR_NOCDIV_L4SYSFREECLK_OFFSET 0 +#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 4 +#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 6 +#define CLKMGR_NOCDIV_SOFTPHY_OFFSET 16 +#define CLKMGR_NOCDIV_CCU_OFFSET 18 +#define CLKMGR_NOCDIV_MPUPERIPH_OFFSET 20 +#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24 +#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26 +#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28 +#define CLKMGR_NOCDIV_DIVIDER_MASK 0x3 + +#define CLKMGR_PLLGLOB_PD_MASK BIT(0) +#define CLKMGR_PLLGLOB_RST_MASK BIT(1) +#define CLKMGR_PLLGLOB_AREFCLKDIV_MASK GENMASK(11, 8) +#define CLKMGR_PLLGLOB_DREFCLKDIV_MASK GENMASK(13, 12) +#define CLKMGR_PLLGLOB_REFCLKDIV_MASK GENMASK(13, 8) +#define CLKMGR_PLLGLOB_MODCLKDIV_MASK GENMASK(24, 27) +#define CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET 8 +#define CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET 12 +#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8 +#define CLKMGR_PLLGLOB_MODCLKDIV_OFFSET 24 +#define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16) +#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16 +#define CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29) + +#define CLKMGR_VCO_PSRC_EOSC1 0 +#define CLKMGR_VCO_PSRC_INTOSC 1 +#define CLKMGR_VCO_PSRC_F2S 2 + +#define CLKMGR_MEM_REQ_SET_MSK BIT(24) +#define CLKMGR_MEM_WR_SET_MSK BIT(25) +#define CLKMGR_MEM_ERR_MSK BIT(26) +#define CLKMGR_MEM_WDAT_LSB_OFFSET 16 +#define CLKMGR_MEM_ADDR_MASK GENMASK(15, 0) +#define CLKMGR_MEM_ADDR_START 0x00004000 + +#define CLKMGR_PLLCX_EN_SET_MSK BIT(27) +#define CLKMGR_PLLCX_MUTE_SET_MSK BIT(28) + +#define CLKMGR_VCOCALIB_MSCNT_MASK GENMASK(23, 16) +#define CLKMGR_VCOCALIB_MSCNT_OFFSET 16 +#define CLKMGR_VCOCALIB_HSCNT_MASK GENMASK(9, 0) +#define CLKMGR_VCOCALIB_MSCNT_CONST 100 +#define CLKMGR_VCOCALIB_HSCNT_CONST 4 + +#define CLKMGR_PLLM_MDIV_MASK GENMASK(9, 0) + +#define CLKMGR_LOSTLOCK_SET_MASK BIT(0) + +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5) +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26 +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26) +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27 +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK BIT(27) +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET 28 +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK BIT(28) + +#define CLKMGR_CTL_EMACCTR_SRC_OFFSET 16 +#define CLKMGR_CTL_EMACCTR_SRC_MASK GENMASK(18, 16) +#define CLKMGR_CTL_EMACCTR_CNT_OFFSET 0 +#define CLKMGR_CTL_EMACCTR_CNT_MASK GENMASK(10, 0) + +#define CLKMGR_CTL_EXTCNTRST_EMACACNTRST BIT(0) +#define CLKMGR_CTL_EXTCNTRST_EMACBCNTRST BIT(1) +#define CLKMGR_CTL_EXTCNTRST_EMACPTPCNTRST BIT(2) +#define CLKMGR_CTL_EXTCNTRST_GPIODBCNTRST BIT(3) +#define CLKMGR_CTL_EXTCNTRST_S2FUSER0CNTRST BIT(5) +#define CLKMGR_CTL_EXTCNTRST_S2FUSER1CNTRST BIT(6) +#define CLKMGR_CTL_EXTCNTRST_PSIREFCNTRST BIT(7) +#define CLKMGR_CTL_EXTCNTRST_USB31REFCNTRST BIT(8) +#define CLKMGR_CTL_EXTCNTRST_DSUCNTRST BIT(10) +#define CLKMGR_CTL_EXTCNTRST_CORE01CNTRST BIT(11) +#define CLKMGR_CTL_EXTCNTRST_CORE2CNTRST BIT(12) +#define CLKMGR_CTL_EXTCNTRST_CORE3CNTRST BIT(13) +#define CLKMGR_CTL_EXTCNTRST_ALLCNTRST \ + (CLKMGR_CTL_EXTCNTRST_EMACACNTRST | \ + CLKMGR_CTL_EXTCNTRST_EMACBCNTRST | \ + CLKMGR_CTL_EXTCNTRST_EMACPTPCNTRST | \ + CLKMGR_CTL_EXTCNTRST_GPIODBCNTRST | \ + CLKMGR_CTL_EXTCNTRST_S2FUSER0CNTRST | \ + CLKMGR_CTL_EXTCNTRST_S2FUSER1CNTRST | \ + CLKMGR_CTL_EXTCNTRST_PSIREFCNTRST | \ + CLKMGR_CTL_EXTCNTRST_USB31REFCNTRST | \ + CLKMGR_CTL_EXTCNTRST_DSUCNTRST | \ + CLKMGR_CTL_EXTCNTRST_CORE01CNTRST | \ + CLKMGR_CTL_EXTCNTRST_CORE2CNTRST | \ + CLKMGR_CTL_EXTCNTRST_CORE3CNTRST) + +#define MEMBUS_MAINPLL 0 +#define MEMBUS_PERPLL 1 +#define MEMBUS_TIMEOUT 1000 + +#define MEMBUS_CLKSLICE_REG 0x27 +#define MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG 0xb3 +#define MEMBUS_SYNTHPPM_WATCHDOGTMR_VF01_REG 0xe6 +#define MEMBUS_CALCLKSLICE0_DUTY_LOCOVR_REG 0x03 +#define MEMBUS_CALCLKSLICE1_DUTY_LOCOVR_REG 0x07 + +#define MPIDR_AFF1_OFFSET 8 +#define MPIDR_AFF1_MASK 0x3 +#endif /* _CLK_AGILEX5_ */ diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index a21a3ce34bb..7dfc829df2c 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -62,6 +62,10 @@ static const char *imx8mp_dram_apb_sels[] = {"clock-osc-24m", "sys_pll2_200m", " "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; +static const char * const imx8mp_pcie_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m", + "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", + "sys_pll1_160m", "sys_pll1_200m", }; + static const char *imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; @@ -272,6 +276,7 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt", imx8mp_dram_alt_sels, base + 0xa000)); clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080)); + clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite("pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400)); clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480)); clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500)); clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880)); @@ -322,6 +327,7 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0)); clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); + clk_dm(IMX8MP_CLK_PCIE_ROOT, imx_clk_gate4("pcie_root_clk", "pcie_aux", base + 0x4250, 0)); clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0)); clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0)); clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0)); diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 6c05d07c340..01e33de9d63 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -95,20 +95,23 @@ ulong imx8_clk_get_rate(struct clk *clk) resource = SC_R_SDHC_2; pm_clk = SC_PM_CLK_PER; break; - case IMX8QM_UART0_IPG_CLK: case IMX8QM_UART0_CLK: + case IMX8QM_UART0_IPG_CLK: resource = SC_R_UART_0; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART1_CLK: + case IMX8QM_UART1_IPG_CLK: resource = SC_R_UART_1; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART2_CLK: + case IMX8QM_UART2_IPG_CLK: resource = SC_R_UART_2; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART3_CLK: + case IMX8QM_UART3_IPG_CLK: resource = SC_R_UART_3; pm_clk = SC_PM_CLK_PER; break; @@ -181,18 +184,22 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART0_CLK: + case IMX8QM_UART0_IPG_CLK: resource = SC_R_UART_0; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART1_CLK: + case IMX8QM_UART1_IPG_CLK: resource = SC_R_UART_1; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART2_CLK: + case IMX8QM_UART2_IPG_CLK: resource = SC_R_UART_2; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART3_CLK: + case IMX8QM_UART3_IPG_CLK: resource = SC_R_UART_3; pm_clk = SC_PM_CLK_PER; break; @@ -283,18 +290,22 @@ int __imx8_clk_enable(struct clk *clk, bool enable) pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART0_CLK: + case IMX8QM_UART0_IPG_CLK: resource = SC_R_UART_0; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART1_CLK: + case IMX8QM_UART1_IPG_CLK: resource = SC_R_UART_1; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART2_CLK: + case IMX8QM_UART2_IPG_CLK: resource = SC_R_UART_2; pm_clk = SC_PM_CLK_PER; break; case IMX8QM_UART3_CLK: + case IMX8QM_UART3_IPG_CLK: resource = SC_R_UART_3; pm_clk = SC_PM_CLK_PER; break; diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 8bf7e325481..d900d4cd528 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -88,20 +88,23 @@ ulong imx8_clk_get_rate(struct clk *clk) resource = SC_R_SDHC_1; pm_clk = SC_PM_CLK_PER; break; - case IMX8QXP_UART0_IPG_CLK: case IMX8QXP_UART0_CLK: + case IMX8QXP_UART0_IPG_CLK: resource = SC_R_UART_0; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART1_CLK: + case IMX8QXP_UART1_IPG_CLK: resource = SC_R_UART_1; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART2_CLK: + case IMX8QXP_UART2_IPG_CLK: resource = SC_R_UART_2; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART3_CLK: + case IMX8QXP_UART3_IPG_CLK: resource = SC_R_UART_3; pm_clk = SC_PM_CLK_PER; break; @@ -170,18 +173,22 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART0_CLK: + case IMX8QXP_UART0_IPG_CLK: resource = SC_R_UART_0; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART1_CLK: + case IMX8QXP_UART1_IPG_CLK: resource = SC_R_UART_1; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART2_CLK: + case IMX8QXP_UART2_IPG_CLK: resource = SC_R_UART_2; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART3_CLK: + case IMX8QXP_UART3_IPG_CLK: resource = SC_R_UART_3; pm_clk = SC_PM_CLK_PER; break; @@ -263,18 +270,22 @@ int __imx8_clk_enable(struct clk *clk, bool enable) pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART0_CLK: + case IMX8QXP_UART0_IPG_CLK: resource = SC_R_UART_0; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART1_CLK: + case IMX8QXP_UART1_IPG_CLK: resource = SC_R_UART_1; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART2_CLK: + case IMX8QXP_UART2_IPG_CLK: resource = SC_R_UART_2; pm_clk = SC_PM_CLK_PER; break; case IMX8QXP_UART3_CLK: + case IMX8QXP_UART3_IPG_CLK: resource = SC_R_UART_3; pm_clk = SC_PM_CLK_PER; break; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 2df3dc42d0f..a7fb1eb3f4c 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -256,6 +256,9 @@ config MCP230XX_GPIO - MCP23008 - MCP23017 - MCP23018 + - MCP23S08 + - MCP23S17 + - MCP23S18 config MSCC_SGPIO bool "Microsemi Serial GPIO driver" diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index da3da5da2b3..90711702a69 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -23,7 +23,7 @@ obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o obj-$(CONFIG_IPROC_GPIO) += iproc_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o -obj-$(CONFIG_MCP230XX_GPIO) += mcp230xx_gpio.o +obj-$(CONFIG_$(SPL_TPL_)MCP230XX_GPIO) += mcp230xx_gpio.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o obj-$(CONFIG_NPCM_GPIO) += npcm_gpio.o diff --git a/drivers/gpio/mcp230xx_gpio.c b/drivers/gpio/mcp230xx_gpio.c index 9f02fd42b35..df99fde5660 100644 --- a/drivers/gpio/mcp230xx_gpio.c +++ b/drivers/gpio/mcp230xx_gpio.c @@ -11,6 +11,7 @@ #include <errno.h> #include <dm.h> #include <i2c.h> +#include <spi.h> #include <asm/gpio.h> #include <dm/device_compat.h> #include <dt-bindings/gpio/gpio.h> @@ -20,6 +21,13 @@ enum mcp230xx_type { MCP23008, MCP23017, MCP23018, + MCP23S08, + MCP23S17, + MCP23S18, +}; + +struct mcp230xx_info { + uint dev_addr; }; #define MCP230XX_IODIR 0x00 @@ -29,29 +37,136 @@ enum mcp230xx_type { #define BANKSIZE 8 +#define MCP230XX_ADDR 0x20 + +static int mcp230xx_read_spi(struct udevice *dev, uint reg_addr) +{ + struct mcp230xx_info *info = dev_get_plat(dev); + uint dev_addr, value = 0; + int ret; + + /* set R/W bit for reading */ + dev_addr = (info->dev_addr << 1) | 1; + + ret = dm_spi_claim_bus(dev); + if (ret) + return ret; + + ret = dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_BEGIN); + if (ret < 0) + goto fail; + udelay(1); + + ret = dm_spi_xfer(dev, 8, &dev_addr, NULL, 0); + if (ret < 0) + goto fail; + + ret = dm_spi_xfer(dev, 8, ®_addr, NULL, 0); + if (ret < 0) + goto fail; + + ret = dm_spi_xfer(dev, 8, NULL, &value, 0); + +fail: + dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END); + dm_spi_release_bus(dev); + if (ret < 0) + return ret; + return value; +} + static int mcp230xx_read(struct udevice *dev, uint reg, uint offset) { struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); int bank = offset / BANKSIZE; int mask = 1 << (offset % BANKSIZE); int shift = (uc_priv->gpio_count / BANKSIZE) - 1; - int ret; + int reg_addr = (reg << shift) | bank; + int ret = 0; + + switch (dev_get_driver_data(dev)) { + case MCP23008: + case MCP23017: + case MCP23018: + ret = dm_i2c_reg_read(dev, reg_addr); + break; + case MCP23S08: + case MCP23S17: + case MCP23S18: + ret = mcp230xx_read_spi(dev, reg_addr); + break; + default: + return -ENODEV; + } - ret = dm_i2c_reg_read(dev, (reg << shift) | bank); if (ret < 0) return ret; return !!(ret & mask); } +static int mcp230xx_clrset_spi(struct udevice *dev, uint reg_addr, uint clr, uint set) +{ + struct mcp230xx_info *info = dev_get_plat(dev); + int dev_addr, value; + int ret; + + /* R/W bit = 0 for writing */ + dev_addr = (info->dev_addr << 1); + + ret = mcp230xx_read_spi(dev, reg_addr); + if (ret < 0) + return ret; + + value = ret; + value &= ~clr; + value |= set; + + ret = dm_spi_claim_bus(dev); + if (ret) + return ret; + + ret = dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_BEGIN); + if (ret < 0) + goto fail; + udelay(1); + + ret = dm_spi_xfer(dev, 8, &dev_addr, NULL, 0); + if (ret < 0) + goto fail; + + ret = dm_spi_xfer(dev, 8, ®_addr, NULL, 0); + if (ret < 0) + goto fail; + + ret = dm_spi_xfer(dev, 8, &value, NULL, 0); + +fail: + dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END); + dm_spi_release_bus(dev); + return ret; +} + static int mcp230xx_write(struct udevice *dev, uint reg, uint offset, bool val) { struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); int bank = offset / BANKSIZE; int mask = 1 << (offset % BANKSIZE); int shift = (uc_priv->gpio_count / BANKSIZE) - 1; + int reg_addr = (reg << shift) | bank; - return dm_i2c_reg_clrset(dev, (reg << shift) | bank, mask, val ? mask : 0); + switch (dev_get_driver_data(dev)) { + case MCP23008: + case MCP23017: + case MCP23018: + return dm_i2c_reg_clrset(dev, reg_addr, mask, val ? mask : 0); + case MCP23S08: + case MCP23S17: + case MCP23S18: + return mcp230xx_clrset_spi(dev, reg_addr, mask, val ? mask : 0); + default: + return -ENODEV; + } } static int mcp230xx_get_value(struct udevice *dev, uint offset) @@ -181,22 +296,37 @@ static const struct dm_gpio_ops mcp230xx_ops = { static int mcp230xx_probe(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - char name[32], label[8], *str; + struct mcp230xx_info *info = dev_get_plat(dev); + char name[32], label[32], *str; int addr, gpio_count, size; const u8 *tmp; switch (dev_get_driver_data(dev)) { case MCP23008: + case MCP23S08: gpio_count = 8; break; case MCP23017: case MCP23018: + case MCP23S17: + case MCP23S18: gpio_count = 16; break; default: return -ENODEV; } + switch (dev_get_driver_data(dev)) { + case MCP23S08: + case MCP23S17: + case MCP23S18: + info->dev_addr = dev_read_u32_default(dev, "addr", MCP230XX_ADDR); + break; + default: + info->dev_addr = 0; + break; + } + addr = dev_read_addr(dev); tmp = dev_read_prop(dev, "label", &size); if (tmp) { @@ -220,9 +350,14 @@ static int mcp230xx_probe(struct udevice *dev) } static const struct udevice_id mcp230xx_ids[] = { + /* i2c interface */ { .compatible = "microchip,mcp23008", .data = MCP23008, }, { .compatible = "microchip,mcp23017", .data = MCP23017, }, { .compatible = "microchip,mcp23018", .data = MCP23018, }, + /* spi interface */ + { .compatible = "microchip,mcp23s08", .data = MCP23S08, }, + { .compatible = "microchip,mcp23s17", .data = MCP23S17, }, + { .compatible = "microchip,mcp23s18", .data = MCP23S18, }, { } }; @@ -231,5 +366,6 @@ U_BOOT_DRIVER(mcp230xx) = { .id = UCLASS_GPIO, .ops = &mcp230xx_ops, .probe = mcp230xx_probe, + .plat_auto = sizeof(struct mcp230xx_info), .of_match = mcp230xx_ids, }; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index f11ce72525f..98043fc2ff3 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -689,4 +689,11 @@ config SL28CPLD the base driver which provides common access methods for the sub-drivers. +config SPL_SOCFPGA_DT_REG + bool "Enable register setting from device tree in SPL" + depends on SPL + help + Enable register setting from device tree. This also + provides user a clean interface and all register settings are + centralized in one place, device tree. endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 0432db6ed12..1522f6c3b7d 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -90,3 +90,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o obj-$(CONFIG_ESM_K3) += k3_esm.o obj-$(CONFIG_ESM_PMIC) += esm_pmic.o obj-$(CONFIG_SL28CPLD) += sl28cpld.o +obj-$(CONFIG_SPL_SOCFPGA_SEC_REG) += socfpga_dtreg.o diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index 0c017734a49..e0ec22c7abf 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -528,6 +528,38 @@ int ele_start_rng(void) return ret; } +int ele_commit(u16 fuse_id, u32 *response, u32 *info_type) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg; + int ret = 0; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 2; + msg.command = ELE_COMMIT_REQ; + msg.data[0] = fuse_id; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n", + __func__, ret, fuse_id, msg.data[0]); + + if (response) + *response = msg.data[0]; + + if (info_type) + *info_type = msg.data[1]; + + return ret; +} + int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response) { struct udevice *dev = gd->arch.ele_dev; diff --git a/drivers/misc/socfpga_dtreg.c b/drivers/misc/socfpga_dtreg.c new file mode 100644 index 00000000000..ea5d0bcdf51 --- /dev/null +++ b/drivers/misc/socfpga_dtreg.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + */ + +#include <dm.h> +#include <errno.h> +#include <asm/io.h> +#include <linux/sizes.h> + +#define NUMBER_OF_ELEMENTS 3 + +static int socfpga_dtreg_probe(struct udevice *dev) +{ + const fdt32_t *list; + fdt_addr_t offset, base; + fdt_val_t val, read_val, mask, set_mask; + int size, i; + u32 blk_sz, reg; + ofnode node; + const char *name = NULL; + + debug("%s(dev=%p)\n", __func__, dev); + + if (!dev_has_ofnode(dev)) + return 0; + + dev_for_each_subnode(node, dev) { + name = ofnode_get_name(node); + if (!name) + return -EINVAL; + + if (ofnode_read_u32_index(node, "reg", 1, &blk_sz)) + return -EINVAL; + + base = ofnode_get_addr(node); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + debug("%s(node_offset 0x%lx node_name %s ", __func__, + node.of_offset, name); + debug("node addr 0x%llx blk sz 0x%x)\n", base, blk_sz); + + list = ofnode_read_prop(node, "intel,offset-settings", &size); + if (!list) + return -EINVAL; + + debug("%s(intel,offset-settings property size=%x)\n", __func__, + size); + size /= sizeof(*list) * NUMBER_OF_ELEMENTS; + + /* + * First element: offset + * Second element: val + * Third element: mask + */ + for (i = 0; i < size; i++) { + offset = fdt32_to_cpu(*list++); + val = fdt32_to_cpu(*list++); + + /* Reads the masking bit value from the list */ + mask = fdt32_to_cpu(*list++); + + /* + * Reads out the offsets, value and masking bits + * Ex: <0x00000000 0x00000230 0xffffffff> + */ + debug("%s(intel,offset-settings 0x%llx : 0x%llx : 0x%llx)\n", + __func__, offset, val, mask); + + if (blk_sz < offset + SZ_4) { + printf("%s: Overflow as offset 0x%llx or reg", + __func__, offset); + printf(" write is more than block size 0x%x\n", + blk_sz); + return -EINVAL; + } + + if (mask != 0) { + if (mask == 0xffffffff) { + reg = base + offset; + writel(val, (uintptr_t)reg); + } else { + /* Mask the value with the masking bits */ + set_mask = val & mask; + + reg = base + offset; + + /* Clears and sets specific bits in the register */ + clrsetbits_le32((uintptr_t)reg, mask, set_mask); + } + } + + read_val = readl((uintptr_t)reg); + + /* Reads out the register, masked value and the read value */ + debug("%s(reg 0x%x = wr : 0x%llx rd : 0x%llx)\n", + __func__, reg, set_mask, read_val); + } + } + + return 0; +}; + +static const struct udevice_id socfpga_dtreg_ids[] = { + {.compatible = "intel,socfpga-dtreg"}, + { } +}; + +U_BOOT_DRIVER(socfpga_dtreg) = { + .name = "socfpga-dtreg", + .id = UCLASS_NOP, + .of_match = socfpga_dtreg_ids, + .probe = socfpga_dtreg_probe, +}; diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 84a2a7cf904..4e7ba666770 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -116,6 +116,8 @@ static struct pci_device_id e1000_supported[] = { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I225_IT) }, {} }; @@ -1575,6 +1577,8 @@ e1000_set_mac_type(struct e1000_hw *hw) case PCI_DEVICE_ID_INTEL_I210_SERDES: case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS: case PCI_DEVICE_ID_INTEL_I210_1000BASEKX: + case PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED: + case PCI_DEVICE_ID_INTEL_I225_IT: hw->mac_type = e1000_igb; break; default: @@ -3258,7 +3262,8 @@ e1000_setup_copper_link(struct e1000_hw *hw) if (ret_val) return ret_val; } else if (hw->phy_type == e1000_phy_m88 || - hw->phy_type == e1000_phy_igb) { + hw->phy_type == e1000_phy_igb || + hw->phy_type == e1000_phy_igc) { ret_val = e1000_copper_link_mgp_setup(hw); if (ret_val) return ret_val; @@ -4531,6 +4536,8 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw) case e1000_igb: while (timeout) { if (hw->mac_type == e1000_igb) { + if (hw->phy_type == e1000_phy_igc) + break; if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask) break; } else { @@ -4769,6 +4776,7 @@ e1000_phy_reset(struct e1000_hw *hw) case e1000_phy_igp_3: case e1000_phy_ife: case e1000_phy_igb: + case e1000_phy_igc: ret_val = e1000_phy_hw_reset(hw); if (ret_val) return ret_val; @@ -4834,6 +4842,9 @@ static int e1000_set_phy_type (struct e1000_hw *hw) case I210_I_PHY_ID: hw->phy_type = e1000_phy_igb; break; + case I225_I_PHY_ID: + hw->phy_type = e1000_phy_igc; + break; /* Fall Through */ default: /* Should never have loaded on this device */ @@ -4941,6 +4952,8 @@ e1000_detect_gig_phy(struct e1000_hw *hw) case e1000_igb: if (hw->phy_id == I210_I_PHY_ID) match = true; + if (hw->phy_id == I225_I_PHY_ID) + match = true; break; default: DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index f788394da87..e1311126a3f 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -212,6 +212,7 @@ typedef enum { e1000_phy_igp_3, e1000_phy_ife, e1000_phy_igb, + e1000_phy_igc, e1000_phy_bm, e1000_phy_undefined = 0xFF } e1000_phy_type; @@ -2420,6 +2421,7 @@ struct e1000_hw { #define BME1000_E_PHY_ID 0x01410CB0 #define I210_I_PHY_ID 0x01410C00 +#define I225_I_PHY_ID 0x67C9DCC0 /* Miscellaneous PHY bit definitions. */ #define PHY_PREAMBLE 0xFFFFFFFF diff --git a/drivers/net/hifemac.c b/drivers/net/hifemac.c index b61a29e6360..90cc247b3b6 100644 --- a/drivers/net/hifemac.c +++ b/drivers/net/hifemac.c @@ -15,6 +15,9 @@ #include <wait_bit.h> #include <asm/io.h> #include <dm/device_compat.h> +#include <dm/lists.h> +#include <linux/bitfield.h> +#include <linux/ethtool.h> #include <linux/delay.h> #include <linux/kernel.h> @@ -124,6 +127,57 @@ struct hisi_femac_priv { u32 link_status; }; +struct hisi_femac_stat_entry { + const char *name; + u32 offset; + u32 mask; +}; + +/* please refer to the datasheet for the description of these entries */ +static const struct hisi_femac_stat_entry hisi_femac_stats_table[] = { + { "rxsof_cnt", 0x584, GENMASK(31, 28) }, + { "rxeof_cnt", 0x584, GENMASK(27, 24) }, + { "rxcrcok_cnt", 0x584, GENMASK(23, 20) }, + { "rxcrcbad_cnt", 0x584, GENMASK(19, 16) }, + { "txsof_cnt", 0x584, GENMASK(15, 12) }, + { "txeof_cnt", 0x584, GENMASK(11, 8) }, + { "txcrcok_cnt", 0x584, GENMASK(7, 4) }, + { "txcrcbad_cnt", 0x584, GENMASK(3, 0) }, + { "pkts_cpu", 0x5a0, GENMASK(15, 0) }, + { "addr_cpu", 0x5a4, GENMASK(15, 0) }, + { "pkts_port", 0x5a8, GENMASK(15, 0) }, + { "pkts_cpu2tx", 0x5ac, GENMASK(15, 0) }, + { "rxdvrise", 0x600, GENMASK(31, 0) }, + { "ifinoctets", 0x604, GENMASK(31, 0) }, + { "octets_rx", 0x608, GENMASK(31, 0) }, + { "local_mac_match", 0x60c, GENMASK(31, 0) }, + { "pkts", 0x610, GENMASK(31, 0) }, + { "broadcastpkts", 0x614, GENMASK(31, 0) }, + { "multicastpkts", 0x618, GENMASK(31, 0) }, + { "ifinucastpkts", 0x61c, GENMASK(31, 0) }, + { "ifinerrors", 0x620, GENMASK(31, 0) }, + { "crcerr", 0x624, GENMASK(31, 0) }, + { "abnormalsizepkts", 0x628, GENMASK(31, 0) }, + { "dot3alignmenterr", 0x62c, GENMASK(31, 0) }, + { "dot3pause", 0x630, GENMASK(31, 0) }, + { "dropevents", 0x634, GENMASK(31, 0) }, + { "flux_frame_cnt", 0x638, GENMASK(31, 0) }, + { "flux_drop_cnt", 0x63c, GENMASK(31, 0) }, + { "mac_not2cpu_pkts", 0x64c, GENMASK(31, 0) }, + { "pkts_tx", 0x780, GENMASK(31, 0) }, + { "broadcastpkts_tx", 0x784, GENMASK(31, 0) }, + { "multicastpkts_tx", 0x788, GENMASK(31, 0) }, + { "ifoutucastpkts_tx", 0x78c, GENMASK(31, 0) }, + { "octets_tx", 0x790, GENMASK(31, 0) }, + { "dot3pause", 0x794, GENMASK(31, 0) }, + { "retry_times_tx", 0x798, GENMASK(31, 0) }, + { "collisions", 0x79c, GENMASK(31, 0) }, + { "dot3latecol", 0x7a0, GENMASK(31, 0) }, + { "dot3colok", 0x7a4, GENMASK(31, 0) }, + { "dot3excessivecol", 0x7a8, GENMASK(31, 0) }, + { "dot3colcnt", 0x7ac, GENMASK(31, 0) }, +}; + static void hisi_femac_irq_enable(struct hisi_femac_priv *priv, int irqs) { u32 val; @@ -245,8 +299,10 @@ static int hisi_femac_start(struct udevice *dev) hisi_femac_rx_refill(priv); ret = phy_startup(priv->phy); - if (ret) - return log_msg_ret("Failed to startup phy", ret); + if (ret) { + dev_err(dev, "Failed to startup phy: %d\n", ret); + return log_msg_ret("phy", ret); + } if (!priv->phy->link) { debug("%s: link down\n", __func__); @@ -281,8 +337,10 @@ static int hisi_femac_send(struct udevice *dev, void *packet, int length) // wait until FIFO is empty ret = wait_for_bit_le32(priv->glb_base + GLB_IRQ_RAW, IRQ_INT_TX_PER_PACKET, true, 50, false); - if (ret == -ETIMEDOUT) - return log_msg_ret("FIFO timeout", ret); + if (ret == -ETIMEDOUT) { + dev_err(dev, "FIFO timeout\n"); + return log_msg_ret("net", ret); + } return 0; } @@ -329,10 +387,43 @@ static void hisi_femac_stop(struct udevice *dev) writel(SOFT_RESET_ALL, priv->glb_base + GLB_SOFT_RESET); } -int hisi_femac_of_to_plat(struct udevice *dev) +static int hisi_femac_get_sset_count(struct udevice *dev) +{ + return ARRAY_SIZE(hisi_femac_stats_table); +} + +static void hisi_femac_get_strings(struct udevice *dev, u8 *data) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(hisi_femac_stats_table); i++) + strcpy(data + i * ETH_GSTRING_LEN, hisi_femac_stats_table[i].name); +} + +/* Non-constant mask variant of FIELD_GET/FIELD_PREP */ +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) + +static void hisi_femac_get_stats(struct udevice *dev, u64 *data) +{ + int i; + u32 mask, reg; + struct hisi_femac_priv *priv = dev_get_priv(dev); + void __iomem *port_base = priv->port_base; + + for (i = 0; i < ARRAY_SIZE(hisi_femac_stats_table); i++) { + mask = hisi_femac_stats_table[i].mask; + reg = readl(port_base + hisi_femac_stats_table[i].offset); + + data[i] = field_get(mask, reg); + } +} + +static int hisi_femac_of_to_plat(struct udevice *dev) { int ret, i; struct hisi_femac_priv *priv = dev_get_priv(dev); + ofnode mdio_node; + bool mdio_registered = false; static const char * const clk_strs[] = { [CLK_MAC] = "mac", [CLK_BUS] = "bus", @@ -340,40 +431,75 @@ int hisi_femac_of_to_plat(struct udevice *dev) }; priv->port_base = dev_remap_addr_name(dev, "port"); - if (IS_ERR(priv->port_base)) - return log_msg_ret("Failed to remap port address space", PTR_ERR(priv->port_base)); + if (!priv->port_base) { + dev_err(dev, "Failed to remap port address space\n"); + return log_msg_ret("net", -EINVAL); + } priv->glb_base = dev_remap_addr_name(dev, "glb"); - if (IS_ERR(priv->glb_base)) - return log_msg_ret("Failed to remap global address space", PTR_ERR(priv->glb_base)); + if (IS_ERR(priv->glb_base)) { + dev_err(dev, "Failed to remap global address space\n"); + return log_msg_ret("net", -EINVAL); + } for (i = 0; i < ARRAY_SIZE(clk_strs); i++) { priv->clks[i] = devm_clk_get(dev, clk_strs[i]); if (IS_ERR(priv->clks[i])) { dev_err(dev, "Error getting clock %s\n", clk_strs[i]); - return log_msg_ret("Failed to get clocks", PTR_ERR(priv->clks[i])); + return log_msg_ret("clk", PTR_ERR(priv->clks[i])); } } priv->mac_rst = devm_reset_control_get(dev, "mac"); - if (IS_ERR(priv->mac_rst)) - return log_msg_ret("Failed to get MAC reset", PTR_ERR(priv->mac_rst)); + if (IS_ERR(priv->mac_rst)) { + dev_err(dev, "Failed to get MAC reset %ld\n", PTR_ERR(priv->mac_rst)); + return log_msg_ret("rst", PTR_ERR(priv->mac_rst)); + } priv->phy_rst = devm_reset_control_get(dev, "phy"); - if (IS_ERR(priv->phy_rst)) - return log_msg_ret("Failed to get PHY reset", PTR_ERR(priv->phy_rst)); + if (IS_ERR(priv->phy_rst)) { + dev_err(dev, "Failed to get PHY reset %ld\n", PTR_ERR(priv->phy_rst)); + return log_msg_ret("rst", PTR_ERR(priv->phy_rst)); + } ret = dev_read_u32_array(dev, PHY_RESET_DELAYS_PROPERTY, priv->phy_reset_delays, DELAYS_NUM); - if (ret < 0) - return log_msg_ret("Failed to get PHY reset delays", ret); + if (ret < 0) { + dev_err(dev, "Failed to get PHY reset delays %d\n", ret); + return log_msg_ret("rst", ret); + } priv->mac_reset_delay = dev_read_u32_default(dev, MAC_RESET_DELAY_PROPERTY, MAC_RESET_ASSERT_PERIOD); + /* Create MDIO bus */ + ofnode_for_each_subnode(mdio_node, dev_ofnode(dev)) { + const char *subnode_name = ofnode_get_name(mdio_node); + struct udevice *mdiodev; + + // Skip subnodes not starting with "mdio" + if (strncmp(subnode_name, "mdio", 4)) + continue; + + ret = device_bind_driver_to_node(dev, "hisi-femac-mdio", + subnode_name, mdio_node, &mdiodev); + if (ret) { + dev_err(dev, "Failed to register MDIO bus device %d\n", ret); + return log_msg_ret("net", ret); + } + + mdio_registered = true; + break; + } + + if (!mdio_registered) { + dev_err(dev, "No MDIO subnode is found!\n"); + return log_msg_ret("mdio", -ENODATA); + } + return 0; } @@ -385,37 +511,49 @@ static int hisi_femac_phy_reset(struct hisi_femac_priv *priv) // Disable MAC clk before phy reset ret = clk_disable(priv->clks[CLK_MAC]); - if (ret < 0) - return log_msg_ret("Failed to disable MAC clock", ret); + if (ret < 0) { + pr_err("%s: Failed to disable MAC clock %d\n", __func__, ret); + return log_msg_ret("clk", ret); + } ret = clk_disable(priv->clks[CLK_BUS]); - if (ret < 0) - return log_msg_ret("Failed to disable bus clock", ret); + if (ret < 0) { + pr_err("%s: Failed to disable bus clock %d\n", __func__, ret); + return log_msg_ret("clk", ret); + } udelay(delays[PRE_DELAY]); ret = reset_assert(rst); - if (ret < 0) - return log_msg_ret("Failed to assert reset", ret); + if (ret < 0) { + pr_err("%s: Failed to assert reset %d\n", __func__, ret); + return log_msg_ret("rst", ret); + } udelay(delays[PULSE]); ret = reset_deassert(rst); - if (ret < 0) - return log_msg_ret("Failed to deassert reset", ret); + if (ret < 0) { + pr_err("%s: Failed to deassert reset %d\n", __func__, ret); + return log_msg_ret("rst", ret); + } udelay(delays[POST_DELAY]); ret = clk_enable(priv->clks[CLK_MAC]); - if (ret < 0) - return log_msg_ret("Failed to enable MAC clock", ret); + if (ret < 0) { + pr_err("%s: Failed to enable MAC clock %d\n", __func__, ret); + return log_msg_ret("clk", ret); + } ret = clk_enable(priv->clks[CLK_BUS]); - if (ret < 0) - return log_msg_ret("Failed to enable MAC bus clock", ret); + if (ret < 0) { + pr_err("%s: Failed to enable MAC bus clock %d\n", __func__, ret); + return log_msg_ret("clk", ret); + } return 0; } -int hisi_femac_probe(struct udevice *dev) +static int hisi_femac_probe(struct udevice *dev) { struct hisi_femac_priv *priv = dev_get_priv(dev); int ret, i; @@ -423,30 +561,40 @@ int hisi_femac_probe(struct udevice *dev) // Enable clocks for (i = 0; i < CLK_NUM; i++) { ret = clk_prepare_enable(priv->clks[i]); - if (ret < 0) - return log_msg_ret("Failed to enable clks", ret); + if (ret < 0) { + dev_err(dev, "Failed to enable clk %d: %d\n", i, ret); + return log_msg_ret("clk", ret); + } } // Reset MAC ret = reset_assert(priv->mac_rst); - if (ret < 0) - return log_msg_ret("Failed to assert MAC reset", ret); + if (ret < 0) { + dev_err(dev, "Failed to assert MAC reset: %d\n", ret); + return log_msg_ret("net", ret); + } udelay(priv->mac_reset_delay); ret = reset_deassert(priv->mac_rst); - if (ret < 0) - return log_msg_ret("Failed to deassert MAC reset", ret); + if (ret < 0) { + dev_err(dev, "Failed to deassert MAC reset: %d\n", ret); + return log_msg_ret("net", ret); + } // Reset PHY ret = hisi_femac_phy_reset(priv); - if (ret < 0) - return log_msg_ret("Failed to reset phy", ret); + if (ret < 0) { + dev_err(dev, "Failed to reset PHY: %d\n", ret); + return log_msg_ret("net", ret); + } // Connect to PHY priv->phy = dm_eth_phy_connect(dev); - if (!priv->phy) - return log_msg_ret("Failed to connect to phy", -EINVAL); + if (!priv->phy) { + dev_err(dev, "Failed to connect to phy\n"); + return log_msg_ret("phy", -EINVAL); + } hisi_femac_port_init(priv); return 0; @@ -459,6 +607,9 @@ static const struct eth_ops hisi_femac_ops = { .free_pkt = hisi_femac_free_pkt, .stop = hisi_femac_stop, .write_hwaddr = hisi_femac_set_hw_mac_addr, + .get_sset_count = hisi_femac_get_sset_count, + .get_strings = hisi_femac_get_strings, + .get_stats = hisi_femac_get_stats, }; static const struct udevice_id hisi_femac_ids[] = { diff --git a/drivers/net/hifemac_mdio.c b/drivers/net/hifemac_mdio.c index 343c5f3a38a..0b59d060917 100644 --- a/drivers/net/hifemac_mdio.c +++ b/drivers/net/hifemac_mdio.c @@ -8,6 +8,7 @@ #include <dm.h> #include <clk.h> #include <miiphy.h> +#include <dm/device_compat.h> #include <linux/io.h> #include <linux/iopoll.h> @@ -74,7 +75,8 @@ static int hisi_femac_mdio_of_to_plat(struct udevice *dev) data->membase = dev_remap_addr(dev); if (IS_ERR(data->membase)) { ret = PTR_ERR(data->membase); - return log_msg_ret("Failed to remap base addr", ret); + dev_err(dev, "Failed to remap base addr %d\n", ret); + return log_msg_ret("mdio", ret); } // clk is optional @@ -89,8 +91,10 @@ static int hisi_femac_mdio_probe(struct udevice *dev) int ret; ret = clk_prepare_enable(data->clk); - if (ret) - return log_msg_ret("Failed to enable clk", ret); + if (ret) { + dev_err(dev, "Failed to enable clock: %d\n", ret); + return log_msg_ret("clk", ret); + } return 0; } @@ -112,5 +116,6 @@ U_BOOT_DRIVER(hisi_femac_mdio_driver) = { .of_to_plat = hisi_femac_mdio_of_to_plat, .probe = hisi_femac_mdio_probe, .ops = &hisi_femac_mdio_ops, + .plat_auto = sizeof(struct mdio_perdev_priv), .priv_auto = sizeof(struct hisi_femac_mdio_data), }; diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c index 82e3bbef7dd..ecccb7c3b54 100644 --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c @@ -42,6 +42,12 @@ #define BCM54810_SHD_CLK_CTL 0x3 #define BCM54810_SHD_CLK_CTL_GTXCLK_EN BIT(9) +#define BCM54XX_SHD_LEDS1 0x0d +#define BCM_LED_SRC_LINKSPD2 0x1 +#define BCM_LED_SRC_ACTIVITYLED 0x3 +#define BCM54XX_SHD_LEDS1_LED3(src) (((src) & 0xf) << 4) +#define BCM54XX_SHD_LEDS1_LED1(src) (((src) & 0xf) << 0) + static int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum) { /* The register must be written to both the Shadow Register Select and @@ -148,7 +154,16 @@ static int bcm54210e_config(struct phy_device *phydev) if (ret < 0) return ret; - return bcm5461_config(phydev); + ret = bcm5461_config(phydev); + if (ret < 0) + return ret; + + /* Configure LEDs to blink. */ + bcm_phy_write_shadow(phydev, BCM54XX_SHD_LEDS1, + BCM54XX_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) | + BCM54XX_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2)); + + return 0; } static int bcm54xx_parse_status(struct phy_device *phydev) diff --git a/drivers/net/phy/ethernet_id.c b/drivers/net/phy/ethernet_id.c index 6cb1fd4453e..4dfdee60dcc 100644 --- a/drivers/net/phy/ethernet_id.c +++ b/drivers/net/phy/ethernet_id.c @@ -18,12 +18,11 @@ struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev, { struct phy_device *phydev; struct ofnode_phandle_args phandle_args; - struct gpio_desc gpio; const char *node_name; struct udevice *pdev; - ofnode node; - u32 id, assert, deassert; u16 vendor, device; + ofnode node; + u32 id; int ret; if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, @@ -41,35 +40,9 @@ struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev, return NULL; } - if (!IS_ENABLED(CONFIG_DM_ETH_PHY)) { - ret = gpio_request_by_name_nodev(node, "reset-gpios", 0, &gpio, - GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); - if (!ret) { - assert = ofnode_read_u32_default(node, - "reset-assert-us", 0); - deassert = ofnode_read_u32_default(node, - "reset-deassert-us", - 0); - ret = dm_gpio_set_value(&gpio, 1); - if (ret) { - dev_err(dev, - "Failed assert gpio, err: %d\n", ret); - return NULL; - } - - udelay(assert); - - ret = dm_gpio_set_value(&gpio, 0); - if (ret) { - dev_err(dev, - "Failed deassert gpio, err: %d\n", - ret); - return NULL; - } - - udelay(deassert); - } - } + ret = phy_gpio_reset(dev); + if (ret) + return NULL; if (phyaddr == -1) phyaddr = ofnode_read_u32_default(phandle_args.node, "reg", -1); diff --git a/drivers/net/phy/ncsi.c b/drivers/net/phy/ncsi.c index eb3fd65bb47..2bca116a9d8 100644 --- a/drivers/net/phy/ncsi.c +++ b/drivers/net/phy/ncsi.c @@ -286,11 +286,11 @@ static void ncsi_rsp_gc(struct ncsi_rsp_pkt *pkt) } c = &ncsi_priv->packages[np].channels[nc]; - c->cap_generic = ntohl(gc->cap) & NCSI_CAP_GENERIC_MASK; - c->cap_bc = ntohl(gc->bc_cap) & NCSI_CAP_BC_MASK; - c->cap_mc = ntohl(gc->mc_cap) & NCSI_CAP_MC_MASK; - c->cap_aen = ntohl(gc->aen_cap) & NCSI_CAP_AEN_MASK; - c->cap_vlan = ntohl(gc->vlan_mode) & NCSI_CAP_VLAN_MASK; + c->cap_generic = get_unaligned_be32(&gc->cap) & NCSI_CAP_GENERIC_MASK; + c->cap_bc = get_unaligned_be32(&gc->bc_cap) & NCSI_CAP_BC_MASK; + c->cap_mc = get_unaligned_be32(&gc->mc_cap) & NCSI_CAP_MC_MASK; + c->cap_aen = get_unaligned_be32(&gc->aen_cap) & NCSI_CAP_AEN_MASK; + c->cap_vlan = gc->vlan_mode & NCSI_CAP_VLAN_MASK; /* End of probe for this channel */ } @@ -551,7 +551,7 @@ static int ncsi_send_command(unsigned int np, unsigned int nc, unsigned int cmd, checksum = ncsi_calculate_checksum((unsigned char *)hdr, sizeof(*hdr) + len); pchecksum = (__be32 *)((void *)(hdr + 1) + len); - put_unaligned_be32(htonl(checksum), pchecksum); + put_unaligned_be32(checksum, pchecksum); if (wait) { net_set_timeout_handler(1000UL, ncsi_timeout_handler); @@ -619,9 +619,12 @@ static void ncsi_handle_aen(struct ip_udp_hdr *ip, unsigned int len) /* Link or configuration lost - just redo the discovery process */ ncsi_priv->state = NCSI_PROBE_PACKAGE_SP; - for (i = 0; i < ncsi_priv->n_packages; i++) + for (i = 0; i < ncsi_priv->n_packages; i++) { free(ncsi_priv->packages[i].channels); + ncsi_priv->packages[i].channels = NULL; + } free(ncsi_priv->packages); + ncsi_priv->packages = NULL; ncsi_priv->n_packages = 0; ncsi_priv->current_package = NCSI_PACKAGE_MAX; diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 63b3e46f101..270176cfe62 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -18,6 +18,8 @@ #include <phy.h> #include <errno.h> #include <asm/global_data.h> +#include <asm-generic/gpio.h> +#include <dm/device_compat.h> #include <dm/of_extra.h> #include <linux/bitops.h> #include <linux/delay.h> @@ -566,7 +568,8 @@ struct phy_device *phy_device_create(struct mii_dev *bus, int addr, return NULL; } - if (addr >= 0 && addr < PHY_MAX_ADDR && phy_id != PHY_FIXED_ID) + if (addr >= 0 && addr < PHY_MAX_ADDR && phy_id != PHY_FIXED_ID && + phy_id != PHY_NCSI_ID) bus->phymap[addr] = dev; return dev; @@ -642,12 +645,12 @@ static struct phy_device *search_for_existing_phy(struct mii_dev *bus, { /* If we have one, return the existing device, with new interface */ while (phy_mask) { - int addr = ffs(phy_mask) - 1; + unsigned int addr = ffs(phy_mask) - 1; if (bus->phymap[addr]) return bus->phymap[addr]; - phy_mask &= ~(1 << addr); + phy_mask &= ~(1U << addr); } return NULL; } @@ -768,6 +771,59 @@ int miiphy_reset(const char *devname, unsigned char addr) return phy_reset(phydev); } +#if CONFIG_IS_ENABLED(DM_GPIO) && CONFIG_IS_ENABLED(OF_REAL) && \ + !IS_ENABLED(CONFIG_DM_ETH_PHY) +int phy_gpio_reset(struct udevice *dev) +{ + struct ofnode_phandle_args phandle_args; + struct gpio_desc gpio; + u32 assert, deassert; + ofnode node; + int ret; + + ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, + &phandle_args); + /* No PHY handle is OK */ + if (ret) + return 0; + + node = phandle_args.node; + if (!ofnode_valid(node)) + return -EINVAL; + + ret = gpio_request_by_name_nodev(node, "reset-gpios", 0, &gpio, + GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); + /* No PHY reset GPIO is OK */ + if (ret) + return 0; + + assert = ofnode_read_u32_default(node, "reset-assert-us", 20000); + deassert = ofnode_read_u32_default(node, "reset-deassert-us", 1000); + ret = dm_gpio_set_value(&gpio, 1); + if (ret) { + dev_err(dev, "Failed assert gpio, err: %d\n", ret); + return ret; + } + + udelay(assert); + + ret = dm_gpio_set_value(&gpio, 0); + if (ret) { + dev_err(dev, "Failed deassert gpio, err: %d\n", ret); + return ret; + } + + udelay(deassert); + + return 0; +} +#else +int phy_gpio_reset(struct udevice *dev) +{ + return 0; +} +#endif + struct phy_device *phy_find_by_mask(struct mii_dev *bus, uint phy_mask) { /* Reset the bus */ diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 463ec47eb92..8d02ab82ad9 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -413,4 +413,15 @@ config PCIE_STARFIVE_JH7110 Say Y here if you want to enable PLDA XpressRich PCIe controller support on StarFive JH7110 SoC. +config PCIE_DW_IMX + bool "i.MX DW PCIe controller support" + depends on ARCH_IMX8M + select PCIE_DW_COMMON + select DM_REGULATOR + select REGMAP + select SYSCON + help + Say Y here if you want to enable DW PCIe controller support on + iMX SoCs. + endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 72ef8b4bc77..2927c519129 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -53,3 +53,4 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o +obj-$(CONFIG_PCIE_DW_IMX) += pcie_dw_imx.o diff --git a/drivers/pci/pcie_dw_imx.c b/drivers/pci/pcie_dw_imx.c new file mode 100644 index 00000000000..a2ee228224b --- /dev/null +++ b/drivers/pci/pcie_dw_imx.c @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Linaro Ltd. + * + * Author: Sumit Garg <sumit.garg@linaro.org> + */ + +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <generic-phy.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/iopoll.h> +#include <log.h> +#include <pci.h> +#include <power/regulator.h> +#include <regmap.h> +#include <reset.h> +#include <syscon.h> +#include <time.h> + +#include "pcie_dw_common.h" + +#define PCIE_LINK_CAPABILITY 0x7c +#define TARGET_LINK_SPEED_MASK 0xf +#define LINK_SPEED_GEN_1 0x1 +#define LINK_SPEED_GEN_2 0x2 +#define LINK_SPEED_GEN_3 0x3 + +#define PCIE_MISC_CONTROL_1_OFF 0x8bc +#define PCIE_DBI_RO_WR_EN BIT(0) + +#define PCIE_PORT_DEBUG0 0x728 +#define PCIE_PORT_DEBUG1 0x72c +#define PCIE_PORT_DEBUG1_LINK_UP BIT(4) +#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29) + +#define PCIE_LINK_UP_TIMEOUT_MS 100 + +#define IOMUXC_GPR14_OFFSET 0x38 +#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10) +#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) + +struct pcie_dw_imx { + /* Must be first member of the struct */ + struct pcie_dw dw; + struct regmap *iomuxc_gpr; + struct clk_bulk clks; + struct gpio_desc reset_gpio; + struct reset_ctl apps_reset; + struct phy phy; + struct udevice *vpcie; +}; + +static void pcie_dw_configure(struct pcie_dw_imx *priv, u32 cap_speed) +{ + dw_pcie_dbi_write_enable(&priv->dw, true); + + clrsetbits_le32(priv->dw.dbi_base + PCIE_LINK_CAPABILITY, + TARGET_LINK_SPEED_MASK, cap_speed); + + dw_pcie_dbi_write_enable(&priv->dw, false); +} + +static void imx_pcie_ltssm_enable(struct pcie_dw_imx *priv) +{ + reset_deassert(&priv->apps_reset); +} + +static void imx_pcie_ltssm_disable(struct pcie_dw_imx *priv) +{ + reset_assert(&priv->apps_reset); +} + +static bool is_link_up(u32 val) +{ + return ((val & PCIE_PORT_DEBUG1_LINK_UP) && + (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING))); +} + +static int wait_link_up(struct pcie_dw_imx *priv) +{ + u32 val; + + return readl_poll_sleep_timeout(priv->dw.dbi_base + PCIE_PORT_DEBUG1, + val, is_link_up(val), 10000, 100000); +} + +static int pcie_link_up(struct pcie_dw_imx *priv, u32 cap_speed) +{ + int ret; + + /* DW pre link configurations */ + pcie_dw_configure(priv, cap_speed); + + /* Initiate link training */ + imx_pcie_ltssm_enable(priv); + + /* Check that link was established */ + ret = wait_link_up(priv); + if (ret) + imx_pcie_ltssm_disable(priv); + + return ret; +} + +static int imx_pcie_assert_core_reset(struct pcie_dw_imx *priv) +{ + if (dm_gpio_is_valid(&priv->reset_gpio)) { + dm_gpio_set_value(&priv->reset_gpio, 1); + mdelay(20); + } + + return reset_assert(&priv->apps_reset); +} + +static int imx_pcie_clk_enable(struct pcie_dw_imx *priv) +{ + int ret; + + ret = clk_enable_bulk(&priv->clks); + if (ret) + return ret; + + /* + * Set the over ride low and enabled make sure that + * REF_CLK is turned on. + */ + regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET, + IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE, 0); + regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET, + IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN, + IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN); + + /* allow the clocks to stabilize */ + udelay(500); + + return 0; +} + +static void imx_pcie_deassert_core_reset(struct pcie_dw_imx *priv) +{ + if (!dm_gpio_is_valid(&priv->reset_gpio)) + return; + + mdelay(100); + dm_gpio_set_value(&priv->reset_gpio, 0); + /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ + mdelay(100); +} + +static int pcie_dw_imx_probe(struct udevice *dev) +{ + struct pcie_dw_imx *priv = dev_get_priv(dev); + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *hose = dev_get_uclass_priv(ctlr); + int ret; + + if (priv->vpcie) { + ret = regulator_set_enable(priv->vpcie, true); + if (ret) { + dev_err(dev, "failed to enable vpcie regulator\n"); + return ret; + } + } + + ret = imx_pcie_assert_core_reset(priv); + if (ret) { + dev_err(dev, "failed to assert core reset\n"); + return ret; + } + + ret = imx_pcie_clk_enable(priv); + if (ret) { + dev_err(dev, "failed to enable clocks\n"); + goto err_clk; + } + + ret = generic_phy_init(&priv->phy); + if (ret) { + dev_err(dev, "failed to initialize PHY\n"); + goto err_phy_init; + } + + ret = generic_phy_power_on(&priv->phy); + if (ret) { + dev_err(dev, "failed to power on PHY\n"); + goto err_phy_power; + } + + imx_pcie_deassert_core_reset(priv); + + priv->dw.first_busno = dev_seq(dev); + priv->dw.dev = dev; + pcie_dw_setup_host(&priv->dw); + + if (pcie_link_up(priv, LINK_SPEED_GEN_1)) { + printf("PCIE-%d: Link down\n", dev_seq(dev)); + ret = -ENODEV; + goto err_link; + } + + printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev_seq(dev), + pcie_dw_get_link_speed(&priv->dw), + pcie_dw_get_link_width(&priv->dw), + hose->first_busno); + + pcie_dw_prog_outbound_atu_unroll(&priv->dw, PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_MEM, + priv->dw.mem.phys_start, + priv->dw.mem.bus_start, priv->dw.mem.size); + + return 0; + +err_link: + generic_shutdown_phy(&priv->phy); +err_phy_power: + generic_phy_exit(&priv->phy); +err_phy_init: + clk_disable_bulk(&priv->clks); +err_clk: + imx_pcie_deassert_core_reset(priv); + + return ret; +} + +static int pcie_dw_imx_remove(struct udevice *dev) +{ + struct pcie_dw_imx *priv = dev_get_priv(dev); + + generic_shutdown_phy(&priv->phy); + dm_gpio_free(dev, &priv->reset_gpio); + reset_free(&priv->apps_reset); + clk_release_bulk(&priv->clks); + + return 0; +} + +static int pcie_dw_imx_of_to_plat(struct udevice *dev) +{ + struct pcie_dw_imx *priv = dev_get_priv(dev); + ofnode gpr; + int ret; + + /* Get the controller base address */ + priv->dw.dbi_base = (void *)dev_read_addr_name(dev, "dbi"); + if ((fdt_addr_t)priv->dw.dbi_base == FDT_ADDR_T_NONE) { + dev_err(dev, "failed to get dbi_base address\n"); + return -EINVAL; + } + + /* Get the config space base address and size */ + priv->dw.cfg_base = (void *)dev_read_addr_size_name(dev, "config", + &priv->dw.cfg_size); + if ((fdt_addr_t)priv->dw.cfg_base == FDT_ADDR_T_NONE) { + dev_err(dev, "failed to get cfg_base address\n"); + return -EINVAL; + } + + ret = clk_get_bulk(dev, &priv->clks); + if (ret) { + dev_err(dev, "failed to get PCIe clks\n"); + return ret; + } + + ret = reset_get_by_name(dev, "apps", &priv->apps_reset); + if (ret) { + dev_err(dev, + "Failed to get PCIe apps reset control\n"); + goto err_reset; + } + + ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + if (ret) { + dev_err(dev, "unable to get reset-gpio\n"); + goto err_gpio; + } + + ret = generic_phy_get_by_name(dev, "pcie-phy", &priv->phy); + if (ret) { + dev_err(dev, "failed to get pcie phy\n"); + goto err_phy; + } + + gpr = ofnode_by_compatible(ofnode_null(), "fsl,imx8mp-iomuxc-gpr"); + if (ofnode_equal(gpr, ofnode_null())) { + dev_err(dev, "unable to find GPR node\n"); + ret = -ENODEV; + goto err_phy; + } + + priv->iomuxc_gpr = syscon_node_to_regmap(gpr); + if (IS_ERR(priv->iomuxc_gpr)) { + dev_err(dev, "unable to find iomuxc registers\n"); + ret = PTR_ERR(priv->iomuxc_gpr); + goto err_phy; + } + + /* vpcie-supply regulator is optional */ + device_get_supply_regulator(dev, "vpcie-supply", &priv->vpcie); + + return 0; + +err_phy: + dm_gpio_free(dev, &priv->reset_gpio); +err_gpio: + reset_free(&priv->apps_reset); +err_reset: + clk_release_bulk(&priv->clks); + + return ret; +} + +static const struct dm_pci_ops pcie_dw_imx_ops = { + .read_config = pcie_dw_read_config, + .write_config = pcie_dw_write_config, +}; + +static const struct udevice_id pcie_dw_imx_ids[] = { + { .compatible = "fsl,imx8mp-pcie" }, + { } +}; + +U_BOOT_DRIVER(pcie_dw_imx) = { + .name = "pcie_dw_imx", + .id = UCLASS_PCI, + .of_match = pcie_dw_imx_ids, + .ops = &pcie_dw_imx_ops, + .of_to_plat = pcie_dw_imx_of_to_plat, + .probe = pcie_dw_imx_probe, + .remove = pcie_dw_imx_remove, + .priv_auto = sizeof(struct pcie_dw_imx), +}; diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 4a18b0e0910..78f2c7d6bcd 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -7,6 +7,14 @@ * Based on upstream Linux kernel driver: * pci-imx6.c: Sean Cross <xobs@kosagi.com> * pcie-designware.c: Jingoo Han <jg1.han@samsung.com> + * + * This is a legacy PCIe iMX driver kept to support older iMX6 SoCs. It is + * rather tied to quite old port of pcie-designware driver from Linux which + * suffices only iMX6 specific needs. But now we have modern PCIe iMX driver + * (drivers/pci/pcie_dw_imx.c) utilizing all the common DWC specific bits from + * (drivers/pci/pcie_dw_common.*). So you are encouraged to add any further iMX + * SoC support there or even better if you posses older iMX6 SoCs then switch + * those too in order to have a single modern PCIe iMX driver. */ #include <common.h> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 60138beca49..8f767877e73 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -284,6 +284,17 @@ config PHY_IMX8MQ_USB help Support the USB3.0 PHY in NXP i.MX8MQ or i.MX8MP SoC +config PHY_IMX8M_PCIE + bool "NXP i.MX8MM/i.MX8MP PCIe PHY Driver" + depends on PHY + depends on IMX8MM || IMX8MP + select REGMAP + select SYSCON + help + Support the PCIe PHY in NXP i.MX8MM or i.MX8MP SoC + + This PHY is found on i.MX8M devices supporting PCIe. + config PHY_XILINX_ZYNQMP tristate "Xilinx ZynqMP PHY driver" depends on PHY && ARCH_ZYNQMP diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 2e8723186c0..7a2b764492b 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o +obj-$(CONFIG_PHY_IMX8M_PCIE) += phy-imx8m-pcie.o obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o obj-y += cadence/ obj-y += ti/ diff --git a/drivers/phy/phy-imx8m-pcie.c b/drivers/phy/phy-imx8m-pcie.c new file mode 100644 index 00000000000..2418388cb3c --- /dev/null +++ b/drivers/phy/phy-imx8m-pcie.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 Linaro Ltd. + * + * Derived from Linux counterpart driver + */ + +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <generic-phy.h> +#include <linux/bitfield.h> +#include <linux/clk-provider.h> +#include <linux/iopoll.h> +#include <syscon.h> +#include <regmap.h> +#include <reset.h> + +#include <dt-bindings/phy/phy-imx8-pcie.h> + +#define IMX8MM_PCIE_PHY_CMN_REG061 0x184 +#define ANA_PLL_CLK_OUT_TO_EXT_IO_EN BIT(0) +#define IMX8MM_PCIE_PHY_CMN_REG062 0x188 +#define ANA_PLL_CLK_OUT_TO_EXT_IO_SEL BIT(3) +#define IMX8MM_PCIE_PHY_CMN_REG063 0x18C +#define AUX_PLL_REFCLK_SEL_SYS_PLL GENMASK(7, 6) +#define IMX8MM_PCIE_PHY_CMN_REG064 0x190 +#define ANA_AUX_RX_TX_SEL_TX BIT(7) +#define ANA_AUX_RX_TERM_GND_EN BIT(3) +#define ANA_AUX_TX_TERM BIT(2) +#define IMX8MM_PCIE_PHY_CMN_REG065 0x194 +#define ANA_AUX_RX_TERM (BIT(7) | BIT(4)) +#define ANA_AUX_TX_LVL GENMASK(3, 0) +#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4 +#define ANA_PLL_DONE 0x3 +#define PCIE_PHY_TRSV_REG5 0x414 +#define PCIE_PHY_TRSV_REG6 0x418 + +#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24) +#define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3) +#define IMX8MM_GPR_PCIE_REF_CLK_EXT FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x2) +#define IMX8MM_GPR_PCIE_AUX_EN BIT(19) +#define IMX8MM_GPR_PCIE_CMN_RST BIT(18) +#define IMX8MM_GPR_PCIE_POWER_OFF BIT(17) +#define IMX8MM_GPR_PCIE_SSC_EN BIT(16) +#define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9) + +#define IOMUXC_GPR14_OFFSET 0x38 + +enum imx8_pcie_phy_type { + IMX8MM, + IMX8MP, +}; + +struct imx8_pcie_phy_drvdata { + const char *gpr; + enum imx8_pcie_phy_type variant; +}; + +struct imx8_pcie_phy { + ulong base; + struct clk hsio_clk; + struct regmap *iomuxc_gpr; + struct reset_ctl perst; + struct reset_ctl reset; + u32 refclk_pad_mode; + u32 tx_deemph_gen1; + u32 tx_deemph_gen2; + bool clkreq_unused; + const struct imx8_pcie_phy_drvdata *drvdata; +}; + +static int imx8_pcie_phy_power_on(struct phy *phy) +{ + int ret; + u32 val, pad_mode; + struct imx8_pcie_phy *imx8_phy = dev_get_priv(phy->dev); + + pad_mode = imx8_phy->refclk_pad_mode; + switch (imx8_phy->drvdata->variant) { + case IMX8MM: + reset_assert(&imx8_phy->reset); + + /* Tune PHY de-emphasis setting to pass PCIe compliance. */ + if (imx8_phy->tx_deemph_gen1) + writel(imx8_phy->tx_deemph_gen1, + imx8_phy->base + PCIE_PHY_TRSV_REG5); + if (imx8_phy->tx_deemph_gen2) + writel(imx8_phy->tx_deemph_gen2, + imx8_phy->base + PCIE_PHY_TRSV_REG6); + break; + case IMX8MP: /* Do nothing. */ + break; + } + + if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT || + pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) { + /* Configure the pad as input */ + val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); + writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN, + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); + } else { + /* Configure the PHY to output the refclock via pad */ + writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN, + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); + } + + if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT || + pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) { + /* Source clock from SoC internal PLL */ + writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL, + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062); + writel(AUX_PLL_REFCLK_SEL_SYS_PLL, + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063); + val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM; + writel(val | ANA_AUX_RX_TERM_GND_EN, + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064); + writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL, + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065); + } + + /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */ + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET, + IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE, + imx8_phy->clkreq_unused ? + 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE); + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET, + IMX8MM_GPR_PCIE_AUX_EN, + IMX8MM_GPR_PCIE_AUX_EN); + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET, + IMX8MM_GPR_PCIE_POWER_OFF, 0); + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET, + IMX8MM_GPR_PCIE_SSC_EN, 0); + + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET, + IMX8MM_GPR_PCIE_REF_CLK_SEL, + pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ? + IMX8MM_GPR_PCIE_REF_CLK_EXT : + IMX8MM_GPR_PCIE_REF_CLK_PLL); + udelay(200); + + /* Do the PHY common block reset */ + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET, + IMX8MM_GPR_PCIE_CMN_RST, + IMX8MM_GPR_PCIE_CMN_RST); + + switch (imx8_phy->drvdata->variant) { + case IMX8MP: + reset_deassert(&imx8_phy->perst); + fallthrough; + case IMX8MM: + reset_deassert(&imx8_phy->reset); + udelay(500); + break; + } + + /* Polling to check the phy is ready or not. */ + ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075, + val, val == ANA_PLL_DONE, 20000); + return ret; +} + +static int imx8_pcie_phy_init(struct phy *phy) +{ + struct imx8_pcie_phy *imx8_phy = dev_get_priv(phy->dev); + + return clk_enable(&imx8_phy->hsio_clk); +} + +static int imx8_pcie_phy_exit(struct phy *phy) +{ + struct imx8_pcie_phy *imx8_phy = dev_get_priv(phy->dev); + + return clk_disable(&imx8_phy->hsio_clk); +} + +static const struct phy_ops imx8_pcie_phy_ops = { + .init = imx8_pcie_phy_init, + .exit = imx8_pcie_phy_exit, + .power_on = imx8_pcie_phy_power_on, +}; + +static const struct imx8_pcie_phy_drvdata imx8mm_drvdata = { + .gpr = "fsl,imx8mm-iomuxc-gpr", + .variant = IMX8MM, +}; + +static const struct imx8_pcie_phy_drvdata imx8mp_drvdata = { + .gpr = "fsl,imx8mp-iomuxc-gpr", + .variant = IMX8MP, +}; + +static const struct udevice_id imx8_pcie_phy_of_match[] = { + {.compatible = "fsl,imx8mm-pcie-phy", .data = (ulong)&imx8mm_drvdata, }, + {.compatible = "fsl,imx8mp-pcie-phy", .data = (ulong)&imx8mp_drvdata, }, + { }, +}; + +static int imx8_pcie_phy_probe(struct udevice *dev) +{ + struct imx8_pcie_phy *imx8_phy = dev_get_priv(dev); + ofnode gpr; + int ret = 0; + + imx8_phy->drvdata = (void *)dev_get_driver_data(dev); + imx8_phy->base = dev_read_addr(dev); + if (!imx8_phy->base) + return -EINVAL; + + /* get PHY refclk pad mode */ + dev_read_u32(dev, "fsl,refclk-pad-mode", &imx8_phy->refclk_pad_mode); + + imx8_phy->tx_deemph_gen1 = dev_read_u32_default(dev, + "fsl,tx-deemph-gen1", + 0); + imx8_phy->tx_deemph_gen2 = dev_read_u32_default(dev, + "fsl,tx-deemph-gen2", + 0); + imx8_phy->clkreq_unused = dev_read_bool(dev, "fsl,clkreq-unsupported"); + + /* Grab GPR config register range */ + gpr = ofnode_by_compatible(ofnode_null(), imx8_phy->drvdata->gpr); + if (ofnode_equal(gpr, ofnode_null())) { + dev_err(dev, "unable to find GPR node\n"); + return -ENODEV; + } + + imx8_phy->iomuxc_gpr = syscon_node_to_regmap(gpr); + if (IS_ERR(imx8_phy->iomuxc_gpr)) { + dev_err(dev, "unable to find iomuxc registers\n"); + return PTR_ERR(imx8_phy->iomuxc_gpr); + } + + ret = clk_get_by_name(dev, "ref", &imx8_phy->hsio_clk); + if (ret) { + dev_err(dev, "Failed to get PCIEPHY ref clock\n"); + return ret; + } + + ret = reset_get_by_name(dev, "pciephy", &imx8_phy->reset); + if (ret) { + dev_err(dev, "Failed to get PCIEPHY reset control\n"); + return ret; + } + + if (imx8_phy->drvdata->variant == IMX8MP) { + ret = reset_get_by_name(dev, "perst", &imx8_phy->perst); + if (ret) { + dev_err(dev, + "Failed to get PCIEPHY PHY PERST control\n"); + goto err_perst; + } + } + + return 0; + +err_perst: + reset_free(&imx8_phy->reset); + return ret; +} + +static int imx8_pcie_phy_remove(struct udevice *dev) +{ + struct imx8_pcie_phy *imx8_phy = dev_get_priv(dev); + + if (imx8_phy->drvdata->variant == IMX8MP) + reset_free(&imx8_phy->perst); + + reset_free(&imx8_phy->reset); + + return 0; +} + +U_BOOT_DRIVER(nxp_imx8_pcie_phy) = { + .name = "nxp_imx8_pcie_phy", + .id = UCLASS_PHY, + .of_match = imx8_pcie_phy_of_match, + .probe = imx8_pcie_phy_probe, + .remove = imx8_pcie_phy_remove, + .ops = &imx8_pcie_phy_ops, + .priv_auto = sizeof(struct imx8_pcie_phy), +}; diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c index e2d772c5ec7..6188a04c45e 100644 --- a/drivers/power/domain/imx8mp-hsiomix.c +++ b/drivers/power/domain/imx8mp-hsiomix.c @@ -6,9 +6,15 @@ #include <common.h> #include <asm/io.h> #include <clk.h> +#include <clk-uclass.h> #include <dm.h> #include <dm/device.h> #include <dm/device_compat.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/iopoll.h> #include <power-domain-uclass.h> #include <dt-bindings/power/imx8mp-power.h> @@ -16,48 +22,94 @@ #define GPR_REG0 0x0 #define PCIE_CLOCK_MODULE_EN BIT(0) #define USB_CLOCK_MODULE_EN BIT(1) +#define PCIE_PHY_APB_RST BIT(4) +#define PCIE_PHY_INIT_RST BIT(5) +#define GPR_REG1 0x4 +#define PLL_LOCK BIT(13) +#define GPR_REG2 0x8 +#define P_PLL_MASK GENMASK(5, 0) +#define M_PLL_MASK GENMASK(15, 6) +#define S_PLL_MASK GENMASK(18, 16) +#define GPR_REG3 0xc +#define PLL_CKE BIT(17) +#define PLL_RST BIT(31) struct imx8mp_hsiomix_priv { void __iomem *base; struct clk clk_usb; + struct clk clk_pcie; struct power_domain pd_bus; struct power_domain pd_usb; + struct power_domain pd_pcie; struct power_domain pd_usb_phy1; struct power_domain pd_usb_phy2; + struct power_domain pd_pcie_phy; }; -static int imx8mp_hsiomix_on(struct power_domain *power_domain) +static int imx8mp_hsiomix_set(struct power_domain *power_domain, bool power_on) { struct udevice *dev = power_domain->dev; struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev); - struct power_domain *domain; + struct power_domain *domain = NULL; + struct clk *clk = NULL; + u32 gpr_reg0_bits = 0; int ret; - ret = power_domain_on(&priv->pd_bus); - if (ret) - return ret; - - if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) { + switch (power_domain->id) { + case IMX8MP_HSIOBLK_PD_USB: domain = &priv->pd_usb; - } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY1) { + clk = &priv->clk_usb; + gpr_reg0_bits |= USB_CLOCK_MODULE_EN; + break; + case IMX8MP_HSIOBLK_PD_USB_PHY1: domain = &priv->pd_usb_phy1; - } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2) { + break; + case IMX8MP_HSIOBLK_PD_USB_PHY2: domain = &priv->pd_usb_phy2; - } else { - ret = -EINVAL; - goto err_pd; + break; + case IMX8MP_HSIOBLK_PD_PCIE: + domain = &priv->pd_pcie; + clk = &priv->clk_pcie; + gpr_reg0_bits |= PCIE_CLOCK_MODULE_EN; + break; + case IMX8MP_HSIOBLK_PD_PCIE_PHY: + domain = &priv->pd_pcie_phy; + /* Bits to deassert PCIe PHY reset */ + gpr_reg0_bits |= PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST; + break; + default: + dev_err(dev, "unknown power domain id: %ld\n", + power_domain->id); + return -EINVAL; } - ret = power_domain_on(domain); - if (ret) - goto err_pd; + if (power_on) { + ret = power_domain_on(&priv->pd_bus); + if (ret) + return ret; - ret = clk_enable(&priv->clk_usb); - if (ret) - goto err_clk; + ret = power_domain_on(domain); + if (ret) + goto err_pd; - if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) - setbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN); + if (clk) { + ret = clk_enable(clk); + if (ret) + goto err_clk; + } + + if (gpr_reg0_bits) + setbits_le32(priv->base + GPR_REG0, gpr_reg0_bits); + } else { + if (gpr_reg0_bits) + clrbits_le32(priv->base + GPR_REG0, gpr_reg0_bits); + + if (clk) + clk_disable(clk); + + power_domain_off(domain); + power_domain_off(&priv->pd_bus); + } return 0; @@ -68,36 +120,85 @@ err_pd: return ret; } +static int imx8mp_hsiomix_on(struct power_domain *power_domain) +{ + return imx8mp_hsiomix_set(power_domain, true); +} + static int imx8mp_hsiomix_off(struct power_domain *power_domain) { - struct udevice *dev = power_domain->dev; - struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev); + return imx8mp_hsiomix_set(power_domain, false); +} + +static int imx8mp_hsiomix_of_xlate(struct power_domain *power_domain, + struct ofnode_phandle_args *args) +{ + power_domain->id = args->args[0]; + + return 0; +} - if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) - clrbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN); +static int hsio_pll_clk_enable(struct clk *clk) +{ + void *base = (void *)dev_get_driver_data(clk->dev); + u32 val; + int ret; - clk_disable(&priv->clk_usb); + /* Setup HSIO PLL as 100 MHz output clock */ + clrsetbits_le32(base + GPR_REG2, + P_PLL_MASK | M_PLL_MASK | S_PLL_MASK, + FIELD_PREP(P_PLL_MASK, 12) | + FIELD_PREP(M_PLL_MASK, 800) | + FIELD_PREP(S_PLL_MASK, 4)); - if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) - power_domain_off(&priv->pd_usb); - else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY1) - power_domain_off(&priv->pd_usb_phy1); - else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2) - power_domain_off(&priv->pd_usb_phy2); + /* de-assert PLL reset */ + setbits_le32(base + GPR_REG3, PLL_RST); - power_domain_off(&priv->pd_bus); + /* enable PLL */ + setbits_le32(base + GPR_REG3, PLL_CKE); - return 0; + /* Check if PLL is locked */ + ret = readl_poll_sleep_timeout(base + GPR_REG1, val, + val & PLL_LOCK, 10, 100000); + if (ret) + dev_err(clk->dev, "failed to lock HSIO PLL\n"); + + return ret; } -static int imx8mp_hsiomix_of_xlate(struct power_domain *power_domain, - struct ofnode_phandle_args *args) +static int hsio_pll_clk_disable(struct clk *clk) { - power_domain->id = args->args[0]; + void *base = (void *)dev_get_driver_data(clk->dev); + + clrbits_le32(base + GPR_REG3, PLL_CKE | PLL_RST); return 0; } +static const struct clk_ops hsio_pll_clk_ops = { + .enable = hsio_pll_clk_enable, + .disable = hsio_pll_clk_disable, +}; + +U_BOOT_DRIVER(hsio_pll) = { + .name = "hsio-pll", + .id = UCLASS_CLK, + .ops = &hsio_pll_clk_ops, +}; + +int imx8mp_hsiomix_bind(struct udevice *dev) +{ + struct driver *drv; + + drv = lists_driver_lookup_name("hsio-pll"); + if (!drv) + return -ENOENT; + + return device_bind_with_driver_data(dev, drv, "hsio-pll", + (ulong)dev_read_addr_ptr(dev), + dev_ofnode(dev), NULL); +} + static int imx8mp_hsiomix_probe(struct udevice *dev) { struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev); @@ -109,6 +210,10 @@ static int imx8mp_hsiomix_probe(struct udevice *dev) if (ret < 0) return ret; + ret = clk_get_by_name(dev, "pcie", &priv->clk_pcie); + if (ret < 0) + return ret; + ret = power_domain_get_by_name(dev, &priv->pd_bus, "bus"); if (ret < 0) return ret; @@ -125,8 +230,20 @@ static int imx8mp_hsiomix_probe(struct udevice *dev) if (ret < 0) goto err_pd_usb_phy2; + ret = power_domain_get_by_name(dev, &priv->pd_pcie, "pcie"); + if (ret < 0) + goto err_pd_pcie; + + ret = power_domain_get_by_name(dev, &priv->pd_pcie_phy, "pcie-phy"); + if (ret < 0) + goto err_pd_pcie_phy; + return 0; +err_pd_pcie_phy: + power_domain_free(&priv->pd_pcie); +err_pd_pcie: + power_domain_free(&priv->pd_usb_phy2); err_pd_usb_phy2: power_domain_free(&priv->pd_usb_phy1); err_pd_usb_phy1: @@ -152,6 +269,7 @@ U_BOOT_DRIVER(imx8mp_hsiomix) = { .id = UCLASS_POWER_DOMAIN, .of_match = imx8mp_hsiomix_ids, .probe = imx8mp_hsiomix_probe, + .bind = imx8mp_hsiomix_bind, .priv_auto = sizeof(struct imx8mp_hsiomix_priv), .ops = &imx8mp_hsiomix_ops, }; diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index 781de530aff..a49802c1323 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -102,4 +102,11 @@ config REMOTEPROC_TI_IPU help Say 'y' here to add support for TI' K3 remoteproc driver. +config REMOTEPROC_MAX_FW_SIZE + hex "Maximum size of firmware file that needs to be loaded to the remote processor" + default 0x10000 + help + Maximum size of the firmware file (elf, binary) that needs to be + loaded to the remote processor. + endmenu diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c index 28b362c887a..aa7f7586a81 100644 --- a/drivers/remoteproc/rproc-uclass.c +++ b/drivers/remoteproc/rproc-uclass.c @@ -13,6 +13,7 @@ #include <log.h> #include <malloc.h> #include <virtio_ring.h> +#include <fs_loader.h> #include <remoteproc.h> #include <asm/io.h> #include <dm/device-internal.h> @@ -961,3 +962,106 @@ unsigned long rproc_parse_resource_table(struct udevice *dev, struct rproc *cfg) return 1; } + +int rproc_set_firmware(struct udevice *rproc_dev, const char *fw_name) +{ + struct dm_rproc_uclass_pdata *uc_pdata; + int len; + char *p; + + if (!rproc_dev || !fw_name) + return -EINVAL; + + uc_pdata = dev_get_uclass_plat(rproc_dev); + if (!uc_pdata) + return -EINVAL; + + len = strcspn(fw_name, "\n"); + if (!len) { + debug("invalid firmware name\n"); + return -EINVAL; + } + + if (uc_pdata->fw_name) + free(uc_pdata->fw_name); + + p = strndup(fw_name, len); + if (!p) + return -ENOMEM; + + uc_pdata->fw_name = p; + + return 0; +} + +#if CONFIG_IS_ENABLED(FS_LOADER) +int rproc_boot(struct udevice *rproc_dev) +{ + struct dm_rproc_uclass_pdata *uc_pdata; + struct udevice *fs_loader; + int core_id, ret = 0; + char *firmware; + void *addr; + + if (!rproc_dev) + return -EINVAL; + + uc_pdata = dev_get_uclass_plat(rproc_dev); + if (!uc_pdata) + return -EINVAL; + + core_id = dev_seq(rproc_dev); + firmware = uc_pdata->fw_name; + if (!firmware) { + debug("No firmware name set for rproc core %d\n", core_id); + return -EINVAL; + } + + /* Initialize all rproc cores */ + if (!rproc_is_initialized()) { + ret = rproc_init(); + if (ret) { + debug("rproc_init() failed: %d\n", ret); + return ret; + } + } + + /* Loading firmware to a given address */ + ret = get_fs_loader(&fs_loader); + if (ret) { + debug("could not get fs loader: %d\n", ret); + return ret; + } + + if (CONFIG_REMOTEPROC_MAX_FW_SIZE) { + addr = malloc(CONFIG_REMOTEPROC_MAX_FW_SIZE); + if (!addr) + return -ENOMEM; + } else { + debug("CONFIG_REMOTEPROC_MAX_FW_SIZE not defined\n"); + return -EINVAL; + } + + ret = request_firmware_into_buf(fs_loader, firmware, addr, CONFIG_REMOTEPROC_MAX_FW_SIZE, + 0); + if (ret < 0) { + debug("could not request %s: %d\n", firmware, ret); + goto free_buffer; + } + + ret = rproc_load(core_id, (ulong)addr, ret); + if (ret) { + debug("failed to load %s to rproc core %d from addr 0x%08lX err %d\n", + uc_pdata->fw_name, core_id, (ulong)addr, ret); + goto free_buffer; + } + + ret = rproc_start(core_id); + if (ret) + debug("failed to start rproc core %d\n", core_id); + +free_buffer: + free(addr); + return ret; +} +#endif diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c index 1c6515f9ab7..e790406324a 100644 --- a/drivers/remoteproc/ti_k3_dsp_rproc.c +++ b/drivers/remoteproc/ti_k3_dsp_rproc.c @@ -338,7 +338,8 @@ static int k3_dsp_of_get_memories(struct udevice *dev) for (i = 0; i < dsp->num_mems; i++) { /* C71 cores only have a L1P Cache, there are no L1P SRAMs */ - if (device_is_compatible(dev, "ti,j721e-c71-dsp") && + if (((device_is_compatible(dev, "ti,j721e-c71-dsp")) || + (device_is_compatible(dev, "ti,j721s2-c71-dsp"))) && !strcmp(mem_names[i], "l1pram")) { dsp->mem[i].bus_addr = FDT_ADDR_T_NONE; dsp->mem[i].dev_addr = FDT_ADDR_T_NONE; @@ -457,6 +458,7 @@ static const struct k3_dsp_boot_data c71_data = { static const struct udevice_id k3_dsp_ids[] = { { .compatible = "ti,j721e-c66-dsp", .data = (ulong)&c66_data, }, { .compatible = "ti,j721e-c71-dsp", .data = (ulong)&c71_data, }, + { .compatible = "ti,j721s2-c71-dsp", .data = (ulong)&c71_data, }, {} }; diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c index 6f3e12d915e..631e548dcce 100644 --- a/drivers/remoteproc/ti_k3_r5f_rproc.c +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c @@ -855,7 +855,7 @@ static const struct k3_r5f_ip_data k3_data = { .tcm_ecc_autoinit = false, }; -static const struct k3_r5f_ip_data j7200_data = { +static const struct k3_r5f_ip_data j7200_j721s2_data = { .tcm_is_double = true, .tcm_ecc_autoinit = true, }; @@ -863,7 +863,8 @@ static const struct k3_r5f_ip_data j7200_data = { static const struct udevice_id k3_r5f_rproc_ids[] = { { .compatible = "ti,am654-r5f", .data = (ulong)&k3_data, }, { .compatible = "ti,j721e-r5f", .data = (ulong)&k3_data, }, - { .compatible = "ti,j7200-r5f", .data = (ulong)&j7200_data, }, + { .compatible = "ti,j7200-r5f", .data = (ulong)&j7200_j721s2_data, }, + { .compatible = "ti,j721s2-r5f", .data = (ulong)&j7200_j721s2_data, }, {} }; @@ -901,6 +902,7 @@ static const struct udevice_id k3_r5fss_ids[] = { { .compatible = "ti,am654-r5fss"}, { .compatible = "ti,j721e-r5fss"}, { .compatible = "ti,j7200-r5fss"}, + { .compatible = "ti,j721s2-r5fss"}, {} }; diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index eaef2cc2cdf..a3b3132f2fa 100644 --- a/drivers/reset/reset-imx7.c +++ b/drivers/reset/reset-imx7.c @@ -9,12 +9,13 @@ #include <common.h> #include <dm.h> #include <dt-bindings/reset/imx7-reset.h> +#include <dt-bindings/reset/imx8mp-reset.h> #include <dt-bindings/reset/imx8mq-reset.h> #include <reset-uclass.h> #include <linux/bitops.h> #include <linux/delay.h> -struct imx7_reset_priv { +struct imx_reset_priv { void __iomem *base; struct reset_ops ops; }; @@ -64,9 +65,9 @@ static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = { [IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) }, }; -static int imx7_reset_deassert_imx7(struct reset_ctl *rst) +static int imx7_reset_deassert(struct reset_ctl *rst) { - struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + struct imx_reset_priv *priv = dev_get_priv(rst->dev); const struct imx7_src_signal *sig = imx7_src_signals; u32 val; @@ -95,9 +96,9 @@ static int imx7_reset_deassert_imx7(struct reset_ctl *rst) return 0; } -static int imx7_reset_assert_imx7(struct reset_ctl *rst) +static int imx7_reset_assert(struct reset_ctl *rst) { - struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + struct imx_reset_priv *priv = dev_get_priv(rst->dev); const struct imx7_src_signal *sig = imx7_src_signals; u32 val; @@ -185,9 +186,9 @@ static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = { [IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) }, }; -static int imx7_reset_deassert_imx8mq(struct reset_ctl *rst) +static int imx8mq_reset_deassert(struct reset_ctl *rst) { - struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + struct imx_reset_priv *priv = dev_get_priv(rst->dev); const struct imx7_src_signal *sig = imx8mq_src_signals; u32 val; @@ -223,9 +224,9 @@ static int imx7_reset_deassert_imx8mq(struct reset_ctl *rst) return 0; } -static int imx7_reset_assert_imx8mq(struct reset_ctl *rst) +static int imx8mq_reset_assert(struct reset_ctl *rst) { - struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + struct imx_reset_priv *priv = dev_get_priv(rst->dev); const struct imx7_src_signal *sig = imx8mq_src_signals; u32 val; @@ -252,43 +253,143 @@ static int imx7_reset_assert_imx8mq(struct reset_ctl *rst) return 0; } -static int imx7_reset_assert(struct reset_ctl *rst) +enum imx8mp_src_registers { + SRC_SUPERMIX_RCR = 0x0018, + SRC_AUDIOMIX_RCR = 0x001c, + SRC_MLMIX_RCR = 0x0028, + SRC_GPU2D_RCR = 0x0038, + SRC_GPU3D_RCR = 0x003c, + SRC_VPU_G1_RCR = 0x0048, + SRC_VPU_G2_RCR = 0x004c, + SRC_VPUVC8KE_RCR = 0x0050, + SRC_NOC_RCR = 0x0054, +}; + +static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = { + [IMX8MP_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) }, + [IMX8MP_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) }, + [IMX8MP_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) }, + [IMX8MP_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) }, + [IMX8MP_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) }, + [IMX8MP_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) }, + [IMX8MP_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) }, + [IMX8MP_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) }, + [IMX8MP_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) }, + [IMX8MP_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) }, + [IMX8MP_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) }, + [IMX8MP_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) }, + [IMX8MP_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) }, + [IMX8MP_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) }, + [IMX8MP_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) }, + [IMX8MP_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) }, + [IMX8MP_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) }, + [IMX8MP_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) }, + [IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) }, + [IMX8MP_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) }, + [IMX8MP_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) }, + [IMX8MP_RESET_SUPERMIX_RESET] = { SRC_SUPERMIX_RCR, BIT(0) }, + [IMX8MP_RESET_AUDIOMIX_RESET] = { SRC_AUDIOMIX_RCR, BIT(0) }, + [IMX8MP_RESET_MLMIX_RESET] = { SRC_MLMIX_RCR, BIT(0) }, + [IMX8MP_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) }, + [IMX8MP_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, + [IMX8MP_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, + [IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, + [IMX8MP_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) }, + [IMX8MP_RESET_MEDIA_RESET] = { SRC_DISP_RCR, BIT(0) }, + [IMX8MP_RESET_GPU2D_RESET] = { SRC_GPU2D_RCR, BIT(0) }, + [IMX8MP_RESET_GPU3D_RESET] = { SRC_GPU3D_RCR, BIT(0) }, + [IMX8MP_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) }, + [IMX8MP_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) }, + [IMX8MP_RESET_VPU_G1_RESET] = { SRC_VPU_G1_RCR, BIT(0) }, + [IMX8MP_RESET_VPU_G2_RESET] = { SRC_VPU_G2_RCR, BIT(0) }, + [IMX8MP_RESET_VPUVC8KE_RESET] = { SRC_VPUVC8KE_RCR, BIT(0) }, + [IMX8MP_RESET_NOC_RESET] = { SRC_NOC_RCR, BIT(0) }, +}; + +static int imx8mp_reset_set(struct reset_ctl *rst, bool assert) { - struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + struct imx_reset_priv *priv = dev_get_priv(rst->dev); + unsigned int bit, value; + + if (rst->id >= IMX8MP_RESET_NUM) + return -EINVAL; + + bit = imx8mp_src_signals[rst->id].bit; + value = assert ? bit : 0; + + switch (rst->id) { + case IMX8MP_RESET_PCIEPHY: + /* + * wait for more than 10us to release phy g_rst and + * btnrst + */ + if (!assert) + udelay(10); + break; + + case IMX8MP_RESET_PCIE_CTRL_APPS_EN: + case IMX8MP_RESET_PCIEPHY_PERST: + value = assert ? 0 : bit; + break; + } + + clrsetbits_le32(priv->base + imx8mp_src_signals[rst->id].offset, bit, + value); + + return 0; +} + +static int imx8mp_reset_assert(struct reset_ctl *rst) +{ + return imx8mp_reset_set(rst, true); +} + +static int imx8mp_reset_deassert(struct reset_ctl *rst) +{ + return imx8mp_reset_set(rst, false); +} + +static int imx_reset_assert(struct reset_ctl *rst) +{ + struct imx_reset_priv *priv = dev_get_priv(rst->dev); return priv->ops.rst_assert(rst); } -static int imx7_reset_deassert(struct reset_ctl *rst) +static int imx_reset_deassert(struct reset_ctl *rst) { - struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + struct imx_reset_priv *priv = dev_get_priv(rst->dev); return priv->ops.rst_deassert(rst); } static const struct reset_ops imx7_reset_reset_ops = { - .rst_assert = imx7_reset_assert, - .rst_deassert = imx7_reset_deassert, + .rst_assert = imx_reset_assert, + .rst_deassert = imx_reset_deassert, }; static const struct udevice_id imx7_reset_ids[] = { { .compatible = "fsl,imx7d-src" }, { .compatible = "fsl,imx8mq-src" }, + { .compatible = "fsl,imx8mp-src" }, { } }; static int imx7_reset_probe(struct udevice *dev) { - struct imx7_reset_priv *priv = dev_get_priv(dev); + struct imx_reset_priv *priv = dev_get_priv(dev); priv->base = dev_remap_addr(dev); if (!priv->base) return -ENOMEM; if (device_is_compatible(dev, "fsl,imx8mq-src")) { - priv->ops.rst_assert = imx7_reset_assert_imx8mq; - priv->ops.rst_deassert = imx7_reset_deassert_imx8mq; + priv->ops.rst_assert = imx8mq_reset_assert; + priv->ops.rst_deassert = imx8mq_reset_deassert; } else if (device_is_compatible(dev, "fsl,imx7d-src")) { - priv->ops.rst_assert = imx7_reset_assert_imx7; - priv->ops.rst_deassert = imx7_reset_deassert_imx7; + priv->ops.rst_assert = imx7_reset_assert; + priv->ops.rst_deassert = imx7_reset_deassert; + } else if (device_is_compatible(dev, "fsl,imx8mp-src")) { + priv->ops.rst_assert = imx8mp_reset_assert; + priv->ops.rst_deassert = imx8mp_reset_deassert; } return 0; @@ -300,5 +401,5 @@ U_BOOT_DRIVER(imx7_reset) = { .of_match = imx7_reset_ids, .ops = &imx7_reset_reset_ops, .probe = imx7_reset_probe, - .priv_auto = sizeof(struct imx7_reset_priv), + .priv_auto = sizeof(struct imx_reset_priv), }; diff --git a/drivers/serial/serial_sbi.c b/drivers/serial/serial_sbi.c index a51a96c1ef0..f3ecfccab43 100644 --- a/drivers/serial/serial_sbi.c +++ b/drivers/serial/serial_sbi.c @@ -17,7 +17,7 @@ static inline void _debug_uart_putc(int c) #else -static int sbi_dbcn_available; +static int sbi_dbcn_available __section(".data"); static inline void _debug_uart_init(void) { diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c index 4721cfbc021..c7fe0f07a60 100644 --- a/drivers/thermal/imx_tmu.c +++ b/drivers/thermal/imx_tmu.c @@ -570,12 +570,14 @@ static int imx_tmu_parse_fdt(struct udevice *dev) { struct imx_tmu_plat *pdata = dev_get_plat(dev), *p_parent_data; struct ofnode_phandle_args args; - ofnode trips_np; + ofnode trips_np, cpu_thermal_np; int ret; dev_dbg(dev, "%s\n", __func__); - pdata->polling_delay = IMX_TMU_POLLING_DELAY_MS; + cpu_thermal_np = ofnode_path("/thermal-zones/cpu-thermal"); + pdata->polling_delay = ofnode_read_u32_default(cpu_thermal_np, "polling-delay", + IMX_TMU_POLLING_DELAY_MS); if (pdata->zone_node) { pdata->regs = (union tmu_regs *)dev_read_addr_ptr(dev); diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c index a0231293f31..34ef5a52294 100644 --- a/drivers/video/console_normal.c +++ b/drivers/video/console_normal.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <charset.h> #include <dm.h> #include <video.h> #include <video_console.h> @@ -63,7 +64,7 @@ static int console_move_rows(struct udevice *dev, uint rowdst, return 0; } -static int console_putc_xy(struct udevice *dev, uint x_frac, uint y, char ch) +static int console_putc_xy(struct udevice *dev, uint x_frac, uint y, int cp) { struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; @@ -73,8 +74,9 @@ static int console_putc_xy(struct udevice *dev, uint x_frac, uint y, char ch) int pbytes = VNBYTES(vid_priv->bpix); int x, linenum, ret; void *start, *line; + u8 ch = console_utf_to_cp437(cp); uchar *pfont = fontdata->video_fontdata + - (u8)ch * fontdata->char_pixel_bytes; + ch * fontdata->char_pixel_bytes; if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) return -EAGAIN; diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c index 65358a1c6e7..e4303dfb364 100644 --- a/drivers/video/console_rotate.c +++ b/drivers/video/console_rotate.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <charset.h> #include <dm.h> #include <video.h> #include <video_console.h> @@ -67,7 +68,7 @@ static int console_move_rows_1(struct udevice *dev, uint rowdst, uint rowsrc, return 0; } -static int console_putc_xy_1(struct udevice *dev, uint x_frac, uint y, char ch) +static int console_putc_xy_1(struct udevice *dev, uint x_frac, uint y, int cp) { struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; @@ -77,8 +78,9 @@ static int console_putc_xy_1(struct udevice *dev, uint x_frac, uint y, char ch) int pbytes = VNBYTES(vid_priv->bpix); int x, linenum, ret; void *start, *line; + u8 ch = console_utf_to_cp437(cp); uchar *pfont = fontdata->video_fontdata + - (u8)ch * fontdata->char_pixel_bytes; + ch * fontdata->char_pixel_bytes; if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) return -EAGAIN; @@ -145,7 +147,7 @@ static int console_move_rows_2(struct udevice *dev, uint rowdst, uint rowsrc, return 0; } -static int console_putc_xy_2(struct udevice *dev, uint x_frac, uint y, char ch) +static int console_putc_xy_2(struct udevice *dev, uint x_frac, uint y, int cp) { struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; @@ -155,8 +157,9 @@ static int console_putc_xy_2(struct udevice *dev, uint x_frac, uint y, char ch) int pbytes = VNBYTES(vid_priv->bpix); int linenum, x, ret; void *start, *line; + u8 ch = console_utf_to_cp437(cp); uchar *pfont = fontdata->video_fontdata + - (u8)ch * fontdata->char_pixel_bytes; + ch * fontdata->char_pixel_bytes; if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) return -EAGAIN; @@ -227,7 +230,7 @@ static int console_move_rows_3(struct udevice *dev, uint rowdst, uint rowsrc, return 0; } -static int console_putc_xy_3(struct udevice *dev, uint x_frac, uint y, char ch) +static int console_putc_xy_3(struct udevice *dev, uint x_frac, uint y, int cp) { struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; @@ -237,8 +240,9 @@ static int console_putc_xy_3(struct udevice *dev, uint x_frac, uint y, char ch) int pbytes = VNBYTES(vid_priv->bpix); int linenum, x, ret; void *start, *line; + u8 ch = console_utf_to_cp437(cp); uchar *pfont = fontdata->video_fontdata + - (u8)ch * fontdata->char_pixel_bytes; + ch * fontdata->char_pixel_bytes; if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) return -EAGAIN; diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c index 547e5a8d9cf..362458aecd4 100644 --- a/drivers/video/console_truetype.c +++ b/drivers/video/console_truetype.c @@ -262,7 +262,7 @@ static int console_truetype_move_rows(struct udevice *dev, uint rowdst, } static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y, - char ch) + int cp) { struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; @@ -281,7 +281,7 @@ static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y, int row, ret; /* First get some basic metrics about this character */ - stbtt_GetCodepointHMetrics(font, ch, &advance, &lsb); + stbtt_GetCodepointHMetrics(font, cp, &advance, &lsb); /* * First out our current X position in fractional pixels. If we wrote @@ -290,7 +290,7 @@ static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y, xpos = frac(VID_TO_PIXEL((double)x)); if (vc_priv->last_ch) { xpos += met->scale * stbtt_GetCodepointKernAdvance(font, - vc_priv->last_ch, ch); + vc_priv->last_ch, cp); } /* @@ -320,7 +320,7 @@ static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y, * return NULL; */ data = stbtt_GetCodepointBitmapSubpixel(font, met->scale, met->scale, - x_shift, 0, ch, &width, &height, + x_shift, 0, cp, &width, &height, &xoff, &yoff); if (!data) return width_frac; diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index 22d55df71f6..5f89f6a5219 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -11,6 +11,7 @@ #include <common.h> #include <abuf.h> +#include <charset.h> #include <command.h> #include <console.h> #include <log.h> @@ -20,7 +21,7 @@ #include <video_font.h> /* Bitmap font for code page 437 */ #include <linux/ctype.h> -int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, char ch) +int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, int ch) { struct vidconsole_ops *ops = vidconsole_get_ops(dev); @@ -426,8 +427,8 @@ error: priv->escape = 0; } -/* Put that actual character on the screen (using the CP437 code page). */ -static int vidconsole_output_glyph(struct udevice *dev, char ch) +/* Put that actual character on the screen (using the UTF-32 code points). */ +static int vidconsole_output_glyph(struct udevice *dev, int ch) { struct vidconsole_priv *priv = dev_get_uclass_priv(dev); int ret; @@ -455,7 +456,7 @@ static int vidconsole_output_glyph(struct udevice *dev, char ch) int vidconsole_put_char(struct udevice *dev, char ch) { struct vidconsole_priv *priv = dev_get_uclass_priv(dev); - int ret; + int cp, ret; if (priv->escape) { vidconsole_escape_char(dev, ch); @@ -489,7 +490,14 @@ int vidconsole_put_char(struct udevice *dev, char ch) priv->last_ch = 0; break; default: - ret = vidconsole_output_glyph(dev, ch); + if (CONFIG_IS_ENABLED(CHARSET)) { + cp = utf8_to_utf32_stream(ch, priv->utf8_buf); + if (cp == 0) + return 0; + } else { + cp = ch; + } + ret = vidconsole_output_glyph(dev, cp); if (ret < 0) return ret; break; diff --git a/drivers/video/vidconsole_internal.h b/drivers/video/vidconsole_internal.h index 0ec581b2663..bb0277ee451 100644 --- a/drivers/video/vidconsole_internal.h +++ b/drivers/video/vidconsole_internal.h @@ -6,6 +6,9 @@ * (C) Copyright 2023 Dzmitry Sankouski <dsankouski@gmail.com> */ +#include <charset.h> +#include <config.h> + #define FLIPPED_DIRECTION 1 #define NORMAL_DIRECTION 0 @@ -142,3 +145,19 @@ int console_simple_get_font(struct udevice *dev, int seq, struct vidfont_info *i * See details in video_console.h select_font function **/ int console_simple_select_font(struct udevice *dev, const char *name, uint size); + +/** + * Internal function to convert Unicode code points to code page 437. + * Used by video consoles using bitmap fonts. + * + * @param codepoint Unicode code point + * @returns code page 437 character. + */ +static inline u8 console_utf_to_cp437(int codepoint) +{ + if (CONFIG_IS_ENABLED(CHARSET)) { + utf_to_cp(&codepoint, codepage_437); + return codepoint; + } + return codepoint; +} diff --git a/dts/upstream/src/arm/Makefile b/dts/upstream/src/arm/Makefile new file mode 100644 index 00000000000..9a8f6aa3584 --- /dev/null +++ b/dts/upstream/src/arm/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ + +include $(srctree)/scripts/Makefile.dts + +targets += $(dtb-y) + +# Add any required device tree compiler flags here +DTC_FLAGS += -a 0x8 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := */*.dtb */*.dtbo diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index e67562ef654..15fd61a51d7 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -57,17 +57,41 @@ struct __packed acpi_table_header { char oem_id[6]; /* OEM identification */ char oem_table_id[8]; /* OEM table identification */ u32 oem_revision; /* OEM revision number */ - char aslc_id[4]; /* ASL compiler vendor ID */ - u32 aslc_revision; /* ASL compiler revision number */ + char creator_id[4]; /* ASL compiler vendor ID */ + u32 creator_revision; /* ASL compiler revision number */ }; +/** + * struct acpi_gen_regaddr - generic address structure (GAS) + */ struct acpi_gen_regaddr { - u8 space_id; /* Address space ID */ - u8 bit_width; /* Register size in bits */ - u8 bit_offset; /* Register bit offset */ - u8 access_size; /* Access size */ - u32 addrl; /* Register address, low 32 bits */ - u32 addrh; /* Register address, high 32 bits */ + /** + * @space_id: address space ID + * + * See table "Operation Region Address Space Identifiers" in the ACPI + * specification. + */ + u8 space_id; + /** @bit_width: size in bits of the register */ + u8 bit_width; + /** @bit_offset: bit offset of the register */ + u8 bit_offset; + /** + * @access_size: access size + * + * * 0 - undefined + * * 1 - byte access + * * 2 - word (2 bytes) access + * * 3 - Dword (4 bytes) access + * * 4 - Qword (8 bytes) access + * + * See ACPI_ACCESS_SIZE_*_ACCESS macros. + */ + u8 access_size; + /** @addrl: register address, low 32 bits */ + u32 addrl; + /** @addrh: register address, high 32 bits */ + u32 addrh; }; /* A maximum number of 32 ACPI tables ought to be enough for now */ @@ -85,15 +109,26 @@ struct __packed acpi_xsdt { u64 entry[MAX_ACPI_TABLES]; }; -/* HPET timers */ -struct __packed acpi_hpet { +/** + * struct acpi_hpet: High Precision Event Timers (HETP) + * + * The structure is defined in the + * "IA-PC HPET (High Precision Event Timers) Specification", rev 1.0a, Oct 2004 + */ +struct acpi_hpet { + /** @header: table header */ struct acpi_table_header header; + /** @id hardware ID of Event Timer Block */ u32 id; + /** @addr: address of Event Timer Block */ struct acpi_gen_regaddr addr; + /** @number: HPET sequence number */ u8 number; + /** @min_tick: minimum clock ticks without lost interrupts */ u16 min_tick; + /** @attributes: page protection and OEM atttribute */ u8 attributes; -}; +} __packed; struct __packed acpi_tpm2 { struct acpi_table_header header; @@ -364,7 +399,7 @@ enum { * This holds information about the Generic Interrupt Controller (GIC) CPU * interface. See ACPI Spec v6.3 section 5.2.12.14 */ -struct __packed acpi_madr_gicc { +struct acpi_madr_gicc { u8 type; u8 length; u16 reserved; @@ -383,7 +418,7 @@ struct __packed acpi_madr_gicc { u8 efficiency; u8 reserved2; u16 spi_overflow_irq; -}; +} __packed; /** * struct __packed acpi_madr_gicc - GIC distributor (type 0xc) @@ -391,7 +426,7 @@ struct __packed acpi_madr_gicc { * This holds information about the Generic Interrupt Controller (GIC) * Distributor interface. See ACPI Spec v6.3 section 5.2.12.15 */ -struct __packed acpi_madr_gicd { +struct acpi_madr_gicd { u8 type; u8 length; u16 reserved; @@ -400,7 +435,7 @@ struct __packed acpi_madr_gicd { u32 reserved2; u8 gic_version; u8 reserved3[3]; -}; +} __packed; /* MCFG (PCI Express MMIO config space BAR description table) */ struct acpi_mcfg { @@ -653,7 +688,7 @@ struct __packed acpi_spcr { * * See ACPI Spec v6.3 section 5.2.24 for details */ -struct __packed acpi_gtdt { +struct acpi_gtdt { struct acpi_table_header header; u64 cnt_ctrl_base; u32 reserved0; @@ -670,7 +705,7 @@ struct __packed acpi_gtdt { u32 plat_timer_offset; u32 virt_el2_gsiv; u32 virt_el2_flags; -}; +} __packed; /** * struct acpi_bgrt - Boot Graphics Resource Table (BGRT) @@ -680,7 +715,7 @@ struct __packed acpi_gtdt { * * See ACPI Spec v6.3 section 5.2.22 for details */ -struct __packed acpi_bgrt { +struct acpi_bgrt { struct acpi_table_header header; u16 version; u8 status; @@ -688,7 +723,7 @@ struct __packed acpi_bgrt { u64 addr; u32 offset_x; u32 offset_y; -}; +} __packed; /* Types for PPTT */ #define ACPI_PPTT_TYPE_PROC 0 @@ -709,22 +744,22 @@ struct __packed acpi_bgrt { * * See ACPI Spec v6.3 section 5.2.29 for details */ -struct __packed acpi_pptt_header { +struct acpi_pptt_header { u8 type; /* ACPI_PPTT_TYPE_... */ u8 length; u16 reserved; -}; +} __packed; /** * struct acpi_pptt_proc - a processor as described by PPTT */ -struct __packed acpi_pptt_proc { +struct acpi_pptt_proc { struct acpi_pptt_header hdr; u32 flags; u32 parent; u32 proc_id; u32 num_resources; -}; +} __packed; /* Cache flags for acpi_pptt_cache */ #define ACPI_PPTT_SIZE_VALID BIT(0) @@ -751,7 +786,7 @@ struct __packed acpi_pptt_proc { /** * struct acpi_pptt_cache - a cache as described by PPTT */ -struct __packed acpi_pptt_cache { +struct acpi_pptt_cache { struct acpi_pptt_header hdr; u32 flags; u32 next_cache_level; @@ -760,7 +795,7 @@ struct __packed acpi_pptt_cache { u8 assoc; u8 attributes; u16 line_size; -}; +} __packed; /* Tables defined/reserved by ACPI and generated by U-Boot */ enum acpi_tables { @@ -829,16 +864,6 @@ void acpi_create_dbg2(struct acpi_dbg2_header *dbg2, const char *device_path); /** - * acpi_fill_header() - Set up a new table header - * - * This sets all fields except length, revision, checksum and aslc_revision - * - * @header: ACPI header to update - * @signature: Table signature to use (4 characters) - */ -void acpi_fill_header(struct acpi_table_header *header, char *signature); - -/** * acpi_align() - Align the ACPI output pointer to a 16-byte boundary * * @ctx: ACPI context diff --git a/include/charset.h b/include/charset.h index f1050c903d6..348bad5883a 100644 --- a/include/charset.h +++ b/include/charset.h @@ -16,7 +16,7 @@ /* * codepage_437 - Unicode to codepage 437 translation table */ -extern const u16 codepage_437[128]; +extern const u16 codepage_437[160]; /** * console_read_unicode() - read Unicode code point from console diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 11a17be7fe1..206c4d50d27 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -13,49 +13,6 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#define CFG_EXTRA_ENV_SETTINGS \ - "image=Image\0" \ - "console=ttymxc0,115200\0" \ - "fdt_addr=0x48000000\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "ip_dyn=yes\0" \ - "dofastboot=0\0" \ - "fastboot_raw_partition_bootloader=64 8128\0" \ - "fastboot_raw_partition_all=0 4194304\0" \ - "emmc_dev=2\0" \ - "sd_dev=1\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "mmcroot=2\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if run loadfdt; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;\0 " \ - "nfsroot=/nfs\0" \ - "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \ - "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${loadaddr} ${image}; " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;\0" \ - /* Link Definitions */ #define CFG_SYS_INIT_RAM_ADDR 0x40000000 diff --git a/include/configs/sama7g54_curiosity.h b/include/configs/sama7g54_curiosity.h new file mode 100644 index 00000000000..fe47236158e --- /dev/null +++ b/include/configs/sama7g54_curiosity.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for the SAMA7G54 CURIOSITY board. + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Mihai Sain <mihai.sain@microchip.com> + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 + +#endif diff --git a/include/configs/socfpga_agilex5_socdk.h b/include/configs/socfpga_agilex5_socdk.h new file mode 100644 index 00000000000..b5b5bd767fb --- /dev/null +++ b/include/configs/socfpga_agilex5_socdk.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2024 Intel Corporation <www.intel.com> + * + */ + +#ifndef __CONFIG_SOCFGPA_AGILEX5_H__ +#define __CONFIG_SOCFGPA_AGILEX5_H__ + +#include <configs/socfpga_soc64_common.h> + +#endif /* __CONFIG_SOCFGPA_AGILEX5_H__ */ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 820372c28b3..b7ee1dbf201 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> + * Copyright (C) 2017-2024 Intel Corporation <www.intel.com> * */ @@ -26,8 +26,13 @@ /* * U-Boot run time memory configurations */ +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define CFG_SYS_INIT_RAM_ADDR 0x0 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 +#else #define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 #define CFG_SYS_INIT_RAM_SIZE 0x40000 +#endif /* * U-Boot environment configurations @@ -36,9 +41,121 @@ /* * Environment variable */ +#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS) +#if IS_ENABLED(CONFIG_CMD_MMC) +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#if IS_ENABLED(CONFIG_CMD_SF) +#define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) +#else +#define BOOT_TARGET_DEVICES_QSPI(func) +#endif + +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_qspi=ubi detach; sf probe && " \ + "if ubi part root && ubi readvol ${scriptaddr} script; " \ + "then echo QSPI: Running script from UBIFS; " \ + "elif sf read ${scriptaddr} ${qspiscriptaddr} ${scriptsize}; " \ + "then echo QSPI: Running script from JFFS2; fi; " \ + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo QSPI: SCRIPT FAILED: continuing...; ubi detach;\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + "qspi " + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_QSPI(func) + +#include <config_distro_bootcmd.h> + +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + #define CFG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x82000000\0" \ + "fdt_addr_r=0x86000000\0" \ + "qspiscriptaddr=0x02110000\0" \ + "scriptsize=0x00010000\0" \ + "qspibootimageaddr=0x02120000\0" \ + "bootimagesize=0x03200000\0" \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootfile=" CONFIG_BOOTFILE "\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "linux_qspi_enable=if sf probe; then " \ + "echo Enabling QSPI at Linux DTB...;" \ + "fdt addr ${fdt_addr}; fdt resize;" \ + "fdt set /soc/spi@108d2000 status okay;" \ + "if fdt set /clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " else fdt set /clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ + "scriptaddr=0x81000000\0" \ + "scriptfile=boot.scr\0" \ + "socfpga_legacy_reset_compat=1\0" \ + "smc_fid_rd=0xC2000007\0" \ + "smc_fid_wr=0xC2000008\0" \ + "smc_fid_upd=0xC2000009\0 " \ + BOOTENV + +#else + +#define CFG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x2000000\0" \ + "fdt_addr_r=0x6000000\0" \ + "qspiscriptaddr=0x02110000\0" \ + "scriptsize=0x00010000\0" \ + "qspibootimageaddr=0x02120000\0" \ + "bootimagesize=0x03200000\0" \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootfile=" CONFIG_BOOTFILE "\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "linux_qspi_enable=if sf probe; then " \ + "echo Enabling QSPI at Linux DTB...;" \ + "fdt addr ${fdt_addr}; fdt resize;" \ + "fdt set /soc/spi@ff8d2000 status okay;" \ + "if fdt set /soc/clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " else fdt set /clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ + "scriptaddr=0x05FF0000\0" \ + "scriptfile=boot.scr\0" \ + "socfpga_legacy_reset_compat=1\0" \ + "smc_fid_rd=0xC2000007\0" \ + "smc_fid_wr=0xC2000008\0" \ + "smc_fid_upd=0xC2000009\0 " \ + BOOTENV +#endif /*#IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)*/ + +#else + +#define CFG_EXTRA_ENV_SETTINGS \ + "kernel_comp_addr_r=0x9000000\0" \ + "kernel_comp_size=0x01000000\0" \ + "qspibootimageaddr=0x020E0000\0" \ + "qspifdtaddr=0x020D0000\0" \ + "bootimagesize=0x01F00000\0" \ + "fdtimagesize=0x00010000\0" \ + "qspiload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize};" \ + "sf read ${fdt_addr} ${qspifdtaddr} ${fdtimagesize}\0" \ + "qspiboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \ + "rootfstype=jffs2 rootwait;booti ${loadaddr} - ${fdt_addr}\0" \ + "qspifitload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize}\0" \ + "qspifitboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \ + "rootfstype=jffs2 rootwait;bootm ${loadaddr}\0" \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootfile=" CONFIG_BOOTFILE "\0" \ "fdt_addr=8000000\0" \ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "mmcroot=/dev/mmcblk0p2\0" \ @@ -53,24 +170,40 @@ "bootm ${loadaddr}\0" \ "mmcfitload=mmc rescan;" \ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "linux_qspi_enable=if sf probe; then " \ "echo Enabling QSPI at Linux DTB...;" \ "fdt addr ${fdt_addr}; fdt resize;" \ "fdt set /soc/spi@ff8d2000 status okay;" \ - "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \ - " ${qspi_clock}; fi; \0" \ + "if fdt set /soc/clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ + " ${qspi_clock}; then echo QSPI clock frequency updated;" \ + " else fdt set /clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ "scriptaddr=0x02100000\0" \ "scriptfile=u-boot.scr\0" \ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ - "then source ${scriptaddr}; fi\0" \ - "socfpga_legacy_reset_compat=1\0" + "then source ${scriptaddr}:script; fi\0" \ + "socfpga_legacy_reset_compat=1\0" \ + "smc_fid_rd=0xC2000007\0" \ + "smc_fid_wr=0xC2000008\0" \ + "smc_fid_upd=0xC2000009\0 " +#endif /*#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS)*/ /* * External memory configurations */ +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) +#define CFG_SYS_SDRAM_BASE 0x80000000 +#else #define PHYS_SDRAM_1 0x0 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) #define CFG_SYS_SDRAM_BASE 0 +#endif /* * Serial / UART configurations diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index 29c74470c71..049b0a06301 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -15,17 +15,6 @@ #define __io -/* Environment options */ - -#define BOOT_TARGET_DEVICES(func) \ - func(NVME, nvme, 0) \ - func(USB, usb, 0) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(DHCP, dhcp, na) - -#include <config_distro_bootcmd.h> - #define TYPE_GUID_SPL "2E54B353-1271-4842-806F-E436D6AF6985" #define TYPE_GUID_UBOOT "BC13C2FF-59E6-4262-A352-B275FD6F7172" #define TYPE_GUID_SYSTEM "EBD0A0A2-B9E5-4433-87C0-68B6B72699C7" @@ -48,7 +37,6 @@ "type_guid_gpt_loader2=" TYPE_GUID_UBOOT "\0" \ "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ "partitions=" PARTS_DEFAULT "\0" \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - BOOTENV + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" #endif /* _STARFIVE_VISIONFIVE2_H */ diff --git a/include/cp1250.h b/include/cp1250.h index adacf8a9580..b762c78d9f6 100644 --- a/include/cp1250.h +++ b/include/cp1250.h @@ -1,10 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Constant CP1250 contains the Unicode code points for characters 0x80 - 0xff - * of the code page 1250. + * Constant CP1250 contains the Unicode code points for characters 0x00 - 0x1f + * and 0x80 - 0xff of the code page 1250. */ #define CP1250 { \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000, 0x0000, 0x0000, 0x0000, \ 0x20ac, 0x0000, 0x201a, 0x0000, \ 0x201e, 0x2026, 0x2020, 0x2021, \ 0x0000, 0x2030, 0x0160, 0x2039, \ diff --git a/include/cp437.h b/include/cp437.h index 0b2b97132e3..5093130f5ed 100644 --- a/include/cp437.h +++ b/include/cp437.h @@ -1,10 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Constant CP437 contains the Unicode code points for characters 0x80 - 0xff - * of the code page 437. + * Constant CP437 contains the Unicode code points for characters 0x00 - 0x1f + * and 0x80 - 0xff of the code page 437. */ #define CP437 { \ + 0x0000, 0x263a, 0x263b, 0x2665, \ + 0x2666, 0x2663, 0x2660, 0x2022, \ + 0x25d8, 0x25cb, 0x25d9, 0x2642, \ + 0x2640, 0x266a, 0x266b, 0x263c, \ + 0x25ba, 0x25c4, 0x2195, 0x203c, \ + 0x00b6, 0x00a7, 0x25ac, 0x21a8, \ + 0x2191, 0x2193, 0x2192, 0x2190, \ + 0x221f, 0x2194, 0x25b2, 0x25bc, \ 0x00c7, 0x00fc, 0x00e9, 0x00e2, \ 0x00e4, 0x00e0, 0x00e5, 0x00e7, \ 0x00ea, 0x00eb, 0x00e8, 0x00ef, \ diff --git a/include/dt-bindings/clock/agilex5-clock.h b/include/dt-bindings/clock/agilex5-clock.h new file mode 100644 index 00000000000..c84fa51540c --- /dev/null +++ b/include/dt-bindings/clock/agilex5-clock.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024, Intel Corporation + */ + +#ifndef __AGILEX5_CLOCK_H +#define __AGILEX5_CLOCK_H + +/* fixed rate clocks */ +#define AGILEX5_OSC1 0 +#define AGILEX5_CB_INTOSC_HS_DIV2_CLK 1 +#define AGILEX5_CB_INTOSC_LS_CLK 2 +#define AGILEX5_L4_SYS_FREE_CLK 3 +#define AGILEX5_F2S_FREE_CLK 4 + +/* PLL clocks */ +#define AGILEX5_MAIN_PLL_CLK 5 +#define AGILEX5_MAIN_PLL_C0_CLK 6 +#define AGILEX5_MAIN_PLL_C1_CLK 7 +#define AGILEX5_MAIN_PLL_C2_CLK 8 +#define AGILEX5_MAIN_PLL_C3_CLK 9 +#define AGILEX5_PERIPH_PLL_CLK 10 +#define AGILEX5_PERIPH_PLL_C0_CLK 11 +#define AGILEX5_PERIPH_PLL_C1_CLK 12 +#define AGILEX5_PERIPH_PLL_C2_CLK 13 +#define AGILEX5_PERIPH_PLL_C3_CLK 14 +#define AGILEX5_MPU_FREE_CLK 15 +#define AGILEX5_MPU_CCU_CLK 16 +#define AGILEX5_BOOT_CLK 17 + +/* fixed factor clocks */ +#define AGILEX5_L3_MAIN_FREE_CLK 18 +#define AGILEX5_NOC_FREE_CLK 19 +#define AGILEX5_S2F_USR0_CLK 20 +#define AGILEX5_NOC_CLK 21 +#define AGILEX5_EMAC_A_FREE_CLK 22 +#define AGILEX5_EMAC_B_FREE_CLK 23 +#define AGILEX5_EMAC_PTP_FREE_CLK 24 +#define AGILEX5_GPIO_DB_FREE_CLK 25 +#define AGILEX5_SDMMC_FREE_CLK 26 +#define AGILEX5_S2F_USER0_FREE_CLK 27 +#define AGILEX5_S2F_USER1_FREE_CLK 28 +#define AGILEX5_PSI_REF_FREE_CLK 29 + +/* Gate clocks */ +#define AGILEX5_MPU_CLK 30 +#define AGILEX5_MPU_PERIPH_CLK 31 +#define AGILEX5_L4_MAIN_CLK 32 +#define AGILEX5_L4_MP_CLK 33 +#define AGILEX5_L4_SP_CLK 34 +#define AGILEX5_CS_AT_CLK 35 +#define AGILEX5_CS_TRACE_CLK 36 +#define AGILEX5_CS_PDBG_CLK 37 +#define AGILEX5_CS_TIMER_CLK 38 +#define AGILEX5_S2F_USER0_CLK 39 +#define AGILEX5_EMAC0_CLK 40 +#define AGILEX5_EMAC1_CLK 41 +#define AGILEX5_EMAC2_CLK 42 +#define AGILEX5_EMAC_PTP_CLK 43 +#define AGILEX5_GPIO_DB_CLK 44 +#define AGILEX5_NAND_CLK 45 +#define AGILEX5_PSI_REF_CLK 46 +#define AGILEX5_S2F_USER1_CLK 47 +#define AGILEX5_SDMMC_CLK 48 +#define AGILEX5_SPI_M_CLK 49 +#define AGILEX5_USB_CLK 50 +#define AGILEX5_NAND_X_CLK 51 +#define AGILEX5_NAND_ECC_CLK 52 +#define AGILEX5_NUM_CLKS 53 + +#endif /* __AGILEX5_CLOCK_H */ diff --git a/include/dt-bindings/reset/altr,rst-mgr-agx5.h b/include/dt-bindings/reset/altr,rst-mgr-agx5.h new file mode 100644 index 00000000000..1dba270aed4 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr-agx5.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Intel Corporation. All rights reserved + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H + +/* PER0MODRST */ +#define EMAC0_RESET 0 +#define EMAC1_RESET 1 +#define EMAC2_RESET 2 +#define USB0_RESET 3 +#define USB1_RESET 4 +#define NAND_RESET 5 +#define COMBOPHY_RESET 6 +#define SDMMC_RESET 7 +#define EMAC0_OCP_RESET 8 +#define EMAC1_OCP_RESET 9 +#define EMAC2_OCP_RESET 10 +#define USB0_OCP_RESET 11 +#define USB1_OCP_RESET 12 +#define NAND_OCP_RESET 13 +/* 14 is empty */ +#define SDMMC_OCP_RESET 15 +#define DMA_RESET 16 +#define SPIM0_RESET 17 +#define SPIM1_RESET 18 +#define SPIS0_RESET 19 +#define SPIS1_RESET 20 +#define DMA_OCP_RESET 21 +#define EMAC_PTP_RESET 22 +/* 23 is empty*/ +#define DMAIF0_RESET 24 +#define DMAIF1_RESET 25 +#define DMAIF2_RESET 26 +#define DMAIF3_RESET 27 +#define DMAIF4_RESET 28 +#define DMAIF5_RESET 29 +#define DMAIF6_RESET 30 +#define DMAIF7_RESET 31 + +/* PER1MODRST */ +#define WATCHDOG0_RESET 32 +#define WATCHDOG1_RESET 33 +#define WATCHDOG2_RESET 34 +#define WATCHDOG3_RESET 35 +#define L4SYSTIMER0_RESET 36 +#define L4SYSTIMER1_RESET 37 +#define SPTIMER0_RESET 38 +#define SPTIMER1_RESET 39 +#define I2C0_RESET 40 +#define I2C1_RESET 41 +#define I2C2_RESET 42 +#define I2C3_RESET 43 +#define I2C4_RESET 44 +#define I3C0_RESET 45 +#define I3C1_RESET 46 +/* 47 is empty */ +#define UART0_RESET 48 +#define UART1_RESET 49 +/* 50-55 is empty */ +#define GPIO0_RESET 56 +#define GPIO1_RESET 57 +#define WATCHDOG4_RESET 58 +/* 59-63 is empty */ + +/* BRGMODRST */ +#define SOC2FPGA_RESET 64 +#define LWHPS2FPGA_RESET 65 +#define FPGA2SOC_RESET 66 +#define F2SSDRAM_RESET 67 +/* 68-69 is empty */ +#define DDRSCH_RESET 70 +/* 71-95 is empty */ + +/* DBGMODRST */ +#define DBG_RESET 192 + +#endif diff --git a/include/env/phytec/rauc.env b/include/env/phytec/rauc.env new file mode 100644 index 00000000000..89e17ff70ec --- /dev/null +++ b/include/env/phytec/rauc.env @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* Logic to select a boot partition based on environment variables and switch + * to the other if the boot fails. */ + +doraucboot=0 + +raucbootpart0=1 +raucrootpart0=5 +raucbootpart1=2 +raucrootpart1=6 + +raucinit= + echo Booting RAUC A/B system; + test -n "${BOOT_ORDER}" || env set BOOT_ORDER "system0 system1"; + test -n "${BOOT_system0_LEFT}" || env set BOOT_system0_LEFT 3; + test -n "${BOOT_system1_LEFT}" || env set BOOT_system1_LEFT 3; + env set raucstatus; + for BOOT_SLOT in "${BOOT_ORDER}"; do + if test "x${raucstatus}" != "x"; then + echo Skipping remaing slots!; + elif test "x${BOOT_SLOT}" = "xsystem0"; then + if test ${BOOT_system0_LEFT} -gt 0; then + echo Found valid slot A, ${BOOT_system0_LEFT} attempts remaining; + setexpr BOOT_system0_LEFT ${BOOT_system0_LEFT} - 1; + env set mmcpart ${raucbootpart0}; + env set mmcroot ${raucrootpart0}; + env set raucargs rauc.slot=system0; + env set raucstatus success; + fi; + elif test "x${BOOT_SLOT}" = "xsystem1"; then + if test ${BOOT_system1_LEFT} -gt 0; then + echo Found valid slot B, ${BOOT_system1_LEFT} attempts remaining; + setexpr BOOT_system1_LEFT ${BOOT_system1_LEFT} - 1; + env set mmcpart ${raucbootpart1}; + env set mmcroot ${raucrootpart1}; + env set raucargs rauc.slot=system1; + env set raucstatus success; + fi; + fi; + done; + if test -n "${raucstatus}"; then + env delete raucstatus; + env save; + else + echo WARN: No valid slot found; + env set BOOT_system0_LEFT 3; + env set BOOT_system1_LEFT 3; + env delete raucstatus; + env save; + reset; + fi; diff --git a/include/pci_ids.h b/include/pci_ids.h index b63bf45168d..f1886c3a751 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2710,6 +2710,8 @@ #define PCI_DEVICE_ID_INTEL_I211_COPPER 0x1539 #define PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS 0x157b #define PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS 0x157c +#define PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED 0x15dF +#define PCI_DEVICE_ID_INTEL_I225_IT 0x0d9f #define PCI_DEVICE_ID_INTEL_80960_RP 0x1960 #define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21 #define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30 diff --git a/include/phy.h b/include/phy.h index ae23814bbf3..90b7e364101 100644 --- a/include/phy.h +++ b/include/phy.h @@ -184,6 +184,15 @@ struct fixed_link { int phy_reset(struct phy_device *phydev); /** + * phy_gpio_reset() - Resets the specified PHY using GPIO reset + * Toggles the optional PHY reset GPIO + * + * @dev: PHY udevice to reset + * @return: 0 if OK, -ve on error + */ +int phy_gpio_reset(struct udevice *dev); + +/** * phy_find_by_mask() - Searches for a PHY on the specified MDIO bus * The function checks the PHY addresses flagged in phy_mask and returns a * phy_device pointer if it detects a PHY. diff --git a/include/remoteproc.h b/include/remoteproc.h index 91a88791a47..6f8068e1496 100644 --- a/include/remoteproc.h +++ b/include/remoteproc.h @@ -403,6 +403,7 @@ enum rproc_mem_type { * @name: Platform-specific way of naming the Remote proc * @mem_type: one of 'enum rproc_mem_type' * @driver_plat_data: driver specific platform data that may be needed. + * @fw_name: firmware name * * This can be accessed with dev_get_uclass_plat() for any UCLASS_REMOTEPROC * device. @@ -412,6 +413,7 @@ struct dm_rproc_uclass_pdata { const char *name; enum rproc_mem_type mem_type; void *driver_plat_data; + char *fw_name; }; /** @@ -705,6 +707,34 @@ unsigned long rproc_parse_resource_table(struct udevice *dev, struct resource_table *rproc_find_resource_table(struct udevice *dev, unsigned int addr, int *tablesz); +/** + * rproc_set_firmware() - assign a new firmware name + * @rproc_dev: device for which new firmware name is being assigned + * @fw_name: new firmware name to be assigned + * + * This function allows remoteproc drivers or clients to configure a custom + * firmware name. The function does not trigger a remote processor boot, + * only sets the firmware name used for a subsequent boot. + * + * This function sets the fw_name field in uclass pdata of the Remote proc + * + * Return: 0 on success or a negative value upon failure + */ +int rproc_set_firmware(struct udevice *rproc_dev, const char *fw_name); + +/** + * rproc_boot() - boot a remote processor + * @rproc_dev: rproc device to boot + * + * Boot a remote processor (i.e. load its firmware, power it on, ...). + * + * This function first loads the firmware set in the uclass pdata of Remote + * processor to a buffer and then loads firmware to the remote processor + * using rproc_load(). + * + * Return: 0 on success, and an appropriate error value otherwise + */ +int rproc_boot(struct udevice *rproc_dev); #else static inline int rproc_init(void) { return -ENOSYS; } static inline int rproc_dev_init(int id) { return -ENOSYS; } @@ -744,6 +774,10 @@ static inline int rproc_elf_load_rsc_table(struct udevice *dev, ulong fw_addr, ulong fw_size, ulong *rsc_addr, ulong *rsc_size) { return -ENOSYS; } +static inline int rproc_set_firmware(struct udevice *rproc_dev, const char *fw_name) +{ return -ENOSYS; } +static inline int rproc_boot(struct udevice *rproc_dev) +{ return -ENOSYS; } #endif #endif /* _RPROC_H_ */ diff --git a/include/smbios.h b/include/smbios.h index 3df8827b60d..a4fda9df7bd 100644 --- a/include/smbios.h +++ b/include/smbios.h @@ -108,6 +108,33 @@ struct __packed smbios_type0 { char eos[SMBIOS_STRUCT_EOS_BYTES]; }; +/** + * enum smbios_wakeup_type - wake-up type + * + * These constants are used for the Wake-Up Type field in the SMBIOS + * System Information (Type 1) structure. + */ +enum smbios_wakeup_type { + /** @SMBIOS_WAKEUP_TYPE_RESERVED: Reserved */ + SMBIOS_WAKEUP_TYPE_RESERVED, + /** @SMBIOS_WAKEUP_TYPE_OTHER: Other */ + SMBIOS_WAKEUP_TYPE_OTHER, + /** @SMBIOS_WAKEUP_TYPE_UNKNOWN: Unknown */ + SMBIOS_WAKEUP_TYPE_UNKNOWN, + /** @SMBIOS_WAKEUP_TYPE_APM_TIMER: APM Timer */ + SMBIOS_WAKEUP_TYPE_APM_TIMER, + /** @SMBIOS_WAKEUP_TYPE_MODEM_RING: Modem Ring */ + SMBIOS_WAKEUP_TYPE_MODEM_RING, + /** @SMBIOS_WAKEUP_TYPE_LAN_REMOTE: LAN Remote */ + SMBIOS_WAKEUP_TYPE_LAN_REMOTE, + /** @SMBIOS_WAKEUP_TYPE_POWER_SWITCH: Power Switch */ + SMBIOS_WAKEUP_TYPE_POWER_SWITCH, + /** @SMBIOS_WAKEUP_TYPE_PCI_PME: PCI PME# */ + SMBIOS_WAKEUP_TYPE_PCI_PME, + /** @SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED: AC Power Restored */ + SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED, +}; + struct __packed smbios_type1 { u8 type; u8 length; diff --git a/include/video_console.h b/include/video_console.h index bde67fa9a5a..8b5928dc5eb 100644 --- a/include/video_console.h +++ b/include/video_console.h @@ -43,6 +43,7 @@ enum { * @col_saved: Saved X position, in fractional units (VID_TO_POS(x)) * @row_saved: Saved Y position in pixels (0=top) * @escape_buf: Buffer to accumulate escape sequence + * @utf8_buf: Buffer to accumulate UTF-8 byte sequence */ struct vidconsole_priv { struct stdio_dev sdev; @@ -66,6 +67,7 @@ struct vidconsole_priv { int row_saved; int col_saved; char escape_buf[32]; + char utf8_buf[5]; }; /** @@ -124,12 +126,12 @@ struct vidconsole_ops { * @x_frac: Fractional pixel X position (0=left-most pixel) which * is the X position multipled by VID_FRAC_DIV. * @y: Pixel Y position (0=top-most pixel) - * @ch: Character to write + * @cp: UTF-32 code point to write * @return number of fractional pixels that the cursor should move, * if all is OK, -EAGAIN if we ran out of space on this line, other -ve * on error */ - int (*putc_xy)(struct udevice *dev, uint x_frac, uint y, char ch); + int (*putc_xy)(struct udevice *dev, uint x_frac, uint y, int cp); /** * move_rows() - Move text rows from one place to another @@ -403,12 +405,12 @@ void vidconsole_pop_colour(struct udevice *dev, struct vidconsole_colour *old); * @x_frac: Fractional pixel X position (0=left-most pixel) which * is the X position multipled by VID_FRAC_DIV. * @y: Pixel Y position (0=top-most pixel) - * @ch: Character to write + * @cp: UTF-32 code point to write * Return: number of fractional pixels that the cursor should move, * if all is OK, -EAGAIN if we ran out of space on this line, other -ve * on error */ -int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, char ch); +int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, int cp); /** * vidconsole_move_rows() - Move text rows from one place to another diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index 39dd53ec402..c16ead6a6ec 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -116,7 +116,7 @@ void acpi_fill_header(struct acpi_table_header *header, char *signature) memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, OEM_TABLE_ID, 8); header->oem_revision = OEM_REVISION; - memcpy(header->aslc_id, ASLC_ID, 4); + memcpy(header->creator_id, ASLC_ID, 4); } void acpi_align(struct acpi_ctx *ctx) @@ -219,7 +219,7 @@ void acpi_create_dbg2(struct acpi_dbg2_header *dbg2, header->revision = acpi_get_table_revision(ACPITAB_DBG2); acpi_fill_header(header, "DBG2"); - header->aslc_revision = ASL_REVISION; + header->creator_revision = ASL_REVISION; /* One debug device defined */ dbg2->devices_offset = sizeof(struct acpi_dbg2_header); diff --git a/lib/acpi/ssdt.c b/lib/acpi/ssdt.c index b0a96f846e3..e032e266b3c 100644 --- a/lib/acpi/ssdt.c +++ b/lib/acpi/ssdt.c @@ -23,7 +23,7 @@ int acpi_write_ssdt(struct acpi_ctx *ctx, const struct acpi_writer *entry) acpi_fill_header(ssdt, "SSDT"); ssdt->revision = acpi_get_table_revision(ACPITAB_SSDT); - ssdt->aslc_revision = 1; + ssdt->creator_revision = 1; ssdt->length = sizeof(struct acpi_table_header); acpi_inc(ctx, sizeof(struct acpi_table_header)); diff --git a/lib/charset.c b/lib/charset.c index 2b43175b1d9..df4f0407485 100644 --- a/lib/charset.c +++ b/lib/charset.c @@ -15,7 +15,7 @@ /** * codepage_437 - Unicode to codepage 437 translation table */ -const u16 codepage_437[128] = CP437; +const u16 codepage_437[160] = CP437; static struct capitalization_table capitalization_table[] = #ifdef CONFIG_EFI_UNICODE_CAPITALIZATION @@ -516,9 +516,12 @@ int utf_to_cp(s32 *c, const u16 *codepage) int j; /* Look up codepage translation */ - for (j = 0; j < 0x80; ++j) { + for (j = 0; j < 0xA0; ++j) { if (*c == codepage[j]) { - *c = j + 0x80; + if (j < 0x20) + *c = j; + else + *c = j + 0x60; return 0; } } diff --git a/lib/efi_loader/efi_bootbin.c b/lib/efi_loader/efi_bootbin.c index 733cc1a61b5..b7910f78fb6 100644 --- a/lib/efi_loader/efi_bootbin.c +++ b/lib/efi_loader/efi_bootbin.c @@ -125,7 +125,7 @@ efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size) efi_handle_t mem_handle = NULL, handle; struct efi_device_path *file_path = NULL; struct efi_device_path *msg_path; - efi_status_t ret, ret2; + efi_status_t ret; u16 *load_options; if (!bootefi_device_path || !bootefi_image_path) { @@ -172,11 +172,17 @@ efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size) ret = do_bootefi_exec(handle, load_options); out: - ret2 = efi_uninstall_multiple_protocol_interfaces(mem_handle, - &efi_guid_device_path, - file_path, NULL); + if (mem_handle) { + efi_status_t r; + + r = efi_uninstall_multiple_protocol_interfaces( + mem_handle, &efi_guid_device_path, file_path, NULL); + if (r != EFI_SUCCESS) + log_err("Uninstalling protocol interfaces failed\n"); + } efi_free_pool(file_path); - return (ret != EFI_SUCCESS) ? ret : ret2; + + return ret; } /** diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c index 5dd9cc876e4..58761fae784 100644 --- a/lib/efi_loader/efi_helper.c +++ b/lib/efi_loader/efi_helper.c @@ -456,11 +456,11 @@ efi_status_t efi_install_fdt(void *fdt) return EFI_LOAD_ERROR; } - /* Create memory reservations as indicated by the device tree */ - efi_carve_out_dt_rsv(fdt); - - if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)) + if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)) { + /* Create memory reservations as indicated by the device tree */ + efi_carve_out_dt_rsv(fdt); return EFI_SUCCESS; + } /* Prepare device tree for payload */ ret = copy_fdt(&fdt); @@ -474,6 +474,9 @@ efi_status_t efi_install_fdt(void *fdt) return EFI_LOAD_ERROR; } + /* Create memory reservations as indicated by the device tree */ + efi_carve_out_dt_rsv(fdt); + efi_try_purge_kaslr_seed(fdt); if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) { diff --git a/lib/efi_loader/efi_unicode_collation.c b/lib/efi_loader/efi_unicode_collation.c index 2b6912c5092..627bb9123cf 100644 --- a/lib/efi_loader/efi_unicode_collation.c +++ b/lib/efi_loader/efi_unicode_collation.c @@ -256,7 +256,7 @@ static void EFIAPI efi_fat_to_str(struct efi_unicode_collation_protocol *this, for (i = 0; i < fat_size; ++i) { c = (unsigned char)fat[i]; if (c > 0x80) - c = codepage[c - 0x80]; + c = codepage[c - 0x60]; string[i] = c; if (!c) break; diff --git a/lib/efi_selftest/efi_selftest_textoutput.c b/lib/efi_selftest/efi_selftest_textoutput.c index cc44b38bc23..a3023c82567 100644 --- a/lib/efi_selftest/efi_selftest_textoutput.c +++ b/lib/efi_selftest/efi_selftest_textoutput.c @@ -31,6 +31,42 @@ static int execute(void) 0xD804, 0xDC22, 0}; + const u16 text[] = + u"This should render international characters as described\n" + u"U+00D6 \u00D6 - Latin capital letter O with diaresis\n" + u"U+00DF \u00DF - Latin small letter sharp s\n" + u"U+00E5 \u00E5 - Latin small letter a with ring above\n" + u"U+00E9 \u00E9 - Latin small letter e with acute\n" + u"U+00F1 \u00F1 - Latin small letter n with tilde\n" + u"U+00F6 \u00F6 - Latin small letter o with diaresis\n" + u"The following characters will render as '?' with bitmap fonts\n" + u"U+00F8 \u00F8 - Latin small letter o with stroke\n" + u"U+03AC \u03AC - Greek small letter alpha with tonus\n" + u"U+03BB \u03BB - Greek small letter lambda\n" + u"U+03C2 \u03C2 - Greek small letter final sigma\n" + u"U+1F19 \u1F19 - Greek capital letter epsilon with dasia\n"; + + const u16 boxes[] = + u"This should render as four boxes with text\n" + u"\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500" + u"\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500" + u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\n\u2502" + u" left top \u2502 right top \u2502\n\u251c\u2500" + u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500" + u"\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500" + u"\u2500\u2500\u2500\u2500\u2500\u2500\u2524\n\u2502 " + u"left bottom \u2502 right bottom \u2502\n\u2514\u2500\u2500\u2500" + u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2534" + u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500" + u"\u2500\u2500\u2500\u2500\u2518\n"; + + const u16 shapes[] = + u"Geometric shapes as described\n" + u"U+25B2 \u25B2 - Black up-pointing triangle\n" + u"U+25BA \u25BA - Black right-pointing pointer\n" + u"U+25BC \u25BC - Black down-pointing triangle\n" + u"U+25C4 \u25C4 - Black left-pointing pointer\n"; + /* SetAttribute */ efi_st_printf("\nColor palette\n"); for (foreground = 0; foreground < 0x10; ++foreground) { @@ -119,6 +155,24 @@ static int execute(void) return EFI_ST_FAILURE; } efi_st_printf("\n"); + ret = con_out->output_string(con_out, text); + if (ret != EFI_ST_SUCCESS) { + efi_st_error("OutputString failed for international chars\n"); + return EFI_ST_FAILURE; + } + efi_st_printf("\n"); + ret = con_out->output_string(con_out, boxes); + if (ret != EFI_ST_SUCCESS) { + efi_st_error("OutputString failed for box drawing chars\n"); + return EFI_ST_FAILURE; + } + efi_st_printf("\n"); + ret = con_out->output_string(con_out, shapes); + if (ret != EFI_ST_SUCCESS) { + efi_st_error("OutputString failed for geometric shapes\n"); + return EFI_ST_FAILURE; + } + efi_st_printf("\n"); return EFI_ST_SUCCESS; } diff --git a/lib/efi_selftest/efi_selftest_unicode_collation.c b/lib/efi_selftest/efi_selftest_unicode_collation.c index 32c99caf352..ad7dfa9fb9b 100644 --- a/lib/efi_selftest/efi_selftest_unicode_collation.c +++ b/lib/efi_selftest/efi_selftest_unicode_collation.c @@ -220,6 +220,18 @@ static int test_str_to_fat(void) return EFI_ST_FAILURE; } + /* + * Test unicode code points which map to CP 437 0x01 - 0x1f are + * converted to '_'. + */ + boottime->set_mem(fat, 16, 0); + ret = unicode_collation_protocol->str_to_fat(unicode_collation_protocol, + u"\u263a\u2666\u2022\u25d8\u2642\u2194\u00b6\u203c", 8, fat); + if (!ret || efi_st_strcmp_16_8(u"________", fat)) { + efi_st_error("str_to_fat returned %u, \"%s\"\n", ret, fat); + return EFI_ST_FAILURE; + } + return EFI_ST_SUCCESS; } diff --git a/lib/smbios.c b/lib/smbios.c index c83af730a91..b190b010f30 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -394,6 +394,7 @@ static int smbios_write_type1(ulong *current, int handle, } else { t->serial_number = smbios_add_prop(ctx, "serial", NULL); } + t->wakeup_type = SMBIOS_WAKEUP_TYPE_UNKNOWN; t->sku_number = smbios_add_prop(ctx, "sku", NULL); t->family = smbios_add_prop(ctx, "family", NULL); diff --git a/net/mdio-uclass.c b/net/mdio-uclass.c index 6fc7034111f..0ebfb2f1343 100644 --- a/net/mdio-uclass.c +++ b/net/mdio-uclass.c @@ -6,6 +6,8 @@ #include <common.h> #include <dm.h> +#include <dm/lists.h> +#include <eth_phy.h> #include <log.h> #include <malloc.h> #include <miiphy.h> @@ -121,6 +123,42 @@ static int mdio_reset(struct mii_dev *mii_bus) return dm_mdio_reset(mii_bus->priv); } +static int mdio_bind_phy_nodes(struct udevice *mdio_dev) +{ + ofnode mdio_node, phy_node; + struct udevice *phy_dev; + const char *node_name; + int ret; + + mdio_node = dev_ofnode(mdio_dev); + if (!ofnode_valid(mdio_node)) { + dev_dbg(mdio_dev, "invalid ofnode for mdio_dev\n"); + return -ENXIO; + } + + ofnode_for_each_subnode(phy_node, mdio_node) { + node_name = ofnode_get_name(phy_node); + dev_dbg(mdio_dev, "* Found child node: '%s'\n", node_name); + ret = device_bind_driver_to_node(mdio_dev, + "eth_phy_generic_drv", + node_name, phy_node, &phy_dev); + if (ret) { + dev_dbg(mdio_dev, " - Eth phy binding error: %d\n", ret); + continue; + } + + dev_dbg(mdio_dev, " - bound phy device: '%s'\n", node_name); + ret = device_probe(phy_dev); + if (ret) { + dev_dbg(mdio_dev, "Device '%s' probe failed\n", phy_dev->name); + device_unbind(phy_dev); + continue; + } + } + + return 0; +} + static int dm_mdio_post_probe(struct udevice *dev) { struct mdio_perdev_priv *pdata = dev_get_uclass_priv(dev); @@ -154,6 +192,9 @@ static int dm_mdio_post_probe(struct udevice *dev) } } + if (CONFIG_IS_ENABLED(DM_ETH_PHY)) + mdio_bind_phy_nodes(dev); + return mdio_register(pdata->mii_bus); } diff --git a/test/dm/acpi.c b/test/dm/acpi.c index c53ebcdb1c1..f14b3962f84 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -237,7 +237,7 @@ static int dm_test_acpi_fill_header(struct unit_test_state *uts) hdr.length = 0x11; hdr.revision = 0x22; hdr.checksum = 0x33; - hdr.aslc_revision = 0x44; + hdr.creator_revision = 0x44; acpi_fill_header(&hdr, "ABCD"); ut_asserteq_mem("ABCD", hdr.signature, sizeof(hdr.signature)); @@ -248,8 +248,8 @@ static int dm_test_acpi_fill_header(struct unit_test_state *uts) ut_asserteq_mem(OEM_TABLE_ID, hdr.oem_table_id, sizeof(hdr.oem_table_id)); ut_asserteq(OEM_REVISION, hdr.oem_revision); - ut_asserteq_mem(ASLC_ID, hdr.aslc_id, sizeof(hdr.aslc_id)); - ut_asserteq(0x44, hdr.aslc_revision); + ut_asserteq_mem(ASLC_ID, hdr.creator_id, sizeof(hdr.creator_id)); + ut_asserteq(0x44, hdr.creator_revision); return 0; } diff --git a/test/dm/button.c b/test/dm/button.c index 3318668df25..830d96fbef3 100644 --- a/test/dm/button.c +++ b/test/dm/button.c @@ -131,3 +131,99 @@ static int dm_test_button_keys_adc(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_button_keys_adc, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + +/* Test of the button uclass using the button_gpio driver */ +static int dm_test_button_cmd(struct unit_test_state *uts) +{ + struct udevice *btn1_dev, *btn2_dev, *gpio; + const char *envstr; + +#define BTN1_GPIO 3 +#define BTN2_GPIO 4 +#define BTN1_PASS_VAR "test_button_cmds_0" +#define BTN2_PASS_VAR "test_button_cmds_1" + + /* + * Buttons 1 and 2 are connected to gpio_a gpios 3 and 4 respectively. + * set the GPIOs to known values and then check that the appropriate + * commands are run when invoking process_button_cmds(). + */ + ut_assertok(uclass_get_device(UCLASS_BUTTON, 1, &btn1_dev)); + ut_assertok(uclass_get_device(UCLASS_BUTTON, 2, &btn2_dev)); + ut_assertok(uclass_get_device(UCLASS_GPIO, 1, &gpio)); + + /* + * Map a command to button 1 and check that it process_button_cmds() + * runs it if called with button 1 pressed. + */ + ut_assertok(env_set("button_cmd_0_name", "button1")); + ut_assertok(env_set("button_cmd_0", "env set " BTN1_PASS_VAR " PASS")); + ut_assertok(sandbox_gpio_set_value(gpio, BTN1_GPIO, 1)); + /* Sanity check that the button is actually pressed */ + ut_asserteq(BUTTON_ON, button_get_state(btn1_dev)); + process_button_cmds(); + ut_assertnonnull((envstr = env_get(BTN1_PASS_VAR))); + ut_asserteq_str(envstr, "PASS"); + + /* Clear result */ + ut_assertok(env_set(BTN1_PASS_VAR, NULL)); + + /* + * Map a command for button 2, press it, check that only the command + * for button 1 runs because it comes first and is also pressed. + */ + ut_assertok(env_set("button_cmd_1_name", "button2")); + ut_assertok(env_set("button_cmd_1", "env set " BTN2_PASS_VAR " PASS")); + ut_assertok(sandbox_gpio_set_value(gpio, BTN2_GPIO, 1)); + ut_asserteq(BUTTON_ON, button_get_state(btn2_dev)); + process_button_cmds(); + /* Check that button 1 triggered again */ + ut_assertnonnull((envstr = env_get(BTN1_PASS_VAR))); + ut_asserteq_str(envstr, "PASS"); + /* And button 2 didn't */ + ut_assertnull(env_get(BTN2_PASS_VAR)); + + /* Clear result */ + ut_assertok(env_set(BTN1_PASS_VAR, NULL)); + + /* + * Release button 1 and check that the command for button 2 is run + */ + ut_assertok(sandbox_gpio_set_value(gpio, BTN1_GPIO, 0)); + process_button_cmds(); + ut_assertnull(env_get(BTN1_PASS_VAR)); + /* Check that the command for button 2 ran */ + ut_assertnonnull((envstr = env_get(BTN2_PASS_VAR))); + ut_asserteq_str(envstr, "PASS"); + + /* Clear result */ + ut_assertok(env_set(BTN2_PASS_VAR, NULL)); + + /* + * Unset "button_cmd_0_name" and check that no commands run even + * with both buttons pressed. + */ + ut_assertok(env_set("button_cmd_0_name", NULL)); + /* Press button 1 (button 2 is already pressed )*/ + ut_assertok(sandbox_gpio_set_value(gpio, BTN1_GPIO, 1)); + ut_asserteq(BUTTON_ON, button_get_state(btn1_dev)); + process_button_cmds(); + ut_assertnull(env_get(BTN1_PASS_VAR)); + ut_assertnull(env_get(BTN2_PASS_VAR)); + + /* + * Check that no command is run if the button name is wrong. + */ + ut_assertok(env_set("button_cmd_0_name", "invalid_button")); + process_button_cmds(); + ut_assertnull(env_get(BTN1_PASS_VAR)); + ut_assertnull(env_get(BTN2_PASS_VAR)); + +#undef BTN1_PASS_VAR +#undef BTN2_PASS_VAR +#undef BTN1_GPIO +#undef BTN2_GPIO + + return 0; +} +DM_TEST(dm_test_button_cmd, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); diff --git a/test/py/tests/test_reset.py b/test/py/tests/test_reset.py new file mode 100644 index 00000000000..00fc31da57d --- /dev/null +++ b/test/py/tests/test_reset.py @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0 +# (C) Copyright 2023, Advanced Micro Devices, Inc. + +""" +Note: This test doesn't rely on boardenv_* configuration value but they can +change test behavior. + +For example: + +# Setup env__reset_test_skip to True if reset test is not possible or desired +# and should be skipped. +env__reset_test_skip = True + +# Setup env__reset_test to set the bootmode if 'modeboot' u-boot environment +# variable is not set. Test will be skipped if bootmode is not set in both +# places i.e, boardenv and modeboot u-boot environment variable +env__reset_test = { + 'bootmode': 'qspiboot', +} + +# This test will be also skipped if the bootmode is detected to JTAG. +""" + +import pytest +import test_000_version + +def setup_reset_env(u_boot_console): + if u_boot_console.config.env.get('env__reset_test_skip', False): + pytest.skip('reset test is not enabled') + + output = u_boot_console.run_command('echo $modeboot') + if output: + bootmode = output + else: + f = u_boot_console.config.env.get('env__reset_test', None) + if not f: + pytest.skip('bootmode cannot be determined') + bootmode = f.get('bootmode', 'jtagboot') + + if 'jtag' in bootmode: + pytest.skip('skipping reset test due to jtag bootmode') + +@pytest.mark.buildconfigspec('hush_parser') +def test_reset(u_boot_console): + """Test the reset command in non-JTAG bootmode. + It does COLD reset, which resets CPU, DDR and peripherals + """ + setup_reset_env(u_boot_console) + u_boot_console.run_command('reset', wait_for_reboot=True) + + # Checks the u-boot command prompt's functionality after reset + test_000_version.test_version(u_boot_console) + +@pytest.mark.buildconfigspec('hush_parser') +def test_reset_w(u_boot_console): + """Test the reset -w command in non-JTAG bootmode. + It does WARM reset, which resets CPU but keep DDR/peripherals active. + """ + setup_reset_env(u_boot_console) + u_boot_console.run_command('reset -w', wait_for_reboot=True) + + # Checks the u-boot command prompt's functionality after reset + test_000_version.test_version(u_boot_console) diff --git a/test/py/tests/test_saveenv.py b/test/py/tests/test_saveenv.py new file mode 100644 index 00000000000..7faa3bdf93d --- /dev/null +++ b/test/py/tests/test_saveenv.py @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: GPL-2.0 +# (C) Copyright 2023, Advanced Micro Devices, Inc. + +""" +Note: This test doesn't rely on boardenv_* configuration value but they can +change test behavior. + +For example: + +# Setup env__saveenv_test_skip to True if saveenv test is not possible or +# desired and should be skipped. +env__saveenv_test_skip = True + +# Setup env__saveenv_test to set the bootmode if 'modeboot' u-boot environment +# variable is not set. Test will be skipped if bootmode is not set in both +# places i.e, boardenv and modeboot u-boot environment variable +env__saveenv_test = { + 'bootmode': 'qspiboot', +} + +# This test will be also skipped if the bootmode is detected to JTAG. +""" + +import pytest +import random +import ipaddress +import string +import uuid + +# Setup the env +def setup_saveenv_env(u_boot_console): + if u_boot_console.config.env.get('env__saveenv_test_skip', False): + pytest.skip('saveenv test is not enabled') + + output = u_boot_console.run_command('echo $modeboot') + if output: + bootmode = output + else: + f = u_boot_console.config.env.get('env__saveenv_test', None) + if not f: + pytest.skip('bootmode cannot be determined') + bootmode = f.get('bootmode', 'jtagboot') + + if 'jtag' in bootmode: + pytest.skip('skipping saveenv test due to jtag bootmode') + +# Check return code +def ret_code(u_boot_console): + return u_boot_console.run_command('echo $?') + +# Verify env variable +def check_env(u_boot_console, var_name, var_value): + if var_value: + output = u_boot_console.run_command(f'printenv {var_name}') + var_value = str(var_value) + if (var_value.startswith("'") and var_value.endswith("'")) or ( + var_value.startswith('"') and var_value.endswith('"') + ): + var_value = var_value.split(var_value[-1])[1] + assert var_value in output + assert ret_code(u_boot_console).endswith('0') + else: + u_boot_console.p.send(f'printenv {var_name}\n') + output = u_boot_console.p.expect(['not defined']) + assert output == 0 + assert ret_code(u_boot_console).endswith('1') + +# Set env variable +def set_env(u_boot_console, var_name, var_value): + u_boot_console.run_command(f'setenv {var_name} {var_value}') + assert ret_code(u_boot_console).endswith('0') + check_env(u_boot_console, var_name, var_value) + +@pytest.mark.buildconfigspec('cmd_saveenv') +@pytest.mark.buildconfigspec('hush_parser') +def test_saveenv(u_boot_console): + """Test the saveenv command in non-JTAG bootmode. + It saves the U-Boot environment in persistent storage. + """ + setup_saveenv_env(u_boot_console) + + # Set env for random mac address + rand_mac = '%02x:%02x:%02x:%02x:%02x:%02x' % ( + random.randint(0, 255), + random.randint(0, 255), + random.randint(0, 255), + random.randint(0, 255), + random.randint(0, 255), + random.randint(0, 255), + ) + set_env(u_boot_console, 'mac_addr', rand_mac) + + # Set env for random IPv4 address + rand_ipv4 = ipaddress.IPv4Address._string_from_ip_int( + random.randint(0, ipaddress.IPv4Address._ALL_ONES) + ) + set_env(u_boot_console, 'ipv4_addr', rand_ipv4) + + # Set env for random IPv6 address + rand_ipv6 = ipaddress.IPv6Address._string_from_ip_int( + random.randint(0, ipaddress.IPv6Address._ALL_ONES) + ) + set_env(u_boot_console, 'ipv6_addr', rand_ipv6) + + # Set env for random number + rand_num = random.randrange(1, 10**9) + set_env(u_boot_console, 'num_var', rand_num) + + # Set env for uuid + uuid_str = uuid.uuid4().hex.lower() + set_env(u_boot_console, 'uuid_var', uuid_str) + + # Set env for random string including special characters + sc = "!#%&()*+,-./:;<=>?@[\\]^_`{|}~" + rand_str = ''.join( + random.choices(' ' + string.ascii_letters + sc + string.digits, k=300) + ) + set_env(u_boot_console, 'str_var', f'"{rand_str}"') + + # Set env for empty string + set_env(u_boot_console, 'empty_var', '') + + # Save the env variables + u_boot_console.run_command('saveenv') + assert ret_code(u_boot_console).endswith('0') + + # Reboot + u_boot_console.run_command('reset', wait_for_reboot=True) + + # Verify the saved env variables + check_env(u_boot_console, 'mac_addr', rand_mac) + check_env(u_boot_console, 'ipv4_addr', rand_ipv4) + check_env(u_boot_console, 'ipv6_addr', rand_ipv6) + check_env(u_boot_console, 'num_var', rand_num) + check_env(u_boot_console, 'uuid_var', uuid_str) + check_env(u_boot_console, 'str_var', rand_str) + check_env(u_boot_console, 'empty_var', '') diff --git a/tools/patman/patman.rst b/tools/patman/patman.rst index e01355824c5..f4588c00fc1 100644 --- a/tools/patman/patman.rst +++ b/tools/patman/patman.rst @@ -144,7 +144,7 @@ patman.py. For reference, the useful ones (at the moment) shown below process_tags: False verbose: True smtp_server: /path/to/sendmail - patchwork_server: https://patchwork.ozlabs.org + patchwork_url: https://patchwork.ozlabs.org If you want to adjust settings (or aliases) that affect just a single project you can add a section that looks like [project_settings] or @@ -248,9 +248,9 @@ Series-links: [id | version:id]... Series-patchwork-url: url This allows specifying the Patchwork URL for a branch. This overrides - both the setting files and the command-line argument. The URL should - include the protocol and web site, with no trailing slash, for example - 'https://patchwork.ozlabs.org/project' + both the setting files ("patchwork_url") and the command-line argument. + The URL should include the protocol and web site, with no trailing slash, + for example 'https://patchwork.ozlabs.org/project' Cover-letter: Sets the cover letter contents for the series. The first line |