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-rw-r--r--arch/arm/dts/Makefile2
-rw-r--r--arch/arm/dts/imx8mm-cl-iot-gate.dts1
-rw-r--r--arch/arm/dts/imx8mp-dhcom-drc02-u-boot.dtsi6
-rw-r--r--arch/arm/dts/imx8mp-dhcom-drc02.dts230
-rw-r--r--arch/arm/dts/imx8mp-dhcom-picoitx-u-boot.dtsi6
-rw-r--r--arch/arm/dts/imx8mp-dhcom-picoitx.dts152
-rw-r--r--arch/arm/mach-imx/cmd_mfgprot.c2
-rw-r--r--arch/arm/mach-imx/imx8m/soc.c1
-rw-r--r--configs/imx8mp_dhcom_drc02_defconfig277
-rw-r--r--configs/imx8mp_dhcom_picoitx_defconfig273
-rw-r--r--configs/lxr2_defconfig3
-rw-r--r--drivers/gpio/Kconfig6
-rw-r--r--drivers/gpio/Makefile2
-rw-r--r--drivers/mmc/fsl_esdhc_imx.c44
-rw-r--r--drivers/power/pmic/da9063.c12
-rw-r--r--drivers/watchdog/Kconfig6
-rw-r--r--drivers/watchdog/Makefile1
-rw-r--r--drivers/watchdog/da9063-wdt.c149
-rw-r--r--include/fsl_esdhc_imx.h1
19 files changed, 1159 insertions, 15 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d46f0bda1a8..65176c8fb83 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -968,9 +968,11 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-dhcom-som-overlay-eth2xfast.dtbo \
imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \
imx8mp-debix-model-a.dtb \
+ imx8mp-dhcom-drc02.dtb \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-rev100.dtbo \
+ imx8mp-dhcom-picoitx.dtb \
imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-msc-sm2s.dtb \
imx8mq-pico-pi.dtb \
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate.dts b/arch/arm/dts/imx8mm-cl-iot-gate.dts
index 425701204a0..aa6ca070bff 100644
--- a/arch/arm/dts/imx8mm-cl-iot-gate.dts
+++ b/arch/arm/dts/imx8mm-cl-iot-gate.dts
@@ -350,6 +350,7 @@
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
bus-width = <8>;
non-removable;
+ no-mmc-hs400;
status = "okay";
};
diff --git a/arch/arm/dts/imx8mp-dhcom-drc02-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-drc02-u-boot.dtsi
new file mode 100644
index 00000000000..8a23b117d9a
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-drc02-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Marek Vasut <marex@denx.de>
+ */
+
+#include "imx8mp-dhcom-u-boot.dtsi"
diff --git a/arch/arm/dts/imx8mp-dhcom-drc02.dts b/arch/arm/dts/imx8mp-dhcom-drc02.dts
new file mode 100644
index 00000000000..b3ab6e94508
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-drc02.dts
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Marek Vasut <marex@denx.de>
+ *
+ * DHCOM iMX8MP variant:
+ * DHCM-iMX8ML8-C160-R204-F1638-SPI16-E2-CAN2-RTC-I-01D2
+ * DHCOM PCB number: 660-100 or newer
+ * DRC02 PCB number: 568-100 or newer
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include "imx8mp-dhcom-som.dtsi"
+
+/ {
+ model = "DH electronics i.MX8M Plus DHCOM on DRC02";
+ compatible = "dh,imx8mp-dhcom-drc02", "dh,imx8mp-dhcom-som",
+ "fsl,imx8mp";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+};
+
+&eqos { /* First ethernet */
+ pinctrl-0 = <&pinctrl_eqos_rmii>;
+ phy-handle = <&ethphy0f>;
+ phy-mode = "rmii";
+
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
+ <&clk IMX8MP_SYS_PLL2_100M>,
+ <&clk IMX8MP_SYS_PLL2_50M>;
+ assigned-clock-rates = <0>, <100000000>, <50000000>;
+};
+
+&ethphy0g { /* Micrel KSZ9131RNXI */
+ status = "disabled";
+};
+
+&ethphy0f { /* SMSC LAN8740Ai */
+ status = "okay";
+};
+
+&fec { /* Second ethernet */
+ pinctrl-0 = <&pinctrl_fec_rmii>;
+ phy-handle = <&ethphy1f>;
+ phy-mode = "rmii";
+ status = "okay";
+
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
+ <&clk IMX8MP_SYS_PLL2_100M>,
+ <&clk IMX8MP_SYS_PLL2_50M>,
+ <&clk IMX8MP_SYS_PLL2_50M>;
+ assigned-clock-rates = <0>, <100000000>, <50000000>, <0>;
+};
+
+&ethphy1f { /* SMSC LAN8740Ai */
+ status = "okay";
+};
+
+&flexcan1 {
+ status = "okay";
+};
+
+&flexcan2 {
+ status = "okay";
+};
+
+&gpio1 {
+ gpio-line-names =
+ "DRC02-In1", "", "", "", "", "DHCOM-I", "DRC02-HW2", "DRC02-HW0",
+ "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+
+ /*
+ * NOTE: On DRC02, the RS485_RX_En is controlled by a separate
+ * GPIO line, however the i.MX8 UART driver assumes RX happens
+ * during TX anyway and that it only controls drive enable DE
+ * line. Hence, the RX is always enabled here.
+ */
+ rs485-rx-en-hog {
+ gpio-hog;
+ gpios = <13 0>; /* GPIO Q */
+ line-name = "rs485-rx-en";
+ output-low;
+ };
+};
+
+&gpio2 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "DHCOM-O", "DHCOM-N", "", "SOM-HW1", "", "", "", "",
+ "", "", "", "", "DRC02-In2", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "SOM-HW0", "",
+ "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
+ "SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "SOM-HW1", "", "", "", "",
+ "", "", "", "DRC02-Out2", "", "", "", "";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "", "", "DHCOM-C", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "DHCOM-E", "DRC02-Out1",
+ "", "", "", "", "", "", "", "";
+};
+
+&i2c3 {
+ /* Resistive touch controller not populated on this one SoM variant. */
+ touchscreen@49 {
+ status = "disabled";
+ };
+};
+
+&pcie_phy {
+ status = "disabled";
+};
+
+&pcie {
+ status = "disabled";
+};
+
+/* Console UART */
+&pinctrl_uart1 {
+ fsl,pins = <
+ /* No pull-ups on DRC02, enable in-SoC pull-ups */
+ MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x149
+ MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x149
+ >;
+};
+
+&pinctrl_uart3 {
+ fsl,pins = <
+ /* No pull-ups on DRC02, enable in-SoC pull-ups */
+ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x149
+ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x149
+ >;
+};
+
+&uart1 {
+ /*
+ * Due to the use of CAN2 the signals for CAN2 Tx and Rx are routed to
+ * DHCOM UART1 RTS/CTS pins. Therefore this UART have to use DHCOM GPIOs
+ * for RTS/CTS. So configure DHCOM GPIO I as RTS and GPIO M as CTS.
+ */
+ /delete-property/ uart-has-rtscts;
+ cts-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; /* GPIO M */
+ pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>;
+ pinctrl-names = "default";
+ rts-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */
+};
+
+&uart3 {
+ /*
+ * On DRC02 this UART is used as RS485 interface and RS485_TX_En is
+ * controlled by DHCOM GPIO P. So remove RTS/CTS pins and the property
+ * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via
+ * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1
+ * node above.
+ */
+ /delete-property/ uart-has-rtscts;
+ linux,rs485-enabled-at-boot-time;
+ pinctrl-0 = <&pinctrl_uart3 &pinctrl_dhcom_p &pinctrl_dhcom_q>;
+ pinctrl-names = "default";
+ rts-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* GPIO P */
+};
+
+/* No WiFi/BT chipset on this SoM variant. */
+&uart2 {
+ bluetooth {
+ status = "disabled";
+ };
+};
+
+/* USB_OTG port is not routed out on DRC02. */
+&usb3_0 {
+ status = "disabled";
+};
+
+&usb_dwc3_0 {
+ status = "disabled";
+};
+
+/* USB_HOST port has USB Hub connected to it, PWR/OC pins are unused */
+&usb3_1 {
+ fsl,disable-port-power-control;
+ fsl,permanently-attached;
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+};
+
+/* No WiFi/BT chipset on this SoM variant. */
+&usdhc1 {
+ status = "disabled";
+};
+
+&iomuxc {
+ /*
+ * GPIO I is connected to UART1_RTS
+ * GPIO M is connected to UART1_CTS
+ * GPIO P is connected to RS485_TX_En
+ * GPIO Q is connected to RS485_RX_En
+ */
+ pinctrl-0 = <&pinctrl_hog_base
+ &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
+ &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
+ &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_j
+ &pinctrl_dhcom_k &pinctrl_dhcom_l &pinctrl_dhcom_n
+ &pinctrl_dhcom_o &pinctrl_dhcom_r &pinctrl_dhcom_s
+ &pinctrl_dhcom_int>;
+};
diff --git a/arch/arm/dts/imx8mp-dhcom-picoitx-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-picoitx-u-boot.dtsi
new file mode 100644
index 00000000000..4e95cd0e483
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-picoitx-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023-2024 Marek Vasut <marex@denx.de>
+ */
+
+#include "imx8mp-dhcom-u-boot.dtsi"
diff --git a/arch/arm/dts/imx8mp-dhcom-picoitx.dts b/arch/arm/dts/imx8mp-dhcom-picoitx.dts
new file mode 100644
index 00000000000..285aaa5b6c0
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-picoitx.dts
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023-2024 Marek Vasut <marex@denx.de>
+ *
+ * DHCOM iMX8MP variant:
+ * DHCM-iMX8ML8-C160-R204-F1638-SPI16-E-SD-RTC-T-RGB-I-01D2
+ * DHCOM PCB number: 660-200 or newer
+ * PicoITX PCB number: 487-600 or newer
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "imx8mp-dhcom-som.dtsi"
+
+/ {
+ model = "DH electronics i.MX8M Plus DHCOM PicoITX";
+ compatible = "dh,imx8mp-dhcom-picoitx", "dh,imx8mp-dhcom-som",
+ "fsl,imx8mp";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ led {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_YELLOW>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */
+ pinctrl-0 = <&pinctrl_dhcom_i>;
+ pinctrl-names = "default";
+ };
+ };
+};
+
+&eqos { /* First ethernet */
+ pinctrl-0 = <&pinctrl_eqos_rmii>;
+ phy-handle = <&ethphy0f>;
+ phy-mode = "rmii";
+
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
+ <&clk IMX8MP_SYS_PLL2_100M>,
+ <&clk IMX8MP_SYS_PLL2_50M>;
+ assigned-clock-rates = <0>, <100000000>, <50000000>;
+};
+
+&ethphy0g { /* Micrel KSZ9131RNXI */
+ status = "disabled";
+};
+
+&ethphy0f { /* SMSC LAN8740Ai */
+ status = "okay";
+};
+
+&fec {
+ status = "disabled";
+};
+
+&flexcan1 {
+ status = "okay";
+};
+
+&gpio1 {
+ gpio-line-names =
+ "DHCOM-G", "", "", "",
+ "", "DHCOM-I", "PicoITX-HW0", "PicoITX-HW2",
+ "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "PicoITX-HW1", "", "", "", "",
+ "", "", "", "", "DHCOM-INT", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "SOM-HW1", "", "", "", "",
+ "", "", "", "PicoITX-Out2", "", "", "", "";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "", "", "PicoITX-In2", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "",
+ "", "", "PicoITX-In1", "PicoITX-Out1",
+ "", "", "", "", "", "", "", "";
+};
+
+/* No HS connector on this SoM variant, so no HDMI, PCIe and only USB HS. */
+&pcie_phy {
+ status = "disabled";
+};
+
+&pcie {
+ status = "disabled";
+};
+
+/* No WiFi/BT chipset on this SoM variant. */
+&uart2 {
+ bluetooth {
+ status = "disabled";
+ };
+};
+
+/* USB_OTG port is not routed out on PicoITX. */
+&usb3_0 {
+ status = "disabled";
+};
+
+&usb_dwc3_0 {
+ status = "disabled";
+};
+
+&usb3_1 {
+ fsl,over-current-active-low;
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+};
+
+/* No WiFi/BT chipset on this SoM variant. */
+&usdhc1 {
+ status = "disabled";
+};
+
+&iomuxc {
+ /*
+ * The following DHCOM GPIOs are used on this board.
+ * Therefore, they have been removed from the list below.
+ * I: yellow led
+ */
+ pinctrl-0 = <&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
+ &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
+ &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_j
+ &pinctrl_dhcom_k &pinctrl_dhcom_l &pinctrl_dhcom_m
+ &pinctrl_dhcom_n &pinctrl_dhcom_o &pinctrl_dhcom_p
+ &pinctrl_dhcom_q &pinctrl_dhcom_r &pinctrl_dhcom_s
+ &pinctrl_dhcom_int>;
+};
diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c
index 9f37e611a1e..8f66de699c5 100644
--- a/arch/arm/mach-imx/cmd_mfgprot.c
+++ b/arch/arm/mach-imx/cmd_mfgprot.c
@@ -143,6 +143,6 @@ U_BOOT_LONGHELP(mfgprot,
U_BOOT_CMD(
mfgprot, 4, 1, do_mfgprot,
- "Manufacturing Protection\n",
+ "Manufacturing Protection",
mfgprot_help_text
);
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 46974bf0618..5293cb85e56 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1004,6 +1004,7 @@ int disable_vpu_nodes(void *blob)
"/soc@0/video-codec@38300000",
"/soc@0/video-codec@38310000",
"/soc@0/blk-ctrl@38330000",
+ "/soc@0/blk-ctl@38330000",
};
if (is_imx8mq())
diff --git a/configs/imx8mp_dhcom_drc02_defconfig b/configs/imx8mp_dhcom_drc02_defconfig
new file mode 100644
index 00000000000..7c684d3bea5
--- /dev/null
+++ b/configs/imx8mp_dhcom_drc02_defconfig
@@ -0,0 +1,277 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xFE0000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-drc02"
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y
+CONFIG_DM_RESET=y
+CONFIG_SYS_MONITOR_LEN=1048576
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
+CONFIG_SPL_STACK=0x96fc00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x96fc00
+CONFIG_SPL_BSS_MAX_SIZE=0x400
+CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_DEBUG_UART_BASE=0x30860000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_ENV_OFFSET_REDUND=0xFF0000
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
+CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
+CONFIG_SYS_BOOTM_LEN=0x8000000
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run dh_update_env distro_bootcmd ; reset"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT=""
+CONFIG_DEFAULT_FDT_FILE="imx8mp-dhcom-drc02.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2081
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+# CONFIG_SPL_FIT_IMAGE_TINY is not set
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_SIZE=16384
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_SHA1SUM_VERIFY=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MBR=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_BKOPS_ENABLE=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_WGET=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_KASLRSEED=y
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_SMC=y
+CONFIG_HASH_VERIFY=y
+CONFIG_CMD_BTRFS=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
+CONFIG_MMC_SPEED_MODE_SET=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE_AUTO=y
+CONFIG_ENV_SPI_MAX_HZ=80000000
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_TSIZE=y
+CONFIG_PROT_TCP_SACK=y
+CONFIG_IPV6=y
+CONFIG_SPL_DM=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_FSL_CAAM=y
+CONFIG_IMX8M_DRAM_INLINE_ECC=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_TIMEOUT=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_GPIO_HOG=y
+CONFIG_SPL_GPIO_HOG=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+# CONFIG_INPUT is not set
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_PHY_SMSC=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_IMX=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PHY_IMX8M_PCIE=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_SPL_DM_REGULATOR_PCA9450=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RNG=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_M41T62=y
+CONFIG_CONS_INDEX=2
+CONFIG_DM_SERIAL=y
+# CONFIG_SPL_DM_SERIAL is not set
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="DH electronics"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_FUNCTION_ACM=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mp_dhcom_picoitx_defconfig b/configs/imx8mp_dhcom_picoitx_defconfig
new file mode 100644
index 00000000000..4d8ce2dba4b
--- /dev/null
+++ b/configs/imx8mp_dhcom_picoitx_defconfig
@@ -0,0 +1,273 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xFE0000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-picoitx"
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y
+CONFIG_DM_RESET=y
+CONFIG_SYS_MONITOR_LEN=1048576
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
+CONFIG_SPL_STACK=0x96fc00
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x96fc00
+CONFIG_SPL_BSS_MAX_SIZE=0x400
+CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_DEBUG_UART_BASE=0x30860000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_ENV_OFFSET_REDUND=0xFF0000
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
+CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
+CONFIG_SYS_BOOTM_LEN=0x8000000
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run dh_update_env distro_bootcmd ; reset"
+CONFIG_USE_PREBOOT=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-dhcom-picoitx.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2081
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+# CONFIG_SPL_FIT_IMAGE_TINY is not set
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_SIZE=16384
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_SHA1SUM_VERIFY=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MBR=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_BKOPS_ENABLE=y
+CONFIG_MMC_SPEED_MODE_SET=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_WGET=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_KASLRSEED=y
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_SMC=y
+CONFIG_HASH_VERIFY=y
+CONFIG_CMD_BTRFS=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE_AUTO=y
+CONFIG_ENV_SPI_MAX_HZ=80000000
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_TSIZE=y
+CONFIG_PROT_TCP_SACK=y
+CONFIG_IPV6=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_FSL_CAAM=y
+CONFIG_IMX8M_DRAM_INLINE_ECC=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_TIMEOUT=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_GPIO_HOG=y
+CONFIG_SPL_GPIO_HOG=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+# CONFIG_INPUT is not set
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_PHY_SMSC=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_SPL_DM_REGULATOR_PCA9450=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RNG=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_M41T62=y
+CONFIG_CONS_INDEX=2
+CONFIG_DM_SERIAL=y
+# CONFIG_SPL_DM_SERIAL is not set
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="DH electronics"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_FUNCTION_ACM=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_IMX_WATCHDOG=y
diff --git a/configs/lxr2_defconfig b/configs/lxr2_defconfig
index 855366d4215..2659b1f14b7 100644
--- a/configs/lxr2_defconfig
+++ b/configs/lxr2_defconfig
@@ -104,6 +104,8 @@ CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_DA9063=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
@@ -116,3 +118,4 @@ CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_SYSRESET_WATCHDOG_AUTO=y
CONFIG_IMX_THERMAL=y
+CONFIG_WDT_DA9063=y
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 3996333fe8d..1e5711663eb 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -700,4 +700,10 @@ config RZG2L_GPIO
Support the gpio functionality of the pin function controller (PFC)
on the Renesas RZ/G2L SoC family.
+config SPL_ADP5585_GPIO
+ bool "ADP5585 GPIO driver in SPL"
+ depends on SPL_DM_GPIO && SPL_I2C
+ help
+ Support ADP5585 GPIO expander in SPL.
+
endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index da0faf05246..56c20e4c635 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -76,5 +76,5 @@ obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o
obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o
obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o
obj-$(CONFIG_FTGPIO010) += ftgpio010.o
-obj-$(CONFIG_ADP5585_GPIO) += adp5585_gpio.o
+obj-$(CONFIG_$(SPL_)ADP5585_GPIO) += adp5585_gpio.o
obj-$(CONFIG_RZG2L_GPIO) += rzg2l-gpio.o
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 03de7dcd505..fb410104c1f 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -148,6 +148,7 @@ struct fsl_esdhc_priv {
struct fsl_esdhc *esdhc_regs;
unsigned int sdhc_clk;
struct clk per_clk;
+ struct clk_bulk clk_bulk;
unsigned int clock;
unsigned int mode;
#if !CONFIG_IS_ENABLED(DM_MMC)
@@ -986,11 +987,11 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
ulong start;
/* Reset the entire host controller */
- esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
+ esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA | SYSCTL_RSTT);
/* Wait until the controller is available */
start = get_timer(0);
- while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
+ while ((esdhc_read32(&regs->sysctl) & (SYSCTL_RSTA | SYSCTL_RSTT))) {
if (get_timer(start) > 1000)
return -ETIMEDOUT;
}
@@ -1034,6 +1035,11 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
/* Set timout to the maximum value */
esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
+ /* max 1ms delay with clock on for initialization */
+ esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+ udelay(1000);
+ esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+
return 0;
}
@@ -1089,11 +1095,11 @@ static int esdhc_reset(struct fsl_esdhc *regs)
ulong start;
/* reset the controller */
- esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
+ esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA | SYSCTL_RSTT);
/* hardware clears the bit when it is done */
start = get_timer(0);
- while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
+ while ((esdhc_read32(&regs->sysctl) & (SYSCTL_RSTA | SYSCTL_RSTT))) {
if (get_timer(start) > 100) {
printf("MMC/SD: Reset never completed.\n");
return -ETIMEDOUT;
@@ -1188,8 +1194,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
esdhc_write32(&regs->irqstaten, SDHCI_IRQ_EN_BITS);
cfg = &plat->cfg;
- if (!CONFIG_IS_ENABLED(DM_MMC))
- memset(cfg, '\0', sizeof(*cfg));
caps = esdhc_read32(&regs->hostcapblt);
@@ -1323,6 +1327,8 @@ int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
break;
default:
printf("invalid max bus width %u\n", cfg->max_bus_width);
+ free(plat);
+ free(priv);
return -EINVAL;
}
@@ -1521,14 +1527,21 @@ static int fsl_esdhc_probe(struct udevice *dev)
#if CONFIG_IS_ENABLED(CLK)
/* Assigned clock already set clock */
- ret = clk_get_by_name(dev, "per", &priv->per_clk);
+ ret = clk_get_bulk(dev, &priv->clk_bulk);
if (ret) {
- printf("Failed to get per_clk\n");
+ dev_err(dev, "Failed to get clks: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_enable_bulk(&priv->clk_bulk);
+ if (ret) {
+ dev_err(dev, "Failed to enable clks: %d\n", ret);
return ret;
}
- ret = clk_enable(&priv->per_clk);
+
+ ret = clk_get_by_name(dev, "per", &priv->per_clk);
if (ret) {
- printf("Failed to enable per_clk\n");
+ printf("Failed to get per_clk\n");
return ret;
}
@@ -1561,7 +1574,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
upriv->mmc = mmc;
- return esdhc_init_common(priv, mmc);
+ return 0;
}
static int fsl_esdhc_get_cd(struct udevice *dev)
@@ -1613,6 +1626,14 @@ static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
return esdhc_wait_dat0_common(priv, state, timeout_us);
}
+static int fsl_esdhc_reinit(struct udevice *dev)
+{
+ struct fsl_esdhc_plat *plat = dev_get_plat(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+ return esdhc_init_common(priv, &plat->mmc);
+}
+
static const struct dm_mmc_ops fsl_esdhc_ops = {
.get_cd = fsl_esdhc_get_cd,
.send_cmd = fsl_esdhc_send_cmd,
@@ -1624,6 +1645,7 @@ static const struct dm_mmc_ops fsl_esdhc_ops = {
.set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
#endif
.wait_dat0 = fsl_esdhc_wait_dat0,
+ .reinit = fsl_esdhc_reinit,
};
static struct esdhc_soc_data usdhc_imx7d_data = {
diff --git a/drivers/power/pmic/da9063.c b/drivers/power/pmic/da9063.c
index 7bd3df39142..59c65702863 100644
--- a/drivers/power/pmic/da9063.c
+++ b/drivers/power/pmic/da9063.c
@@ -7,6 +7,9 @@
#include <fdtdec.h>
#include <errno.h>
#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
#include <i2c.h>
#include <log.h>
#include <linux/printk.h>
@@ -86,6 +89,7 @@ static int da9063_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
static int da9063_bind(struct udevice *dev)
{
ofnode regulators_node;
+ struct driver *drv;
int children;
regulators_node = dev_read_subnode(dev, "regulators");
@@ -101,8 +105,12 @@ static int da9063_bind(struct udevice *dev)
if (!children)
debug("%s: %s - no child found\n", __func__, dev->name);
- /* Always return success for this device */
- return 0;
+ drv = lists_driver_lookup_name("da9063-wdt");
+ if (!drv)
+ return 0;
+
+ return device_bind_with_driver_data(dev, drv, "da9063-wdt", dev->driver_data,
+ dev_ofnode(dev), &dev);
}
static int da9063_probe(struct udevice *dev)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 0c3e9913318..90bc5653ee3 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -169,6 +169,12 @@ config WDT_CORTINA
This driver support all CPU ISAs supported by Cortina
Access CAxxxx SoCs.
+config WDT_DA9063
+ bool "DA9063 watchdog timer support"
+ depends on WDT && DM_PMIC_DA9063
+ help
+ Enable support for the watchdog timer in Dialog DA9063.
+
config WDT_GPIO
bool "External gpio watchdog support"
depends on WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 7b39adcf0ff..6b564b7f96d 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o
obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
+obj-$(CONFIG_WDT_DA9063) += da9063-wdt.o
obj-$(CONFIG_WDT_FTWDT010) += ftwdt010_wdt.o
obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o
obj-$(CONFIG_WDT_MAX6370) += max6370_wdt.o
diff --git a/drivers/watchdog/da9063-wdt.c b/drivers/watchdog/da9063-wdt.c
new file mode 100644
index 00000000000..b7216b57863
--- /dev/null
+++ b/drivers/watchdog/da9063-wdt.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Based on the Linux drivers/watchdog/da9063_wdt.c file.
+ *
+ * Watchdog driver for DA9063 PMICs.
+ *
+ * Copyright(c) 2012 Dialog Semiconductor Ltd.
+ *
+ * Author: Mariusz Wojtasik <mariusz.wojtasik@diasemi.com>
+ *
+ * Ported to U-Boot by Fabio Estevam <festevam@denx.de>
+ *
+ */
+
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <i2c.h>
+#include <linux/delay.h>
+#include <wdt.h>
+
+#define DA9063_REG_CONTROL_D 0x11
+/* DA9063_REG_CONTROL_D (addr=0x11) */
+#define DA9063_TWDSCALE_MASK 0x0
+#define DA9063_TWDSCALE_DISABLE 0
+#define DA9063_REG_CONTROL_F 0x13
+/* DA9063_REG_CONTROL_F (addr=0x13) */
+#define DA9063_WATCHDOG 0x01
+#define DA9063_SHUTDOWN 0x02
+
+/*
+ * Watchdog selector to timeout in seconds.
+ * 0: WDT disabled;
+ * others: timeout = 2048 ms * 2^(TWDSCALE-1).
+ */
+static const unsigned int wdt_timeout[] = { 0, 2, 4, 8, 16, 32, 65, 131 };
+
+#define DA9063_TWDSCALE_DISABLE 0
+#define DA9063_TWDSCALE_MIN 1
+#define DA9063_TWDSCALE_MAX (ARRAY_SIZE(wdt_timeout) - 1)
+
+static unsigned int da9063_wdt_timeout_to_sel(unsigned int secs)
+{
+ unsigned int i;
+
+ for (i = DA9063_TWDSCALE_MIN; i <= DA9063_TWDSCALE_MAX; i++) {
+ if (wdt_timeout[i] >= secs)
+ return i;
+ }
+
+ return DA9063_TWDSCALE_MAX;
+}
+
+static int da9063_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ return dm_i2c_read(dev->parent, reg, buff, len);
+}
+
+static int da9063_write(struct udevice *dev, uint reg, const u8 *buff, int len)
+{
+ return dm_i2c_write(dev->parent, reg, buff, len);
+}
+
+static int da9063_wdt_disable_timer(struct udevice *dev)
+{
+ u8 val;
+
+ da9063_read(dev, DA9063_REG_CONTROL_D, &val, 1);
+ val &= ~DA9063_TWDSCALE_MASK;
+ val |= DA9063_TWDSCALE_DISABLE;
+ da9063_write(dev, DA9063_REG_CONTROL_D, &val, 1);
+
+ return 0;
+}
+
+static int da9063_wdt_update_timeout(struct udevice *dev, unsigned int timeout)
+{
+ unsigned int regval;
+ int ret;
+ u8 val;
+
+ /*
+ * The watchdog triggers a reboot if a timeout value is already
+ * programmed because the timeout value combines two functions
+ * in one: indicating the counter limit and starting the watchdog.
+ * The watchdog must be disabled to be able to change the timeout
+ * value if the watchdog is already running. Then we can set the
+ * new timeout value which enables the watchdog again.
+ */
+ ret = da9063_wdt_disable_timer(dev);
+ if (ret)
+ return ret;
+
+ udelay(300);
+
+ regval = da9063_wdt_timeout_to_sel(timeout);
+
+ da9063_read(dev, DA9063_REG_CONTROL_D, &val, 1);
+ val &= ~DA9063_TWDSCALE_MASK;
+ val |= regval;
+ da9063_write(dev, DA9063_REG_CONTROL_D, &val, 1);
+
+ return 0;
+}
+
+static int da9063_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ return da9063_wdt_update_timeout(dev, timeout);
+}
+
+static int da9063_wdt_stop(struct udevice *dev)
+{
+ return da9063_wdt_disable_timer(dev);
+}
+
+static int da9063_wdt_reset(struct udevice *dev)
+{
+ u8 val = DA9063_WATCHDOG;
+
+ return da9063_write(dev, DA9063_REG_CONTROL_F, &val, 1);
+}
+
+static int da9063_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ u8 val = DA9063_SHUTDOWN;
+
+ return da9063_write(dev, DA9063_REG_CONTROL_F, &val, 1);
+}
+
+static const struct wdt_ops da9063_wdt_ops = {
+ .start = da9063_wdt_start,
+ .stop = da9063_wdt_stop,
+ .reset = da9063_wdt_reset,
+ .expire_now = da9063_wdt_expire_now,
+};
+
+static const struct udevice_id da9063_wdt_ids[] = {
+ { .compatible = "dlg,da9063-watchdog", },
+ {}
+};
+
+U_BOOT_DRIVER(da9063_wdt) = {
+ .name = "da9063-wdt",
+ .id = UCLASS_WDT,
+ .of_match = da9063_wdt_ids,
+ .ops = &da9063_wdt_ops,
+ .flags = DM_FLAG_PROBE_AFTER_BIND,
+};
diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h
index b8efd2a1664..8612b56609e 100644
--- a/include/fsl_esdhc_imx.h
+++ b/include/fsl_esdhc_imx.h
@@ -31,6 +31,7 @@
#define SYSCTL_RSTA 0x01000000
#define SYSCTL_RSTC 0x02000000
#define SYSCTL_RSTD 0x04000000
+#define SYSCTL_RSTT 0x10000000
#define VENDORSPEC_CKEN 0x00004000
#define VENDORSPEC_PEREN 0x00002000
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-24 21:51:32 +0000