diff options
| -rw-r--r-- | README | 3 | ||||
| -rw-r--r-- | include/configs/alt.h | 3 | ||||
| -rw-r--r-- | include/configs/condor.h | 3 | ||||
| -rw-r--r-- | include/configs/gose.h | 3 | ||||
| -rw-r--r-- | include/configs/grpeach.h | 3 | ||||
| -rw-r--r-- | include/configs/koelsch.h | 3 | ||||
| -rw-r--r-- | include/configs/lager.h | 3 | ||||
| -rw-r--r-- | include/configs/porter.h | 3 | ||||
| -rw-r--r-- | include/configs/silk.h | 3 | ||||
| -rw-r--r-- | include/configs/stout.h | 3 | ||||
| -rw-r--r-- | include/configs/v3hsk.h | 3 |
11 files changed, 0 insertions, 33 deletions
@@ -382,9 +382,6 @@ The following options need to be configured: CFG_SH_ETHER_PHY_ADDR Define the ETH PHY's address - CFG_SH_ETHER_CACHE_WRITEBACK - If this option is set, the driver enables cache flush. - - TPM Support: CONFIG_TPM Support TPM devices. diff --git a/include/configs/alt.h b/include/configs/alt.h index 52b8c95cd7b..987fd25bb4c 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -23,9 +23,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/condor.h b/include/configs/condor.h index ecaf58e4c0f..b2d66c785fc 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -16,9 +16,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ /* XTAL_CLK : 33.33MHz */ diff --git a/include/configs/gose.h b/include/configs/gose.h index 323977e9b8a..acef925855a 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -22,9 +22,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 67ad8339816..9a7eef57c87 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -19,8 +19,5 @@ /* Network interface */ #define CFG_SH_ETHER_PHY_ADDR 0 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 #endif /* __GRPEACH_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 11f637d3f33..13d2127ac13 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -22,9 +22,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/lager.h b/include/configs/lager.h index aaf4a4a6931..d76f003e391 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -23,9 +23,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/porter.h b/include/configs/porter.h index ff99c3fb817..eaf5d31c1d3 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -24,9 +24,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/silk.h b/include/configs/silk.h index 20d18aa5aa7..4ef70281dda 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -24,9 +24,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/stout.h b/include/configs/stout.h index 454d8ca5716..cb544de243e 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -28,9 +28,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h index e16a289ac1a..a8d1641b36e 100644 --- a/include/configs/v3hsk.h +++ b/include/configs/v3hsk.h @@ -17,9 +17,6 @@ /* SH Ether */ #define CFG_SH_ETHER_PHY_ADDR 0x0 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID -#define CFG_SH_ETHER_CACHE_WRITEBACK -#define CFG_SH_ETHER_CACHE_INVALIDATE -#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ /* XTAL_CLK : 33.33MHz */ |