diff options
569 files changed, 17008 insertions, 5603 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index d77b9ffc9b6..417061ae2f9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -117,7 +117,7 @@ F: drivers/mmc/snps_dw_mmc.c APPLE M1 SOC SUPPORT M: Mark Kettenis <kettenis@openbsd.org> S: Maintained -F: arch/arm/include/asm/arch-m1/ +F: arch/arm/include/asm/arch-apple/ F: arch/arm/mach-apple/ F: configs/apple_m1_defconfig F: drivers/iommu/apple_dart.c @@ -411,6 +411,8 @@ F: drivers/watchdog/mtk_wdt.c F: drivers/net/mtk_eth.c F: drivers/net/mtk_eth.h F: drivers/reset/reset-mediatek.c +F: include/dt-bindings/clock/mediatek,* +F: include/dt-bindings/power/mediatek,* F: tools/mtk_image.c F: tools/mtk_image.h F: tools/mtk_nand_headers.c @@ -1528,7 +1530,6 @@ F: cmd/stackprot_test.c F: test/py/tests/test_stackprotector.py TARGET_BCMNS3 -M: Bharat Gooty <bharat.gooty@broadcom.com> M: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> S: Maintained F: board/broadcom/bcmns3/ @@ -3,7 +3,7 @@ VERSION = 2024 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc4 +EXTRAVERSION = -rc5 NAME = # *DOCUMENTATION* diff --git a/arch/arc/include/asm/arc-bcr.h b/arch/arc/include/asm/arc-bcr.h index 823906d946e..a6c972bf1e3 100644 --- a/arch/arc/include/asm/arc-bcr.h +++ b/arch/arc/include/asm/arc-bcr.h @@ -13,8 +13,6 @@ #define __ARC_BCR_H #ifndef __ASSEMBLY__ -#include <config.h> - union bcr_di_cache { struct { #ifdef CONFIG_CPU_BIG_ENDIAN diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index a9f54f61e0c..273fb8eed85 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -7,7 +7,6 @@ #define _ASM_ARC_ARCREGS_H #include <asm/cache.h> -#include <config.h> /* * ARC architecture has additional address space - auxiliary registers. diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 74cff716ef6..65dff421483 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -6,8 +6,6 @@ #ifndef __ASM_ARC_CACHE_H #define __ASM_ARC_CACHE_H -#include <config.h> - /* * As of today we may handle any L1 cache line length right in software. * For that essentially cache line length is a variable not constant. diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c index 803dfd42558..593950449f2 100644 --- a/arch/arc/lib/cpu.c +++ b/arch/arc/lib/cpu.c @@ -3,6 +3,7 @@ * Copyright (C) 2013-2014, 2018 Synopsys, Inc. All rights reserved. */ +#include <config.h> #include <clock_legacy.h> #include <init.h> #include <malloc.h> diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 7ea029e3712..77bca7e331a 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -1177,8 +1177,9 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, if (adjust_up && cfg->bo_irq) { if (powered_by_linreg) { - bo_int = readl(cfg->reg); - clrbits_le32(cfg->reg, cfg->bo_enirq); + bo_int = readl(&power_regs->hw_power_ctrl); + clrbits_le32(&power_regs->hw_power_ctrl, + cfg->bo_enirq); } setbits_le32(cfg->reg, cfg->bo_offset_mask); } @@ -1220,7 +1221,8 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, if (adjust_up && powered_by_linreg) { writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr); if (bo_int & cfg->bo_enirq) - setbits_le32(cfg->reg, cfg->bo_enirq); + setbits_le32(&power_regs->hw_power_ctrl, + cfg->bo_enirq); } clrsetbits_le32(cfg->reg, cfg->bo_offset_mask, diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ef0e705f3d7..e9e58c5478d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -835,6 +835,7 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \ sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_MACH_SUN50I_H616) += \ sun50i-h616-orangepi-zero2.dtb \ + sun50i-h618-orangepi-zero3.dtb \ sun50i-h616-x96-mate.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-amarula-relic.dtb \ @@ -1516,6 +1517,8 @@ targets += $(dtb-y) # Add any required device tree compiler flags here DTC_FLAGS += -a 0x8 +DTC_FLAGS_imx8mp-dhcom-pdk3-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format + PHONY += dtbs dtbs: $(addprefix $(obj)/, $(dtb-y)) @: diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi index f2d6b183ed9..c54a59e89c5 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi @@ -93,6 +93,12 @@ &gpio4 { bootph-some-ram; + + usbh_en { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + }; }; &gpio5 { diff --git a/arch/arm/dts/fsl-imx8qm-apalis.dts b/arch/arm/dts/fsl-imx8qm-apalis.dts index bc7c75d3372..e089ddb8468 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis.dts +++ b/arch/arm/dts/fsl-imx8qm-apalis.dts @@ -9,7 +9,6 @@ /memreserve/ 0x80000000 0x00020000; #include "fsl-imx8qm.dtsi" -#include "fsl-imx8qm-apalis-u-boot.dtsi" / { model = "Toradex Apalis iMX8"; diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi index a6af4e5e2b7..6ab6b1f9ee6 100644 --- a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi @@ -84,6 +84,21 @@ bootph-some-ram; }; +&gpio_expander_43 { + usb-bypass-n-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + line-name = "usb-bypass-n"; + output-high; + }; + usb-reset-n-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + line-name = "usb-reset-n"; + output-low; + }; +}; + &gpio0 { bootph-some-ram; }; diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts index df992ac6396..b479921aff9 100644 --- a/arch/arm/dts/fsl-imx8qxp-colibri.dts +++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts @@ -6,7 +6,6 @@ /dts-v1/; #include "fsl-imx8qxp.dtsi" -#include "fsl-imx8qxp-colibri-u-boot.dtsi" / { model = "Toradex Colibri iMX8X"; @@ -320,8 +319,6 @@ gpio-controller; #gpio-cells = <2>; reg = <0x43>; - initial_io_dir = <0xff>; - initial_output = <0x05>; }; }; diff --git a/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi b/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi index 3dd01e36a4a..3b5f14ecb04 100644 --- a/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi +++ b/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi @@ -7,6 +7,12 @@ usb0 = &usbotg1; display0 = &lcdif; }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; }; &usbotg1 { @@ -46,6 +52,10 @@ }; }; +&wdog1 { + bootph-pre-ram; +}; + &iomuxc { pinctrl_backlight: backlight { fsl,pins = < diff --git a/arch/arm/dts/imx7s-warp-u-boot.dtsi b/arch/arm/dts/imx7s-warp-u-boot.dtsi index 49b992dccca..4f44598c9a2 100644 --- a/arch/arm/dts/imx7s-warp-u-boot.dtsi +++ b/arch/arm/dts/imx7s-warp-u-boot.dtsi @@ -1,12 +1,12 @@ / { - aliases { - mmc0 = &usdhc3; - usb0 = &usbotg1; - }; + aliases { + mmc0 = &usdhc3; + usb0 = &usbotg1; + }; - chosen { - stdout-path = &uart1; - }; + chosen { + stdout-path = &uart1; + }; }; &aips3 { diff --git a/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi index 92e44d4ba96..31f9d47bced 100644 --- a/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi @@ -39,6 +39,13 @@ gpios = <9 GPIO_ACTIVE_HIGH>; line-name = "dio1"; }; + + tpm_rst { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "tpm_rst#"; + }; }; &gpio4 { diff --git a/arch/arm/dts/imx8mm-venice-gw72xx.dtsi b/arch/arm/dts/imx8mm-venice-gw72xx.dtsi index 41d0de6a702..97ed34a3c58 100644 --- a/arch/arm/dts/imx8mm-venice-gw72xx.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw72xx.dtsi @@ -84,8 +84,15 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio1 { @@ -314,6 +321,7 @@ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 >; }; diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi index e0caf3179ea..2bbc4a49418 100644 --- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi @@ -39,11 +39,11 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; }; &pinctrl_i2c1 { - bootph-pre-ram; + bootph-all; }; &pinctrl_pmic { @@ -83,5 +83,5 @@ }; &eeprom_som { - bootph-pre-ram; + bootph-all; }; diff --git a/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi index 7f2609ab546..525316d1189 100644 --- a/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi @@ -4,6 +4,15 @@ */ #include "imx8mp-venice-gw702x-u-boot.dtsi" +&gpio1 { + tpm_rst { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "tpm_rst#"; + }; +}; + &gpio4 { dio_1 { gpio-hog; diff --git a/arch/arm/dts/imx8mp-venice-gw72xx.dtsi b/arch/arm/dts/imx8mp-venice-gw72xx.dtsi index e05fdecdaf4..4e726128ccf 100644 --- a/arch/arm/dts/imx8mp-venice-gw72xx.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw72xx.dtsi @@ -83,8 +83,14 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio4 { @@ -286,6 +292,7 @@ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 >; }; diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index f0a73605020..018faaa13b6 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -24,7 +24,8 @@ <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; clocks = <&k3_clks 61 1>; - assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; + assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>; + assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>; assigned-clock-rates = <2000000000>, <200000000>; ti,sci = <&dmsc>; ti,sci-proc-id = <32>; diff --git a/arch/arm/dts/meson-gx-libretech-pc.dtsi b/arch/arm/dts/meson-gx-libretech-pc.dtsi index 2d7032f41e4..4e84ab87cc7 100644 --- a/arch/arm/dts/meson-gx-libretech-pc.dtsi +++ b/arch/arm/dts/meson-gx-libretech-pc.dtsi @@ -17,7 +17,7 @@ io-channel-names = "buttons"; keyup-threshold-microvolt = <1800000>; - update-button { + button-update { label = "update"; linux,code = <KEY_VENDOR>; press-threshold-microvolt = <1300000>; @@ -416,7 +416,7 @@ pinctrl-names = "default"; status = "okay"; - gd25lq128: spi-flash@0 { + gd25lq128: flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/meson-gx.dtsi b/arch/arm/dts/meson-gx.dtsi index 6b457b2c30a..11f89bfecb5 100644 --- a/arch/arm/dts/meson-gx.dtsi +++ b/arch/arm/dts/meson-gx.dtsi @@ -49,6 +49,12 @@ no-map; }; + /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ + secmon_reserved_bl32: secmon@5300000 { + reg = <0x0 0x05300000 0x0 0x2000000>; + no-map; + }; + linux,cma { compatible = "shared-dma-pool"; reusable; @@ -126,6 +132,7 @@ l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; @@ -226,7 +233,7 @@ reg = <0x14 0x10>; }; - eth_mac: eth_mac@34 { + eth_mac: eth-mac@34 { reg = <0x34 0x10>; }; @@ -243,7 +250,7 @@ scpi_clocks: clocks { compatible = "arm,scpi-clocks"; - scpi_dvfs: scpi_clocks@0 { + scpi_dvfs: clocks-0 { compatible = "arm,scpi-dvfs-clocks"; #clock-cells = <1>; clock-indices = <0>; @@ -444,7 +451,7 @@ sysctrl_AO: sys-ctrl@0 { compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; - reg = <0x0 0x0 0x0 0x100>; + reg = <0x0 0x0 0x0 0x100>; clkc_AO: clock-controller { compatible = "amlogic,meson-gx-aoclkc"; @@ -525,7 +532,7 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; - hwrng: rng { + hwrng: rng@0 { compatible = "amlogic,meson-rng"; reg = <0x0 0x0 0x0 0x4>; }; @@ -596,21 +603,21 @@ sd_emmc_a: mmc@70000 { compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; reg = <0x0 0x70000 0x0 0x800>; - interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; sd_emmc_b: mmc@72000 { compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; reg = <0x0 0x72000 0x0 0x800>; - interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; sd_emmc_c: mmc@74000 { compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; reg = <0x0 0x74000 0x0 0x800>; - interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; }; diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts b/arch/arm/dts/meson-gxbb-nanopi-k2.dts index 7273eed5292..7d94160f580 100644 --- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts +++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts @@ -385,9 +385,20 @@ /* Bluetooth on AP6212 */ &uart_A { - status = "disabled"; + status = "okay"; pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&wifi_32k>; + clock-names = "lpo"; + vbat-supply = <&vddio_ao3v3>; + vddio-supply = <&vddio_ao18>; + host-wakeup-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; + }; }; /* 40-pin CON1 */ diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts index 201596247fd..01356437a07 100644 --- a/arch/arm/dts/meson-gxbb-odroidc2.dts +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts @@ -250,21 +250,6 @@ }; }; -&gpio_ao { - /* - * WARNING: The USB Hub on the Odroid-C2 needs a reset signal - * to be turned high in order to be detected by the USB Controller - * This signal should be handled by a USB specific power sequence - * in order to reset the Hub when USB bus is powered down. - */ - hog-0 { - gpio-hog; - gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-hub-reset"; - }; -}; - &hdmi_tx { status = "okay"; pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; @@ -414,5 +399,16 @@ }; &usb1 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + hub@1 { + /* Genesys Logic GL852G USB 2.0 hub */ + compatible = "usb5e3,610"; + reg = <1>; + vdd-supply = <&p5v0>; + reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; + }; }; diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi index 7c029f552a2..12ef6e81c8b 100644 --- a/arch/arm/dts/meson-gxbb.dtsi +++ b/arch/arm/dts/meson-gxbb.dtsi @@ -300,8 +300,8 @@ }; &gpio_intc { - compatible = "amlogic,meson-gpio-intc", - "amlogic,meson-gxbb-gpio-intc"; + compatible = "amlogic,meson-gxbb-gpio-intc", + "amlogic,meson-gpio-intc"; status = "okay"; }; @@ -427,6 +427,20 @@ }; }; + spi_idle_high_pins: spi-idle-high-pins { + mux { + groups = "spi_sclk"; + bias-pull-up; + }; + }; + + spi_idle_low_pins: spi-idle-low-pins { + mux { + groups = "spi_sclk"; + bias-pull-down; + }; + }; + spi_ss0_pins: spi-ss0 { mux { groups = "spi_ss0"; diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts index 2d769203f67..213a0705ebd 100644 --- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts +++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts @@ -298,7 +298,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - w25q32: spi-flash@0 { + w25q32: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts b/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts index 6eafb908695..a18d6d241a5 100644 --- a/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts +++ b/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts @@ -86,11 +86,11 @@ }; &efuse { - bt_mac: bt_mac@6 { + bt_mac: bt-mac@6 { reg = <0x6 0x6>; }; - wifi_mac: wifi_mac@C { + wifi_mac: wifi-mac@c { reg = <0xc 0x6>; }; }; @@ -213,6 +213,12 @@ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; pinctrl-names = "default"; uart-has-rtscts; + + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>; + }; }; &uart_C { @@ -233,7 +239,7 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c_b_pins>; - pcf8563: pcf8563@51 { + pcf8563: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; status = "okay"; diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts index 60feac0179c..02f81839d4e 100644 --- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts @@ -140,7 +140,6 @@ compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; - clock-frequency = <32768>; clock-output-names = "xin32k"; }; }; @@ -218,20 +217,7 @@ }; &sd_emmc_a { - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -&uart_A { - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; + max-frequency = <100000000>; }; /* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts index 93d8f8aff70..6c4e68e0e62 100644 --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts @@ -284,7 +284,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - nor_4u1: spi-flash@0 { + nor_4u1: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -305,7 +305,6 @@ }; &usb2_phy0 { - pinctrl-names = "default"; phy-supply = <&vcc5v>; }; diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dts b/arch/arm/dts/meson-gxl-s905x-p212.dts index 2602940c207..9b4ea6a4939 100644 --- a/arch/arm/dts/meson-gxl-s905x-p212.dts +++ b/arch/arm/dts/meson-gxl-s905x-p212.dts @@ -7,11 +7,19 @@ /dts-v1/; #include "meson-gxl-s905x-p212.dtsi" +#include <dt-bindings/sound/meson-aiu.h> / { compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl"; model = "Amlogic Meson GXL (S905X) P212 Development Board"; + dio2133: analog-amplifier { + compatible = "simple-audio-amplifier"; + sound-name-prefix = "AU2"; + VCC-supply = <&hdmi_5v>; + enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; + }; + cvbs-connector { compatible = "composite-video-connector"; @@ -32,6 +40,66 @@ }; }; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "S905X-P212"; + audio-aux-devs = <&dio2133>; + audio-widgets = "Line", "Lineout"; + audio-routing = "AU2 INL", "ACODEC LOLN", + "AU2 INR", "ACODEC LORN", + "Lineout", "AU2 OUTL", + "Lineout", "AU2 OUTR"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + + codec-1 { + sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + + dai-link-3 { + sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; + + codec-0 { + sound-dai = <&acodec>; + }; + }; + }; +}; + +&acodec { + AVDD-supply = <&vddio_ao18>; + status = "okay"; +}; + +&aiu { + status = "okay"; }; &cec_AO { diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi index 05cb2f5e5c3..a150cc0e18f 100644 --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi +++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi @@ -97,6 +97,14 @@ pinctrl-names = "default"; }; +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "clkin0"; +}; + &saradc { status = "okay"; vref-supply = <&vddio_ao18>; @@ -125,6 +133,11 @@ vmmc-supply = <&vddao_3v3>; vqmmc-supply = <&vddio_boot>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; }; /* SD card */ @@ -165,14 +178,6 @@ vqmmc-supply = <&vddio_boot>; }; -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - /* This is connected to the Bluetooth module: */ &uart_A { status = "okay"; diff --git a/arch/arm/dts/meson-gxl.dtsi b/arch/arm/dts/meson-gxl.dtsi index c3ac531c4f8..17bcfa4702e 100644 --- a/arch/arm/dts/meson-gxl.dtsi +++ b/arch/arm/dts/meson-gxl.dtsi @@ -312,8 +312,8 @@ }; &gpio_intc { - compatible = "amlogic,meson-gpio-intc", - "amlogic,meson-gxl-gpio-intc"; + compatible = "amlogic,meson-gxl-gpio-intc", + "amlogic,meson-gpio-intc"; status = "okay"; }; @@ -429,6 +429,20 @@ }; }; + spi_idle_high_pins: spi-idle-high-pins { + mux { + groups = "spi_sclk"; + bias-pull-up; + }; + }; + + spi_idle_low_pins: spi-idle-low-pins { + mux { + groups = "spi_sclk"; + bias-pull-down; + }; + }; + spi_ss0_pins: spi-ss0 { mux { groups = "spi_ss0"; @@ -759,16 +773,23 @@ }; }; - eth-phy-mux { - compatible = "mdio-mux-mmioreg", "mdio-mux"; + eth_phy_mux: mdio@558 { + reg = <0x0 0x558 0x0 0xc>; + compatible = "amlogic,gxl-mdio-mux"; #address-cells = <1>; #size-cells = <0>; - reg = <0x0 0x55c 0x0 0x4>; - mux-mask = <0xffffffff>; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "ref"; mdio-parent-bus = <&mdio0>; - internal_mdio: mdio@e40908ff { - reg = <0xe40908ff>; + external_mdio: mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + internal_mdio: mdio@1 { + reg = <0x1>; #address-cells = <1>; #size-cells = <0>; @@ -779,12 +800,6 @@ max-speed = <100>; }; }; - - external_mdio: mdio@2009087f { - reg = <0x2009087f>; - #address-cells = <1>; - #size-cells = <0>; - }; }; }; diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts index 18a4b7a6c5d..74897a15489 100644 --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts @@ -52,10 +52,11 @@ gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH &gpio GPIODV_15 GPIO_ACTIVE_HIGH>; /* Dummy RPM values since fan is optional */ - gpio-fan,speed-map = <0 0 - 1 1 - 2 2 - 3 3>; + gpio-fan,speed-map = + <0 0>, + <1 1>, + <2 2>, + <3 3>; #cooling-cells = <2>; }; @@ -270,7 +271,6 @@ compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; - clock-frequency = <32768>; clock-output-names = "xin32k"; }; }; @@ -307,7 +307,8 @@ #size-cells = <0>; bus-width = <4>; - max-frequency = <60000000>; + cap-sd-highspeed; + max-frequency = <100000000>; non-removable; disable-wp; @@ -373,7 +374,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - w25q32: spi-flash@0 { + w25q32: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "winbond,w25q16", "jedec,spi-nor"; diff --git a/arch/arm/dts/meson-gxm-wetek-core2.dts b/arch/arm/dts/meson-gxm-wetek-core2.dts index 1e7f77f9b53..f8c40340b9c 100644 --- a/arch/arm/dts/meson-gxm-wetek-core2.dts +++ b/arch/arm/dts/meson-gxm-wetek-core2.dts @@ -45,8 +45,6 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; button-power { diff --git a/arch/arm/dts/mt6357.dtsi b/arch/arm/dts/mt6357.dtsi new file mode 100644 index 00000000000..3330a03c2f7 --- /dev/null +++ b/arch/arm/dts/mt6357.dtsi @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2020 MediaTek Inc. + * Copyright (c) 2023 BayLibre Inc. + */ + +#include <dt-bindings/input/input.h> + +&pwrap { + mt6357_pmic: pmic { + compatible = "mediatek,mt6357"; + + regulators { + mt6357_vproc_reg: buck-vproc { + regulator-name = "vproc"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <220>; + regulator-always-on; + }; + + mt6357_vcore_reg: buck-vcore { + regulator-name = "vcore"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <220>; + regulator-always-on; + }; + + mt6357_vmodem_reg: buck-vmodem { + regulator-name = "vmodem"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1193750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <220>; + }; + + mt6357_vs1_reg: buck-vs1 { + regulator-name = "vs1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2200000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <220>; + regulator-always-on; + }; + + mt6357_vpa_reg: buck-vpa { + regulator-name = "vpa"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3650000>; + regulator-ramp-delay = <50000>; + regulator-enable-ramp-delay = <220>; + }; + + mt6357_vfe28_reg: ldo-vfe28 { + compatible = "regulator-fixed"; + regulator-name = "vfe28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vxo22_reg: ldo-vxo22 { + regulator-name = "vxo22"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2400000>; + regulator-enable-ramp-delay = <110>; + }; + + mt6357_vrf18_reg: ldo-vrf18 { + compatible = "regulator-fixed"; + regulator-name = "vrf18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <110>; + }; + + mt6357_vrf12_reg: ldo-vrf12 { + compatible = "regulator-fixed"; + regulator-name = "vrf12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <110>; + }; + + mt6357_vefuse_reg: ldo-vefuse { + regulator-name = "vefuse"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcn33_bt_reg: ldo-vcn33-bt { + regulator-name = "vcn33-bt"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3500000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcn33_wifi_reg: ldo-vcn33-wifi { + regulator-name = "vcn33-wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3500000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcn28_reg: ldo-vcn28 { + compatible = "regulator-fixed"; + regulator-name = "vcn28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcn18_reg: ldo-vcn18 { + compatible = "regulator-fixed"; + regulator-name = "vcn18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcama_reg: ldo-vcama { + regulator-name = "vcama"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcamd_reg: ldo-vcamd { + regulator-name = "vcamd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcamio_reg: ldo-vcamio18 { + compatible = "regulator-fixed"; + regulator-name = "vcamio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vldo28_reg: ldo-vldo28 { + regulator-name = "vldo28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vsram_others_reg: ldo-vsram-others { + regulator-name = "vsram-others"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <110>; + regulator-always-on; + }; + + mt6357_vsram_proc_reg: ldo-vsram-proc { + regulator-name = "vsram-proc"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <110>; + regulator-always-on; + }; + + mt6357_vaux18_reg: ldo-vaux18 { + compatible = "regulator-fixed"; + regulator-name = "vaux18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vaud28_reg: ldo-vaud28 { + compatible = "regulator-fixed"; + regulator-name = "vaud28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vio28_reg: ldo-vio28 { + compatible = "regulator-fixed"; + regulator-name = "vio28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vio18_reg: ldo-vio18 { + compatible = "regulator-fixed"; + regulator-name = "vio18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + }; + + mt6357_vdram_reg: ldo-vdram { + regulator-name = "vdram"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <3300>; + }; + + mt6357_vmc_reg: ldo-vmc { + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <44>; + }; + + mt6357_vmch_reg: ldo-vmch { + regulator-name = "vmch"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <44>; + }; + + mt6357_vemc_reg: ldo-vemc { + regulator-name = "vemc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <44>; + regulator-always-on; + }; + + mt6357_vsim1_reg: ldo-vsim1 { + regulator-name = "vsim1"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vsim2_reg: ldo-vsim2 { + regulator-name = "vsim2"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vibr_reg: ldo-vibr { + regulator-name = "vibr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <44>; + }; + + mt6357_vusb33_reg: ldo-vusb33 { + regulator-name = "vusb33"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <264>; + }; + }; + + rtc { + compatible = "mediatek,mt6357-rtc"; + }; + + keys { + compatible = "mediatek,mt6357-keys"; + + key-power { + linux,keycodes = <KEY_POWER>; + wakeup-source; + }; + + key-home { + linux,keycodes = <KEY_HOME>; + wakeup-source; + }; + + }; + }; +}; diff --git a/arch/arm/dts/mt8365-evk.dts b/arch/arm/dts/mt8365-evk.dts new file mode 100644 index 00000000000..50cbaefa1a9 --- /dev/null +++ b/arch/arm/dts/mt8365-evk.dts @@ -0,0 +1,418 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021-2022 BayLibre, SAS. + * Authors: + * Fabien Parent <fparent@baylibre.com> + * Bernhard Rosenkränzer <bero@baylibre.com> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/mt8365-pinfunc.h> +#include "mt8365.dtsi" +#include "mt6357.dtsi" + +/ { + model = "MediaTek MT8365 Open Platform EVK"; + compatible = "mediatek,mt8365-evk", "mediatek,mt8365"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; + + key-volume-up { + gpios = <&pio 24 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = <KEY_VOLUMEUP>; + wakeup-source; + debounce-interval = <15>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0xc0000000>; + }; + + usb_otg_vbus: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + no-map; + reg = <0 0x43000000 0 0x30000>; + }; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + }; +}; + +&cpu0 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu1 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu2 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu3 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +ðernet { + pinctrl-0 = <ðernet_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy>; + phy-mode = "rmii"; + /* + * Ethernet and HDMI (DSI0) are sharing pins. + * Only one can be enabled at a time and require the physical switch + * SW2101 to be set on LAN position + * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet + */ + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mmc0 { + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>; + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + hs400-ds-delay = <0x12012>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sd; + no-sdio; + non-removable; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&mt6357_vemc_reg>; + vqmmc-supply = <&mt6357_vio18_reg>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>; + max-frequency = <200000000>; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + pinctrl-names = "default", "state_uhs"; + sd-uhs-sdr104; + sd-uhs-sdr50; + vmmc-supply = <&mt6357_vmch_reg>; + vqmmc-supply = <&mt6357_vmc_reg>; + status = "okay"; +}; + +&mt6357_pmic { + interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; +}; + +&pio { + ethernet_pins: ethernet-pins { + phy_reset_pins { + pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>; + }; + + rmii_pins { + pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>, + <MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>, + <MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>, + <MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>, + <MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>, + <MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>, + <MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>, + <MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>, + <MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>, + <MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>, + <MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>, + <MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>, + <MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>, + <MT8365_PIN_13_GPIO13__FUNC_EXT_COL>, + <MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>, + <MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>; + }; + }; + + gpio_keys: gpio-keys-pins { + pins { + pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>; + bias-pull-up; + input-enable; + }; + }; + + i2c0_pins: i2c0-pins { + pins { + pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>, + <MT8365_PIN_58_SCL0__FUNC_SCL0_0>; + bias-pull-up; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + clk-pins { + pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>; + bias-pull-down; + }; + + cmd-dat-pins { + pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>, + <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>, + <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>, + <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>, + <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>, + <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>, + <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>, + <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>, + <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>; + input-enable; + bias-pull-up; + }; + + rst-pins { + pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>; + bias-pull-up; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + clk-pins { + pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>; + drive-strength = <MTK_DRIVE_10mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + cmd-dat-pins { + pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>, + <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>, + <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>, + <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>, + <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>, + <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>, + <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>, + <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>, + <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_10mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + ds-pins { + pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>; + drive-strength = <MTK_DRIVE_10mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + rst-pins { + pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>; + drive-strength = <MTK_DRIVE_10mA>; + bias-pull-up; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + cd-pins { + pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>; + bias-pull-up; + }; + + clk-pins { + pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + cmd-dat-pins { + pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>, + <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>, + <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>, + <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>, + <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + clk-pins { + pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + cmd-dat-pins { + pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>, + <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>, + <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>, + <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>, + <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>, + <MT8365_PIN_36_UTXD0__FUNC_UTXD0>; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>, + <MT8365_PIN_38_UTXD1__FUNC_UTXD1>; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>, + <MT8365_PIN_40_UTXD2__FUNC_UTXD2>; + }; + }; + + usb_pins: usb-pins { + id-pins { + pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>; + input-enable; + bias-pull-up; + }; + + usb0-vbus-pins { + pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>; + output-high; + }; + + usb1-vbus-pins { + pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>; + output-high; + }; + }; + + pwm_pins: pwm-pins { + pins { + pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>, + <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>; + }; + }; +}; + +&pwm { + pinctrl-0 = <&pwm_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ssusb { + dr_mode = "otg"; + maximum-speed = "high-speed"; + pinctrl-0 = <&usb_pins>; + pinctrl-names = "default"; + usb-role-switch; + vusb33-supply = <&mt6357_vusb33_reg>; + status = "okay"; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>; + type = "micro"; + vbus-supply = <&usb_otg_vbus>; + }; +}; + +&usb_host { + vusb33-supply = <&mt6357_vusb33_reg>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/dts/mt8365.dtsi b/arch/arm/dts/mt8365.dtsi new file mode 100644 index 00000000000..24581f7410a --- /dev/null +++ b/arch/arm/dts/mt8365.dtsi @@ -0,0 +1,840 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * (C) 2018 MediaTek Inc. + * Copyright (C) 2022 BayLibre SAS + * Fabien Parent <fparent@baylibre.com> + * Bernhard Rosenkränzer <bero@baylibre.com> + */ +#include <dt-bindings/clock/mediatek,mt8365-clk.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/power/mediatek,mt8365-power.h> + +/ { + compatible = "mediatek,mt8365"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <650000>; + }; + + opp-918000000 { + opp-hz = /bits/ 64 <918000000>; + opp-microvolt = <668750>; + }; + + opp-987000000 { + opp-hz = /bits/ 64 <987000000>; + opp-microvolt = <687500>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <706250>; + }; + + opp-1125000000 { + opp-hz = /bits/ 64 <1125000000>; + opp-microvolt = <725000>; + }; + + opp-1216000000 { + opp-hz = /bits/ 64 <1216000000>; + opp-microvolt = <750000>; + }; + + opp-1308000000 { + opp-hz = /bits/ 64 <1308000000>; + opp-microvolt = <775000>; + }; + + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <800000>; + }; + + opp-1466000000 { + opp-hz = /bits/ 64 <1466000000>; + opp-microvolt = <825000>; + }; + + opp-1533000000 { + opp-hz = /bits/ 64 <1533000000>; + opp-microvolt = <850000>; + }; + + opp-1633000000 { + opp-hz = /bits/ 64 <1633000000>; + opp-microvolt = <887500>; + }; + + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <912500>; + }; + + opp-1767000000 { + opp-hz = /bits/ 64 <1767000000>; + opp-microvolt = <937500>; + }; + + opp-1834000000 { + opp-hz = /bits/ 64 <1834000000>; + opp-microvolt = <962500>; + }; + + opp-1917000000 { + opp-hz = /bits/ 64 <1917000000>; + opp-microvolt = <993750>; + }; + + opp-2001000000 { + opp-hz = /bits/ 64 <2001000000>; + opp-microvolt = <1025000>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + #cooling-cells = <2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + #cooling-cells = <2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + #cooling-cells = <2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + #cooling-cells = <2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + }; + + idle-states { + entry-method = "psci"; + + CPU_MCDI: cpu-mcdi { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x00010001>; + entry-latency-us = <300>; + exit-latency-us = <200>; + min-residency-us = <1000>; + }; + + CLUSTER_MCDI: cluster-mcdi { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x01010001>; + entry-latency-us = <350>; + exit-latency-us = <250>; + min-residency-us = <1200>; + }; + + CLUSTER_DPIDLE: cluster-dpidle { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x01010004>; + entry-latency-us = <300>; + exit-latency-us = <800>; + min-residency-us = <3300>; + }; + }; + + l2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + }; + }; + + clk26m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x10000>, /* GICD */ + <0 0x0c080000 0 0x80000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8365-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt8365-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt8365-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + + syscfg_pctl: syscfg-pctl@10005000 { + compatible = "mediatek,mt8365-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + scpsys: syscon@10006000 { + compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8365-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domains of the SoC */ + power-domain@MT8365_POWER_DOMAIN_MM { + reg = <MT8365_POWER_DOMAIN_MM>; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&mmsys CLK_MM_MM_SMI_COMMON>, + <&mmsys CLK_MM_MM_SMI_COMM0>, + <&mmsys CLK_MM_MM_SMI_COMM1>, + <&mmsys CLK_MM_MM_SMI_LARB0>; + clock-names = "mm", "mm-0", "mm-1", + "mm-2", "mm-3"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + mediatek,infracfg-nao = <&infracfg_nao>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@MT8365_POWER_DOMAIN_CAM { + reg = <MT8365_POWER_DOMAIN_CAM>; + clocks = <&camsys CLK_CAM_LARB2>, + <&camsys CLK_CAM_SENIF>, + <&camsys CLK_CAMSV0>, + <&camsys CLK_CAMSV1>, + <&camsys CLK_CAM_FDVT>, + <&camsys CLK_CAM_WPE>; + clock-names = "cam-0", "cam-1", + "cam-2", "cam-3", + "cam-4", "cam-5"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + }; + + power-domain@MT8365_POWER_DOMAIN_VDEC { + reg = <MT8365_POWER_DOMAIN_VDEC>; + #power-domain-cells = <0>; + mediatek,smi = <&smi_common>; + }; + + power-domain@MT8365_POWER_DOMAIN_VENC { + reg = <MT8365_POWER_DOMAIN_VENC>; + #power-domain-cells = <0>; + mediatek,smi = <&smi_common>; + }; + + power-domain@MT8365_POWER_DOMAIN_APU { + reg = <MT8365_POWER_DOMAIN_APU>; + clocks = <&infracfg CLK_IFR_APU_AXI>, + <&apu CLK_APU_IPU_CK>, + <&apu CLK_APU_AXI>, + <&apu CLK_APU_JTAG>, + <&apu CLK_APU_IF_CK>, + <&apu CLK_APU_EDMA>, + <&apu CLK_APU_AHB>; + clock-names = "apu", "apu-0", + "apu-1", "apu-2", + "apu-3", "apu-4", + "apu-5"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + }; + }; + + power-domain@MT8365_POWER_DOMAIN_CONN { + reg = <MT8365_POWER_DOMAIN_CONN>; + clocks = <&topckgen CLK_TOP_CONN_32K>, + <&topckgen CLK_TOP_CONN_26M>; + clock-names = "conn", "conn1"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_MFG { + reg = <MT8365_POWER_DOMAIN_MFG>; + clocks = <&topckgen CLK_TOP_MFG_SEL>; + clock-names = "mfg"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_AUDIO { + reg = <MT8365_POWER_DOMAIN_AUDIO>; + clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&infracfg CLK_IFR_AUDIO>, + <&infracfg CLK_IFR_AUD_26M_BK>; + clock-names = "audio", "audio1", "audio2"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_DSP { + reg = <MT8365_POWER_DOMAIN_DSP>; + clocks = <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_DSP_26M>; + clock-names = "dsp", "dsp1"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; + #reset-cells = <1>; + }; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8365-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8365-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt8365-pwrap"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_IFR_PWRAP_SPI>, + <&infracfg CLK_IFR_PMIC_AP>, + <&infracfg CLK_IFR_PWRAP_SYS>, + <&infracfg CLK_IFR_PWRAP_TMR>; + clock-names = "spi", "wrap", "sys", "tmr"; + }; + + keypad: keypad@10010000 { + compatible = "mediatek,mt6779-keypad"; + reg = <0 0x10010000 0 0x1000>; + wakeup-source; + interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>; + clocks = <&clk26m>; + clock-names = "kpd"; + status = "disabled"; + }; + + mcucfg: syscon@10200000 { + compatible = "mediatek,mt8365-mcucfg", "syscon"; + reg = <0 0x10200000 0 0x2000>; + #clock-cells = <1>; + }; + + sysirq: interrupt-controller@10200a80 { + compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200a80 0 0x20>; + }; + + iommu: iommu@10205000 { + compatible = "mediatek,mt8365-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>; + #iommu-cells = <1>; + }; + + infracfg_nao: infracfg@1020e000 { + compatible = "mediatek,mt8365-infracfg", "syscon"; + reg = <0 0x1020e000 0 0x1000>; + #clock-cells = <1>; + }; + + rng: rng@1020f000 { + compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x100>; + clocks = <&infracfg CLK_IFR_TRNG>; + clock-names = "rng"; + }; + + apdma: dma-controller@11000280 { + compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; + reg = <0 0x11000280 0 0x80>, + <0 0x11000300 0 0x80>, + <0 0x11000380 0 0x80>, + <0 0x11000400 0 0x80>, + <0 0x11000580 0 0x80>, + <0 0x11000600 0 0x80>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; + dma-requests = <6>; + clocks = <&infracfg CLK_IFR_AP_DMA>; + clock-names = "apdma"; + #dma-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; + clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x1000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; + clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x1000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; + clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + pwm: pwm@11006000 { + compatible = "mediatek,mt8365-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_IFR_PWM_HCLK>, + <&infracfg CLK_IFR_PWM>, + <&infracfg CLK_IFR_PWM1>, + <&infracfg CLK_IFR_PWM2>, + <&infracfg CLK_IFR_PWM3>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; + }; + + i2c0: i2c@11007000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi: spi@1100a000 { + compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; + reg = <0 0x1100a000 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_IFR_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + i2c3: i2c@1100f000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssusb: usb@11201000 { + compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; + reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u2port1 PHY_TYPE_USB2>; + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host: usb@11200000 { + compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>, + <&infracfg CLK_IFR_SSUSB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck"; + status = "disabled"; + }; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11cd0000 0 0x1000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&infracfg CLK_IFR_MSDC0_HCLK>, + <&infracfg CLK_IFR_MSDC0_SRC>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11c90000 0 0x1000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, + <&infracfg CLK_IFR_MSDC1_HCLK>, + <&infracfg CLK_IFR_MSDC1_SRC>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc2: mmc@11250000 { + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11250000 0 0x1000>, + <0 0x11c60000 0 0x1000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>, + <&infracfg CLK_IFR_MSDC2_HCLK>, + <&infracfg CLK_IFR_MSDC2_SRC>, + <&infracfg CLK_IFR_MSDC2_BK>, + <&infracfg CLK_IFR_AP_MSDC0>; + clock-names = "source", "hclk", "source_cg", + "bus_clk", "sys_cg"; + status = "disabled"; + }; + + ethernet: ethernet@112a0000 { + compatible = "mediatek,mt8365-eth"; + reg = <0 0x112a0000 0 0x1000>; + mediatek,pericfg = <&infracfg>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_ETH_SEL>, + <&infracfg CLK_IFR_NIC_AXI>, + <&infracfg CLK_IFR_NIC_SLV_AXI>; + clock-names = "core", "reg", "trans"; + status = "disabled"; + }; + + u3phy: t-phy@11cc0000 { + compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11cc0000 0x9000>; + + u2port0: usb-phy@0 { + reg = <0x0 0x400>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + + u2port1: usb-phy@1000 { + reg = <0x1000 0x400>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt8365-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + smi_common: smi@14002000 { + compatible = "mediatek,mt8365-smi-common"; + reg = <0 0x14002000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_SMI_COMMON>, + <&mmsys CLK_MM_MM_SMI_COMMON>, + <&mmsys CLK_MM_MM_SMI_COMM0>, + <&mmsys CLK_MM_MM_SMI_COMM1>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + larb0: larb@14003000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x14003000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_MM_SMI_LARB0>, + <&mmsys CLK_MM_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + mediatek,larb-id = <0>; + }; + + camsys: syscon@15000000 { + compatible = "mediatek,mt8365-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb2: larb@15001000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_MM_SMI_IMG>, + <&camsys CLK_CAM_LARB2>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; + mediatek,larb-id = <2>; + }; + + vdecsys: syscon@16000000 { + compatible = "mediatek,mt8365-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb3: larb@16010000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_LARB1>, + <&vdecsys CLK_VDEC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>; + mediatek,larb-id = <3>; + }; + + vencsys: syscon@17000000 { + compatible = "mediatek,mt8365-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb1: larb@17010000 { + compatible = "mediatek,mt8365-smi-larb", + "mediatek,mt8186-smi-larb"; + reg = <0 0x17010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8365_POWER_DOMAIN_VENC>; + mediatek,larb-id = <1>; + }; + + apu: syscon@19020000 { + compatible = "mediatek,mt8365-apu", "syscon"; + reg = <0 0x19020000 0 0x1000>; + #clock-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + systimer: timer@10017000 { + compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; + reg = <0 0x10017000 0 0x100>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&system_clk>; + clock-names = "clk13m"; + }; +}; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi b/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi index 15290e6892f..fc7315b9440 100644 --- a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi +++ b/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi @@ -68,10 +68,7 @@ &emac0 { pinctrl-names = "default"; pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii"; phy-handle = <&ext_rgmii_phy>; - allwinner,rx-delay-ps = <3100>; - allwinner,tx-delay-ps = <700>; status = "okay"; }; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts index d83852e72f0..b5d713926a3 100644 --- a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts @@ -13,6 +13,9 @@ }; &emac0 { + allwinner,rx-delay-ps = <3100>; + allwinner,tx-delay-ps = <700>; + phy-mode = "rgmii"; phy-supply = <®_dcdce>; }; diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts index 00fe28caac9..b3b1b869212 100644 --- a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts +++ b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts @@ -13,6 +13,8 @@ }; &emac0 { + allwinner,tx-delay-ps = <700>; + phy-mode = "rgmii-rxid"; phy-supply = <®_dldo1>; }; diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts index 5d8f21059f6..5cf604e8659 100644 --- a/arch/arm/dts/tegra20-paz00.dts +++ b/arch/arm/dts/tegra20-paz00.dts @@ -522,8 +522,8 @@ power-supply = <&vdd_bl_reg>; pwms = <&pwm 0 5000000>; - brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; - default-brightness-level = <10>; + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <2>; backlight-boot-off; }; diff --git a/arch/arm/dts/tegra30-asus-grouper-common.dtsi b/arch/arm/dts/tegra30-asus-grouper-common.dtsi index c9277388c9a..e8a3511a9f7 100644 --- a/arch/arm/dts/tegra30-asus-grouper-common.dtsi +++ b/arch/arm/dts/tegra30-asus-grouper-common.dtsi @@ -44,6 +44,718 @@ }; }; + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat3_pb4", + "sdmmc3_dat2_pb5", + "sdmmc3_dat1_pb6", + "sdmmc3_dat0_pb7", + "sdmmc3_dat4_pd1", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pwr1_pc1", + "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd_pclk_pb3 { + nvidia,pins = "lcd_pclk_pb3", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_dc0_pn6", + "lcd_cs1_n_pw0", + "lcd_sdin_pz2", + "lcd_sck_pz4"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs4_n_pk2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_dat5_pd0 { + nvidia,pins = "sdmmc3_dat5_pd0"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad14_ph6", + "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad6_pg6", + "gmi_ad7_pg7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad4_pg4 { + nvidia,pins = "gmi_ad4_pg4", + "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad11_ph3 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_adv_n_pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad15_ph7 { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_dqs_pi2 { + nvidia,pins = "gmi_dqs_pi2", + "pu2", + "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_rst_n_pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_cs7_n_pi6 { + nvidia,pins = "gmi_cs7_n_pi6", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0", + "kb_col1_pq1", + "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2", + "kb_col3_pq3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7", + "kb_row2_pr2", + "kb_row4_pr4", + "kb_row5_pr5", + "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6", + "kb_row8_ps0", + "kb_row9_ps1", + "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3", + "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu0 { + nvidia,pins = "pu0", + "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2", + "spi2_miso_px1", + "spi2_sck_px2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_cs0_n_px3 { + nvidia,pins = "spi2_cs0_n_px3"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_wr_n_pz3 { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + pbb0 { + nvidia,pins = "pbb0", + "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb7 { + nvidia,pins = "pbb7", + "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1", + "drive_sdio3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; + }; + drive_gma { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + }; + }; + uarta: serial@70006000 { status = "okay"; }; diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts index bfc675ca926..1714e083e91 100644 --- a/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts +++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts @@ -7,6 +7,119 @@ model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) E1565"; compatible = "asus,grouper", "nvidia,tegra30"; + pinmux@70000868 { + state_default: pinmux { + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs4_n_pk2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + }; + }; + i2c@7000d000 { pmic: max77663@3c { compatible = "maxim,max77663"; diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts index cf03011bc1f..e7765a4a6ae 100644 --- a/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts +++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts @@ -7,6 +7,119 @@ model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) PM269"; compatible = "asus,grouper", "nvidia,tegra30"; + pinmux@70000868 { + state_default: pinmux { + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs4_n_pk2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + }; + }; + i2c@7000d000 { /* Texas Instruments TPS659110 PMIC */ pmic: tps65911@2d { diff --git a/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts index ef8b2b5049b..3f0dff8fe65 100644 --- a/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts +++ b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts @@ -7,6 +7,155 @@ model = "ASUS Google Nexus 7 (Project Bach / ME370TG) E1565"; compatible = "asus,tilapia", "nvidia,tegra30"; + pinmux@70000868 { + state_default: pinmux { + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs4_n_pk2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + }; + }; + i2c@7000d000 { pmic: max77663@3c { compatible = "maxim,max77663"; diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts index 19de984d5fe..350443d55eb 100644 --- a/arch/arm/dts/tegra30-asus-p1801-t.dts +++ b/arch/arm/dts/tegra30-asus-p1801-t.dts @@ -60,6 +60,988 @@ }; }; + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1_clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_cmd { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_cd { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_wp { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC2 pinmux */ + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3_clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_dat4_pd1", + "sdmmc3_dat5_pd0", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_rst_n { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + drive_sdmmc4 { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + + /* I2C pinmux */ + gen1_i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + gen2_i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + cam_i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + ddc_i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + pwr_i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + hotplug_i2c { + nvidia,pins = "pu4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* HDMI pinmux */ + hdmi_cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + hdmi_hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-A */ + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-B */ + uartb_txd_rts { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uartb_rxd_cts { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-C */ + uartc_rxd_cts { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartc_txd_rts { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UART-D */ + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* I2S pinmux */ + dap_i2s0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap_i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_fs { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_dout { + nvidia,pins = "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap_i2s3 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* sensors pinmux */ + nct_irq { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Asus EC pinmux */ + ec_irqs { + nvidia,pins = "kb_row10_ps2", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ec_reqs { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* memory type bootstrap */ + mem_boostraps { + nvidia,pins = "gmi_ad4_pg4", + "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PCI-e pinmux */ + pex_l2_rst_n { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pex_l2_clkreq_n { + nvidia,pins = "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_wake_n_pdd3", + "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SPI pinmux */ + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Display A pinmux */ + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_cs1_n_pw0", + "lcd_dc0_pn6", + "lcd_sck_pz4", + "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + blink { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* KBC keys */ + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_col1_pq1 { + nvidia,pins = "kb_row1_pr1", + "kb_row3_pr3", + "kb_row9_ps1", + "kb_row11_ps3", + "kb_row14_ps6", + "kb_col6_pq6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7", + "kb_row2_pr2", + "kb_row4_pr4", + "kb_row5_pr5", + "kb_row12_ps4", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_cs0_n_pj0 { + nvidia,pins = "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* GPIO keys pinmux */ + power_key { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + vol_keys { + nvidia,pins = "kb_col2_pq2", + "kb_col3_pq3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Bluetooth */ + bt_shutdown { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bt_dev_wake { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt_host_wake { + nvidia,pins = "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2", + "vi_d0_pt4", "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_rst_n_pi4"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + /* USB2 VBUS control */ + usb2_vbus_control { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + /* PWM pinmux */ + pwm_0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwm_1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwm_2 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* S/PDIF pinmux */ + spdif_out { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif_in { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk1_out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk2_out { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk3_out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sys_clk_req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5", + "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* P1801-T specific pinmux */ + lcd_pwr2 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_m1 { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + key_mode { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + splashtop { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "nand_alt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + w8_detect { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand_alt"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + tp_vendor { + nvidia,pins = "kb_row6_pr6", + "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + tp_power { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* GPIO power/drive control */ + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1", + "drive_sdio3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; + }; + }; + }; + uarta: serial@70006000 { status = "okay"; }; diff --git a/arch/arm/dts/tegra30-asus-tf201.dts b/arch/arm/dts/tegra30-asus-tf201.dts index 59e19f97667..12dd909b5fe 100644 --- a/arch/arm/dts/tegra30-asus-tf201.dts +++ b/arch/arm/dts/tegra30-asus-tf201.dts @@ -7,6 +7,51 @@ model = "ASUS Transformer Prime TF201"; compatible = "asus,tf201", "nvidia,tegra30"; + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + }; + }; + usb-phy@7d008000 { /delete-property/ nvidia,xcvr-setup-use-fuses; nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */ diff --git a/arch/arm/dts/tegra30-asus-tf300t.dts b/arch/arm/dts/tegra30-asus-tf300t.dts index db08488420e..b30afa30228 100644 --- a/arch/arm/dts/tegra30-asus-tf300t.dts +++ b/arch/arm/dts/tegra30-asus-tf300t.dts @@ -15,4 +15,49 @@ output-low; }; }; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + }; + }; }; diff --git a/arch/arm/dts/tegra30-asus-tf300tg.dts b/arch/arm/dts/tegra30-asus-tf300tg.dts index 6f42182c99d..83921c664c4 100644 --- a/arch/arm/dts/tegra30-asus-tf300tg.dts +++ b/arch/arm/dts/tegra30-asus-tf300tg.dts @@ -6,4 +6,132 @@ / { model = "ASUS Transformer Pad 3G TF300TG"; compatible = "asus,tf300tg", "nvidia,tegra30"; + + pinmux@70000868 { + state_default: pinmux { + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + }; + + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + }; + }; }; diff --git a/arch/arm/dts/tegra30-asus-tf300tl.dts b/arch/arm/dts/tegra30-asus-tf300tl.dts index 242f79170c4..13b96fd0b08 100644 --- a/arch/arm/dts/tegra30-asus-tf300tl.dts +++ b/arch/arm/dts/tegra30-asus-tf300tl.dts @@ -6,4 +6,167 @@ / { model = "ASUS Transformer Pad LTE TF300TL"; compatible = "asus,tf300tl", "nvidia,tegra30"; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* TF300TL specific pinmux reconfiguration */ + + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + crt_vsync_pv7 { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + }; + + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + }; + }; }; diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts index 3f11d33bc4a..f49e7341fe0 100644 --- a/arch/arm/dts/tegra30-asus-tf600t.dts +++ b/arch/arm/dts/tegra30-asus-tf600t.dts @@ -53,6 +53,895 @@ }; }; + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1_clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_cmd { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_cd { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_wp { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC2 pinmux */ + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3_clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_dat4_pd1", + "sdmmc3_dat5_pd0", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_rst_n { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* I2C pinmux */ + gen1_i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + gen2_i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + cam_i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + ddc_i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + pwr_i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + hotplug_i2c { + nvidia,pins = "pu4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* HDMI pinmux */ + hdmi_cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + hdmi_hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-A */ + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-B */ + uartb_txd_rts { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uartb_rxd_cts { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-C */ + uartc_rxd_cts { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartc_txd_rts { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UART-D */ + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* I2S pinmux */ + dap_i2s0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap_i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_fs { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_din { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_dout { + nvidia,pins = "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap_i2s3 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + i2s4 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + nct_irq { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hall { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Asus EC pinmux */ + ec_irqs { + nvidia,pins = "kb_row10_ps2", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ec_reqs { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Memory type bootstrap */ + mem_boostraps { + nvidia,pins = "gmi_ad4_pg4", + "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PCI-e pinmux */ + pex_l2_rst_n { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pex_l2_clkreq_n { + nvidia,pins = "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_wake_n_pdd3", + "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Display A pinmux */ + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_cs1_n_pw0", + "lcd_m1_pw1", + "lcd_dc0_pn6", + "lcd_sck_pz4", + "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_sdout_pn5", + "lcd_wr_n_pz3", + "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + blink { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* KBC keys */ + kb_col0 { + nvidia,pins = "kb_col0_pq0", + "kb_row1_pr1", + "kb_row3_pr3", + "kb_row6_pr6", + "kb_row8_ps0", + "kb_row9_ps1", + "kb_row11_ps3", + "kb_row14_ps6", + "kb_col6_pq6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col5 { + nvidia,pins = "kb_col5_pq5", + "kb_col7_pq7", + "kb_row2_pr2", + "kb_row4_pr4", + "kb_row5_pr5", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_cs0_n_pj0 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs2_n_pk3", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* GPIO keys pinmux */ + power_key { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + vol_keys { + nvidia,pins = "kb_col3_pq3", + "kb_col4_pq4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Bluetooth */ + bt_shutdown { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bt_dev_wake { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt_host_wake { + nvidia,pins = "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2", + "vi_d0_pt4", "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_rst_n_pi4", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Vibrator control */ + vibrator { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PWM pinmux */ + pwm_0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwm_1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwm_2 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_cs_n { + nvidia,pins = "gmi_cs4_n_pk2", + "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Spdif pinmux */ + spdif_out { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif_in { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + jtag { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + crt_sync { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk1_out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk2_out { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk3_out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + sys_clk_req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5", + "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO power/drive control */ + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1", + "drive_sdio3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; + }; + drive_sdmmc4 { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + }; + }; + uarta: serial@70006000 { status = "okay"; }; diff --git a/arch/arm/dts/tegra30-asus-tf700t.dts b/arch/arm/dts/tegra30-asus-tf700t.dts index d530527c9f8..cc03f5a7ec2 100644 --- a/arch/arm/dts/tegra30-asus-tf700t.dts +++ b/arch/arm/dts/tegra30-asus-tf700t.dts @@ -9,5 +9,58 @@ /delete-node/ host1x@50000000; + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + }; + }; + /delete-node/ panel; }; diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi index c4649eee79d..e6cc6e7105f 100644 --- a/arch/arm/dts/tegra30-asus-transformer.dtsi +++ b/arch/arm/dts/tegra30-asus-transformer.dtsi @@ -37,6 +37,990 @@ }; }; + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1_clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc1_cmd { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc1_cd { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc1_wp { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC2 pinmux */ + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3_clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc3_cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_dat4_pd1", + "sdmmc3_dat5_pd0", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc4_cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc4_rst_n { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + cam_mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + drive_sdmmc4 { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + + /* I2C pinmux */ + gen1_i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + gen2_i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + cam_i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + ddc_i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + pwr_i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + hotplug_i2c { + nvidia,pins = "pu4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* HDMI pinmux */ + hdmi_cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + hdmi_hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-A */ + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-B */ + uartb_txd_rts { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + uartb_rxd_cts { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-C */ + uartc_rxd_cts { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + uartc_txd_rts { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UART-D */ + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* I2S pinmux */ + dap_i2s0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap_i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap3_fs { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap3_dout { + nvidia,pins = "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap_i2s3 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + nct_irq { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Asus EC pinmux */ + ec_irqs { + nvidia,pins = "kb_row10_ps2", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ec_reqs { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Memory type bootstrap */ + mem_boostraps { + nvidia,pins = "gmi_ad4_pg4", + "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PCI-e pinmux */ + pex_l2_rst_n { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pex_l2_clkreq_n { + nvidia,pins = "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_wake_n_pdd3", + "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SPI pinmux */ + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + hp_detect { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + mic_detect { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Display A pinmux */ + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_cs1_n_pw0", + "lcd_m1_pw1", + "lcd_dc0_pn6", + "lcd_sck_pz4", + "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + blink { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* KBC keys */ + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + kb_col1_pq1 { + nvidia,pins = "kb_row1_pr1", + "kb_row3_pr3", + "kb_row6_pr6", + "kb_row8_ps0", + "kb_row9_ps1", + "kb_row11_ps3", + "kb_row14_ps6", + "kb_col6_pq6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7", + "kb_row2_pr2", + "kb_row4_pr4", + "kb_row5_pr5", + "kb_row12_ps4", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_cs0_n_pj0 { + nvidia,pins = "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + /* GPIO keys pinmux */ + power_key { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + vol_keys { + nvidia,pins = "kb_col2_pq2", + "kb_col3_pq3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Bluetooth */ + bt_shutdown { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + bt_dev_wake { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + bt_host_wake { + nvidia,pins = "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2", + "vi_d0_pt4", "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_rst_n_pi4", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Vibrator control */ + vibrator { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PWM pimnmux */ + pwm_0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwm_1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwm_2 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Spdif pinmux */ + spdif_out { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spdif_in { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + jtag_rtck { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk1_out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk2_out { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk3_out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + sys_clk_req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5", + "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO power/drive control */ + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1", + "drive_sdio3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; + }; + }; + }; + uarta: serial@70006000 { status = "okay"; }; diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts index 21cd0f9207b..dbff795bd89 100644 --- a/arch/arm/dts/tegra30-htc-endeavoru.dts +++ b/arch/arm/dts/tegra30-htc-endeavoru.dts @@ -52,6 +52,1153 @@ }; }; + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* PORT A */ + clk_32k_out { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt_uart_cts { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_aic3008_i2s { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + wifi_sdio_clock { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + wifi_sdio_command { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT B */ + mdm_imc_uart { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_3v3_en { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + wifi_sdio_data { + nvidia,pins = "sdmmc3_dat3_pb4", + "sdmmc3_dat2_pb5", + "sdmmc3_dat1_pb6", + "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT C */ + bt_uart_rts { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mdm_ap2bb_rst_pwrdwn { + nvidia,pins = "lcd_pwr1_pc1"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cam_spi_clk_do { + nvidia,pins = "uart2_txd_pc2", + "uart2_rxd_pc3"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + per_sensor_i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + mdm_ap2bb_slave_wakeup { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mhl_int { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT D */ + sdmmc3_data { + nvidia,pins = "sdmmc3_dat5_pd0", + "sdmmc3_dat4_pd1"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_1v8_en { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_dat6_pd3 { + nvidia,pins = "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT E */ + mhl_usb_sel { + nvidia,pins = "lcd_d0_pe0"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd_d1_pe1 { + nvidia,pins = "lcd_d1_pe1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + peh_cap_int { + nvidia,pins = "lcd_d2_pe2"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mhl_1v2_en { + nvidia,pins = "lcd_d3_pe3", + "lcd_d4_pe4"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dsp_lcm_1v8_en { + nvidia,pins = "lcd_d5_pe5"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mhl_rst { + nvidia,pins = "lcd_d6_pe6"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + peh_vibrator_on { + nvidia,pins = "lcd_d7_pe7"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT F */ + cam_vcm_2v85_pwr { + nvidia,pins = "lcd_d8_pf0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_d9_d13 { + nvidia,pins = "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_cam2_core_1v8_en { + nvidia,pins = "lcd_d14_pf6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sys_pmu_msecure { + nvidia,pins = "lcd_d15_pf7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PORT G */ + bootstraps { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT H */ + haptic_pwm { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad9 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_ad10 { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dsp_tp_rst { + nvidia,pins = "gmi_ad11_ph3", + "gmi_ad12_ph4", + "gmi_ad13_ph5", + "gmi_ad14_ph6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_ad15 { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT I */ + gmi_wr_n { + nvidia,pins = "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_cs6_n_pi3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_rst_n_pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sim_detect { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + peh_gyr_int { + nvidia,pins = "gmi_cs7_n_pi6", + "gmi_wait_pi7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT J */ + mdm_bb2ap_host_wakeup { + nvidia,pins = "gmi_cs0_n_pj0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dsp_lcm_de { + nvidia,pins = "lcd_de_pj1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + peh_comp_int { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_hsync { + nvidia,pins = "lcd_hsync_pj3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mdm_ap_usb_uart_oe { + nvidia,pins = "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mcam_spi_di_cs0 { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rts_n_pj6"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mdm_tx { + nvidia,pins = "gmi_a16_pj7"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PORT K */ + gmi_adv_n { + nvidia,pins = "gmi_adv_n_pk0", + "gmi_clk_pk1", + "gmi_cs2_n_pk3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_cs4_n { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_cs3_n { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spdif_out { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif_in { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mdm_rts { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PORT L */ + port_l { + nvidia,pins = "vi_d2_pl0", + "vi_d3_pl1", + "vi_d4_pl2", + "vi_d5_pl3", + "vi_d6_pl4", + "vi_d7_pl5", + "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT M */ + dsp_lcd_id { + nvidia,pins = "lcd_d16_pm0", + "lcd_d17_pm1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + front_cam_rst { + nvidia,pins = "lcd_d18_pm2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mdm_v_dcin_modem_en { + nvidia,pins = "lcd_d19_pm3", + "lcd_d20_pm4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + nfc_pins { + nvidia,pins = "lcd_d21_pm5", + "lcd_d22_pm6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cam_vaa_2v85_en { + nvidia,pins = "lcd_d23_pm7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT N */ + mdm_ap2bb_rst_host_pwr { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mdm_bb_fatal_int { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_cs0_n { + nvidia,pins = "lcd_cs0_n_pn4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_sdout { + nvidia,pins = "lcd_sdout_pn5"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dsp_lcd_rst { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mhl_hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT O */ + ap_usb_uart_sel { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bsp_ap_debug_tx { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bsp_ap_debug_rx { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data2 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + con_wifi_irq { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "hsi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + per_gsensor_int { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data5_data6 { + nvidia,pins = "ulpi_data5_po6", + "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT P */ + aud_ap_pcm { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_btpcm { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_ext { + nvidia,pins = "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PORT Q */ + port_q { + nvidia,pins = "kb_col0_pq0", + "kb_col1_pq1", + "kb_col2_pq2", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_col5_pq5", + "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT R */ + raw_intr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + per_torch_en { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gyro_pwr { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + haptic_en { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row4_row5 { + nvidia,pins = "kb_row4_pr4", + "kb_row5_pr5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_id { + nvidia,pins = "kb_row6_pr6", + "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT S */ + dsp_vol_up { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + con_usb_id_1 { + nvidia,pins = "kb_row9_ps1", + "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + port_s { + nvidia,pins = "kb_row11_ps3", + "kb_row12_ps4", + "kb_row13_ps5", + "kb_row14_ps6", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT T */ + dsp_tw_i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + per_emmc_cmd { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT U */ + con_bt_en { + nvidia,pins = "pu0", "pu1", "pu2", + "pu3", "pu4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + per_capsensor_int_cpu { + nvidia,pins = "pu5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dsp_ap_kpdpwr { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT V */ + mdm_bb2ap_suspend_req { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dsp_tp_att { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + con_wifi_en { + nvidia,pins = "pv2", "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mhl_ddc { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + crt_hsync { + nvidia,pins = "crt_hsync_pv6"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + crt_vsync { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PORT W */ + pwr_chg_stat { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dsp_bl_pwm_cpu { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + aud_hp_det { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dsp_vol_down { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_mclk { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_aic3008_rst { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + con_bt_tx { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + con_bt_rx { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT X */ + aud_spi_do { + nvidia,pins = "spi2_mosi_px0", + "spi2_sck_px2", + "spi2_cs0_n_px3"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + aud_spi_di { + nvidia,pins = "spi2_miso_px1"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_mosi { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pwr_chg_int { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_cs0_n { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + audio_mclk_en { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PORT Y */ + led_drv_en_trig { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mhl_3v3_en { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + peh_v_srio_1v8_en { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_remo_tx { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "uarte"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + aud_remo_rx { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "uarte"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + nfc_irq { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + testpoint1 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT Z */ + aud_remo_oe { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + testpoint2 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mdm_usb_uart_oe { + nvidia,pins = "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_wr_n { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_sck { + nvidia,pins = "lcd_sck_pz4"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sys_clk_req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sys_pwr_i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + + /* PORT AA */ + bsp_emmc { + nvidia,pins = "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT BB */ + cam1_rst { + nvidia,pins = "pbb0"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + per_flash_en { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cam_vddio_1v8_en { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam1_vcm_pd { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_remo_pres { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + front_cam_standby { + nvidia,pins = "pbb7"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT CC */ + cam_mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_sel { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pwr_themp_alert_int { + nvidia,pins = "pcc2"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bsp_emmc_resout { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bsp_emmc_clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_dock_out_en { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PORT DD */ + /* PORT EE */ + clk3_out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + raw_intr1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk1_req { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hdmi_cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + }; + }; + uarta: serial@70006000 { status = "okay"; }; diff --git a/arch/arm/dts/tegra30-lg-p880.dts b/arch/arm/dts/tegra30-lg-p880.dts index 81d364310d0..1d5ca1459bc 100644 --- a/arch/arm/dts/tegra30-lg-p880.dts +++ b/arch/arm/dts/tegra30-lg-p880.dts @@ -11,6 +11,96 @@ mmc1 = &sdmmc3; /* uSD slot */ }; + pinmux@70000868 { + state_default: pinmux { + /* WLAN SDIO pinmux */ + host_wlan_wake { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GNSS UART-B pinmux */ + uartb_rxd { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartb_txd { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gps_reset { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* MicroSD pinmux */ + sdmmc3_clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_data { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + microsd_detect { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO keys pinmux */ + volume_up { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + current_alert_irq { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* AUDIO pinmux */ + sub_mic_ldo { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + }; + }; + sdmmc3: sdhci@78000400 { status = "okay"; bus-width = <4>; diff --git a/arch/arm/dts/tegra30-lg-p895.dts b/arch/arm/dts/tegra30-lg-p895.dts index 074205d5a98..43bb373a164 100644 --- a/arch/arm/dts/tegra30-lg-p895.dts +++ b/arch/arm/dts/tegra30-lg-p895.dts @@ -15,6 +15,99 @@ }; }; + pinmux@70000868 { + state_default: pinmux { + /* GNSS UART-B pinmux */ + uartb_cts_rxd { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartb_rts_txd { + nvidia,pins = "uart2_rts_n_pj6", + "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gps_reset { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* GPIO keys pinmux */ + volume_up { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + memo_key { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + current_alert_irq { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Panel pinmux */ + panel_vdd { + nvidia,pins = "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* AUDIO pinmux */ + sub_mic_ldo { + nvidia,pins = "gmi_dqs_pi2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Modem pinmux */ + usim_detect { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO power/drive control */ + drive_sdmmc4 { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + }; + }; + panel: panel { compatible = "hitachi,tx13d100vm0eaa"; diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi index 01936b872e0..30d6dcb6548 100644 --- a/arch/arm/dts/tegra30-lg-x3.dtsi +++ b/arch/arm/dts/tegra30-lg-x3.dtsi @@ -37,6 +37,851 @@ }; }; + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* WLAN SDIO pinmux */ + sdmmc1_clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_cmd { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + wlan_reset { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + wlan_host_wake { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GNSS UART-B pinmux */ + gps_pwr_en { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gps_ldo_en { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gps_clk_ref { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Bluetooth UART-C pinmux */ + uartc_cts_rxd { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartc_rts_txd { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt_reset { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt_dev_wake { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt_host_wake { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bt_pcm_dap4 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* EMMC pinmux */ + sdmmc4_clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_data { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_reset { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* I2C pinmux */ + gen1_i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + + gen2_i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + + cam_i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + + ddc_i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + + pwr_i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + + mhl_i2c { + nvidia,pins = "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO keys pinmux */ + power_key { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + volume_down { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + sen_vdd { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + proxi_vdd { + nvidia,pins = "spi2_miso_px1"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sen_vio { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + nct_irq { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bat_irq { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + charger_irq { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mpu_irq { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + compass_irq { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + light_irq { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* LED pinmux */ + backlight_en { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + flash_led_en { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + keypad_led { + nvidia,pins = "kb_row2_pr2", + "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* NFC pinmux */ + nfc_irq { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + nfc_ven { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + nfc_firm { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* DC pinmux */ + lcd_pwr { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pwr1_pc1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd_wr_n { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_id { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd_pclk { + nvidia,pins = "lcd_pclk_pb3", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + lcd_rgb_blue { + nvidia,pins = "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d18_pm2", + "lcd_d19_pm3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_rgb_green { + nvidia,pins = "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d20_pm4", + "lcd_d21_pm5"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_rgb_red { + nvidia,pins = "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d22_pm6", + "lcd_d23_pm7"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Bridge pinmux */ + bridge_reset { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + rgb_ic_en { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bridge_clk { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + rgb_bridge { + nvidia,pins = "lcd_sdin_pz2", + "lcd_sdout_pn5", + "lcd_cs0_n_pn4", + "lcd_sck_pz4"; + nvidia,function = "spi5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Panel pinmux */ + panel_reset { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + panel_vio { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Touchscreen pinmux */ + touch_vdd { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + touch_vio { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + touch_int_n { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + touch_rst_n { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + touch_maker_id { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* MHL pinmux */ + mhl_vio { + nvidia,pins = "pv2"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mhl_rst_n { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mhl_int { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mhl_sel { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + hdmi_hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* AUDIO pinmux */ + hp_detect { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hp_hook { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ear_mic_en { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + audio_irq { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + audio_mclk { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap_i2s0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap_i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* MUIC pinmux */ + muic_irq { + nvidia,pins = "gmi_cs0_n_pj0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + muic_dp2t { + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + muic_usif { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ifx_usb_vbus_en { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pcb_rev { + nvidia,pins = "gmi_wait_pi7", + "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Camera pinmux */ + cam_mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_pmic_en { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + front_cam_rst { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + front_cam_vio { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + rear_cam_rst { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + rear_cam_eprom_pr { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + rear_cam_vcm_pwdn { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Haptic pinmux */ + haptic_en { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + haptic_osc { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Modem pinmux */ + cp2ap_ack1_host_active { + nvidia,pins = "pu5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cp2ap_ack2_host_wakeup { + nvidia,pins = "pv0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ap2cp_ack2_suspend_req { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ap2cp_ack1_slave_wakeup { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + cp_kkp { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cp_crash_irq { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ap2cp_uarta_tx_ipc { + nvidia,pins = "pu0"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ap2cp_uarta_rx_ipc { + nvidia,pins = "pu1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + fota_ap_cts_cp_rts { + nvidia,pins = "pu2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + fota_ap_rts_cp_cts { + nvidia,pins = "pu3"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + modem_enable { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "hsi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + modem_reset { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + dap_i2s2 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO power/drive control */ + drive_i2c { + nvidia,pins = "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive_uart3 { + nvidia,pins = "drive_uart3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive_gmi { + nvidia,pins = "drive_at3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + }; + }; + uartd: serial@70006300 { status = "okay"; }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 516c9eab047..faace43da71 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -7,7 +7,6 @@ #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ -#include <linux/kconfig.h> #include <fsl_ddrc_version.h> #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 8f436517569..9e29350ca4b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -7,8 +7,6 @@ #ifndef __FSL_SERDES_H__ #define __FSL_SERDES_H__ -#include <config.h> - #ifdef CONFIG_FSL_LSCH3 enum srds_prtcl { /* diff --git a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h index d99a6f318f8..9244e0a78fd 100644 --- a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h +++ b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h @@ -6,8 +6,6 @@ #ifndef __FSL_SERDES_H #define __FSL_SERDES_H -#include <config.h> - enum srds_prtcl { /* * Nobody will check whether the device 'NONE' has been configured, diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 2359e142fb7..04910d594eb 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -174,8 +174,7 @@ struct clk_rst_ctlr { uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */ uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */ - uint crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */ - uint crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */ + struct clk_pll_simple plld2; /* _PLLD2_BASE_0, 0x4B8 */ uint crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */ uint crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */ uint crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */ diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h index 9b95b339e25..95fadd0c594 100644 --- a/arch/arm/include/asm/arch-tegra114/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra114/clock-tables.h @@ -23,6 +23,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DISPLAY2, /* These are the base clocks (inputs to the Tegra SOC) */ CLOCK_ID_32KHZ, @@ -30,7 +31,6 @@ enum clock_id { CLOCK_ID_CLK_M, CLOCK_ID_COUNT, /* number of PLLs */ - CLOCK_ID_DISPLAY2, /* placeholder */ CLOCK_ID_NONE = -1, }; diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h index 414b22e2013..63b36849315 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -312,6 +312,309 @@ enum pmux_func { PMUX_FUNC_COUNT, }; +static const char * const tegra_pinctrl_to_pingrp[] = { + [PMUX_PINGRP_ULPI_DATA0_PO1] = "ulpi_data0_po1", + [PMUX_PINGRP_ULPI_DATA1_PO2] = "ulpi_data1_po2", + [PMUX_PINGRP_ULPI_DATA2_PO3] = "ulpi_data2_po3", + [PMUX_PINGRP_ULPI_DATA3_PO4] = "ulpi_data3_po4", + [PMUX_PINGRP_ULPI_DATA4_PO5] = "ulpi_data4_po5", + [PMUX_PINGRP_ULPI_DATA5_PO6] = "ulpi_data5_po6", + [PMUX_PINGRP_ULPI_DATA6_PO7] = "ulpi_data6_po7", + [PMUX_PINGRP_ULPI_DATA7_PO0] = "ulpi_data7_po0", + [PMUX_PINGRP_ULPI_CLK_PY0] = "ulpi_clk_py0", + [PMUX_PINGRP_ULPI_DIR_PY1] = "ulpi_dir_py1", + [PMUX_PINGRP_ULPI_NXT_PY2] = "ulpi_nxt_py2", + [PMUX_PINGRP_ULPI_STP_PY3] = "ulpi_stp_py3", + [PMUX_PINGRP_DAP3_FS_PP0] = "dap3_fs_pp0", + [PMUX_PINGRP_DAP3_DIN_PP1] = "dap3_din_pp1", + [PMUX_PINGRP_DAP3_DOUT_PP2] = "dap3_dout_pp2", + [PMUX_PINGRP_DAP3_SCLK_PP3] = "dap3_sclk_pp3", + [PMUX_PINGRP_PV0] = "pv0", + [PMUX_PINGRP_PV1] = "pv1", + [PMUX_PINGRP_SDMMC1_CLK_PZ0] = "sdmmc1_clk_pz0", + [PMUX_PINGRP_SDMMC1_CMD_PZ1] = "sdmmc1_cmd_pz1", + [PMUX_PINGRP_SDMMC1_DAT3_PY4] = "sdmmc1_dat3_py4", + [PMUX_PINGRP_SDMMC1_DAT2_PY5] = "sdmmc1_dat2_py5", + [PMUX_PINGRP_SDMMC1_DAT1_PY6] = "sdmmc1_dat1_py6", + [PMUX_PINGRP_SDMMC1_DAT0_PY7] = "sdmmc1_dat0_py7", + [PMUX_PINGRP_CLK2_OUT_PW5] = "clk2_out_pw5", + [PMUX_PINGRP_CLK2_REQ_PCC5] = "clk2_req_pcc5", + [PMUX_PINGRP_HDMI_INT_PN7] = "hdmi_int_pn7", + [PMUX_PINGRP_DDC_SCL_PV4] = "ddc_scl_pv4", + [PMUX_PINGRP_DDC_SDA_PV5] = "ddc_sda_pv5", + [PMUX_PINGRP_UART2_RXD_PC3] = "uart2_rxd_pc3", + [PMUX_PINGRP_UART2_TXD_PC2] = "uart2_txd_pc2", + [PMUX_PINGRP_UART2_RTS_N_PJ6] = "uart2_rts_n_pj6", + [PMUX_PINGRP_UART2_CTS_N_PJ5] = "uart2_cts_n_pj5", + [PMUX_PINGRP_UART3_TXD_PW6] = "uart3_txd_pw6", + [PMUX_PINGRP_UART3_RXD_PW7] = "uart3_rxd_pw7", + [PMUX_PINGRP_UART3_CTS_N_PA1] = "uart3_cts_n_pa1", + [PMUX_PINGRP_UART3_RTS_N_PC0] = "uart3_rts_n_pc0", + [PMUX_PINGRP_PU0] = "pu0", + [PMUX_PINGRP_PU1] = "pu1", + [PMUX_PINGRP_PU2] = "pu2", + [PMUX_PINGRP_PU3] = "pu3", + [PMUX_PINGRP_PU4] = "pu4", + [PMUX_PINGRP_PU5] = "pu5", + [PMUX_PINGRP_PU6] = "pu6", + [PMUX_PINGRP_GEN1_I2C_SDA_PC5] = "gen1_i2c_sda_pc5", + [PMUX_PINGRP_GEN1_I2C_SCL_PC4] = "gen1_i2c_scl_pc4", + [PMUX_PINGRP_DAP4_FS_PP4] = "dap4_fs_pp4", + [PMUX_PINGRP_DAP4_DIN_PP5] = "dap4_din_pp5", + [PMUX_PINGRP_DAP4_DOUT_PP6] = "dap4_dout_pp6", + [PMUX_PINGRP_DAP4_SCLK_PP7] = "dap4_sclk_pp7", + [PMUX_PINGRP_CLK3_OUT_PEE0] = "clk3_out_pee0", + [PMUX_PINGRP_CLK3_REQ_PEE1] = "clk3_req_pee1", + [PMUX_PINGRP_GMI_WP_N_PC7] = "gmi_wp_n_pc7", + [PMUX_PINGRP_GMI_IORDY_PI5] = "gmi_iordy_pi5", + [PMUX_PINGRP_GMI_WAIT_PI7] = "gmi_wait_pi7", + [PMUX_PINGRP_GMI_ADV_N_PK0] = "gmi_adv_n_pk0", + [PMUX_PINGRP_GMI_CLK_PK1] = "gmi_clk_pk1", + [PMUX_PINGRP_GMI_CS0_N_PJ0] = "gmi_cs0_n_pj0", + [PMUX_PINGRP_GMI_CS1_N_PJ2] = "gmi_cs1_n_pj2", + [PMUX_PINGRP_GMI_CS2_N_PK3] = "gmi_cs2_n_pk3", + [PMUX_PINGRP_GMI_CS3_N_PK4] = "gmi_cs3_n_pk4", + [PMUX_PINGRP_GMI_CS4_N_PK2] = "gmi_cs4_n_pk2", + [PMUX_PINGRP_GMI_CS6_N_PI3] = "gmi_cs6_n_pi3", + [PMUX_PINGRP_GMI_CS7_N_PI6] = "gmi_cs7_n_pi6", + [PMUX_PINGRP_GMI_AD0_PG0] = "gmi_ad0_pg0", + [PMUX_PINGRP_GMI_AD1_PG1] = "gmi_ad1_pg1", + [PMUX_PINGRP_GMI_AD2_PG2] = "gmi_ad2_pg2", + [PMUX_PINGRP_GMI_AD3_PG3] = "gmi_ad3_pg3", + [PMUX_PINGRP_GMI_AD4_PG4] = "gmi_ad4_pg4", + [PMUX_PINGRP_GMI_AD5_PG5] = "gmi_ad5_pg5", + [PMUX_PINGRP_GMI_AD6_PG6] = "gmi_ad6_pg6", + [PMUX_PINGRP_GMI_AD7_PG7] = "gmi_ad7_pg7", + [PMUX_PINGRP_GMI_AD8_PH0] = "gmi_ad8_ph0", + [PMUX_PINGRP_GMI_AD9_PH1] = "gmi_ad9_ph1", + [PMUX_PINGRP_GMI_AD10_PH2] = "gmi_ad10_ph2", + [PMUX_PINGRP_GMI_AD11_PH3] = "gmi_ad11_ph3", + [PMUX_PINGRP_GMI_AD12_PH4] = "gmi_ad12_ph4", + [PMUX_PINGRP_GMI_AD13_PH5] = "gmi_ad13_ph5", + [PMUX_PINGRP_GMI_AD14_PH6] = "gmi_ad14_ph6", + [PMUX_PINGRP_GMI_AD15_PH7] = "gmi_ad15_ph7", + [PMUX_PINGRP_GMI_A16_PJ7] = "gmi_a16_pj7", + [PMUX_PINGRP_GMI_A17_PB0] = "gmi_a17_pb0", + [PMUX_PINGRP_GMI_A18_PB1] = "gmi_a18_pb1", + [PMUX_PINGRP_GMI_A19_PK7] = "gmi_a19_pk7", + [PMUX_PINGRP_GMI_WR_N_PI0] = "gmi_wr_n_pi0", + [PMUX_PINGRP_GMI_OE_N_PI1] = "gmi_oe_n_pi1", + [PMUX_PINGRP_GMI_DQS_P_PJ3] = "gmi_dqs_p_pj3", + [PMUX_PINGRP_GMI_RST_N_PI4] = "gmi_rst_n_pi4", + [PMUX_PINGRP_GEN2_I2C_SCL_PT5] = "gen2_i2c_scl_pt5", + [PMUX_PINGRP_GEN2_I2C_SDA_PT6] = "gen2_i2c_sda_pt6", + [PMUX_PINGRP_SDMMC4_CLK_PCC4] = "sdmmc4_clk_pcc4", + [PMUX_PINGRP_SDMMC4_CMD_PT7] = "sdmmc4_cmd_pt7", + [PMUX_PINGRP_SDMMC4_DAT0_PAA0] = "sdmmc4_dat0_paa0", + [PMUX_PINGRP_SDMMC4_DAT1_PAA1] = "sdmmc4_dat1_paa1", + [PMUX_PINGRP_SDMMC4_DAT2_PAA2] = "sdmmc4_dat2_paa2", + [PMUX_PINGRP_SDMMC4_DAT3_PAA3] = "sdmmc4_dat3_paa3", + [PMUX_PINGRP_SDMMC4_DAT4_PAA4] = "sdmmc4_dat4_paa4", + [PMUX_PINGRP_SDMMC4_DAT5_PAA5] = "sdmmc4_dat5_paa5", + [PMUX_PINGRP_SDMMC4_DAT6_PAA6] = "sdmmc4_dat6_paa6", + [PMUX_PINGRP_SDMMC4_DAT7_PAA7] = "sdmmc4_dat7_paa7", + [PMUX_PINGRP_CAM_MCLK_PCC0] = "cam_mclk_pcc0", + [PMUX_PINGRP_PCC1] = "pcc1", + [PMUX_PINGRP_PBB0] = "pbb0", + [PMUX_PINGRP_CAM_I2C_SCL_PBB1] = "cam_i2c_scl_pbb1", + [PMUX_PINGRP_CAM_I2C_SDA_PBB2] = "cam_i2c_sda_pbb2", + [PMUX_PINGRP_PBB3] = "pbb3", + [PMUX_PINGRP_PBB4] = "pbb4", + [PMUX_PINGRP_PBB5] = "pbb5", + [PMUX_PINGRP_PBB6] = "pbb6", + [PMUX_PINGRP_PBB7] = "pbb7", + [PMUX_PINGRP_PCC2] = "pcc2", + [PMUX_PINGRP_JTAG_RTCK] = "jtag_rtck", + [PMUX_PINGRP_PWR_I2C_SCL_PZ6] = "pwr_i2c_scl_pz6", + [PMUX_PINGRP_PWR_I2C_SDA_PZ7] = "pwr_i2c_sda_pz7", + [PMUX_PINGRP_KB_ROW0_PR0] = "kb_row0_pr0", + [PMUX_PINGRP_KB_ROW1_PR1] = "kb_row1_pr1", + [PMUX_PINGRP_KB_ROW2_PR2] = "kb_row2_pr2", + [PMUX_PINGRP_KB_ROW3_PR3] = "kb_row3_pr3", + [PMUX_PINGRP_KB_ROW4_PR4] = "kb_row4_pr4", + [PMUX_PINGRP_KB_ROW5_PR5] = "kb_row5_pr5", + [PMUX_PINGRP_KB_ROW6_PR6] = "kb_row6_pr6", + [PMUX_PINGRP_KB_ROW7_PR7] = "kb_row7_pr7", + [PMUX_PINGRP_KB_ROW8_PS0] = "kb_row8_ps0", + [PMUX_PINGRP_KB_ROW9_PS1] = "kb_row9_ps1", + [PMUX_PINGRP_KB_ROW10_PS2] = "kb_row10_ps2", + [PMUX_PINGRP_KB_COL0_PQ0] = "kb_col0_pq0", + [PMUX_PINGRP_KB_COL1_PQ1] = "kb_col1_pq1", + [PMUX_PINGRP_KB_COL2_PQ2] = "kb_col2_pq2", + [PMUX_PINGRP_KB_COL3_PQ3] = "kb_col3_pq3", + [PMUX_PINGRP_KB_COL4_PQ4] = "kb_col4_pq4", + [PMUX_PINGRP_KB_COL5_PQ5] = "kb_col5_pq5", + [PMUX_PINGRP_KB_COL6_PQ6] = "kb_col6_pq6", + [PMUX_PINGRP_KB_COL7_PQ7] = "kb_col7_pq7", + [PMUX_PINGRP_CLK_32K_OUT_PA0] = "clk_32k_out_pa0", + [PMUX_PINGRP_SYS_CLK_REQ_PZ5] = "sys_clk_req_pz5", + [PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req", + [PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req", + [PMUX_PINGRP_PWR_INT_N] = "pwr_int_n", + [PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in", + [PMUX_PINGRP_OWR] = "owr", + [PMUX_PINGRP_DAP1_FS_PN0] = "dap1_fs_pn0", + [PMUX_PINGRP_DAP1_DIN_PN1] = "dap1_din_pn1", + [PMUX_PINGRP_DAP1_DOUT_PN2] = "dap1_dout_pn2", + [PMUX_PINGRP_DAP1_SCLK_PN3] = "dap1_sclk_pn3", + [PMUX_PINGRP_CLK1_REQ_PEE2] = "clk1_req_pee2", + [PMUX_PINGRP_CLK1_OUT_PW4] = "clk1_out_pw4", + [PMUX_PINGRP_SPDIF_IN_PK6] = "spdif_in_pk6", + [PMUX_PINGRP_SPDIF_OUT_PK5] = "spdif_out_pk5", + [PMUX_PINGRP_DAP2_FS_PA2] = "dap2_fs_pa2", + [PMUX_PINGRP_DAP2_DIN_PA4] = "dap2_din_pa4", + [PMUX_PINGRP_DAP2_DOUT_PA5] = "dap2_dout_pa5", + [PMUX_PINGRP_DAP2_SCLK_PA3] = "dap2_sclk_pa3", + [PMUX_PINGRP_DVFS_PWM_PX0] = "dvfs_pwm_px0", + [PMUX_PINGRP_GPIO_X1_AUD_PX1] = "gpio_x1_aud_px1", + [PMUX_PINGRP_GPIO_X3_AUD_PX3] = "gpio_x3_aud_px3", + [PMUX_PINGRP_DVFS_CLK_PX2] = "dvfs_clk_px2", + [PMUX_PINGRP_GPIO_X4_AUD_PX4] = "gpio_x4_aud_px4", + [PMUX_PINGRP_GPIO_X5_AUD_PX5] = "gpio_x5_aud_px5", + [PMUX_PINGRP_GPIO_X6_AUD_PX6] = "gpio_x6_aud_px6", + [PMUX_PINGRP_GPIO_X7_AUD_PX7] = "gpio_x7_aud_px7", + [PMUX_PINGRP_SDMMC3_CLK_PA6] = "sdmmc3_clk_pa6", + [PMUX_PINGRP_SDMMC3_CMD_PA7] = "sdmmc3_cmd_pa7", + [PMUX_PINGRP_SDMMC3_DAT0_PB7] = "sdmmc3_dat0_pb7", + [PMUX_PINGRP_SDMMC3_DAT1_PB6] = "sdmmc3_dat1_pb6", + [PMUX_PINGRP_SDMMC3_DAT2_PB5] = "sdmmc3_dat2_pb5", + [PMUX_PINGRP_SDMMC3_DAT3_PB4] = "sdmmc3_dat3_pb4", + [PMUX_PINGRP_HDMI_CEC_PEE3] = "hdmi_cec_pee3", + [PMUX_PINGRP_SDMMC1_WP_N_PV3] = "sdmmc1_wp_n_pv3", + [PMUX_PINGRP_SDMMC3_CD_N_PV2] = "sdmmc3_cd_n_pv2", + [PMUX_PINGRP_GPIO_W2_AUD_PW2] = "gpio_w2_aud_pw2", + [PMUX_PINGRP_GPIO_W3_AUD_PW3] = "gpio_w3_aud_pw3", + [PMUX_PINGRP_USB_VBUS_EN0_PN4] = "usb_vbus_en0_pn4", + [PMUX_PINGRP_USB_VBUS_EN1_PN5] = "usb_vbus_en1_pn5", + [PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5] = "sdmmc3_clk_lb_in_pee5", + [PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4] = "sdmmc3_clk_lb_out_pee4", + [PMUX_PINGRP_GMI_CLK_LB] = "gmi_clk_lb", + [PMUX_PINGRP_RESET_OUT_N] = "reset_out_n", +}; + +static const char * const tegra_pinctrl_to_drvgrp[] = { + [PMUX_DRVGRP_AO1] = "drive_ao1", + [PMUX_DRVGRP_AO2] = "drive_ao2", + [PMUX_DRVGRP_AT1] = "drive_at1", + [PMUX_DRVGRP_AT2] = "drive_at2", + [PMUX_DRVGRP_AT3] = "drive_at3", + [PMUX_DRVGRP_AT4] = "drive_at4", + [PMUX_DRVGRP_AT5] = "drive_at5", + [PMUX_DRVGRP_CDEV1] = "drive_cdev1", + [PMUX_DRVGRP_CDEV2] = "drive_cdev2", + [PMUX_DRVGRP_DAP1] = "drive_dap1", + [PMUX_DRVGRP_DAP2] = "drive_dap2", + [PMUX_DRVGRP_DAP3] = "drive_dap3", + [PMUX_DRVGRP_DAP4] = "drive_dap4", + [PMUX_DRVGRP_DBG] = "drive_dbg", + [PMUX_DRVGRP_SDIO3] = "drive_sdio3", + [PMUX_DRVGRP_SPI] = "drive_spi", + [PMUX_DRVGRP_UAA] = "drive_uaa", + [PMUX_DRVGRP_UAB] = "drive_uab", + [PMUX_DRVGRP_UART2] = "drive_uart2", + [PMUX_DRVGRP_UART3] = "drive_uart3", + [PMUX_DRVGRP_SDIO1] = "drive_sdio1", + [PMUX_DRVGRP_DDC] = "drive_ddc", + [PMUX_DRVGRP_GMA] = "drive_gma", + [PMUX_DRVGRP_GME] = "drive_gme", + [PMUX_DRVGRP_GMF] = "drive_gmf", + [PMUX_DRVGRP_GMG] = "drive_gmg", + [PMUX_DRVGRP_GMH] = "drive_gmh", + [PMUX_DRVGRP_OWR] = "drive_owr", + [PMUX_DRVGRP_UDA] = "drive_uda", + [PMUX_DRVGRP_DEV3] = "drive_dev3", + [PMUX_DRVGRP_CEC] = "drive_cec", + [PMUX_DRVGRP_AT6] = "drive_at6", + [PMUX_DRVGRP_DAP5] = "drive_dap5", + [PMUX_DRVGRP_USB_VBUS_EN] = "drive_usb_vbus_en", + [PMUX_DRVGRP_AO3] = "drive_ao3", + [PMUX_DRVGRP_HV0] = "drive_hv0", + [PMUX_DRVGRP_SDIO4] = "drive_sdio4", + [PMUX_DRVGRP_AO0] = "drive_ao0", +}; + +static const char * const tegra_pinctrl_to_func[] = { + [PMUX_FUNC_DEFAULT] = "default", + [PMUX_FUNC_BLINK] = "blink", + [PMUX_FUNC_CEC] = "cec", + [PMUX_FUNC_CLDVFS] = "cldvfs", + [PMUX_FUNC_CLK] = "clk", + [PMUX_FUNC_CLK12] = "clk12", + [PMUX_FUNC_CPU] = "cpu", + [PMUX_FUNC_DAP] = "dap", + [PMUX_FUNC_DAP1] = "dap1", + [PMUX_FUNC_DAP2] = "dap2", + [PMUX_FUNC_DEV3] = "dev3", + [PMUX_FUNC_DISPLAYA] = "displaya", + [PMUX_FUNC_DISPLAYA_ALT] = "displaya_alt", + [PMUX_FUNC_DISPLAYB] = "displayb", + [PMUX_FUNC_DTV] = "dtv", + [PMUX_FUNC_EMC_DLL] = "emc_dll", + [PMUX_FUNC_EXTPERIPH1] = "extperiph1", + [PMUX_FUNC_EXTPERIPH2] = "extperiph2", + [PMUX_FUNC_EXTPERIPH3] = "extperiph3", + [PMUX_FUNC_GMI] = "gmi", + [PMUX_FUNC_GMI_ALT] = "gmi_alt", + [PMUX_FUNC_HDA] = "hda", + [PMUX_FUNC_HSI] = "hsi", + [PMUX_FUNC_I2C1] = "i2c1", + [PMUX_FUNC_I2C2] = "i2c2", + [PMUX_FUNC_I2C3] = "i2c3", + [PMUX_FUNC_I2C4] = "i2c4", + [PMUX_FUNC_I2CPWR] = "i2cpwr", + [PMUX_FUNC_I2S0] = "i2s0", + [PMUX_FUNC_I2S1] = "i2s1", + [PMUX_FUNC_I2S2] = "i2s2", + [PMUX_FUNC_I2S3] = "i2s3", + [PMUX_FUNC_I2S4] = "i2s4", + [PMUX_FUNC_IRDA] = "irda", + [PMUX_FUNC_KBC] = "kbc", + [PMUX_FUNC_NAND] = "nand", + [PMUX_FUNC_NAND_ALT] = "nand_alt", + [PMUX_FUNC_OWR] = "owr", + [PMUX_FUNC_PMI] = "pmi", + [PMUX_FUNC_PWM0] = "pwm0", + [PMUX_FUNC_PWM1] = "pwm1", + [PMUX_FUNC_PWM2] = "pwm2", + [PMUX_FUNC_PWM3] = "pwm3", + [PMUX_FUNC_PWRON] = "pwron", + [PMUX_FUNC_RESET_OUT_N] = "reset_out_n", + [PMUX_FUNC_RTCK] = "rtck", + [PMUX_FUNC_SDMMC1] = "sdmmc1", + [PMUX_FUNC_SDMMC2] = "sdmmc2", + [PMUX_FUNC_SDMMC3] = "sdmmc3", + [PMUX_FUNC_SDMMC4] = "sdmmc4", + [PMUX_FUNC_SOC] = "soc", + [PMUX_FUNC_SPDIF] = "spdif", + [PMUX_FUNC_SPI1] = "spi1", + [PMUX_FUNC_SPI2] = "spi2", + [PMUX_FUNC_SPI3] = "spi3", + [PMUX_FUNC_SPI4] = "spi4", + [PMUX_FUNC_SPI5] = "spi5", + [PMUX_FUNC_SPI6] = "spi6", + [PMUX_FUNC_SYSCLK] = "sysclk", + [PMUX_FUNC_TRACE] = "trace", + [PMUX_FUNC_UARTA] = "uarta", + [PMUX_FUNC_UARTB] = "uartb", + [PMUX_FUNC_UARTC] = "uartc", + [PMUX_FUNC_UARTD] = "uartd", + [PMUX_FUNC_ULPI] = "ulpi", + [PMUX_FUNC_USB] = "usb", + [PMUX_FUNC_VGP1] = "vgp1", + [PMUX_FUNC_VGP2] = "vgp2", + [PMUX_FUNC_VGP3] = "vgp3", + [PMUX_FUNC_VGP4] = "vgp4", + [PMUX_FUNC_VGP5] = "vgp5", + [PMUX_FUNC_VGP6] = "vgp6", + [PMUX_FUNC_VI] = "vi", + [PMUX_FUNC_VI_ALT1] = "vi_alt1", + [PMUX_FUNC_VI_ALT3] = "vi_alt3", + [PMUX_FUNC_RSVD1] = "rsvd1", + [PMUX_FUNC_RSVD2] = "rsvd2", + [PMUX_FUNC_RSVD3] = "rsvd3", + [PMUX_FUNC_RSVD4] = "rsvd4", +}; + #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING #define TEGRA_PMX_SOC_HAS_DRVGRPS diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h index 4c593aae7c1..3aba17d21e4 100644 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -341,6 +341,333 @@ enum pmux_func { PMUX_FUNC_COUNT, }; +static const char * const tegra_pinctrl_to_pingrp[] = { + [PMUX_PINGRP_ULPI_DATA0_PO1] = "ulpi_data0_po1", + [PMUX_PINGRP_ULPI_DATA1_PO2] = "ulpi_data1_po2", + [PMUX_PINGRP_ULPI_DATA2_PO3] = "ulpi_data2_po3", + [PMUX_PINGRP_ULPI_DATA3_PO4] = "ulpi_data3_po4", + [PMUX_PINGRP_ULPI_DATA4_PO5] = "ulpi_data4_po5", + [PMUX_PINGRP_ULPI_DATA5_PO6] = "ulpi_data5_po6", + [PMUX_PINGRP_ULPI_DATA6_PO7] = "ulpi_data6_po7", + [PMUX_PINGRP_ULPI_DATA7_PO0] = "ulpi_data7_po0", + [PMUX_PINGRP_ULPI_CLK_PY0] = "ulpi_clk_py0", + [PMUX_PINGRP_ULPI_DIR_PY1] = "ulpi_dir_py1", + [PMUX_PINGRP_ULPI_NXT_PY2] = "ulpi_nxt_py2", + [PMUX_PINGRP_ULPI_STP_PY3] = "ulpi_stp_py3", + [PMUX_PINGRP_DAP3_FS_PP0] = "dap3_fs_pp0", + [PMUX_PINGRP_DAP3_DIN_PP1] = "dap3_din_pp1", + [PMUX_PINGRP_DAP3_DOUT_PP2] = "dap3_dout_pp2", + [PMUX_PINGRP_DAP3_SCLK_PP3] = "dap3_sclk_pp3", + [PMUX_PINGRP_PV0] = "pv0", + [PMUX_PINGRP_PV1] = "pv1", + [PMUX_PINGRP_SDMMC1_CLK_PZ0] = "sdmmc1_clk_pz0", + [PMUX_PINGRP_SDMMC1_CMD_PZ1] = "sdmmc1_cmd_pz1", + [PMUX_PINGRP_SDMMC1_DAT3_PY4] = "sdmmc1_dat3_py4", + [PMUX_PINGRP_SDMMC1_DAT2_PY5] = "sdmmc1_dat2_py5", + [PMUX_PINGRP_SDMMC1_DAT1_PY6] = "sdmmc1_dat1_py6", + [PMUX_PINGRP_SDMMC1_DAT0_PY7] = "sdmmc1_dat0_py7", + [PMUX_PINGRP_CLK2_OUT_PW5] = "clk2_out_pw5", + [PMUX_PINGRP_CLK2_REQ_PCC5] = "clk2_req_pcc5", + [PMUX_PINGRP_HDMI_INT_PN7] = "hdmi_int_pn7", + [PMUX_PINGRP_DDC_SCL_PV4] = "ddc_scl_pv4", + [PMUX_PINGRP_DDC_SDA_PV5] = "ddc_sda_pv5", + [PMUX_PINGRP_UART2_RXD_PC3] = "uart2_rxd_pc3", + [PMUX_PINGRP_UART2_TXD_PC2] = "uart2_txd_pc2", + [PMUX_PINGRP_UART2_RTS_N_PJ6] = "uart2_rts_n_pj6", + [PMUX_PINGRP_UART2_CTS_N_PJ5] = "uart2_cts_n_pj5", + [PMUX_PINGRP_UART3_TXD_PW6] = "uart3_txd_pw6", + [PMUX_PINGRP_UART3_RXD_PW7] = "uart3_rxd_pw7", + [PMUX_PINGRP_UART3_CTS_N_PA1] = "uart3_cts_n_pa1", + [PMUX_PINGRP_UART3_RTS_N_PC0] = "uart3_rts_n_pc0", + [PMUX_PINGRP_PU0] = "pu0", + [PMUX_PINGRP_PU1] = "pu1", + [PMUX_PINGRP_PU2] = "pu2", + [PMUX_PINGRP_PU3] = "pu3", + [PMUX_PINGRP_PU4] = "pu4", + [PMUX_PINGRP_PU5] = "pu5", + [PMUX_PINGRP_PU6] = "pu6", + [PMUX_PINGRP_GEN1_I2C_SDA_PC5] = "gen1_i2c_sda_pc5", + [PMUX_PINGRP_GEN1_I2C_SCL_PC4] = "gen1_i2c_scl_pc4", + [PMUX_PINGRP_DAP4_FS_PP4] = "dap4_fs_pp4", + [PMUX_PINGRP_DAP4_DIN_PP5] = "dap4_din_pp5", + [PMUX_PINGRP_DAP4_DOUT_PP6] = "dap4_dout_pp6", + [PMUX_PINGRP_DAP4_SCLK_PP7] = "dap4_sclk_pp7", + [PMUX_PINGRP_CLK3_OUT_PEE0] = "clk3_out_pee0", + [PMUX_PINGRP_CLK3_REQ_PEE1] = "clk3_req_pee1", + [PMUX_PINGRP_PC7] = "pc7", + [PMUX_PINGRP_PI5] = "pi5", + [PMUX_PINGRP_PI7] = "pi7", + [PMUX_PINGRP_PK0] = "pk0", + [PMUX_PINGRP_PK1] = "pk1", + [PMUX_PINGRP_PJ0] = "pj0", + [PMUX_PINGRP_PJ2] = "pj2", + [PMUX_PINGRP_PK3] = "pk3", + [PMUX_PINGRP_PK4] = "pk4", + [PMUX_PINGRP_PK2] = "pk2", + [PMUX_PINGRP_PI3] = "pi3", + [PMUX_PINGRP_PI6] = "pi6", + [PMUX_PINGRP_PG0] = "pg0", + [PMUX_PINGRP_PG1] = "pg1", + [PMUX_PINGRP_PG2] = "pg2", + [PMUX_PINGRP_PG3] = "pg3", + [PMUX_PINGRP_PG4] = "pg4", + [PMUX_PINGRP_PG5] = "pg5", + [PMUX_PINGRP_PG6] = "pg6", + [PMUX_PINGRP_PG7] = "pg7", + [PMUX_PINGRP_PH0] = "ph0", + [PMUX_PINGRP_PH1] = "ph1", + [PMUX_PINGRP_PH2] = "ph2", + [PMUX_PINGRP_PH3] = "ph3", + [PMUX_PINGRP_PH4] = "ph4", + [PMUX_PINGRP_PH5] = "ph5", + [PMUX_PINGRP_PH6] = "ph6", + [PMUX_PINGRP_PH7] = "ph7", + [PMUX_PINGRP_PJ7] = "pj7", + [PMUX_PINGRP_PB0] = "pb0", + [PMUX_PINGRP_PB1] = "pb1", + [PMUX_PINGRP_PK7] = "pk7", + [PMUX_PINGRP_PI0] = "pi0", + [PMUX_PINGRP_PI1] = "pi1", + [PMUX_PINGRP_PI2] = "pi2", + [PMUX_PINGRP_PI4] = "pi4", + [PMUX_PINGRP_GEN2_I2C_SCL_PT5] = "gen2_i2c_scl_pt5", + [PMUX_PINGRP_GEN2_I2C_SDA_PT6] = "gen2_i2c_sda_pt6", + [PMUX_PINGRP_SDMMC4_CLK_PCC4] = "sdmmc4_clk_pcc4", + [PMUX_PINGRP_SDMMC4_CMD_PT7] = "sdmmc4_cmd_pt7", + [PMUX_PINGRP_SDMMC4_DAT0_PAA0] = "sdmmc4_dat0_paa0", + [PMUX_PINGRP_SDMMC4_DAT1_PAA1] = "sdmmc4_dat1_paa1", + [PMUX_PINGRP_SDMMC4_DAT2_PAA2] = "sdmmc4_dat2_paa2", + [PMUX_PINGRP_SDMMC4_DAT3_PAA3] = "sdmmc4_dat3_paa3", + [PMUX_PINGRP_SDMMC4_DAT4_PAA4] = "sdmmc4_dat4_paa4", + [PMUX_PINGRP_SDMMC4_DAT5_PAA5] = "sdmmc4_dat5_paa5", + [PMUX_PINGRP_SDMMC4_DAT6_PAA6] = "sdmmc4_dat6_paa6", + [PMUX_PINGRP_SDMMC4_DAT7_PAA7] = "sdmmc4_dat7_paa7", + [PMUX_PINGRP_CAM_MCLK_PCC0] = "cam_mclk_pcc0", + [PMUX_PINGRP_PCC1] = "pcc1", + [PMUX_PINGRP_PBB0] = "pbb0", + [PMUX_PINGRP_CAM_I2C_SCL_PBB1] = "cam_i2c_scl_pbb1", + [PMUX_PINGRP_CAM_I2C_SDA_PBB2] = "cam_i2c_sda_pbb2", + [PMUX_PINGRP_PBB3] = "pbb3", + [PMUX_PINGRP_PBB4] = "pbb4", + [PMUX_PINGRP_PBB5] = "pbb5", + [PMUX_PINGRP_PBB6] = "pbb6", + [PMUX_PINGRP_PBB7] = "pbb7", + [PMUX_PINGRP_PCC2] = "pcc2", + [PMUX_PINGRP_JTAG_RTCK] = "jtag_rtck", + [PMUX_PINGRP_PWR_I2C_SCL_PZ6] = "pwr_i2c_scl_pz6", + [PMUX_PINGRP_PWR_I2C_SDA_PZ7] = "pwr_i2c_sda_pz7", + [PMUX_PINGRP_KB_ROW0_PR0] = "kb_row0_pr0", + [PMUX_PINGRP_KB_ROW1_PR1] = "kb_row1_pr1", + [PMUX_PINGRP_KB_ROW2_PR2] = "kb_row2_pr2", + [PMUX_PINGRP_KB_ROW3_PR3] = "kb_row3_pr3", + [PMUX_PINGRP_KB_ROW4_PR4] = "kb_row4_pr4", + [PMUX_PINGRP_KB_ROW5_PR5] = "kb_row5_pr5", + [PMUX_PINGRP_KB_ROW6_PR6] = "kb_row6_pr6", + [PMUX_PINGRP_KB_ROW7_PR7] = "kb_row7_pr7", + [PMUX_PINGRP_KB_ROW8_PS0] = "kb_row8_ps0", + [PMUX_PINGRP_KB_ROW9_PS1] = "kb_row9_ps1", + [PMUX_PINGRP_KB_ROW10_PS2] = "kb_row10_ps2", + [PMUX_PINGRP_KB_ROW11_PS3] = "kb_row11_ps3", + [PMUX_PINGRP_KB_ROW12_PS4] = "kb_row12_ps4", + [PMUX_PINGRP_KB_ROW13_PS5] = "kb_row13_ps5", + [PMUX_PINGRP_KB_ROW14_PS6] = "kb_row14_ps6", + [PMUX_PINGRP_KB_ROW15_PS7] = "kb_row15_ps7", + [PMUX_PINGRP_KB_COL0_PQ0] = "kb_col0_pq0", + [PMUX_PINGRP_KB_COL1_PQ1] = "kb_col1_pq1", + [PMUX_PINGRP_KB_COL2_PQ2] = "kb_col2_pq2", + [PMUX_PINGRP_KB_COL3_PQ3] = "kb_col3_pq3", + [PMUX_PINGRP_KB_COL4_PQ4] = "kb_col4_pq4", + [PMUX_PINGRP_KB_COL5_PQ5] = "kb_col5_pq5", + [PMUX_PINGRP_KB_COL6_PQ6] = "kb_col6_pq6", + [PMUX_PINGRP_KB_COL7_PQ7] = "kb_col7_pq7", + [PMUX_PINGRP_CLK_32K_OUT_PA0] = "clk_32k_out_pa0", + [PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req", + [PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req", + [PMUX_PINGRP_PWR_INT_N] = "pwr_int_n", + [PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in", + [PMUX_PINGRP_OWR] = "owr", + [PMUX_PINGRP_DAP1_FS_PN0] = "dap1_fs_pn0", + [PMUX_PINGRP_DAP1_DIN_PN1] = "dap1_din_pn1", + [PMUX_PINGRP_DAP1_DOUT_PN2] = "dap1_dout_pn2", + [PMUX_PINGRP_DAP1_SCLK_PN3] = "dap1_sclk_pn3", + [PMUX_PINGRP_DAP_MCLK1_REQ_PEE2] = "dap_mclk1_req_pee2", + [PMUX_PINGRP_DAP_MCLK1_PW4] = "dap_mclk1_pw4", + [PMUX_PINGRP_SPDIF_IN_PK6] = "spdif_in_pk6", + [PMUX_PINGRP_SPDIF_OUT_PK5] = "spdif_out_pk5", + [PMUX_PINGRP_DAP2_FS_PA2] = "dap2_fs_pa2", + [PMUX_PINGRP_DAP2_DIN_PA4] = "dap2_din_pa4", + [PMUX_PINGRP_DAP2_DOUT_PA5] = "dap2_dout_pa5", + [PMUX_PINGRP_DAP2_SCLK_PA3] = "dap2_sclk_pa3", + [PMUX_PINGRP_DVFS_PWM_PX0] = "dvfs_pwm_px0", + [PMUX_PINGRP_GPIO_X1_AUD_PX1] = "gpio_x1_aud_px1", + [PMUX_PINGRP_GPIO_X3_AUD_PX3] = "gpio_x3_aud_px3", + [PMUX_PINGRP_DVFS_CLK_PX2] = "dvfs_clk_px2", + [PMUX_PINGRP_GPIO_X4_AUD_PX4] = "gpio_x4_aud_px4", + [PMUX_PINGRP_GPIO_X5_AUD_PX5] = "gpio_x5_aud_px5", + [PMUX_PINGRP_GPIO_X6_AUD_PX6] = "gpio_x6_aud_px6", + [PMUX_PINGRP_GPIO_X7_AUD_PX7] = "gpio_x7_aud_px7", + [PMUX_PINGRP_SDMMC3_CLK_PA6] = "sdmmc3_clk_pa6", + [PMUX_PINGRP_SDMMC3_CMD_PA7] = "sdmmc3_cmd_pa7", + [PMUX_PINGRP_SDMMC3_DAT0_PB7] = "sdmmc3_dat0_pb7", + [PMUX_PINGRP_SDMMC3_DAT1_PB6] = "sdmmc3_dat1_pb6", + [PMUX_PINGRP_SDMMC3_DAT2_PB5] = "sdmmc3_dat2_pb5", + [PMUX_PINGRP_SDMMC3_DAT3_PB4] = "sdmmc3_dat3_pb4", + [PMUX_PINGRP_PEX_L0_RST_N_PDD1] = "pex_l0_rst_n_pdd1", + [PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2] = "pex_l0_clkreq_n_pdd2", + [PMUX_PINGRP_PEX_WAKE_N_PDD3] = "pex_wake_n_pdd3", + [PMUX_PINGRP_PEX_L1_RST_N_PDD5] = "pex_l1_rst_n_pdd5", + [PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6] = "pex_l1_clkreq_n_pdd6", + [PMUX_PINGRP_HDMI_CEC_PEE3] = "hdmi_cec_pee3", + [PMUX_PINGRP_SDMMC1_WP_N_PV3] = "sdmmc1_wp_n_pv3", + [PMUX_PINGRP_SDMMC3_CD_N_PV2] = "sdmmc3_cd_n_pv2", + [PMUX_PINGRP_GPIO_W2_AUD_PW2] = "gpio_w2_aud_pw2", + [PMUX_PINGRP_GPIO_W3_AUD_PW3] = "gpio_w3_aud_pw3", + [PMUX_PINGRP_USB_VBUS_EN0_PN4] = "usb_vbus_en0_pn4", + [PMUX_PINGRP_USB_VBUS_EN1_PN5] = "usb_vbus_en1_pn5", + [PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5] = "sdmmc3_clk_lb_in_pee5", + [PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4] = "sdmmc3_clk_lb_out_pee4", + [PMUX_PINGRP_GMI_CLK_LB] = "gmi_clk_lb", + [PMUX_PINGRP_RESET_OUT_N] = "reset_out_n", + [PMUX_PINGRP_KB_ROW16_PT0] = "kb_row16_pt0", + [PMUX_PINGRP_KB_ROW17_PT1] = "kb_row17_pt1", + [PMUX_PINGRP_USB_VBUS_EN2_PFF1] = "usb_vbus_en2_pff1", + [PMUX_PINGRP_PFF2] = "pff2", + [PMUX_PINGRP_DP_HPD_PFF0] = "dp_hpd_pff0", +}; + +static const char * const tegra_pinctrl_to_drvgrp[] = { + [PMUX_DRVGRP_AO1] = "ao1", + [PMUX_DRVGRP_AO2] = "ao2", + [PMUX_DRVGRP_AT1] = "at1", + [PMUX_DRVGRP_AT2] = "at2", + [PMUX_DRVGRP_AT3] = "at3", + [PMUX_DRVGRP_AT4] = "at4", + [PMUX_DRVGRP_AT5] = "at5", + [PMUX_DRVGRP_CDEV1] = "cdev1", + [PMUX_DRVGRP_CDEV2] = "cdev2", + [PMUX_DRVGRP_DAP1] = "dap1", + [PMUX_DRVGRP_DAP2] = "dap2", + [PMUX_DRVGRP_DAP3] = "dap3", + [PMUX_DRVGRP_DAP4] = "dap4", + [PMUX_DRVGRP_DBG] = "dbg", + [PMUX_DRVGRP_SDIO3] = "sdio3", + [PMUX_DRVGRP_SPI] = "spi", + [PMUX_DRVGRP_UAA] = "uaa", + [PMUX_DRVGRP_UAB] = "uab", + [PMUX_DRVGRP_UART2] = "uart2", + [PMUX_DRVGRP_UART3] = "uart3", + [PMUX_DRVGRP_SDIO1] = "sdio1", + [PMUX_DRVGRP_DDC] = "ddc", + [PMUX_DRVGRP_GMA] = "gma", + [PMUX_DRVGRP_GME] = "gme", + [PMUX_DRVGRP_GMF] = "gmf", + [PMUX_DRVGRP_GMG] = "gmg", + [PMUX_DRVGRP_GMH] = "gmh", + [PMUX_DRVGRP_OWR] = "owr", + [PMUX_DRVGRP_UDA] = "uda", + [PMUX_DRVGRP_GPV] = "gpv", + [PMUX_DRVGRP_DEV3] = "dev3", + [PMUX_DRVGRP_CEC] = "cec", + [PMUX_DRVGRP_AT6] = "at6", + [PMUX_DRVGRP_DAP5] = "dap5", + [PMUX_DRVGRP_USB_VBUS_EN] = "usb_vbus_en", + [PMUX_DRVGRP_AO3] = "ao3", + [PMUX_DRVGRP_AO0] = "ao0", + [PMUX_DRVGRP_HV0] = "hv0", + [PMUX_DRVGRP_SDIO4] = "sdio4", + [PMUX_DRVGRP_AO4] = "ao4", +}; + +static const char * const tegra_pinctrl_to_func[] = { + [PMUX_FUNC_DEFAULT] = "default", + [PMUX_FUNC_BLINK] = "blink", + [PMUX_FUNC_CCLA] = "ccla", + [PMUX_FUNC_CEC] = "cec", + [PMUX_FUNC_CLDVFS] = "cldvfs", + [PMUX_FUNC_CLK] = "clk", + [PMUX_FUNC_CLK12] = "clk12", + [PMUX_FUNC_CPU] = "cpu", + [PMUX_FUNC_CSI] = "csi", + [PMUX_FUNC_DAP] = "dap", + [PMUX_FUNC_DAP1] = "dap1", + [PMUX_FUNC_DAP2] = "dap2", + [PMUX_FUNC_DEV3] = "dev3", + [PMUX_FUNC_DISPLAYA] = "displaya", + [PMUX_FUNC_DISPLAYA_ALT] = "displaya_alt", + [PMUX_FUNC_DISPLAYB] = "displayb", + [PMUX_FUNC_DP] = "dp", + [PMUX_FUNC_DSI_B] = "dsi_b", + [PMUX_FUNC_DTV] = "dtv", + [PMUX_FUNC_EXTPERIPH1] = "extperiph1", + [PMUX_FUNC_EXTPERIPH2] = "extperiph2", + [PMUX_FUNC_EXTPERIPH3] = "extperiph3", + [PMUX_FUNC_GMI] = "gmi", + [PMUX_FUNC_GMI_ALT] = "gmi_alt", + [PMUX_FUNC_HDA] = "hda", + [PMUX_FUNC_HSI] = "hsi", + [PMUX_FUNC_I2C1] = "i2c1", + [PMUX_FUNC_I2C2] = "i2c2", + [PMUX_FUNC_I2C3] = "i2c3", + [PMUX_FUNC_I2C4] = "i2c4", + [PMUX_FUNC_I2CPWR] = "i2cpwr", + [PMUX_FUNC_I2S0] = "i2s0", + [PMUX_FUNC_I2S1] = "i2s1", + [PMUX_FUNC_I2S2] = "i2s2", + [PMUX_FUNC_I2S3] = "i2s3", + [PMUX_FUNC_I2S4] = "i2s4", + [PMUX_FUNC_IRDA] = "irda", + [PMUX_FUNC_KBC] = "kbc", + [PMUX_FUNC_OWR] = "owr", + [PMUX_FUNC_PE] = "pe", + [PMUX_FUNC_PE0] = "pe0", + [PMUX_FUNC_PE1] = "pe1", + [PMUX_FUNC_PMI] = "pmi", + [PMUX_FUNC_PWM0] = "pwm0", + [PMUX_FUNC_PWM1] = "pwm1", + [PMUX_FUNC_PWM2] = "pwm2", + [PMUX_FUNC_PWM3] = "pwm3", + [PMUX_FUNC_PWRON] = "pwron", + [PMUX_FUNC_RESET_OUT_N] = "reset_out_n", + [PMUX_FUNC_RTCK] = "rtck", + [PMUX_FUNC_SATA] = "sata", + [PMUX_FUNC_SDMMC1] = "sdmmc1", + [PMUX_FUNC_SDMMC2] = "sdmmc2", + [PMUX_FUNC_SDMMC3] = "sdmmc3", + [PMUX_FUNC_SDMMC4] = "sdmmc4", + [PMUX_FUNC_SOC] = "soc", + [PMUX_FUNC_SPDIF] = "spdif", + [PMUX_FUNC_SPI1] = "spi1", + [PMUX_FUNC_SPI2] = "spi2", + [PMUX_FUNC_SPI3] = "spi3", + [PMUX_FUNC_SPI4] = "spi4", + [PMUX_FUNC_SPI5] = "spi5", + [PMUX_FUNC_SPI6] = "spi6", + [PMUX_FUNC_SYS] = "sys", + [PMUX_FUNC_TMDS] = "tmds", + [PMUX_FUNC_TRACE] = "trace", + [PMUX_FUNC_UARTA] = "uarta", + [PMUX_FUNC_UARTB] = "uartb", + [PMUX_FUNC_UARTC] = "uartc", + [PMUX_FUNC_UARTD] = "uartd", + [PMUX_FUNC_ULPI] = "ulpi", + [PMUX_FUNC_USB] = "usb", + [PMUX_FUNC_VGP1] = "vgp1", + [PMUX_FUNC_VGP2] = "vgp2", + [PMUX_FUNC_VGP3] = "vgp3", + [PMUX_FUNC_VGP4] = "vgp4", + [PMUX_FUNC_VGP5] = "vgp5", + [PMUX_FUNC_VGP6] = "vgp6", + [PMUX_FUNC_VI] = "vi", + [PMUX_FUNC_VI_ALT1] = "vi_alt1", + [PMUX_FUNC_VI_ALT3] = "vi_alt3", + [PMUX_FUNC_VIMCLK2] = "vimclk2", + [PMUX_FUNC_VIMCLK2_ALT] = "vimclk2_alt", + [PMUX_FUNC_RSVD1] = "rsvd1", + [PMUX_FUNC_RSVD2] = "rsvd2", + [PMUX_FUNC_RSVD3] = "rsvd3", + [PMUX_FUNC_RSVD4] = "rsvd4", +}; + #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h index e9e3801e6f4..8c8579e87e3 100644 --- a/arch/arm/include/asm/arch-tegra20/pinmux.h +++ b/arch/arm/include/asm/arch-tegra20/pinmux.h @@ -159,6 +159,47 @@ enum pmux_pingrp { PMUX_PINGRP_COUNT, }; +enum pmux_drvgrp { + PMUX_DRVGRP_AO1, + PMUX_DRVGRP_AO2, + PMUX_DRVGRP_AT1, + PMUX_DRVGRP_AT2, + PMUX_DRVGRP_CDEV1, + PMUX_DRVGRP_CDEV2, + PMUX_DRVGRP_CSUS, + PMUX_DRVGRP_DAP1, + PMUX_DRVGRP_DAP2, + PMUX_DRVGRP_DAP3, + PMUX_DRVGRP_DAP4, + PMUX_DRVGRP_DBG, + PMUX_DRVGRP_LCD1, + PMUX_DRVGRP_LCD2, + PMUX_DRVGRP_SDIO2, + PMUX_DRVGRP_SDIO3, + PMUX_DRVGRP_SPI, + PMUX_DRVGRP_UAA, + PMUX_DRVGRP_UAB, + PMUX_DRVGRP_UART2, + PMUX_DRVGRP_UART3, + PMUX_DRVGRP_VI1, + PMUX_DRVGRP_VI2, + PMUX_DRVGRP_XM2A, + PMUX_DRVGRP_XM2C, + PMUX_DRVGRP_XM2D, + PMUX_DRVGRP_XM2CLK, + PMUX_DRVGRP_SDIO1 = (0x78 / 4), + PMUX_DRVGRP_CRT = (0x84 / 4), + PMUX_DRVGRP_DDC, + PMUX_DRVGRP_GMA, + PMUX_DRVGRP_GMB, + PMUX_DRVGRP_GMC, + PMUX_DRVGRP_GMD, + PMUX_DRVGRP_GME, + PMUX_DRVGRP_OWR, + PMUX_DRVGRP_UDA, + PMUX_DRVGRP_COUNT, +}; + /* * Functions which can be assigned to each of the pin groups. The values here * bear no relation to the values programmed into pinmux registers and are @@ -232,6 +273,256 @@ enum pmux_func { PMUX_FUNC_COUNT, }; +static const char * const tegra_pinctrl_to_pingrp[] = { + /* APB_MISC_PP_TRISTATE_REG_A_0 */ + [PMUX_PINGRP_ATA] = "ata", + [PMUX_PINGRP_ATB] = "atb", + [PMUX_PINGRP_ATC] = "atc", + [PMUX_PINGRP_ATD] = "atd", + [PMUX_PINGRP_CDEV1] = "cdev1", + [PMUX_PINGRP_CDEV2] = "cdev2", + [PMUX_PINGRP_CSUS] = "csus", + [PMUX_PINGRP_DAP1] = "dap1", + + [PMUX_PINGRP_DAP2] = "dap2", + [PMUX_PINGRP_DAP3] = "dap3", + [PMUX_PINGRP_DAP4] = "dap4", + [PMUX_PINGRP_DTA] = "dta", + [PMUX_PINGRP_DTB] = "dtb", + [PMUX_PINGRP_DTC] = "dtc", + [PMUX_PINGRP_DTD] = "dtd", + [PMUX_PINGRP_DTE] = "dte", + + [PMUX_PINGRP_GPU] = "gpu", + [PMUX_PINGRP_GPV] = "gpv", + [PMUX_PINGRP_I2CP] = "i2cp", + [PMUX_PINGRP_IRTX] = "irtx", + [PMUX_PINGRP_IRRX] = "irrx", + [PMUX_PINGRP_KBCB] = "kbcb", + [PMUX_PINGRP_KBCA] = "kbca", + [PMUX_PINGRP_PMC] = "pmc", + + [PMUX_PINGRP_PTA] = "pta", + [PMUX_PINGRP_RM] = "rm", + [PMUX_PINGRP_KBCE] = "kbce", + [PMUX_PINGRP_KBCF] = "kbcf", + [PMUX_PINGRP_GMA] = "gma", + [PMUX_PINGRP_GMC] = "gmc", + [PMUX_PINGRP_SDIO1] = "sdio1", + [PMUX_PINGRP_OWC] = "owc", + + /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ + [PMUX_PINGRP_GME] = "gme", + [PMUX_PINGRP_SDC] = "sdc", + [PMUX_PINGRP_SDD] = "sdd", + [PMUX_PINGRP_RESERVED0] = "reserved0", + [PMUX_PINGRP_SLXA] = "slxa", + [PMUX_PINGRP_SLXC] = "slxc", + [PMUX_PINGRP_SLXD] = "slxd", + [PMUX_PINGRP_SLXK] = "slxk", + + [PMUX_PINGRP_SPDI] = "spdi", + [PMUX_PINGRP_SPDO] = "spdo", + [PMUX_PINGRP_SPIA] = "spia", + [PMUX_PINGRP_SPIB] = "spib", + [PMUX_PINGRP_SPIC] = "spic", + [PMUX_PINGRP_SPID] = "spid", + [PMUX_PINGRP_SPIE] = "spie", + [PMUX_PINGRP_SPIF] = "spif", + + [PMUX_PINGRP_SPIG] = "spig", + [PMUX_PINGRP_SPIH] = "spih", + [PMUX_PINGRP_UAA] = "uaa", + [PMUX_PINGRP_UAB] = "uab", + [PMUX_PINGRP_UAC] = "uac", + [PMUX_PINGRP_UAD] = "uad", + [PMUX_PINGRP_UCA] = "uca", + [PMUX_PINGRP_UCB] = "ucb", + + [PMUX_PINGRP_RESERVED1] = "reserved1", + [PMUX_PINGRP_ATE] = "ate", + [PMUX_PINGRP_KBCC] = "kbcc", + [PMUX_PINGRP_RESERVED2] = "reserved2", + [PMUX_PINGRP_RESERVED3] = "reserved3", + [PMUX_PINGRP_GMB] = "gmb", + [PMUX_PINGRP_GMD] = "gmd", + [PMUX_PINGRP_DDC] = "ddc", + + /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */ + [PMUX_PINGRP_LD0] = "ld0", + [PMUX_PINGRP_LD1] = "ld1", + [PMUX_PINGRP_LD2] = "ld2", + [PMUX_PINGRP_LD3] = "ld3", + [PMUX_PINGRP_LD4] = "ld4", + [PMUX_PINGRP_LD5] = "ld5", + [PMUX_PINGRP_LD6] = "ld6", + [PMUX_PINGRP_LD7] = "ld7", + + [PMUX_PINGRP_LD8] = "ld8", + [PMUX_PINGRP_LD9] = "ld9", + [PMUX_PINGRP_LD10] = "ld10", + [PMUX_PINGRP_LD11] = "ld11", + [PMUX_PINGRP_LD12] = "ld12", + [PMUX_PINGRP_LD13] = "ld13", + [PMUX_PINGRP_LD14] = "ld14", + [PMUX_PINGRP_LD15] = "ld15", + + [PMUX_PINGRP_LD16] = "ld16", + [PMUX_PINGRP_LD17] = "ld17", + [PMUX_PINGRP_LHP0] = "lhp0", + [PMUX_PINGRP_LHP1] = "lhp1", + [PMUX_PINGRP_LHP2] = "lhp2", + [PMUX_PINGRP_LVP0] = "lvp0", + [PMUX_PINGRP_LVP1] = "lvp1", + [PMUX_PINGRP_HDINT] = "hdint", + + [PMUX_PINGRP_LM0] = "lm0", + [PMUX_PINGRP_LM1] = "lm1", + [PMUX_PINGRP_LVS] = "lvs", + [PMUX_PINGRP_LSC0] = "lsc0", + [PMUX_PINGRP_LSC1] = "lsc1", + [PMUX_PINGRP_LSCK] = "lsck", + [PMUX_PINGRP_LDC] = "ldc", + [PMUX_PINGRP_LCSN] = "lcsn", + + /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */ + [PMUX_PINGRP_LSPI] = "lspi", + [PMUX_PINGRP_LSDA] = "lsda", + [PMUX_PINGRP_LSDI] = "lsdi", + [PMUX_PINGRP_LPW0] = "lpw0", + [PMUX_PINGRP_LPW1] = "lpw1", + [PMUX_PINGRP_LPW2] = "lpw2", + [PMUX_PINGRP_LDI] = "ldi", + [PMUX_PINGRP_LHS] = "lhs", + + [PMUX_PINGRP_LPP] = "lpp", + [PMUX_PINGRP_RESERVED4] = "reserved4", + [PMUX_PINGRP_KBCD] = "kbcd", + [PMUX_PINGRP_GPU7] = "gpu7", + [PMUX_PINGRP_DTF] = "dtf", + [PMUX_PINGRP_UDA] = "uda", + [PMUX_PINGRP_CRTP] = "crtp", + [PMUX_PINGRP_SDB] = "sdb", + + /* these pin groups only have pullup and pull down control */ + [PMUX_PINGRP_CK32] = "ck32", + [PMUX_PINGRP_DDRC] = "ddrc", + [PMUX_PINGRP_PMCA] = "pmca", + [PMUX_PINGRP_PMCB] = "pmcb", + [PMUX_PINGRP_PMCC] = "pmcc", + [PMUX_PINGRP_PMCD] = "pmcd", + [PMUX_PINGRP_PMCE] = "pmce", + [PMUX_PINGRP_XM2C] = "xm2c", + [PMUX_PINGRP_XM2D] = "xm2d", +}; + +static const char * const tegra_pinctrl_to_drvgrp[] = { + [PMUX_DRVGRP_AO1] = "drive_ao1", + [PMUX_DRVGRP_AO2] = "drive_ao2", + [PMUX_DRVGRP_AT1] = "drive_at1", + [PMUX_DRVGRP_AT2] = "drive_at2", + [PMUX_DRVGRP_CDEV1] = "drive_cdev1", + [PMUX_DRVGRP_CDEV2] = "drive_cdev2", + [PMUX_DRVGRP_CSUS] = "drive_csus", + [PMUX_DRVGRP_DAP1] = "drive_dap1", + [PMUX_DRVGRP_DAP2] = "drive_dap2", + [PMUX_DRVGRP_DAP3] = "drive_dap3", + [PMUX_DRVGRP_DAP4] = "drive_dap4", + [PMUX_DRVGRP_DBG] = "drive_dbg", + [PMUX_DRVGRP_LCD1] = "drive_lcd1", + [PMUX_DRVGRP_LCD2] = "drive_lcd2", + [PMUX_DRVGRP_SDIO2] = "drive_sdio2", + [PMUX_DRVGRP_SDIO3] = "drive_sdio3", + [PMUX_DRVGRP_SPI] = "drive_spi", + [PMUX_DRVGRP_UAA] = "drive_uaa", + [PMUX_DRVGRP_UAB] = "drive_uab", + [PMUX_DRVGRP_UART2] = "drive_uart2", + [PMUX_DRVGRP_UART3] = "drive_uart3", + [PMUX_DRVGRP_VI1] = "drive_vi1", + [PMUX_DRVGRP_VI2] = "drive_vi2", + [PMUX_DRVGRP_XM2A] = "drive_xm2a", + [PMUX_DRVGRP_XM2C] = "drive_xm2c", + [PMUX_DRVGRP_XM2D] = "drive_xm2d", + [PMUX_DRVGRP_XM2CLK] = "drive_xm2clk", + [PMUX_DRVGRP_SDIO1] = "drive_sdio1", + [PMUX_DRVGRP_CRT] = "drive_crt", + [PMUX_DRVGRP_DDC] = "drive_ddc", + [PMUX_DRVGRP_GMA] = "drive_gma", + [PMUX_DRVGRP_GMB] = "drive_gmb", + [PMUX_DRVGRP_GMC] = "drive_gmc", + [PMUX_DRVGRP_GMD] = "drive_gmd", + [PMUX_DRVGRP_GME] = "drive_gme", + [PMUX_DRVGRP_OWR] = "drive_owr", + [PMUX_DRVGRP_UDA] = "drive_uda", +}; + +static const char * const tegra_pinctrl_to_func[] = { + [PMUX_FUNC_DEFAULT] = "default", + [PMUX_FUNC_AHB_CLK] = "ahb_clk", + [PMUX_FUNC_APB_CLK] = "apb_clk", + [PMUX_FUNC_AUDIO_SYNC] = "audio_sync", + [PMUX_FUNC_CRT] = "crt", + [PMUX_FUNC_DAP1] = "dap1", + [PMUX_FUNC_DAP2] = "dap2", + [PMUX_FUNC_DAP3] = "dap3", + [PMUX_FUNC_DAP4] = "dap4", + [PMUX_FUNC_DAP5] = "dap5", + [PMUX_FUNC_DISPA] = "dispa", + [PMUX_FUNC_DISPB] = "dispb", + [PMUX_FUNC_EMC_TEST0_DLL] = "emc_test0_dll", + [PMUX_FUNC_EMC_TEST1_DLL] = "emc_test1_dll", + [PMUX_FUNC_GMI] = "gmi", + [PMUX_FUNC_GMI_INT] = "gmi_int", + [PMUX_FUNC_HDMI] = "hdmi", + [PMUX_FUNC_I2C] = "i2c", + [PMUX_FUNC_I2C2] = "i2c2", + [PMUX_FUNC_I2C3] = "i2c3", + [PMUX_FUNC_IDE] = "ide", + [PMUX_FUNC_KBC] = "kbc", + [PMUX_FUNC_MIO] = "mio", + [PMUX_FUNC_MIPI_HS] = "mipi_hs", + [PMUX_FUNC_NAND] = "nand", + [PMUX_FUNC_OSC] = "osc", + [PMUX_FUNC_OWR] = "owr", + [PMUX_FUNC_PCIE] = "pcie", + [PMUX_FUNC_PLLA_OUT] = "plla_out", + [PMUX_FUNC_PLLC_OUT1] = "pllc_out1", + [PMUX_FUNC_PLLM_OUT1] = "pllm_out1", + [PMUX_FUNC_PLLP_OUT2] = "pllp_out2", + [PMUX_FUNC_PLLP_OUT3] = "pllp_out3", + [PMUX_FUNC_PLLP_OUT4] = "pllp_out4", + [PMUX_FUNC_PWM] = "pwm", + [PMUX_FUNC_PWR_INTR] = "pwr_intr", + [PMUX_FUNC_PWR_ON] = "pwr_on", + [PMUX_FUNC_RTCK] = "rtck", + [PMUX_FUNC_SDIO1] = "sdio1", + [PMUX_FUNC_SDIO2] = "sdio2", + [PMUX_FUNC_SDIO3] = "sdio3", + [PMUX_FUNC_SDIO4] = "sdio4", + [PMUX_FUNC_SFLASH] = "sflash", + [PMUX_FUNC_SPDIF] = "spdif", + [PMUX_FUNC_SPI1] = "spi1", + [PMUX_FUNC_SPI2] = "spi2", + [PMUX_FUNC_SPI2_ALT] = "spi2_alt", + [PMUX_FUNC_SPI3] = "spi3", + [PMUX_FUNC_SPI4] = "spi4", + [PMUX_FUNC_TRACE] = "trace", + [PMUX_FUNC_TWC] = "twc", + [PMUX_FUNC_UARTA] = "uarta", + [PMUX_FUNC_UARTB] = "uartb", + [PMUX_FUNC_UARTC] = "uartc", + [PMUX_FUNC_UARTD] = "uartd", + [PMUX_FUNC_UARTE] = "uarte", + [PMUX_FUNC_ULPI] = "ulpi", + [PMUX_FUNC_VI] = "vi", + [PMUX_FUNC_VI_SENSOR_CLK] = "vi_sensor_clk", + [PMUX_FUNC_XIO] = "xio", + [PMUX_FUNC_RSVD1] = "rsvd1", + [PMUX_FUNC_RSVD2] = "rsvd2", + [PMUX_FUNC_RSVD3] = "rsvd3", + [PMUX_FUNC_RSVD4] = "rsvd4", +}; + #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #include <asm/arch-tegra/pinmux.h> diff --git a/arch/arm/include/asm/arch-tegra210/pinmux.h b/arch/arm/include/asm/arch-tegra210/pinmux.h index 9e940746286..062d7243193 100644 --- a/arch/arm/include/asm/arch-tegra210/pinmux.h +++ b/arch/arm/include/asm/arch-tegra210/pinmux.h @@ -403,6 +403,400 @@ enum pmux_func { PMUX_FUNC_COUNT, }; +static const char * const tegra_pinctrl_to_pingrp[] = { + [PMUX_PINGRP_SDMMC1_CLK_PM0] = "sdmmc1_clk_pm0", + [PMUX_PINGRP_SDMMC1_CMD_PM1] = "sdmmc1_cmd_pm1", + [PMUX_PINGRP_SDMMC1_DAT3_PM2] = "sdmmc1_dat3_pm2", + [PMUX_PINGRP_SDMMC1_DAT2_PM3] = "sdmmc1_dat2_pm3", + [PMUX_PINGRP_SDMMC1_DAT1_PM4] = "sdmmc1_dat1_pm4", + [PMUX_PINGRP_SDMMC1_DAT0_PM5] = "sdmmc1_dat0_pm5", + [PMUX_PINGRP_SDMMC3_CLK_PP0] = "sdmmc3_clk_pp0", + [PMUX_PINGRP_SDMMC3_CMD_PP1] = "sdmmc3_cmd_pp1", + [PMUX_PINGRP_SDMMC3_DAT0_PP5] = "sdmmc3_dat0_pp5", + [PMUX_PINGRP_SDMMC3_DAT1_PP4] = "sdmmc3_dat1_pp4", + [PMUX_PINGRP_SDMMC3_DAT2_PP3] = "sdmmc3_dat2_pp3", + [PMUX_PINGRP_SDMMC3_DAT3_PP2] = "sdmmc3_dat3_pp2", + [PMUX_PINGRP_PEX_L0_RST_N_PA0] = "pex_l0_rst_n_pa0", + [PMUX_PINGRP_PEX_L0_CLKREQ_N_PA1] = "pex_l0_clkreq_n_pa1", + [PMUX_PINGRP_PEX_WAKE_N_PA2] = "pex_wake_n_pa2", + [PMUX_PINGRP_PEX_L1_RST_N_PA3] = "pex_l1_rst_n_pa3", + [PMUX_PINGRP_PEX_L1_CLKREQ_N_PA4] = "pex_l1_clkreq_n_pa4", + [PMUX_PINGRP_SATA_LED_ACTIVE_PA5] = "sata_led_active_pa5", + [PMUX_PINGRP_SPI1_MOSI_PC0] = "spi1_mosi_pc0", + [PMUX_PINGRP_SPI1_MISO_PC1] = "spi1_miso_pc1", + [PMUX_PINGRP_SPI1_SCK_PC2] = "spi1_sck_pc2", + [PMUX_PINGRP_SPI1_CS0_PC3] = "spi1_cs0_pc3", + [PMUX_PINGRP_SPI1_CS1_PC4] = "spi1_cs1_pc4", + [PMUX_PINGRP_SPI2_MOSI_PB4] = "spi2_mosi_pb4", + [PMUX_PINGRP_SPI2_MISO_PB5] = "spi2_miso_pb5", + [PMUX_PINGRP_SPI2_SCK_PB6] = "spi2_sck_pb6", + [PMUX_PINGRP_SPI2_CS0_PB7] = "spi2_cs0_pb7", + [PMUX_PINGRP_SPI2_CS1_PDD0] = "spi2_cs1_pdd0", + [PMUX_PINGRP_SPI4_MOSI_PC7] = "spi4_mosi_pc7", + [PMUX_PINGRP_SPI4_MISO_PD0] = "spi4_miso_pd0", + [PMUX_PINGRP_SPI4_SCK_PC5] = "spi4_sck_pc5", + [PMUX_PINGRP_SPI4_CS0_PC6] = "spi4_cs0_pc6", + [PMUX_PINGRP_QSPI_SCK_PEE0] = "qspi_sck_pee0", + [PMUX_PINGRP_QSPI_CS_N_PEE1] = "qspi_cs_n_pee1", + [PMUX_PINGRP_QSPI_IO0_PEE2] = "qspi_io0_pee2", + [PMUX_PINGRP_QSPI_IO1_PEE3] = "qspi_io1_pee3", + [PMUX_PINGRP_QSPI_IO2_PEE4] = "qspi_io2_pee4", + [PMUX_PINGRP_QSPI_IO3_PEE5] = "qspi_io3_pee5", + [PMUX_PINGRP_DMIC1_CLK_PE0] = "dmic1_clk_pe0", + [PMUX_PINGRP_DMIC1_DAT_PE1] = "dmic1_dat_pe1", + [PMUX_PINGRP_DMIC2_CLK_PE2] = "dmic2_clk_pe2", + [PMUX_PINGRP_DMIC2_DAT_PE3] = "dmic2_dat_pe3", + [PMUX_PINGRP_DMIC3_CLK_PE4] = "dmic3_clk_pe4", + [PMUX_PINGRP_DMIC3_DAT_PE5] = "dmic3_dat_pe5", + [PMUX_PINGRP_GEN1_I2C_SCL_PJ1] = "gen1_i2c_scl_pj1", + [PMUX_PINGRP_GEN1_I2C_SDA_PJ0] = "gen1_i2c_sda_pj0", + [PMUX_PINGRP_GEN2_I2C_SCL_PJ2] = "gen2_i2c_scl_pj2", + [PMUX_PINGRP_GEN2_I2C_SDA_PJ3] = "gen2_i2c_sda_pj3", + [PMUX_PINGRP_GEN3_I2C_SCL_PF0] = "gen3_i2c_scl_pf0", + [PMUX_PINGRP_GEN3_I2C_SDA_PF1] = "gen3_i2c_sda_pf1", + [PMUX_PINGRP_CAM_I2C_SCL_PS2] = "cam_i2c_scl_ps2", + [PMUX_PINGRP_CAM_I2C_SDA_PS3] = "cam_i2c_sda_ps3", + [PMUX_PINGRP_PWR_I2C_SCL_PY3] = "pwr_i2c_scl_py3", + [PMUX_PINGRP_PWR_I2C_SDA_PY4] = "pwr_i2c_sda_py4", + [PMUX_PINGRP_UART1_TX_PU0] = "uart1_tx_pu0", + [PMUX_PINGRP_UART1_RX_PU1] = "uart1_rx_pu1", + [PMUX_PINGRP_UART1_RTS_PU2] = "uart1_rts_pu2", + [PMUX_PINGRP_UART1_CTS_PU3] = "uart1_cts_pu3", + [PMUX_PINGRP_UART2_TX_PG0] = "uart2_tx_pg0", + [PMUX_PINGRP_UART2_RX_PG1] = "uart2_rx_pg1", + [PMUX_PINGRP_UART2_RTS_PG2] = "uart2_rts_pg2", + [PMUX_PINGRP_UART2_CTS_PG3] = "uart2_cts_pg3", + [PMUX_PINGRP_UART3_TX_PD1] = "uart3_tx_pd1", + [PMUX_PINGRP_UART3_RX_PD2] = "uart3_rx_pd2", + [PMUX_PINGRP_UART3_RTS_PD3] = "uart3_rts_pd3", + [PMUX_PINGRP_UART3_CTS_PD4] = "uart3_cts_pd4", + [PMUX_PINGRP_UART4_TX_PI4] = "uart4_tx_pi4", + [PMUX_PINGRP_UART4_RX_PI5] = "uart4_rx_pi5", + [PMUX_PINGRP_UART4_RTS_PI6] = "uart4_rts_pi6", + [PMUX_PINGRP_UART4_CTS_PI7] = "uart4_cts_pi7", + [PMUX_PINGRP_DAP1_FS_PB0] = "dap1_fs_pb0", + [PMUX_PINGRP_DAP1_DIN_PB1] = "dap1_din_pb1", + [PMUX_PINGRP_DAP1_DOUT_PB2] = "dap1_dout_pb2", + [PMUX_PINGRP_DAP1_SCLK_PB3] = "dap1_sclk_pb3", + [PMUX_PINGRP_DAP2_FS_PAA0] = "dap2_fs_paa0", + [PMUX_PINGRP_DAP2_DIN_PAA2] = "dap2_din_paa2", + [PMUX_PINGRP_DAP2_DOUT_PAA3] = "dap2_dout_paa3", + [PMUX_PINGRP_DAP2_SCLK_PAA1] = "dap2_sclk_paa1", + [PMUX_PINGRP_DAP4_FS_PJ4] = "dap4_fs_pj4", + [PMUX_PINGRP_DAP4_DIN_PJ5] = "dap4_din_pj5", + [PMUX_PINGRP_DAP4_DOUT_PJ6] = "dap4_dout_pj6", + [PMUX_PINGRP_DAP4_SCLK_PJ7] = "dap4_sclk_pj7", + [PMUX_PINGRP_CAM1_MCLK_PS0] = "cam1_mclk_ps0", + [PMUX_PINGRP_CAM2_MCLK_PS1] = "cam2_mclk_ps1", + [PMUX_PINGRP_JTAG_RTCK] = "jtag_rtck", + [PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in", + [PMUX_PINGRP_CLK_32K_OUT_PY5] = "clk_32k_out_py5", + [PMUX_PINGRP_BATT_BCL] = "batt_bcl", + [PMUX_PINGRP_CLK_REQ] = "clk_req", + [PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req", + [PMUX_PINGRP_PWR_INT_N] = "pwr_int_n", + [PMUX_PINGRP_SHUTDOWN] = "shutdown", + [PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req", + [PMUX_PINGRP_AUD_MCLK_PBB0] = "aud_mclk_pbb0", + [PMUX_PINGRP_DVFS_PWM_PBB1] = "dvfs_pwm_pbb1", + [PMUX_PINGRP_DVFS_CLK_PBB2] = "dvfs_clk_pbb2", + [PMUX_PINGRP_GPIO_X1_AUD_PBB3] = "gpio_x1_aud_pbb3", + [PMUX_PINGRP_GPIO_X3_AUD_PBB4] = "gpio_x3_aud_pbb4", + [PMUX_PINGRP_PCC7] = "pcc7", + [PMUX_PINGRP_HDMI_CEC_PCC0] = "hdmi_cec_pcc0", + [PMUX_PINGRP_HDMI_INT_DP_HPD_PCC1] = "hdmi_int_dp_hpd_pcc1", + [PMUX_PINGRP_SPDIF_OUT_PCC2] = "spdif_out_pcc2", + [PMUX_PINGRP_SPDIF_IN_PCC3] = "spdif_in_pcc3", + [PMUX_PINGRP_USB_VBUS_EN0_PCC4] = "usb_vbus_en0_pcc4", + [PMUX_PINGRP_USB_VBUS_EN1_PCC5] = "usb_vbus_en1_pcc5", + [PMUX_PINGRP_DP_HPD0_PCC6] = "dp_hpd0_pcc6", + [PMUX_PINGRP_WIFI_EN_PH0] = "wifi_en_ph0", + [PMUX_PINGRP_WIFI_RST_PH1] = "wifi_rst_ph1", + [PMUX_PINGRP_WIFI_WAKE_AP_PH2] = "wifi_wake_ap_ph2", + [PMUX_PINGRP_AP_WAKE_BT_PH3] = "ap_wake_bt_ph3", + [PMUX_PINGRP_BT_RST_PH4] = "bt_rst_ph4", + [PMUX_PINGRP_BT_WAKE_AP_PH5] = "bt_wake_ap_ph5", + [PMUX_PINGRP_AP_WAKE_NFC_PH7] = "ap_wake_nfc_ph7", + [PMUX_PINGRP_NFC_EN_PI0] = "nfc_en_pi0", + [PMUX_PINGRP_NFC_INT_PI1] = "nfc_int_pi1", + [PMUX_PINGRP_GPS_EN_PI2] = "gps_en_pi2", + [PMUX_PINGRP_GPS_RST_PI3] = "gps_rst_pi3", + [PMUX_PINGRP_CAM_RST_PS4] = "cam_rst_ps4", + [PMUX_PINGRP_CAM_AF_EN_PS5] = "cam_af_en_ps5", + [PMUX_PINGRP_CAM_FLASH_EN_PS6] = "cam_flash_en_ps6", + [PMUX_PINGRP_CAM1_PWDN_PS7] = "cam1_pwdn_ps7", + [PMUX_PINGRP_CAM2_PWDN_PT0] = "cam2_pwdn_pt0", + [PMUX_PINGRP_CAM1_STROBE_PT1] = "cam1_strobe_pt1", + [PMUX_PINGRP_LCD_TE_PY2] = "lcd_te_py2", + [PMUX_PINGRP_LCD_BL_PWM_PV0] = "lcd_bl_pwm_pv0", + [PMUX_PINGRP_LCD_BL_EN_PV1] = "lcd_bl_en_pv1", + [PMUX_PINGRP_LCD_RST_PV2] = "lcd_rst_pv2", + [PMUX_PINGRP_LCD_GPIO1_PV3] = "lcd_gpio1_pv3", + [PMUX_PINGRP_LCD_GPIO2_PV4] = "lcd_gpio2_pv4", + [PMUX_PINGRP_AP_READY_PV5] = "ap_ready_pv5", + [PMUX_PINGRP_TOUCH_RST_PV6] = "touch_rst_pv6", + [PMUX_PINGRP_TOUCH_CLK_PV7] = "touch_clk_pv7", + [PMUX_PINGRP_MODEM_WAKE_AP_PX0] = "modem_wake_ap_px0", + [PMUX_PINGRP_TOUCH_INT_PX1] = "touch_int_px1", + [PMUX_PINGRP_MOTION_INT_PX2] = "motion_int_px2", + [PMUX_PINGRP_ALS_PROX_INT_PX3] = "als_prox_int_px3", + [PMUX_PINGRP_TEMP_ALERT_PX4] = "temp_alert_px4", + [PMUX_PINGRP_BUTTON_POWER_ON_PX5] = "button_power_on_px5", + [PMUX_PINGRP_BUTTON_VOL_UP_PX6] = "button_vol_up_px6", + [PMUX_PINGRP_BUTTON_VOL_DOWN_PX7] = "button_vol_down_px7", + [PMUX_PINGRP_BUTTON_SLIDE_SW_PY0] = "button_slide_sw_py0", + [PMUX_PINGRP_BUTTON_HOME_PY1] = "button_home_py1", + [PMUX_PINGRP_PA6] = "pa6", + [PMUX_PINGRP_PE6] = "pe6", + [PMUX_PINGRP_PE7] = "pe7", + [PMUX_PINGRP_PH6] = "ph6", + [PMUX_PINGRP_PK0] = "pk0", + [PMUX_PINGRP_PK1] = "pk1", + [PMUX_PINGRP_PK2] = "pk2", + [PMUX_PINGRP_PK3] = "pk3", + [PMUX_PINGRP_PK4] = "pk4", + [PMUX_PINGRP_PK5] = "pk5", + [PMUX_PINGRP_PK6] = "pk6", + [PMUX_PINGRP_PK7] = "pk7", + [PMUX_PINGRP_PL0] = "pl0", + [PMUX_PINGRP_PL1] = "pl1", + [PMUX_PINGRP_PZ0] = "pz0", + [PMUX_PINGRP_PZ1] = "pz1", + [PMUX_PINGRP_PZ2] = "pz2", + [PMUX_PINGRP_PZ3] = "pz3", + [PMUX_PINGRP_PZ4] = "pz4", + [PMUX_PINGRP_PZ5] = "pz5", +}; + +static const char * const tegra_pinctrl_to_drvgrp[] = { + [PMUX_DRVGRP_ALS_PROX_INT] = "als_prox_int", + [PMUX_DRVGRP_AP_READY] = "ap_ready", + [PMUX_DRVGRP_AP_WAKE_BT] = "ap_wake_bt", + [PMUX_DRVGRP_AP_WAKE_NFC] = "ap_wake_nfc", + [PMUX_DRVGRP_AUD_MCLK] = "aud_mclk", + [PMUX_DRVGRP_BATT_BCL] = "batt_bcl", + [PMUX_DRVGRP_BT_RST] = "bt_rst", + [PMUX_DRVGRP_BT_WAKE_AP] = "bt_wake_ap", + [PMUX_DRVGRP_BUTTON_HOME] = "button_home", + [PMUX_DRVGRP_BUTTON_POWER_ON] = "button_power_on", + [PMUX_DRVGRP_BUTTON_SLIDE_SW] = "button_slide_sw", + [PMUX_DRVGRP_BUTTON_VOL_DOWN] = "button_vol_down", + [PMUX_DRVGRP_BUTTON_VOL_UP] = "button_vol_up", + [PMUX_DRVGRP_CAM1_MCLK] = "cam1_mclk", + [PMUX_DRVGRP_CAM1_PWDN] = "cam1_pwdn", + [PMUX_DRVGRP_CAM1_STROBE] = "cam1_strobe", + [PMUX_DRVGRP_CAM2_MCLK] = "cam2_mclk", + [PMUX_DRVGRP_CAM2_PWDN] = "cam2_pwdn", + [PMUX_DRVGRP_CAM_AF_EN] = "cam_af_en", + [PMUX_DRVGRP_CAM_FLASH_EN] = "cam_flash_en", + [PMUX_DRVGRP_CAM_I2C_SCL] = "cam_i2c_scl", + [PMUX_DRVGRP_CAM_I2C_SDA] = "cam_i2c_sda", + [PMUX_DRVGRP_CAM_RST] = "cam_rst", + [PMUX_DRVGRP_CLK_32K_IN] = "clk_32k_in", + [PMUX_DRVGRP_CLK_32K_OUT] = "clk_32k_out", + [PMUX_DRVGRP_CLK_REQ] = "clk_req", + [PMUX_DRVGRP_CORE_PWR_REQ] = "core_pwr_req", + [PMUX_DRVGRP_CPU_PWR_REQ] = "cpu_pwr_req", + [PMUX_DRVGRP_DAP1_DIN] = "dap1_din", + [PMUX_DRVGRP_DAP1_DOUT] = "dap1_dout", + [PMUX_DRVGRP_DAP1_FS] = "dap1_fs", + [PMUX_DRVGRP_DAP1_SCLK] = "dap1_sclk", + [PMUX_DRVGRP_DAP2_DIN] = "dap2_din", + [PMUX_DRVGRP_DAP2_DOUT] = "dap2_dout", + [PMUX_DRVGRP_DAP2_FS] = "dap2_fs", + [PMUX_DRVGRP_DAP2_SCLK] = "dap2_sclk", + [PMUX_DRVGRP_DAP4_DIN] = "dap4_din", + [PMUX_DRVGRP_DAP4_DOUT] = "dap4_dout", + [PMUX_DRVGRP_DAP4_FS] = "dap4_fs", + [PMUX_DRVGRP_DAP4_SCLK] = "dap4_sclk", + [PMUX_DRVGRP_DMIC1_CLK] = "dmic1_clk", + [PMUX_DRVGRP_DMIC1_DAT] = "dmic1_dat", + [PMUX_DRVGRP_DMIC2_CLK] = "dmic2_clk", + [PMUX_DRVGRP_DMIC2_DAT] = "dmic2_dat", + [PMUX_DRVGRP_DMIC3_CLK] = "dmic3_clk", + [PMUX_DRVGRP_DMIC3_DAT] = "dmic3_dat", + [PMUX_DRVGRP_DP_HPD0] = "dp_hpd0", + [PMUX_DRVGRP_DVFS_CLK] = "dvfs_clk", + [PMUX_DRVGRP_DVFS_PWM] = "dvfs_pwm", + [PMUX_DRVGRP_GEN1_I2C_SCL] = "gen1_i2c_scl", + [PMUX_DRVGRP_GEN1_I2C_SDA] = "gen1_i2c_sda", + [PMUX_DRVGRP_GEN2_I2C_SCL] = "gen2_i2c_scl", + [PMUX_DRVGRP_GEN2_I2C_SDA] = "gen2_i2c_sda", + [PMUX_DRVGRP_GEN3_I2C_SCL] = "gen3_i2c_scl", + [PMUX_DRVGRP_GEN3_I2C_SDA] = "gen3_i2c_sda", + [PMUX_DRVGRP_PA6] = "pa6", + [PMUX_DRVGRP_PCC7] = "pcc7", + [PMUX_DRVGRP_PE6] = "pe6", + [PMUX_DRVGRP_PE7] = "pe7", + [PMUX_DRVGRP_PH6] = "ph6", + [PMUX_DRVGRP_PK0] = "pk0", + [PMUX_DRVGRP_PK1] = "pk1", + [PMUX_DRVGRP_PK2] = "pk2", + [PMUX_DRVGRP_PK3] = "pk3", + [PMUX_DRVGRP_PK4] = "pk4", + [PMUX_DRVGRP_PK5] = "pk5", + [PMUX_DRVGRP_PK6] = "pk6", + [PMUX_DRVGRP_PK7] = "pk7", + [PMUX_DRVGRP_PL0] = "pl0", + [PMUX_DRVGRP_PL1] = "pl1", + [PMUX_DRVGRP_PZ0] = "pz0", + [PMUX_DRVGRP_PZ1] = "pz1", + [PMUX_DRVGRP_PZ2] = "pz2", + [PMUX_DRVGRP_PZ3] = "pz3", + [PMUX_DRVGRP_PZ4] = "pz4", + [PMUX_DRVGRP_PZ5] = "pz5", + [PMUX_DRVGRP_GPIO_X1_AUD] = "gpio_x1_aud", + [PMUX_DRVGRP_GPIO_X3_AUD] = "gpio_x3_aud", + [PMUX_DRVGRP_GPS_EN] = "gps_en", + [PMUX_DRVGRP_GPS_RST] = "gps_rst", + [PMUX_DRVGRP_HDMI_CEC] = "hdmi_cec", + [PMUX_DRVGRP_HDMI_INT_DP_HPD] = "hdmi_int_dp_hpd", + [PMUX_DRVGRP_JTAG_RTCK] = "jtag_rtck", + [PMUX_DRVGRP_LCD_BL_EN] = "lcd_bl_en", + [PMUX_DRVGRP_LCD_BL_PWM] = "lcd_bl_pwm", + [PMUX_DRVGRP_LCD_GPIO1] = "lcd_gpio1", + [PMUX_DRVGRP_LCD_GPIO2] = "lcd_gpio2", + [PMUX_DRVGRP_LCD_RST] = "lcd_rst", + [PMUX_DRVGRP_LCD_TE] = "lcd_te", + [PMUX_DRVGRP_MODEM_WAKE_AP] = "modem_wake_ap", + [PMUX_DRVGRP_MOTION_INT] = "motion_int", + [PMUX_DRVGRP_NFC_EN] = "nfc_en", + [PMUX_DRVGRP_NFC_INT] = "nfc_int", + [PMUX_DRVGRP_PEX_L0_CLKREQ_N] = "pex_l0_clkreq_n", + [PMUX_DRVGRP_PEX_L0_RST_N] = "pex_l0_rst_n", + [PMUX_DRVGRP_PEX_L1_CLKREQ_N] = "pex_l1_clkreq_n", + [PMUX_DRVGRP_PEX_L1_RST_N] = "pex_l1_rst_n", + [PMUX_DRVGRP_PEX_WAKE_N] = "pex_wake_n", + [PMUX_DRVGRP_PWR_I2C_SCL] = "pwr_i2c_scl", + [PMUX_DRVGRP_PWR_I2C_SDA] = "pwr_i2c_sda", + [PMUX_DRVGRP_PWR_INT_N] = "pwr_int_n", + [PMUX_DRVGRP_QSPI_SCK] = "qspi_sck", + [PMUX_DRVGRP_SATA_LED_ACTIVE] = "sata_led_active", + [PMUX_DRVGRP_SDMMC1] = "sdmmc1", + [PMUX_DRVGRP_SDMMC2] = "sdmmc2", + [PMUX_DRVGRP_SDMMC3] = "sdmmc3", + [PMUX_DRVGRP_SDMMC4] = "sdmmc4", + [PMUX_DRVGRP_SHUTDOWN] = "shutdown", + [PMUX_DRVGRP_SPDIF_IN] = "spdif_in", + [PMUX_DRVGRP_SPDIF_OUT] = "spdif_out", + [PMUX_DRVGRP_SPI1_CS0] = "spi1_cs0", + [PMUX_DRVGRP_SPI1_CS1] = "spi1_cs1", + [PMUX_DRVGRP_SPI1_MISO] = "spi1_miso", + [PMUX_DRVGRP_SPI1_MOSI] = "spi1_mosi", + [PMUX_DRVGRP_SPI1_SCK] = "spi1_sck", + [PMUX_DRVGRP_SPI2_CS0] = "spi2_cs0", + [PMUX_DRVGRP_SPI2_CS1] = "spi2_cs1", + [PMUX_DRVGRP_SPI2_MISO] = "spi2_miso", + [PMUX_DRVGRP_SPI2_MOSI] = "spi2_mosi", + [PMUX_DRVGRP_SPI2_SCK] = "spi2_sck", + [PMUX_DRVGRP_SPI4_CS0] = "spi4_cs0", + [PMUX_DRVGRP_SPI4_MISO] = "spi4_miso", + [PMUX_DRVGRP_SPI4_MOSI] = "spi4_mosi", + [PMUX_DRVGRP_SPI4_SCK] = "spi4_sck", + [PMUX_DRVGRP_TEMP_ALERT] = "temp_alert", + [PMUX_DRVGRP_TOUCH_CLK] = "touch_clk", + [PMUX_DRVGRP_TOUCH_INT] = "touch_int", + [PMUX_DRVGRP_TOUCH_RST] = "touch_rst", + [PMUX_DRVGRP_UART1_CTS] = "uart1_cts", + [PMUX_DRVGRP_UART1_RTS] = "uart1_rts", + [PMUX_DRVGRP_UART1_RX] = "uart1_rx", + [PMUX_DRVGRP_UART1_TX] = "uart1_tx", + [PMUX_DRVGRP_UART2_CTS] = "uart2_cts", + [PMUX_DRVGRP_UART2_RTS] = "uart2_rts", + [PMUX_DRVGRP_UART2_RX] = "uart2_rx", + [PMUX_DRVGRP_UART2_TX] = "uart2_tx", + [PMUX_DRVGRP_UART3_CTS] = "uart3_cts", + [PMUX_DRVGRP_UART3_RTS] = "uart3_rts", + [PMUX_DRVGRP_UART3_RX] = "uart3_rx", + [PMUX_DRVGRP_UART3_TX] = "uart3_tx", + [PMUX_DRVGRP_UART4_CTS] = "uart4_cts", + [PMUX_DRVGRP_UART4_RTS] = "uart4_rts", + [PMUX_DRVGRP_UART4_RX] = "uart4_rx", + [PMUX_DRVGRP_UART4_TX] = "uart4_tx", + [PMUX_DRVGRP_USB_VBUS_EN0] = "usb_vbus_en0", + [PMUX_DRVGRP_USB_VBUS_EN1] = "usb_vbus_en1", + [PMUX_DRVGRP_WIFI_EN] = "wifi_en", + [PMUX_DRVGRP_WIFI_RST] = "wifi_rst", + [PMUX_DRVGRP_WIFI_WAKE_AP] = "wifi_wake_ap", +}; + +static const char * const tegra_pinctrl_to_func[] = { + [PMUX_FUNC_DEFAULT] = "default", + [PMUX_FUNC_AUD] = "aud", + [PMUX_FUNC_BCL] = "bcl", + [PMUX_FUNC_BLINK] = "blink", + [PMUX_FUNC_CCLA] = "ccla", + [PMUX_FUNC_CEC] = "cec", + [PMUX_FUNC_CLDVFS] = "cldvfs", + [PMUX_FUNC_CLK] = "clk", + [PMUX_FUNC_CORE] = "core", + [PMUX_FUNC_CPU] = "cpu", + [PMUX_FUNC_DISPLAYA] = "displaya", + [PMUX_FUNC_DISPLAYB] = "displayb", + [PMUX_FUNC_DMIC1] = "dmic1", + [PMUX_FUNC_DMIC2] = "dmic2", + [PMUX_FUNC_DMIC3] = "dmic3", + [PMUX_FUNC_DP] = "dp", + [PMUX_FUNC_DTV] = "dtv", + [PMUX_FUNC_EXTPERIPH3] = "extperiph3", + [PMUX_FUNC_I2C1] = "i2c1", + [PMUX_FUNC_I2C2] = "i2c2", + [PMUX_FUNC_I2C3] = "i2c3", + [PMUX_FUNC_I2CPMU] = "i2cpmu", + [PMUX_FUNC_I2CVI] = "i2cvi", + [PMUX_FUNC_I2S1] = "i2s1", + [PMUX_FUNC_I2S2] = "i2s2", + [PMUX_FUNC_I2S3] = "i2s3", + [PMUX_FUNC_I2S4A] = "i2s4a", + [PMUX_FUNC_I2S4B] = "i2s4b", + [PMUX_FUNC_I2S5A] = "i2s5a", + [PMUX_FUNC_I2S5B] = "i2s5b", + [PMUX_FUNC_IQC0] = "iqc0", + [PMUX_FUNC_IQC1] = "iqc1", + [PMUX_FUNC_JTAG] = "jtag", + [PMUX_FUNC_PE] = "pe", + [PMUX_FUNC_PE0] = "pe0", + [PMUX_FUNC_PE1] = "pe1", + [PMUX_FUNC_PMI] = "pmi", + [PMUX_FUNC_PWM0] = "pwm0", + [PMUX_FUNC_PWM1] = "pwm1", + [PMUX_FUNC_PWM2] = "pwm2", + [PMUX_FUNC_PWM3] = "pwm3", + [PMUX_FUNC_QSPI] = "qspi", + [PMUX_FUNC_SATA] = "sata", + [PMUX_FUNC_SDMMC1] = "sdmmc1", + [PMUX_FUNC_SDMMC3] = "sdmmc3", + [PMUX_FUNC_SHUTDOWN] = "shutdown", + [PMUX_FUNC_SOC] = "soc", + [PMUX_FUNC_SOR0] = "sor0", + [PMUX_FUNC_SOR1] = "sor1", + [PMUX_FUNC_SPDIF] = "spdif", + [PMUX_FUNC_SPI1] = "spi1", + [PMUX_FUNC_SPI2] = "spi2", + [PMUX_FUNC_SPI3] = "spi3", + [PMUX_FUNC_SPI4] = "spi4", + [PMUX_FUNC_SYS] = "sys", + [PMUX_FUNC_TOUCH] = "touch", + [PMUX_FUNC_UART] = "uart", + [PMUX_FUNC_UARTA] = "uarta", + [PMUX_FUNC_UARTB] = "uartb", + [PMUX_FUNC_UARTC] = "uartc", + [PMUX_FUNC_UARTD] = "uartd", + [PMUX_FUNC_USB] = "usb", + [PMUX_FUNC_VGP1] = "vgp1", + [PMUX_FUNC_VGP2] = "vgp2", + [PMUX_FUNC_VGP3] = "vgp3", + [PMUX_FUNC_VGP4] = "vgp4", + [PMUX_FUNC_VGP5] = "vgp5", + [PMUX_FUNC_VGP6] = "vgp6", + [PMUX_FUNC_VIMCLK] = "vimclk", + [PMUX_FUNC_VIMCLK2] = "vimclk2", + [PMUX_FUNC_RSVD0] = "rsvd0", + [PMUX_FUNC_RSVD1] = "rsvd1", + [PMUX_FUNC_RSVD2] = "rsvd2", + [PMUX_FUNC_RSVD3] = "rsvd3", +}; + #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x8d4 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING #define TEGRA_PMX_SOC_HAS_DRVGRPS diff --git a/arch/arm/include/asm/arch-tegra30/clock-tables.h b/arch/arm/include/asm/arch-tegra30/clock-tables.h index 6c899ff64c8..5ebcbc2c9ad 100644 --- a/arch/arm/include/asm/arch-tegra30/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra30/clock-tables.h @@ -23,6 +23,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DISPLAY2, /* These are the base clocks (inputs to the Tegra SOC) */ CLOCK_ID_32KHZ, @@ -30,7 +31,6 @@ enum clock_id { CLOCK_ID_CLK_M, CLOCK_ID_COUNT, /* number of PLLs */ - CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */ CLOCK_ID_NONE = -1, }; diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h index 1261943f58d..686417d5b3f 100644 --- a/arch/arm/include/asm/arch-tegra30/pinmux.h +++ b/arch/arm/include/asm/arch-tegra30/pinmux.h @@ -390,6 +390,387 @@ enum pmux_func { PMUX_FUNC_COUNT, }; +static const char * const tegra_pinctrl_to_pingrp[] = { + [PMUX_PINGRP_ULPI_DATA0_PO1] = "ulpi_data0_po1", + [PMUX_PINGRP_ULPI_DATA1_PO2] = "ulpi_data1_po2", + [PMUX_PINGRP_ULPI_DATA2_PO3] = "ulpi_data2_po3", + [PMUX_PINGRP_ULPI_DATA3_PO4] = "ulpi_data3_po4", + [PMUX_PINGRP_ULPI_DATA4_PO5] = "ulpi_data4_po5", + [PMUX_PINGRP_ULPI_DATA5_PO6] = "ulpi_data5_po6", + [PMUX_PINGRP_ULPI_DATA6_PO7] = "ulpi_data6_po7", + [PMUX_PINGRP_ULPI_DATA7_PO0] = "ulpi_data7_po0", + [PMUX_PINGRP_ULPI_CLK_PY0] = "ulpi_clk_py0", + [PMUX_PINGRP_ULPI_DIR_PY1] = "ulpi_dir_py1", + [PMUX_PINGRP_ULPI_NXT_PY2] = "ulpi_nxt_py2", + [PMUX_PINGRP_ULPI_STP_PY3] = "ulpi_stp_py3", + [PMUX_PINGRP_DAP3_FS_PP0] = "dap3_fs_pp0", + [PMUX_PINGRP_DAP3_DIN_PP1] = "dap3_din_pp1", + [PMUX_PINGRP_DAP3_DOUT_PP2] = "dap3_dout_pp2", + [PMUX_PINGRP_DAP3_SCLK_PP3] = "dap3_sclk_pp3", + [PMUX_PINGRP_PV0] = "pv0", + [PMUX_PINGRP_PV1] = "pv1", + [PMUX_PINGRP_SDMMC1_CLK_PZ0] = "sdmmc1_clk_pz0", + [PMUX_PINGRP_SDMMC1_CMD_PZ1] = "sdmmc1_cmd_pz1", + [PMUX_PINGRP_SDMMC1_DAT3_PY4] = "sdmmc1_dat3_py4", + [PMUX_PINGRP_SDMMC1_DAT2_PY5] = "sdmmc1_dat2_py5", + [PMUX_PINGRP_SDMMC1_DAT1_PY6] = "sdmmc1_dat1_py6", + [PMUX_PINGRP_SDMMC1_DAT0_PY7] = "sdmmc1_dat0_py7", + [PMUX_PINGRP_PV2] = "pv2", + [PMUX_PINGRP_PV3] = "pv3", + [PMUX_PINGRP_CLK2_OUT_PW5] = "clk2_out_pw5", + [PMUX_PINGRP_CLK2_REQ_PCC5] = "clk2_req_pcc5", + [PMUX_PINGRP_LCD_PWR1_PC1] = "lcd_pwr1_pc1", + [PMUX_PINGRP_LCD_PWR2_PC6] = "lcd_pwr2_pc6", + [PMUX_PINGRP_LCD_SDIN_PZ2] = "lcd_sdin_pz2", + [PMUX_PINGRP_LCD_SDOUT_PN5] = "lcd_sdout_pn5", + [PMUX_PINGRP_LCD_WR_N_PZ3] = "lcd_wr_n_pz3", + [PMUX_PINGRP_LCD_CS0_N_PN4] = "lcd_cs0_n_pn4", + [PMUX_PINGRP_LCD_DC0_PN6] = "lcd_dc0_pn6", + [PMUX_PINGRP_LCD_SCK_PZ4] = "lcd_sck_pz4", + [PMUX_PINGRP_LCD_PWR0_PB2] = "lcd_pwr0_pb2", + [PMUX_PINGRP_LCD_PCLK_PB3] = "lcd_pclk_pb3", + [PMUX_PINGRP_LCD_DE_PJ1] = "lcd_de_pj1", + [PMUX_PINGRP_LCD_HSYNC_PJ3] = "lcd_hsync_pj3", + [PMUX_PINGRP_LCD_VSYNC_PJ4] = "lcd_vsync_pj4", + [PMUX_PINGRP_LCD_D0_PE0] = "lcd_d0_pe0", + [PMUX_PINGRP_LCD_D1_PE1] = "lcd_d1_pe1", + [PMUX_PINGRP_LCD_D2_PE2] = "lcd_d2_pe2", + [PMUX_PINGRP_LCD_D3_PE3] = "lcd_d3_pe3", + [PMUX_PINGRP_LCD_D4_PE4] = "lcd_d4_pe4", + [PMUX_PINGRP_LCD_D5_PE5] = "lcd_d5_pe5", + [PMUX_PINGRP_LCD_D6_PE6] = "lcd_d6_pe6", + [PMUX_PINGRP_LCD_D7_PE7] = "lcd_d7_pe7", + [PMUX_PINGRP_LCD_D8_PF0] = "lcd_d8_pf0", + [PMUX_PINGRP_LCD_D9_PF1] = "lcd_d9_pf1", + [PMUX_PINGRP_LCD_D10_PF2] = "lcd_d10_pf2", + [PMUX_PINGRP_LCD_D11_PF3] = "lcd_d11_pf3", + [PMUX_PINGRP_LCD_D12_PF4] = "lcd_d12_pf4", + [PMUX_PINGRP_LCD_D13_PF5] = "lcd_d13_pf5", + [PMUX_PINGRP_LCD_D14_PF6] = "lcd_d14_pf6", + [PMUX_PINGRP_LCD_D15_PF7] = "lcd_d15_pf7", + [PMUX_PINGRP_LCD_D16_PM0] = "lcd_d16_pm0", + [PMUX_PINGRP_LCD_D17_PM1] = "lcd_d17_pm1", + [PMUX_PINGRP_LCD_D18_PM2] = "lcd_d18_pm2", + [PMUX_PINGRP_LCD_D19_PM3] = "lcd_d19_pm3", + [PMUX_PINGRP_LCD_D20_PM4] = "lcd_d20_pm4", + [PMUX_PINGRP_LCD_D21_PM5] = "lcd_d21_pm5", + [PMUX_PINGRP_LCD_D22_PM6] = "lcd_d22_pm6", + [PMUX_PINGRP_LCD_D23_PM7] = "lcd_d23_pm7", + [PMUX_PINGRP_LCD_CS1_N_PW0] = "lcd_cs1_n_pw0", + [PMUX_PINGRP_LCD_M1_PW1] = "lcd_m1_pw1", + [PMUX_PINGRP_LCD_DC1_PD2] = "lcd_dc1_pd2", + [PMUX_PINGRP_HDMI_INT_PN7] = "hdmi_int_pn7", + [PMUX_PINGRP_DDC_SCL_PV4] = "ddc_scl_pv4", + [PMUX_PINGRP_DDC_SDA_PV5] = "ddc_sda_pv5", + [PMUX_PINGRP_CRT_HSYNC_PV6] = "crt_hsync_pv6", + [PMUX_PINGRP_CRT_VSYNC_PV7] = "crt_vsync_pv7", + [PMUX_PINGRP_VI_D0_PT4] = "vi_d0_pt4", + [PMUX_PINGRP_VI_D1_PD5] = "vi_d1_pd5", + [PMUX_PINGRP_VI_D2_PL0] = "vi_d2_pl0", + [PMUX_PINGRP_VI_D3_PL1] = "vi_d3_pl1", + [PMUX_PINGRP_VI_D4_PL2] = "vi_d4_pl2", + [PMUX_PINGRP_VI_D5_PL3] = "vi_d5_pl3", + [PMUX_PINGRP_VI_D6_PL4] = "vi_d6_pl4", + [PMUX_PINGRP_VI_D7_PL5] = "vi_d7_pl5", + [PMUX_PINGRP_VI_D8_PL6] = "vi_d8_pl6", + [PMUX_PINGRP_VI_D9_PL7] = "vi_d9_pl7", + [PMUX_PINGRP_VI_D10_PT2] = "vi_d10_pt2", + [PMUX_PINGRP_VI_D11_PT3] = "vi_d11_pt3", + [PMUX_PINGRP_VI_PCLK_PT0] = "vi_pclk_pt0", + [PMUX_PINGRP_VI_MCLK_PT1] = "vi_mclk_pt1", + [PMUX_PINGRP_VI_VSYNC_PD6] = "vi_vsync_pd6", + [PMUX_PINGRP_VI_HSYNC_PD7] = "vi_hsync_pd7", + [PMUX_PINGRP_UART2_RXD_PC3] = "uart2_rxd_pc3", + [PMUX_PINGRP_UART2_TXD_PC2] = "uart2_txd_pc2", + [PMUX_PINGRP_UART2_RTS_N_PJ6] = "uart2_rts_n_pj6", + [PMUX_PINGRP_UART2_CTS_N_PJ5] = "uart2_cts_n_pj5", + [PMUX_PINGRP_UART3_TXD_PW6] = "uart3_txd_pw6", + [PMUX_PINGRP_UART3_RXD_PW7] = "uart3_rxd_pw7", + [PMUX_PINGRP_UART3_CTS_N_PA1] = "uart3_cts_n_pa1", + [PMUX_PINGRP_UART3_RTS_N_PC0] = "uart3_rts_n_pc0", + [PMUX_PINGRP_PU0] = "pu0", + [PMUX_PINGRP_PU1] = "pu1", + [PMUX_PINGRP_PU2] = "pu2", + [PMUX_PINGRP_PU3] = "pu3", + [PMUX_PINGRP_PU4] = "pu4", + [PMUX_PINGRP_PU5] = "pu5", + [PMUX_PINGRP_PU6] = "pu6", + [PMUX_PINGRP_GEN1_I2C_SDA_PC5] = "gen1_i2c_sda_pc5", + [PMUX_PINGRP_GEN1_I2C_SCL_PC4] = "gen1_i2c_scl_pc4", + [PMUX_PINGRP_DAP4_FS_PP4] = "dap4_fs_pp4", + [PMUX_PINGRP_DAP4_DIN_PP5] = "dap4_din_pp5", + [PMUX_PINGRP_DAP4_DOUT_PP6] = "dap4_dout_pp6", + [PMUX_PINGRP_DAP4_SCLK_PP7] = "dap4_sclk_pp7", + [PMUX_PINGRP_CLK3_OUT_PEE0] = "clk3_out_pee0", + [PMUX_PINGRP_CLK3_REQ_PEE1] = "clk3_req_pee1", + [PMUX_PINGRP_GMI_WP_N_PC7] = "gmi_wp_n_pc7", + [PMUX_PINGRP_GMI_IORDY_PI5] = "gmi_iordy_pi5", + [PMUX_PINGRP_GMI_WAIT_PI7] = "gmi_wait_pi7", + [PMUX_PINGRP_GMI_ADV_N_PK0] = "gmi_adv_n_pk0", + [PMUX_PINGRP_GMI_CLK_PK1] = "gmi_clk_pk1", + [PMUX_PINGRP_GMI_CS0_N_PJ0] = "gmi_cs0_n_pj0", + [PMUX_PINGRP_GMI_CS1_N_PJ2] = "gmi_cs1_n_pj2", + [PMUX_PINGRP_GMI_CS2_N_PK3] = "gmi_cs2_n_pk3", + [PMUX_PINGRP_GMI_CS3_N_PK4] = "gmi_cs3_n_pk4", + [PMUX_PINGRP_GMI_CS4_N_PK2] = "gmi_cs4_n_pk2", + [PMUX_PINGRP_GMI_CS6_N_PI3] = "gmi_cs6_n_pi3", + [PMUX_PINGRP_GMI_CS7_N_PI6] = "gmi_cs7_n_pi6", + [PMUX_PINGRP_GMI_AD0_PG0] = "gmi_ad0_pg0", + [PMUX_PINGRP_GMI_AD1_PG1] = "gmi_ad1_pg1", + [PMUX_PINGRP_GMI_AD2_PG2] = "gmi_ad2_pg2", + [PMUX_PINGRP_GMI_AD3_PG3] = "gmi_ad3_pg3", + [PMUX_PINGRP_GMI_AD4_PG4] = "gmi_ad4_pg4", + [PMUX_PINGRP_GMI_AD5_PG5] = "gmi_ad5_pg5", + [PMUX_PINGRP_GMI_AD6_PG6] = "gmi_ad6_pg6", + [PMUX_PINGRP_GMI_AD7_PG7] = "gmi_ad7_pg7", + [PMUX_PINGRP_GMI_AD8_PH0] = "gmi_ad8_ph0", + [PMUX_PINGRP_GMI_AD9_PH1] = "gmi_ad9_ph1", + [PMUX_PINGRP_GMI_AD10_PH2] = "gmi_ad10_ph2", + [PMUX_PINGRP_GMI_AD11_PH3] = "gmi_ad11_ph3", + [PMUX_PINGRP_GMI_AD12_PH4] = "gmi_ad12_ph4", + [PMUX_PINGRP_GMI_AD13_PH5] = "gmi_ad13_ph5", + [PMUX_PINGRP_GMI_AD14_PH6] = "gmi_ad14_ph6", + [PMUX_PINGRP_GMI_AD15_PH7] = "gmi_ad15_ph7", + [PMUX_PINGRP_GMI_A16_PJ7] = "gmi_a16_pj7", + [PMUX_PINGRP_GMI_A17_PB0] = "gmi_a17_pb0", + [PMUX_PINGRP_GMI_A18_PB1] = "gmi_a18_pb1", + [PMUX_PINGRP_GMI_A19_PK7] = "gmi_a19_pk7", + [PMUX_PINGRP_GMI_WR_N_PI0] = "gmi_wr_n_pi0", + [PMUX_PINGRP_GMI_OE_N_PI1] = "gmi_oe_n_pi1", + [PMUX_PINGRP_GMI_DQS_PI2] = "gmi_dqs_pi2", + [PMUX_PINGRP_GMI_RST_N_PI4] = "gmi_rst_n_pi4", + [PMUX_PINGRP_GEN2_I2C_SCL_PT5] = "gen2_i2c_scl_pt5", + [PMUX_PINGRP_GEN2_I2C_SDA_PT6] = "gen2_i2c_sda_pt6", + [PMUX_PINGRP_SDMMC4_CLK_PCC4] = "sdmmc4_clk_pcc4", + [PMUX_PINGRP_SDMMC4_CMD_PT7] = "sdmmc4_cmd_pt7", + [PMUX_PINGRP_SDMMC4_DAT0_PAA0] = "sdmmc4_dat0_paa0", + [PMUX_PINGRP_SDMMC4_DAT1_PAA1] = "sdmmc4_dat1_paa1", + [PMUX_PINGRP_SDMMC4_DAT2_PAA2] = "sdmmc4_dat2_paa2", + [PMUX_PINGRP_SDMMC4_DAT3_PAA3] = "sdmmc4_dat3_paa3", + [PMUX_PINGRP_SDMMC4_DAT4_PAA4] = "sdmmc4_dat4_paa4", + [PMUX_PINGRP_SDMMC4_DAT5_PAA5] = "sdmmc4_dat5_paa5", + [PMUX_PINGRP_SDMMC4_DAT6_PAA6] = "sdmmc4_dat6_paa6", + [PMUX_PINGRP_SDMMC4_DAT7_PAA7] = "sdmmc4_dat7_paa7", + [PMUX_PINGRP_SDMMC4_RST_N_PCC3] = "sdmmc4_rst_n_pcc3", + [PMUX_PINGRP_CAM_MCLK_PCC0] = "cam_mclk_pcc0", + [PMUX_PINGRP_PCC1] = "pcc1", + [PMUX_PINGRP_PBB0] = "pbb0", + [PMUX_PINGRP_CAM_I2C_SCL_PBB1] = "cam_i2c_scl_pbb1", + [PMUX_PINGRP_CAM_I2C_SDA_PBB2] = "cam_i2c_sda_pbb2", + [PMUX_PINGRP_PBB3] = "pbb3", + [PMUX_PINGRP_PBB4] = "pbb4", + [PMUX_PINGRP_PBB5] = "pbb5", + [PMUX_PINGRP_PBB6] = "pbb6", + [PMUX_PINGRP_PBB7] = "pbb7", + [PMUX_PINGRP_PCC2] = "pcc2", + [PMUX_PINGRP_JTAG_RTCK_PU7] = "jtag_rtck_pu7", + [PMUX_PINGRP_PWR_I2C_SCL_PZ6] = "pwr_i2c_scl_pz6", + [PMUX_PINGRP_PWR_I2C_SDA_PZ7] = "pwr_i2c_sda_pz7", + [PMUX_PINGRP_KB_ROW0_PR0] = "kb_row0_pr0", + [PMUX_PINGRP_KB_ROW1_PR1] = "kb_row1_pr1", + [PMUX_PINGRP_KB_ROW2_PR2] = "kb_row2_pr2", + [PMUX_PINGRP_KB_ROW3_PR3] = "kb_row3_pr3", + [PMUX_PINGRP_KB_ROW4_PR4] = "kb_row4_pr4", + [PMUX_PINGRP_KB_ROW5_PR5] = "kb_row5_pr5", + [PMUX_PINGRP_KB_ROW6_PR6] = "kb_row6_pr6", + [PMUX_PINGRP_KB_ROW7_PR7] = "kb_row7_pr7", + [PMUX_PINGRP_KB_ROW8_PS0] = "kb_row8_ps0", + [PMUX_PINGRP_KB_ROW9_PS1] = "kb_row9_ps1", + [PMUX_PINGRP_KB_ROW10_PS2] = "kb_row10_ps2", + [PMUX_PINGRP_KB_ROW11_PS3] = "kb_row11_ps3", + [PMUX_PINGRP_KB_ROW12_PS4] = "kb_row12_ps4", + [PMUX_PINGRP_KB_ROW13_PS5] = "kb_row13_ps5", + [PMUX_PINGRP_KB_ROW14_PS6] = "kb_row14_ps6", + [PMUX_PINGRP_KB_ROW15_PS7] = "kb_row15_ps7", + [PMUX_PINGRP_KB_COL0_PQ0] = "kb_col0_pq0", + [PMUX_PINGRP_KB_COL1_PQ1] = "kb_col1_pq1", + [PMUX_PINGRP_KB_COL2_PQ2] = "kb_col2_pq2", + [PMUX_PINGRP_KB_COL3_PQ3] = "kb_col3_pq3", + [PMUX_PINGRP_KB_COL4_PQ4] = "kb_col4_pq4", + [PMUX_PINGRP_KB_COL5_PQ5] = "kb_col5_pq5", + [PMUX_PINGRP_KB_COL6_PQ6] = "kb_col6_pq6", + [PMUX_PINGRP_KB_COL7_PQ7] = "kb_col7_pq7", + [PMUX_PINGRP_CLK_32K_OUT_PA0] = "clk_32k_out_pa0", + [PMUX_PINGRP_SYS_CLK_REQ_PZ5] = "sys_clk_req_pz5", + [PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req", + [PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req", + [PMUX_PINGRP_PWR_INT_N] = "pwr_int_n", + [PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in", + [PMUX_PINGRP_OWR] = "owr", + [PMUX_PINGRP_DAP1_FS_PN0] = "dap1_fs_pn0", + [PMUX_PINGRP_DAP1_DIN_PN1] = "dap1_din_pn1", + [PMUX_PINGRP_DAP1_DOUT_PN2] = "dap1_dout_pn2", + [PMUX_PINGRP_DAP1_SCLK_PN3] = "dap1_sclk_pn3", + [PMUX_PINGRP_CLK1_REQ_PEE2] = "clk1_req_pee2", + [PMUX_PINGRP_CLK1_OUT_PW4] = "clk1_out_pw4", + [PMUX_PINGRP_SPDIF_IN_PK6] = "spdif_in_pk6", + [PMUX_PINGRP_SPDIF_OUT_PK5] = "spdif_out_pk5", + [PMUX_PINGRP_DAP2_FS_PA2] = "dap2_fs_pa2", + [PMUX_PINGRP_DAP2_DIN_PA4] = "dap2_din_pa4", + [PMUX_PINGRP_DAP2_DOUT_PA5] = "dap2_dout_pa5", + [PMUX_PINGRP_DAP2_SCLK_PA3] = "dap2_sclk_pa3", + [PMUX_PINGRP_SPI2_MOSI_PX0] = "spi2_mosi_px0", + [PMUX_PINGRP_SPI2_MISO_PX1] = "spi2_miso_px1", + [PMUX_PINGRP_SPI2_CS0_N_PX3] = "spi2_cs0_n_px3", + [PMUX_PINGRP_SPI2_SCK_PX2] = "spi2_sck_px2", + [PMUX_PINGRP_SPI1_MOSI_PX4] = "spi1_mosi_px4", + [PMUX_PINGRP_SPI1_SCK_PX5] = "spi1_sck_px5", + [PMUX_PINGRP_SPI1_CS0_N_PX6] = "spi1_cs0_n_px6", + [PMUX_PINGRP_SPI1_MISO_PX7] = "spi1_miso_px7", + [PMUX_PINGRP_SPI2_CS1_N_PW2] = "spi2_cs1_n_pw2", + [PMUX_PINGRP_SPI2_CS2_N_PW3] = "spi2_cs2_n_pw3", + [PMUX_PINGRP_SDMMC3_CLK_PA6] = "sdmmc3_clk_pa6", + [PMUX_PINGRP_SDMMC3_CMD_PA7] = "sdmmc3_cmd_pa7", + [PMUX_PINGRP_SDMMC3_DAT0_PB7] = "sdmmc3_dat0_pb7", + [PMUX_PINGRP_SDMMC3_DAT1_PB6] = "sdmmc3_dat1_pb6", + [PMUX_PINGRP_SDMMC3_DAT2_PB5] = "sdmmc3_dat2_pb5", + [PMUX_PINGRP_SDMMC3_DAT3_PB4] = "sdmmc3_dat3_pb4", + [PMUX_PINGRP_SDMMC3_DAT4_PD1] = "sdmmc3_dat4_pd1", + [PMUX_PINGRP_SDMMC3_DAT5_PD0] = "sdmmc3_dat5_pd0", + [PMUX_PINGRP_SDMMC3_DAT6_PD3] = "sdmmc3_dat6_pd3", + [PMUX_PINGRP_SDMMC3_DAT7_PD4] = "sdmmc3_dat7_pd4", + [PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0] = "pex_l0_prsnt_n_pdd0", + [PMUX_PINGRP_PEX_L0_RST_N_PDD1] = "pex_l0_rst_n_pdd1", + [PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2] = "pex_l0_clkreq_n_pdd2", + [PMUX_PINGRP_PEX_WAKE_N_PDD3] = "pex_wake_n_pdd3", + [PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4] = "pex_l1_prsnt_n_pdd4", + [PMUX_PINGRP_PEX_L1_RST_N_PDD5] = "pex_l1_rst_n_pdd5", + [PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6] = "pex_l1_clkreq_n_pdd6", + [PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7] = "pex_l2_prsnt_n_pdd7", + [PMUX_PINGRP_PEX_L2_RST_N_PCC6] = "pex_l2_rst_n_pcc6", + [PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7] = "pex_l2_clkreq_n_pcc7", + [PMUX_PINGRP_HDMI_CEC_PEE3] = "hdmi_cec_pee3", +}; + +static const char * const tegra_pinctrl_to_drvgrp[] = { + [PMUX_DRVGRP_AO1] = "drive_ao1", + [PMUX_DRVGRP_AO2] = "drive_ao2", + [PMUX_DRVGRP_AT1] = "drive_at1", + [PMUX_DRVGRP_AT2] = "drive_at2", + [PMUX_DRVGRP_AT3] = "drive_at3", + [PMUX_DRVGRP_AT4] = "drive_at4", + [PMUX_DRVGRP_AT5] = "drive_at5", + [PMUX_DRVGRP_CDEV1] = "drive_cdev1", + [PMUX_DRVGRP_CDEV2] = "drive_cdev2", + [PMUX_DRVGRP_CSUS] = "drive_csus", + [PMUX_DRVGRP_DAP1] = "drive_dap1", + [PMUX_DRVGRP_DAP2] = "drive_dap2", + [PMUX_DRVGRP_DAP3] = "drive_dap3", + [PMUX_DRVGRP_DAP4] = "drive_dap4", + [PMUX_DRVGRP_DBG] = "drive_dbg", + [PMUX_DRVGRP_LCD1] = "drive_lcd1", + [PMUX_DRVGRP_LCD2] = "drive_lcd2", + [PMUX_DRVGRP_SDIO2] = "drive_sdio2", + [PMUX_DRVGRP_SDIO3] = "drive_sdio3", + [PMUX_DRVGRP_SPI] = "drive_spi", + [PMUX_DRVGRP_UAA] = "drive_uaa", + [PMUX_DRVGRP_UAB] = "drive_uab", + [PMUX_DRVGRP_UART2] = "drive_uart2", + [PMUX_DRVGRP_UART3] = "drive_uart3", + [PMUX_DRVGRP_VI1] = "drive_vi1", + [PMUX_DRVGRP_SDIO1] = "drive_sdio1", + [PMUX_DRVGRP_CRT] = "drive_crt", + [PMUX_DRVGRP_DDC] = "drive_ddc", + [PMUX_DRVGRP_GMA] = "drive_gma", + [PMUX_DRVGRP_GMB] = "drive_gmb", + [PMUX_DRVGRP_GMC] = "drive_gmc", + [PMUX_DRVGRP_GMD] = "drive_gmd", + [PMUX_DRVGRP_GME] = "drive_gme", + [PMUX_DRVGRP_GMF] = "drive_gmf", + [PMUX_DRVGRP_GMG] = "drive_gmg", + [PMUX_DRVGRP_GMH] = "drive_gmh", + [PMUX_DRVGRP_OWR] = "drive_owr", + [PMUX_DRVGRP_UDA] = "drive_uda", + [PMUX_DRVGRP_GPV] = "drive_gpv", + [PMUX_DRVGRP_DEV3] = "drive_dev3", + [PMUX_DRVGRP_CEC] = "drive_cec", +}; + +static const char * const tegra_pinctrl_to_func[] = { + [PMUX_FUNC_DEFAULT] = "default", + [PMUX_FUNC_BLINK] = "blink", + [PMUX_FUNC_CEC] = "cec", + [PMUX_FUNC_CLK_12M_OUT] = "clk_12m_out", + [PMUX_FUNC_CLK_32K_IN] = "clk_32k_in", + [PMUX_FUNC_CORE_PWR_REQ] = "core_pwr_req", + [PMUX_FUNC_CPU_PWR_REQ] = "cpu_pwr_req", + [PMUX_FUNC_CRT] = "crt", + [PMUX_FUNC_DAP] = "dap", + [PMUX_FUNC_DDR] = "ddr", + [PMUX_FUNC_DEV3] = "dev3", + [PMUX_FUNC_DISPLAYA] = "displaya", + [PMUX_FUNC_DISPLAYB] = "displayb", + [PMUX_FUNC_DTV] = "dtv", + [PMUX_FUNC_EXTPERIPH1] = "extperiph1", + [PMUX_FUNC_EXTPERIPH2] = "extperiph2", + [PMUX_FUNC_EXTPERIPH3] = "extperiph3", + [PMUX_FUNC_GMI] = "gmi", + [PMUX_FUNC_GMI_ALT] = "gmi_alt", + [PMUX_FUNC_HDA] = "hda", + [PMUX_FUNC_HDCP] = "hdcp", + [PMUX_FUNC_HDMI] = "hdmi", + [PMUX_FUNC_HSI] = "hsi", + [PMUX_FUNC_I2C1] = "i2c1", + [PMUX_FUNC_I2C2] = "i2c2", + [PMUX_FUNC_I2C3] = "i2c3", + [PMUX_FUNC_I2C4] = "i2c4", + [PMUX_FUNC_I2CPWR] = "i2cpwr", + [PMUX_FUNC_I2S0] = "i2s0", + [PMUX_FUNC_I2S1] = "i2s1", + [PMUX_FUNC_I2S2] = "i2s2", + [PMUX_FUNC_I2S3] = "i2s3", + [PMUX_FUNC_I2S4] = "i2s4", + [PMUX_FUNC_INVALID] = "invalid", + [PMUX_FUNC_KBC] = "kbc", + [PMUX_FUNC_MIO] = "mio", + [PMUX_FUNC_NAND] = "nand", + [PMUX_FUNC_NAND_ALT] = "nand_alt", + [PMUX_FUNC_OWR] = "owr", + [PMUX_FUNC_PCIE] = "pcie", + [PMUX_FUNC_PWM0] = "pwm0", + [PMUX_FUNC_PWM1] = "pwm1", + [PMUX_FUNC_PWM2] = "pwm2", + [PMUX_FUNC_PWM3] = "pwm3", + [PMUX_FUNC_PWR_INT_N] = "pwr_int_n", + [PMUX_FUNC_RTCK] = "rtck", + [PMUX_FUNC_SATA] = "sata", + [PMUX_FUNC_SDMMC1] = "sdmmc1", + [PMUX_FUNC_SDMMC2] = "sdmmc2", + [PMUX_FUNC_SDMMC3] = "sdmmc3", + [PMUX_FUNC_SDMMC4] = "sdmmc4", + [PMUX_FUNC_SPDIF] = "spdif", + [PMUX_FUNC_SPI1] = "spi1", + [PMUX_FUNC_SPI2] = "spi2", + [PMUX_FUNC_SPI2_ALT] = "spi2_alt", + [PMUX_FUNC_SPI3] = "spi3", + [PMUX_FUNC_SPI4] = "spi4", + [PMUX_FUNC_SPI5] = "spi5", + [PMUX_FUNC_SPI6] = "spi6", + [PMUX_FUNC_SYSCLK] = "sysclk", + [PMUX_FUNC_TEST] = "test", + [PMUX_FUNC_TRACE] = "trace", + [PMUX_FUNC_UARTA] = "uarta", + [PMUX_FUNC_UARTB] = "uartb", + [PMUX_FUNC_UARTC] = "uartc", + [PMUX_FUNC_UARTD] = "uartd", + [PMUX_FUNC_UARTE] = "uarte", + [PMUX_FUNC_ULPI] = "ulpi", + [PMUX_FUNC_VGP1] = "vgp1", + [PMUX_FUNC_VGP2] = "vgp2", + [PMUX_FUNC_VGP3] = "vgp3", + [PMUX_FUNC_VGP4] = "vgp4", + [PMUX_FUNC_VGP5] = "vgp5", + [PMUX_FUNC_VGP6] = "vgp6", + [PMUX_FUNC_VI] = "vi", + [PMUX_FUNC_VI_ALT1] = "vi_alt1", + [PMUX_FUNC_VI_ALT2] = "vi_alt2", + [PMUX_FUNC_VI_ALT3] = "vi_alt3", + [PMUX_FUNC_RSVD1] = "rsvd1", + [PMUX_FUNC_RSVD2] = "rsvd2", + [PMUX_FUNC_RSVD3] = "rsvd3", + [PMUX_FUNC_RSVD4] = "rsvd4", +}; + #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #define TEGRA_PMX_SOC_HAS_DRVGRPS #define TEGRA_PMX_GRPS_HAVE_LPMD diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 8d42ef4823e..4fda483b8d8 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -14,7 +14,6 @@ * assembler source. */ -#include <config.h> #include <asm/unified.h> /* diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 75bd9d56f89..2bb978d6683 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -11,7 +11,6 @@ #include <config.h> -#include <asm/types.h> #include <linux/types.h> /* Architecture-specific global data */ diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h index c7b00be8e0b..abfa46470b2 100644 --- a/arch/arm/include/asm/secure.h +++ b/arch/arm/include/asm/secure.h @@ -1,7 +1,6 @@ #ifndef __ASM_SECURE_H #define __ASM_SECURE_H -#include <config.h> #include <asm/global_data.h> #define __secure __section("._secure.text") diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h index ead3f2c3564..c9ecdde0d3d 100644 --- a/arch/arm/include/asm/string.h +++ b/arch/arm/include/asm/string.h @@ -1,8 +1,6 @@ #ifndef __ASM_ARM_STRING_H #define __ASM_ARM_STRING_H -#include <config.h> - /* * We don't do inline string functions, since the * optimised inline asm versions are not small. diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 47393babbc6..7a6151a9722 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -372,6 +372,22 @@ static struct mm_region t6020_mem_map[] = { PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { /* I/O */ + .virt = 0x400000000, + .phys = 0x400000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x480000000, + .phys = 0x480000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ .virt = 0x580000000, .phys = 0x580000000, .size = SZ_512M, @@ -473,6 +489,22 @@ static struct mm_region t6022_mem_map[] = { PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { /* I/O */ + .virt = 0x400000000, + .phys = 0x400000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x480000000, + .phys = 0x480000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ .virt = 0x580000000, .phys = 0x580000000, .size = SZ_512M, @@ -553,6 +585,22 @@ static struct mm_region t6022_mem_map[] = { PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { /* I/O */ + .virt = 0x2400000000, + .phys = 0x2400000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2480000000, + .phys = 0x2480000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ .virt = 0x2580000000, .phys = 0x2580000000, .size = SZ_512M, diff --git a/arch/arm/mach-davinci/include/mach/pinmux_defs.h b/arch/arm/mach-davinci/include/mach/pinmux_defs.h index 4901ba49c9b..12093531080 100644 --- a/arch/arm/mach-davinci/include/mach/pinmux_defs.h +++ b/arch/arm/mach-davinci/include/mach/pinmux_defs.h @@ -9,7 +9,6 @@ #define __ASM_ARCH_PINMUX_DEFS_H #include <asm/arch/davinci_misc.h> -#include <config.h> /* SPI0 pin muxer settings */ extern const struct pinmux_config spi0_pins_base[3]; diff --git a/arch/arm/mach-exynos/exynos4_setup.h b/arch/arm/mach-exynos/exynos4_setup.h index fbb45eb897e..23c9011fbc6 100644 --- a/arch/arm/mach-exynos/exynos4_setup.h +++ b/arch/arm/mach-exynos/exynos4_setup.h @@ -8,7 +8,6 @@ #ifndef _ORIGEN_SETUP_H #define _ORIGEN_SETUP_H -#include <config.h> #include <asm/arch/cpu.h> /* Bus Configuration Register Address */ diff --git a/arch/arm/mach-exynos/exynos5_setup.h b/arch/arm/mach-exynos/exynos5_setup.h index af7a5afb03c..e9874a8c1b2 100644 --- a/arch/arm/mach-exynos/exynos5_setup.h +++ b/arch/arm/mach-exynos/exynos5_setup.h @@ -8,7 +8,6 @@ #ifndef _SMDK5250_SETUP_H #define _SMDK5250_SETUP_H -#include <config.h> #include <asm/arch/dmc.h> #define NOT_AVAILABLE 0 diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 5cf97a5ea95..47219957b58 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -56,6 +56,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { PLL_1443X_RATE(1000000000U, 250, 3, 1, 0), PLL_1443X_RATE(933000000U, 311, 4, 1, 0), + PLL_1443X_RATE(900000000U, 300, 8, 0, 0), PLL_1443X_RATE(800000000U, 300, 9, 0, 0), PLL_1443X_RATE(750000000U, 250, 8, 0, 0), PLL_1443X_RATE(650000000U, 325, 3, 2, 0), diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c index 1d4ef35e7b4..6c96e881146 100644 --- a/arch/arm/mach-k3/am625_init.c +++ b/arch/arm/mach-k3/am625_init.c @@ -222,11 +222,8 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) switch (bootmode) { case BOOT_DEVICE_EMMC: - if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) { - if (spl_mmc_emmc_boot_partition(mmc)) - return MMCSD_MODE_EMMCBOOT; - return MMCSD_MODE_FS; - } + if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) + return MMCSD_MODE_EMMCBOOT; if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4)) return MMCSD_MODE_FS; return MMCSD_MODE_EMMCBOOT; diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index fd400e7e3dd..d5db805c62b 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -6,6 +6,7 @@ * Lokesh Vutla <lokeshvutla@ti.com> */ +#include <config.h> #include <cpu_func.h> #include <image.h> #include <init.h> diff --git a/arch/arm/mach-k3/include/mach/clock.h b/arch/arm/mach-k3/include/mach/clock.h index 32368ce0ede..866319365f0 100644 --- a/arch/arm/mach-k3/include/mach/clock.h +++ b/arch/arm/mach-k3/include/mach/clock.h @@ -7,8 +7,6 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H -#include <config.h> - /* Clock Defines */ #define V_OSCK 24000000 #define V_SCLK V_OSCK diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h index 780341124a8..0ba37c9ec7d 100644 --- a/arch/arm/mach-k3/include/mach/j721e_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h @@ -7,7 +7,6 @@ #ifndef __ASM_ARCH_J721E_HARDWARE_H #define __ASM_ARCH_J721E_HARDWARE_H -#include <config.h> #ifndef __ASSEMBLY__ #include <linux/bitops.h> #endif diff --git a/arch/arm/mach-k3/include/mach/j721s2_hardware.h b/arch/arm/mach-k3/include/mach/j721s2_hardware.h index ad4fcdd4a97..5aa2282f59a 100644 --- a/arch/arm/mach-k3/include/mach/j721s2_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h @@ -7,7 +7,6 @@ #ifndef __ASM_ARCH_J721S2_HARDWARE_H #define __ASM_ARCH_J721S2_HARDWARE_H -#include <config.h> #ifndef __ASSEMBLY__ #include <linux/bitops.h> #endif diff --git a/arch/arm/mach-k3/r5/j7200/clk-data.c b/arch/arm/mach-k3/r5/j7200/clk-data.c index 9b45786a2d4..eb8436decbd 100644 --- a/arch/arm/mach-k3/r5/j7200/clk-data.c +++ b/arch/arm/mach-k3/r5/j7200/clk-data.c @@ -141,6 +141,11 @@ static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { "hsdiv4_16fft_main_0_hsdivout0_clk", }; +static const char * const main_pll8_sel_extwave_out0_parents[] = { + "pllfracf_ssmod_16fft_main_8_foutvcop_clk", + "hsdiv0_16fft_main_8_hsdivout0_clk", +}; + static const char * const mcu_obsclk_outmux_out0_parents[] = { "mcu_obsclk_div_out0", "gluelogic_hfosc0_clkout", @@ -396,6 +401,7 @@ static const struct clk_data clk_list[] = { CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0), CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_MUX("main_pll8_sel_extwave_out0", main_pll8_sel_extwave_out0_parents, 2, 0x688040, 0, 1, 0), CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0, 0), CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0), CLK_PLL("pllfracf_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0), @@ -545,11 +551,14 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(288, 14, "board_0_hfosc1_clk_out"), DEV_CLK(288, 15, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(288, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(323, 0, "main_pll8_sel_extwave_out0"), + DEV_CLK(323, 1, "pllfracf_ssmod_16fft_main_8_foutvcop_clk"), + DEV_CLK(323, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), }; const struct ti_k3_clk_platdata j7200_clk_platdata = { .clk_list = clk_list, - .clk_list_cnt = 109, + .clk_list_cnt = ARRAY_SIZE(clk_list), .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 129, + .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data), }; diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c index c6e7e2c3097..d3b894c1b37 100644 --- a/arch/arm/mach-keystone/cmd_mon.c +++ b/arch/arm/mach-keystone/cmd_mon.c @@ -6,6 +6,7 @@ * Texas Instruments Incorporated, <www.ti.com> */ +#include <config.h> #include <command.h> #include <image.h> #include <mach/mon.h> diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 8971e2d2b0f..c3872f42869 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -76,6 +76,14 @@ config TARGET_MT8183 SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options. +config TARGET_MT8365 + bool "MediaTek MT8365 SoC" + select ARM64 + help + The MediaTek MT8365 is a ARM64-based SoC with a quad-core Cortex-A53. + It is including UART, SPI, USB2.0 dual role, SD and MMC cards, NAND, PWM, + I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options. + config TARGET_MT8512 bool "MediaTek MT8512 M1 Board" select ARM64 @@ -133,6 +141,7 @@ config SYS_CONFIG_NAME default "mt7986" if TARGET_MT7986 default "mt7988" if TARGET_MT7988 default "mt8183" if TARGET_MT8183 + default "mt8365" if TARGET_MT8365 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 default "mt8518" if TARGET_MT8518 diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index 71aa341e344..46bdab88206 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -11,5 +11,6 @@ obj-$(CONFIG_TARGET_MT7981) += mt7981/ obj-$(CONFIG_TARGET_MT7986) += mt7986/ obj-$(CONFIG_TARGET_MT7988) += mt7988/ obj-$(CONFIG_TARGET_MT8183) += mt8183/ +obj-$(CONFIG_TARGET_MT8365) += mt8365/ obj-$(CONFIG_TARGET_MT8516) += mt8516/ obj-$(CONFIG_TARGET_MT8518) += mt8518/ diff --git a/arch/arm/mach-mediatek/mt8365/Makefile b/arch/arm/mach-mediatek/mt8365/Makefile new file mode 100644 index 00000000000..886ab7e4eb9 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8365/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o diff --git a/arch/arm/mach-mediatek/mt8365/init.c b/arch/arm/mach-mediatek/mt8365/init.c new file mode 100644 index 00000000000..8f03ed28763 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8365/init.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 MediaTek Inc. + * Copyright (C) 2023 BayLibre, SAS + * Author: Julien Masson <jmasson@baylibre.com> + * Author: Fabien Parent <fparent@baylibre.com> + */ + +#include <asm/global_data.h> +#include <asm/system.h> +#include <dm/uclass.h> +#include <wdt.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +int mtk_soc_early_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + struct udevice *wdt; + + if (IS_ENABLED(CONFIG_PSCI_RESET)) { + psci_system_reset(); + } else { + uclass_first_device(UCLASS_WDT, &wdt); + if (wdt) + wdt_expire_now(wdt, 0); + } +} + +int print_cpuinfo(void) +{ + printf("CPU: MediaTek MT8365\n"); + return 0; +} diff --git a/arch/arm/mach-rmobile/cpu_info-rzg2l.c b/arch/arm/mach-rmobile/cpu_info-rzg2l.c index f69649dc7ea..bd3146fb011 100644 --- a/arch/arm/mach-rmobile/cpu_info-rzg2l.c +++ b/arch/arm/mach-rmobile/cpu_info-rzg2l.c @@ -4,6 +4,7 @@ * */ +#include <mach/rmobile.h> #include <asm/io.h> #include <linux/libfdt.h> diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index fdd0c592b3e..2c3e9789cc8 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -16,7 +16,6 @@ #include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <linux/bitops.h> -#include <linux/kconfig.h> #if CONFIG_IS_ENABLED(BANNER_PRINT) #include <timestamp.h> diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index bff2e42513c..62bc2a0231e 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -15,7 +15,6 @@ #include <asm/arch/prcm.h> #include <linux/bitops.h> #include <linux/delay.h> -#include <linux/kconfig.h> /* * The DRAM controller structure on H6 is similar to the ones on A23/A80: diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index c5c1331a4c3..e62d5711d0f 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -22,7 +22,6 @@ #include <asm/arch/prcm.h> #include <linux/bitops.h> #include <linux/delay.h> -#include <linux/kconfig.h> enum { MBUS_QOS_LOWEST = 0, diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 9382d3d0be8..daef051d0c8 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -16,7 +16,6 @@ #include <asm/arch/dram.h> #include <asm/arch/cpu.h> #include <linux/delay.h> -#include <linux/kconfig.h> static void mctl_phy_init(u32 val) { diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index f2737781287..b18885f4c1f 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -33,9 +33,6 @@ config TEGRA_IVC config TEGRA_MC bool -config TEGRA_PINCTRL - bool - config TEGRA_PMC bool @@ -61,7 +58,6 @@ config TEGRA_COMMON select OF_CONTROL select SPI select SYSRESET - select SPL_SYSRESET if SPL select SYSRESET_TEGRA imply CMD_DM imply CRC32_VERIFY @@ -76,9 +72,15 @@ config TEGRA_ARMV7_COMMON bool "Tegra 32-bit common options" select BINMAN select CPU_V7A + select PINCTRL + select PINCTRL_TEGRA select SPL select SPL_BOARD_INIT if SPL + select SPL_DM if SPL + select SPL_PINCTRL if SPL + select SPL_PINCTRL_TEGRA if SPL select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL + select SPL_SYSRESET if SPL select SUPPORT_SPL select TIMER select TEGRA_CLKRST @@ -87,7 +89,6 @@ config TEGRA_ARMV7_COMMON select TEGRA_GP_PADCTRL select TEGRA_MC select TEGRA_NO_BPMP - select TEGRA_PINCTRL select TEGRA_PMC select TEGRA_TIMER @@ -134,6 +135,8 @@ config TEGRA124 config TEGRA210 bool "Tegra210 family" select GICV2 + select PINCTRL + select PINCTRL_TEGRA select TIMER select TEGRA_ARMV8_COMMON select TEGRA_CLKRST @@ -141,7 +144,6 @@ config TEGRA210 select TEGRA_GP_PADCTRL select TEGRA_MC select TEGRA_NO_BPMP - select TEGRA_PINCTRL select TEGRA_PMC select TEGRA_PMC_SECURE select TEGRA_TIMER @@ -194,7 +196,7 @@ config TEGRA_SPI choice prompt "UART to use for console" - depends on TEGRA_PINCTRL + depends on PINCTRL_TEGRA default TEGRA_ENABLE_UARTA config TEGRA_ENABLE_UARTA diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index a5733b0bf6b..1d22dc3942f 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -17,7 +17,6 @@ obj-y += board.o board2.o obj-y += cache.o obj-$(CONFIG_TEGRA_CLKRST) += clock.o obj-$(CONFIG_$(SPL_)TEGRA_CRYPTO) += crypto.o -obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o obj-$(CONFIG_TEGRA_PMC) += powergate.o obj-y += xusb-padctl-dummy.o diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index f8b61a2b3e3..9224743d0ed 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -17,7 +17,7 @@ #if IS_ENABLED(CONFIG_TEGRA_CLKRST) #include <asm/arch/clock.h> #endif -#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) +#if CONFIG_IS_ENABLED(PINCTRL_TEGRA) #include <asm/arch/funcmux.h> #endif #if IS_ENABLED(CONFIG_TEGRA_MC) @@ -163,7 +163,7 @@ int dram_init(void) return 0; } -#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) +#if CONFIG_IS_ENABLED(PINCTRL_TEGRA) static int uart_configs[] = { #if defined(CONFIG_TEGRA20) #if defined(CONFIG_TEGRA_UARTA_UAA_UAB) @@ -235,7 +235,7 @@ static void setup_uarts(int uart_ids) void board_init_uart_f(void) { -#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) +#if CONFIG_IS_ENABLED(PINCTRL_TEGRA) int uart_ids = 0; /* bit mask of which UART ids to enable */ #ifdef CONFIG_TEGRA_ENABLE_UARTA diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 8ad76d5edf7..adea12c9b7f 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -34,7 +34,7 @@ #if IS_ENABLED(CONFIG_TEGRA_CLKRST) #include <asm/arch/clock.h> #endif -#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) +#if CONFIG_IS_ENABLED(PINCTRL_TEGRA) #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> #endif diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 966009f3752..575da2bdb5a 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -128,14 +128,14 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, struct clk_pll_simple *simple_pll = NULL; u32 misc_data, data; - if (clkid < (enum clock_id)TEGRA_CLK_PLLS) { + if (clkid < (enum clock_id)TEGRA_CLK_PLLS) pll = get_pll(clkid); - } else { + else simple_pll = clock_get_simple_pll(clkid); - if (!simple_pll) { - debug("%s: Uknown simple PLL %d\n", __func__, clkid); - return 0; - } + + if (!simple_pll && !pll) { + log_err("Unknown PLL id %d\n", clkid); + return 0; } /* @@ -542,7 +542,8 @@ unsigned int __weak clk_m_get_rate(unsigned int parent_rate) unsigned clock_get_rate(enum clock_id clkid) { - struct clk_pll *pll; + struct clk_pll *pll = NULL; + struct clk_pll_simple *simple_pll = NULL; u32 base, divm; u64 parent_rate, rate; struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; @@ -554,10 +555,20 @@ unsigned clock_get_rate(enum clock_id clkid) if (clkid == CLOCK_ID_CLK_M) return clk_m_get_rate(parent_rate); - pll = get_pll(clkid); - if (!pll) + if (clkid < (enum clock_id)TEGRA_CLK_PLLS) + pll = get_pll(clkid); + else + simple_pll = clock_get_simple_pll(clkid); + + if (!simple_pll && !pll) { + log_err("Unknown PLL id %d\n", clkid); return 0; - base = readl(&pll->pll_base); + } + + if (pll) + base = readl(&pll->pll_base); + else + base = readl(&simple_pll->pll_base); rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask); divm = (base >> pllinfo->m_shift) & pllinfo->m_mask; @@ -599,12 +610,24 @@ unsigned clock_get_rate(enum clock_id clkid) int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) { u32 base_reg, misc_reg; - struct clk_pll *pll; + struct clk_pll *pll = NULL; + struct clk_pll_simple *simple_pll = NULL; struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; - pll = get_pll(clkid); + if (clkid < (enum clock_id)TEGRA_CLK_PLLS) + pll = get_pll(clkid); + else + simple_pll = clock_get_simple_pll(clkid); - base_reg = readl(&pll->pll_base); + if (!simple_pll && !pll) { + log_err("Unknown PLL id %d\n", clkid); + return 0; + } + + if (pll) + base_reg = readl(&pll->pll_base); + else + base_reg = readl(&simple_pll->pll_base); /* Set BYPASS, m, n and p to PLL_BASE */ base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift); @@ -631,21 +654,37 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) } base_reg |= PLL_BYPASS_MASK; - writel(base_reg, &pll->pll_base); + if (pll) + writel(base_reg, &pll->pll_base); + else + writel(base_reg, &simple_pll->pll_base); /* Set cpcon (KCP) to PLL_MISC */ - misc_reg = readl(&pll->pll_misc); + if (pll) + misc_reg = readl(&pll->pll_misc); + else + misc_reg = readl(&simple_pll->pll_misc); + misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift); misc_reg |= cpcon << pllinfo->kcp_shift; - writel(misc_reg, &pll->pll_misc); + if (pll) + writel(misc_reg, &pll->pll_misc); + else + writel(misc_reg, &simple_pll->pll_misc); /* Enable PLL */ base_reg |= PLL_ENABLE_MASK; - writel(base_reg, &pll->pll_base); + if (pll) + writel(base_reg, &pll->pll_base); + else + writel(base_reg, &simple_pll->pll_base); /* Disable BYPASS */ base_reg &= ~PLL_BYPASS_MASK; - writel(base_reg, &pll->pll_base); + if (pll) + writel(base_reg, &pll->pll_base); + else + writel(base_reg, &simple_pll->pll_base); return 0; } @@ -729,6 +768,9 @@ void clock_init(void) pll_rate[CLOCK_ID_SFROM32KHZ] = 32768; pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC); pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M); +#ifndef CONFIG_TEGRA20 + pll_rate[CLOCK_ID_DISPLAY2] = clock_get_rate(CLOCK_ID_DISPLAY2); +#endif debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]); debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]); diff --git a/arch/arm/mach-tegra/tegra114/Makefile b/arch/arm/mach-tegra/tegra114/Makefile index 0e8f32cbd68..346d6cb5696 100644 --- a/arch/arm/mach-tegra/tegra114/Makefile +++ b/arch/arm/mach-tegra/tegra114/Makefile @@ -4,4 +4,4 @@ obj-$(CONFIG_SPL_BUILD) += cpu.o -obj-y += clock.o funcmux.o pinmux.o +obj-y += clock.o diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index 8ad71f590fa..418ad48ddc2 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -457,6 +457,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ }; /* @@ -671,6 +673,9 @@ enum clock_id clk_id_to_pll_id(int clk_id) case TEGRA114_CLK_PLL_D: case TEGRA114_CLK_PLL_D_OUT0: return CLOCK_ID_DISPLAY; + case TEGRA114_CLK_PLL_D2: + case TEGRA114_CLK_PLL_D2_OUT0: + return CLOCK_ID_DISPLAY2; case TEGRA114_CLK_PLL_X: return CLOCK_ID_XCPU; case TEGRA114_CLK_PLL_E_OUT0: @@ -768,6 +773,23 @@ void arch_timer_init(void) debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); } +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + switch (clkid) { + case CLOCK_ID_XCPU: + case CLOCK_ID_EPCI: + case CLOCK_ID_SFROM32KHZ: + return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + case CLOCK_ID_DISPLAY2: + return &clkrst->plld2; + default: + return NULL; + } +} + struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, diff --git a/arch/arm/mach-tegra/tegra124/Makefile b/arch/arm/mach-tegra/tegra124/Makefile index d275dafdc4f..6ea511e7b25 100644 --- a/arch/arm/mach-tegra/tegra124/Makefile +++ b/arch/arm/mach-tegra/tegra124/Makefile @@ -8,8 +8,6 @@ obj-$(CONFIG_SPL_BUILD) += cpu.o obj-y += clock.o -obj-y += funcmux.o -obj-y += pinmux.o obj-y += pmc.o obj-y += xusb-padctl.o obj-y += ../xusb-padctl-common.o diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index ca9549a3186..ed8b6d96381 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -1189,10 +1189,16 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - if (clkid == CLOCK_ID_DP) + switch (clkid) { + case CLOCK_ID_XCPU: + case CLOCK_ID_EPCI: + case CLOCK_ID_SFROM32KHZ: + return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + case CLOCK_ID_DP: return &clkrst->plldp; - - return NULL; + default: + return NULL; + } } struct periph_clk_init periph_clk_init_table[] = { diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index 991cabeec56..c2ae98eb376 100644 --- a/arch/arm/mach-tegra/tegra20/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -11,7 +11,7 @@ CFLAGS_warmboot_avp.o = -march=armv4t -U__LINUX_ARM_ARCH__ \ -D__LINUX_ARM_ARCH__=4 CFLAGS_REMOVE_warmboot_avp.o := $(LTO_CFLAGS) -obj-y += clock.o funcmux.o pinmux.o +obj-y += clock.o obj-$(CONFIG_TEGRA_LP0) += warmboot.o warmboot_avp.o obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o obj-$(CONFIG_TEGRA_PMU) += pmu.o diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index abd6e3917ac..109b73bfbe7 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -792,6 +792,21 @@ int tegra_plle_enable(void) return 0; } +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + switch (clkid) { + case CLOCK_ID_XCPU: + case CLOCK_ID_EPCI: + case CLOCK_ID_SFROM32KHZ: + return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + default: + return NULL; + } +} + struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SPI1, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/arch/arm/mach-tegra/tegra210/Makefile index cfcba5b68fe..5cc718d2767 100644 --- a/arch/arm/mach-tegra/tegra210/Makefile +++ b/arch/arm/mach-tegra/tegra210/Makefile @@ -6,6 +6,5 @@ # obj-y += clock.o -obj-y += funcmux.o obj-y += xusb-padctl.o obj-y += ../xusb-padctl-common.o diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 900537afbe5..74817e0440b 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -1266,6 +1266,21 @@ int tegra_plle_enable(void) return 0; } +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + switch (clkid) { + case CLOCK_ID_XCPU: + case CLOCK_ID_EPCI: + case CLOCK_ID_SFROM32KHZ: + return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + default: + return NULL; + } +} + struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, diff --git a/arch/arm/mach-tegra/tegra30/Makefile b/arch/arm/mach-tegra/tegra30/Makefile index 28dd486d8dd..ee0e6f5b948 100644 --- a/arch/arm/mach-tegra/tegra30/Makefile +++ b/arch/arm/mach-tegra/tegra30/Makefile @@ -5,4 +5,4 @@ obj-$(CONFIG_SPL_BUILD) += cpu.o obj-$(CONFIG_$(SPL_)CMD_EBTUPDATE) += bct.o -obj-y += clock.o funcmux.o pinmux.o +obj-y += clock.o diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 698c7ab9560..0af8cde8c64 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -438,6 +438,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ }; /* @@ -654,6 +656,9 @@ enum clock_id clk_id_to_pll_id(int clk_id) case TEGRA30_CLK_PLL_D: case TEGRA30_CLK_PLL_D_OUT0: return CLOCK_ID_DISPLAY; + case TEGRA30_CLK_PLL_D2: + case TEGRA30_CLK_PLL_D2_OUT0: + return CLOCK_ID_DISPLAY2; case TEGRA30_CLK_PLL_X: return CLOCK_ID_XCPU; case TEGRA30_CLK_PLL_E: @@ -871,6 +876,23 @@ int tegra_plle_enable(void) return 0; } +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + switch (clkid) { + case CLOCK_ID_XCPU: + case CLOCK_ID_EPCI: + case CLOCK_ID_SFROM32KHZ: + return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + case CLOCK_ID_DISPLAY2: + return &clkrst->plld2; + default: + return NULL; + } +} + struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, diff --git a/arch/arm/mach-zynq/clk.c b/arch/arm/mach-zynq/clk.c index 1945f60e08f..e6a67326dd4 100644 --- a/arch/arm/mach-zynq/clk.c +++ b/arch/arm/mach-zynq/clk.c @@ -13,20 +13,6 @@ DECLARE_GLOBAL_DATA_PTR; -static const char * const clk_names[clk_max] = { - "armpll", "ddrpll", "iopll", - "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", - "ddr2x", "ddr3x", "dci", - "lqspi", "smc", "pcap", "gem0", "gem1", - "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", - "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", - "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", - "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", - "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", - "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", - "smc_aper", "swdt", "dbg_trc", "dbg_apb" -}; - /** * set_cpu_clk_info() - Setup clock information * @@ -65,46 +51,3 @@ int set_cpu_clk_info(void) return 0; } - -/** - * soc_clk_dump() - Print clock frequencies - * Returns zero on success - * - * Implementation for the clk dump command. - */ -int soc_clk_dump(void) -{ - struct udevice *dev; - int i, ret; - - ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_DRIVER_GET(zynq_clk), &dev); - if (ret) - return ret; - - printf("clk\t\tfrequency\n"); - for (i = 0; i < clk_max; i++) { - const char *name = clk_names[i]; - if (name) { - struct clk clk; - unsigned long rate; - - clk.id = i; - ret = clk_request(dev, &clk); - if (ret < 0) - return ret; - - rate = clk_get_rate(&clk); - - clk_free(&clk); - - if ((rate == (unsigned long)-ENOSYS) || - (rate == (unsigned long)-ENXIO)) - printf("%10s%20s\n", name, "unknown"); - else - printf("%10s%20lu\n", name, rate); - } - } - - return 0; -} diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index 8ed2b4dbab4..6ef7f7be1af 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -9,6 +9,8 @@ #ifndef __CACHE_H #define __CACHE_H +#include <config.h> + #if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \ defined(CONFIG_MCF52x2) #define CFG_CF_V2 diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h index 5f576ba16f9..c2ef5770a3d 100644 --- a/arch/m68k/include/asm/global_data.h +++ b/arch/m68k/include/asm/global_data.h @@ -7,8 +7,6 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H -#include <config.h> - /* Architecture-specific global data */ struct arch_global_data { #ifdef CONFIG_SYS_I2C_FSL @@ -24,7 +22,7 @@ struct arch_global_data { unsigned long sdhc_clk; #endif #if defined(CONFIG_FSL_ESDHC) - u32 sdhc_per_clk; + unsigned long sdhc_per_clk; #endif }; diff --git a/arch/m68k/lib/traps.c b/arch/m68k/lib/traps.c index ae8ae6ccf59..e09f36f2fdd 100644 --- a/arch/m68k/lib/traps.c +++ b/arch/m68k/lib/traps.c @@ -7,6 +7,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include <config.h> #include <cpu_func.h> #include <init.h> #include <watchdog.h> diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h index f0d3b07bf1e..34b7e0bed94 100644 --- a/arch/mips/include/asm/global_data.h +++ b/arch/mips/include/asm/global_data.h @@ -7,8 +7,8 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include <linux/types.h> #include <asm/regdef.h> -#include <asm/types.h> struct octeon_eeprom_mac_addr { u8 mac_addr_base[6]; diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c index dbf8c9cd221..3181a946a27 100644 --- a/arch/mips/mach-pic32/cpu.c +++ b/arch/mips/mach-pic32/cpu.c @@ -143,26 +143,3 @@ const char *get_core_name(void) return str; } #endif -#ifdef CONFIG_CMD_CLK - -int soc_clk_dump(void) -{ - int i; - - printf("PLL Speed: %lu MHz\n", - CLK_MHZ(rate(PLLCLK))); - - printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK))); - - printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL))); - - for (i = PB1CLK; i <= PB7CLK; i++) - printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1, - CLK_MHZ(rate(i))); - - for (i = REF1CLK; i <= REF5CLK; i++) - printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1, - CLK_MHZ(rate(i))); - return 0; -} -#endif diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h index 1a0e7d25fa3..b56e8a5078e 100644 --- a/arch/nios2/include/asm/global_data.h +++ b/arch/nios2/include/asm/global_data.h @@ -6,6 +6,8 @@ #ifndef __ASM_NIOS2_GLOBALDATA_H_ #define __ASM_NIOS2_GLOBALDATA_H_ +#include <linux/types.h> + /* Architecture-specific global data */ struct arch_global_data { u32 dcache_line_size; diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 43d71f5caec..f7860122a00 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -8,7 +8,6 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H -#include <config.h> #include <linux/types.h> /* Architecture-specific global data */ diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6d0d812ddb5..67126d96af8 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -39,6 +39,9 @@ config TARGET_TH1520_LPI4A bool "Support Sipeed's TH1520 Lichee PI 4A Board" select SYS_CACHE_SHIFT_6 +config TARGET_XILINX_MBV + bool "Support AMD/Xilinx MicroBlaze V" + endchoice config SYS_ICACHE_OFF @@ -82,6 +85,7 @@ source "board/sifive/unmatched/Kconfig" source "board/sipeed/maix/Kconfig" source "board/starfive/visionfive2/Kconfig" source "board/thead/th1520_lpi4a/Kconfig" +source "board/xilinx/mbv/Kconfig" # platform-specific options below source "arch/riscv/cpu/andesv5/Kconfig" diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index be6c8a42272..b05bb5607f0 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,6 +9,8 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb +dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb + include $(srctree)/scripts/Makefile.dts targets += $(dtb-y) diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index 6b4eb8dc7b9..9271de0ddfc 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -5,9 +5,6 @@ #include <config.h> -#define U64_TO_U32_H(addr) (((addr) >> 32) & 0xffffffff) -#define U64_TO_U32_L(addr) ((addr) & 0xffffffff) - / { binman: binman { multiple-images; @@ -36,8 +33,7 @@ os = "U-Boot"; arch = "riscv"; compression = "none"; - load = <U64_TO_U32_H(CONFIG_TEXT_BASE) - U64_TO_U32_L(CONFIG_TEXT_BASE)>; + load = /bits/ 64 <CONFIG_TEXT_BASE>; uboot_blob: blob-ext { filename = "u-boot-nodtb.bin"; @@ -50,7 +46,7 @@ os = "Linux"; arch = "riscv"; compression = "none"; - load = <CONFIG_TEXT_BASE>; + load = /bits/ 64 <CONFIG_TEXT_BASE>; linux_blob: blob-ext { filename = "Image"; @@ -64,10 +60,8 @@ os = "opensbi"; arch = "riscv"; compression = "none"; - load = <U64_TO_U32_H(CONFIG_SPL_OPENSBI_LOAD_ADDR) - U64_TO_U32_L(CONFIG_SPL_OPENSBI_LOAD_ADDR)>; - entry = <U64_TO_U32_H(CONFIG_SPL_OPENSBI_LOAD_ADDR) - U64_TO_U32_L(CONFIG_SPL_OPENSBI_LOAD_ADDR)>; + load = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>; + entry = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>; opensbi_blob: opensbi { filename = "fw_dynamic.bin"; diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi index e40f57a1508..e94f9fe826a 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi @@ -34,6 +34,11 @@ device_type = "memory"; reg = <0x0 0x40000000 0x2 0x0>; }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>; + }; }; &osc { diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 13c47f7caa3..6d2675d6cea 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -533,6 +533,16 @@ #gpio-cells = <2>; }; + watchdog@13070000 { + compatible = "starfive,jh7110-wdt"; + reg = <0x0 0x13070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, + <&syscrg JH7110_SYSCLK_WDT_CORE>; + clock-names = "apb", "core"; + resets = <&syscrg JH7110_SYSRST_WDT_APB>, + <&syscrg JH7110_SYSRST_WDT_CORE>; + }; + mmc0: mmc@16010000 { compatible = "starfive,jh7110-mmc"; reg = <0x0 0x16010000 0x0 0x10000>; diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts new file mode 100644 index 00000000000..6a6b8b694bd --- /dev/null +++ b/arch/riscv/dts/xilinx-mbv32.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for AMD MicroBlaze V + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "AMD MicroBlaze V 32bit"; + compatible = "amd,mbv"; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <102000000>; + cpu_0: cpu@0 { + compatible = "amd,mbv32", "riscv"; + device_type = "cpu"; + reg = <0>; + riscv,isa = "rv32imafdc"; + i-cache-size = <32768>; + d-cache-size = <32768>; + clock-frequency = <102000000>; + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x20000000>; + }; + + clk102: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <102000000>; + }; + + axi: axi { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + bootph-all; + + axi_intc: interrupt-controller@41200000 { + compatible = "xlnx,xps-intc-1.00.a"; + reg = <0x41200000 0x1000>; + interrupt-controller; + interrupt-parent = <&cpu0_intc>; + #interrupt-cells = <2>; + kind-of-intr = <0>; + }; + + xlnx_timer0: timer@41c00000 { + compatible = "xlnx,xps-timer-1.00.a"; + reg = <0x41c00000 0x1000>; + interrupt-parent = <&axi_intc>; + interrupts = <1 2>; + bootph-all; + xlnx,one-timer-only = <0>; + clock-names = "s_axi_aclk"; + clocks = <&clk102>; + }; + + xlnx_timer1: timer@41c20000 { + compatible = "xlnx,xps-timer-1.00.a"; + reg = <0x41c20000 0x1000>; + interrupt-parent = <&axi_intc>; + interrupts = <0 2>; + xlnx,one-timer-only = <0>; + clock-names = "s_axi_aclk"; + clocks = <&clk102>; + }; + + uart0: serial@40600000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x40600000 0x1000>; + interrupt-parent = <&axi_intc>; + interrupts = <2 2>; + bootph-all; + clocks = <&clk102>; + current-speed = <115200>; + xlnx,data-bits = <8>; + xlnx,use-parity = <0>; + }; + }; +}; diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 937fa4d1544..d00247ad953 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -10,6 +10,7 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include <linux/types.h> #include <asm/smp.h> #include <asm/u-boot.h> #include <compiler.h> diff --git a/arch/riscv/lib/andes_plicsw.c b/arch/riscv/lib/andes_plicsw.c index 6a63661312a..c09e5c69bc3 100644 --- a/arch/riscv/lib/andes_plicsw.c +++ b/arch/riscv/lib/andes_plicsw.c @@ -21,41 +21,36 @@ #include <linux/err.h> /* pending register */ -#define PENDING_REG(base) ((ulong)(base) + 0x1000) +#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + 4 * (((hart) + 1) / 32)) /* enable register */ -#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) +#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80 + 4 * (((hart) + 1) / 32)) /* claim register */ #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) /* priority register */ #define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE) /* Bit 0 of PLIC-SW pending array is hardwired to zero, so we start from bit 1 */ -#define FIRST_AVAILABLE_BIT 0x2 -#define SEND_IPI_TO_HART(hart) (FIRST_AVAILABLE_BIT << (hart)) #define PLICSW_PRIORITY_BASE 0x4 -#define PLICSW_INTERRUPT_PER_HART 0x1 DECLARE_GLOBAL_DATA_PTR; static int enable_ipi(int hart) { - unsigned int en; + u32 enable_bit = (hart + 1) % 32; - en = FIRST_AVAILABLE_BIT << hart; - writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart)); + writel(BIT(enable_bit), (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart)); return 0; } static void init_priority_ipi(int hart_num) { - uint32_t *priority = (void *)PRIORITY_REG(gd->arch.plicsw); + u32 *priority = (void *)PRIORITY_REG(gd->arch.plicsw); - for (int i = 0; i < hart_num * PLICSW_INTERRUPT_PER_HART; i++) { - writel(1, &priority[i]); - } + for (int i = 0; i < hart_num; i++) + writel(1, &priority[i]); - return; + return; } int riscv_init_ipi(void) @@ -104,9 +99,10 @@ int riscv_init_ipi(void) int riscv_send_ipi(int hart) { - unsigned int ipi = SEND_IPI_TO_HART(hart); + u32 interrupt_id = hart + 1; + u32 pending_bit = interrupt_id % 32; - writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw)); + writel(BIT(pending_bit), (void __iomem *)PENDING_REG(gd->arch.plicsw, hart)); return 0; } @@ -123,10 +119,11 @@ int riscv_clear_ipi(int hart) int riscv_get_ipi(int hart, int *pending) { - unsigned int ipi = SEND_IPI_TO_HART(hart); + u32 interrupt_id = hart + 1; + u32 pending_bit = interrupt_id % 32; - *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw)); - *pending = !!(*pending & ipi); + *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw, hart)); + *pending = !!(*pending & BIT(pending_bit)); return 0; } diff --git a/arch/sandbox/cpu/cache.c b/arch/sandbox/cpu/cache.c index 46c62c0b446..c8a5e64214b 100644 --- a/arch/sandbox/cpu/cache.c +++ b/arch/sandbox/cpu/cache.c @@ -3,7 +3,6 @@ * Copyright 2020, Heinrich Schuchardt <xypron.glpk@gmx.de> */ -#include <common.h> #include <cpu_func.h> #include <asm/state.h> diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index d134905e3f5..0ed85b354cf 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_SANDBOX -#include <common.h> #include <bootstage.h> #include <cpu_func.h> #include <errno.h> diff --git a/arch/sandbox/cpu/sdl.c b/arch/sandbox/cpu/sdl.c index 590e406517b..ed84646bdab 100644 --- a/arch/sandbox/cpu/sdl.c +++ b/arch/sandbox/cpu/sdl.c @@ -72,7 +72,7 @@ static struct sdl_info { static void sandbox_sdl_poll_events(void) { /* - * We don't want to include common.h in this file since it uses + * We don't want to include cpu_func.h in this file since it uses * system headers. So add a declation here. */ extern void reset_cpu(void); diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index 16b76627983..9ad9da686c6 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -3,7 +3,6 @@ * Copyright (c) 2016 Google, Inc */ -#include <common.h> #include <dm.h> #include <hang.h> #include <handoff.h> diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 2589c2eba73..dce80416529 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -3,7 +3,7 @@ * Copyright (c) 2011-2012 The Chromium OS Authors. */ -#include <common.h> +#include <config.h> #include <cli.h> #include <command.h> #include <efi_loader.h> diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index e38bb248b7f..a9ca79e76d2 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -3,9 +3,8 @@ * Copyright (c) 2011-2012 The Chromium OS Authors. */ -#include <common.h> -#include <autoboot.h> #include <bloblist.h> +#include <config.h> #include <errno.h> #include <fdtdec.h> #include <log.h> diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 9131eda970b..4fe72664c4b 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -631,9 +631,10 @@ clocks = <&clk_fixed>, <&clk_sandbox 1>, <&clk_sandbox 0>, + <&ccf 11>, <&clk_sandbox 3>, <&clk_sandbox 2>; - clock-names = "fixed", "i2c", "spi", "uart2", "uart1"; + clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1"; }; clk-test2 { @@ -654,6 +655,7 @@ ccf: clk-ccf { compatible = "sandbox,clk-ccf"; + #clock-cells = <1>; }; efi-media { diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h index 2b7dbca8f75..d4e04ad1486 100644 --- a/arch/sandbox/include/asm/clk.h +++ b/arch/sandbox/include/asm/clk.h @@ -38,6 +38,7 @@ enum sandbox_clk_test_id { SANDBOX_CLK_TEST_ID_FIXED, SANDBOX_CLK_TEST_ID_SPI, SANDBOX_CLK_TEST_ID_I2C, + SANDBOX_CLK_TEST_ID_I2C_ROOT, SANDBOX_CLK_TEST_ID_DEVM1, SANDBOX_CLK_TEST_ID_DEVM2, SANDBOX_CLK_TEST_ID_DEVM_NULL, diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h index c6977735029..001b2b53c1c 100644 --- a/arch/sandbox/include/asm/global_data.h +++ b/arch/sandbox/include/asm/global_data.h @@ -9,6 +9,8 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include <linux/types.h> + /* Architecture-specific global data */ struct arch_global_data { uint8_t *ram_buf; /* emulated RAM buffer */ diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h index 77a02e5f524..3c0a102697e 100644 --- a/arch/sandbox/include/asm/io.h +++ b/arch/sandbox/include/asm/io.h @@ -6,6 +6,8 @@ #ifndef __SANDBOX_ASM_IO_H #define __SANDBOX_ASM_IO_H +#include <linux/types.h> + enum sandboxio_size_t { SB_SIZE_8, SB_SIZE_16, diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index 59a20595f51..c84a1f7060f 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -6,7 +6,6 @@ #ifndef __SANDBOX_STATE_H #define __SANDBOX_STATE_H -#include <config.h> #include <sysreset.h> #include <stdbool.h> #include <linux/list.h> diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c index e56de90e75b..8dbcd9ff7dd 100644 --- a/arch/sandbox/lib/bootm.c +++ b/arch/sandbox/lib/bootm.c @@ -4,7 +4,6 @@ * Copyright (c) 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> */ -#include <common.h> #include <bootm.h> #include <bootstage.h> #include <image.h> diff --git a/arch/sandbox/lib/fdt_fixup.c b/arch/sandbox/lib/fdt_fixup.c index a646f2059c2..e333bd52ea2 100644 --- a/arch/sandbox/lib/fdt_fixup.c +++ b/arch/sandbox/lib/fdt_fixup.c @@ -2,7 +2,6 @@ #define LOG_CATEGORY LOGC_ARCH -#include <common.h> #include <fdt_support.h> #include <log.h> diff --git a/arch/sandbox/lib/interrupts.c b/arch/sandbox/lib/interrupts.c index 4d7cbff802c..3f6583e11f0 100644 --- a/arch/sandbox/lib/interrupts.c +++ b/arch/sandbox/lib/interrupts.c @@ -5,7 +5,6 @@ * found in the LICENSE file. */ -#include <common.h> #include <efi_loader.h> #include <irq_func.h> #include <os.h> diff --git a/arch/sandbox/lib/pci_io.c b/arch/sandbox/lib/pci_io.c index 2038141947a..6040eacb594 100644 --- a/arch/sandbox/lib/pci_io.c +++ b/arch/sandbox/lib/pci_io.c @@ -8,7 +8,6 @@ * IO space access commands. */ -#include <common.h> #include <command.h> #include <dm.h> #include <log.h> diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 6f4a7130f1d..1ef7f1f0349 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -9,6 +9,7 @@ #ifndef __ASSEMBLY__ +#include <linux/types.h> #include <asm/processor.h> #include <asm/mrccache.h> diff --git a/board/BuR/common/br_resetc.h b/board/BuR/common/br_resetc.h index ba0689bf205..999045b867d 100644 --- a/board/BuR/common/br_resetc.h +++ b/board/BuR/common/br_resetc.h @@ -7,7 +7,6 @@ */ #ifndef __CONFIG_BRRESETC_H__ #define __CONFIG_BRRESETC_H__ -#include <common.h> int br_resetc_regget(u8 reg, u8 *dst); int br_resetc_regset(u8 reg, u8 val); diff --git a/board/CZ.NIC/turris_mox/mox_sp.h b/board/CZ.NIC/turris_mox/mox_sp.h index 720880d5df3..c766c7423ac 100644 --- a/board/CZ.NIC/turris_mox/mox_sp.h +++ b/board/CZ.NIC/turris_mox/mox_sp.h @@ -6,8 +6,6 @@ #ifndef _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_ #define _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_ -#include <common.h> - enum cznic_a3720_board { BOARD_UNDEFINED = 0x0, BOARD_TURRIS_MOX = 0x1, diff --git a/board/abilis/tb100/tb100.c b/board/abilis/tb100/tb100.c index 3dc9e14ef8c..eb7d1290813 100644 --- a/board/abilis/tb100/tb100.c +++ b/board/abilis/tb100/tb100.c @@ -14,6 +14,10 @@ void reset_cpu(void) writel(0x1, (void *)CRM_SWRESET); } +/* + * Ethernet configuration + */ +#define ETH0_BASE_ADDRESS 0xFE100000 int board_eth_init(struct bd_info *bis) { if (designware_initialize(ETH0_BASE_ADDRESS, 0) >= 0) diff --git a/board/asus/grouper/grouper.c b/board/asus/grouper/grouper.c index dc1d1102c3f..78eb34e7d46 100644 --- a/board/asus/grouper/grouper.c +++ b/board/asus/grouper/grouper.c @@ -7,25 +7,7 @@ * Svyatoslav Ryhel <clamor95@gmail.com> */ -#include <dm.h> #include <fdt_support.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/gp_padctrl.h> - -#include "pinmux-config-grouper.h" - -/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) -{ - pinmux_config_pingrp_table(grouper_pinmux_common, - ARRAY_SIZE(grouper_pinmux_common)); - - pinmux_config_drvgrp_table(grouper_padctrl, - ARRAY_SIZE(grouper_padctrl)); -} #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/board/asus/grouper/pinmux-config-grouper.h b/board/asus/grouper/pinmux-config-grouper.h deleted file mode 100644 index 98134f74f1a..00000000000 --- a/board/asus/grouper/pinmux-config-grouper.h +++ /dev/null @@ -1,362 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _PINMUX_CONFIG_GROUPER_H_ -#define _PINMUX_CONFIG_GROUPER_H_ - -#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_DEFAULT, \ - .od = PMUX_PIN_OD_DEFAULT, \ - .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ - } - -#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_##_lock, \ - .od = PMUX_PIN_OD_##_od, \ - .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ - } - -#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_##_lock, \ - .od = PMUX_PIN_OD_DEFAULT, \ - .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ - } - -#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ - { \ - .drvgrp = PMUX_DRVGRP_##_drvgrp, \ - .slwf = _slwf, \ - .slwr = _slwr, \ - .drvup = _drvup, \ - .drvdn = _drvdn, \ - .lpmd = PMUX_LPMD_##_lpmd, \ - .schmt = PMUX_SCHMT_##_schmt, \ - .hsm = PMUX_HSM_##_hsm, \ - } - -static struct pmux_pingrp_config grouper_pinmux_common[] = { - /* SDMMC1 pinmux */ - DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), - - /* SDMMC3 pinmux */ - DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, NORMAL, INPUT), - - /* SDMMC4 pinmux */ - LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD2, DOWN, NORMAL, INPUT, DISABLE, DISABLE), - - /* I2C pinmux */ - I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - - /* HDMI-CEC pinmux */ - DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), - - /* ULPI pinmux */ - DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, DOWN, TRISTATE, OUTPUT), - DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, UP, TRISTATE, OUTPUT), - DEFAULT_PINMUX(ULPI_CLK_PY0, ULPI, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(ULPI_DIR_PY1, ULPI, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(ULPI_NXT_PY2, RSVD1, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(ULPI_STP_PY3, RSVD1, NORMAL, TRISTATE, OUTPUT), - - /* DAP3 pinmux */ - DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, DOWN, TRISTATE, INPUT), - - DEFAULT_PINMUX(PV0, RSVD1, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PV2, OWR, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(PV3, RSVD1, NORMAL, TRISTATE, INPUT), - - /* CLK2 pinmux */ - DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT), - - /* LCD pinmux */ - DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, UP, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT), - - /* VI-group pinmux */ - LV_PINMUX(VI_D0_PT4, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D1_PD5, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D2_PL0, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D3_PL1, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D4_PL2, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D5_PL3, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D6_PL4, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D7_PL5, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D8_PL6, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D9_PL7, SDMMC2, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D10_PT2, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D11_PT3, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_PCLK_PT0, SDMMC2, UP, TRISTATE, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_MCLK_PT1, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_HSYNC_PD7, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_VSYNC_PD6, RSVD1, DOWN, TRISTATE, INPUT, DISABLE, DISABLE), - - /* UART-B pinmux */ - DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), - - /* UART-C pinmux */ - DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), - - /* U-gpio group pinmux */ - DEFAULT_PINMUX(PU0, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PU3, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PU6, RSVD4, NORMAL, NORMAL, INPUT), - - /* DAP4 pinmux */ - DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), - - /* CLK3 pinmux */ - DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, DOWN, NORMAL, INPUT), - - DEFAULT_PINMUX(PCC1, RSVD2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, UP, NORMAL, INPUT), - - /* KBC keys */ - DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, UP, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW1_PR1, KBC, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(KB_ROW2_PR2, KBC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW3_PR3, KBC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW4_PR4, KBC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW10_PS2, KBC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW11_PS3, KBC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW12_PS4, KBC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW13_PS5, KBC, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(KB_ROW14_PS6, KBC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW15_PS7, KBC, NORMAL, NORMAL, OUTPUT), - - DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(KB_COL2_PQ2, RSVD4, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_COL3_PQ3, RSVD4, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_COL4_PQ4, KBC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, TRISTATE, INPUT), - - /* CLK */ - DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), - - /* DAP1 pinmux */ - DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), - - /* CLK1 pinmux */ - DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT), - - /* SPDIF pinmux */ - DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT), - - /* DAP2 pinmux */ - DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), - - /* SPI pinmux */ - DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI2_MISO_PX1, SPI2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI2_SCK_PX2, SPI2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI2_CS2_N_PW3, SPI2, NORMAL, NORMAL, INPUT), - - /* PEX pinmux */ - DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, OUTPUT), - - /* GMI pinmux */ - DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_WAIT_PI7, RSVD1, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_ADV_N_PK0, RSVD1, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_CS0_N_PJ0, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_CS1_N_PJ2, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD1, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_CS6_N_PI3, GMI, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD0_PG0, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD1_PG1, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD2_PG2, RSVD1, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD3_PG3, RSVD1, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD6_PG6, RSVD1, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD7_PG7, RSVD1, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD9_PH1, RSVD4, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD10_PH2, PWM2, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD11_PH3, PWM3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD13_PH5, RSVD1, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD14_PH6, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD15_PH7, RSVD1, UP, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_WR_N_PI0, RSVD1, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_OE_N_PI1, RSVD1, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_DQS_PI2, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_RST_N_PI4, NAND, UP, NORMAL, OUTPUT), -}; - -static struct pmux_drvgrp_config grouper_padctrl[] = { - /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ - DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ - SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), -}; -#endif /* _PINMUX_CONFIG_GROUPER_H_ */ diff --git a/board/asus/transformer-t30/pinmux-config-transformer.h b/board/asus/transformer-t30/pinmux-config-transformer.h deleted file mode 100644 index 96ff45d3750..00000000000 --- a/board/asus/transformer-t30/pinmux-config-transformer.h +++ /dev/null @@ -1,365 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * Copyright (c) 2021, Svyatoslav Ryhel. - */ - -#ifndef _PINMUX_CONFIG_TRANSFORMER_H_ -#define _PINMUX_CONFIG_TRANSFORMER_H_ - -#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_DEFAULT, \ - .od = PMUX_PIN_OD_DEFAULT, \ - .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ - } - -#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_##_lock, \ - .od = PMUX_PIN_OD_##_od, \ - .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ - } - -#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_##_lock, \ - .od = PMUX_PIN_OD_DEFAULT, \ - .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ - } - -#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ - { \ - .drvgrp = PMUX_DRVGRP_##_drvgrp, \ - .slwf = _slwf, \ - .slwr = _slwr, \ - .drvup = _drvup, \ - .drvdn = _drvdn, \ - .lpmd = PMUX_LPMD_##_lpmd, \ - .schmt = PMUX_SCHMT_##_schmt, \ - .hsm = PMUX_HSM_##_hsm, \ - } - -static struct pmux_pingrp_config transformer_pinmux_common[] = { - /* SDMMC1 pinmux */ - DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), - - /* SDMMC3 pinmux */ - DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, NORMAL, INPUT), - - /* SDMMC4 pinmux */ - LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), - - /* I2C pinmux */ - I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - - /* HDMI-CEC pinmux */ - DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), - - /* ULPI pinmux */ - DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, DOWN, TRISTATE, INPUT), - DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA3_PO4, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, TRISTATE, OUTPUT), - - /* DAP3 pinmux */ - DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(PV0, RSVD1, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(PV2, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PV3, RSVD1, NORMAL, TRISTATE, OUTPUT), - - /* CLK2 pinmux */ - DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT), - - /* LCD pinmux */ - DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, TRISTATE, OUTPUT), - - /* VI-group pinmux */ - LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - - /* UART-B pinmux */ - DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), - - /* UART-C pinmux */ - DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), - - /* U-gpio group pinmux */ - DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PU4, RSVD1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PU6, RSVD1, DOWN, NORMAL, INPUT), - - /* DAP4 pinmux */ - DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), - - /* CLK3 pinmux */ - DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, TRISTATE, INPUT), - - DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, NORMAL, INPUT), - - DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), - - /* KBC keys */ - DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, UP, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW2_PR2, KBC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW4_PR4, KBC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW11_PS3, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW12_PS4, KBC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW13_PS5, KBC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT), - - DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL2_PQ2, RSVD4, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_COL3_PQ3, RSVD4, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_COL4_PQ4, RSVD4, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, TRISTATE, INPUT), - - /* CLK */ - DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), - - /* DAP1 pinmux */ - DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, TRISTATE, INPUT), - - /* CLK1 pinmux */ - DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT), - - /* SPDIF pinmux */ - DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, TRISTATE, OUTPUT), - - /* DAP2 pinmux */ - DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), - - /* SPI pinmux */ - DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT), - - /* PEX pinmux */ - DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), - - /* GMI pinmux */ - DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_WAIT_PI7, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD13_PH5, NAND, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD15_PH7, NAND, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT), -}; - -static struct pmux_pingrp_config tf700t_mipi_pinmux[] = { - DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_CS4_N_PK2, GMI, UP, NORMAL, INPUT), - DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, TRISTATE, INPUT), -}; - -static struct pmux_drvgrp_config transformer_padctrl[] = { - /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ - DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ - SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), -}; -#endif /* _PINMUX_CONFIG_TRANSFORMER_H_ */ diff --git a/board/asus/transformer-t30/transformer-t30.c b/board/asus/transformer-t30/transformer-t30.c index 7cac6fde6f4..a3fac1ca366 100644 --- a/board/asus/transformer-t30/transformer-t30.c +++ b/board/asus/transformer-t30/transformer-t30.c @@ -9,30 +9,7 @@ /* T30 Transformers derive from Cardhu board */ -#include <dm.h> #include <fdt_support.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/gp_padctrl.h> - -#include "pinmux-config-transformer.h" - -/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) -{ - pinmux_config_pingrp_table(transformer_pinmux_common, - ARRAY_SIZE(transformer_pinmux_common)); - - pinmux_config_drvgrp_table(transformer_padctrl, - ARRAY_SIZE(transformer_padctrl)); - - if (of_machine_is_compatible("asus,tf700t")) { - pinmux_config_pingrp_table(tf700t_mipi_pinmux, - ARRAY_SIZE(tf700t_mipi_pinmux)); - } -} #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile deleted file mode 100644 index 22c26ed1f6b..00000000000 --- a/board/compal/paz00/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. -# -# See file CREDITS for list of people who contributed to this -# project. - -obj-y := paz00.o diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c deleted file mode 100644 index d92eb162243..00000000000 --- a/board/compal/paz00/paz00.c +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * See file CREDITS for list of people who contributed to this - * project. - */ - -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <asm/arch/tegra.h> -#include <asm/arch/pinmux.h> -#include <asm/gpio.h> - -#ifdef CONFIG_MMC_SDHCI_TEGRA -/* - * Routine: pin_mux_mmc - * Description: setup the pin muxes/tristate values for the SDMMC(s) - */ -void pin_mux_mmc(void) -{ - /* SDMMC4: config 3, x8 on 2nd set of pins */ - pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4); - pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4); - pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4); - - pinmux_tristate_disable(PMUX_PINGRP_ATB); - pinmux_tristate_disable(PMUX_PINGRP_GMA); - pinmux_tristate_disable(PMUX_PINGRP_GME); - - /* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */ - pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1); - - pinmux_tristate_disable(PMUX_PINGRP_SDIO1); - - /* For power GPIO PV1 */ - pinmux_tristate_disable(PMUX_PINGRP_UAC); - /* For CD GPIO PV5 */ - pinmux_tristate_disable(PMUX_PINGRP_GPV); -} -#endif - -#ifdef CONFIG_VIDEO -/* this is a weak define that we are overriding */ -void pin_mux_display(void) -{ - debug("init display pinmux\n"); - - /* EN_VDD_PANEL GPIO A4 */ - pinmux_tristate_disable(PMUX_PINGRP_DAP2); -} -#endif diff --git a/board/cssi/cmpc885/sdram.c b/board/cssi/cmpc885/sdram.c index 11a50c3a52d..828784bd368 100644 --- a/board/cssi/cmpc885/sdram.c +++ b/board/cssi/cmpc885/sdram.c @@ -4,6 +4,7 @@ * Charles Frey <charles.frey@c-s.fr> */ +#include <config.h> #include <linux/sizes.h> #include <linux/delay.h> #include <init.h> diff --git a/board/data_modul/common/common.c b/board/data_modul/common/common.c index bf9a11472d1..4ece82c7303 100644 --- a/board/data_modul/common/common.c +++ b/board/data_modul/common/common.c @@ -12,7 +12,6 @@ #include <asm/io.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> -#include <common.h> #include <dm/uclass.h> #include <hang.h> #include <i2c_eeprom.h> @@ -30,6 +29,8 @@ DECLARE_GLOBAL_DATA_PTR; #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) +#define DDRC_ECCCFG0_ECC_MODE_MASK 0x7 + u8 dmo_get_memcfg(void) { struct gpio_desc gpio[4]; @@ -58,8 +59,16 @@ u8 dmo_get_memcfg(void) int board_phys_sdram_size(phys_size_t *size) { u8 memcfg = dmo_get_memcfg(); + u8 ecc = 0; - *size = (4ULL >> ((memcfg >> 1) & 0x3)) * SZ_1G; + *size = 4ULL >> ((memcfg >> 1) & 0x3); + + if (IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)) { + /* 896 MiB, i.e. 1 GiB without 12.5% reserved for in-band ECC */ + ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK; + } + + *size *= SZ_1G - (ecc ? (SZ_1G / 8) : 0); return 0; } @@ -100,6 +109,12 @@ static void spl_dram_init(struct dram_timing_info *dram_timing_info[8]) } ddr_init(dram_timing_info[memcfg]); + + if (IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)) { + printf("DDR: Inline ECC %sabled\n", + (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ? + "en" : "dis"); + } } void dmo_board_init_f(const iomux_v3_cfg_t wdog_pad, diff --git a/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c b/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c index 04cef3a8b9f..0ad40002d4e 100644 --- a/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c +++ b/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c @@ -19,47 +19,66 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400030, 0x1 }, { 0x3d400000, 0xa3080020 }, { 0x3d400020, 0x1303 }, - { 0x3d400024, 0x1c79100 }, + { 0x3d400024, 0x1c7cf80 }, { 0x3d400064, 0x710106 }, +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + { 0x3d400070, 0x7027fd4 }, +#else { 0x3d400070, 0x7027f90 }, +#endif { 0x3d400074, 0x790 }, - { 0x3d4000d0, 0xc0030720 }, + { 0x3d4000d0, 0xc0030721 }, { 0x3d4000d4, 0xb80000 }, - { 0x3d4000dc, 0xe40036 }, - { 0x3d4000e0, 0x330000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0xf30000 }, { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x1e262028 }, - { 0x3d400104, 0x7073b }, + { 0x3d400100, 0x1f262028 }, + { 0x3d400104, 0x8083b }, { 0x3d40010c, 0xe0e000 }, { 0x3d400110, 0x11040a11 }, - { 0x3d400114, 0x2050e0e }, - { 0x3d400118, 0x1010008 }, - { 0x3d40011c, 0x501 }, - { 0x3d400130, 0x20700 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x502 }, + { 0x3d400130, 0x20800 }, { 0x3d400134, 0xe100002 }, { 0x3d400138, 0x10d }, { 0x3d400144, 0xbb005e }, - { 0x3d400180, 0x3a5001c }, - { 0x3d400184, 0x2f071e5 }, + { 0x3d400180, 0x3a6001d }, + { 0x3d400184, 0x2f071f4 }, { 0x3d400188, 0x0 }, - { 0x3d400190, 0x49b820c }, + { 0x3d400190, 0x4a3820e }, { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x1b0c }, + { 0x3d4001b4, 0x230e }, { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x1 }, + { 0x3d4001c0, 0x7 }, { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x810191a }, + { 0x3d4000f4, 0x799 }, + { 0x3d400108, 0x9141c1c }, +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + { 0x3d400200, 0x14 }, +#else { 0x3d400200, 0x17 }, +#endif + { 0x3d400208, 0x0 }, +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + { 0x3d40020c, 0x14141400 }, +#else { 0x3d40020c, 0x0 }, +#endif { 0x3d400210, 0x1f1f }, +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + { 0x3d400204, 0x50505 }, + { 0x3d400214, 0x4040404 }, + { 0x3d400218, 0x4040404 }, +#else { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x7070707 }, +#endif { 0x3d40021c, 0xf0f }, { 0x3d400250, 0x1705 }, { 0x3d400254, 0x2c }, @@ -78,7 +97,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402050, 0x20d000 }, { 0x3d402064, 0xc001c }, { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x330000 }, + { 0x3d4020e0, 0xf30000 }, { 0x3d4020e8, 0x660048 }, { 0x3d4020ec, 0x160048 }, { 0x3d402100, 0xa040305 }, @@ -88,7 +107,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402110, 0x2040202 }, { 0x3d402114, 0x2030202 }, { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x301 }, + { 0x3d40211c, 0x302 }, { 0x3d402130, 0x20300 }, { 0x3d402134, 0xa100002 }, { 0x3d402138, 0x1d }, @@ -97,13 +116,13 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402190, 0x3818200 }, { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0xc99 }, + { 0x3d4020f4, 0x599 }, { 0x3d403020, 0x1001 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x30007 }, { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x330000 }, + { 0x3d4030e0, 0xf30000 }, { 0x3d4030e8, 0x660048 }, { 0x3d4030ec, 0x160048 }, { 0x3d403100, 0xa010102 }, @@ -113,7 +132,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d403110, 0x2040202 }, { 0x3d403114, 0x2030202 }, { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x301 }, + { 0x3d40311c, 0x302 }, { 0x3d403130, 0x20300 }, { 0x3d403134, 0xa100002 }, { 0x3d403138, 0x8 }, @@ -122,7 +141,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d403190, 0x3818200 }, { 0x3d403194, 0x80303 }, { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0xc99 }, + { 0x3d4030f4, 0x599 }, { 0x3d400028, 0x0 }, }; @@ -260,16 +279,16 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x212149, 0xeba }, { 0x213049, 0xeba }, { 0x213149, 0xeba }, - { 0x43, 0xe7 }, - { 0x1043, 0xe7 }, - { 0x2043, 0xe7 }, - { 0x3043, 0xe7 }, - { 0x4043, 0xe7 }, - { 0x5043, 0xe7 }, - { 0x6043, 0xe7 }, - { 0x7043, 0xe7 }, - { 0x8043, 0xe7 }, - { 0x9043, 0xe7 }, + { 0x43, 0x3ff }, + { 0x1043, 0x3ff }, + { 0x2043, 0x3ff }, + { 0x3043, 0x3ff }, + { 0x4043, 0x3ff }, + { 0x5043, 0x3ff }, + { 0x6043, 0x3ff }, + { 0x7043, 0x3ff }, + { 0x8043, 0x3ff }, + { 0x9043, 0x3ff }, { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, @@ -319,19 +338,15 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x200f6, 0x0 }, { 0x200f7, 0xf000 }, { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, + { 0x2002d, 0x1 }, + { 0x12002d, 0x1 }, + { 0x22002d, 0x1 }, { 0x2007d, 0x212 }, { 0x12007d, 0x212 }, { 0x22007d, 0x212 }, { 0x2007c, 0x61 }, { 0x12007c, 0x61 }, { 0x22007c, 0x61 }, - { 0x1004a, 0x500 }, - { 0x1104a, 0x500 }, - { 0x1204a, 0x500 }, - { 0x1304a, 0x500 }, { 0x2002c, 0x0 }, }; @@ -1061,7 +1076,7 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { /* P0 message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xe94 }, + { 0x54003, 0xe96 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1070,26 +1085,26 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x5400b, 0x2 }, { 0x5400f, 0x100 }, { 0x54012, 0x310 }, - { 0x54019, 0x36e4 }, - { 0x5401a, 0x33 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x36e4 }, - { 0x54020, 0x33 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x54032, 0xe400 }, - { 0x54033, 0x3336 }, + { 0x54032, 0xf400 }, + { 0x54033, 0xf33f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xe400 }, - { 0x54039, 0x3336 }, + { 0x54038, 0xf400 }, + { 0x54039, 0xf33f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1111,25 +1126,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x5400f, 0x100 }, { 0x54012, 0x310 }, { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, + { 0x54033, 0xf300 }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, + { 0x54039, 0xf300 }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1151,25 +1166,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { { 0x5400f, 0x100 }, { 0x54012, 0x310 }, { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, + { 0x54033, 0xf300 }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, + { 0x54039, 0xf300 }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1180,7 +1195,7 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { /* P0 2D message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xe94 }, + { 0x54003, 0xe96 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1190,26 +1205,26 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x310 }, - { 0x54019, 0x36e4 }, - { 0x5401a, 0x33 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x36e4 }, - { 0x54020, 0x33 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x54032, 0xe400 }, - { 0x54033, 0x3336 }, + { 0x54032, 0xf400 }, + { 0x54033, 0xf33f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xe400 }, - { 0x54039, 0x3336 }, + { 0x54038, 0xf400 }, + { 0x54039, 0xf33f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1699,9 +1714,9 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, { 0x200be, 0x3 }, - { 0x2000b, 0x419 }, + { 0x2000b, 0x41a }, { 0x2000c, 0xe9 }, - { 0x2000d, 0x91c }, + { 0x2000d, 0x91d }, { 0x2000e, 0x2c }, { 0x12000b, 0x70 }, { 0x12000c, 0x19 }, @@ -1804,8 +1819,8 @@ static struct dram_cfg_param ddr_phy_pie[] = { static struct dram_fsp_msg ddr_dram_fsp_msg[] = { { - /* P0 3733mts 1D */ - .drate = 3733, + /* P0 3600mts 1D */ + .drate = 3600, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), @@ -1825,8 +1840,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), }, { - /* P0 3733mts 2D */ - .drate = 3733, + /* P0 3600mts 2D */ + .drate = 3600, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), @@ -1845,5 +1860,19 @@ struct dram_timing_info dmo_imx8mp_sbc_dram_timing_32_32 = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3733, 400, 100, }, + .fsp_table = { 3600, 400, 100, }, }; + +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) +void board_dram_ecc_scrub(void) +{ + ddrc_inline_ecc_scrub(0x0,0x7ffffff); + ddrc_inline_ecc_scrub(0x8000000,0xfffffff); + ddrc_inline_ecc_scrub(0x10000000,0x17ffffff); + ddrc_inline_ecc_scrub(0x18000000,0x1fffffff); + ddrc_inline_ecc_scrub(0x20000000,0x27ffffff); + ddrc_inline_ecc_scrub(0x28000000,0x2fffffff); + ddrc_inline_ecc_scrub(0x30000000,0x37ffffff); + ddrc_inline_ecc_scrub_end(0x0,0x3fffffff); +} +#endif diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c index cfc4b65e0f9..a3600c8568a 100644 --- a/board/data_modul/imx8mp_edm_sbc/spl.c +++ b/board/data_modul/imx8mp_edm_sbc/spl.c @@ -68,6 +68,11 @@ int data_modul_imx_edm_sbc_board_power_init(void) /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c); + /* DRAM Vdd1 always FPWM */ + pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d); + /* DRAM Vdd2/Vddq always FPWM */ + pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d); + /* Set LDO4 and CONFIG2 to enable the I2C level translator. */ pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59); pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 2709c9ca1eb..cdd0d0d95f6 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -54,8 +54,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SCSI_AHCI imply AHCI_PCI imply E1000 - imply NVME imply PCI + imply NVME_PCI imply PCIE_ECAM_GENERIC imply DM_RNG imply SCSI diff --git a/board/freescale/common/vsc3316_3308.h b/board/freescale/common/vsc3316_3308.h index 8d343ba4d65..9725d6d9e39 100644 --- a/board/freescale/common/vsc3316_3308.h +++ b/board/freescale/common/vsc3316_3308.h @@ -6,7 +6,6 @@ #ifndef __VSC_CROSSBAR_H_ #define __VSC_CROSSBAR_H_ -#include <common.h> #include <i2c.h> #include <errno.h> diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index 2fece3a1b09..e6033d251c5 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -3,6 +3,7 @@ * Copyright 2017 NXP */ +#include <config.h> #include <vsprintf.h> #include <linux/string.h> #include <asm/io.h> diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 048ab44c591..b47e2ec5a79 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -3,6 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ +#include <config.h> #include <vsprintf.h> #include <linux/string.h> #include <asm/io.h> diff --git a/board/gateworks/venice/lpddr4_timing_imx8mm_512mb.c b/board/gateworks/venice/lpddr4_timing_imx8mm_512mb.c deleted file mode 100644 index 8803fbfdc7d..00000000000 --- a/board/gateworks/venice/lpddr4_timing_imx8mm_512mb.c +++ /dev/null @@ -1,1849 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Generated code from MX8M_DDR_tool v3.20 using RPAv20 - * - 1x Micron MT53E128M32D2DS-046 32bit dual-channel for total of 512MiB - * - imx8mm-gw7903 - * - * Align with uboot version: - * imx_v2019.04_5.4.x and above version - * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: - * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h> - */ - -#include <linux/kernel.h> -#include <asm/arch/ddr.h> - -static struct dram_cfg_param ddr_ddrc_cfg[] = { - /** Initialize DDRC registers **/ - { 0x3d400304, 0x1 }, - { 0x3d400030, 0x1 }, - { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x203 }, - { 0x3d400024, 0x3a980 }, - { 0x3d400064, 0x5b0062 }, - { 0x3d4000d0, 0xc00305ba }, - { 0x3d4000d4, 0x940000 }, - { 0x3d4000dc, 0xd4002d }, - { 0x3d4000e0, 0x310000 }, - { 0x3d4000e8, 0x66004d }, - { 0x3d4000ec, 0x16004d }, - { 0x3d400100, 0x191e1920 }, - { 0x3d400104, 0x60630 }, - { 0x3d40010c, 0xb0b000 }, - { 0x3d400110, 0xe04080e }, - { 0x3d400114, 0x2040c0c }, - { 0x3d400118, 0x1010007 }, - { 0x3d40011c, 0x401 }, - { 0x3d400130, 0x20600 }, - { 0x3d400134, 0xc100002 }, - { 0x3d400138, 0x68 }, - { 0x3d400144, 0x96004b }, - { 0x3d400180, 0x2ee0017 }, - { 0x3d400184, 0x2605b8e }, - { 0x3d400188, 0x0 }, - { 0x3d400190, 0x497820a }, - { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x170a }, - { 0x3d4001a0, 0xe0400018 }, - { 0x3d4001a4, 0xdf00e4 }, - { 0x3d4001a8, 0x80000000 }, - { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x1 }, - { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x70e1617 }, - { 0x3d400200, 0x1f }, - { 0x3d40020c, 0x0 }, - { 0x3d400210, 0x1f1f }, - { 0x3d400204, 0x80808 }, - { 0x3d400214, 0x7070707 }, - { 0x3d400218, 0xf0f0707 }, - { 0x3d40021c, 0xf0f }, - { 0x3d400250, 0x29001701 }, - { 0x3d400254, 0x2c }, - { 0x3d40025c, 0x4000030 }, - { 0x3d400264, 0x900093e7 }, - { 0x3d40026c, 0x2005574 }, - { 0x3d400400, 0x111 }, - { 0x3d400408, 0x72ff }, - { 0x3d400494, 0x2100e07 }, - { 0x3d400498, 0x620096 }, - { 0x3d40049c, 0x1100e07 }, - { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1 }, - { 0x3d402024, 0x7d00 }, - { 0x3d402050, 0x20d040 }, - { 0x3d402064, 0xc000d }, - { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x310000 }, - { 0x3d4020e8, 0x66004d }, - { 0x3d4020ec, 0x16004d }, - { 0x3d402100, 0xa040305 }, - { 0x3d402104, 0x30407 }, - { 0x3d402108, 0x203060b }, - { 0x3d40210c, 0x505000 }, - { 0x3d402110, 0x2040202 }, - { 0x3d402114, 0x2030202 }, - { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x301 }, - { 0x3d402130, 0x20300 }, - { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0xe }, - { 0x3d402144, 0x14000a }, - { 0x3d402180, 0x640004 }, - { 0x3d402190, 0x3818200 }, - { 0x3d402194, 0x80303 }, - { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x1 }, - { 0x3d403024, 0x1f40 }, - { 0x3d403050, 0x20d040 }, - { 0x3d403064, 0x30004 }, - { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x310000 }, - { 0x3d4030e8, 0x66004d }, - { 0x3d4030ec, 0x16004d }, - { 0x3d403100, 0xa010102 }, - { 0x3d403104, 0x30404 }, - { 0x3d403108, 0x203060b }, - { 0x3d40310c, 0x505000 }, - { 0x3d403110, 0x2040202 }, - { 0x3d403114, 0x2030202 }, - { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x301 }, - { 0x3d403130, 0x20300 }, - { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x4 }, - { 0x3d403144, 0x50003 }, - { 0x3d403180, 0x190004 }, - { 0x3d403190, 0x3818200 }, - { 0x3d403194, 0x80303 }, - { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0xc99 }, - { 0x3d400028, 0x0 }, -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - { 0x100a0, 0x0 }, - { 0x100a1, 0x1 }, - { 0x100a2, 0x2 }, - { 0x100a3, 0x3 }, - { 0x100a4, 0x4 }, - { 0x100a5, 0x5 }, - { 0x100a6, 0x6 }, - { 0x100a7, 0x7 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x1 }, - { 0x110a2, 0x3 }, - { 0x110a3, 0x4 }, - { 0x110a4, 0x5 }, - { 0x110a5, 0x2 }, - { 0x110a6, 0x7 }, - { 0x110a7, 0x6 }, - { 0x120a0, 0x0 }, - { 0x120a1, 0x1 }, - { 0x120a2, 0x3 }, - { 0x120a3, 0x4 }, - { 0x120a4, 0x5 }, - { 0x120a5, 0x2 }, - { 0x120a6, 0x7 }, - { 0x120a7, 0x6 }, - { 0x130a0, 0x0 }, - { 0x130a1, 0x1 }, - { 0x130a2, 0x2 }, - { 0x130a3, 0x3 }, - { 0x130a4, 0x4 }, - { 0x130a5, 0x5 }, - { 0x130a6, 0x6 }, - { 0x130a7, 0x7 }, - { 0x1005f, 0x1ff }, - { 0x1015f, 0x1ff }, - { 0x1105f, 0x1ff }, - { 0x1115f, 0x1ff }, - { 0x1205f, 0x1ff }, - { 0x1215f, 0x1ff }, - { 0x1305f, 0x1ff }, - { 0x1315f, 0x1ff }, - { 0x11005f, 0x1ff }, - { 0x11015f, 0x1ff }, - { 0x11105f, 0x1ff }, - { 0x11115f, 0x1ff }, - { 0x11205f, 0x1ff }, - { 0x11215f, 0x1ff }, - { 0x11305f, 0x1ff }, - { 0x11315f, 0x1ff }, - { 0x21005f, 0x1ff }, - { 0x21015f, 0x1ff }, - { 0x21105f, 0x1ff }, - { 0x21115f, 0x1ff }, - { 0x21205f, 0x1ff }, - { 0x21215f, 0x1ff }, - { 0x21305f, 0x1ff }, - { 0x21315f, 0x1ff }, - { 0x55, 0x1ff }, - { 0x1055, 0x1ff }, - { 0x2055, 0x1ff }, - { 0x3055, 0x1ff }, - { 0x4055, 0x1ff }, - { 0x5055, 0x1ff }, - { 0x6055, 0x1ff }, - { 0x7055, 0x1ff }, - { 0x8055, 0x1ff }, - { 0x9055, 0x1ff }, - { 0x200c5, 0x19 }, - { 0x1200c5, 0x7 }, - { 0x2200c5, 0x7 }, - { 0x2002e, 0x2 }, - { 0x12002e, 0x2 }, - { 0x22002e, 0x2 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x20024, 0x1ab }, - { 0x2003a, 0x0 }, - { 0x120024, 0x1ab }, - { 0x2003a, 0x0 }, - { 0x220024, 0x1ab }, - { 0x2003a, 0x0 }, - { 0x20056, 0x3 }, - { 0x120056, 0x3 }, - { 0x220056, 0x3 }, - { 0x1004d, 0xe00 }, - { 0x1014d, 0xe00 }, - { 0x1104d, 0xe00 }, - { 0x1114d, 0xe00 }, - { 0x1204d, 0xe00 }, - { 0x1214d, 0xe00 }, - { 0x1304d, 0xe00 }, - { 0x1314d, 0xe00 }, - { 0x11004d, 0xe00 }, - { 0x11014d, 0xe00 }, - { 0x11104d, 0xe00 }, - { 0x11114d, 0xe00 }, - { 0x11204d, 0xe00 }, - { 0x11214d, 0xe00 }, - { 0x11304d, 0xe00 }, - { 0x11314d, 0xe00 }, - { 0x21004d, 0xe00 }, - { 0x21014d, 0xe00 }, - { 0x21104d, 0xe00 }, - { 0x21114d, 0xe00 }, - { 0x21204d, 0xe00 }, - { 0x21214d, 0xe00 }, - { 0x21304d, 0xe00 }, - { 0x21314d, 0xe00 }, - { 0x10049, 0xeba }, - { 0x10149, 0xeba }, - { 0x11049, 0xeba }, - { 0x11149, 0xeba }, - { 0x12049, 0xeba }, - { 0x12149, 0xeba }, - { 0x13049, 0xeba }, - { 0x13149, 0xeba }, - { 0x110049, 0xeba }, - { 0x110149, 0xeba }, - { 0x111049, 0xeba }, - { 0x111149, 0xeba }, - { 0x112049, 0xeba }, - { 0x112149, 0xeba }, - { 0x113049, 0xeba }, - { 0x113149, 0xeba }, - { 0x210049, 0xeba }, - { 0x210149, 0xeba }, - { 0x211049, 0xeba }, - { 0x211149, 0xeba }, - { 0x212049, 0xeba }, - { 0x212149, 0xeba }, - { 0x213049, 0xeba }, - { 0x213149, 0xeba }, - { 0x43, 0x63 }, - { 0x1043, 0x63 }, - { 0x2043, 0x63 }, - { 0x3043, 0x63 }, - { 0x4043, 0x63 }, - { 0x5043, 0x63 }, - { 0x6043, 0x63 }, - { 0x7043, 0x63 }, - { 0x8043, 0x63 }, - { 0x9043, 0x63 }, - { 0x20018, 0x3 }, - { 0x20075, 0x4 }, - { 0x20050, 0x0 }, - { 0x20008, 0x2ee }, - { 0x120008, 0x64 }, - { 0x220008, 0x19 }, - { 0x20088, 0x9 }, - { 0x200b2, 0xdc }, - { 0x10043, 0x5a1 }, - { 0x10143, 0x5a1 }, - { 0x11043, 0x5a1 }, - { 0x11143, 0x5a1 }, - { 0x12043, 0x5a1 }, - { 0x12143, 0x5a1 }, - { 0x13043, 0x5a1 }, - { 0x13143, 0x5a1 }, - { 0x1200b2, 0xdc }, - { 0x110043, 0x5a1 }, - { 0x110143, 0x5a1 }, - { 0x111043, 0x5a1 }, - { 0x111143, 0x5a1 }, - { 0x112043, 0x5a1 }, - { 0x112143, 0x5a1 }, - { 0x113043, 0x5a1 }, - { 0x113143, 0x5a1 }, - { 0x2200b2, 0xdc }, - { 0x210043, 0x5a1 }, - { 0x210143, 0x5a1 }, - { 0x211043, 0x5a1 }, - { 0x211143, 0x5a1 }, - { 0x212043, 0x5a1 }, - { 0x212143, 0x5a1 }, - { 0x213043, 0x5a1 }, - { 0x213143, 0x5a1 }, - { 0x200fa, 0x1 }, - { 0x1200fa, 0x1 }, - { 0x2200fa, 0x1 }, - { 0x20019, 0x1 }, - { 0x120019, 0x1 }, - { 0x220019, 0x1 }, - { 0x200f0, 0x660 }, - { 0x200f1, 0x0 }, - { 0x200f2, 0x4444 }, - { 0x200f3, 0x8888 }, - { 0x200f4, 0x5665 }, - { 0x200f5, 0x0 }, - { 0x200f6, 0x0 }, - { 0x200f7, 0xf000 }, - { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, - { 0x200c7, 0x21 }, - { 0x1200c7, 0x21 }, - { 0x2200c7, 0x21 }, - { 0x200ca, 0x24 }, - { 0x1200ca, 0x24 }, - { 0x2200ca, 0x24 }, -}; - -/* ddr phy trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - { 0x200b2, 0x0 }, - { 0x1200b2, 0x0 }, - { 0x2200b2, 0x0 }, - { 0x200cb, 0x0 }, - { 0x10043, 0x0 }, - { 0x110043, 0x0 }, - { 0x210043, 0x0 }, - { 0x10143, 0x0 }, - { 0x110143, 0x0 }, - { 0x210143, 0x0 }, - { 0x11043, 0x0 }, - { 0x111043, 0x0 }, - { 0x211043, 0x0 }, - { 0x11143, 0x0 }, - { 0x111143, 0x0 }, - { 0x211143, 0x0 }, - { 0x12043, 0x0 }, - { 0x112043, 0x0 }, - { 0x212043, 0x0 }, - { 0x12143, 0x0 }, - { 0x112143, 0x0 }, - { 0x212143, 0x0 }, - { 0x13043, 0x0 }, - { 0x113043, 0x0 }, - { 0x213043, 0x0 }, - { 0x13143, 0x0 }, - { 0x113143, 0x0 }, - { 0x213143, 0x0 }, - { 0x80, 0x0 }, - { 0x100080, 0x0 }, - { 0x200080, 0x0 }, - { 0x1080, 0x0 }, - { 0x101080, 0x0 }, - { 0x201080, 0x0 }, - { 0x2080, 0x0 }, - { 0x102080, 0x0 }, - { 0x202080, 0x0 }, - { 0x3080, 0x0 }, - { 0x103080, 0x0 }, - { 0x203080, 0x0 }, - { 0x4080, 0x0 }, - { 0x104080, 0x0 }, - { 0x204080, 0x0 }, - { 0x5080, 0x0 }, - { 0x105080, 0x0 }, - { 0x205080, 0x0 }, - { 0x6080, 0x0 }, - { 0x106080, 0x0 }, - { 0x206080, 0x0 }, - { 0x7080, 0x0 }, - { 0x107080, 0x0 }, - { 0x207080, 0x0 }, - { 0x8080, 0x0 }, - { 0x108080, 0x0 }, - { 0x208080, 0x0 }, - { 0x9080, 0x0 }, - { 0x109080, 0x0 }, - { 0x209080, 0x0 }, - { 0x10080, 0x0 }, - { 0x110080, 0x0 }, - { 0x210080, 0x0 }, - { 0x10180, 0x0 }, - { 0x110180, 0x0 }, - { 0x210180, 0x0 }, - { 0x11080, 0x0 }, - { 0x111080, 0x0 }, - { 0x211080, 0x0 }, - { 0x11180, 0x0 }, - { 0x111180, 0x0 }, - { 0x211180, 0x0 }, - { 0x12080, 0x0 }, - { 0x112080, 0x0 }, - { 0x212080, 0x0 }, - { 0x12180, 0x0 }, - { 0x112180, 0x0 }, - { 0x212180, 0x0 }, - { 0x13080, 0x0 }, - { 0x113080, 0x0 }, - { 0x213080, 0x0 }, - { 0x13180, 0x0 }, - { 0x113180, 0x0 }, - { 0x213180, 0x0 }, - { 0x10081, 0x0 }, - { 0x110081, 0x0 }, - { 0x210081, 0x0 }, - { 0x10181, 0x0 }, - { 0x110181, 0x0 }, - { 0x210181, 0x0 }, - { 0x11081, 0x0 }, - { 0x111081, 0x0 }, - { 0x211081, 0x0 }, - { 0x11181, 0x0 }, - { 0x111181, 0x0 }, - { 0x211181, 0x0 }, - { 0x12081, 0x0 }, - { 0x112081, 0x0 }, - { 0x212081, 0x0 }, - { 0x12181, 0x0 }, - { 0x112181, 0x0 }, - { 0x212181, 0x0 }, - { 0x13081, 0x0 }, - { 0x113081, 0x0 }, - { 0x213081, 0x0 }, - { 0x13181, 0x0 }, - { 0x113181, 0x0 }, - { 0x213181, 0x0 }, - { 0x100d0, 0x0 }, - { 0x1100d0, 0x0 }, - { 0x2100d0, 0x0 }, - { 0x101d0, 0x0 }, - { 0x1101d0, 0x0 }, - { 0x2101d0, 0x0 }, - { 0x110d0, 0x0 }, - { 0x1110d0, 0x0 }, - { 0x2110d0, 0x0 }, - { 0x111d0, 0x0 }, - { 0x1111d0, 0x0 }, - { 0x2111d0, 0x0 }, - { 0x120d0, 0x0 }, - { 0x1120d0, 0x0 }, - { 0x2120d0, 0x0 }, - { 0x121d0, 0x0 }, - { 0x1121d0, 0x0 }, - { 0x2121d0, 0x0 }, - { 0x130d0, 0x0 }, - { 0x1130d0, 0x0 }, - { 0x2130d0, 0x0 }, - { 0x131d0, 0x0 }, - { 0x1131d0, 0x0 }, - { 0x2131d0, 0x0 }, - { 0x100d1, 0x0 }, - { 0x1100d1, 0x0 }, - { 0x2100d1, 0x0 }, - { 0x101d1, 0x0 }, - { 0x1101d1, 0x0 }, - { 0x2101d1, 0x0 }, - { 0x110d1, 0x0 }, - { 0x1110d1, 0x0 }, - { 0x2110d1, 0x0 }, - { 0x111d1, 0x0 }, - { 0x1111d1, 0x0 }, - { 0x2111d1, 0x0 }, - { 0x120d1, 0x0 }, - { 0x1120d1, 0x0 }, - { 0x2120d1, 0x0 }, - { 0x121d1, 0x0 }, - { 0x1121d1, 0x0 }, - { 0x2121d1, 0x0 }, - { 0x130d1, 0x0 }, - { 0x1130d1, 0x0 }, - { 0x2130d1, 0x0 }, - { 0x131d1, 0x0 }, - { 0x1131d1, 0x0 }, - { 0x2131d1, 0x0 }, - { 0x10068, 0x0 }, - { 0x10168, 0x0 }, - { 0x10268, 0x0 }, - { 0x10368, 0x0 }, - { 0x10468, 0x0 }, - { 0x10568, 0x0 }, - { 0x10668, 0x0 }, - { 0x10768, 0x0 }, - { 0x10868, 0x0 }, - { 0x11068, 0x0 }, - { 0x11168, 0x0 }, - { 0x11268, 0x0 }, - { 0x11368, 0x0 }, - { 0x11468, 0x0 }, - { 0x11568, 0x0 }, - { 0x11668, 0x0 }, - { 0x11768, 0x0 }, - { 0x11868, 0x0 }, - { 0x12068, 0x0 }, - { 0x12168, 0x0 }, - { 0x12268, 0x0 }, - { 0x12368, 0x0 }, - { 0x12468, 0x0 }, - { 0x12568, 0x0 }, - { 0x12668, 0x0 }, - { 0x12768, 0x0 }, - { 0x12868, 0x0 }, - { 0x13068, 0x0 }, - { 0x13168, 0x0 }, - { 0x13268, 0x0 }, - { 0x13368, 0x0 }, - { 0x13468, 0x0 }, - { 0x13568, 0x0 }, - { 0x13668, 0x0 }, - { 0x13768, 0x0 }, - { 0x13868, 0x0 }, - { 0x10069, 0x0 }, - { 0x10169, 0x0 }, - { 0x10269, 0x0 }, - { 0x10369, 0x0 }, - { 0x10469, 0x0 }, - { 0x10569, 0x0 }, - { 0x10669, 0x0 }, - { 0x10769, 0x0 }, - { 0x10869, 0x0 }, - { 0x11069, 0x0 }, - { 0x11169, 0x0 }, - { 0x11269, 0x0 }, - { 0x11369, 0x0 }, - { 0x11469, 0x0 }, - { 0x11569, 0x0 }, - { 0x11669, 0x0 }, - { 0x11769, 0x0 }, - { 0x11869, 0x0 }, - { 0x12069, 0x0 }, - { 0x12169, 0x0 }, - { 0x12269, 0x0 }, - { 0x12369, 0x0 }, - { 0x12469, 0x0 }, - { 0x12569, 0x0 }, - { 0x12669, 0x0 }, - { 0x12769, 0x0 }, - { 0x12869, 0x0 }, - { 0x13069, 0x0 }, - { 0x13169, 0x0 }, - { 0x13269, 0x0 }, - { 0x13369, 0x0 }, - { 0x13469, 0x0 }, - { 0x13569, 0x0 }, - { 0x13669, 0x0 }, - { 0x13769, 0x0 }, - { 0x13869, 0x0 }, - { 0x1008c, 0x0 }, - { 0x11008c, 0x0 }, - { 0x21008c, 0x0 }, - { 0x1018c, 0x0 }, - { 0x11018c, 0x0 }, - { 0x21018c, 0x0 }, - { 0x1108c, 0x0 }, - { 0x11108c, 0x0 }, - { 0x21108c, 0x0 }, - { 0x1118c, 0x0 }, - { 0x11118c, 0x0 }, - { 0x21118c, 0x0 }, - { 0x1208c, 0x0 }, - { 0x11208c, 0x0 }, - { 0x21208c, 0x0 }, - { 0x1218c, 0x0 }, - { 0x11218c, 0x0 }, - { 0x21218c, 0x0 }, - { 0x1308c, 0x0 }, - { 0x11308c, 0x0 }, - { 0x21308c, 0x0 }, - { 0x1318c, 0x0 }, - { 0x11318c, 0x0 }, - { 0x21318c, 0x0 }, - { 0x1008d, 0x0 }, - { 0x11008d, 0x0 }, - { 0x21008d, 0x0 }, - { 0x1018d, 0x0 }, - { 0x11018d, 0x0 }, - { 0x21018d, 0x0 }, - { 0x1108d, 0x0 }, - { 0x11108d, 0x0 }, - { 0x21108d, 0x0 }, - { 0x1118d, 0x0 }, - { 0x11118d, 0x0 }, - { 0x21118d, 0x0 }, - { 0x1208d, 0x0 }, - { 0x11208d, 0x0 }, - { 0x21208d, 0x0 }, - { 0x1218d, 0x0 }, - { 0x11218d, 0x0 }, - { 0x21218d, 0x0 }, - { 0x1308d, 0x0 }, - { 0x11308d, 0x0 }, - { 0x21308d, 0x0 }, - { 0x1318d, 0x0 }, - { 0x11318d, 0x0 }, - { 0x21318d, 0x0 }, - { 0x100c0, 0x0 }, - { 0x1100c0, 0x0 }, - { 0x2100c0, 0x0 }, - { 0x101c0, 0x0 }, - { 0x1101c0, 0x0 }, - { 0x2101c0, 0x0 }, - { 0x102c0, 0x0 }, - { 0x1102c0, 0x0 }, - { 0x2102c0, 0x0 }, - { 0x103c0, 0x0 }, - { 0x1103c0, 0x0 }, - { 0x2103c0, 0x0 }, - { 0x104c0, 0x0 }, - { 0x1104c0, 0x0 }, - { 0x2104c0, 0x0 }, - { 0x105c0, 0x0 }, - { 0x1105c0, 0x0 }, - { 0x2105c0, 0x0 }, - { 0x106c0, 0x0 }, - { 0x1106c0, 0x0 }, - { 0x2106c0, 0x0 }, - { 0x107c0, 0x0 }, - { 0x1107c0, 0x0 }, - { 0x2107c0, 0x0 }, - { 0x108c0, 0x0 }, - { 0x1108c0, 0x0 }, - { 0x2108c0, 0x0 }, - { 0x110c0, 0x0 }, - { 0x1110c0, 0x0 }, - { 0x2110c0, 0x0 }, - { 0x111c0, 0x0 }, - { 0x1111c0, 0x0 }, - { 0x2111c0, 0x0 }, - { 0x112c0, 0x0 }, - { 0x1112c0, 0x0 }, - { 0x2112c0, 0x0 }, - { 0x113c0, 0x0 }, - { 0x1113c0, 0x0 }, - { 0x2113c0, 0x0 }, - { 0x114c0, 0x0 }, - { 0x1114c0, 0x0 }, - { 0x2114c0, 0x0 }, - { 0x115c0, 0x0 }, - { 0x1115c0, 0x0 }, - { 0x2115c0, 0x0 }, - { 0x116c0, 0x0 }, - { 0x1116c0, 0x0 }, - { 0x2116c0, 0x0 }, - { 0x117c0, 0x0 }, - { 0x1117c0, 0x0 }, - { 0x2117c0, 0x0 }, - { 0x118c0, 0x0 }, - { 0x1118c0, 0x0 }, - { 0x2118c0, 0x0 }, - { 0x120c0, 0x0 }, - { 0x1120c0, 0x0 }, - { 0x2120c0, 0x0 }, - { 0x121c0, 0x0 }, - { 0x1121c0, 0x0 }, - { 0x2121c0, 0x0 }, - { 0x122c0, 0x0 }, - { 0x1122c0, 0x0 }, - { 0x2122c0, 0x0 }, - { 0x123c0, 0x0 }, - { 0x1123c0, 0x0 }, - { 0x2123c0, 0x0 }, - { 0x124c0, 0x0 }, - { 0x1124c0, 0x0 }, - { 0x2124c0, 0x0 }, - { 0x125c0, 0x0 }, - { 0x1125c0, 0x0 }, - { 0x2125c0, 0x0 }, - { 0x126c0, 0x0 }, - { 0x1126c0, 0x0 }, - { 0x2126c0, 0x0 }, - { 0x127c0, 0x0 }, - { 0x1127c0, 0x0 }, - { 0x2127c0, 0x0 }, - { 0x128c0, 0x0 }, - { 0x1128c0, 0x0 }, - { 0x2128c0, 0x0 }, - { 0x130c0, 0x0 }, - { 0x1130c0, 0x0 }, - { 0x2130c0, 0x0 }, - { 0x131c0, 0x0 }, - { 0x1131c0, 0x0 }, - { 0x2131c0, 0x0 }, - { 0x132c0, 0x0 }, - { 0x1132c0, 0x0 }, - { 0x2132c0, 0x0 }, - { 0x133c0, 0x0 }, - { 0x1133c0, 0x0 }, - { 0x2133c0, 0x0 }, - { 0x134c0, 0x0 }, - { 0x1134c0, 0x0 }, - { 0x2134c0, 0x0 }, - { 0x135c0, 0x0 }, - { 0x1135c0, 0x0 }, - { 0x2135c0, 0x0 }, - { 0x136c0, 0x0 }, - { 0x1136c0, 0x0 }, - { 0x2136c0, 0x0 }, - { 0x137c0, 0x0 }, - { 0x1137c0, 0x0 }, - { 0x2137c0, 0x0 }, - { 0x138c0, 0x0 }, - { 0x1138c0, 0x0 }, - { 0x2138c0, 0x0 }, - { 0x100c1, 0x0 }, - { 0x1100c1, 0x0 }, - { 0x2100c1, 0x0 }, - { 0x101c1, 0x0 }, - { 0x1101c1, 0x0 }, - { 0x2101c1, 0x0 }, - { 0x102c1, 0x0 }, - { 0x1102c1, 0x0 }, - { 0x2102c1, 0x0 }, - { 0x103c1, 0x0 }, - { 0x1103c1, 0x0 }, - { 0x2103c1, 0x0 }, - { 0x104c1, 0x0 }, - { 0x1104c1, 0x0 }, - { 0x2104c1, 0x0 }, - { 0x105c1, 0x0 }, - { 0x1105c1, 0x0 }, - { 0x2105c1, 0x0 }, - { 0x106c1, 0x0 }, - { 0x1106c1, 0x0 }, - { 0x2106c1, 0x0 }, - { 0x107c1, 0x0 }, - { 0x1107c1, 0x0 }, - { 0x2107c1, 0x0 }, - { 0x108c1, 0x0 }, - { 0x1108c1, 0x0 }, - { 0x2108c1, 0x0 }, - { 0x110c1, 0x0 }, - { 0x1110c1, 0x0 }, - { 0x2110c1, 0x0 }, - { 0x111c1, 0x0 }, - { 0x1111c1, 0x0 }, - { 0x2111c1, 0x0 }, - { 0x112c1, 0x0 }, - { 0x1112c1, 0x0 }, - { 0x2112c1, 0x0 }, - { 0x113c1, 0x0 }, - { 0x1113c1, 0x0 }, - { 0x2113c1, 0x0 }, - { 0x114c1, 0x0 }, - { 0x1114c1, 0x0 }, - { 0x2114c1, 0x0 }, - { 0x115c1, 0x0 }, - { 0x1115c1, 0x0 }, - { 0x2115c1, 0x0 }, - { 0x116c1, 0x0 }, - { 0x1116c1, 0x0 }, - { 0x2116c1, 0x0 }, - { 0x117c1, 0x0 }, - { 0x1117c1, 0x0 }, - { 0x2117c1, 0x0 }, - { 0x118c1, 0x0 }, - { 0x1118c1, 0x0 }, - { 0x2118c1, 0x0 }, - { 0x120c1, 0x0 }, - { 0x1120c1, 0x0 }, - { 0x2120c1, 0x0 }, - { 0x121c1, 0x0 }, - { 0x1121c1, 0x0 }, - { 0x2121c1, 0x0 }, - { 0x122c1, 0x0 }, - { 0x1122c1, 0x0 }, - { 0x2122c1, 0x0 }, - { 0x123c1, 0x0 }, - { 0x1123c1, 0x0 }, - { 0x2123c1, 0x0 }, - { 0x124c1, 0x0 }, - { 0x1124c1, 0x0 }, - { 0x2124c1, 0x0 }, - { 0x125c1, 0x0 }, - { 0x1125c1, 0x0 }, - { 0x2125c1, 0x0 }, - { 0x126c1, 0x0 }, - { 0x1126c1, 0x0 }, - { 0x2126c1, 0x0 }, - { 0x127c1, 0x0 }, - { 0x1127c1, 0x0 }, - { 0x2127c1, 0x0 }, - { 0x128c1, 0x0 }, - { 0x1128c1, 0x0 }, - { 0x2128c1, 0x0 }, - { 0x130c1, 0x0 }, - { 0x1130c1, 0x0 }, - { 0x2130c1, 0x0 }, - { 0x131c1, 0x0 }, - { 0x1131c1, 0x0 }, - { 0x2131c1, 0x0 }, - { 0x132c1, 0x0 }, - { 0x1132c1, 0x0 }, - { 0x2132c1, 0x0 }, - { 0x133c1, 0x0 }, - { 0x1133c1, 0x0 }, - { 0x2133c1, 0x0 }, - { 0x134c1, 0x0 }, - { 0x1134c1, 0x0 }, - { 0x2134c1, 0x0 }, - { 0x135c1, 0x0 }, - { 0x1135c1, 0x0 }, - { 0x2135c1, 0x0 }, - { 0x136c1, 0x0 }, - { 0x1136c1, 0x0 }, - { 0x2136c1, 0x0 }, - { 0x137c1, 0x0 }, - { 0x1137c1, 0x0 }, - { 0x2137c1, 0x0 }, - { 0x138c1, 0x0 }, - { 0x1138c1, 0x0 }, - { 0x2138c1, 0x0 }, - { 0x10020, 0x0 }, - { 0x110020, 0x0 }, - { 0x210020, 0x0 }, - { 0x11020, 0x0 }, - { 0x111020, 0x0 }, - { 0x211020, 0x0 }, - { 0x12020, 0x0 }, - { 0x112020, 0x0 }, - { 0x212020, 0x0 }, - { 0x13020, 0x0 }, - { 0x113020, 0x0 }, - { 0x213020, 0x0 }, - { 0x20072, 0x0 }, - { 0x20073, 0x0 }, - { 0x20074, 0x0 }, - { 0x100aa, 0x0 }, - { 0x110aa, 0x0 }, - { 0x120aa, 0x0 }, - { 0x130aa, 0x0 }, - { 0x20010, 0x0 }, - { 0x120010, 0x0 }, - { 0x220010, 0x0 }, - { 0x20011, 0x0 }, - { 0x120011, 0x0 }, - { 0x220011, 0x0 }, - { 0x100ae, 0x0 }, - { 0x1100ae, 0x0 }, - { 0x2100ae, 0x0 }, - { 0x100af, 0x0 }, - { 0x1100af, 0x0 }, - { 0x2100af, 0x0 }, - { 0x110ae, 0x0 }, - { 0x1110ae, 0x0 }, - { 0x2110ae, 0x0 }, - { 0x110af, 0x0 }, - { 0x1110af, 0x0 }, - { 0x2110af, 0x0 }, - { 0x120ae, 0x0 }, - { 0x1120ae, 0x0 }, - { 0x2120ae, 0x0 }, - { 0x120af, 0x0 }, - { 0x1120af, 0x0 }, - { 0x2120af, 0x0 }, - { 0x130ae, 0x0 }, - { 0x1130ae, 0x0 }, - { 0x2130ae, 0x0 }, - { 0x130af, 0x0 }, - { 0x1130af, 0x0 }, - { 0x2130af, 0x0 }, - { 0x20020, 0x0 }, - { 0x120020, 0x0 }, - { 0x220020, 0x0 }, - { 0x100a0, 0x0 }, - { 0x100a1, 0x0 }, - { 0x100a2, 0x0 }, - { 0x100a3, 0x0 }, - { 0x100a4, 0x0 }, - { 0x100a5, 0x0 }, - { 0x100a6, 0x0 }, - { 0x100a7, 0x0 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x0 }, - { 0x110a2, 0x0 }, - { 0x110a3, 0x0 }, - { 0x110a4, 0x0 }, - { 0x110a5, 0x0 }, - { 0x110a6, 0x0 }, - { 0x110a7, 0x0 }, - { 0x120a0, 0x0 }, - { 0x120a1, 0x0 }, - { 0x120a2, 0x0 }, - { 0x120a3, 0x0 }, - { 0x120a4, 0x0 }, - { 0x120a5, 0x0 }, - { 0x120a6, 0x0 }, - { 0x120a7, 0x0 }, - { 0x130a0, 0x0 }, - { 0x130a1, 0x0 }, - { 0x130a2, 0x0 }, - { 0x130a3, 0x0 }, - { 0x130a4, 0x0 }, - { 0x130a5, 0x0 }, - { 0x130a6, 0x0 }, - { 0x130a7, 0x0 }, - { 0x2007c, 0x0 }, - { 0x12007c, 0x0 }, - { 0x22007c, 0x0 }, - { 0x2007d, 0x0 }, - { 0x12007d, 0x0 }, - { 0x22007d, 0x0 }, - { 0x400fd, 0x0 }, - { 0x400c0, 0x0 }, - { 0x90201, 0x0 }, - { 0x190201, 0x0 }, - { 0x290201, 0x0 }, - { 0x90202, 0x0 }, - { 0x190202, 0x0 }, - { 0x290202, 0x0 }, - { 0x90203, 0x0 }, - { 0x190203, 0x0 }, - { 0x290203, 0x0 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x90205, 0x0 }, - { 0x190205, 0x0 }, - { 0x290205, 0x0 }, - { 0x90206, 0x0 }, - { 0x190206, 0x0 }, - { 0x290206, 0x0 }, - { 0x90207, 0x0 }, - { 0x190207, 0x0 }, - { 0x290207, 0x0 }, - { 0x90208, 0x0 }, - { 0x190208, 0x0 }, - { 0x290208, 0x0 }, - { 0x10062, 0x0 }, - { 0x10162, 0x0 }, - { 0x10262, 0x0 }, - { 0x10362, 0x0 }, - { 0x10462, 0x0 }, - { 0x10562, 0x0 }, - { 0x10662, 0x0 }, - { 0x10762, 0x0 }, - { 0x10862, 0x0 }, - { 0x11062, 0x0 }, - { 0x11162, 0x0 }, - { 0x11262, 0x0 }, - { 0x11362, 0x0 }, - { 0x11462, 0x0 }, - { 0x11562, 0x0 }, - { 0x11662, 0x0 }, - { 0x11762, 0x0 }, - { 0x11862, 0x0 }, - { 0x12062, 0x0 }, - { 0x12162, 0x0 }, - { 0x12262, 0x0 }, - { 0x12362, 0x0 }, - { 0x12462, 0x0 }, - { 0x12562, 0x0 }, - { 0x12662, 0x0 }, - { 0x12762, 0x0 }, - { 0x12862, 0x0 }, - { 0x13062, 0x0 }, - { 0x13162, 0x0 }, - { 0x13262, 0x0 }, - { 0x13362, 0x0 }, - { 0x13462, 0x0 }, - { 0x13562, 0x0 }, - { 0x13662, 0x0 }, - { 0x13762, 0x0 }, - { 0x13862, 0x0 }, - { 0x20077, 0x0 }, - { 0x10001, 0x0 }, - { 0x11001, 0x0 }, - { 0x12001, 0x0 }, - { 0x13001, 0x0 }, - { 0x10040, 0x0 }, - { 0x10140, 0x0 }, - { 0x10240, 0x0 }, - { 0x10340, 0x0 }, - { 0x10440, 0x0 }, - { 0x10540, 0x0 }, - { 0x10640, 0x0 }, - { 0x10740, 0x0 }, - { 0x10840, 0x0 }, - { 0x10030, 0x0 }, - { 0x10130, 0x0 }, - { 0x10230, 0x0 }, - { 0x10330, 0x0 }, - { 0x10430, 0x0 }, - { 0x10530, 0x0 }, - { 0x10630, 0x0 }, - { 0x10730, 0x0 }, - { 0x10830, 0x0 }, - { 0x11040, 0x0 }, - { 0x11140, 0x0 }, - { 0x11240, 0x0 }, - { 0x11340, 0x0 }, - { 0x11440, 0x0 }, - { 0x11540, 0x0 }, - { 0x11640, 0x0 }, - { 0x11740, 0x0 }, - { 0x11840, 0x0 }, - { 0x11030, 0x0 }, - { 0x11130, 0x0 }, - { 0x11230, 0x0 }, - { 0x11330, 0x0 }, - { 0x11430, 0x0 }, - { 0x11530, 0x0 }, - { 0x11630, 0x0 }, - { 0x11730, 0x0 }, - { 0x11830, 0x0 }, - { 0x12040, 0x0 }, - { 0x12140, 0x0 }, - { 0x12240, 0x0 }, - { 0x12340, 0x0 }, - { 0x12440, 0x0 }, - { 0x12540, 0x0 }, - { 0x12640, 0x0 }, - { 0x12740, 0x0 }, - { 0x12840, 0x0 }, - { 0x12030, 0x0 }, - { 0x12130, 0x0 }, - { 0x12230, 0x0 }, - { 0x12330, 0x0 }, - { 0x12430, 0x0 }, - { 0x12530, 0x0 }, - { 0x12630, 0x0 }, - { 0x12730, 0x0 }, - { 0x12830, 0x0 }, - { 0x13040, 0x0 }, - { 0x13140, 0x0 }, - { 0x13240, 0x0 }, - { 0x13340, 0x0 }, - { 0x13440, 0x0 }, - { 0x13540, 0x0 }, - { 0x13640, 0x0 }, - { 0x13740, 0x0 }, - { 0x13840, 0x0 }, - { 0x13030, 0x0 }, - { 0x13130, 0x0 }, - { 0x13230, 0x0 }, - { 0x13330, 0x0 }, - { 0x13430, 0x0 }, - { 0x13530, 0x0 }, - { 0x13630, 0x0 }, - { 0x13730, 0x0 }, - { 0x13830, 0x0 }, -}; - -/* P0 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x131f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x54012, 0x110 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P1 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x101 }, - { 0x54003, 0x190 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x54012, 0x110 }, - { 0x54019, 0x84 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0x8400 }, - { 0x54033, 0x3100 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0x3100 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P2 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x102 }, - { 0x54003, 0x64 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x54012, 0x110 }, - { 0x54019, 0x84 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0x8400 }, - { 0x54033, 0x3100 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0x3100 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P0 2D message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x61 }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54010, 0x1f7f }, - { 0x54012, 0x110 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - { 0xd0000, 0x0 }, - { 0x90000, 0x10 }, - { 0x90001, 0x400 }, - { 0x90002, 0x10e }, - { 0x90003, 0x0 }, - { 0x90004, 0x0 }, - { 0x90005, 0x8 }, - { 0x90029, 0xb }, - { 0x9002a, 0x480 }, - { 0x9002b, 0x109 }, - { 0x9002c, 0x8 }, - { 0x9002d, 0x448 }, - { 0x9002e, 0x139 }, - { 0x9002f, 0x8 }, - { 0x90030, 0x478 }, - { 0x90031, 0x109 }, - { 0x90032, 0x0 }, - { 0x90033, 0xe8 }, - { 0x90034, 0x109 }, - { 0x90035, 0x2 }, - { 0x90036, 0x10 }, - { 0x90037, 0x139 }, - { 0x90038, 0xf }, - { 0x90039, 0x7c0 }, - { 0x9003a, 0x139 }, - { 0x9003b, 0x44 }, - { 0x9003c, 0x630 }, - { 0x9003d, 0x159 }, - { 0x9003e, 0x14f }, - { 0x9003f, 0x630 }, - { 0x90040, 0x159 }, - { 0x90041, 0x47 }, - { 0x90042, 0x630 }, - { 0x90043, 0x149 }, - { 0x90044, 0x4f }, - { 0x90045, 0x630 }, - { 0x90046, 0x179 }, - { 0x90047, 0x8 }, - { 0x90048, 0xe0 }, - { 0x90049, 0x109 }, - { 0x9004a, 0x0 }, - { 0x9004b, 0x7c8 }, - { 0x9004c, 0x109 }, - { 0x9004d, 0x0 }, - { 0x9004e, 0x1 }, - { 0x9004f, 0x8 }, - { 0x90050, 0x0 }, - { 0x90051, 0x45a }, - { 0x90052, 0x9 }, - { 0x90053, 0x0 }, - { 0x90054, 0x448 }, - { 0x90055, 0x109 }, - { 0x90056, 0x40 }, - { 0x90057, 0x630 }, - { 0x90058, 0x179 }, - { 0x90059, 0x1 }, - { 0x9005a, 0x618 }, - { 0x9005b, 0x109 }, - { 0x9005c, 0x40c0 }, - { 0x9005d, 0x630 }, - { 0x9005e, 0x149 }, - { 0x9005f, 0x8 }, - { 0x90060, 0x4 }, - { 0x90061, 0x48 }, - { 0x90062, 0x4040 }, - { 0x90063, 0x630 }, - { 0x90064, 0x149 }, - { 0x90065, 0x0 }, - { 0x90066, 0x4 }, - { 0x90067, 0x48 }, - { 0x90068, 0x40 }, - { 0x90069, 0x630 }, - { 0x9006a, 0x149 }, - { 0x9006b, 0x10 }, - { 0x9006c, 0x4 }, - { 0x9006d, 0x18 }, - { 0x9006e, 0x0 }, - { 0x9006f, 0x4 }, - { 0x90070, 0x78 }, - { 0x90071, 0x549 }, - { 0x90072, 0x630 }, - { 0x90073, 0x159 }, - { 0x90074, 0xd49 }, - { 0x90075, 0x630 }, - { 0x90076, 0x159 }, - { 0x90077, 0x94a }, - { 0x90078, 0x630 }, - { 0x90079, 0x159 }, - { 0x9007a, 0x441 }, - { 0x9007b, 0x630 }, - { 0x9007c, 0x149 }, - { 0x9007d, 0x42 }, - { 0x9007e, 0x630 }, - { 0x9007f, 0x149 }, - { 0x90080, 0x1 }, - { 0x90081, 0x630 }, - { 0x90082, 0x149 }, - { 0x90083, 0x0 }, - { 0x90084, 0xe0 }, - { 0x90085, 0x109 }, - { 0x90086, 0xa }, - { 0x90087, 0x10 }, - { 0x90088, 0x109 }, - { 0x90089, 0x9 }, - { 0x9008a, 0x3c0 }, - { 0x9008b, 0x149 }, - { 0x9008c, 0x9 }, - { 0x9008d, 0x3c0 }, - { 0x9008e, 0x159 }, - { 0x9008f, 0x18 }, - { 0x90090, 0x10 }, - { 0x90091, 0x109 }, - { 0x90092, 0x0 }, - { 0x90093, 0x3c0 }, - { 0x90094, 0x109 }, - { 0x90095, 0x18 }, - { 0x90096, 0x4 }, - { 0x90097, 0x48 }, - { 0x90098, 0x18 }, - { 0x90099, 0x4 }, - { 0x9009a, 0x58 }, - { 0x9009b, 0xa }, - { 0x9009c, 0x10 }, - { 0x9009d, 0x109 }, - { 0x9009e, 0x2 }, - { 0x9009f, 0x10 }, - { 0x900a0, 0x109 }, - { 0x900a1, 0x5 }, - { 0x900a2, 0x7c0 }, - { 0x900a3, 0x109 }, - { 0x900a4, 0x10 }, - { 0x900a5, 0x10 }, - { 0x900a6, 0x109 }, - { 0x40000, 0x811 }, - { 0x40020, 0x880 }, - { 0x40040, 0x0 }, - { 0x40060, 0x0 }, - { 0x40001, 0x4008 }, - { 0x40021, 0x83 }, - { 0x40041, 0x4f }, - { 0x40061, 0x0 }, - { 0x40002, 0x4040 }, - { 0x40022, 0x83 }, - { 0x40042, 0x51 }, - { 0x40062, 0x0 }, - { 0x40003, 0x811 }, - { 0x40023, 0x880 }, - { 0x40043, 0x0 }, - { 0x40063, 0x0 }, - { 0x40004, 0x720 }, - { 0x40024, 0xf }, - { 0x40044, 0x1740 }, - { 0x40064, 0x0 }, - { 0x40005, 0x16 }, - { 0x40025, 0x83 }, - { 0x40045, 0x4b }, - { 0x40065, 0x0 }, - { 0x40006, 0x716 }, - { 0x40026, 0xf }, - { 0x40046, 0x2001 }, - { 0x40066, 0x0 }, - { 0x40007, 0x716 }, - { 0x40027, 0xf }, - { 0x40047, 0x2800 }, - { 0x40067, 0x0 }, - { 0x40008, 0x716 }, - { 0x40028, 0xf }, - { 0x40048, 0xf00 }, - { 0x40068, 0x0 }, - { 0x40009, 0x720 }, - { 0x40029, 0xf }, - { 0x40049, 0x1400 }, - { 0x40069, 0x0 }, - { 0x4000a, 0xe08 }, - { 0x4002a, 0xc15 }, - { 0x4004a, 0x0 }, - { 0x4006a, 0x0 }, - { 0x4000b, 0x623 }, - { 0x4002b, 0x15 }, - { 0x4004b, 0x0 }, - { 0x4006b, 0x0 }, - { 0x4000c, 0x4028 }, - { 0x4002c, 0x80 }, - { 0x4004c, 0x0 }, - { 0x4006c, 0x0 }, - { 0x4000d, 0xe08 }, - { 0x4002d, 0xc1a }, - { 0x4004d, 0x0 }, - { 0x4006d, 0x0 }, - { 0x4000e, 0x623 }, - { 0x4002e, 0x1a }, - { 0x4004e, 0x0 }, - { 0x4006e, 0x0 }, - { 0x4000f, 0x4040 }, - { 0x4002f, 0x80 }, - { 0x4004f, 0x0 }, - { 0x4006f, 0x0 }, - { 0x40010, 0x2604 }, - { 0x40030, 0x15 }, - { 0x40050, 0x0 }, - { 0x40070, 0x0 }, - { 0x40011, 0x708 }, - { 0x40031, 0x5 }, - { 0x40051, 0x0 }, - { 0x40071, 0x2002 }, - { 0x40012, 0x8 }, - { 0x40032, 0x80 }, - { 0x40052, 0x0 }, - { 0x40072, 0x0 }, - { 0x40013, 0x2604 }, - { 0x40033, 0x1a }, - { 0x40053, 0x0 }, - { 0x40073, 0x0 }, - { 0x40014, 0x708 }, - { 0x40034, 0xa }, - { 0x40054, 0x0 }, - { 0x40074, 0x2002 }, - { 0x40015, 0x4040 }, - { 0x40035, 0x80 }, - { 0x40055, 0x0 }, - { 0x40075, 0x0 }, - { 0x40016, 0x60a }, - { 0x40036, 0x15 }, - { 0x40056, 0x1200 }, - { 0x40076, 0x0 }, - { 0x40017, 0x61a }, - { 0x40037, 0x15 }, - { 0x40057, 0x1300 }, - { 0x40077, 0x0 }, - { 0x40018, 0x60a }, - { 0x40038, 0x1a }, - { 0x40058, 0x1200 }, - { 0x40078, 0x0 }, - { 0x40019, 0x642 }, - { 0x40039, 0x1a }, - { 0x40059, 0x1300 }, - { 0x40079, 0x0 }, - { 0x4001a, 0x4808 }, - { 0x4003a, 0x880 }, - { 0x4005a, 0x0 }, - { 0x4007a, 0x0 }, - { 0x900a7, 0x0 }, - { 0x900a8, 0x790 }, - { 0x900a9, 0x11a }, - { 0x900aa, 0x8 }, - { 0x900ab, 0x7aa }, - { 0x900ac, 0x2a }, - { 0x900ad, 0x10 }, - { 0x900ae, 0x7b2 }, - { 0x900af, 0x2a }, - { 0x900b0, 0x0 }, - { 0x900b1, 0x7c8 }, - { 0x900b2, 0x109 }, - { 0x900b3, 0x10 }, - { 0x900b4, 0x2a8 }, - { 0x900b5, 0x129 }, - { 0x900b6, 0x8 }, - { 0x900b7, 0x370 }, - { 0x900b8, 0x129 }, - { 0x900b9, 0xa }, - { 0x900ba, 0x3c8 }, - { 0x900bb, 0x1a9 }, - { 0x900bc, 0xc }, - { 0x900bd, 0x408 }, - { 0x900be, 0x199 }, - { 0x900bf, 0x14 }, - { 0x900c0, 0x790 }, - { 0x900c1, 0x11a }, - { 0x900c2, 0x8 }, - { 0x900c3, 0x4 }, - { 0x900c4, 0x18 }, - { 0x900c5, 0xe }, - { 0x900c6, 0x408 }, - { 0x900c7, 0x199 }, - { 0x900c8, 0x8 }, - { 0x900c9, 0x8568 }, - { 0x900ca, 0x108 }, - { 0x900cb, 0x18 }, - { 0x900cc, 0x790 }, - { 0x900cd, 0x16a }, - { 0x900ce, 0x8 }, - { 0x900cf, 0x1d8 }, - { 0x900d0, 0x169 }, - { 0x900d1, 0x10 }, - { 0x900d2, 0x8558 }, - { 0x900d3, 0x168 }, - { 0x900d4, 0x70 }, - { 0x900d5, 0x788 }, - { 0x900d6, 0x16a }, - { 0x900d7, 0x1ff8 }, - { 0x900d8, 0x85a8 }, - { 0x900d9, 0x1e8 }, - { 0x900da, 0x50 }, - { 0x900db, 0x798 }, - { 0x900dc, 0x16a }, - { 0x900dd, 0x60 }, - { 0x900de, 0x7a0 }, - { 0x900df, 0x16a }, - { 0x900e0, 0x8 }, - { 0x900e1, 0x8310 }, - { 0x900e2, 0x168 }, - { 0x900e3, 0x8 }, - { 0x900e4, 0xa310 }, - { 0x900e5, 0x168 }, - { 0x900e6, 0xa }, - { 0x900e7, 0x408 }, - { 0x900e8, 0x169 }, - { 0x900e9, 0x6e }, - { 0x900ea, 0x0 }, - { 0x900eb, 0x68 }, - { 0x900ec, 0x0 }, - { 0x900ed, 0x408 }, - { 0x900ee, 0x169 }, - { 0x900ef, 0x0 }, - { 0x900f0, 0x8310 }, - { 0x900f1, 0x168 }, - { 0x900f2, 0x0 }, - { 0x900f3, 0xa310 }, - { 0x900f4, 0x168 }, - { 0x900f5, 0x1ff8 }, - { 0x900f6, 0x85a8 }, - { 0x900f7, 0x1e8 }, - { 0x900f8, 0x68 }, - { 0x900f9, 0x798 }, - { 0x900fa, 0x16a }, - { 0x900fb, 0x78 }, - { 0x900fc, 0x7a0 }, - { 0x900fd, 0x16a }, - { 0x900fe, 0x68 }, - { 0x900ff, 0x790 }, - { 0x90100, 0x16a }, - { 0x90101, 0x8 }, - { 0x90102, 0x8b10 }, - { 0x90103, 0x168 }, - { 0x90104, 0x8 }, - { 0x90105, 0xab10 }, - { 0x90106, 0x168 }, - { 0x90107, 0xa }, - { 0x90108, 0x408 }, - { 0x90109, 0x169 }, - { 0x9010a, 0x58 }, - { 0x9010b, 0x0 }, - { 0x9010c, 0x68 }, - { 0x9010d, 0x0 }, - { 0x9010e, 0x408 }, - { 0x9010f, 0x169 }, - { 0x90110, 0x0 }, - { 0x90111, 0x8b10 }, - { 0x90112, 0x168 }, - { 0x90113, 0x0 }, - { 0x90114, 0xab10 }, - { 0x90115, 0x168 }, - { 0x90116, 0x0 }, - { 0x90117, 0x1d8 }, - { 0x90118, 0x169 }, - { 0x90119, 0x80 }, - { 0x9011a, 0x790 }, - { 0x9011b, 0x16a }, - { 0x9011c, 0x18 }, - { 0x9011d, 0x7aa }, - { 0x9011e, 0x6a }, - { 0x9011f, 0xa }, - { 0x90120, 0x0 }, - { 0x90121, 0x1e9 }, - { 0x90122, 0x8 }, - { 0x90123, 0x8080 }, - { 0x90124, 0x108 }, - { 0x90125, 0xf }, - { 0x90126, 0x408 }, - { 0x90127, 0x169 }, - { 0x90128, 0xc }, - { 0x90129, 0x0 }, - { 0x9012a, 0x68 }, - { 0x9012b, 0x9 }, - { 0x9012c, 0x0 }, - { 0x9012d, 0x1a9 }, - { 0x9012e, 0x0 }, - { 0x9012f, 0x408 }, - { 0x90130, 0x169 }, - { 0x90131, 0x0 }, - { 0x90132, 0x8080 }, - { 0x90133, 0x108 }, - { 0x90134, 0x8 }, - { 0x90135, 0x7aa }, - { 0x90136, 0x6a }, - { 0x90137, 0x0 }, - { 0x90138, 0x8568 }, - { 0x90139, 0x108 }, - { 0x9013a, 0xb7 }, - { 0x9013b, 0x790 }, - { 0x9013c, 0x16a }, - { 0x9013d, 0x1f }, - { 0x9013e, 0x0 }, - { 0x9013f, 0x68 }, - { 0x90140, 0x8 }, - { 0x90141, 0x8558 }, - { 0x90142, 0x168 }, - { 0x90143, 0xf }, - { 0x90144, 0x408 }, - { 0x90145, 0x169 }, - { 0x90146, 0xc }, - { 0x90147, 0x0 }, - { 0x90148, 0x68 }, - { 0x90149, 0x0 }, - { 0x9014a, 0x408 }, - { 0x9014b, 0x169 }, - { 0x9014c, 0x0 }, - { 0x9014d, 0x8558 }, - { 0x9014e, 0x168 }, - { 0x9014f, 0x8 }, - { 0x90150, 0x3c8 }, - { 0x90151, 0x1a9 }, - { 0x90152, 0x3 }, - { 0x90153, 0x370 }, - { 0x90154, 0x129 }, - { 0x90155, 0x20 }, - { 0x90156, 0x2aa }, - { 0x90157, 0x9 }, - { 0x90158, 0x0 }, - { 0x90159, 0x400 }, - { 0x9015a, 0x10e }, - { 0x9015b, 0x8 }, - { 0x9015c, 0xe8 }, - { 0x9015d, 0x109 }, - { 0x9015e, 0x0 }, - { 0x9015f, 0x8140 }, - { 0x90160, 0x10c }, - { 0x90161, 0x10 }, - { 0x90162, 0x8138 }, - { 0x90163, 0x10c }, - { 0x90164, 0x8 }, - { 0x90165, 0x7c8 }, - { 0x90166, 0x101 }, - { 0x90167, 0x8 }, - { 0x90168, 0x0 }, - { 0x90169, 0x8 }, - { 0x9016a, 0x8 }, - { 0x9016b, 0x448 }, - { 0x9016c, 0x109 }, - { 0x9016d, 0xf }, - { 0x9016e, 0x7c0 }, - { 0x9016f, 0x109 }, - { 0x90170, 0x0 }, - { 0x90171, 0xe8 }, - { 0x90172, 0x109 }, - { 0x90173, 0x47 }, - { 0x90174, 0x630 }, - { 0x90175, 0x109 }, - { 0x90176, 0x8 }, - { 0x90177, 0x618 }, - { 0x90178, 0x109 }, - { 0x90179, 0x8 }, - { 0x9017a, 0xe0 }, - { 0x9017b, 0x109 }, - { 0x9017c, 0x0 }, - { 0x9017d, 0x7c8 }, - { 0x9017e, 0x109 }, - { 0x9017f, 0x8 }, - { 0x90180, 0x8140 }, - { 0x90181, 0x10c }, - { 0x90182, 0x0 }, - { 0x90183, 0x1 }, - { 0x90184, 0x8 }, - { 0x90185, 0x8 }, - { 0x90186, 0x4 }, - { 0x90187, 0x8 }, - { 0x90188, 0x8 }, - { 0x90189, 0x7c8 }, - { 0x9018a, 0x101 }, - { 0x90006, 0x0 }, - { 0x90007, 0x0 }, - { 0x90008, 0x8 }, - { 0x90009, 0x0 }, - { 0x9000a, 0x0 }, - { 0x9000b, 0x0 }, - { 0xd00e7, 0x400 }, - { 0x90017, 0x0 }, - { 0x9001f, 0x2a }, - { 0x90026, 0x6a }, - { 0x400d0, 0x0 }, - { 0x400d1, 0x101 }, - { 0x400d2, 0x105 }, - { 0x400d3, 0x107 }, - { 0x400d4, 0x10f }, - { 0x400d5, 0x202 }, - { 0x400d6, 0x20a }, - { 0x400d7, 0x20b }, - { 0x2003a, 0x2 }, - { 0x2000b, 0x5d }, - { 0x2000c, 0xbb }, - { 0x2000d, 0x753 }, - { 0x2000e, 0x2c }, - { 0x12000b, 0xc }, - { 0x12000c, 0x19 }, - { 0x12000d, 0xfa }, - { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, - { 0x22000c, 0x6 }, - { 0x22000d, 0x3e }, - { 0x22000e, 0x10 }, - { 0x9000c, 0x0 }, - { 0x9000d, 0x173 }, - { 0x9000e, 0x60 }, - { 0x9000f, 0x6110 }, - { 0x90010, 0x2152 }, - { 0x90011, 0xdfbd }, - { 0x90012, 0x60 }, - { 0x90013, 0x6152 }, - { 0x20010, 0x5a }, - { 0x20011, 0x3 }, - { 0x120010, 0x5a }, - { 0x120011, 0x3 }, - { 0x220010, 0x5a }, - { 0x220011, 0x3 }, - { 0x40080, 0xe0 }, - { 0x40081, 0x12 }, - { 0x40082, 0xe0 }, - { 0x40083, 0x12 }, - { 0x40084, 0xe0 }, - { 0x40085, 0x12 }, - { 0x140080, 0xe0 }, - { 0x140081, 0x12 }, - { 0x140082, 0xe0 }, - { 0x140083, 0x12 }, - { 0x140084, 0xe0 }, - { 0x140085, 0x12 }, - { 0x240080, 0xe0 }, - { 0x240081, 0x12 }, - { 0x240082, 0xe0 }, - { 0x240083, 0x12 }, - { 0x240084, 0xe0 }, - { 0x240085, 0x12 }, - { 0x400fd, 0xf }, - { 0x10011, 0x1 }, - { 0x10012, 0x1 }, - { 0x10013, 0x180 }, - { 0x10018, 0x1 }, - { 0x10002, 0x6209 }, - { 0x100b2, 0x1 }, - { 0x101b4, 0x1 }, - { 0x102b4, 0x1 }, - { 0x103b4, 0x1 }, - { 0x104b4, 0x1 }, - { 0x105b4, 0x1 }, - { 0x106b4, 0x1 }, - { 0x107b4, 0x1 }, - { 0x108b4, 0x1 }, - { 0x11011, 0x1 }, - { 0x11012, 0x1 }, - { 0x11013, 0x180 }, - { 0x11018, 0x1 }, - { 0x11002, 0x6209 }, - { 0x110b2, 0x1 }, - { 0x111b4, 0x1 }, - { 0x112b4, 0x1 }, - { 0x113b4, 0x1 }, - { 0x114b4, 0x1 }, - { 0x115b4, 0x1 }, - { 0x116b4, 0x1 }, - { 0x117b4, 0x1 }, - { 0x118b4, 0x1 }, - { 0x12011, 0x1 }, - { 0x12012, 0x1 }, - { 0x12013, 0x180 }, - { 0x12018, 0x1 }, - { 0x12002, 0x6209 }, - { 0x120b2, 0x1 }, - { 0x121b4, 0x1 }, - { 0x122b4, 0x1 }, - { 0x123b4, 0x1 }, - { 0x124b4, 0x1 }, - { 0x125b4, 0x1 }, - { 0x126b4, 0x1 }, - { 0x127b4, 0x1 }, - { 0x128b4, 0x1 }, - { 0x13011, 0x1 }, - { 0x13012, 0x1 }, - { 0x13013, 0x180 }, - { 0x13018, 0x1 }, - { 0x13002, 0x6209 }, - { 0x130b2, 0x1 }, - { 0x131b4, 0x1 }, - { 0x132b4, 0x1 }, - { 0x133b4, 0x1 }, - { 0x134b4, 0x1 }, - { 0x135b4, 0x1 }, - { 0x136b4, 0x1 }, - { 0x137b4, 0x1 }, - { 0x138b4, 0x1 }, - { 0x2003a, 0x2 }, - { 0xc0080, 0x2 }, - { 0xd0000, 0x1 } -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 3000mts 1D */ - .drate = 3000, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 400mts 1D */ - .drate = 400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 3000mts 2D */ - .drate = 3000, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing_512mb = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100, }, -}; diff --git a/board/gateworks/venice/lpddr4_timing_imx8mp.c b/board/gateworks/venice/lpddr4_timing_imx8mp.c index 7bfd1b556bb..56c6e2b5cff 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mp.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mp.c @@ -1211,9 +1211,9 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, { 0x200be, 0x3 }, - { 0x2000b, 0x34b }, - { 0x2000c, 0xbb }, - { 0x2000d, 0x753 }, + { 0x2000b, 0x465 }, + { 0x2000c, 0xfa }, + { 0x2000d, 0x9c4 }, { 0x2000e, 0x2c }, { 0x12000b, 0x70 }, { 0x12000c, 0x19 }, @@ -1323,42 +1323,42 @@ struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x1203 }, - { 0x3d400024, 0x16e3600 }, - { 0x3d400064, 0x5b0087 }, + { 0x3d400020, 0x1323 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a00b4 }, { 0x3d400070, 0x7027f90 }, { 0x3d400074, 0x790 }, - { 0x3d4000d0, 0xc00305ba }, - { 0x3d4000d4, 0x940000 }, - { 0x3d4000dc, 0xd4002d }, - { 0x3d4000e0, 0x310000 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x330000 }, { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x191e1920 }, - { 0x3d400104, 0x60630 }, - { 0x3d40010c, 0xb0b000 }, - { 0x3d400110, 0xe04080e }, - { 0x3d400114, 0x2040c0c }, - { 0x3d400118, 0x1010007 }, - { 0x3d40011c, 0x402 }, - { 0x3d400130, 0x20600 }, - { 0x3d400134, 0xc100002 }, - { 0x3d400138, 0x8d }, - { 0x3d400144, 0x96004b }, - { 0x3d400180, 0x2ee0017 }, - { 0x3d400184, 0x2605b8e }, + { 0x3d400100, 0x2028222a }, + { 0x3d400104, 0x8083f }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x502 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0xbc }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, { 0x3d400188, 0x0 }, - { 0x3d400190, 0x497820a }, + { 0x3d400190, 0x49f820e }, { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x170a }, + { 0x3d4001b4, 0x1f0e }, { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, { 0x3d4001b0, 0x11 }, { 0x3d4001c0, 0x1 }, { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0x699 }, - { 0x3d400108, 0x70e1617 }, + { 0x3d4000f4, 0x799 }, + { 0x3d400108, 0x9121b1c }, { 0x3d400200, 0x1f }, { 0x3d400208, 0x0 }, { 0x3d40020c, 0x0 }, @@ -1379,7 +1379,7 @@ struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { { 0x3d400498, 0x620096 }, { 0x3d40049c, 0x1100e07 }, { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1001 }, + { 0x3d402020, 0x1021 }, { 0x3d402024, 0x30d400 }, { 0x3d402050, 0x20d000 }, { 0x3d402064, 0xc0012 }, @@ -1404,7 +1404,7 @@ struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, { 0x3d4020f4, 0x599 }, - { 0x3d403020, 0x1001 }, + { 0x3d403020, 0x1021 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x30005 }, @@ -1436,36 +1436,36 @@ struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { { 0x100a0, 0x0 }, { 0x100a1, 0x1 }, - { 0x100a2, 0x3 }, - { 0x100a3, 0x2 }, - { 0x100a4, 0x5 }, - { 0x100a5, 0x4 }, - { 0x100a6, 0x7 }, - { 0x100a7, 0x6 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, { 0x110a0, 0x0 }, { 0x110a1, 0x1 }, - { 0x110a2, 0x2 }, - { 0x110a3, 0x3 }, - { 0x110a4, 0x4 }, - { 0x110a5, 0x5 }, - { 0x110a6, 0x6 }, - { 0x110a7, 0x7 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, - { 0x120a2, 0x2 }, - { 0x120a3, 0x3 }, - { 0x120a4, 0x4 }, - { 0x120a5, 0x5 }, - { 0x120a6, 0x6 }, - { 0x120a7, 0x7 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, { 0x130a0, 0x0 }, { 0x130a1, 0x1 }, - { 0x130a2, 0x3 }, - { 0x130a3, 0x4 }, - { 0x130a4, 0x5 }, - { 0x130a5, 0x2 }, - { 0x130a6, 0x7 }, - { 0x130a7, 0x6 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, { 0x1005f, 0x1ff }, { 0x1015f, 0x1ff }, { 0x1105f, 0x1ff }, @@ -1500,7 +1500,7 @@ struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { { 0x7055, 0x1ff }, { 0x8055, 0x1ff }, { 0x9055, 0x1ff }, - { 0x200c5, 0x19 }, + { 0x200c5, 0x18 }, { 0x1200c5, 0x7 }, { 0x2200c5, 0x7 }, { 0x2002e, 0x2 }, @@ -1509,11 +1509,11 @@ struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { { 0x90204, 0x0 }, { 0x190204, 0x0 }, { 0x290204, 0x0 }, - { 0x20024, 0x1a3 }, + { 0x20024, 0x1e3 }, { 0x2003a, 0x2 }, - { 0x120024, 0x1a3 }, + { 0x120024, 0x1e3 }, { 0x2003a, 0x2 }, - { 0x220024, 0x1a3 }, + { 0x220024, 0x1e3 }, { 0x2003a, 0x2 }, { 0x20056, 0x3 }, { 0x120056, 0x3 }, @@ -1579,7 +1579,7 @@ struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, - { 0x20008, 0x2ee }, + { 0x20008, 0x3e8 }, { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, @@ -1644,7 +1644,7 @@ struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { /* P0 message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, + { 0x54003, 0xfa0 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1653,26 +1653,26 @@ struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = { { 0x5400b, 0x2 }, { 0x5400f, 0x100 }, { 0x54012, 0x110 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1763,7 +1763,7 @@ struct dram_cfg_param ddr_fsp2_cfg_1gb_single_die[] = { /* P0 2D message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, + { 0x54003, 0xfa0 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1773,26 +1773,26 @@ struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = { { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x110 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1802,8 +1802,8 @@ struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = { struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = { { - /* P0 3000mts 1D */ - .drate = 3000, + /* P0 4000mts 1D */ + .drate = 4000, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg_1gb_single_die, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_1gb_single_die), @@ -1823,8 +1823,8 @@ struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_1gb_single_die), }, { - /* P0 3000mts 2D */ - .drate = 3000, + /* P0 4000mts 2D */ + .drate = 4000, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg_1gb_single_die, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_1gb_single_die), @@ -1843,7 +1843,7 @@ struct dram_timing_info dram_timing_1gb_single_die = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100, }, + .fsp_table = { 4000, 400, 100, }, }; /* @@ -1856,43 +1856,44 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa3080020 }, - { 0x3d400020, 0x1203 }, - { 0x3d400024, 0x16e3600 }, - { 0x3d400064, 0x5b00d2 }, + { 0x3d400020, 0x1323 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a0118 }, { 0x3d400070, 0x7027f90 }, { 0x3d400074, 0x790 }, - { 0x3d4000d0, 0xc00305ba }, - { 0x3d4000d4, 0x940000 }, - { 0x3d4000dc, 0xd4002d }, - { 0x3d4000e0, 0x310000 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x330000 }, { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x191e1920 }, - { 0x3d400104, 0x60630 }, - { 0x3d40010c, 0xb0b000 }, - { 0x3d400110, 0xe04080e }, - { 0x3d400114, 0x2040c0c }, - { 0x3d400118, 0x1010007 }, - { 0x3d40011c, 0x401 }, - { 0x3d400130, 0x20600 }, - { 0x3d400134, 0xc100002 }, - { 0x3d400138, 0xd8 }, - { 0x3d400144, 0x96004b }, - { 0x3d400180, 0x2ee0017 }, - { 0x3d400184, 0x2605b8e }, + { 0x3d400100, 0x2028222a }, + { 0x3d400104, 0x8083f }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x502 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x120 }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, { 0x3d400188, 0x0 }, - { 0x3d400190, 0x497820a }, + { 0x3d400190, 0x49f820e}, { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x170a }, + { 0x3d4001b4, 0x1f0e }, { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, { 0x3d4001b0, 0x11 }, { 0x3d4001c0, 0x1 }, { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x70e1617 }, + { 0x3d4000f4, 0x799 }, + { 0x3d400108, 0x9121b1c }, { 0x3d400200, 0x17 }, + { 0x3d400208, 0x0 }, { 0x3d40020c, 0x0 }, { 0x3d400210, 0x1f1f }, { 0x3d400204, 0x80808 }, @@ -1911,7 +1912,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d400498, 0x620096 }, { 0x3d40049c, 0x1100e07 }, { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1001 }, + { 0x3d402020, 0x1021 }, { 0x3d402024, 0x30d400 }, { 0x3d402050, 0x20d000 }, { 0x3d402064, 0xc001c }, @@ -1926,7 +1927,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d402110, 0x2040202 }, { 0x3d402114, 0x2030202 }, { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x301 }, + { 0x3d40211c, 0x302 }, { 0x3d402130, 0x20300 }, { 0x3d402134, 0xa100002 }, { 0x3d402138, 0x1d }, @@ -1935,8 +1936,8 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d402190, 0x3818200 }, { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x1001 }, + { 0x3d4020f4, 0x599 }, + { 0x3d403020, 0x1021 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x30007 }, @@ -1951,7 +1952,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d403110, 0x2040202 }, { 0x3d403114, 0x2030202 }, { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x301 }, + { 0x3d40311c, 0x302 }, { 0x3d403130, 0x20300 }, { 0x3d403134, 0xa100002 }, { 0x3d403138, 0x8 }, @@ -1960,7 +1961,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { { 0x3d403190, 0x3818200 }, { 0x3d403194, 0x80303 }, { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0xc99 }, + { 0x3d4030f4, 0x599 }, { 0x3d400028, 0x0 }, }; @@ -1968,36 +1969,36 @@ static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = { { 0x100a0, 0x0 }, { 0x100a1, 0x1 }, - { 0x100a2, 0x3 }, - { 0x100a3, 0x2 }, - { 0x100a4, 0x5 }, - { 0x100a5, 0x4 }, - { 0x100a6, 0x7 }, - { 0x100a7, 0x6 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, { 0x110a0, 0x0 }, { 0x110a1, 0x1 }, - { 0x110a2, 0x2 }, - { 0x110a3, 0x3 }, - { 0x110a4, 0x4 }, - { 0x110a5, 0x5 }, - { 0x110a6, 0x6 }, - { 0x110a7, 0x7 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, - { 0x120a2, 0x2 }, - { 0x120a3, 0x3 }, - { 0x120a4, 0x4 }, - { 0x120a5, 0x5 }, - { 0x120a6, 0x6 }, - { 0x120a7, 0x7 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, { 0x130a0, 0x0 }, { 0x130a1, 0x1 }, - { 0x130a2, 0x3 }, - { 0x130a3, 0x4 }, - { 0x130a4, 0x5 }, - { 0x130a5, 0x2 }, - { 0x130a6, 0x7 }, - { 0x130a7, 0x6 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, { 0x1005f, 0x1ff }, { 0x1015f, 0x1ff }, { 0x1105f, 0x1ff }, @@ -2032,7 +2033,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = { { 0x7055, 0x1ff }, { 0x8055, 0x1ff }, { 0x9055, 0x1ff }, - { 0x200c5, 0x19 }, + { 0x200c5, 0x18 }, { 0x1200c5, 0x7 }, { 0x2200c5, 0x7 }, { 0x2002e, 0x2 }, @@ -2041,11 +2042,11 @@ static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = { { 0x90204, 0x0 }, { 0x190204, 0x0 }, { 0x290204, 0x0 }, - { 0x20024, 0x1a3 }, + { 0x20024, 0x1e3 }, { 0x2003a, 0x2 }, - { 0x120024, 0x1a3 }, + { 0x120024, 0x1e3 }, { 0x2003a, 0x2 }, - { 0x220024, 0x1a3 }, + { 0x220024, 0x1e3 }, { 0x2003a, 0x2 }, { 0x20056, 0x3 }, { 0x120056, 0x3 }, @@ -2111,7 +2112,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = { { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, - { 0x20008, 0x2ee }, + { 0x20008, 0x3e8 }, { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, @@ -2175,7 +2176,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_die[] = { static struct dram_cfg_param ddr_fsp0_cfg_4gb_dual_die[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, + { 0x54003, 0xfa0 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -2184,26 +2185,26 @@ static struct dram_cfg_param ddr_fsp0_cfg_4gb_dual_die[] = { { 0x5400b, 0x2 }, { 0x5400f, 0x100 }, { 0x54012, 0x310 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -2294,7 +2295,7 @@ static struct dram_cfg_param ddr_fsp2_cfg_4gb_dual_die[] = { /* P0 2D message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_2d_cfg_4gb_dual_die[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, + { 0x54003, 0xfa0 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -2304,26 +2305,26 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg_4gb_dual_die[] = { { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x310 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -2333,8 +2334,8 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg_4gb_dual_die[] = { static struct dram_fsp_msg ddr_dram_fsp_msg_4gb_dual_die[] = { { - /* P0 3000mts 1D */ - .drate = 3000, + /* P0 4000mts 1D */ + .drate = 4000, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg_4gb_dual_die, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_4gb_dual_die), @@ -2354,8 +2355,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_4gb_dual_die[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_4gb_dual_die), }, { - /* P0 3000mts 2D */ - .drate = 3000, + /* P0 4000mts 2D */ + .drate = 4000, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg_4gb_dual_die, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_4gb_dual_die), @@ -2374,5 +2375,5 @@ struct dram_timing_info dram_timing_4gb_dual_die = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100, }, + .fsp_table = { 4000, 400, 100, }, }; diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index a39ae58c8a0..0902a1da3e2 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -238,12 +238,12 @@ int ft_board_setup(void *fdt, struct bd_info *bd) if (!strncmp(base_model, "GW73", 4)) { pcbrev = get_pcb_rev(base_model); - if (pcbrev > 'B') { + if (pcbrev > 'B' && pcbrev < 'E') { printf("adjusting dt for %s\n", base_model); /* - * revC replaced PCIe 5-port switch with 4-port - * which changed ethernet1 PCIe GbE + * revC/D/E has PCIe 4-port switch which changes + * ethernet1 PCIe GbE: * from: pcie@0,0/pcie@1,0/pcie@2,4/pcie@6.0 * to: pcie@0,0/pcie@1,0/pcie@2,3/pcie@5.0 */ diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c index 48392c48e5c..cf1d7cee925 100644 --- a/board/grinn/liteboard/board.c +++ b/board/grinn/liteboard/board.c @@ -20,7 +20,6 @@ #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/boot_mode.h> #include <asm/io.h> -#include <common.h> #include <env.h> #include <fsl_esdhc_imx.h> #include <linux/sizes.h> diff --git a/board/htc/endeavoru/endeavoru.c b/board/htc/endeavoru/endeavoru.c index 7fb6125b143..78eb34e7d46 100644 --- a/board/htc/endeavoru/endeavoru.c +++ b/board/htc/endeavoru/endeavoru.c @@ -7,21 +7,7 @@ * Svyatoslav Ryhel <clamor95@gmail.com> */ -#include <dm.h> #include <fdt_support.h> -#include <asm/arch/pinmux.h> - -#include "pinmux-config-endeavoru.h" - -/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) -{ - pinmux_config_pingrp_table(endeavoru_pinmux_common, - ARRAY_SIZE(endeavoru_pinmux_common)); -} #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/board/htc/endeavoru/pinmux-config-endeavoru.h b/board/htc/endeavoru/pinmux-config-endeavoru.h deleted file mode 100644 index a00c5c988f1..00000000000 --- a/board/htc/endeavoru/pinmux-config-endeavoru.h +++ /dev/null @@ -1,362 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * Copyright (c) 2022, Svyatoslav Ryhel. - */ - -#ifndef _PINMUX_CONFIG_ENDEAVORU_H_ -#define _PINMUX_CONFIG_ENDEAVORU_H_ - -#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_DEFAULT, \ - .od = PMUX_PIN_OD_DEFAULT, \ - .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ - } - -#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_##_lock, \ - .od = PMUX_PIN_OD_##_od, \ - .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ - } - -#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_##_lock, \ - .od = PMUX_PIN_OD_DEFAULT, \ - .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ - } - -#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ - { \ - .drvgrp = PMUX_DRVGRP_##_drvgrp, \ - .slwf = _slwf, \ - .slwr = _slwr, \ - .drvup = _drvup, \ - .drvdn = _drvdn, \ - .lpmd = PMUX_LPMD_##_lpmd, \ - .schmt = PMUX_SCHMT_##_schmt, \ - .hsm = PMUX_HSM_##_hsm, \ - } - -static struct pmux_pingrp_config endeavoru_pinmux_common[] = { - /* SDMMC1 pinmux */ - DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT3_PY4, UARTE, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SDMMC1_DAT2_PY5, UARTE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT1_PY6, RSVD2, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), - - /* SDMMC3 pinmux */ - DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT6_PD3, INVALID, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT7_PD4, INVALID, NORMAL, NORMAL, INPUT), - - /* SDMMC4 pinmux */ - LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - - /* I2C pinmux */ - I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - - /* HDMI pinmux */ - DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), - - /* ULPI pinmux */ - DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA2_PO3, SPI3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA3_PO4, HSI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA4_PO5, SPI2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA7_PO0, SPI2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_CLK_PY0, RSVD2, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_DIR_PY1, RSVD2, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_NXT_PY2, ULPI, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_STP_PY3, ULPI, NORMAL, NORMAL, INPUT), - - /* DAP3 pinmux */ - DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), - - /* PV-gpio group pinmux */ - DEFAULT_PINMUX(PV0, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PV2, RSVD2, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PV3, RSVD2, NORMAL, NORMAL, OUTPUT), - - /* CLK2 pinmux */ - DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD4, NORMAL, NORMAL, OUTPUT), - - /* LCD pinmux */ - DEFAULT_PINMUX(LCD_PWR1_PC1, RSVD4, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, UP, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_CS0_N_PN4, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, UP, TRISTATE, OUTPUT), - DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D2_PE2, RSVD3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D6_PE6, RSVD3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D8_PF0, RSVD4, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D14_PF6, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D15_PF7, RSVD4, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D18_PM2, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D19_PM3, RSVD4, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D21_PM5, RSVD4, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_D22_PM6, RSVD4, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_D23_PM7, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_CS1_N_PW0, RSVD4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_DC1_PD2, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CRT_VSYNC_PV7, RSVD4, NORMAL, NORMAL, OUTPUT), - - /* VI-group pinmux */ - LV_PINMUX(VI_D0_PT4, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D4_PL2, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D6_PL4, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D10_PT2, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D11_PT3, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_PCLK_PT0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_MCLK_PT1, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_VSYNC_PD6, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_HSYNC_PD7, INVALID, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - - /* UART-2 pinmux */ - DEFAULT_PINMUX(UART2_RXD_PC3, SPI4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_TXD_PC2, SPI4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_RTS_N_PJ6, SPI4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_CTS_N_PJ5, SPI4, NORMAL, NORMAL, INPUT), - - /* UART-3 pinmux */ - DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), - - /* PU-gpio group pinmux */ - DEFAULT_PINMUX(PU0, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PU1, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PU2, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PU3, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PU4, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PU5, RSVD4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(PU6, PWM3, UP, TRISTATE, INPUT), - - /* DAP4 pinmux */ - DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DOUT_PP6, RSVD4, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(DAP4_SCLK_PP7, RSVD4, NORMAL, NORMAL, OUTPUT), - - /* CLK3 pinmux */ - DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD4, NORMAL, TRISTATE, INPUT), - - /* GMI pinmux */ - DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_WAIT_PI7, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_ADV_N_PK0, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CLK_PK1, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS1_N_PJ2, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS6_N_PI3, NAND, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD0_PG0, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD1_PG1, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD2_PG2, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD3_PG3, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD4_PG4, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD5_PG5, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD6_PG6, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD7_PG7, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD9_PH1, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD11_PH3, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD12_PH4, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD13_PH5, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD14_PH6, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD15_PH7, NAND, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_WR_N_PI0, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_OE_N_PI1, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_DQS_PI2, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_RST_N_PI4, RSVD4, UP, TRISTATE, INPUT), - - DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(PCC1, RSVD3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB0, RSVD3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB7, RSVD3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PCC2, RSVD3, UP, NORMAL, INPUT), - - DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, UP, NORMAL, INPUT), - - /* KBC keys */ - DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW1_PR1, KBC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW2_PR2, RSVD4, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW3_PR3, RSVD3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW4_PR4, RSVD4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW10_PS2, KBC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW11_PS3, KBC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW12_PS4, KBC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW13_PS5, KBC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW14_PS6, KBC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW15_PS7, KBC, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL6_PQ6, KBC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, NORMAL, INPUT), - - /* CLK */ - DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(OWR, OWR, UP, NORMAL, INPUT), - - /* DAP1 pinmux */ - DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, TRISTATE, OUTPUT), - - /* CLK1 pinmux */ - DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK1_OUT_PW4, RSVD4, NORMAL, NORMAL, INPUT), - - /* SPDIF pinmux */ - DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, TRISTATE, OUTPUT), - - /* DAP2 pinmux */ - DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, DOWN, NORMAL, INPUT), - - /* SPI pinmux */ - DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SPI2_MISO_PX1, SPI2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI2_CS0_N_PX3, SPI2, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SPI2_SCK_PX2, SPI2, NORMAL, NORMAL, OUTPUT), - - DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SPI2_CS2_N_PW3, SPI2, UP, TRISTATE, INPUT), - - DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_SCK_PX5, SPI2, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, OUTPUT), - - /* PEX pinmux */ - DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), -}; - -#endif /* _PINMUX_CONFIG_TRANSFORMER_H_ */ diff --git a/board/keymile/kmcent2/kmcent2.env b/board/keymile/kmcent2/kmcent2.env index efa762e5589..dc5508e315c 100644 --- a/board/keymile/kmcent2/kmcent2.env +++ b/board/keymile/kmcent2/kmcent2.env @@ -21,7 +21,7 @@ update=protect off CONFIG_SYS_MONITOR_BASE +${filesize} && erase CONFIG_SYS_MONITOR_BASE +${filesize} && cp.b ${load_addr_r} CONFIG_SYS_MONITOR_BASE ${filesize} && protect on CONFIG_SYS_MONITOR_BASE +${filesize} - update-nor=protect off CONFIG_SYS_FLASH_BASE +${filesize} && +update-nor=protect off CONFIG_SYS_FLASH_BASE +${filesize} && erase CONFIG_SYS_FLASH_BASE +${filesize} && cp.b ${load_addr_r} CONFIG_SYS_FLASH_BASE ${filesize} && protect on CONFIG_SYS_MONITOR_BASE +CONFIG_SYS_MONITOR_LEN diff --git a/board/lg/x3-t30/Kconfig b/board/lg/x3-t30/Kconfig index 53d776019d6..53b6ab3e93c 100644 --- a/board/lg/x3-t30/Kconfig +++ b/board/lg/x3-t30/Kconfig @@ -9,16 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "x3-t30" -config DEVICE_P880 - bool "Enable support for LG Optimus 4X HD" - help - LG Optimus 4X HD derives from x3 board but has slight - differences. - -config DEVICE_P895 - bool "Enable support for LG Optimus Vu" - help - LG Optimus Vu derives from x3 board but has slight - differences. - endif diff --git a/board/lg/x3-t30/configs/p880.config b/board/lg/x3-t30/configs/p880.config index 1a47b5f7692..57c2885779b 100644 --- a/board/lg/x3-t30/configs/p880.config +++ b/board/lg/x3-t30/configs/p880.config @@ -1,4 +1,3 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p880" -CONFIG_DEVICE_P880=y CONFIG_SYS_PROMPT="Tegra30 (P880) # " CONFIG_VIDEO_LCD_RENESAS_R69328=y diff --git a/board/lg/x3-t30/configs/p895.config b/board/lg/x3-t30/configs/p895.config index 019a5662d62..2eba92594b5 100644 --- a/board/lg/x3-t30/configs/p895.config +++ b/board/lg/x3-t30/configs/p895.config @@ -1,4 +1,3 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-lg-p895" -CONFIG_DEVICE_P895=y CONFIG_SYS_PROMPT="Tegra30 (P895) # " CONFIG_VIDEO_LCD_RENESAS_R61307=y diff --git a/board/lg/x3-t30/pinmux-config-x3.h b/board/lg/x3-t30/pinmux-config-x3.h deleted file mode 100644 index cdb28095f3c..00000000000 --- a/board/lg/x3-t30/pinmux-config-x3.h +++ /dev/null @@ -1,449 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * Copyright (c) 2021, Svyatoslav Ryhel. - */ - -#ifndef _PINMUX_CONFIG_X3_H_ -#define _PINMUX_CONFIG_X3_H_ - -#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_DEFAULT, \ - .od = PMUX_PIN_OD_DEFAULT, \ - .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ - } - -#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_##_lock, \ - .od = PMUX_PIN_OD_##_od, \ - .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ - } - -#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ - { \ - .pingrp = PMUX_PINGRP_##_pingrp, \ - .func = PMUX_FUNC_##_mux, \ - .pull = PMUX_PULL_##_pull, \ - .tristate = PMUX_TRI_##_tri, \ - .io = PMUX_PIN_##_io, \ - .lock = PMUX_PIN_LOCK_##_lock, \ - .od = PMUX_PIN_OD_DEFAULT, \ - .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ - } - -static struct pmux_pingrp_config tegra3_x3_pinmux_common[] = { - /* SDMMC1 pinmux */ - DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), - - /* SDMMC3 pinmux */ -// DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific -// DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific -// DEFAULT_PINMUX(SDMMC3_DAT0_PB7, RSVD1, NORMAL, TRISTATE, INPUT), // device specific -// DEFAULT_PINMUX(SDMMC3_DAT1_PB6, RSVD1, NORMAL, NORMAL, INPUT), // device specific -// DEFAULT_PINMUX(SDMMC3_DAT2_PB5, RSVD1, NORMAL, TRISTATE, INPUT), // device specific -// DEFAULT_PINMUX(SDMMC3_DAT3_PB4, RSVD1, NORMAL, TRISTATE, INPUT), // device specific -// DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific -// DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific -// DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, TRISTATE, INPUT), // device specific -// DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD2, NORMAL, TRISTATE, INPUT), // device specific - - /* SDMMC4 pinmux */ - LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), -// LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), // device specific - LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD2, DOWN, NORMAL, INPUT, DISABLE, DISABLE), - - /* I2C1 pinmux */ - I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - - /* I2C2 pinmux */ - I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, UP, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, UP, NORMAL, INPUT, DISABLE, ENABLE), - - /* I2C3 pinmux */ - I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - - /* I2C4 pinmux */ - I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - - /* Power I2C pinmux */ - I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), - - /* HDMI-CEC pinmux */ - DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), - - /* ULPI pinmux */ - DEFAULT_PINMUX(ULPI_DATA0_PO1, SPI3, UP, TRISTATE, OUTPUT), - DEFAULT_PINMUX(ULPI_DATA1_PO2, SPI3, UP, NORMAL, OUTPUT), // LCD_BRIDGE_RESET_N - DEFAULT_PINMUX(ULPI_DATA2_PO3, SPI3, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(ULPI_DATA3_PO4, SPI3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT), -// DEFAULT_PINMUX(ULPI_DATA5_PO6, SPI2, UP, TRISTATE, INPUT), // unconfigured -// DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, UP, NORMAL, INPUT), // device specific -// DEFAULT_PINMUX(ULPI_DATA7_PO0, SPI2, UP, NORMAL, INPUT), // unconfigured - DEFAULT_PINMUX(ULPI_CLK_PY0, RSVD2, DOWN, NORMAL, OUTPUT), // LCD_EN - DEFAULT_PINMUX(ULPI_DIR_PY1, RSVD2, UP, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_NXT_PY2, RSVD2, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT), - - /* DAP3 pinmux */ - DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PV3, RSVD2, DOWN, NORMAL, INPUT), - - /* CLK2 pinmux */ - DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD2, UP, NORMAL, INPUT), - DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, OUTPUT), - - /* LCD pinmux */ - DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, OUTPUT), -// DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, DOWN, TRISTATE, OUTPUT), // unconfigured - DEFAULT_PINMUX(LCD_SDIN_PZ2, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SDI - DEFAULT_PINMUX(LCD_SDOUT_PN5, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SDO - DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_CS0_N_PN4, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_CS - DEFAULT_PINMUX(LCD_DC0_PN6, RSVD3, NORMAL, NORMAL, OUTPUT), // LCD_CP_EN / BL - DEFAULT_PINMUX(LCD_SCK_PZ4, SPI5, NORMAL, NORMAL, INPUT), // LCD_RGB_SCL - DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_PCLK - DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_HSYNC - DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), // LCD_RGB_VSYNC - DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_CS1_N_PW0, RSVD4, UP, NORMAL, OUTPUT), // LCD_RESET_N - DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, TRISTATE, OUTPUT), // LCD_MAKER_ID - DEFAULT_PINMUX(LCD_DC1_PD2, RSVD3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(CRT_HSYNC_PV6, RSVD2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CRT_VSYNC_PV7, RSVD2, NORMAL, NORMAL, INPUT), - - /* VI-group pinmux */ - LV_PINMUX(VI_D0_PT4, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D10_PT2, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_D11_PT3, RSVD2, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_HSYNC_PD7, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LV_PINMUX(VI_VSYNC_PD6, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - - /* UART-B pinmux */ -// DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), // device specific -// DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), // device specific - DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), - - /* UART-C pinmux */ - DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), - - /* PU-gpio group pinmux */ -// DEFAULT_PINMUX(PU0, UARTA, NORMAL, NORMAL, OUTPUT), // device specific -// DEFAULT_PINMUX(PU1, UARTA, NORMAL, NORMAL, INPUT), // device specific -// DEFAULT_PINMUX(PU2, RSVD1, NORMAL, TRISTATE, INPUT), // device specific -// DEFAULT_PINMUX(PU3, PWM0, NORMAL, TRISTATE, INPUT), // device specific -// DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT), // device specific - DEFAULT_PINMUX(PU5, RSVD4, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(PU6, PWM3, DOWN, NORMAL, INPUT), - - /* DAP4 pinmux */ - DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), - - /* CLK3 pinmux */ - DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), // MIPI_BRIDGE_CLK - DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT), - - DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, UP, NORMAL, INPUT), - - DEFAULT_PINMUX(PCC1, RSVD3, NORMAL, NORMAL, OUTPUT), -// DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, OUTPUT), // device specific - DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB7, I2S4, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PCC2, RSVD3, NORMAL, NORMAL, OUTPUT), - - DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), - - /* KBC keys */ - DEFAULT_PINMUX(KB_ROW0_PR0, RSVD4, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW2_PR2, RSVD4, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW3_PR3, RSVD3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW4_PR4, RSVD4, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW5_PR5, KBC, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW6_PR6, KBC, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW7_PR7, KBC, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW9_PS1, KBC, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW10_PS2, KBC, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW11_PS3, KBC, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_ROW12_PS4, KBC, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW14_PS6, KBC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW15_PS7, KBC, DOWN, NORMAL, INPUT), - - DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL3_PQ3, KBC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT), - - /* CLK */ - DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT), -// DEFAULT_PINMUX(CORE_PWR_REQ, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured -// DEFAULT_PINMUX(CPU_PWR_REQ, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured -// DEFAULT_PINMUX(PWR_INT_N, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured -// DEFAULT_PINMUX(CLK_32K_IN, RSVD1, NORMAL, NORMAL, INPUT), // unconfigured - DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), - - /* DAP1 pinmux */ - DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), - - /* CLK1 pinmux */ - DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, DOWN, NORMAL, INPUT), - - /* SPDIF pinmux */ - DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, OUTPUT), -// DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, DOWN, NORMAL, OUTPUT), // device specific - - /* DAP2 pinmux */ - DEFAULT_PINMUX(DAP2_FS_PA2, HDA, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DIN_PA4, HDA, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DOUT_PA5, HDA, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_SCLK_PA3, HDA, DOWN, NORMAL, INPUT), - - /* SPI pinmux */ - DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI2, NORMAL, NORMAL, OUTPUT), -// DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, OUTPUT), // device specific -// DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT), // device specific - DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, OUTPUT), - - DEFAULT_PINMUX(SPI2_MOSI_PX0, SPI2, DOWN, NORMAL, OUTPUT), - DEFAULT_PINMUX(SPI2_MISO_PX1, GMI, NORMAL, NORMAL, OUTPUT), -// DEFAULT_PINMUX(SPI2_CS0_N_PX3, SPI6, UP, NORMAL, INPUT), // unconfigured -// DEFAULT_PINMUX(SPI2_SCK_PX2, SPI6, UP, NORMAL, INPUT), // unconfigured - DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT), -// DEFAULT_PINMUX(SPI2_CS2_N_PW3, SPI2, UP, TRISTATE, INPUT), // unconfigured - - /* PEX pinmux */ - DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, TRISTATE, OUTPUT), - DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, TRISTATE, INPUT), - - /* GMI pinmux */ - DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_WAIT_PI7, GMI, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_ADV_N_PK0, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CLK_PK1, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, UP, TRISTATE, INPUT), // LCD_RGB_DE - DEFAULT_PINMUX(GMI_CS1_N_PJ2, RSVD1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_CS3_N_PK4, RSVD1, NORMAL, NORMAL, OUTPUT), -// DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT), // device specific - DEFAULT_PINMUX(GMI_CS6_N_PI3, GMI, UP, NORMAL, INPUT), -// DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT), // device specific - DEFAULT_PINMUX(GMI_AD0_PG0, GMI, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD1_PG1, GMI, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD2_PG2, GMI, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD3_PG3, GMI, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD4_PG4, GMI, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD5_PG5, GMI, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD6_PG6, GMI, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD7_PG7, GMI, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD8_PH0, GMI, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD9_PH1, GMI, DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD10_PH2, GMI, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD11_PH3, PWM3, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD12_PH4, RSVD4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD13_PH5, RSVD4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD14_PH6, GMI, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_AD15_PH7, GMI, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A18_PB1, UARTD, DOWN, NORMAL, OUTPUT), // RGB_IC_EN - DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_WR_N_PI0, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_OE_N_PI1, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_DQS_PI2, GMI, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_RST_N_PI4, GMI, UP, NORMAL, INPUT), -}; - -#ifdef CONFIG_DEVICE_P880 -static struct pmux_pingrp_config tegra3_p880_pinmux[] = { - /* SDMMC3 pinmux */ - DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, TRISTATE, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, TRISTATE, INPUT), - - /* SDMMC4 pinmux */ - LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), - - /* ULPI pinmux */ - DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, NORMAL, NORMAL, INPUT), - - /* UART-B pinmux */ - DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, UP, NORMAL, OUTPUT), - - /* GPIO group pinmux */ - DEFAULT_PINMUX(PU0, UARTA, UP, NORMAL, OUTPUT), - DEFAULT_PINMUX(PU1, UARTA, UP, NORMAL, INPUT), - DEFAULT_PINMUX(PU2, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PU3, UARTA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PBB0, I2S4, NORMAL, TRISTATE, INPUT), - - /* SPDIF pinmux */ - DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, UP, TRISTATE, OUTPUT), - - /* SPI pinmux */ - DEFAULT_PINMUX(SPI1_SCK_PX5, SPI2, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), - - /* GMI pinmux */ - DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD1, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, DOWN, NORMAL, OUTPUT), -}; -#endif /* CONFIG_DEVICE_P880 */ - -#ifdef CONFIG_DEVICE_P895 -static struct pmux_pingrp_config tegra3_p895_pinmux[] = { - /* SDMMC3 pinmux */ - DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT0_PB7, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT1_PB6, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT2_PB5, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT3_PB4, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD2, NORMAL, TRISTATE, INPUT), - - /* SDMMC4 pinmux */ - LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - - /* ULPI pinmux */ - DEFAULT_PINMUX(ULPI_DATA6_PO7, SPI2, UP, NORMAL, INPUT), - - /* UART-B pinmux */ - DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), - - /* Gpio group pinmux */ - DEFAULT_PINMUX(PU0, UARTA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(PU1, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PU2, RSVD1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PU3, PWM0, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PU4, PWM1, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(PBB0, RSVD2, NORMAL, NORMAL, OUTPUT), // LCD_EN_3V0 - - /* SPDIF pinmux */ - DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, DOWN, NORMAL, OUTPUT), - - /* SPI pinmux */ - DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT), - - /* GMI pinmux */ - DEFAULT_PINMUX(GMI_CS4_N_PK2, RSVD4, UP, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT), -}; -#endif /* CONFIG_DEVICE_P895 */ -#endif /* _PINMUX_CONFIG_X3_H_ */ diff --git a/board/lg/x3-t30/x3-t30.c b/board/lg/x3-t30/x3-t30.c index 6b9169be6a1..b781a16e70c 100644 --- a/board/lg/x3-t30/x3-t30.c +++ b/board/lg/x3-t30/x3-t30.c @@ -9,32 +9,9 @@ #include <dm.h> #include <fdt_support.h> -#include <asm/arch/pinmux.h> #include <asm/arch/clock.h> #include <asm/arch-tegra/fuse.h> -#include "pinmux-config-x3.h" - -/* - * Routine: pinmux_init - * Description: Do individual peripheral pinmux configs - */ -void pinmux_init(void) -{ - pinmux_config_pingrp_table(tegra3_x3_pinmux_common, - ARRAY_SIZE(tegra3_x3_pinmux_common)); - -#ifdef CONFIG_DEVICE_P880 - pinmux_config_pingrp_table(tegra3_p880_pinmux, - ARRAY_SIZE(tegra3_p880_pinmux)); -#endif - -#ifdef CONFIG_DEVICE_P895 - pinmux_config_pingrp_table(tegra3_p895_pinmux, - ARRAY_SIZE(tegra3_p895_pinmux)); -#endif -} - int nvidia_board_init(void) { /* Set up panel bridge clocks */ diff --git a/board/mediatek/mt8365_evk/MAINTAINERS b/board/mediatek/mt8365_evk/MAINTAINERS new file mode 100644 index 00000000000..bb28ae8df7b --- /dev/null +++ b/board/mediatek/mt8365_evk/MAINTAINERS @@ -0,0 +1,6 @@ +MT8365 EVK +M: Julien Masson <jmasson@baylibre.com> +S: Maintained +F: arch/arm/dts/mt8365-evk.dts +F: board/mediatek/mt8365_evk/ +F: configs/mt8365_evk_defconfig diff --git a/board/mediatek/mt8365_evk/Makefile b/board/mediatek/mt8365_evk/Makefile new file mode 100644 index 00000000000..90fc92b28c5 --- /dev/null +++ b/board/mediatek/mt8365_evk/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += mt8365_evk.o diff --git a/board/mediatek/mt8365_evk/mt8365_evk.c b/board/mediatek/mt8365_evk/mt8365_evk.c new file mode 100644 index 00000000000..723a50fec00 --- /dev/null +++ b/board/mediatek/mt8365_evk/mt8365_evk.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 BayLibre SAS + * Author: Julien Masson <jmasson@baylibre.com> + */ + +#include <asm/armv8/mmu.h> + +int board_init(void) +{ + return 0; +} + +static struct mm_region mt8365_evk_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0xc0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = mt8365_evk_mem_map; diff --git a/board/phytec/common/imx8m_som_detection.c b/board/phytec/common/imx8m_som_detection.c index c6c96ed19cb..214b75db3b0 100644 --- a/board/phytec/common/imx8m_som_detection.c +++ b/board/phytec/common/imx8m_som_detection.c @@ -15,6 +15,8 @@ extern struct phytec_eeprom_data eeprom_data; +#if IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) + /* Check if the SoM is actually one of the following products: * - i.MX8MM * - i.MX8MN @@ -23,18 +25,18 @@ extern struct phytec_eeprom_data eeprom_data; * * Returns 0 in case it's a known SoM. Otherwise, returns -1. */ -u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data) +int __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data) { char *opt; u8 som; + if (!data) + data = &eeprom_data; + /* We can not do the check for early API revisions */ if (data->api_rev < PHYTEC_API_REV2) return -1; - if (!data) - data = &eeprom_data; - som = data->data.data_api2.som_no; debug("%s: som id: %u\n", __func__, som); @@ -166,3 +168,33 @@ u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data) debug("%s: rtc: %u\n", __func__, rtc); return rtc; } + +#else + +inline int __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data) +{ + return -1; +} + +inline u8 __maybe_unused +phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) */ diff --git a/board/phytec/common/imx8m_som_detection.h b/board/phytec/common/imx8m_som_detection.h index 88d3037bf36..0176347414f 100644 --- a/board/phytec/common/imx8m_som_detection.h +++ b/board/phytec/common/imx8m_som_detection.h @@ -13,42 +13,10 @@ #define PHYTEC_IMX8MM_SOM 69 #define PHYTEC_IMX8MP_SOM 70 -#if IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) - -u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data); +int __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data); -#else - -inline u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data) -{ - return -1; -} - -inline u8 __maybe_unused -phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data) -{ - return PHYTEC_EEPROM_INVAL; -} - -inline u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data) -{ - return PHYTEC_EEPROM_INVAL; -} - -inline u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data) -{ - return PHYTEC_EEPROM_INVAL; -} - -inline u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data) -{ - return PHYTEC_EEPROM_INVAL; -} - -#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) */ - #endif /* _PHYTEC_IMX8M_SOM_DETECTION_H */ diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index 55562731270..1b10923b62f 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -16,6 +16,8 @@ struct phytec_eeprom_data eeprom_data; +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) + int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data, int bus_num, int addr, int addr_fallback) { @@ -83,8 +85,8 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data, } ptr = (int *)data; - for (i = 0; i < sizeof(struct phytec_eeprom_data); i += sizeof(ptr)) - if (*ptr != 0x0) + for (i = 0; i < sizeof(struct phytec_eeprom_data); i++) + if (ptr[i] != 0x0) break; if (i == sizeof(struct phytec_eeprom_data)) { @@ -159,7 +161,8 @@ void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data) sub_som_type2 = 2; break; default: - break; + pr_err("%s: Invalid SoM type: %i", __func__, api2->som_type); + return; }; printf("SoM: %s-%03u-%s-%03u ", @@ -201,3 +204,40 @@ u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data) return api2->pcb_rev; } + +#else + +inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data, + int bus_num, int addr, + int addr_fallback) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline int phytec_eeprom_data_init(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data) +{ +} + +inline char *__maybe_unused phytec_get_opt(struct phytec_eeprom_data *data) +{ + return NULL; +} + +u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +#endif /* IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) */ diff --git a/board/phytec/common/phytec_som_detection.h b/board/phytec/common/phytec_som_detection.h index c68e2302cc4..11009240875 100644 --- a/board/phytec/common/phytec_som_detection.h +++ b/board/phytec/common/phytec_som_detection.h @@ -56,8 +56,6 @@ struct phytec_eeprom_data { } data; } __packed; -#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) - int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data, int bus_num, int addr, int addr_fallback); @@ -70,40 +68,4 @@ void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data); char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data); -#else - -inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, - int bus_num, int addr) -{ - return PHYTEC_EEPROM_INVAL; -} - -inline int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data, - int bus_num, int addr, - int addr_fallback) -{ - return PHYTEC_EEPROM_INVAL; -} - -inline int phytec_eeprom_data_init(struct phytec_eeprom_data *data, - int bus_num, int addr) -{ - return PHYTEC_EEPROM_INVAL; -} - -inline void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data) -{ -} - -inline char *__maybe_unused phytec_get_opt(struct phytec_eeprom_data *data) -{ - return NULL; -} - -u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data) -{ - return PHYTEC_EEPROM_INVAL; -} -#endif /* IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) */ - #endif /* _PHYTEC_SOM_DETECTION_H */ diff --git a/board/pine64/rockpro64_rk3399/MAINTAINERS b/board/pine64/rockpro64_rk3399/MAINTAINERS index 303db144aab..220ee21f230 100644 --- a/board/pine64/rockpro64_rk3399/MAINTAINERS +++ b/board/pine64/rockpro64_rk3399/MAINTAINERS @@ -1,5 +1,4 @@ ROCKPRO64 -M: Akash Gajjar <akash@openedev.com> M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained F: board/pine64/rockpro64_rk3399 diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index c7e412b54ee..acdb840f209 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -93,7 +93,6 @@ F: configs/rock-4se-rk3399_defconfig F: arch/arm/dts/rk3399-rock-4se-u-boot.dtsi ROCK-PI-4 -M: Akash Gajjar <akash@openedev.com> M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained F: configs/rock-pi-4-rk3399_defconfig diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 9d58860451c..802596569c6 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -3,8 +3,8 @@ * Copyright (c) 2011 The Chromium OS Authors. */ -#include <common.h> #include <addr_map.h> +#include <config.h> #include <cpu_func.h> #include <cros_ec.h> #include <dm.h> diff --git a/board/sifive/unmatched/unmatched.env b/board/sifive/unmatched/unmatched.env new file mode 100644 index 00000000000..0f1e5a71747 --- /dev/null +++ b/board/sifive/unmatched/unmatched.env @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* environment for HiFive Unmatched boards */ + +kernel_addr_r=0x80200000 +kernel_comp_addr_r=0x88000000 +kernel_comp_size=0x4000000 +fdt_addr_r=0x8c000000 +scriptaddr=0x8c100000 +pxefile_addr_r=0x8c200000 +ramdisk_addr_r=0x8c300000 +type_guid_gpt_loader1=5B193300-FC78-40CD-8002-E86C45580B47 +type_guid_gpt_loader2=2E54B353-1271-4842-806F-E436D6AF6985 +type_guid_gpt_system=0FC63DAF-8483-4772-8E79-3D69D8477DE4 +partitions= + name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1}; + name=loader2,size=4MB,type=${type_guid_gpt_loader2}; + name=system,size=-,bootable,type=${type_guid_gpt_system}; +fdtfile= CONFIG_DEFAULT_FDT_FILE diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 00614372119..f556857a391 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -455,6 +455,11 @@ M: Jernej Skrabec <jernej.skrabec@siol.net> S: Maintained F: configs/orangepi_zero2_defconfig +ORANGEPI ZERO 3 BOARD +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/orangepi_zero3_defconfig + ORANGEPI PC 2 BOARD M: Andre Przywara <andre.przywara@arm.com> S: Maintained diff --git a/board/ti/am62ax/rm-cfg.yaml b/board/ti/am62ax/rm-cfg.yaml index b9f3668c073..1fb7d64cb89 100644 --- a/board/ti/am62ax/rm-cfg.yaml +++ b/board/ti/am62ax/rm-cfg.yaml @@ -518,14 +518,14 @@ rm-cfg: host_id: 20 reserved: 0 - - start_resource: 45 - num_resource: 35 + start_resource: 44 + num_resource: 36 type: 1802 host_id: 35 reserved: 0 - - start_resource: 45 - num_resource: 35 + start_resource: 44 + num_resource: 36 type: 1802 host_id: 36 reserved: 0 @@ -536,38 +536,38 @@ rm-cfg: host_id: 30 reserved: 0 - - start_resource: 15 + start_resource: 14 num_resource: 512 type: 1805 host_id: 12 reserved: 0 - - start_resource: 527 + start_resource: 526 num_resource: 256 type: 1805 host_id: 35 reserved: 0 - - start_resource: 527 + start_resource: 526 num_resource: 256 type: 1805 host_id: 36 reserved: 0 - - start_resource: 783 + start_resource: 782 num_resource: 128 type: 1805 host_id: 30 reserved: 0 - - start_resource: 911 + start_resource: 910 num_resource: 128 type: 1805 host_id: 20 reserved: 0 - - start_resource: 1039 - num_resource: 497 + start_resource: 1038 + num_resource: 498 type: 1805 host_id: 128 reserved: 0 diff --git a/board/ti/am62x/rm-cfg.yaml b/board/ti/am62x/rm-cfg.yaml index c06232f6dde..5a265ed1e8e 100644 --- a/board/ti/am62x/rm-cfg.yaml +++ b/board/ti/am62x/rm-cfg.yaml @@ -512,14 +512,14 @@ rm-cfg: host_id: 12 reserved: 0 - - start_resource: 45 - num_resource: 35 + start_resource: 44 + num_resource: 36 type: 1802 host_id: 35 reserved: 0 - - start_resource: 45 - num_resource: 35 + start_resource: 44 + num_resource: 36 type: 1802 host_id: 36 reserved: 0 @@ -530,32 +530,32 @@ rm-cfg: host_id: 30 reserved: 0 - - start_resource: 14 + start_resource: 13 num_resource: 512 type: 1805 host_id: 12 reserved: 0 - - start_resource: 526 + start_resource: 525 num_resource: 256 type: 1805 host_id: 35 reserved: 0 - - start_resource: 526 + start_resource: 525 num_resource: 256 type: 1805 host_id: 36 reserved: 0 - - start_resource: 782 + start_resource: 781 num_resource: 128 type: 1805 host_id: 30 reserved: 0 - - start_resource: 910 - num_resource: 626 + start_resource: 909 + num_resource: 627 type: 1805 host_id: 128 reserved: 0 diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h index f24e62850b8..447e70607f9 100644 --- a/board/ti/ks2_evm/mux-k2g.h +++ b/board/ti/ks2_evm/mux-k2g.h @@ -6,7 +6,6 @@ * Texas Instruments Incorporated, <www.ti.com> */ -#include <common.h> #include <hang.h> #include <asm/io.h> #include <asm/arch/mux-k2g.h> diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index e23f9af20da..2e5b02f7267 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -16,7 +16,6 @@ #include <asm/gpio.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/io.h> -#include <common.h> #include <dm.h> #include <dm/platform_data/serial_mxc.h> #include <fdt_support.h> @@ -66,7 +65,7 @@ int dram_init(void) } static iomux_v3_cfg_t const flash_detection_pads[] = { - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(FLASH_DETECTION_CTRL), + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(FLASH_DETECTION_CTRL) | MUX_MODE_SION, }; static iomux_v3_cfg_t const uart1_pads[] = { @@ -193,9 +192,9 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; /* - * Enable GPIO on NAND_WE_B/eMMC_RST with 100k pull-down. eMMC_RST + * Enable GPIO SION on NAND_WE_B/eMMC_RST with 100k pull-down. eMMC_RST * is pulled high with 4.7k for eMMC devices. This allows to reliably - * detect eMMC/NAND flash + * detect eMMC vs NAND flash. */ imx_iomux_v3_setup_multiple_pads(flash_detection_pads, ARRAY_SIZE(flash_detection_pads)); gpio_request(FLASH_DET_GPIO, "flash-detection-gpio"); diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index d09dda5bccc..2718263eb19 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -6,6 +6,7 @@ * */ +#include <config.h> #include <asm/arch/hardware.h> #include <asm/io.h> #include <dm/uclass.h> diff --git a/board/tq/tqma6/tqma6_bb.h b/board/tq/tqma6/tqma6_bb.h index ca81bdf5853..a2f871af1f8 100644 --- a/board/tq/tqma6/tqma6_bb.h +++ b/board/tq/tqma6/tqma6_bb.h @@ -7,8 +7,6 @@ #ifndef __TQMA6_BB__ #define __TQMA6_BB__ -#include <common.h> - int tqma6_bb_board_mmc_getwp(struct mmc *mmc); int tqma6_bb_board_mmc_getcd(struct mmc *mmc); int tqma6_bb_board_mmc_init(struct bd_info *bis); diff --git a/board/tq/tqma6/tqma6q.cfg b/board/tq/tqma6/tqma6q.cfg index a49489aed3f..a345c4de93d 100644 --- a/board/tq/tqma6/tqma6q.cfg +++ b/board/tq/tqma6/tqma6q.cfg @@ -36,7 +36,7 @@ DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 +DATA 4, MX6_IOM_DRAM_RESET, 0x00003030 DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 48914450a29..8be62c86695 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -28,7 +28,6 @@ #include <env.h> #include <linux/delay.h> #include <linux/sizes.h> -#include <common.h> #include <miiphy.h> #include <netdev.h> #include <phy.h> diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 4f0776e8bd9..843198fa0da 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -51,10 +51,11 @@ config XILINX_OF_BOARD_DTB_ADDR config BOOT_SCRIPT_OFFSET hex "Boot script offset" - depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || MICROBLAZE + depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || MICROBLAZE || TARGET_XILINX_MBV default 0xFC0000 if ARCH_ZYNQ || MICROBLAZE default 0x3E80000 if ARCH_ZYNQMP default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET + default 0 if TARGET_XILINX_MBV help Specifies distro boot script offset in NAND/QSPI/NOR flash. diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 9309b071269..12a877c7154 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -652,6 +652,11 @@ int embedded_dtb_select(void) #endif #if defined(CONFIG_LMB) + +#ifndef MMU_SECTION_SIZE +#define MMU_SECTION_SIZE (1 * 1024 * 1024) +#endif + phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { phys_size_t size; diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig new file mode 100644 index 00000000000..4bc9f72c541 --- /dev/null +++ b/board/xilinx/mbv/Kconfig @@ -0,0 +1,28 @@ +if TARGET_XILINX_MBV + +config SYS_BOARD + default "mbv" + +config SYS_VENDOR + default "xilinx" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "xilinx_mbv" + +config TEXT_BASE + default 0x80000000 if !RISCV_SMODE + default 0x80400000 if RISCV_SMODE && ARCH_RV32I + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select GENERIC_RISCV + imply BOARD_LATE_INIT + imply CMD_SBI + imply CMD_PING + +source "board/xilinx/Kconfig" + +endif diff --git a/board/xilinx/mbv/MAINTAINERS b/board/xilinx/mbv/MAINTAINERS new file mode 100644 index 00000000000..445654fe740 --- /dev/null +++ b/board/xilinx/mbv/MAINTAINERS @@ -0,0 +1,7 @@ +XILINX MicroBlaze V BOARD +M: Michal Simek <michal.simek@amd.com> +S: Maintained +F: arch/riscv/dts/xilinx-mbv* +F: board/xilinx/mbv/ +F: configs/xilinx_mbv* +F: include/configs/xilinx_mbv.h diff --git a/board/xilinx/mbv/Makefile b/board/xilinx/mbv/Makefile new file mode 100644 index 00000000000..e2fc0c69715 --- /dev/null +++ b/board/xilinx/mbv/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# (C) Copyright 2023, Advanced Micro Devices, Inc. + +obj-y += board.o diff --git a/board/xilinx/mbv/board.c b/board/xilinx/mbv/board.c new file mode 100644 index 00000000000..ccf4395d6ac --- /dev/null +++ b/board/xilinx/mbv/board.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +int board_init(void) +{ + return 0; +} diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h index e6caa7c8503..dd823d6f62a 100644 --- a/board/xilinx/zynqmp/xil_io.h +++ b/board/xilinx/zynqmp/xil_io.h @@ -5,7 +5,6 @@ /* FIXME remove this when vivado is fixed */ #include <asm/io.h> -#include <common.h> #include <linux/delay.h> #define xil_printf(...) diff --git a/boot/Kconfig b/boot/Kconfig index b438002059c..9f5b8a0cb2c 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -523,7 +523,7 @@ config BOOTMETH_EXTLINUX_PXE config BOOTMETH_EFILOADER bool "Bootdev support for EFI boot" - depends on CMD_BOOTEFI + depends on BOOTEFI_BOOTMGR default y help Enables support for EFI boot using bootdevs. This makes the @@ -558,7 +558,7 @@ config BOOTMETH_DISTRO select BOOTMETH_SCRIPT if CMDLINE # E.g. Armbian uses scripts select BOOTMETH_EXTLINUX # E.g. Debian uses these select BOOTMETH_EXTLINUX_PXE if CMD_PXE && CMD_NET && DM_ETH - select BOOTMETH_EFILOADER if CMD_BOOTEFI # E.g. Ubuntu uses this + select BOOTMETH_EFILOADER if BOOTEFI_BOOTMGR # E.g. Ubuntu uses this config SPL_BOOTMETH_VBE bool "Bootdev support for Verified Boot for Embedded (SPL)" @@ -1514,6 +1514,15 @@ if OF_LIBFDT menu "Devicetree fixup" +config OF_ENV_SETUP + bool "Run a command from environment to set up device tree before boot" + depends on CMD_FDT + help + This causes U-Boot to run a command from the environment variable + fdt_fixup before booting into the operating system, which can use the + fdt command to modify the device tree. The device tree is then passed + to the OS. + config OF_BOARD_SETUP bool "Set up board-specific details in device tree before boot" help diff --git a/boot/Makefile b/boot/Makefile index de0eafed14b..a90ebea5a86 100644 --- a/boot/Makefile +++ b/boot/Makefile @@ -34,7 +34,7 @@ obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_CROS) += bootm.o bootm_os.o bootmeth_cros.o obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SANDBOX) += bootmeth_sandbox.o obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SCRIPT) += bootmeth_script.o ifdef CONFIG_$(SPL_TPL_)BOOTSTD_FULL -obj-$(CONFIG_CMD_BOOTEFI_BOOTMGR) += bootmeth_efi_mgr.o +obj-$(CONFIG_BOOTEFI_BOOTMGR) += bootmeth_efi_mgr.o obj-$(CONFIG_$(SPL_TPL_)EXPO) += bootflow_menu.o obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootflow_menu.o obj-$(CONFIG_$(SPL_TPL_)CEDIT) += cedit.o diff --git a/boot/bootm.c b/boot/bootm.c index 6a4cebcf7a0..7a050ed41a7 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -1078,7 +1078,11 @@ int bootm_run_states(struct bootm_info *bmi, int states) if (!ret && (states & BOOTM_STATE_OS_BD_T)) ret = boot_fn(BOOTM_STATE_OS_BD_T, bmi); if (!ret && (states & BOOTM_STATE_OS_PREP)) { - ret = bootm_process_cmdline_env(images->os.os == IH_OS_LINUX); + int flags = 0; + /* For Linux OS do all substitutions at console processing */ + if (images->os.os == IH_OS_LINUX) + flags = BOOTM_CL_ALL; + ret = bootm_process_cmdline_env(flags); if (ret) { printf("Cmdline setup failed (err=%d)\n", ret); ret = CMD_RET_FAILURE; diff --git a/boot/bootm_os.c b/boot/bootm_os.c index 47a5fd78fb6..ccde72d22c1 100644 --- a/boot/bootm_os.c +++ b/boot/bootm_os.c @@ -476,43 +476,27 @@ static int do_bootm_tee(int flag, struct bootm_info *bmi) static int do_bootm_efi(int flag, struct bootm_info *bmi) { struct bootm_headers *images = bmi->images; - efi_status_t efi_ret; + int ret; void *image_buf; if (flag != BOOTM_STATE_OS_GO) return 0; - /* Initialize EFI drivers */ - efi_ret = efi_init_obj_list(); - if (efi_ret != EFI_SUCCESS) { - printf("## Failed to initialize UEFI sub-system: r = %lu\n", - efi_ret & ~EFI_ERROR_MASK); - return 1; - } + /* We expect to return */ + images->os.type = IH_TYPE_STANDALONE; - /* Install device tree */ - efi_ret = efi_install_fdt(images->ft_len - ? images->ft_addr : EFI_FDT_USE_INTERNAL); - if (efi_ret != EFI_SUCCESS) { - printf("## Failed to install device tree: r = %lu\n", - efi_ret & ~EFI_ERROR_MASK); - return 1; - } + image_buf = map_sysmem(images->ep, images->os.image_len); /* Run EFI image */ printf("## Transferring control to EFI (at address %08lx) ...\n", images->ep); bootstage_mark(BOOTSTAGE_ID_RUN_OS); - /* We expect to return */ - images->os.type = IH_TYPE_STANDALONE; + ret = efi_binary_run(image_buf, images->os.image_len, + images->ft_len + ? images->ft_addr : EFI_FDT_USE_INTERNAL); - image_buf = map_sysmem(images->ep, images->os.image_len); - - efi_ret = efi_run_image(image_buf, images->os.image_len); - if (efi_ret != EFI_SUCCESS) - return 1; - return 0; + return ret; } #endif diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c index 9ba7734911e..00060f7d25a 100644 --- a/boot/bootmeth_efi.c +++ b/boot/bootmeth_efi.c @@ -160,7 +160,6 @@ static int efiload_read_file(struct bootflow *bflow, ulong addr) if (ret) return log_msg_ret("read", ret); bflow->buf = map_sysmem(addr, bflow->size); - bflow->flags |= BOOTFLOWF_STATIC_BUF; set_efi_bootdev(desc, bflow); @@ -313,6 +312,7 @@ static int distro_efi_try_bootflow_files(struct udevice *dev, */ } else { log_debug("No device tree available\n"); + bflow->flags |= BOOTFLOWF_USE_BUILTIN_FDT; } return 0; @@ -323,7 +323,7 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow) char file_addr[17], fname[256]; char *tftp_argv[] = {"tftp", file_addr, fname, NULL}; struct cmd_tbl cmdtp = {}; /* dummy */ - const char *addr_str, *fdt_addr_str; + const char *addr_str, *fdt_addr_str, *bootfile_name; int ret, arch, size; ulong addr, fdt_addr; char str[36]; @@ -339,7 +339,7 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow) ret = env_set("bootp_vci", str); if (ret) return log_msg_ret("vcs", ret); - ret = env_set_ulong("bootp_arch", arch); + ret = env_set_hex("bootp_arch", arch); if (ret) return log_msg_ret("ars", ret); @@ -360,6 +360,12 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow) return log_msg_ret("sz", -EINVAL); bflow->size = size; + /* bootfile should be setup by dhcp*/ + bootfile_name = env_get("bootfile"); + if (!bootfile_name) + return log_msg_ret("bootfile_name", ret); + bflow->fname = strdup(bootfile_name); + /* do the hideous EFI hack */ efi_set_bootdev("Net", "", bflow->fname, map_sysmem(addr, 0), bflow->size); @@ -385,6 +391,7 @@ static int distro_efi_read_bootflow_net(struct bootflow *bflow) bflow->fdt_addr = fdt_addr; } else { log_debug("No device tree available\n"); + bflow->flags |= BOOTFLOWF_USE_BUILTIN_FDT; } bflow->state = BOOTFLOWST_READY; @@ -396,6 +403,12 @@ static int distro_efi_read_bootflow(struct udevice *dev, struct bootflow *bflow) { int ret; + /* + * bootmeth_efi doesn't allocate any buffer neither for blk nor net device + * set flag to avoid freeing static buffer. + */ + bflow->flags |= BOOTFLOWF_STATIC_BUF; + if (bootmeth_uses_network(bflow)) { /* we only support reading from one device, so ignore 'dev' */ ret = distro_efi_read_bootflow_net(bflow); @@ -413,7 +426,6 @@ static int distro_efi_read_bootflow(struct udevice *dev, struct bootflow *bflow) static int distro_efi_boot(struct udevice *dev, struct bootflow *bflow) { ulong kernel, fdt; - char cmd[50]; int ret; kernel = env_get_hex("kernel_addr_r", 0); @@ -423,13 +435,11 @@ static int distro_efi_boot(struct udevice *dev, struct bootflow *bflow) return log_msg_ret("read", ret); /* - * use the provided device tree if available, else fall back to - * the control FDT + * use the provided device tree if not using the built-in fdt */ - if (bflow->fdt_fname) + if (bflow->flags & ~BOOTFLOWF_USE_BUILTIN_FDT) fdt = bflow->fdt_addr; - else - fdt = (ulong)map_to_sysmem(gd->fdt_blob); + } else { /* * This doesn't actually work for network devices: @@ -442,13 +452,17 @@ static int distro_efi_boot(struct udevice *dev, struct bootflow *bflow) fdt = env_get_hex("fdt_addr_r", 0); } - /* - * At some point we can add a real interface to bootefi so we can call - * this directly. For now, go through the CLI, like distro boot. - */ - snprintf(cmd, sizeof(cmd), "bootefi %lx %lx", kernel, fdt); - if (run_command(cmd, 0)) - return log_msg_ret("run", -EINVAL); + if (bflow->flags & BOOTFLOWF_USE_BUILTIN_FDT) { + log_debug("Booting with built-in fdt\n"); + if (efi_binary_run(map_sysmem(kernel, 0), 0, + EFI_FDT_USE_INTERNAL)) + return log_msg_ret("run", -EINVAL); + } else { + log_debug("Booting with external fdt\n"); + if (efi_binary_run(map_sysmem(kernel, 0), 0, + map_sysmem(fdt, 0))) + return log_msg_ret("run", -EINVAL); + } return 0; } diff --git a/boot/bootmeth_efi_mgr.c b/boot/bootmeth_efi_mgr.c index 6428c096d7f..ed29d7ef021 100644 --- a/boot/bootmeth_efi_mgr.c +++ b/boot/bootmeth_efi_mgr.c @@ -87,7 +87,7 @@ static int efi_mgr_boot(struct udevice *dev, struct bootflow *bflow) int ret; /* Booting is handled by the 'bootefi bootmgr' command */ - ret = run_command("bootefi bootmgr", 0); + ret = efi_bootmgr_run(EFI_FDT_USE_INTERNAL); return 0; } diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 2b166c0ff94..75bdd55f326 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <command.h> #include <fdt_support.h> #include <fdtdec.h> #include <env.h> @@ -576,9 +577,22 @@ int image_setup_libfdt(struct bootm_headers *images, void *blob, { ulong *initrd_start = &images->initrd_start; ulong *initrd_end = &images->initrd_end; - int ret = -EPERM; - int fdt_ret; - int of_size; + int ret, fdt_ret, of_size; + + if (IS_ENABLED(CONFIG_OF_ENV_SETUP)) { + const char *fdt_fixup; + + fdt_fixup = env_get("fdt_fixup"); + if (fdt_fixup) { + set_working_fdt_addr(map_to_sysmem(blob)); + ret = run_command_list(fdt_fixup, -1, 0); + if (ret) + printf("WARNING: fdt_fixup command returned %d\n", + ret); + } + } + + ret = -EPERM; if (fdt_root(blob) < 0) { printf("ERROR: root node setup failed\n"); diff --git a/boot/image-fit.c b/boot/image-fit.c index 3cc556b727f..89e377563ce 100644 --- a/boot/image-fit.c +++ b/boot/image-fit.c @@ -15,6 +15,7 @@ #include <time.h> #include <linux/libfdt.h> #include <u-boot/crc.h> +#include <linux/kconfig.h> #else #include <linux/compiler.h> #include <linux/sizes.h> @@ -36,7 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; #include <bootm.h> #include <image.h> #include <bootstage.h> -#include <linux/kconfig.h> #include <u-boot/crc.h> #include <u-boot/md5.h> #include <u-boot/sha1.h> diff --git a/boot/image.c b/boot/image.c index 675b5dd77f9..073931cd7a3 100644 --- a/boot/image.c +++ b/boot/image.c @@ -42,6 +42,7 @@ DECLARE_GLOBAL_DATA_PTR; #else /* USE_HOSTCC */ #include "mkimage.h" +#include <linux/kconfig.h> #include <u-boot/md5.h> #include <time.h> @@ -62,7 +63,6 @@ DECLARE_GLOBAL_DATA_PTR; #include <relocate.h> #include <linux/lzo.h> #include <linux/zstd.h> -#include <linux/kconfig.h> #include <lzma/LzmaTypes.h> #include <lzma/LzmaDec.h> #include <lzma/LzmaTools.h> diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c index a92bb896c63..83bc1677856 100644 --- a/boot/pxe_utils.c +++ b/boot/pxe_utils.c @@ -700,6 +700,11 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) label->name); goto cleanup; } + + if (label->fdtdir) { + printf("Skipping fdtdir %s for failure retrieving dts\n", + label->fdtdir); + } } if (label->kaslrseed) diff --git a/cmd/Kconfig b/cmd/Kconfig index 748b959961d..5a7678f0ac9 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -273,7 +273,7 @@ config CMD_BOOTMETH config BOOTM_EFI bool "Support booting UEFI FIT images" - depends on CMD_BOOTEFI && CMD_BOOTM && FIT + depends on BOOTEFI_BOOTMGR && CMD_BOOTM && FIT default y help Support booting UEFI FIT images via the bootm command. @@ -362,9 +362,19 @@ config CMD_BOOTEFI help Boot an EFI image from memory. +if CMD_BOOTEFI +config CMD_BOOTEFI_BINARY + bool "Allow booting an EFI binary directly" + depends on BOOTEFI_BOOTMGR + default y + help + Select this option to enable direct execution of binary at 'bootefi'. + This subcommand will allow you to load the UEFI binary using + other U-Boot commands or external methods and then run it. + config CMD_BOOTEFI_BOOTMGR bool "UEFI Boot Manager command" - depends on BOOTEFI_BOOTMGR && CMD_BOOTEFI + depends on BOOTEFI_BOOTMGR default y help Select this option to enable the 'bootmgr' subcommand of 'bootefi'. @@ -373,7 +383,6 @@ config CMD_BOOTEFI_BOOTMGR config CMD_BOOTEFI_HELLO_COMPILE bool "Compile a standard EFI hello world binary for testing" - depends on CMD_BOOTEFI && !CPU_V7M default y help This compiles a standard EFI hello world application with U-Boot so @@ -395,6 +404,7 @@ config CMD_BOOTEFI_HELLO up EFI support on a new architecture. source lib/efi_selftest/Kconfig +endif config CMD_BOOTMENU bool "bootmenu" @@ -485,6 +495,16 @@ config CMD_XIMG help Extract a part of a multi-image. +config SYS_XIMG_LEN + hex "imxtract max gunzip size" + default 0x800000 + depends on CMD_XIMG && GZIP + help + This provides the size of the commad-line argument area + used by imxtract for extracting pieces of FIT image. + It should be large enough to fit uncompressed size of + FIT piece we are extracting. + config CMD_SPL bool "spl export - Export boot information for Falcon boot" depends on SPL diff --git a/cmd/armflash.c b/cmd/armflash.c index d1466f73aa4..fdaea5ad811 100644 --- a/cmd/armflash.c +++ b/cmd/armflash.c @@ -180,6 +180,7 @@ static int load_image(const char * const name, const ulong address) { struct afs_image *afi = NULL; int i; + loff_t len_read = 0; parse_flash(); for (i = 0; i < num_afs_images; i++) { @@ -197,6 +198,7 @@ static int load_image(const char * const name, const ulong address) for (i = 0; i < afi->region_count; i++) { ulong from, to; + u32 size; from = afi->flash_mem_start + afi->regions[i].offset; if (address) { @@ -208,14 +210,20 @@ static int load_image(const char * const name, const ulong address) return CMD_RET_FAILURE; } - memcpy((void *)to, (void *)from, afi->regions[i].size); + size = afi->regions[i].size; + memcpy((void *)to, (void *)from, size); printf("loaded region %d from %08lX to %08lX, %08X bytes\n", i, from, to, - afi->regions[i].size); + size); + + len_read += size; } + + env_set_hex("filesize", len_read); + return CMD_RET_SUCCESS; } diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 2ed29ad6bb8..9cf9027bf40 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -7,555 +7,23 @@ #define LOG_CATEGORY LOGC_EFI -#include <common.h> -#include <bootm.h> -#include <charset.h> #include <command.h> -#include <dm.h> +#include <efi.h> #include <efi_loader.h> -#include <efi_selftest.h> -#include <env.h> -#include <errno.h> -#include <image.h> +#include <exports.h> #include <log.h> #include <malloc.h> -#include <asm/global_data.h> -#include <linux/libfdt.h> -#include <linux/libfdt_env.h> #include <mapmem.h> -#include <memalign.h> +#include <vsprintf.h> #include <asm-generic/sections.h> -#include <linux/linkage.h> +#include <asm/global_data.h> +#include <linux/string.h> DECLARE_GLOBAL_DATA_PTR; -static struct efi_device_path *bootefi_image_path; -static struct efi_device_path *bootefi_device_path; -static void *image_addr; -static size_t image_size; - -/** - * efi_get_image_parameters() - return image parameters - * - * @img_addr: address of loaded image in memory - * @img_size: size of loaded image - */ -void efi_get_image_parameters(void **img_addr, size_t *img_size) -{ - *img_addr = image_addr; - *img_size = image_size; -} - -/** - * efi_clear_bootdev() - clear boot device - */ -static void efi_clear_bootdev(void) -{ - efi_free_pool(bootefi_device_path); - efi_free_pool(bootefi_image_path); - bootefi_device_path = NULL; - bootefi_image_path = NULL; - image_addr = NULL; - image_size = 0; -} - -/** - * efi_set_bootdev() - set boot device - * - * This function is called when a file is loaded, e.g. via the 'load' command. - * We use the path to this file to inform the UEFI binary about the boot device. - * - * @dev: device, e.g. "MMC" - * @devnr: number of the device, e.g. "1:2" - * @path: path to file loaded - * @buffer: buffer with file loaded - * @buffer_size: size of file loaded - */ -void efi_set_bootdev(const char *dev, const char *devnr, const char *path, - void *buffer, size_t buffer_size) -{ - struct efi_device_path *device, *image; - efi_status_t ret; - - log_debug("dev=%s, devnr=%s, path=%s, buffer=%p, size=%zx\n", dev, - devnr, path, buffer, buffer_size); - - /* Forget overwritten image */ - if (buffer + buffer_size >= image_addr && - image_addr + image_size >= buffer) - efi_clear_bootdev(); - - /* Remember only PE-COFF and FIT images */ - if (efi_check_pe(buffer, buffer_size, NULL) != EFI_SUCCESS) { - if (IS_ENABLED(CONFIG_FIT) && - !fit_check_format(buffer, IMAGE_SIZE_INVAL)) { - /* - * FIT images of type EFI_OS are started via command - * bootm. We should not use their boot device with the - * bootefi command. - */ - buffer = 0; - buffer_size = 0; - } else { - log_debug("- not remembering image\n"); - return; - } - } - - /* efi_set_bootdev() is typically called repeatedly, recover memory */ - efi_clear_bootdev(); - - image_addr = buffer; - image_size = buffer_size; - - ret = efi_dp_from_name(dev, devnr, path, &device, &image); - if (ret == EFI_SUCCESS) { - bootefi_device_path = device; - if (image) { - /* FIXME: image should not contain device */ - struct efi_device_path *image_tmp = image; - - efi_dp_split_file_path(image, &device, &image); - efi_free_pool(image_tmp); - } - bootefi_image_path = image; - log_debug("- boot device %pD\n", device); - if (image) - log_debug("- image %pD\n", image); - } else { - log_debug("- efi_dp_from_name() failed, err=%lx\n", ret); - efi_clear_bootdev(); - } -} - -/** - * efi_env_set_load_options() - set load options from environment variable - * - * @handle: the image handle - * @env_var: name of the environment variable - * @load_options: pointer to load options (output) - * Return: status code - */ -static efi_status_t efi_env_set_load_options(efi_handle_t handle, - const char *env_var, - u16 **load_options) -{ - const char *env = env_get(env_var); - size_t size; - u16 *pos; - efi_status_t ret; - - *load_options = NULL; - if (!env) - return EFI_SUCCESS; - size = sizeof(u16) * (utf8_utf16_strlen(env) + 1); - pos = calloc(size, 1); - if (!pos) - return EFI_OUT_OF_RESOURCES; - *load_options = pos; - utf8_utf16_strcpy(&pos, env); - ret = efi_set_load_options(handle, size, *load_options); - if (ret != EFI_SUCCESS) { - free(*load_options); - *load_options = NULL; - } - return ret; -} - -#if !CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) - -/** - * copy_fdt() - Copy the device tree to a new location available to EFI - * - * The FDT is copied to a suitable location within the EFI memory map. - * Additional 12 KiB are added to the space in case the device tree needs to be - * expanded later with fdt_open_into(). - * - * @fdtp: On entry a pointer to the flattened device tree. - * On exit a pointer to the copy of the flattened device tree. - * FDT start - * Return: status code - */ -static efi_status_t copy_fdt(void **fdtp) -{ - unsigned long fdt_ram_start = -1L, fdt_pages; - efi_status_t ret = 0; - void *fdt, *new_fdt; - u64 new_fdt_addr; - uint fdt_size; - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - u64 ram_start = gd->bd->bi_dram[i].start; - u64 ram_size = gd->bd->bi_dram[i].size; - - if (!ram_size) - continue; - - if (ram_start < fdt_ram_start) - fdt_ram_start = ram_start; - } - - /* - * Give us at least 12 KiB of breathing room in case the device tree - * needs to be expanded later. - */ - fdt = *fdtp; - fdt_pages = efi_size_in_pages(fdt_totalsize(fdt) + 0x3000); - fdt_size = fdt_pages << EFI_PAGE_SHIFT; - - ret = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES, - EFI_ACPI_RECLAIM_MEMORY, fdt_pages, - &new_fdt_addr); - if (ret != EFI_SUCCESS) { - log_err("ERROR: Failed to reserve space for FDT\n"); - goto done; - } - new_fdt = (void *)(uintptr_t)new_fdt_addr; - memcpy(new_fdt, fdt, fdt_totalsize(fdt)); - fdt_set_totalsize(new_fdt, fdt_size); - - *fdtp = (void *)(uintptr_t)new_fdt_addr; -done: - return ret; -} - -/** - * get_config_table() - get configuration table - * - * @guid: GUID of the configuration table - * Return: pointer to configuration table or NULL - */ -static void *get_config_table(const efi_guid_t *guid) -{ - size_t i; - - for (i = 0; i < systab.nr_tables; i++) { - if (!guidcmp(guid, &systab.tables[i].guid)) - return systab.tables[i].table; - } - return NULL; -} - -#endif /* !CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) */ - -/** - * efi_install_fdt() - install device tree - * - * If fdt is not EFI_FDT_USE_INTERNAL, the device tree located at that memory - * address will will be installed as configuration table, otherwise the device - * tree located at the address indicated by environment variable fdt_addr or as - * fallback fdtcontroladdr will be used. - * - * On architectures using ACPI tables device trees shall not be installed as - * configuration table. - * - * @fdt: address of device tree or EFI_FDT_USE_INTERNAL to use the - * the hardware device tree as indicated by environment variable - * fdt_addr or as fallback the internal device tree as indicated by - * the environment variable fdtcontroladdr - * Return: status code - */ -efi_status_t efi_install_fdt(void *fdt) -{ - /* - * The EBBR spec requires that we have either an FDT or an ACPI table - * but not both. - */ -#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) - if (fdt) { - log_warning("WARNING: Can't have ACPI table and device tree - ignoring DT.\n"); - return EFI_SUCCESS; - } -#else - struct bootm_headers img = { 0 }; - efi_status_t ret; - - if (fdt == EFI_FDT_USE_INTERNAL) { - const char *fdt_opt; - uintptr_t fdt_addr; - - /* Look for device tree that is already installed */ - if (get_config_table(&efi_guid_fdt)) - return EFI_SUCCESS; - /* Check if there is a hardware device tree */ - fdt_opt = env_get("fdt_addr"); - /* Use our own device tree as fallback */ - if (!fdt_opt) { - fdt_opt = env_get("fdtcontroladdr"); - if (!fdt_opt) { - log_err("ERROR: need device tree\n"); - return EFI_NOT_FOUND; - } - } - fdt_addr = hextoul(fdt_opt, NULL); - if (!fdt_addr) { - log_err("ERROR: invalid $fdt_addr or $fdtcontroladdr\n"); - return EFI_LOAD_ERROR; - } - fdt = map_sysmem(fdt_addr, 0); - } - - /* Install device tree */ - if (fdt_check_header(fdt)) { - log_err("ERROR: invalid device tree\n"); - return EFI_LOAD_ERROR; - } - - /* Prepare device tree for payload */ - ret = copy_fdt(&fdt); - if (ret) { - log_err("ERROR: out of memory\n"); - return EFI_OUT_OF_RESOURCES; - } - - if (image_setup_libfdt(&img, fdt, NULL)) { - log_err("ERROR: failed to process device tree\n"); - return EFI_LOAD_ERROR; - } - - /* Create memory reservations as indicated by the device tree */ - efi_carve_out_dt_rsv(fdt); - - efi_try_purge_kaslr_seed(fdt); - - if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) { - ret = efi_tcg2_measure_dtb(fdt); - if (ret == EFI_SECURITY_VIOLATION) { - log_err("ERROR: failed to measure DTB\n"); - return ret; - } - } - - /* Install device tree as UEFI table */ - ret = efi_install_configuration_table(&efi_guid_fdt, fdt); - if (ret != EFI_SUCCESS) { - log_err("ERROR: failed to install device tree\n"); - return ret; - } -#endif /* GENERATE_ACPI_TABLE */ - - return EFI_SUCCESS; -} - -/** - * do_bootefi_exec() - execute EFI binary - * - * The image indicated by @handle is started. When it returns the allocated - * memory for the @load_options is freed. - * - * @handle: handle of loaded image - * @load_options: load options - * Return: status code - * - * Load the EFI binary into a newly assigned memory unwinding the relocation - * information, install the loaded image protocol, and call the binary. - */ -static efi_status_t do_bootefi_exec(efi_handle_t handle, void *load_options) -{ - efi_status_t ret; - efi_uintn_t exit_data_size = 0; - u16 *exit_data = NULL; - struct efi_event *evt; - - /* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */ - switch_to_non_secure_mode(); - - /* - * The UEFI standard requires that the watchdog timer is set to five - * minutes when invoking an EFI boot option. - * - * Unified Extensible Firmware Interface (UEFI), version 2.7 Errata A - * 7.5. Miscellaneous Boot Services - EFI_BOOT_SERVICES.SetWatchdogTimer - */ - ret = efi_set_watchdog(300); - if (ret != EFI_SUCCESS) { - log_err("ERROR: Failed to set watchdog timer\n"); - goto out; - } - - /* Call our payload! */ - ret = EFI_CALL(efi_start_image(handle, &exit_data_size, &exit_data)); - if (ret != EFI_SUCCESS) { - log_err("## Application failed, r = %lu\n", - ret & ~EFI_ERROR_MASK); - if (exit_data) { - log_err("## %ls\n", exit_data); - efi_free_pool(exit_data); - } - } - - efi_restore_gd(); - -out: - free(load_options); - - if (IS_ENABLED(CONFIG_EFI_LOAD_FILE2_INITRD)) { - if (efi_initrd_deregister() != EFI_SUCCESS) - log_err("Failed to remove loadfile2 for initrd\n"); - } - - /* Notify EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR event group. */ - list_for_each_entry(evt, &efi_events, link) { - if (evt->group && - !guidcmp(evt->group, - &efi_guid_event_group_return_to_efibootmgr)) { - efi_signal_event(evt); - EFI_CALL(systab.boottime->close_event(evt)); - break; - } - } - - /* Control is returned to U-Boot, disable EFI watchdog */ - efi_set_watchdog(0); - - return ret; -} - -/** - * do_efibootmgr() - execute EFI boot manager - * - * Return: status code - */ -static int do_efibootmgr(void) -{ - efi_handle_t handle; - efi_status_t ret; - void *load_options; - - ret = efi_bootmgr_load(&handle, &load_options); - if (ret != EFI_SUCCESS) { - log_notice("EFI boot manager: Cannot load any image\n"); - return CMD_RET_FAILURE; - } - - ret = do_bootefi_exec(handle, load_options); - - if (ret != EFI_SUCCESS) - return CMD_RET_FAILURE; - - return CMD_RET_SUCCESS; -} - -/** - * do_bootefi_image() - execute EFI binary - * - * Set up memory image for the binary to be loaded, prepare device path, and - * then call do_bootefi_exec() to execute it. - * - * @image_opt: string with image start address - * @size_opt: string with image size or NULL - * Return: status code - */ -static int do_bootefi_image(const char *image_opt, const char *size_opt) -{ - void *image_buf; - unsigned long addr, size; - efi_status_t ret; - -#ifdef CONFIG_CMD_BOOTEFI_HELLO - if (!strcmp(image_opt, "hello")) { - image_buf = __efi_helloworld_begin; - size = __efi_helloworld_end - __efi_helloworld_begin; - efi_clear_bootdev(); - } else -#endif - { - addr = strtoul(image_opt, NULL, 16); - /* Check that a numeric value was passed */ - if (!addr) - return CMD_RET_USAGE; - image_buf = map_sysmem(addr, 0); - - if (size_opt) { - size = strtoul(size_opt, NULL, 16); - if (!size) - return CMD_RET_USAGE; - efi_clear_bootdev(); - } else { - if (image_buf != image_addr) { - log_err("No UEFI binary known at %s\n", - image_opt); - return CMD_RET_FAILURE; - } - size = image_size; - } - } - ret = efi_run_image(image_buf, size); - - if (ret != EFI_SUCCESS) - return CMD_RET_FAILURE; +static struct efi_device_path *test_image_path; +static struct efi_device_path *test_device_path; - return CMD_RET_SUCCESS; -} - -/** - * efi_run_image() - run loaded UEFI image - * - * @source_buffer: memory address of the UEFI image - * @source_size: size of the UEFI image - * Return: status code - */ -efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size) -{ - efi_handle_t mem_handle = NULL, handle; - struct efi_device_path *file_path = NULL; - struct efi_device_path *msg_path; - efi_status_t ret, ret2; - u16 *load_options; - - if (!bootefi_device_path || !bootefi_image_path) { - log_debug("Not loaded from disk\n"); - /* - * Special case for efi payload not loaded from disk, - * such as 'bootefi hello' or for example payload - * loaded directly into memory via JTAG, etc: - */ - file_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, - (uintptr_t)source_buffer, - source_size); - /* - * Make sure that device for device_path exist - * in load_image(). Otherwise, shell and grub will fail. - */ - ret = efi_install_multiple_protocol_interfaces(&mem_handle, - &efi_guid_device_path, - file_path, NULL); - if (ret != EFI_SUCCESS) - goto out; - msg_path = file_path; - } else { - file_path = efi_dp_append(bootefi_device_path, - bootefi_image_path); - msg_path = bootefi_image_path; - log_debug("Loaded from disk\n"); - } - - log_info("Booting %pD\n", msg_path); - - ret = EFI_CALL(efi_load_image(false, efi_root, file_path, source_buffer, - source_size, &handle)); - if (ret != EFI_SUCCESS) { - log_err("Loading image failed\n"); - goto out; - } - - /* Transfer environment variable as load options */ - ret = efi_env_set_load_options(handle, "bootargs", &load_options); - if (ret != EFI_SUCCESS) - goto out; - - ret = do_bootefi_exec(handle, load_options); - -out: - ret2 = efi_uninstall_multiple_protocol_interfaces(mem_handle, - &efi_guid_device_path, - file_path, NULL); - efi_free_pool(file_path); - return (ret != EFI_SUCCESS) ? ret : ret2; -} - -#ifdef CONFIG_CMD_BOOTEFI_SELFTEST static efi_status_t bootefi_run_prepare(const char *load_options_path, struct efi_device_path *device_path, struct efi_device_path *image_path, @@ -597,23 +65,26 @@ static efi_status_t bootefi_test_prepare efi_status_t ret; /* Construct a dummy device path */ - bootefi_device_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, 0, 0); - if (!bootefi_device_path) + test_device_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, 0, 0); + if (!test_device_path) return EFI_OUT_OF_RESOURCES; - bootefi_image_path = efi_dp_from_file(NULL, path); - if (!bootefi_image_path) { + test_image_path = efi_dp_from_file(NULL, path); + if (!test_image_path) { ret = EFI_OUT_OF_RESOURCES; goto failure; } - ret = bootefi_run_prepare(load_options_path, bootefi_device_path, - bootefi_image_path, image_objp, + ret = bootefi_run_prepare(load_options_path, test_device_path, + test_image_path, image_objp, loaded_image_infop); if (ret == EFI_SUCCESS) return ret; failure: + efi_free_pool(test_device_path); + efi_free_pool(test_image_path); + /* TODO: not sure calling clear function is necessary */ efi_clear_bootdev(); return ret; } @@ -638,6 +109,8 @@ static int do_efi_selftest(void) ret = EFI_CALL(efi_selftest(&image_obj->header, &systab)); efi_restore_gd(); free(loaded_image_info->load_options); + efi_free_pool(test_device_path); + efi_free_pool(test_image_path); if (ret != EFI_SUCCESS) efi_delete_handle(&image_obj->header); else @@ -645,7 +118,6 @@ static int do_efi_selftest(void) return ret != EFI_SUCCESS; } -#endif /* CONFIG_CMD_BOOTEFI_SELFTEST */ /** * do_bootefi() - execute `bootefi` command @@ -660,20 +132,15 @@ static int do_bootefi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { efi_status_t ret; - char *img_addr, *img_size, *str_copy, *pos; - void *fdt; + char *p; + void *fdt, *image_buf; + unsigned long addr, size; + void *image_addr; + size_t image_size; if (argc < 2) return CMD_RET_USAGE; - /* Initialize EFI drivers */ - ret = efi_init_obj_list(); - if (ret != EFI_SUCCESS) { - log_err("Error: Cannot initialize UEFI sub-system, r = %lu\n", - ret & ~EFI_ERROR_MASK); - return CMD_RET_FAILURE; - } - if (argc > 2) { uintptr_t fdt_addr; @@ -682,32 +149,81 @@ static int do_bootefi(struct cmd_tbl *cmdtp, int flag, int argc, } else { fdt = EFI_FDT_USE_INTERNAL; } - ret = efi_install_fdt(fdt); - if (ret == EFI_INVALID_PARAMETER) - return CMD_RET_USAGE; - else if (ret != EFI_SUCCESS) - return CMD_RET_FAILURE; - if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR)) { - if (!strcmp(argv[1], "bootmgr")) - return do_efibootmgr(); + if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR) && + !strcmp(argv[1], "bootmgr")) { + ret = efi_bootmgr_run(fdt); + + if (ret == EFI_INVALID_PARAMETER) + return CMD_RET_USAGE; + else if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; } -#ifdef CONFIG_CMD_BOOTEFI_SELFTEST - if (!strcmp(argv[1], "selftest")) + + if (IS_ENABLED(CONFIG_CMD_BOOTEFI_SELFTEST) && + !strcmp(argv[1], "selftest")) { + /* Initialize EFI drivers */ + ret = efi_init_obj_list(); + if (ret != EFI_SUCCESS) { + log_err("Error: Cannot initialize UEFI sub-system, r = %lu\n", + ret & ~EFI_ERROR_MASK); + return CMD_RET_FAILURE; + } + + ret = efi_install_fdt(fdt); + if (ret == EFI_INVALID_PARAMETER) + return CMD_RET_USAGE; + else if (ret != EFI_SUCCESS) + return CMD_RET_FAILURE; + return do_efi_selftest(); -#endif - str_copy = strdup(argv[1]); - if (!str_copy) { - log_err("Out of memory\n"); - return CMD_RET_FAILURE; } - pos = str_copy; - img_addr = strsep(&pos, ":"); - img_size = strsep(&pos, ":"); - ret = do_bootefi_image(img_addr, img_size); - free(str_copy); - return ret; + if (!IS_ENABLED(CONFIG_CMD_BOOTEFI_BINARY)) + return CMD_RET_SUCCESS; + + if (IS_ENABLED(CONFIG_CMD_BOOTEFI_HELLO) && + !strcmp(argv[1], "hello")) { + image_buf = __efi_helloworld_begin; + size = __efi_helloworld_end - __efi_helloworld_begin; + /* TODO: not sure calling clear function is necessary */ + efi_clear_bootdev(); + } else { + addr = strtoul(argv[1], NULL, 16); + /* Check that a numeric value was passed */ + if (!addr) + return CMD_RET_USAGE; + image_buf = map_sysmem(addr, 0); + + p = strchr(argv[1], ':'); + if (p) { + size = strtoul(++p, NULL, 16); + if (!size) + return CMD_RET_USAGE; + efi_clear_bootdev(); + } else { + /* Image should be already loaded */ + efi_get_image_parameters(&image_addr, &image_size); + + if (image_buf != image_addr) { + log_err("No UEFI binary known at %s\n", + argv[1]); + return CMD_RET_FAILURE; + } + size = image_size; + } + } + + ret = efi_binary_run(image_buf, size, fdt); + + if (ret == EFI_INVALID_PARAMETER) + return CMD_RET_USAGE; + else if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; } U_BOOT_LONGHELP(bootefi, diff --git a/cmd/bootflow.c b/cmd/bootflow.c index 4a47265ebd5..cc6dfae1668 100644 --- a/cmd/bootflow.c +++ b/cmd/bootflow.c @@ -543,9 +543,9 @@ static int do_bootflow_cmdline(struct cmd_tbl *cmdtp, int flag, int argc, op = argv[1]; arg = argv[2]; if (*op == 's') { - if (argc < 4) + if (argc < 3) return CMD_RET_USAGE; - val = argv[3]; + val = argv[3] ?: (const char *)BOOTFLOWCL_EMPTY; } switch (*op) { diff --git a/cmd/clk.c b/cmd/clk.c index c7c379d7a61..7bbcbfeda33 100644 --- a/cmd/clk.c +++ b/cmd/clk.c @@ -59,9 +59,10 @@ static void show_clks(struct udevice *dev, int depth, int last_flag) } } -int __weak soc_clk_dump(void) +static int soc_clk_dump(void) { struct udevice *dev; + const struct clk_ops *ops; printf(" Rate Usecnt Name\n"); printf("------------------------------------------\n"); @@ -69,10 +70,18 @@ int __weak soc_clk_dump(void) uclass_foreach_dev_probe(UCLASS_CLK, dev) show_clks(dev, -1, 0); + uclass_foreach_dev_probe(UCLASS_CLK, dev) { + ops = dev_get_driver_ops(dev); + if (ops && ops->dump) { + printf("\n%s %s:\n", dev->driver->name, dev->name); + ops->dump(dev); + } + } + return 0; } #else -int __weak soc_clk_dump(void) +static int soc_clk_dump(void) { puts("Not implemented\n"); return 1; diff --git a/cmd/efi_common.c b/cmd/efi_common.c index f4056096cd3..1aa2351fcdf 100644 --- a/cmd/efi_common.c +++ b/cmd/efi_common.c @@ -17,10 +17,8 @@ void efi_show_tables(struct efi_system_table *systab) for (i = 0; i < systab->nr_tables; i++) { struct efi_configuration_table *tab = &systab->tables[i]; - char guid_str[37]; - uuid_bin_to_str(tab->guid.b, guid_str, 1); - printf("%p %pUl %s\n", tab->table, guid_str, + printf("%p %pUl %s\n", tab->table, tab->guid.b, uuid_guid_get_str(tab->guid.b) ?: "(unknown)"); } } diff --git a/cmd/efidebug.c b/cmd/efidebug.c index 78ef16f4cb5..e10fbf891a4 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -1410,7 +1410,7 @@ static __maybe_unused int do_efi_test_bootmgr(struct cmd_tbl *cmdtp, int flag, } static struct cmd_tbl cmd_efidebug_test_sub[] = { -#ifdef CONFIG_CMD_BOOTEFI_BOOTMGR +#ifdef CONFIG_BOOTEFI_BOOTMGR U_BOOT_CMD_MKENT(bootmgr, CONFIG_SYS_MAXARGS, 1, do_efi_test_bootmgr, "", ""), #endif @@ -1604,7 +1604,7 @@ U_BOOT_LONGHELP(efidebug, " - show UEFI memory map\n" "efidebug tables\n" " - show UEFI configuration tables\n" -#ifdef CONFIG_CMD_BOOTEFI_BOOTMGR +#ifdef CONFIG_BOOTEFI_BOOTMGR "efidebug test bootmgr\n" " - run simple bootmgr for test\n" #endif diff --git a/cmd/part.c b/cmd/part.c index 0ce190005d3..c75f85acd52 100644 --- a/cmd/part.c +++ b/cmd/part.c @@ -308,9 +308,9 @@ U_BOOT_CMD( #ifdef CONFIG_PARTITION_TYPE_GUID "part type <interface> <dev>:<part>\n" " - print partition type\n" -#endif "part type <interface> <dev>:<part> <varname>\n" " - set environment variable to partition type\n" +#endif "part set <interface> <dev> type\n" " - set partition type for a device\n" "part types\n" diff --git a/cmd/ximg.c b/cmd/ximg.c index a50dd20b19a..0e7eead8d19 100644 --- a/cmd/ximg.c +++ b/cmd/ximg.c @@ -27,11 +27,6 @@ #include <asm/cache.h> #include <asm/io.h> -#ifndef CFG_SYS_XIMG_LEN -/* use 8MByte as default max gunzip size */ -#define CFG_SYS_XIMG_LEN 0x800000 -#endif - static int do_imgextract(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -52,7 +47,7 @@ do_imgextract(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) size_t fit_len; #endif #ifdef CONFIG_GZIP - uint unc_len = CFG_SYS_XIMG_LEN; + uint unc_len = CONFIG_SYS_XIMG_LEN; #endif uint8_t comp; diff --git a/common/cli_readline.c b/common/cli_readline.c index 06b8d465044..85453beed76 100644 --- a/common/cli_readline.c +++ b/common/cli_readline.c @@ -12,6 +12,8 @@ #include <bootretry.h> #include <cli.h> #include <command.h> +#include <hang.h> +#include <malloc.h> #include <time.h> #include <watchdog.h> #include <asm/global_data.h> @@ -85,7 +87,6 @@ static int hist_cur = -1; static unsigned hist_num; static char *hist_list[HIST_MAX]; -static char hist_lines[HIST_MAX][HIST_SIZE + 1]; /* Save room for NULL */ #define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1) @@ -97,8 +98,9 @@ static void getcmd_putchars(int count, int ch) getcmd_putch(ch); } -static void hist_init(void) +static int hist_init(void) { + unsigned char *hist; int i; hist_max = 0; @@ -106,10 +108,14 @@ static void hist_init(void) hist_cur = -1; hist_num = 0; - for (i = 0; i < HIST_MAX; i++) { - hist_list[i] = hist_lines[i]; - hist_list[i][0] = '\0'; - } + hist = calloc(HIST_MAX, HIST_SIZE + 1); + if (!hist) + return -ENOMEM; + + for (i = 0; i < HIST_MAX; i++) + hist_list[i] = hist + (i * (HIST_SIZE + 1)); + + return 0; } static void cread_add_to_hist(char *line) @@ -493,8 +499,9 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len, #else /* !CONFIG_CMDLINE_EDITING */ -static inline void hist_init(void) +static inline int hist_init(void) { + return 0; } static int cread_line(const char *const prompt, char *buf, unsigned int *len, @@ -643,8 +650,9 @@ int cli_readline_into_buffer(const char *const prompt, char *buffer, */ if (IS_ENABLED(CONFIG_CMDLINE_EDITING) && (gd->flags & GD_FLG_RELOC)) { if (!initted) { - hist_init(); - initted = 1; + rc = hist_init(); + if (rc == 0) + initted = 1; } if (prompt) diff --git a/common/command.c b/common/command.c index 846e16e2ada..7821c273dae 100644 --- a/common/command.c +++ b/common/command.c @@ -355,10 +355,9 @@ static int find_common_prefix(char *const argv[]) return len; } -static char tmp_buf[CONFIG_SYS_CBSIZE + 1]; /* copy of console I/O buffer */ - int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp) { + char tmp_buf[CONFIG_SYS_CBSIZE + 1]; /* copy of console I/O buffer */ int n = *np, col = *colp; char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */ char *cmdv[20]; diff --git a/common/spl/Kconfig b/common/spl/Kconfig index fc284a5bffc..cf7ffc9b112 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -378,7 +378,7 @@ config SPL_STACK default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB default 0x91ffb8 if ARCH_MX6 && !MX6_OCRAM_256KB default 0x118000 if MACH_SUN50I_H6 - default 0x58000 if MACH_SUN50I_H616 + default 0x52a00 if MACH_SUN50I_H616 default 0x40000 if MACH_SUN8I_R528 default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5 default 0x18000 if MACH_SUN9I diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index 056c1fbacfc..d11a31ee641 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -65,6 +65,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_CLK_IMX8=y CONFIG_CPU=y +CONFIG_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_IMX_LPI2C=y diff --git a/configs/bananapi-m2-pro_defconfig b/configs/bananapi-m2-pro_defconfig index 2a3958b0fd0..755bccb4a72 100644 --- a/configs/bananapi-m2-pro_defconfig +++ b/configs/bananapi-m2-pro_defconfig @@ -56,6 +56,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/configs/bananapi-m2s_defconfig b/configs/bananapi-m2s_defconfig index 405ce3a93a9..af8daced622 100644 --- a/configs/bananapi-m2s_defconfig +++ b/configs/bananapi-m2s_defconfig @@ -61,6 +61,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/configs/beelink-gt1-ultimate_defconfig b/configs/beelink-gt1-ultimate_defconfig index 1313dde92f5..00fdad8544b 100644 --- a/configs/beelink-gt1-ultimate_defconfig +++ b/configs/beelink-gt1-ultimate_defconfig @@ -46,7 +46,7 @@ CONFIG_PHY_REALTEK=y CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y -CONFIG_MDIO_MUX_MMIOREG=y +CONFIG_MDIO_MUX_MESON_GXL=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index 13c16bde3d8..ce60c509582 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -65,6 +65,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_CLK_IMX8=y CONFIG_CPU=y +CONFIG_GPIO_HOG=y CONFIG_FXL6408_GPIO=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index 20a38a38280..6a4244e3084 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -162,6 +162,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y +CONFIG_FSL_CAAM=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 01cfb96b0ee..04b738f5d9c 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -31,6 +31,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="gsc wd-disable" +CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 5d2e5a471cb..2f55a5b90fb 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -32,6 +32,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="gsc wd-disable" +CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig index 7ee454076c6..f5914ac2a80 100644 --- a/configs/imx8mp_data_modul_edm_sbc_defconfig +++ b/configs/imx8mp_data_modul_edm_sbc_defconfig @@ -169,6 +169,8 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y +CONFIG_IMX8M_DRAM_INLINE_ECC=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index 54c02dfd7ab..3f9b0e3733c 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -165,6 +165,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig index 6799f0c8b73..50c21d51b8d 100644 --- a/configs/imx8mp_dhcom_pdk3_defconfig +++ b/configs/imx8mp_dhcom_pdk3_defconfig @@ -167,6 +167,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 0b59971723c..683053b42f6 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -71,6 +71,7 @@ CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 730c359779a..d9c7018eeb8 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -32,6 +32,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="gsc wd-disable" +CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/jethub_j80_defconfig b/configs/jethub_j80_defconfig index b370e5d1d4d..15e410de829 100644 --- a/configs/jethub_j80_defconfig +++ b/configs/jethub_j80_defconfig @@ -54,7 +54,7 @@ CONFIG_PHY_MESON_GXL=y CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y -CONFIG_MDIO_MUX_MMIOREG=y +CONFIG_MDIO_MUX_MESON_GXL=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig index 28e90522451..59ef33723e4 100644 --- a/configs/khadas-vim2_defconfig +++ b/configs/khadas-vim2_defconfig @@ -51,7 +51,7 @@ CONFIG_PHY_REALTEK=y CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y -CONFIG_MDIO_MUX_MMIOREG=y +CONFIG_MDIO_MUX_MESON_GXL=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig index d27ab6f5907..5ed7c1a4083 100644 --- a/configs/khadas-vim_defconfig +++ b/configs/khadas-vim_defconfig @@ -45,7 +45,7 @@ CONFIG_PHY_MESON_GXL=y CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y -CONFIG_MDIO_MUX_MMIOREG=y +CONFIG_MDIO_MUX_MESON_GXL=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig index bc17b423a2d..f0ab19580c6 100644 --- a/configs/libretech-ac_defconfig +++ b/configs/libretech-ac_defconfig @@ -57,7 +57,7 @@ CONFIG_PHY_MESON_GXL=y CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y -CONFIG_MDIO_MUX_MMIOREG=y +CONFIG_MDIO_MUX_MESON_GXL=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig index baa9b1b3dbc..bb1a37a0cda 100644 --- a/configs/libretech-cc_defconfig +++ b/configs/libretech-cc_defconfig @@ -44,7 +44,7 @@ CONFIG_PHY_MESON_GXL=y CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y -CONFIG_MDIO_MUX_MMIOREG=y +CONFIG_MDIO_MUX_MESON_GXL=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig index ba74b241ab9..8949e240c93 100644 --- a/configs/libretech-cc_v2_defconfig +++ b/configs/libretech-cc_v2_defconfig @@ -52,7 +52,7 @@ CONFIG_PHY_MESON_GXL=y CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y -CONFIG_MDIO_MUX_MMIOREG=y +CONFIG_MDIO_MUX_MESON_GXL=y CONFIG_PHY=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y @@ -66,6 +66,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MESON_SPIFC=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig index cd138d696e7..a5dc3115fcb 100644 --- a/configs/libretech-s905d-pc_defconfig +++ b/configs/libretech-s905d-pc_defconfig @@ -53,7 +53,7 @@ CONFIG_PHY_REALTEK=y CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y -CONFIG_MDIO_MUX_MMIOREG=y +CONFIG_MDIO_MUX_MESON_GXL=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig index dabb4ca4ece..68f462eeff0 100644 --- a/configs/libretech-s912-pc_defconfig +++ b/configs/libretech-s912-pc_defconfig @@ -52,7 +52,7 @@ CONFIG_PHY_REALTEK=y CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y -CONFIG_MDIO_MUX_MMIOREG=y +CONFIG_MDIO_MUX_MESON_GXL=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/mt8365_evk_defconfig b/configs/mt8365_evk_defconfig new file mode 100644 index 00000000000..94b1f025fc0 --- /dev/null +++ b/configs/mt8365_evk_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=y +CONFIG_SYS_BOARD="mt8365_evk" +CONFIG_COUNTER_FREQUENCY=13000000 +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TEXT_BASE=0x4c000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt8365-evk" +CONFIG_TARGET_MT8365=y +CONFIG_IDENT_STRING=" mt8365-evk" +CONFIG_SYS_LOAD_ADDR=0x4c000000 +CONFIG_DEFAULT_FDT_FILE="mt8365-evk" +CONFIG_CLK=y +CONFIG_MMC_MTK=y +CONFIG_BAUDRATE=921600 +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_WDT=y +CONFIG_WDT_MTK=y diff --git a/configs/odroid-go-ultra_defconfig b/configs/odroid-go-ultra_defconfig index bc0bf9b8961..49d628b76ab 100644 --- a/configs/odroid-go-ultra_defconfig +++ b/configs/odroid-go-ultra_defconfig @@ -63,6 +63,7 @@ CONFIG_MESON_SERIAL=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index f13735e91c7..98aed846f1f 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -8,6 +8,7 @@ CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e CONFIG_DRAM_SUN50I_H616_TPR10=0xf83438 CONFIG_MACH_SUN50I_H616=y CONFIG_SUNXI_DRAM_H616_DDR3_1333=y +CONFIG_USB1_VBUS_PIN="PC16" CONFIG_R_I2C_ENABLE=y CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set @@ -19,6 +20,7 @@ CONFIG_SYS_I2C_SPEED=400000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y +CONFIG_AXP305_POWER=y CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_zero3_defconfig b/configs/orangepi_zero3_defconfig new file mode 100644 index 00000000000..5a019fed84b --- /dev/null +++ b/configs/orangepi_zero3_defconfig @@ -0,0 +1,32 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-orangepi-zero3" +CONFIG_SPL=y +CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707 +CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e +CONFIG_DRAM_SUN50I_H616_ODT_EN=0xaaaaeeee +CONFIG_DRAM_SUN50I_H616_TPR6=0x44000000 +CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663 +CONFIG_DRAM_SUN50I_H616_TPR11=0x24242624 +CONFIG_DRAM_SUN50I_H616_TPR12=0x0f0f100f +CONFIG_MACH_SUN50I_H616=y +CONFIG_SUNXI_DRAM_H616_LPDDR4=y +CONFIG_DRAM_CLK=792 +CONFIG_USB1_VBUS_PIN="PC16" +CONFIG_R_I2C_ENABLE=y +CONFIG_SPL_SPI_SUNXI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_SUN8I_EMAC=y +CONFIG_AXP313_POWER=y +CONFIG_SPI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y diff --git a/configs/p212_defconfig b/configs/p212_defconfig index b90391d9b5f..6b73607d641 100644 --- a/configs/p212_defconfig +++ b/configs/p212_defconfig @@ -40,7 +40,7 @@ CONFIG_PHY_MESON_GXL=y CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y -CONFIG_MDIO_MUX_MMIOREG=y +CONFIG_MDIO_MUX_MESON_GXL=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig index 9f3893dd60f..c698493ad27 100644 --- a/configs/paz00_defconfig +++ b/configs/paz00_defconfig @@ -46,6 +46,9 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_VIDEO=y diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index 1eee1e6c2ff..3af968d5512 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -70,6 +70,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 48364c7548e..5b615daf4a8 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -76,6 +76,8 @@ CONFIG_DM_PMIC=y CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y @@ -95,3 +97,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/radxa-zero2_defconfig b/configs/radxa-zero2_defconfig index e9415762ff3..b795681b3f0 100644 --- a/configs/radxa-zero2_defconfig +++ b/configs/radxa-zero2_defconfig @@ -52,6 +52,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 6a95ab3977a..43fc87d3ce8 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -23,7 +23,7 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000 -CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTSTD_DEFAULTS=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};" CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb" diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index b15e7d24db1..bfd94c3ba94 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -72,6 +72,7 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_BOARD=y @@ -124,6 +125,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_JH7110=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y +CONFIG_SYSRESET=y CONFIG_TIMER_EARLY=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -133,3 +135,7 @@ CONFIG_USB_EHCI_PCI=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_PCI=y CONFIG_USB_KEYBOARD=y +# CONFIG_WATCHDOG is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_STARFIVE=y diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig index 78086018087..cdd6ba8baed 100644 --- a/configs/verdin-am62_a53_defconfig +++ b/configs/verdin-am62_a53_defconfig @@ -17,6 +17,7 @@ CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="k3-am625-verdin-wifi-dev" CONFIG_SPL_TEXT_BASE=0x80080000 +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y @@ -33,7 +34,6 @@ CONFIG_SYS_MEMTEST_END=0xB0000000 CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 -CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=1 diff --git a/configs/wetek-core2_defconfig b/configs/wetek-core2_defconfig index 9bf3de9e7aa..01ffb8bbd75 100644 --- a/configs/wetek-core2_defconfig +++ b/configs/wetek-core2_defconfig @@ -46,7 +46,7 @@ CONFIG_PHY_REALTEK=y CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y CONFIG_ETH_DESIGNWARE_MESON8B=y -CONFIG_MDIO_MUX_MMIOREG=y +CONFIG_MDIO_MUX_MESON_GXL=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig index 318951e19c2..e805e0952b3 100644 --- a/configs/x96_mate_defconfig +++ b/configs/x96_mate_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 +CONFIG_AXP305_POWER=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig new file mode 100644 index 00000000000..2689495057b --- /dev/null +++ b/configs/xilinx_mbv32_defconfig @@ -0,0 +1,30 @@ +CONFIG_RISCV=y +CONFIG_TEXT_BASE=0x21200000 +CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" +CONFIG_DEBUG_UART_BASE=0x40600000 +CONFIG_DEBUG_UART_CLOCK=1000000 +CONFIG_SYS_CLK_FREQ=100000000 +CONFIG_BOOT_SCRIPT_OFFSET=0x0 +CONFIG_SYS_LOAD_ADDR=0x80200000 +CONFIG_DEBUG_UART=y +CONFIG_TARGET_XILINX_MBV=y +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMD_MII is not set +CONFIG_CMD_TIMER=y +CONFIG_OF_EMBED=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_MTD=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_XILINX_UARTLITE=y +CONFIG_XILINX_TIMER=y +CONFIG_PANIC_HANG=y diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig new file mode 100644 index 00000000000..c724d1bad74 --- /dev/null +++ b/configs/xilinx_mbv32_smode_defconfig @@ -0,0 +1,32 @@ +CONFIG_RISCV=y +CONFIG_TEXT_BASE=0x21200000 +CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" +CONFIG_DEBUG_UART_BASE=0x40600000 +CONFIG_DEBUG_UART_CLOCK=1000000 +CONFIG_SYS_CLK_FREQ=100000000 +CONFIG_BOOT_SCRIPT_OFFSET=0x0 +CONFIG_SYS_LOAD_ADDR=0x80200000 +CONFIG_TARGET_XILINX_MBV=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMD_MII is not set +CONFIG_CMD_TIMER=y +CONFIG_OF_EMBED=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_MTD=y +CONFIG_DEBUG_UART_UARTLITE=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_XILINX_UARTLITE=y +# CONFIG_RISCV_TIMER is not set +CONFIG_XILINX_TIMER=y +CONFIG_PANIC_HANG=y diff --git a/disk/part_amiga.h b/disk/part_amiga.h index 42f5eb0f941..dfa70bdb8a8 100644 --- a/disk/part_amiga.h +++ b/disk/part_amiga.h @@ -7,7 +7,6 @@ #ifndef _DISK_PART_AMIGA_H #define _DISK_PART_AMIGA_H -#include <common.h> #if CONFIG_IS_ENABLED(ISO_PARTITION) /* Make the buffers bigger if ISO partition support is enabled -- CD-ROMS diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst index 23902dee89e..5f8db126657 100644 --- a/doc/arch/sandbox/sandbox.rst +++ b/doc/arch/sandbox/sandbox.rst @@ -424,15 +424,59 @@ space. See existing code for examples. VPL (Verifying Program Loader) ------------------------------ -Sandbox provides an example build of vpl called `sandbox_vpl`. This can be run -using:: +Sandbox provides an example build of vpl called `sandbox_vpl`. To build it: - /path/to/sandbox_vpl/tpl/u-boot-tpl -D +.. code-block:: bash + + make sandbox_vpl_defconfig all + +This can be run using: + +.. code-block:: bash + + ./tpl/u-boot-tpl -d u-boot.dtb It starts up TPL (first-stage init), then VPL, then runs SPL and finally U-Boot proper, following the normal flow for a verified boot. At present, no verification is actually implemented. +Here is an example trace:: + + U-Boot TPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700) + Trying to boot from sandbox_image + Trying to boot from sandbox_file + + U-Boot VPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700) + Trying to boot from vbe_simple + Trying to boot from sandbox_image + Trying to boot from sandbox_file + + U-Boot SPL 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700) + Trying to boot from vbe_simple + Trying to boot from sandbox_image + Trying to boot from sandbox_file + + + U-Boot 2024.01-rc2-00129 (Nov 19 2023 - 08:10:12 -0700) + + Reset Status: COLD + Model: sandbox + DRAM: 256 MiB + using memory 0x1b576000-0x1f578000 for malloc() + + Warning: host_lo MAC addresses don't match: + Address in ROM is 96:cd:ef:82:78:51 + Address in environment is 02:00:11:22:33:44 + Core: 103 devices, 51 uclasses, devicetree: board + MMC: + Loading Environment from nowhere... OK + In: serial,cros-ec-keyb,usbkbd + Out: serial,vidconsole + Err: serial,vidconsole + Model: sandbox + Net: eth0: host_lo, eth1: host_enp14s0, eth2: host_eth6, eth3: host_wlp15s0, eth4: host_virbr0, eth5: host_docker0, eth6: eth@10002000 + Hit any key to stop autoboot: 1 + Debugging the init sequence --------------------------- diff --git a/doc/board/allwinner/sunxi.rst b/doc/board/allwinner/sunxi.rst index 797222d8d34..d0c89b956b1 100644 --- a/doc/board/allwinner/sunxi.rst +++ b/doc/board/allwinner/sunxi.rst @@ -251,8 +251,7 @@ the SPI flash content from Linux, using the `MTD utils`_:: # apt-get install mtd-utils # mtdinfo - # mtd_debug erase /dev/mtdX 0 0xf0000 - # mtd_debug write /dev/mtdX 0 0xf0000 u-boot-sunxi-with-spl.bin + # flashcp -v u-boot-sunxi-with-spl.bin /dev/mtdX ``/dev/mtdX`` needs to be replaced with the respective device name, as listed in the output of ``mtdinfo``. diff --git a/doc/build/clang.rst b/doc/build/clang.rst index cc265506c2f..09bb988e923 100644 --- a/doc/build/clang.rst +++ b/doc/build/clang.rst @@ -11,14 +11,6 @@ The ARM backend can be instructed not to use the r9 and x18 registers using supported inline assembly is needed to get and set the r9 or x18 value. This leads to larger code then strictly necessary, but at least works. -**NOTE:** target compilation only work for _some_ ARM boards at the moment. -Also AArch64 is not supported currently due to a lack of private libgcc -support. Boards which reassign gd in c will also fail to compile, but there is -in no strict reason to do so in the ARM world, since crt0.S takes care of this. -These assignments can be avoided by changing the init calls but this is not in -mainline yet. - - Debian based ------------ @@ -28,14 +20,20 @@ Required packages can be installed via apt, e.g. sudo apt-get install clang -Note that we still use binutils for some tools so we must continue to set -CROSS_COMPILE. To compile U-Boot with Clang on Linux without IAS use e.g. +We make use of the CROSS_COMPILE variable to derive the build target which is +passed as the --target parameter to clang. + +The CROSS_COMPILE variable further determines the paths to other build +tools. As assembler we use the binary pointed to by '$(CROSS_COMPILE)as' +instead of the LLVM integrated assembler (IAS). + +Here is an example demonstrating building U-Boot for the Raspberry Pi 2 +using clang: .. code-block:: bash make HOSTCC=clang rpi_2_defconfig - make HOSTCC=clang CROSS_COMPILE=arm-linux-gnueabi- \ - CC="clang -target arm-linux-gnueabi" -j8 + make HOSTCC=clang CROSS_COMPILE=arm-linux-gnueabi- CC=clang -j8 It can also be used to compile sandbox: diff --git a/doc/chromium/files/chromebook_jerry.its b/doc/chromium/files/chromebook_jerry.its index 7505a20535b..02e5e1340f3 100644 --- a/doc/chromium/files/chromebook_jerry.its +++ b/doc/chromium/files/chromebook_jerry.its @@ -15,7 +15,7 @@ load = <0>; entry = <0>; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; @@ -26,7 +26,7 @@ arch = "arm"; compression = "none"; hash-1{ - algo = "sha1"; + algo = "sha256"; }; }; }; diff --git a/doc/chromium/files/nyan-big.its b/doc/chromium/files/nyan-big.its index bd412915e95..60bdffbb829 100644 --- a/doc/chromium/files/nyan-big.its +++ b/doc/chromium/files/nyan-big.its @@ -15,7 +15,7 @@ load = <0>; entry = <0>; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; @@ -26,7 +26,7 @@ arch = "arm"; compression = "none"; hash-1{ - algo = "sha1"; + algo = "sha256"; }; }; }; diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 37e9fc1a34d..8fe77f23b6e 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -72,7 +72,7 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2024.01-rc4 was released on Mon 04 December 2023. -.. * U-Boot v2024.01-rc5 was released on Mon 18 December 2023. +* U-Boot v2024.01-rc5 was released on Mon 18 December 2023. .. * U-Boot v2024.01-rc6 was released on Tue 02 January 2024. diff --git a/doc/develop/sending_patches.rst b/doc/develop/sending_patches.rst index ba73d0d11b4..5a6962f1021 100644 --- a/doc/develop/sending_patches.rst +++ b/doc/develop/sending_patches.rst @@ -363,7 +363,7 @@ A Custodian has additional privileges and can: * Awaiting Upstream - * Superseeded + * Superseded * Deferred @@ -399,7 +399,7 @@ today. Not all states are used by all custodians. and has not merged yet to master, or has queued the patch up to be submitted to be merged, but has not yet. -* Superseeded: Patches are marked as 'superseeded' when the poster submits a +* Superseded: Patches are marked as 'superseded' when the poster submits a new version of these patches. * Deferred: Deferred usually means the patch depends on something else that diff --git a/doc/usage/cmd/imxtract.rst b/doc/usage/cmd/imxtract.rst index eb64b1cefab..16be60b4aab 100644 --- a/doc/usage/cmd/imxtract.rst +++ b/doc/usage/cmd/imxtract.rst @@ -45,14 +45,14 @@ Examples With verify=no incorrect hashes, signatures, or check sums don't stop the extraction. But correct hashes are still indicated in the output -(here: md5, sha1). +(here: sha256, sha512). .. code-block:: console => setenv verify no => imxtract $loadaddr kernel-1 $kernel_addr_r ## Copying 'kernel-1' subimage from FIT image at 40200000 ... - md5+ sha1+ Loading part 0 ... OK + sha256+ sha512+ Loading part 0 ... OK => With verify=yes incorrect hashes, signatures, or check sums stop the extraction. @@ -62,7 +62,7 @@ With verify=yes incorrect hashes, signatures, or check sums stop the extraction. => setenv verify yes => imxtract $loadaddr kernel-1 $kernel_addr_r ## Copying 'kernel-1' subimage from FIT image at 40200000 ... - md5 error! + sha256 error! Bad hash value for 'hash-1' hash node in 'kernel-1' image node Bad Data Hash => diff --git a/doc/usage/fit/beaglebone_vboot.rst b/doc/usage/fit/beaglebone_vboot.rst index a102be187bd..cd6bb141910 100644 --- a/doc/usage/fit/beaglebone_vboot.rst +++ b/doc/usage/fit/beaglebone_vboot.rst @@ -145,7 +145,7 @@ Put this into a file in that directory called sign.its:: load = <0x80008000>; entry = <0x80008000>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; fdt-1 { @@ -155,7 +155,7 @@ Put this into a file in that directory called sign.its:: arch = "arm"; compression = "none"; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; }; @@ -165,7 +165,7 @@ Put this into a file in that directory called sign.its:: kernel = "kernel"; fdt = "fdt-1"; signature-1 { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; key-name-hint = "dev"; sign-images = "fdt", "kernel"; }; @@ -227,8 +227,8 @@ You should see something like this:: OS: Linux Load Address: 0x80008000 Entry Point: 0x80008000 - Hash algo: sha1 - Hash value: c94364646427e10f423837e559898ef02c97b988 + Hash algo: sha256 + Hash value: 51b2adf9c1016ed46f424d85dcc6c34c46a20b9bee7227e06a6b6320ca5d35c1 Image 1 (fdt-1) Description: beaglebone-black Created: Sun Jun 1 12:50:30 2014 @@ -236,8 +236,8 @@ You should see something like this:: Compression: uncompressed Data Size: 31547 Bytes = 30.81 kB = 0.03 MB Architecture: ARM - Hash algo: sha1 - Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d + Hash algo: sha256 + Hash value: 807d5842a04132261ba092373bd40c78991bc7ce173d1175cd976ec37858e7cd Default Configuration: 'conf-1' Configuration 0 (conf-1) Description: unavailable @@ -255,11 +255,11 @@ You can also run fit_check_sign to check it:: which results in:: - Verifying Hash Integrity ... sha1,rsa2048:dev+ + Verifying Hash Integrity ... sha256,rsa2048:dev+ ## Loading kernel from FIT Image at 7fc6ee469000 ... Using 'conf-1' configuration Verifying Hash Integrity ... - sha1,rsa2048:dev+ + sha256,rsa2048:dev+ OK Trying 'kernel' kernel subimage @@ -272,10 +272,10 @@ which results in:: OS: Linux Load Address: 0x80008000 Entry Point: 0x80008000 - Hash algo: sha1 - Hash value: c94364646427e10f423837e559898ef02c97b988 + Hash algo: sha256 + Hash value: 51b2adf9c1016ed46f424d85dcc6c34c46a20b9bee7227e06a6b6320ca5d35c1 Verifying Hash Integrity ... - sha1+ + sha256+ OK Unimplemented compression type 4 @@ -288,10 +288,10 @@ which results in:: Compression: uncompressed Data Size: 31547 Bytes = 30.81 kB = 0.03 MB Architecture: ARM - Hash algo: sha1 - Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d + Hash algo: sha256 + Hash value: 807d5842a04132261ba092373bd40c78991bc7ce173d1175cd976ec37858e7cd Verifying Hash Integrity ... - sha1+ + sha256+ OK Loading Flat Device Tree ... OK @@ -303,14 +303,14 @@ which results in:: Signature check OK -At the top, you see "sha1,rsa2048:dev+". This means that it checked an RSA key -of size 2048 bits using SHA1 as the hash algorithm. The key name checked was +At the top, you see "sha256,rsa2048:dev+". This means that it checked an RSA key +of size 2048 bits using SHA256 as the hash algorithm. The key name checked was 'dev' and the '+' means that it verified. If it showed '-' that would be bad. Once the configuration is verified it is then possible to rely on the hashes in each image referenced by that configuration. So fit_check_sign goes on to load each of the images. We have a kernel and an FDT but no ramkdisk. In each -case fit_check_sign checks the hash and prints sha1+ meaning that the SHA1 +case fit_check_sign checks the hash and prints sha256+ meaning that the SHA256 hash verified. This means that none of the images has been tampered with. There is a test in test/vboot which uses U-Boot's sandbox build to verify that @@ -328,11 +328,11 @@ This tells us that the kernel starts at byte offset 168 (decimal) in image.fit and extends for about 7MB. Try changing a byte at 0x2000 (say) and run fit_check_sign again. You should see something like:: - Verifying Hash Integrity ... sha1,rsa2048:dev+ + Verifying Hash Integrity ... sha256,rsa2048:dev+ ## Loading kernel from FIT Image at 7f5a39571000 ... Using 'conf-1' configuration Verifying Hash Integrity ... - sha1,rsa2048:dev+ + sha256,rsa2048:dev+ OK Trying 'kernel' kernel subimage @@ -345,10 +345,10 @@ fit_check_sign again. You should see something like:: OS: Linux Load Address: 0x80008000 Entry Point: 0x80008000 - Hash algo: sha1 - Hash value: c94364646427e10f423837e559898ef02c97b988 + Hash algo: sha256 + Hash value: 51b2adf9c1016ed46f424d85dcc6c34c46a20b9bee7227e06a6b6320ca5d35c1 Verifying Hash Integrity ... - sha1 error + sha256 error Bad hash value for 'hash-1' hash node in 'kernel' image node Bad Data Hash @@ -361,10 +361,10 @@ fit_check_sign again. You should see something like:: Compression: uncompressed Data Size: 31547 Bytes = 30.81 kB = 0.03 MB Architecture: ARM - Hash algo: sha1 - Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d + Hash algo: sha256 + Hash value: 807d5842a04132261ba092373bd40c78991bc7ce173d1175cd976ec37858e7cd Verifying Hash Integrity ... - sha1+ + sha256+ OK Loading Flat Device Tree ... OK @@ -419,13 +419,13 @@ need to change the hash to match. Let's simulate that by changing a byte of the hash:: fdtget -tx image.fit /images/kernel/hash-1 value - c9436464 6427e10f 423837e5 59898ef0 2c97b988 - fdtput -tx image.fit /images/kernel/hash-1 value c9436464 6427e10f 423837e5 59898ef0 2c97b981 + 51b2adf9 c1016ed4 6f424d85 dcc6c34c 46a20b9b ee7227e0 6a6b6320 ca5d35c1 + fdtput -tx image.fit /images/kernel/hash-1 value 51b2adf9 c1016ed4 6f424d85 dcc6c34c 46a20b9b ee7227e0 6a6b6320 ca5d35c8 Now check it again:: $UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb - Verifying Hash Integrity ... sha1,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13 + Verifying Hash Integrity ... sha256,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13 rsa_verify_with_keynode: RSA failed to verify: -13 - Failed to verify required signature 'key-dev' @@ -446,7 +446,7 @@ running the mkimage link again. Then:: fdtput -p image.fit /configurations/conf-1/signature-1 value fred $UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb Verifying Hash Integrity ... - - sha1,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13 + sha256,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13 rsa_verify_with_keynode: RSA failed to verify: -13 - Failed to verify required signature 'key-dev' @@ -528,7 +528,7 @@ You should then see something like this:: U-Boot# bootm 82000000 ## Loading kernel from FIT Image at 82000000 ... Using 'conf-1' configuration - Verifying Hash Integrity ... sha1,rsa2048:dev+ OK + Verifying Hash Integrity ... sha256,rsa2048:dev+ OK Trying 'kernel' kernel subimage Description: unavailable Created: 2014-06-01 19:32:54 UTC @@ -540,9 +540,9 @@ You should then see something like this:: OS: Linux Load Address: 0x80008000 Entry Point: 0x80008000 - Hash algo: sha1 - Hash value: c94364646427e10f423837e559898ef02c97b988 - Verifying Hash Integrity ... sha1+ OK + Hash algo: sha256 + Hash value: 51b2adf9c1016ed46f424d85dcc6c34c46a20b9bee7227e06a6b6320ca5d35c1 + Verifying Hash Integrity ... sha256+ OK ## Loading fdt from FIT Image at 82000000 ... Using 'conf-1' configuration Trying 'fdt-1' fdt subimage @@ -553,9 +553,9 @@ You should then see something like this:: Data Start: 0x8276e2ec Data Size: 31547 Bytes = 30.8 KiB Architecture: ARM - Hash algo: sha1 - Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d - Verifying Hash Integrity ... sha1+ OK + Hash algo: sha256 + Hash value: 807d5842a04132261ba092373bd40c78991bc7ce173d1175cd976ec37858e7cd + Verifying Hash Integrity ... sha256+ OK Booting using the fdt blob at 0x8276e2ec Uncompressing Kernel Image ... OK Loading Device Tree to 8fff5000, end 8ffffb3a ... OK diff --git a/doc/usage/fit/howto.rst b/doc/usage/fit/howto.rst index def12a70f7b..b5097d4460b 100644 --- a/doc/usage/fit/howto.rst +++ b/doc/usage/fit/howto.rst @@ -8,7 +8,7 @@ Overview The new uImage format allows more flexibility in handling images of various types (kernel, ramdisk, etc.), it also enhances integrity protection of images -with sha1 and md5 checksums. +with cryptographic checksums. Two auxiliary tools are needed on the development host system in order to create an uImage in the new format: mkimage and dtc, although only one @@ -99,7 +99,7 @@ started by ATF where SPL is loading U-Boot (as loadables) and ATF (as firmware). load = <0x8 0x8000000>; entry = <0x8 0x8000000>; hash { - algo = "md5"; + algo = "sha256"; }; }; atf { @@ -112,7 +112,7 @@ started by ATF where SPL is loading U-Boot (as loadables) and ATF (as firmware). load = <0xfffea000>; entry = <0xfffea000>; hash { - algo = "md5"; + algo = "sha256"; }; }; fdt_1 { @@ -123,7 +123,7 @@ started by ATF where SPL is loading U-Boot (as loadables) and ATF (as firmware). compression = "none"; load = <0x100000>; hash { - algo = "md5"; + algo = "sha256"; }; }; }; @@ -190,8 +190,8 @@ its contents: Entry Point: 0x00000000 Hash algo: crc32 Hash value: 2ae2bb40 - Hash algo: sha1 - Hash value: 3c200f34e2c226ddc789240cca0c59fc54a67cf4 + Hash algo: sha256 + Hash value: c22f6bb5a3f96942507a37e7d6a9333ebdc7da57971bc4c082113fe082fdc40f Default Configuration: 'config-1' Configuration 0 (config-1) Description: Boot Linux kernel @@ -236,8 +236,8 @@ specific to the new image format). Entry Point: 0x00000000 Hash algo: crc32 Hash value: 2ae2bb40 - Hash algo: sha1 - Hash value: 3c200f34e2c226ddc789240cca0c59fc54a67cf4 + Hash algo: sha256 + Hash value: c22f6bb5a3f96942507a37e7d6a9333ebdc7da57971bc4c082113fe082fdc40f Default Configuration: 'config-1' Configuration 0 (config-1) Description: Boot Linux kernel @@ -258,8 +258,8 @@ specific to the new image format). Entry Point: 0x00000000 Hash algo: crc32 Hash value: 2ae2bb40 - Hash algo: sha1 - Hash value: 3c200f34e2c226ddc789240cca0c59fc54a67cf4 + Hash algo: sha256 + Hash value: c22f6bb5a3f96942507a37e7d6a9333ebdc7da57971bc4c082113fe082fdc40f Verifying Hash Integrity ... crc32+ sha1+ OK Uncompressing Kernel Image ... OK Memory BAT mapping: BAT2=256Mb, BAT3=0Mb, residual: 0Mb @@ -302,8 +302,8 @@ modified to take the files from some other location if needed): Entry Point: 0x00000000 Hash algo: crc32 Hash value: 2c0cc807 - Hash algo: sha1 - Hash value: 264b59935470e42c418744f83935d44cdf59a3bb + Hash algo: sha256 + Hash value: a3e9e18b793873827d27c97edfbca67c404a1972d9f36cf48e73ff85d69a422c Image 1 (fdt-1) Description: Flattened Device Tree blob Type: Flat Device Tree @@ -312,8 +312,8 @@ modified to take the files from some other location if needed): Architecture: PowerPC Hash algo: crc32 Hash value: 0d655d71 - Hash algo: sha1 - Hash value: 25ab4e15cd4b8a5144610394560d9c318ce52def + Hash algo: sha256 + Hash value: e9b9a40c5e2e12213ac819e7ccad7271ef43eb5edf9b421f0fa0b4b51bfdb214 Default Configuration: 'conf-1' Configuration 0 (conf-1) Description: Boot Linux kernel with FDT blob @@ -353,8 +353,8 @@ inspected and booted: Entry Point: 0x00000000 Hash algo: crc32 Hash value: 2c0cc807 - Hash algo: sha1 - Hash value: 264b59935470e42c418744f83935d44cdf59a3bb + Hash algo: sha256 + Hash value: a3e9e18b793873827d27c97edfbca67c404a1972d9f36cf48e73ff85d69a422c Image 1 (fdt-1) Description: Flattened Device Tree blob Type: Flat Device Tree @@ -364,8 +364,8 @@ inspected and booted: Architecture: PowerPC Hash algo: crc32 Hash value: 0d655d71 - Hash algo: sha1 - Hash value: 25ab4e15cd4b8a5144610394560d9c318ce52def + Hash algo: sha256 + Hash value: e9b9a40c5e2e12213ac819e7ccad7271ef43eb5edf9b421f0fa0b4b51bfdb214 Default Configuration: 'conf-1' Configuration 0 (conf-1) Description: Boot Linux kernel with FDT blob @@ -387,7 +387,7 @@ inspected and booted: Hash algo: crc32 Hash value: 2c0cc807 Hash algo: sha1 - Hash value: 264b59935470e42c418744f83935d44cdf59a3bb + Hash value: a3e9e18b793873827d27c97edfbca67c404a1972d9f36cf48e73ff85d69a422c Verifying Hash Integrity ... crc32+ sha1+ OK Uncompressing Kernel Image ... OK ## Flattened Device Tree from FIT Image at 00900000 @@ -402,7 +402,7 @@ inspected and booted: Hash algo: crc32 Hash value: 0d655d71 Hash algo: sha1 - Hash value: 25ab4e15cd4b8a5144610394560d9c318ce52def + Hash value: e9b9a40c5e2e12213ac819e7ccad7271ef43eb5edf9b421f0fa0b4b51bfdb214 Verifying Hash Integrity ... crc32+ sha1+ OK Booting using the fdt blob at 0xa0abdc Loading Device Tree to 007fc000, end 007fffff ... OK diff --git a/doc/usage/fit/kernel.rst b/doc/usage/fit/kernel.rst index 012a81efead..e56017985b2 100644 --- a/doc/usage/fit/kernel.rst +++ b/doc/usage/fit/kernel.rst @@ -25,7 +25,7 @@ Single kernel algo = "crc32"; }; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; }; @@ -59,7 +59,7 @@ For x86 a setup node is also required: see x86-fit-boot:: load = <0x01000000>; entry = <0x00000000>; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; @@ -73,7 +73,7 @@ For x86 a setup node is also required: see x86-fit-boot:: load = <0x00090000>; entry = <0x00090000>; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; }; diff --git a/doc/usage/fit/kernel_fdt.rst b/doc/usage/fit/kernel_fdt.rst index 8eee13af780..9cc26fb7831 100644 --- a/doc/usage/fit/kernel_fdt.rst +++ b/doc/usage/fit/kernel_fdt.rst @@ -25,7 +25,7 @@ Single kernel and FDT blob algo = "crc32"; }; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; fdt-1 { @@ -38,7 +38,7 @@ Single kernel and FDT blob algo = "crc32"; }; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; }; diff --git a/doc/usage/fit/kernel_fdts_compressed.rst b/doc/usage/fit/kernel_fdts_compressed.rst index 0b169c7c27c..b57871da58b 100644 --- a/doc/usage/fit/kernel_fdts_compressed.rst +++ b/doc/usage/fit/kernel_fdts_compressed.rst @@ -28,7 +28,7 @@ string to match directly. algo = "crc32"; }; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; fdt@1 { @@ -41,7 +41,7 @@ string to match directly. algo = "crc32"; }; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; fdt@2 { @@ -54,7 +54,7 @@ string to match directly. algo = "crc32"; }; hash-2 { - algo = "sha1"; + algo = "sha256"; }; }; }; diff --git a/doc/usage/fit/multi-with-fpga.rst b/doc/usage/fit/multi-with-fpga.rst index 28d7d5d2626..4c7f1bebd5a 100644 --- a/doc/usage/fit/multi-with-fpga.rst +++ b/doc/usage/fit/multi-with-fpga.rst @@ -20,7 +20,7 @@ This example makes use of the 'loadables' field:: compression = "none"; load = <0x10000000>; hash-1 { - algo = "md5"; + algo = "sha256"; }; }; @@ -33,7 +33,7 @@ This example makes use of the 'loadables' field:: load = <0x30000000>; compatible = "u-boot,fpga-legacy" hash-1 { - algo = "md5"; + algo = "sha256"; }; }; @@ -47,7 +47,7 @@ This example makes use of the 'loadables' field:: load = <0x8000>; entry = <0x8000>; hash-1 { - algo = "md5"; + algo = "sha256"; }; }; }; diff --git a/doc/usage/fit/multi-with-loadables.rst b/doc/usage/fit/multi-with-loadables.rst index a0241df96ca..7849cb544f1 100644 --- a/doc/usage/fit/multi-with-loadables.rst +++ b/doc/usage/fit/multi-with-loadables.rst @@ -22,7 +22,7 @@ This example makes use of the 'loadables' field:: load = <0xa0000000>; entry = <0xa0000000>; hash-1 { - algo = "md5"; + algo = "sha256"; }; }; @@ -34,7 +34,7 @@ This example makes use of the 'loadables' field:: compression = "none"; load = <0xb0000000>; hash-1 { - algo = "md5"; + algo = "sha256"; }; }; @@ -46,7 +46,7 @@ This example makes use of the 'loadables' field:: compression = "none"; load = <0xb0400000>; hash-1 { - algo = "md5"; + algo = "sha256"; }; }; @@ -60,7 +60,7 @@ This example makes use of the 'loadables' field:: load = <0xa0000000>; entry = <0xa0000000>; hash-1 { - algo = "md5"; + algo = "sha256"; }; }; }; diff --git a/doc/usage/fit/multi.rst b/doc/usage/fit/multi.rst index 2e6ae58c409..e68752b2ad0 100644 --- a/doc/usage/fit/multi.rst +++ b/doc/usage/fit/multi.rst @@ -22,10 +22,10 @@ Multiple kernels, ramdisks and FDT blobs load = <00000000>; entry = <00000000>; hash-1 { - algo = "md5"; + algo = "sha256"; }; hash-2 { - algo = "sha1"; + algo = "sha512"; }; }; @@ -39,7 +39,7 @@ Multiple kernels, ramdisks and FDT blobs load = <00000000>; entry = <00000000>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; @@ -53,7 +53,7 @@ Multiple kernels, ramdisks and FDT blobs load = <00000000>; entry = <00000000>; hash-1 { - algo = "md5"; + algo = "sha256"; }; }; @@ -67,7 +67,7 @@ Multiple kernels, ramdisks and FDT blobs load = <00000000>; entry = <00000000>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; @@ -104,7 +104,7 @@ Multiple kernels, ramdisks and FDT blobs compression = "none"; load = <00700000>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; diff --git a/doc/usage/fit/sign-configs.rst b/doc/usage/fit/sign-configs.rst index 6a3df8f2c5b..6d98d44430c 100644 --- a/doc/usage/fit/sign-configs.rst +++ b/doc/usage/fit/sign-configs.rst @@ -22,7 +22,7 @@ Signed configurations entry = <0x8>; kernel-version = <1>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; fdt-1 { @@ -33,7 +33,7 @@ Signed configurations compression = "none"; fdt-version = <1>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; }; @@ -43,7 +43,7 @@ Signed configurations kernel = "kernel"; fdt = "fdt-1"; signature { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; key-name-hint = "dev"; sign-images = "fdt", "kernel"; }; diff --git a/doc/usage/fit/sign-images.rst b/doc/usage/fit/sign-images.rst index 7d54d702c97..ca7d10fab83 100644 --- a/doc/usage/fit/sign-images.rst +++ b/doc/usage/fit/sign-images.rst @@ -22,7 +22,7 @@ Signed Images entry = <0x8>; kernel-version = <1>; signature { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; key-name-hint = "dev"; }; }; @@ -34,7 +34,7 @@ Signed Images compression = "none"; fdt-version = <1>; signature { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; key-name-hint = "dev"; }; }; diff --git a/doc/usage/fit/signature.rst b/doc/usage/fit/signature.rst index 0804bffd1ed..03a71b5192d 100644 --- a/doc/usage/fit/signature.rst +++ b/doc/usage/fit/signature.rst @@ -93,7 +93,7 @@ Public keys should be stored as sub-nodes in a /signature node. Required properties are: algo - Algorithm name (e.g. "sha1,rsa2048" or "sha256,ecdsa256") + Algorithm name (e.g. "sha256,rsa2048" or "sha512,ecdsa256") Optional properties are: @@ -219,28 +219,28 @@ As an example, consider this FIT:: kernel-1 { data = <data for kernel1> signature-1 { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; value = <...kernel signature 1...> }; }; kernel-2 { data = <data for kernel2> signature-1 { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; value = <...kernel signature 2...> }; }; fdt-1 { data = <data for fdt1>; signature-1 { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; value = <...fdt signature 1...> }; }; fdt-2 { data = <data for fdt2>; signature-1 { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; value = <...fdt signature 2...> }; }; @@ -291,28 +291,28 @@ So the above example is adjusted to look like this:: kernel-1 { data = <data for kernel1> hash-1 { - algo = "sha1"; + algo = "sha256"; value = <...kernel hash 1...> }; }; kernel-2 { data = <data for kernel2> hash-1 { - algo = "sha1"; + algo = "sha256"; value = <...kernel hash 2...> }; }; fdt-1 { data = <data for fdt1>; hash-1 { - algo = "sha1"; + algo = "sha256"; value = <...fdt hash 1...> }; }; fdt-2 { data = <data for fdt2>; hash-1 { - algo = "sha1"; + algo = "sha256"; value = <...fdt hash 2...> }; }; @@ -323,7 +323,7 @@ So the above example is adjusted to look like this:: kernel = "kernel-1"; fdt = "fdt-1"; signature-1 { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; value = <...conf 1 signature...>; }; }; @@ -331,7 +331,7 @@ So the above example is adjusted to look like this:: kernel = "kernel-2"; fdt = "fdt-2"; signature-1 { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; value = <...conf 1 signature...>; }; }; @@ -671,7 +671,7 @@ Create the fitImage:: Sign the fitImage with the hardware key:: $ ./tools/mkimage -F -k \ - "model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29" \ + "pkcs11:model=PKCS%2315%20emulated;manufacturer=ZeitControl;serial=000xxxxxxxxx;token=OpenPGP%20card%20%28User%20PIN%20%28sig%29%29" \ -K u-boot.dtb -N pkcs11 -r fitImage diff --git a/doc/usage/fit/update3.rst b/doc/usage/fit/update3.rst index 4ff3950c01e..24235801470 100644 --- a/doc/usage/fit/update3.rst +++ b/doc/usage/fit/update3.rst @@ -19,7 +19,7 @@ Automatic software update: multiple files type = "firmware"; load = <FF700000>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; update-2 { @@ -29,7 +29,7 @@ Automatic software update: multiple files type = "firmware"; load = <FF8E0000>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; @@ -40,7 +40,7 @@ Automatic software update: multiple files type = "firmware"; load = <FFAC0000>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; }; diff --git a/doc/usage/fit/update_uboot.rst b/doc/usage/fit/update_uboot.rst index a9288ee6367..811d008d13d 100644 --- a/doc/usage/fit/update_uboot.rst +++ b/doc/usage/fit/update_uboot.rst @@ -21,7 +21,7 @@ Make sure the flashing addresses ('load' prop) is correct for your board! type = "firmware"; load = <0xFFFC0000>; hash-1 { - algo = "sha1"; + algo = "sha256"; }; }; }; diff --git a/doc/usage/fit/x86-fit-boot.rst b/doc/usage/fit/x86-fit-boot.rst index 93b73bb9019..9e3e32204d5 100644 --- a/doc/usage/fit/x86-fit-boot.rst +++ b/doc/usage/fit/x86-fit-boot.rst @@ -207,16 +207,16 @@ You can take a look at the resulting fit file if you like:: OS: Linux Load Address: 0x01000000 Entry Point: 0x00000000 - Hash algo: sha1 - Hash value: 446b5163ebfe0fb6ee20cbb7a8501b263cd92392 + Hash algo: sha256 + Hash value: 4bbf49981ade163ed089f8525236fedfe44508e9b02a21a48294a96a1518107b Image 1 (setup) Description: Linux setup.bin Created: Tue Oct 7 10:57:24 2014 Type: x86 setup.bin Compression: uncompressed Data Size: 12912 Bytes = 12.61 kB = 0.01 MB - Hash algo: sha1 - Hash value: a1f2099cf47ff9816236cd534c77af86e713faad + Hash algo: sha256 + Hash value: 6aa50c2e0392cb119cdf0971dce8339f100608ed3757c8200b0e39e889e432d2 Default Configuration: 'config-1' Configuration 0 (config-1) Description: Boot Linux kernel diff --git a/drivers/bios_emulator/include/x86emu.h b/drivers/bios_emulator/include/x86emu.h index b28cdc6b8ca..d2650a8d160 100644 --- a/drivers/bios_emulator/include/x86emu.h +++ b/drivers/bios_emulator/include/x86emu.h @@ -42,7 +42,6 @@ #define __X86EMU_X86EMU_H #include <asm/types.h> -#include <common.h> #include <pci.h> #include <asm/io.h> #define X86API diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index e5ada5b6d49..eecfacd7fc0 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -1104,46 +1104,12 @@ static int ast2600_clk_enable(struct clk *clk) return 0; } -struct clk_ops ast2600_clk_ops = { - .get_rate = ast2600_clk_get_rate, - .set_rate = ast2600_clk_set_rate, - .enable = ast2600_clk_enable, -}; - -static int ast2600_clk_probe(struct udevice *dev) -{ - struct ast2600_clk_priv *priv = dev_get_priv(dev); - - priv->scu = devfdt_get_addr_ptr(dev); - if (IS_ERR(priv->scu)) - return PTR_ERR(priv->scu); - - ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); - ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); - ast2600_configure_mac12_clk(priv->scu); - ast2600_configure_mac34_clk(priv->scu); - ast2600_configure_rsa_ecc_clk(priv->scu); - - return 0; -} - -static int ast2600_clk_bind(struct udevice *dev) -{ - int ret; - - /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); - if (ret) - debug("Warning: No reset driver: ret=%d\n", ret); - - return 0; -} - struct aspeed_clks { ulong id; const char *name; }; +#if IS_ENABLED(CONFIG_CMD_CLK) static struct aspeed_clks aspeed_clk_names[] = { { ASPEED_CLK_HPLL, "hpll" }, { ASPEED_CLK_MPLL, "mpll" }, @@ -1158,18 +1124,12 @@ static struct aspeed_clks aspeed_clk_names[] = { { ASPEED_CLK_HUARTX, "huxclk" }, }; -int soc_clk_dump(void) +static void ast2600_clk_dump(struct udevice *dev) { - struct udevice *dev; struct clk clk; unsigned long rate; int i, ret; - ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(aspeed_scu), - &dev); - if (ret) - return ret; - printf("Clk\t\tHz\n"); for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { @@ -1202,6 +1162,45 @@ int soc_clk_dump(void) return 0; } +#endif + +struct clk_ops ast2600_clk_ops = { + .get_rate = ast2600_clk_get_rate, + .set_rate = ast2600_clk_set_rate, + .enable = ast2600_clk_enable, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = ast2600_clk_dump, +#endif +}; + +static int ast2600_clk_probe(struct udevice *dev) +{ + struct ast2600_clk_priv *priv = dev_get_priv(dev); + + priv->scu = devfdt_get_addr_ptr(dev); + if (IS_ERR(priv->scu)) + return PTR_ERR(priv->scu); + + ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); + ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); + ast2600_configure_mac12_clk(priv->scu); + ast2600_configure_mac34_clk(priv->scu); + ast2600_configure_rsa_ecc_clk(priv->scu); + + return 0; +} + +static int ast2600_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); + if (ret) + debug("Warning: No reset driver: ret=%d\n", ret); + + return 0; +} static const struct udevice_id ast2600_clk_ids[] = { { .compatible = "aspeed,ast2600-scu", }, diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 6eb2b8133a3..d2e5a1ae401 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -66,7 +66,7 @@ static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate) const struct clk_ops *rate_ops = composite->rate_ops; struct clk *clk_rate = composite->rate; - if (rate && rate_ops) + if (rate && rate_ops && rate_ops->set_rate) return rate_ops->set_rate(clk_rate, rate); else return clk_get_rate(clk); diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 3b5e3f9c86b..3e9d68feb3c 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -640,6 +640,7 @@ int clk_enable(struct clk *clk) if (CONFIG_IS_ENABLED(CLK_CCF)) { /* Take id 0 as a non-valid clk, such as dummy */ if (clk->id && !clk_get_by_id(clk->id, &clkp)) { + ops = clk_dev_ops(clkp->dev); if (clkp->enable_count) { clkp->enable_count++; return 0; @@ -699,6 +700,7 @@ int clk_disable(struct clk *clk) if (CONFIG_IS_ENABLED(CLK_CCF)) { if (clk->id && !clk_get_by_id(clk->id, &clkp)) { + ops = clk_dev_ops(clkp->dev); if (clkp->flags & CLK_IS_CRITICAL) return 0; diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index a5a3461b66c..6ede1b4d4dc 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -18,17 +18,19 @@ int clk_register(struct clk *clk, const char *drv_name, const char *name, const char *parent_name) { - struct udevice *parent; + struct udevice *parent = NULL; struct driver *drv; int ret; - ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent); - if (ret) { - log_err("%s: failed to get %s device (parent of %s)\n", - __func__, parent_name, name); - } else { - log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name, - parent->name, parent); + if (parent_name) { + ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent); + if (ret) { + log_err("%s: failed to get %s device (parent of %s)\n", + __func__, parent_name, name); + } else { + log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name, + parent->name, parent); + } } drv = lists_driver_lookup_name(drv_name); diff --git a/drivers/clk/clk_k210.c b/drivers/clk/clk_k210.c index b9469b93853..7432ae8f064 100644 --- a/drivers/clk/clk_k210.c +++ b/drivers/clk/clk_k210.c @@ -1239,52 +1239,6 @@ static int k210_clk_request(struct clk *clk) return 0; } -static const struct clk_ops k210_clk_ops = { - .request = k210_clk_request, - .set_rate = k210_clk_set_rate, - .get_rate = k210_clk_get_rate, - .set_parent = k210_clk_set_parent, - .enable = k210_clk_enable, - .disable = k210_clk_disable, -}; - -static int k210_clk_probe(struct udevice *dev) -{ - int ret; - struct k210_clk_priv *priv = dev_get_priv(dev); - - priv->base = dev_read_addr_ptr(dev_get_parent(dev)); - if (!priv->base) - return -EINVAL; - - ret = clk_get_by_index(dev, 0, &priv->in0); - if (ret) - return ret; - - /* - * Force setting defaults, even before relocation. This is so we can - * set the clock rate for PLL1 before we relocate into aisram. - */ - if (!(gd->flags & GD_FLG_RELOC)) - clk_set_defaults(dev, CLK_DEFAULTS_POST_FORCE); - - return 0; -} - -static const struct udevice_id k210_clk_ids[] = { - { .compatible = "canaan,k210-clk" }, - { }, -}; - -U_BOOT_DRIVER(k210_clk) = { - .name = "k210_clk", - .id = UCLASS_CLK, - .of_match = k210_clk_ids, - .ops = &k210_clk_ops, - .probe = k210_clk_probe, - .priv_auto = sizeof(struct k210_clk_priv), -}; - #if IS_ENABLED(CONFIG_CMD_CLK) static char show_enabled(struct k210_clk_priv *priv, int id) { @@ -1323,16 +1277,10 @@ static void show_clks(struct k210_clk_priv *priv, int id, int depth) } } -int soc_clk_dump(void) +static void k210_clk_dump(struct udevice *dev) { - int ret; - struct udevice *dev; struct k210_clk_priv *priv; - ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(k210_clk), - &dev); - if (ret) - return ret; priv = dev_get_priv(dev); puts(" Rate Enabled Name\n"); @@ -1340,6 +1288,54 @@ int soc_clk_dump(void) printf(" %-9lu %-7c %*s%s\n", clk_get_rate(&priv->in0), 'y', 0, "", priv->in0.dev->name); show_clks(priv, K210_CLK_IN0, 1); - return 0; } #endif + +static const struct clk_ops k210_clk_ops = { + .request = k210_clk_request, + .set_rate = k210_clk_set_rate, + .get_rate = k210_clk_get_rate, + .set_parent = k210_clk_set_parent, + .enable = k210_clk_enable, + .disable = k210_clk_disable, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = k210_clk_dump, +#endif +}; + +static int k210_clk_probe(struct udevice *dev) +{ + int ret; + struct k210_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev_get_parent(dev)); + if (!priv->base) + return -EINVAL; + + ret = clk_get_by_index(dev, 0, &priv->in0); + if (ret) + return ret; + + /* + * Force setting defaults, even before relocation. This is so we can + * set the clock rate for PLL1 before we relocate into aisram. + */ + if (!(gd->flags & GD_FLG_RELOC)) + clk_set_defaults(dev, CLK_DEFAULTS_POST_FORCE); + + return 0; +} + +static const struct udevice_id k210_clk_ids[] = { + { .compatible = "canaan,k210-clk" }, + { }, +}; + +U_BOOT_DRIVER(k210_clk) = { + .name = "k210_clk", + .id = UCLASS_CLK, + .of_match = k210_clk_ids, + .ops = &k210_clk_ops, + .probe = k210_clk_probe, + .priv_auto = sizeof(struct k210_clk_priv), +}; diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c index ef06a7fb9f6..a77d0e7419c 100644 --- a/drivers/clk/clk_pic32.c +++ b/drivers/clk/clk_pic32.c @@ -20,6 +20,8 @@ DECLARE_GLOBAL_DATA_PTR; +#define CLK_MHZ(x) ((x) / 1000000) + /* Primary oscillator */ #define SYS_POSC_CLK_HZ 24000000 @@ -385,9 +387,44 @@ static ulong pic32_set_rate(struct clk *clk, ulong rate) return rate; } +#if IS_ENABLED(CONFIG_CMD_CLK) +static void pic32_dump(struct udevice *dev) +{ + int i; + struct clk clk; + + clk.dev = dev; + + clk.id = PLLCLK; + printf("PLL Speed: %lu MHz\n", + CLK_MHZ(pic32_get_rate(&clk))); + + clk.id = PB7CLK; + printf("CPU Speed: %lu MHz\n", CLK_MHZ(pic32_get_rate(&clk))); + + clk.id = MPLL; + printf("MPLL Speed: %lu MHz\n", CLK_MHZ(pic32_get_rate(&clk))); + + for (i = PB1CLK; i <= PB7CLK; i++) { + clk.id = i; + printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1, + CLK_MHZ(pic32_get_rate(&clk))); + } + + for (i = REF1CLK; i <= REF5CLK; i++) { + clk.id = i; + printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1, + CLK_MHZ(pic32_get_rate(&clk))); + } +} +#endif + static struct clk_ops pic32_pic32_clk_ops = { .set_rate = pic32_set_rate, .get_rate = pic32_get_rate, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = pic32_dump, +#endif }; static int pic32_clk_probe(struct udevice *dev) diff --git a/drivers/clk/clk_sandbox_ccf.c b/drivers/clk/clk_sandbox_ccf.c index fedcdd40448..38184e27aa4 100644 --- a/drivers/clk/clk_sandbox_ccf.c +++ b/drivers/clk/clk_sandbox_ccf.c @@ -284,6 +284,7 @@ static int sandbox_clk_ccf_probe(struct udevice *dev) U_BOOT_DRIVER(sandbox_clk_ccf) = { .name = "sandbox_clk_ccf", .id = UCLASS_CLK, + .ops = &ccf_clk_ops, .probe = sandbox_clk_ccf_probe, .of_match = sandbox_clk_ccf_test_ids, }; diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c index 5807a454f3b..c695b69321e 100644 --- a/drivers/clk/clk_sandbox_test.c +++ b/drivers/clk/clk_sandbox_test.c @@ -15,6 +15,7 @@ static const char * const sandbox_clk_test_names[] = { [SANDBOX_CLK_TEST_ID_FIXED] = "fixed", [SANDBOX_CLK_TEST_ID_SPI] = "spi", [SANDBOX_CLK_TEST_ID_I2C] = "i2c", + [SANDBOX_CLK_TEST_ID_I2C_ROOT] = "i2c_root", }; int sandbox_clk_test_get(struct udevice *dev) diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index c473643603a..42ab032bf7e 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -555,7 +555,8 @@ static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate) return 0; } -int soc_clk_dump(void) +#if IS_ENABLED(CONFIG_CMD_CLK) +static void versal_clk_dump(struct udevice __always_unused *dev) { u64 clk_rate = 0; u32 type, ret, i = 0; @@ -575,9 +576,8 @@ int soc_clk_dump(void) printf("clk: %s freq:%lld\n", clock[i].clk_name, clk_rate); } - - return 0; } +#endif static void versal_get_clock_info(void) { @@ -769,6 +769,9 @@ static struct clk_ops versal_clk_ops = { .set_rate = versal_clk_set_rate, .get_rate = versal_clk_get_rate, .enable = versal_clk_enable, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = versal_clk_dump, +#endif }; static const struct udevice_id versal_clk_ids[] = { diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c index e80500e382b..34f964d72af 100644 --- a/drivers/clk/clk_zynq.c +++ b/drivers/clk/clk_zynq.c @@ -454,12 +454,64 @@ static int dummy_enable(struct clk *clk) return 0; } +#if IS_ENABLED(CONFIG_CMD_CLK) +static const char * const clk_names[clk_max] = { + "armpll", "ddrpll", "iopll", + "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", + "ddr2x", "ddr3x", "dci", + "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", + "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", + "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", + "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", + "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", + "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", + "smc_aper", "swdt", "dbg_trc", "dbg_apb" +}; + +static void zynq_clk_dump(struct udevice *dev) +{ + int i, ret; + + printf("clk\t\tfrequency\n"); + for (i = 0; i < clk_max; i++) { + const char *name = clk_names[i]; + + if (name) { + struct clk clk; + unsigned long rate; + + clk.id = i; + ret = clk_request(dev, &clk); + if (ret < 0) { + printf("%s clk_request() failed: %d\n", + __func__, ret); + break; + } + + rate = clk_get_rate(&clk); + + clk_free(&clk); + + if ((rate == (unsigned long)-ENOSYS) || + (rate == (unsigned long)-ENXIO)) + printf("%10s%20s\n", name, "unknown"); + else + printf("%10s%20lu\n", name, rate); + } + } +} +#endif + static struct clk_ops zynq_clk_ops = { .get_rate = zynq_clk_get_rate, #ifndef CONFIG_SPL_BUILD .set_rate = zynq_clk_set_rate, #endif .enable = dummy_enable, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = zynq_clk_dump, +#endif }; static int zynq_clk_probe(struct udevice *dev) diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index c059b9e8e65..0ffac194a19 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -735,16 +735,11 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate) } } -int soc_clk_dump(void) +#if IS_ENABLED(CONFIG_CMD_CLK) +static void zynqmp_clk_dump(struct udevice *dev) { - struct udevice *dev; int i, ret; - ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_DRIVER_GET(zynqmp_clk), &dev); - if (ret) - return ret; - printf("clk\t\tfrequency\n"); for (i = 0; i < clk_max; i++) { const char *name = clk_names[i]; @@ -754,8 +749,11 @@ int soc_clk_dump(void) clk.id = i; ret = clk_request(dev, &clk); - if (ret < 0) - return ret; + if (ret < 0) { + printf("%s clk_request() failed: %d\n", + __func__, ret); + break; + } rate = clk_get_rate(&clk); @@ -769,9 +767,8 @@ int soc_clk_dump(void) printf("%10s%20lu\n", name, rate); } } - - return 0; } +#endif static int zynqmp_get_freq_by_name(char *name, struct udevice *dev, ulong *freq) { @@ -872,6 +869,9 @@ static struct clk_ops zynqmp_clk_ops = { .set_rate = zynqmp_clk_set_rate, .get_rate = zynqmp_clk_get_rate, .enable = zynqmp_clk_enable, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = zynqmp_clk_dump, +#endif }; static const struct udevice_id zynqmp_clk_ids[] = { diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c index ceeead34349..9600672e071 100644 --- a/drivers/clk/imx/clk-imx8.c +++ b/drivers/clk/imx/clk-imx8.c @@ -43,18 +43,12 @@ static int imx8_clk_enable(struct clk *clk) } #if IS_ENABLED(CONFIG_CMD_CLK) -int soc_clk_dump(void) +static void imx8_clk_dump(struct udevice *dev) { - struct udevice *dev; struct clk clk; unsigned long rate; int i, ret; - ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_DRIVER_GET(imx8_clk), &dev); - if (ret) - return ret; - printf("Clk\t\tHz\n"); for (i = 0; i < num_clks; i++) { @@ -84,8 +78,6 @@ int soc_clk_dump(void) printf("%s(%3lu):\t%lu\n", imx8_clk_names[i].name, imx8_clk_names[i].id, rate); } - - return 0; } #endif @@ -94,6 +86,9 @@ static struct clk_ops imx8_clk_ops = { .get_rate = imx8_clk_get_rate, .enable = imx8_clk_enable, .disable = imx8_clk_disable, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = imx8_clk_dump, +#endif }; static int imx8_clk_probe(struct udevice *dev) diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e74c6f97807..e631f79e4dd 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -11,5 +11,6 @@ obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o +obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c new file mode 100644 index 00000000000..61ccd4a210f --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -0,0 +1,766 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek clock driver for MT8365 SoC + * + * Copyright (C) 2023 BayLibre, SAS + * Copyright (c) 2023 MediaTek Inc. + * Author: Julien Masson <jmasson@baylibre.com> + * Author: Fabien Parent <fparent@baylibre.com> + * Author: Weiyi Lu <weiyi.lu@mediatek.com> + */ + +#include <dm.h> +#include <dt-bindings/clock/mediatek,mt8365-clk.h> +#include "clk-mtk.h" + +/* apmixedsys */ +#define MT8365_PLL_FMAX (3800UL * MHZ) +#define MT8365_PLL_FMIN (1500UL * MHZ) +#define CON0_MT8365_RST_BAR BIT(23) +#define PLL_AO BIT(1) + +#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ + _pd_shift, _pcw_reg, _pcw_shift, _rst_bar_mask, _pcw_chg_reg) { \ + .id = _id, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .flags = _flags, \ + .rst_bar_mask = _rst_bar_mask, \ + .fmax = MT8365_PLL_FMAX, \ + .fmin = MT8365_PLL_FMIN, \ + .pcwbits = _pcwbits, \ + .pcwibits = 8, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .pcw_chg_reg = _pcw_chg_reg, \ + } + +static const struct mtk_pll_data apmixed_plls[] = { + PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, PLL_AO, 22, 0x0310, + 24, 0x0310, 0, 0, 0), + PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, HAVE_RST_BAR, 22, + 0x022C, 24, 0x022C, 0, CON0_MT8365_RST_BAR, 0), + PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, HAVE_RST_BAR, 22, + 0x020C, 24, 0x020C, 0, CON0_MT8365_RST_BAR, 0), + PLL(CLK_APMIXED_MFGPLL, 0x0218, 0x0224, 0x00000001, 0, 22, 0x021C, 24, + 0x021C, 0, 0, 0), + PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001, 0, 22, 0x0354, 24, + 0x0354, 0, 0, 0), + PLL(CLK_APMIXED_MMPLL, 0x0330, 0x033C, 0x00000001, 0, 22, 0x0334, 24, + 0x0334, 0, 0, 0), + PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001, 0, 32, 0x0320, 24, + 0x0324, 0, 0, 0x0320), + PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001, 0, 32, 0x0364, 24, + 0x0368, 0, 0, 0x0364), + PLL(CLK_APMIXED_LVDSPLL, 0x0374, 0x0380, 0x00000001, 0, 22, 0x0378, 24, + 0x0378, 0, 0, 0), + PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001, 0, 22, 0x0394, 24, + 0x0394, 0, 0, 0), + PLL(CLK_APMIXED_APUPLL, 0x03A0, 0x03AC, 0x00000001, 0, 22, 0x03A4, 24, + 0x03A4, 0, 0, 0), +}; + +/* topckgen */ +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 0), + FIXED_CLK(CLK_TOP_I2S0_BCK, CLK_XTAL, 26000000), + FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, CLK_TOP_CLK26M, 75000000), + FIXED_CLK(CLK_TOP_VPLL_DPIX, CLK_TOP_CLK26M, 75000000), + FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, CLK_TOP_CLK26M, 52500000), +}; + +#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) + +static const struct mtk_fixed_factor top_divs[] = { + PLL_FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_XTAL, 1, 2), + PLL_FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", CLK_APMIXED_MAINPLL, 1, 2), + PLL_FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", CLK_APMIXED_MAINPLL, 1, 4), + PLL_FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", CLK_APMIXED_MAINPLL, 1, 8), + PLL_FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", CLK_APMIXED_MAINPLL, 1, 16), + PLL_FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", CLK_APMIXED_MAINPLL, 1, 32), + PLL_FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", CLK_APMIXED_MAINPLL, 1, 3), + PLL_FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", CLK_APMIXED_MAINPLL, 1, 6), + PLL_FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", CLK_APMIXED_MAINPLL, 1, 12), + PLL_FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", CLK_APMIXED_MAINPLL, 1, 24), + PLL_FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", CLK_APMIXED_MAINPLL, 1, 5), + PLL_FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", CLK_APMIXED_MAINPLL, 1, 10), + PLL_FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", CLK_APMIXED_MAINPLL, 1, 20), + PLL_FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", CLK_APMIXED_MAINPLL, 1, 7), + PLL_FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", CLK_APMIXED_MAINPLL, 1, 14), + PLL_FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", CLK_APMIXED_MAINPLL, 1, 28), + PLL_FACTOR(CLK_TOP_UNIVPLL, "univpll", CLK_APMIXED_UNIV_EN, 1, 2), + PLL_FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", CLK_APMIXED_UNIVPLL, 1, 2), + PLL_FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", CLK_APMIXED_UNIVPLL, 1, 4), + PLL_FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", CLK_APMIXED_UNIVPLL, 1, 8), + PLL_FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", CLK_APMIXED_UNIVPLL, 1, 3), + PLL_FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", CLK_APMIXED_UNIVPLL, 1, 6), + PLL_FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", CLK_APMIXED_UNIVPLL, 1, 12), + PLL_FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", CLK_APMIXED_UNIVPLL, 1, 24), + PLL_FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", CLK_APMIXED_UNIVPLL, 1, 96), + PLL_FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", CLK_APMIXED_UNIVPLL, 1, 5), + PLL_FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", CLK_APMIXED_UNIVPLL, 1, 10), + PLL_FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", CLK_APMIXED_UNIVPLL, 1, 20), + PLL_FACTOR(CLK_TOP_MMPLL, "mmpll_ck", CLK_APMIXED_MMPLL, 1, 1), + PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2), + PLL_FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", CLK_APMIXED_MFGPLL, 1, 1), + PLL_FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", CLK_APMIXED_LVDSPLL, 1, 2), + PLL_FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", CLK_APMIXED_LVDSPLL, 1, 4), + PLL_FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", CLK_APMIXED_LVDSPLL, 1, 8), + PLL_FACTOR(CLK_TOP_LVDSPLL_D16, "lvdspll_d16", CLK_APMIXED_LVDSPLL, 1, 16), + PLL_FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", CLK_APMIXED_USB20_EN, 1, 13), + PLL_FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", CLK_TOP_USB20_192M, 1, 4), + PLL_FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", CLK_TOP_USB20_192M, 1, 8), + PLL_FACTOR(CLK_TOP_USB20_192M_D16, "usb20_192m_d16", CLK_TOP_USB20_192M, 1, 16), + PLL_FACTOR(CLK_TOP_USB20_192M_D32, "usb20_192m_d32", CLK_TOP_USB20_192M, 1, 32), + PLL_FACTOR(CLK_TOP_APLL1, "apll1_ck", CLK_APMIXED_APLL1, 1, 1), + PLL_FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", CLK_APMIXED_APLL1, 1, 2), + PLL_FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", CLK_APMIXED_APLL1, 1, 4), + PLL_FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", CLK_APMIXED_APLL1, 1, 8), + PLL_FACTOR(CLK_TOP_APLL2, "apll2_ck", CLK_APMIXED_APLL2, 1, 1), + PLL_FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", CLK_APMIXED_APLL2, 1, 2), + PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4), + PLL_FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", CLK_APMIXED_APLL2, 1, 8), + PLL_FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", CLK_APMIXED_MSDCPLL, 1, 1), + PLL_FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", CLK_APMIXED_MSDCPLL, 1, 2), + PLL_FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", CLK_APMIXED_DSPPLL, 1, 1), + PLL_FACTOR(CLK_TOP_DSPPLL_D2, "dsppll_d2", CLK_APMIXED_DSPPLL, 1, 2), + PLL_FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", CLK_APMIXED_DSPPLL, 1, 4), + PLL_FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", CLK_APMIXED_DSPPLL, 1, 8), + PLL_FACTOR(CLK_TOP_APUPLL, "apupll_ck", CLK_APMIXED_APUPLL, 1, 1), + PLL_FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", CLK_XTAL, 1, 52), +}; + +static const int axi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D7, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYSPLL3_D2 +}; + +static const int mem_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MMPLL, + CLK_TOP_SYSPLL_D3, + CLK_TOP_SYSPLL1_D2 +}; + +static const int mm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MMPLL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_MMPLL_D2, +}; + +static const int scp_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D3 +}; + +static const int mfg_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MFGPLL, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D3 +}; + +static const int atb_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYSPLL1_D2 +}; + +static const int camtg_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_USB20_192M_D8, + CLK_TOP_UNIVPLL2_D8, + CLK_TOP_USB20_192M_D4, + CLK_TOP_UNIVPLL2_D32, + CLK_TOP_USB20_192M_D16, + CLK_TOP_USB20_192M_D32, +}; + +static const int uart_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int spi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int msdc50_0_hc_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_SYSPLL2_D2 +}; + +static const int msdc50_0_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MSDCPLL, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_SYSPLL4_D2 +}; + +static const int msdc50_2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MSDCPLL, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4 +}; + +static const int msdc30_1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MSDCPLL_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int audio_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL3_D4, + CLK_TOP_SYSPLL4_D4, + CLK_TOP_SYSPLL1_D16 +}; + +static const int aud_intbus_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYSPLL4_D2 +}; + +static const int aud_1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL1 +}; + +static const int aud_2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL2 +}; + +static const int aud_engen1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL1_D2, + CLK_TOP_APLL1_D4, + CLK_TOP_APLL1_D8 +}; + +static const int aud_engen2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL2_D2, + CLK_TOP_APLL2_D4, + CLK_TOP_APLL2_D8, +}; + +static const int aud_spdif_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D2 +}; + +static const int disp_pwm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int dxcc_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYSPLL1_D8 +}; + +static const int ssusb_sys_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL3_D2 +}; + +static const int spm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D8 +}; + +static const int i2c_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_SYSPLL2_D8 +}; + +static const int pwm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_SYSPLL1_D8 +}; + +static const int senif_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL2_D2 +}; + +static const int aes_fde_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MSDCPLL, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D2 +}; + +static const int dpi0_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_LVDSPLL_D2, + CLK_TOP_LVDSPLL_D4, + CLK_TOP_LVDSPLL_D8, + CLK_TOP_LVDSPLL_D16 +}; + +static const int dsp_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYS_26M_D2, + CLK_TOP_DSPPLL, + CLK_TOP_DSPPLL_D2, + CLK_TOP_DSPPLL_D4, + CLK_TOP_DSPPLL_D8 +}; + +static const int nfi2x_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_SYSPLL_D7, + CLK_TOP_SYSPLL_D3, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_MSDCPLL_D2, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL_D5 +}; + +static const int nfiecc_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_SYSPLL_D7, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL_D5 +}; + +static const int ecc_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D2 +}; + +static const int eth_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D8, + CLK_TOP_SYSPLL4_D4, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_SYSPLL4_D2 +}; + +static const int gcpu_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL_D3, + CLK_TOP_SYSPLL2_D2 +}; + +static const int gcpu_cpm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL2_D2 +}; + +static const int apu_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D2, + CLK_APMIXED_APUPLL, + CLK_TOP_MMPLL, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL1_D4 +}; + +static const struct mtk_composite top_muxes[] = { + /* CLK_CFG_0 */ + MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x040, 0, 2, 7), + MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x040, 8, 2, 15), + MUX_GATE(CLK_TOP_MM_SEL, mm_parents, 0x040, 16, 3, 23), + MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x040, 24, 3, 31), + /* CLK_CFG_1 */ + MUX_GATE(CLK_TOP_MFG_SEL, mfg_parents, 0x050, 0, 2, 7), + MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x050, 8, 2, 15), + MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x050, 16, 3, 23), + MUX_GATE(CLK_TOP_CAMTG1_SEL, camtg_parents, 0x050, 24, 3, 31), + /* CLK_CFG_2 */ + MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x060, 0, 1, 7), + MUX_GATE(CLK_TOP_SPI_SEL, spi_parents, 0x060, 8, 2, 15), + MUX_GATE(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, 0x060, 16, 2, 23), + MUX_GATE(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, 0x060, 24, 2, 31), + /* CLK_CFG_3 */ + MUX_GATE(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, 0x070, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, 0x070, 8, 3, 15), + MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x070, 16, 3, 23), + MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x070, 24, 2, 31), + /* CLK_CFG_4 */ + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x080, 0, 2, 7), + MUX_GATE(CLK_TOP_AUD_1_SEL, aud_1_parents, 0x080, 8, 1, 15), + MUX_GATE(CLK_TOP_AUD_2_SEL, aud_2_parents, 0x080, 16, 1, 23), + MUX_GATE(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x080, 24, 2, 31), + /* CLK_CFG_5 */ + MUX_GATE(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x090, 0, 2, 7), + MUX_GATE(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, 0x090, 8, 1, 15), + MUX_GATE(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents, 0x090, 16, 2, 23), + /* CLK_CFG_6 */ + MUX_GATE(CLK_TOP_DXCC_SEL, dxcc_parents, 0x0a0, 0, 2, 7), + MUX_GATE(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, 0x0a0, 8, 2, 15), + MUX_GATE(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, 0x0a0, 16, 2, 23), + MUX_GATE(CLK_TOP_SPM_SEL, spm_parents, 0x0a0, 24, 1, 31), + /* CLK_CFG_7 */ + MUX_GATE(CLK_TOP_I2C_SEL, i2c_parents, 0x0b0, 0, 3, 7), + MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x0b0, 8, 2, 15), + MUX_GATE(CLK_TOP_SENIF_SEL, senif_parents, 0x0b0, 16, 2, 23), + MUX_GATE(CLK_TOP_AES_FDE_SEL, aes_fde_parents, 0x0b0, 24, 3, 31), + /* CLK_CFG_8 */ + MUX_GATE(CLK_TOP_CAMTM_SEL, senif_parents, 0x0c0, 0, 2, 7), + MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_parents, 0x0c0, 8, 3, 15), + MUX_GATE(CLK_TOP_DPI1_SEL, dpi0_parents, 0x0c0, 16, 3, 23), + MUX_GATE(CLK_TOP_DSP_SEL, dsp_parents, 0x0c0, 24, 3, 31), + /* CLK_CFG_9 */ + MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x0d0, 0, 3, 7), + MUX_GATE(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x0d0, 8, 3, 15), + MUX_GATE(CLK_TOP_ECC_SEL, ecc_parents, 0x0d0, 16, 3, 23), + MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x0d0, 24, 3, 31), + /* CLK_CFG_10 */ + MUX_GATE(CLK_TOP_GCPU_SEL, gcpu_parents, 0x0e0, 0, 3, 7), + MUX_GATE(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, 0x0e0, 8, 2, 15), + MUX_GATE(CLK_TOP_APU_SEL, apu_parents, 0x0e0, 16, 3, 23), + MUX_GATE(CLK_TOP_APU_IF_SEL, apu_parents, 0x0e0, 24, 3, 31), +}; + +static const struct mtk_clk_tree mt8365_clk_tree = { + .xtal_rate = 26 * MHZ, + .xtal2_rate = 26 * MHZ, + .fdivs_offs = CLK_TOP_SYSPLL_D2, + .muxes_offs = CLK_TOP_AXI_SEL, + .plls = apmixed_plls, + .fclks = top_fixed_clks, + .fdivs = top_divs, + .muxes = top_muxes, +}; + +/* topckgen cg */ +static const struct mtk_gate_regs top0_cg_regs = { + .set_ofs = 0, + .clr_ofs = 0, + .sta_ofs = 0, +}; + +static const struct mtk_gate_regs top1_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x104, + .sta_ofs = 0x104, +}; + +static const struct mtk_gate_regs top2_cg_regs = { + .set_ofs = 0x320, + .clr_ofs = 0x320, + .sta_ofs = 0x320, +}; + +#define GATE_TOP0(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_TOP1(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_TOP2(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top2_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate top_clk_gates[] = { + GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10), + GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11), + GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16), + GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17), + GATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4, 8), + GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4, 9), + GATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, CLK_TOP_LVDSTX_CLKDIG_CTS, 20), + GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, CLK_TOP_VPLL_DPIX, 21), + GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22), + GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23), + GATE_TOP2(CLK_TOP_AUD_I2S0_M, CLK_TOP_APLL12_CK_DIV0, 0), + GATE_TOP2(CLK_TOP_AUD_I2S1_M, CLK_TOP_APLL12_CK_DIV1, 1), + GATE_TOP2(CLK_TOP_AUD_I2S2_M, CLK_TOP_APLL12_CK_DIV2, 2), + GATE_TOP2(CLK_TOP_AUD_I2S3_M, CLK_TOP_APLL12_CK_DIV3, 3), + GATE_TOP2(CLK_TOP_AUD_TDMOUT_M, CLK_TOP_APLL12_CK_DIV4, 4), + GATE_TOP2(CLK_TOP_AUD_TDMOUT_B, CLK_TOP_APLL12_CK_DIV4B, 5), + GATE_TOP2(CLK_TOP_AUD_TDMIN_M, CLK_TOP_APLL12_CK_DIV5, 6), + GATE_TOP2(CLK_TOP_AUD_TDMIN_B, CLK_TOP_APLL12_CK_DIV5B, 7), + GATE_TOP2(CLK_TOP_AUD_SPDIF_M, CLK_TOP_APLL12_CK_DIV6, 8), +}; + +/* infracfg */ +static const struct mtk_gate_regs ifr2_cg_regs = { + .set_ofs = 0x80, + .clr_ofs = 0x84, + .sta_ofs = 0x90, +}; + +static const struct mtk_gate_regs ifr3_cg_regs = { + .set_ofs = 0x88, + .clr_ofs = 0x8c, + .sta_ofs = 0x94, +}; + +static const struct mtk_gate_regs ifr4_cg_regs = { + .set_ofs = 0xa4, + .clr_ofs = 0xa8, + .sta_ofs = 0xac, +}; + +static const struct mtk_gate_regs ifr5_cg_regs = { + .set_ofs = 0xc0, + .clr_ofs = 0xc4, + .sta_ofs = 0xc8, +}; + +static const struct mtk_gate_regs ifr6_cg_regs = { + .set_ofs = 0xd0, + .clr_ofs = 0xd4, + .sta_ofs = 0xd8, +}; + +#define GATE_IFRX(_id, _parent, _shift, _regs) \ + { \ + .id = _id, \ + .parent = _parent, \ + .regs = _regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_IFR2(_id, _parent, _shift) \ + GATE_IFRX(_id, _parent, _shift, &ifr2_cg_regs) + +#define GATE_IFR3(_id, _parent, _shift) \ + GATE_IFRX(_id, _parent, _shift, &ifr3_cg_regs) + +#define GATE_IFR4(_id, _parent, _shift) \ + GATE_IFRX(_id, _parent, _shift, &ifr4_cg_regs) + +#define GATE_IFR5(_id, _parent, _shift) \ + GATE_IFRX(_id, _parent, _shift, &ifr5_cg_regs) + +#define GATE_IFR6(_id, _parent, _shift) \ + GATE_IFRX(_id, _parent, _shift, &ifr6_cg_regs) + +static const struct mtk_gate ifr_clks[] = { + /* IFR2 */ + GATE_IFR2(CLK_IFR_PMIC_TMR, CLK_TOP_CLK26M, 0), + GATE_IFR2(CLK_IFR_PMIC_AP, CLK_TOP_CLK26M, 1), + GATE_IFR2(CLK_IFR_PMIC_MD, CLK_TOP_CLK26M, 2), + GATE_IFR2(CLK_IFR_PMIC_CONN, CLK_TOP_CLK26M, 3), + GATE_IFR2(CLK_IFR_ICUSB, CLK_TOP_AXI_SEL, 8), + GATE_IFR2(CLK_IFR_GCE, CLK_TOP_AXI_SEL, 9), + GATE_IFR2(CLK_IFR_THERM, CLK_TOP_AXI_SEL, 10), + GATE_IFR2(CLK_IFR_PWM_HCLK, CLK_TOP_AXI_SEL, 15), + GATE_IFR2(CLK_IFR_PWM1, CLK_TOP_PWM_SEL, 16), + GATE_IFR2(CLK_IFR_PWM2, CLK_TOP_PWM_SEL, 17), + GATE_IFR2(CLK_IFR_PWM3, CLK_TOP_PWM_SEL, 18), + GATE_IFR2(CLK_IFR_PWM4, CLK_TOP_PWM_SEL, 19), + GATE_IFR2(CLK_IFR_PWM5, CLK_TOP_PWM_SEL, 20), + GATE_IFR2(CLK_IFR_PWM, CLK_TOP_PWM_SEL, 21), + GATE_IFR2(CLK_IFR_UART0, CLK_TOP_UART_SEL, 22), + GATE_IFR2(CLK_IFR_UART1, CLK_TOP_UART_SEL, 23), + GATE_IFR2(CLK_IFR_UART2, CLK_TOP_UART_SEL, 24), + GATE_IFR2(CLK_IFR_DSP_UART, CLK_TOP_UART_SEL, 26), + GATE_IFR2(CLK_IFR_GCE_26M, CLK_TOP_CLK26M, 27), + GATE_IFR2(CLK_IFR_CQ_DMA_FPC, CLK_TOP_AXI_SEL, 28), + GATE_IFR2(CLK_IFR_BTIF, CLK_TOP_AXI_SEL, 31), + /* IFR3 */ + GATE_IFR3(CLK_IFR_SPI0, CLK_TOP_SPI_SEL, 1), + GATE_IFR3(CLK_IFR_MSDC0_HCLK, CLK_TOP_MSDC50_0_HC_SEL, 2), + GATE_IFR3(CLK_IFR_MSDC2_HCLK, CLK_TOP_MSDC2_2_HC_SEL, 3), + GATE_IFR3(CLK_IFR_MSDC1_HCLK, CLK_TOP_AXI_SEL, 4), + GATE_IFR3(CLK_IFR_DVFSRC, CLK_TOP_CLK26M, 7), + GATE_IFR3(CLK_IFR_GCPU, CLK_TOP_AXI_SEL, 8), + GATE_IFR3(CLK_IFR_TRNG, CLK_TOP_AXI_SEL, 9), + GATE_IFR3(CLK_IFR_AUXADC, CLK_TOP_CLK26M, 10), + GATE_IFR3(CLK_IFR_AUXADC_MD, CLK_TOP_CLK26M, 14), + GATE_IFR3(CLK_IFR_AP_DMA, CLK_TOP_AXI_SEL, 18), + GATE_IFR3(CLK_IFR_DEBUGSYS, CLK_TOP_AXI_SEL, 24), + GATE_IFR3(CLK_IFR_AUDIO, CLK_TOP_AXI_SEL, 25), + /* IFR4 */ + GATE_IFR4(CLK_IFR_PWM_FBCLK6, CLK_TOP_PWM_SEL, 0), + GATE_IFR4(CLK_IFR_DISP_PWM, CLK_TOP_DISP_PWM_SEL, 2), + GATE_IFR4(CLK_IFR_AUD_26M_BK, CLK_TOP_CLK26M, 4), + GATE_IFR4(CLK_IFR_CQ_DMA, CLK_TOP_AXI_SEL, 27), + /* IFR5 */ + GATE_IFR5(CLK_IFR_MSDC0_SF, CLK_TOP_MSDC50_0_SEL, 0), + GATE_IFR5(CLK_IFR_MSDC1_SF, CLK_TOP_MSDC50_0_SEL, 1), + GATE_IFR5(CLK_IFR_MSDC2_SF, CLK_TOP_MSDC50_0_SEL, 2), + GATE_IFR5(CLK_IFR_AP_MSDC0, CLK_TOP_MSDC50_0_SEL, 7), + GATE_IFR5(CLK_IFR_MD_MSDC0, CLK_TOP_MSDC50_0_SEL, 8), + GATE_IFR5(CLK_IFR_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9), + GATE_IFR5(CLK_IFR_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10), + GATE_IFR5(CLK_IFR_MSDC2_SRC, CLK_TOP_MSDC50_2_SEL, 11), + GATE_IFR5(CLK_IFR_PWRAP_TMR, CLK_TOP_CLK26M, 12), + GATE_IFR5(CLK_IFR_PWRAP_SPI, CLK_TOP_CLK26M, 13), + GATE_IFR5(CLK_IFR_PWRAP_SYS, CLK_TOP_CLK26M, 14), + GATE_IFR5(CLK_IFR_IRRX_26M, CLK_TOP_CLK26M, 22), + GATE_IFR5(CLK_IFR_IRRX_32K, CLK_TOP_CLK32K, 23), + GATE_IFR5(CLK_IFR_I2C0_AXI, CLK_TOP_I2C_SEL, 24), + GATE_IFR5(CLK_IFR_I2C1_AXI, CLK_TOP_I2C_SEL, 25), + GATE_IFR5(CLK_IFR_I2C2_AXI, CLK_TOP_I2C_SEL, 26), + GATE_IFR5(CLK_IFR_I2C3_AXI, CLK_TOP_I2C_SEL, 27), + GATE_IFR5(CLK_IFR_NIC_AXI, CLK_TOP_AXI_SEL, 28), + GATE_IFR5(CLK_IFR_NIC_SLV_AXI, CLK_TOP_AXI_SEL, 29), + GATE_IFR5(CLK_IFR_APU_AXI, CLK_TOP_AXI_SEL, 30), + /* IFR6 */ + GATE_IFR6(CLK_IFR_NFIECC, CLK_TOP_NFIECC_SEL, 0), + GATE_IFR6(CLK_IFR_NFI1X_BK, CLK_TOP_NFI2X_SEL, 1), + GATE_IFR6(CLK_IFR_NFIECC_BK, CLK_TOP_NFI2X_SEL, 2), + GATE_IFR6(CLK_IFR_NFI_BK, CLK_TOP_AXI_SEL, 3), + GATE_IFR6(CLK_IFR_MSDC2_AP_BK, CLK_TOP_AXI_SEL, 4), + GATE_IFR6(CLK_IFR_MSDC2_MD_BK, CLK_TOP_AXI_SEL, 5), + GATE_IFR6(CLK_IFR_MSDC2_BK, CLK_TOP_AXI_SEL, 6), + GATE_IFR6(CLK_IFR_SUSB_133_BK, CLK_TOP_AXI_SEL, 7), + GATE_IFR6(CLK_IFR_SUSB_66_BK, CLK_TOP_AXI_SEL, 8), + GATE_IFR6(CLK_IFR_SSUSB_SYS, CLK_TOP_SSUSB_SYS_SEL, 9), + GATE_IFR6(CLK_IFR_SSUSB_REF, CLK_TOP_SSUSB_SYS_SEL, 10), + GATE_IFR6(CLK_IFR_SSUSB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11), +}; + +static int mt8365_apmixedsys_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8365_clk_tree); +} + +static int mt8365_topckgen_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8365_clk_tree); +} + +static int mt8365_topckgen_cg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt8365_clk_tree, top_clk_gates); +} + +static int mt8365_infracfg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt8365_clk_tree, ifr_clks); +} + +static const struct udevice_id mt8365_apmixed_compat[] = { + { .compatible = "mediatek,mt8365-apmixedsys", }, + { } +}; + +static const struct udevice_id mt8365_topckgen_compat[] = { + { .compatible = "mediatek,mt8365-topckgen", }, + { } +}; + +static const struct udevice_id mt8365_topckgen_cg_compat[] = { + { .compatible = "mediatek,mt8365-topckgen-cg", }, + { } +}; + +static const struct udevice_id mt8365_infracfg_compat[] = { + { .compatible = "mediatek,mt8365-infracfg", }, + { } +}; + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt8365-apmixedsys", + .id = UCLASS_CLK, + .of_match = mt8365_apmixed_compat, + .probe = mt8365_apmixedsys_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_apmixedsys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt8365-topckgen", + .id = UCLASS_CLK, + .of_match = mt8365_topckgen_compat, + .probe = mt8365_topckgen_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen_cg) = { + .name = "mt8365-topckgen-cg", + .id = UCLASS_CLK, + .of_match = mt8365_topckgen_cg_compat, + .probe = mt8365_topckgen_cg_probe, + .priv_auto = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_infracfg) = { + .name = "mt8365-infracfg", + .id = UCLASS_CLK, + .of_match = mt8365_infracfg_compat, + .probe = mt8365_infracfg_probe, + .priv_auto = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c index d0f5bb37530..5220a337a8b 100644 --- a/drivers/clk/meson/a1.c +++ b/drivers/clk/meson/a1.c @@ -607,14 +607,6 @@ static int meson_clk_set_parent(struct clk *clk, struct clk *parent_clk) return meson_mux_set_parent_by_id(clk, parent_clk->id); } -static struct clk_ops meson_clk_ops = { - .disable = meson_clk_disable, - .enable = meson_clk_enable, - .get_rate = meson_clk_get_rate, - .set_rate = meson_clk_set_rate, - .set_parent = meson_clk_set_parent, -}; - static int meson_clk_probe(struct udevice *dev) { struct meson_clk *priv = dev_get_priv(dev); @@ -644,15 +636,7 @@ static const struct udevice_id meson_clk_ids[] = { { } }; -U_BOOT_DRIVER(meson_clk) = { - .name = "meson-clk-a1", - .id = UCLASS_CLK, - .of_match = meson_clk_ids, - .priv_auto = sizeof(struct meson_clk), - .ops = &meson_clk_ops, - .probe = meson_clk_probe, -}; - +#if IS_ENABLED(CONFIG_CMD_CLK) static const char *meson_clk_get_name(struct clk *clk, int id) { const struct meson_clk_info *info; @@ -662,7 +646,7 @@ static const char *meson_clk_get_name(struct clk *clk, int id) return IS_ERR(info) ? "unknown" : info->name; } -static int meson_clk_dump(struct clk *clk) +static int meson_clk_dump_single(struct clk *clk) { const struct meson_clk_info *info; struct meson_clk *priv; @@ -697,7 +681,7 @@ static int meson_clk_dump(struct clk *clk) return 0; } -static int meson_clk_dump_dev(struct udevice *dev) +static void meson_clk_dump(struct udevice *dev) { int i; struct meson_clk_data *data; @@ -710,26 +694,30 @@ static int meson_clk_dump_dev(struct udevice *dev) data = (struct meson_clk_data *)dev_get_driver_data(dev); for (i = 0; i < data->num_clocks; i++) { - meson_clk_dump(&(struct clk){ + meson_clk_dump_single(&(struct clk){ .dev = dev, .id = i }); } - - return 0; } +#endif -int soc_clk_dump(void) -{ - struct udevice *dev; - int i = 0; - - while (!uclass_get_device(UCLASS_CLK, i++, &dev)) { - if (dev->driver == DM_DRIVER_GET(meson_clk)) { - meson_clk_dump_dev(dev); - printf("\n"); - } - } +static struct clk_ops meson_clk_ops = { + .disable = meson_clk_disable, + .enable = meson_clk_enable, + .get_rate = meson_clk_get_rate, + .set_rate = meson_clk_set_rate, + .set_parent = meson_clk_set_parent, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = meson_clk_dump, +#endif +}; - return 0; -} +U_BOOT_DRIVER(meson_clk) = { + .name = "meson-clk-a1", + .id = UCLASS_CLK, + .of_match = meson_clk_ids, + .priv_auto = sizeof(struct meson_clk), + .ops = &meson_clk_ops, + .probe = meson_clk_probe, +}; diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c index e75052f383c..1a7097029ae 100644 --- a/drivers/clk/mvebu/armada-37xx-periph.c +++ b/drivers/clk/mvebu/armada-37xx-periph.c @@ -488,33 +488,36 @@ static int armada_37xx_periph_clk_dump(struct udevice *dev) static int clk_dump(const char *name, int (*func)(struct udevice *)) { struct udevice *dev; + int ret; if (uclass_get_device_by_name(UCLASS_CLK, name, &dev)) { printf("Cannot find device %s\n", name); return -ENODEV; } - return func(dev); + ret = func(dev); + if (ret) + printf("Dump failed for %s: %d\n", name, ret); + + return ret; } int armada_37xx_tbg_clk_dump(struct udevice *); -int soc_clk_dump(void) +static void armada37xx_clk_dump(struct udevice __always_unused *dev) { printf(" xtal at %u000000 Hz\n\n", get_ref_clk()); if (clk_dump("tbg@13200", armada_37xx_tbg_clk_dump)) - return 1; + return; if (clk_dump("nb-periph-clk@13000", armada_37xx_periph_clk_dump)) - return 1; + return; if (clk_dump("sb-periph-clk@18000", armada_37xx_periph_clk_dump)) - return 1; - - return 0; + return; } #endif @@ -605,6 +608,9 @@ static const struct clk_ops armada_37xx_periph_clk_ops = { .set_parent = armada_37xx_periph_clk_set_parent, .enable = armada_37xx_periph_clk_enable, .disable = armada_37xx_periph_clk_disable, +#if IS_ENABLED(CONFIG_CMD_CLK) + .dump = armada37xx_clk_dump, +#endif }; static const struct udevice_id armada_37xx_periph_clk_ids[] = { diff --git a/drivers/clk/nuvoton/clk_npcm.c b/drivers/clk/nuvoton/clk_npcm.c index 8d71f2a24b8..18cb9cddbf3 100644 --- a/drivers/clk/nuvoton/clk_npcm.c +++ b/drivers/clk/nuvoton/clk_npcm.c @@ -135,7 +135,7 @@ static u32 npcm_clk_get_div(struct clk *clk) return div; } -static u32 npcm_clk_set_div(struct clk *clk, u32 div) +static int npcm_clk_set_div(struct clk *clk, u32 div) { struct npcm_clk_priv *priv = dev_get_priv(clk->dev); struct npcm_clk_div *divider; @@ -145,6 +145,9 @@ static u32 npcm_clk_set_div(struct clk *clk, u32 div) if (!divider) return -EINVAL; + if (divider->flags & DIV_RO) + return 0; + if (divider->flags & PRE_DIV2) div = div >> 1; @@ -153,6 +156,12 @@ static u32 npcm_clk_set_div(struct clk *clk, u32 div) else clkdiv = ilog2(div); + if (clkdiv > (divider->mask >> (ffs(divider->mask) - 1))) { + printf("clkdiv(%d) for clk(%ld) is over limit\n", + clkdiv, clk->id); + return -EINVAL; + } + val = readl(priv->base + divider->reg); val &= ~divider->mask; val |= (clkdiv << (ffs(divider->mask) - 1)) & divider->mask; @@ -253,8 +262,8 @@ static ulong npcm_clk_set_rate(struct clk *clk, ulong rate) if (ret) return ret; - debug("%s: rate %lu, new rate (%lu / %u)\n", __func__, rate, parent_rate, div); - return (parent_rate / div); + debug("%s: rate %lu, new rate %lu\n", __func__, rate, npcm_clk_get_rate(clk)); + return npcm_clk_get_rate(clk); } static int npcm_clk_set_parent(struct clk *clk, struct clk *parent) diff --git a/drivers/clk/nuvoton/clk_npcm.h b/drivers/clk/nuvoton/clk_npcm.h index 06b60dc8b8d..b4726d8381e 100644 --- a/drivers/clk/nuvoton/clk_npcm.h +++ b/drivers/clk/nuvoton/clk_npcm.h @@ -50,6 +50,7 @@ #define PRE_DIV2 BIT(2) /* Pre divisor = 2 */ #define POST_DIV2 BIT(3) /* Post divisor = 2 */ #define FIXED_PARENT BIT(4) /* clock source is fixed */ +#define DIV_RO BIT(5) /* divider is read-only */ /* Parameters of PLL configuration */ struct npcm_clk_pll { diff --git a/drivers/clk/nuvoton/clk_npcm8xx.c b/drivers/clk/nuvoton/clk_npcm8xx.c index 27e3cfcf553..d1b32e32371 100644 --- a/drivers/clk/nuvoton/clk_npcm8xx.c +++ b/drivers/clk/nuvoton/clk_npcm8xx.c @@ -45,12 +45,12 @@ static struct npcm_clk_select npcm8xx_clk_selectors[] = { }; static struct npcm_clk_div npcm8xx_clk_dividers[] = { - {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2}, - {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2}, - {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2}, - {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1}, - {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1}, - {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1}, + {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2 | DIV_RO}, + {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2 | DIV_RO}, + {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2 | DIV_RO}, + {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1 | DIV_RO}, + {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1 | DIV_RO}, + {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1 | DIV_RO}, {NPCM8XX_CLK_SPIX, CLKDIV3, SPIXCKDIV, DIV_TYPE1}, {NPCM8XX_CLK_UART, CLKDIV1, UARTDIV1, DIV_TYPE1}, {NPCM8XX_CLK_UART2, CLKDIV3, UARTDIV2, DIV_TYPE1}, diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index a835541e48e..a38694809a0 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -434,6 +434,15 @@ static int jh7110_syscrg_init(struct udevice *dev) starfive_clk_gate(priv->reg, "i2c5_apb", "apb0", OFFSET(JH7110_SYSCLK_I2C5_APB))); + /* Watchdog clocks */ + clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_APB), + starfive_clk_gate(priv->reg, + "wdt_apb", "apb0", + OFFSET(JH7110_SYSCLK_WDT_APB))); + clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_CORE), + starfive_clk_gate(priv->reg, + "wdt_core", "oscillator", + OFFSET(JH7110_SYSCLK_WDT_CORE))); /* enable noc_bus_stg_axi clock */ if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk)) diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c index f3ac8c75831..6f000c8e444 100644 --- a/drivers/clk/stm32/clk-stm32mp1.c +++ b/drivers/clk/stm32/clk-stm32mp1.c @@ -2225,10 +2225,13 @@ static void stm32mp1_osc_init(struct udevice *dev) } } -static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv) +static void __maybe_unused stm32mp1_clk_dump(struct udevice *dev) { char buf[32]; int i, s, p; + struct stm32mp1_clk_priv *priv; + + priv = dev_get_priv(dev); printf("Clocks:\n"); for (i = 0; i < _PARENT_NB; i++) { @@ -2252,27 +2255,6 @@ static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv) } } -#ifdef CONFIG_CMD_CLK -int soc_clk_dump(void) -{ - struct udevice *dev; - struct stm32mp1_clk_priv *priv; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_DRIVER_GET(stm32mp1_clock), - &dev); - if (ret) - return ret; - - priv = dev_get_priv(dev); - - stm32mp1_clk_dump(priv); - - return 0; -} -#endif - static int stm32mp1_clk_probe(struct udevice *dev) { int result = 0; @@ -2302,7 +2284,7 @@ static int stm32mp1_clk_probe(struct udevice *dev) #if defined(VERBOSE_DEBUG) /* display debug information for probe after relocation */ if (gd->flags & GD_FLG_RELOC) - stm32mp1_clk_dump(priv); + stm32mp1_clk_dump(dev); #endif gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU); @@ -2333,6 +2315,9 @@ static const struct clk_ops stm32mp1_clk_ops = { .disable = stm32mp1_clk_disable, .get_rate = stm32mp1_clk_get_rate, .set_rate = stm32mp1_clk_set_rate, +#if IS_ENABLED(CONFIG_CMD_CLK) && !IS_ENABLED(CONFIG_SPL_BUILD) + .dump = stm32mp1_clk_dump, +#endif }; U_BOOT_DRIVER(stm32mp1_clock) = { diff --git a/drivers/crypto/fsl/jobdesc.h b/drivers/crypto/fsl/jobdesc.h index c4501abd26b..69adfdca95b 100644 --- a/drivers/crypto/fsl/jobdesc.h +++ b/drivers/crypto/fsl/jobdesc.h @@ -7,7 +7,6 @@ #ifndef __JOBDESC_H #define __JOBDESC_H -#include <common.h> #include <asm/io.h> #include "rsa_caam.h" diff --git a/drivers/crypto/fsl/rsa_caam.h b/drivers/crypto/fsl/rsa_caam.h index 9a6a8afa4aa..fb132a3d181 100644 --- a/drivers/crypto/fsl/rsa_caam.h +++ b/drivers/crypto/fsl/rsa_caam.h @@ -6,8 +6,6 @@ #ifndef __RSA_CAAM_H #define __RSA_CAAM_H -#include <common.h> - /** * struct pk_in_params - holder for input to PKHA block in CAAM * These parameters are required to perform Modular Exponentiation diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 07a0f9f2ae9..87a70a861ba 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -6,7 +6,6 @@ #ifndef _SDRAM_SOC64_H_ #define _SDRAM_SOC64_H_ -#include <common.h> #include <linux/sizes.h> struct altera_sdram_priv { diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c index fd8b4113b7b..45e1a70dbd4 100644 --- a/drivers/ddr/imx/phy/ddrphy_utils.c +++ b/drivers/ddr/imx/phy/ddrphy_utils.c @@ -111,11 +111,16 @@ void ddrphy_init_set_dfi_clk(unsigned int drate) dram_pll_init(MHZ(1000)); dram_disable_bypass(); break; + case 3734: case 3733: case 3732: dram_pll_init(MHZ(933)); dram_disable_bypass(); break; + case 3600: + dram_pll_init(MHZ(900)); + dram_disable_bypass(); + break; case 3200: dram_pll_init(MHZ(800)); dram_disable_bypass(); diff --git a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h index 73573119658..dff56338b19 100644 --- a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h +++ b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h @@ -6,7 +6,6 @@ #ifndef _DDR_ML_WRAPPER_H #define _DDR_ML_WRAPPER_H -#include <common.h> #include <i2c.h> #include <spl.h> #include <asm/io.h> diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h index c40cd768abf..c3d282477f5 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp.h +++ b/drivers/ddr/marvell/axp/ddr3_axp.h @@ -6,6 +6,8 @@ #ifndef __DDR3_AXP_H #define __DDR3_AXP_H +#include <config.h> + #define MV_78XX0_Z1_REV 0x0 #define MV_78XX0_A0_REV 0x1 #define MV_78XX0_B0_REV 0x2 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index ba42b0768e1..63e62e1acd2 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -238,6 +238,15 @@ config MAX7320_GPIO original maxim device has 8 push/pull outputs, some clones offers 16bit. +config MAX77663_GPIO + bool "MAX77663 GPIO cell of PMIC driver" + depends on DM_GPIO && DM_PMIC_MAX77663 + help + GPIO driver for MAX77663 PMIC from Maxim Semiconductor. + MAX77663 PMIC has 8 pins that can be configured as GPIOs + and 3 GPIO-like pins dedicated for power/reset buttons + and LID sensor. + config MCP230XX_GPIO bool "MCP230XX GPIO driver" depends on DM @@ -426,6 +435,13 @@ config VYBRID_GPIO help Say yes here to support Vybrid vf610 GPIOs. +config PALMAS_GPIO + bool "TI PALMAS series PMICs GPIO" + depends on DM_GPIO && PMIC_PALMAS + help + Select this option to enable GPIO driver for the TI PALMAS + series chip family. + config PIC32_GPIO bool "Microchip PIC32 GPIO driver" depends on DM_GPIO && MACH_PIC32 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index c8b3fd78141..da3da5da2b3 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o obj-$(CONFIG_HSDK_CREG_GPIO) += hsdk-creg-gpio.o obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o +obj-$(CONFIG_$(SPL_)PALMAS_GPIO) += palmas_gpio.o obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o obj-$(CONFIG_OCTEON_GPIO) += octeon_gpio.o obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o @@ -68,6 +69,7 @@ obj-$(CONFIG_NX_GPIO) += nx_gpio.o obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o +obj-$(CONFIG_$(SPL_)MAX77663_GPIO) += max77663_gpio.o obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c index e6e919444f5..7a6eae9ba18 100644 --- a/drivers/gpio/dwapb_gpio.c +++ b/drivers/gpio/dwapb_gpio.c @@ -5,21 +5,15 @@ * DesignWare APB GPIO driver */ -#include <common.h> -#include <log.h> -#include <malloc.h> -#include <asm/arch/gpio.h> #include <asm/gpio.h> #include <asm/io.h> -#include <dm.h> +#include <dm/device.h> #include <dm/device-internal.h> #include <dm/device_compat.h> #include <dm/devres.h> -#include <dm/lists.h> -#include <dm/root.h> +#include <dm/read.h> #include <errno.h> #include <reset.h> -#include <linux/bitops.h> #define GPIO_SWPORT_DR(p) (0x00 + (p) * 0xc) #define GPIO_SWPORT_DDR(p) (0x04 + (p) * 0xc) diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index 2c5415c671d..1c3d18796b3 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -11,7 +11,6 @@ #include <asm/gpio.h> #include <config.h> -#include <common.h> #include <clk.h> #include <dm.h> #include <asm/io.h> diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 7aece85a70a..4234cd912c9 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -1143,9 +1143,29 @@ static int gpio_request_tail(int ret, const char *nodename, ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node, &desc->dev); if (ret) { +#if CONFIG_IS_ENABLED(MAX77663_GPIO) || CONFIG_IS_ENABLED(PALMAS_GPIO) + struct udevice *pmic; + ret = uclass_get_device_by_ofnode(UCLASS_PMIC, args->node, + &pmic); + if (ret) { + log_debug("%s: PMIC device get failed, err %d\n", + __func__, ret); + goto err; + } + + device_foreach_child(desc->dev, pmic) { + if (device_get_uclass_id(desc->dev) == UCLASS_GPIO) + break; + } + + /* if loop exits without GPIO device return error */ + if (device_get_uclass_id(desc->dev) != UCLASS_GPIO) + goto err; +#else debug("%s: uclass_get_device_by_ofnode failed\n", __func__); goto err; +#endif } } ret = gpio_find_and_xlate(desc, args); diff --git a/drivers/gpio/max77663_gpio.c b/drivers/gpio/max77663_gpio.c new file mode 100644 index 00000000000..ecb60478088 --- /dev/null +++ b/drivers/gpio/max77663_gpio.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <asm/gpio.h> +#include <power/max77663.h> +#include <power/pmic.h> + +#define NUM_ENTRIES 11 /* 8 GPIOs + 3 KEYs */ +#define NUM_GPIOS 8 + +#define MAX77663_CNFG1_GPIO 0x36 +#define GPIO_REG_ADDR(offset) (MAX77663_CNFG1_GPIO + (offset)) + +#define MAX77663_CNFG_GPIO_DIR_MASK BIT(1) +#define MAX77663_CNFG_GPIO_DIR_INPUT BIT(1) +#define MAX77663_CNFG_GPIO_DIR_OUTPUT 0 +#define MAX77663_CNFG_GPIO_INPUT_VAL_MASK BIT(2) +#define MAX77663_CNFG_GPIO_OUTPUT_VAL_MASK BIT(3) +#define MAX77663_CNFG_GPIO_OUTPUT_VAL_HIGH BIT(3) +#define MAX77663_CNFG_GPIO_OUTPUT_VAL_LOW 0 +#define MAX77663_CNFG_IRQ GENMASK(5, 4) + +#define MAX77663_ONOFFSTAT_REG 0x15 +#define EN0 BIT(2) /* KEY 2 */ +#define ACOK BIT(1) /* KEY 1 */ +#define LID BIT(0) /* KEY 0 */ + +static int max77663_gpio_direction_input(struct udevice *dev, unsigned int offset) +{ + int ret; + + if (offset >= NUM_GPIOS) + return 0; + + ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(offset), + MAX77663_CNFG_GPIO_DIR_MASK, + MAX77663_CNFG_GPIO_DIR_INPUT); + if (ret < 0) + log_debug("%s: CNFG_GPIOx dir update failed: %d\n", __func__, ret); + + return ret; +} + +static int max77663_gpio_direction_output(struct udevice *dev, unsigned int offset, + int value) +{ + u8 val; + int ret; + + if (offset >= NUM_GPIOS) + return -EINVAL; + + val = (value) ? MAX77663_CNFG_GPIO_OUTPUT_VAL_HIGH : + MAX77663_CNFG_GPIO_OUTPUT_VAL_LOW; + + ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(offset), + MAX77663_CNFG_GPIO_OUTPUT_VAL_MASK, val); + if (ret < 0) { + log_debug("%s: CNFG_GPIOx val update failed: %d\n", __func__, ret); + return ret; + } + + ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(offset), + MAX77663_CNFG_GPIO_DIR_MASK, + MAX77663_CNFG_GPIO_DIR_OUTPUT); + if (ret < 0) + log_debug("%s: CNFG_GPIOx dir update failed: %d\n", __func__, ret); + + return ret; +} + +static int max77663_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + int ret; + + if (offset >= NUM_GPIOS) { + ret = pmic_reg_read(dev->parent, MAX77663_ONOFFSTAT_REG); + if (ret < 0) { + log_debug("%s: ONOFFSTAT_REG read failed: %d\n", __func__, ret); + return ret; + } + + return !!(ret & BIT(offset - NUM_GPIOS)); + } + + ret = pmic_reg_read(dev->parent, GPIO_REG_ADDR(offset)); + if (ret < 0) { + log_debug("%s: CNFG_GPIOx read failed: %d\n", __func__, ret); + return ret; + } + + if (ret & MAX77663_CNFG_GPIO_DIR_MASK) + return !!(ret & MAX77663_CNFG_GPIO_INPUT_VAL_MASK); + else + return !!(ret & MAX77663_CNFG_GPIO_OUTPUT_VAL_MASK); +} + +static int max77663_gpio_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + u8 val; + int ret; + + if (offset >= NUM_GPIOS) + return -EINVAL; + + val = (value) ? MAX77663_CNFG_GPIO_OUTPUT_VAL_HIGH : + MAX77663_CNFG_GPIO_OUTPUT_VAL_LOW; + + ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(offset), + MAX77663_CNFG_GPIO_OUTPUT_VAL_MASK, val); + if (ret < 0) + log_debug("%s: CNFG_GPIO_OUT update failed: %d\n", __func__, ret); + + return ret; +} + +static int max77663_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + int ret; + + if (offset >= NUM_GPIOS) + return GPIOF_INPUT; + + ret = pmic_reg_read(dev->parent, GPIO_REG_ADDR(offset)); + if (ret < 0) { + log_debug("%s: CNFG_GPIOx read failed: %d\n", __func__, ret); + return ret; + } + + if (ret & MAX77663_CNFG_GPIO_DIR_MASK) + return GPIOF_INPUT; + else + return GPIOF_OUTPUT; +} + +static const struct dm_gpio_ops max77663_gpio_ops = { + .direction_input = max77663_gpio_direction_input, + .direction_output = max77663_gpio_direction_output, + .get_value = max77663_gpio_get_value, + .set_value = max77663_gpio_set_value, + .get_function = max77663_gpio_get_function, +}; + +static int max77663_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + int i, ret; + + uc_priv->gpio_count = NUM_ENTRIES; + uc_priv->bank_name = "GPIO"; + + /* + * GPIO interrupts may be left ON after bootloader, hence let's + * pre-initialize hardware to the expected state by disabling all + * the interrupts. + */ + for (i = 0; i < NUM_GPIOS; i++) { + ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(i), + MAX77663_CNFG_IRQ, 0); + if (ret < 0) { + log_debug("%s: failed to disable interrupt: %d\n", __func__, ret); + return ret; + } + } + + return 0; +} + +U_BOOT_DRIVER(max77663_gpio) = { + .name = MAX77663_GPIO_DRIVER, + .id = UCLASS_GPIO, + .probe = max77663_gpio_probe, + .ops = &max77663_gpio_ops, +}; diff --git a/drivers/gpio/palmas_gpio.c b/drivers/gpio/palmas_gpio.c new file mode 100644 index 00000000000..15039351dd5 --- /dev/null +++ b/drivers/gpio/palmas_gpio.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Based on mainline Linux palmas GPIO driver + * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <i2c.h> +#include <asm/gpio.h> +#include <power/palmas.h> + +#define NUM_GPIOS 8 + +static int palmas_gpio_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + struct palmas_priv *priv = dev_get_priv(dev->parent); + u32 reg; + int ret; + + reg = (value) ? PALMAS_GPIO_SET_DATA_OUT : PALMAS_GPIO_CLEAR_DATA_OUT; + + ret = dm_i2c_reg_write(priv->chip2, reg, BIT(offset)); + if (ret < 0) + log_debug("%s: Reg 0x%02x write failed, %d\n", __func__, reg, ret); + + return ret; +} + +static int palmas_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct palmas_priv *priv = dev_get_priv(dev->parent); + u32 reg; + int ret; + + ret = dm_i2c_reg_read(priv->chip2, PALMAS_GPIO_DATA_DIR); + if (ret < 0) { + log_debug("%s: GPIO_DATA_DIR read failed, %d\n", __func__, ret); + return ret; + } + + if (ret & BIT(offset)) + reg = PALMAS_GPIO_DATA_OUT; + else + reg = PALMAS_GPIO_DATA_IN; + + ret = dm_i2c_reg_read(priv->chip2, reg); + if (ret < 0) { + log_debug("%s: Reg 0x%02x read failed, %d\n", __func__, reg, ret); + return ret; + } + + return !!(ret & BIT(offset)); +} + +static int palmas_gpio_direction_input(struct udevice *dev, unsigned int offset) +{ + struct palmas_priv *priv = dev_get_priv(dev->parent); + int ret; + + ret = dm_i2c_reg_clrset(priv->chip2, PALMAS_GPIO_DATA_DIR, + BIT(offset), 0); + if (ret < 0) + log_debug("%s: GPIO_DATA_DIR val update failed: %d\n", __func__, ret); + + return ret; +} + +static int palmas_gpio_direction_output(struct udevice *dev, unsigned int offset, + int value) +{ + struct palmas_priv *priv = dev_get_priv(dev->parent); + int ret; + + /* Set the initial value */ + palmas_gpio_set_value(dev, offset, value); + + ret = dm_i2c_reg_clrset(priv->chip2, PALMAS_GPIO_DATA_DIR, + BIT(offset), BIT(offset)); + if (ret < 0) + log_debug("%s: GPIO_DATA_DIR val update failed: %d\n", __func__, ret); + + return ret; +} + +static int palmas_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct palmas_priv *priv = dev_get_priv(dev->parent); + int ret; + + ret = dm_i2c_reg_read(priv->chip2, PALMAS_GPIO_DATA_DIR); + if (ret < 0) { + log_debug("%s: GPIO_DATA_DIR read failed, %d\n", __func__, ret); + return ret; + } + + if (ret & BIT(offset)) + return GPIOF_OUTPUT; + else + return GPIOF_INPUT; +} + +static const struct dm_gpio_ops palmas_gpio_ops = { + .direction_input = palmas_gpio_direction_input, + .direction_output = palmas_gpio_direction_output, + .get_value = palmas_gpio_get_value, + .set_value = palmas_gpio_set_value, + .get_function = palmas_gpio_get_function, +}; + +static int palmas_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->gpio_count = NUM_GPIOS; + uc_priv->bank_name = "GPIO"; + + return 0; +} + +static const struct udevice_id palmas_ids[] = { + { .compatible = "ti,palmas-gpio" }, + { } +}; + +U_BOOT_DRIVER(palmas_gpio) = { + .name = PALMAS_GPIO_DRIVER, + .id = UCLASS_GPIO, + .of_match = palmas_ids, + .probe = palmas_gpio_probe, + .ops = &palmas_gpio_ops, +}; diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index dabc1f900d5..2ba6d9c1362 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -24,4 +24,20 @@ config APPLE_DART configuration to put the DART into bypass mode such that it can be used transparently by U-Boot. +config QCOM_HYP_SMMU + bool "Qualcomm quirky SMMU support" + depends on IOMMU && ARCH_SNAPDRAGON + help + Enable support for the Qualcomm variant of the Arm System MMU-500. + Qualcomm boards have a non-standard SMMU where some registers are + emulated by the hypervisor. It is initialised early in the boot + process and can't be turned off. + + The main caveat with this hardware is that it doesn't support BYPASS + streams, attempting to configure once will instead wind up with a + FAULT stream, and the device will crash when DMA is attempted. + + Say Y here to enable support for non-boot peripherals like USB by + configuring identity mapped streams for them. + endmenu diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index e3e0900e170..438cab8a7c4 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_IOMMU) += iommu-uclass.o obj-$(CONFIG_APPLE_DART) += apple_dart.o obj-$(CONFIG_SANDBOX) += sandbox_iommu.o +obj-$(CONFIG_QCOM_HYP_SMMU) += qcom-hyp-smmu.o diff --git a/drivers/iommu/iommu-uclass.c b/drivers/iommu/iommu-uclass.c index 72f123df55a..6babc0e3a67 100644 --- a/drivers/iommu/iommu-uclass.c +++ b/drivers/iommu/iommu-uclass.c @@ -77,6 +77,7 @@ int dev_iommu_enable(struct udevice *dev) { struct ofnode_phandle_args args; struct udevice *dev_iommu; + const struct iommu_ops *ops; int i, count, ret = 0; count = dev_count_phandle_with_args(dev, "iommus", @@ -98,11 +99,22 @@ int dev_iommu_enable(struct udevice *dev) return ret; } dev->iommu = dev_iommu; + + if (dev->parent && dev->parent->iommu == dev_iommu) + continue; + + ops = device_get_ops(dev->iommu); + if (ops && ops->connect) { + ret = ops->connect(dev); + if (ret) + return ret; + } } - if (CONFIG_IS_ENABLED(PCI) && count < 0 && - device_is_on_pci_bus(dev)) +#if CONFIG_IS_ENABLED(PCI) + if (count < 0 && device_is_on_pci_bus(dev)) return dev_pci_iommu_enable(dev); +#endif return 0; } diff --git a/drivers/iommu/qcom-hyp-smmu.c b/drivers/iommu/qcom-hyp-smmu.c new file mode 100644 index 00000000000..8e5cdb58155 --- /dev/null +++ b/drivers/iommu/qcom-hyp-smmu.c @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Linaro Ltd. + * Basic ARM SMMU-500 driver, assuming a pre-initialised SMMU and only IDENTITY domains + * this driver only implements the bare minimum to configure stream mappings for periphals + * used by u-boot on platforms where the SMMU can't be disabled. + */ + +#include <log.h> +#include <cpu_func.h> +#include <dm.h> +#include <iommu.h> +#include <linux/bitfield.h> +#include <linux/list.h> +#include <linux/err.h> +#include <lmb.h> +#include <memalign.h> +#include <asm/io.h> + +#define ARM_SMMU_GR0 0 +#define ARM_SMMU_GR1 1 + +#define ARM_SMMU_GR0_ID0 0x20 +#define ARM_SMMU_ID0_NUMSMRG GENMASK(7, 0) /* Number of stream mapping groups */ +#define ARM_SMMU_GR0_ID1 0x24 +#define ARM_SMMU_ID1_PAGESIZE \ + BIT(31) /* Page shift is 16 bits when set, otherwise 23 */ +#define ARM_SMMU_ID1_NUMPAGENDXB \ + GENMASK(30, 28) /* Number of pages before context banks */ +#define ARM_SMMU_ID1_NUMCB GENMASK(7, 0) /* Number of context banks supported */ + +#define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) +#define ARM_SMMU_CBAR_TYPE GENMASK(17, 16) +#define ARM_SMMU_CBAR_VMID GENMASK(7, 0) +enum arm_smmu_cbar_type { + CBAR_TYPE_S2_TRANS, + CBAR_TYPE_S1_TRANS_S2_BYPASS, + CBAR_TYPE_S1_TRANS_S2_FAULT, + CBAR_TYPE_S1_TRANS_S2_TRANS, +}; + +#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) +#define ARM_SMMU_CBA2R_VA64 BIT(0) + +/* Per-CB system control register */ +#define ARM_SMMU_CB_SCTLR 0x0 +#define ARM_SMMU_SCTLR_CFCFG BIT(7) /* Stall on context fault */ +#define ARM_SMMU_SCTLR_CFIE BIT(6) /* Context fault interrupt enable */ +#define ARM_SMMU_SCTLR_CFRE BIT(5) /* Abort on context fault */ + +/* Translation Table Base, holds address of translation table in memory to be used + * for this context bank. Or 0 for bypass + */ +#define ARM_SMMU_CB_TTBR0 0x20 +#define ARM_SMMU_CB_TTBR1 0x28 +/* Translation Control Register, configured TTBR/TLB behaviour (0 for bypass) */ +#define ARM_SMMU_CB_TCR 0x30 +/* Memory Attribute Indirection, also 0 for bypass */ +#define ARM_SMMU_CB_S1_MAIR0 0x38 +#define ARM_SMMU_CB_S1_MAIR1 0x3c + +#define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) +#define ARM_SMMU_SMR_VALID BIT(31) +#define ARM_SMMU_SMR_MASK GENMASK(31, 16) // Always 0 for now?? +#define ARM_SMMU_SMR_ID GENMASK(15, 0) + +#define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) +#define ARM_SMMU_S2CR_PRIVCFG GENMASK(25, 24) + +enum arm_smmu_s2cr_privcfg { + S2CR_PRIVCFG_DEFAULT, + S2CR_PRIVCFG_DIPAN, + S2CR_PRIVCFG_UNPRIV, + S2CR_PRIVCFG_PRIV, +}; + +#define ARM_SMMU_S2CR_TYPE GENMASK(17, 16) + +enum arm_smmu_s2cr_type { + S2CR_TYPE_TRANS, + S2CR_TYPE_BYPASS, + S2CR_TYPE_FAULT, +}; + +#define ARM_SMMU_S2CR_EXIDVALID BIT(10) +#define ARM_SMMU_S2CR_CBNDX GENMASK(7, 0) + +#define VMID_UNUSED 0xff + +struct qcom_smmu_priv { + phys_addr_t base; + struct list_head devices; + struct udevice *dev; + + /* Read-once config */ + int num_cb; + int num_smr; + u32 pgshift; + u32 cb_pg_offset; +}; + +struct mmu_dev { + struct list_head li; + struct udevice *dev; + u16 sid; + u16 cbx; + u16 smr; +}; + +#define page_addr(priv, page) ((priv)->base + ((page) << (priv)->pgshift)) + +#define smmu_readl(priv, page, offset) readl(page_addr(priv, page) + offset) +#define gr0_readl(priv, offset) smmu_readl(priv, ARM_SMMU_GR0, offset) +#define gr1_readl(priv, offset) smmu_readl(priv, ARM_SMMU_GR1, offset) +#define cbx_readl(priv, cbx, offset) \ + smmu_readl(priv, (priv->cb_pg_offset) + cbx, offset) + +#define smmu_writel(priv, page, offset, value) \ + writel((value), page_addr(priv, page) + offset) +#define gr0_writel(priv, offset, value) \ + smmu_writel(priv, ARM_SMMU_GR0, offset, (value)) +#define gr1_writel(priv, offset, value) \ + smmu_writel(priv, ARM_SMMU_GR1, offset, (value)) +#define cbx_writel(priv, cbx, offset, value) \ + smmu_writel(priv, (priv->cb_pg_offset) + cbx, offset, value) + +#define gr1_setbits(priv, offset, value) \ + gr1_writel(priv, offset, gr1_readl(priv, offset) | (value)) + +static int get_stream_id(struct udevice *dev) +{ + ofnode node = dev_ofnode(dev); + struct ofnode_phandle_args args; + int count = ofnode_parse_phandle_with_args(node, "iommus", + "#iommu-cells", 0, 0, &args); + + if (count < 0 || args.args[0] == 0) { + printf("Error: %s: iommus property not found or wrong number of cells\n", + __func__); + return -EINVAL; + } + + return args.args[0]; // Some mask from bit 16 onward? +} + +static struct mmu_dev *alloc_dev(struct udevice *dev) +{ + struct qcom_smmu_priv *priv = dev_get_priv(dev->iommu); + struct mmu_dev *mmu_dev; + int sid; + + sid = get_stream_id(dev); + debug("%s %s has SID %#x\n", dev->iommu->name, dev->name, sid); + if (sid < 0 || sid > 0xffff) { + printf("\tSMMU: Invalid stream ID for %s\n", dev->name); + return ERR_PTR(-EINVAL); + } + + /* We only support a single SID per device for now */ + list_for_each_entry(mmu_dev, &priv->devices, li) { + if (mmu_dev->sid == sid) + return ERR_PTR(-EEXIST); + } + + mmu_dev = calloc(sizeof(*mmu_dev), 1); + if (!mmu_dev) + return ERR_PTR(-ENOMEM); + + mmu_dev->dev = dev; + mmu_dev->sid = sid; + + list_add_tail(&mmu_dev->li, &priv->devices); + + return mmu_dev; +} + +/* Find and init the first free context bank */ +static int alloc_cb(struct qcom_smmu_priv *priv) +{ + u32 cbar, type, vmid, val; + + for (int i = 0; i < priv->num_cb; i++) { + cbar = gr1_readl(priv, ARM_SMMU_GR1_CBAR(i)); + type = FIELD_GET(ARM_SMMU_CBAR_TYPE, cbar); + vmid = FIELD_GET(ARM_SMMU_CBAR_VMID, cbar); + + /* Check that the context bank is available. We haven't reset the SMMU so + * we just make a best guess. + */ + if (type != CBAR_TYPE_S2_TRANS && + (type != CBAR_TYPE_S1_TRANS_S2_BYPASS || + vmid != VMID_UNUSED)) + continue; + + debug("%s: Found free context bank %d (cbar %#x)\n", + priv->dev->name, i, cbar); + type = CBAR_TYPE_S1_TRANS_S2_BYPASS; + vmid = 0; + cbar &= ~ARM_SMMU_CBAR_TYPE & ~ARM_SMMU_CBAR_VMID; + cbar |= FIELD_PREP(ARM_SMMU_CBAR_TYPE, type) | + FIELD_PREP(ARM_SMMU_CBAR_VMID, vmid); + gr1_writel(priv, ARM_SMMU_GR1_CBAR(i), cbar); + + val = IS_ENABLED(CONFIG_ARM64) == 1 ? ARM_SMMU_CBA2R_VA64 : 0; + gr1_setbits(priv, ARM_SMMU_GR1_CBA2R(i), val); + return i; + } + + return -1; +} + +/* Search for a context bank that is already configured for this stream + * returns the context bank index or -ENOENT + */ +static int find_smr(struct qcom_smmu_priv *priv, u16 stream_id) +{ + u32 val; + int i; + + for (i = 0; i < priv->num_smr; i++) { + val = gr0_readl(priv, ARM_SMMU_GR0_SMR(i)); + if (!(val & ARM_SMMU_SMR_VALID) || + FIELD_GET(ARM_SMMU_SMR_ID, val) != stream_id) + continue; + + return i; + } + + return -ENOENT; +} + +static int configure_smr_s2cr(struct qcom_smmu_priv *priv, struct mmu_dev *mdev) +{ + u32 val; + int i; + + for (i = 0; i < priv->num_smr; i++) { + /* Configure SMR */ + val = gr0_readl(priv, ARM_SMMU_GR0_SMR(i)); + if (val & ARM_SMMU_SMR_VALID) + continue; + + val = mdev->sid | ARM_SMMU_SMR_VALID; + gr0_writel(priv, ARM_SMMU_GR0_SMR(i), val); + + /* + * WARNING: Don't change this to use S2CR_TYPE_BYPASS! + * Some Qualcomm boards have angry hypervisor firmware + * that converts S2CR type BYPASS to type FAULT on write. + * We don't use virtual addressing for these boards in + * u-boot so we can get away with using S2CR_TYPE_TRANS + * instead + */ + val = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_TRANS) | + FIELD_PREP(ARM_SMMU_S2CR_CBNDX, mdev->cbx); + gr0_writel(priv, ARM_SMMU_GR0_S2CR(i), val); + + mdev->smr = i; + break; + } + + /* Make sure our writes went through */ + mb(); + + return 0; +} + +static int qcom_smmu_connect(struct udevice *dev) +{ + struct mmu_dev *mdev; + struct qcom_smmu_priv *priv; + int ret; + + debug("%s: %s -> %s\n", __func__, dev->name, dev->iommu->name); + + priv = dev_get_priv(dev->iommu); + if (WARN_ON(!priv)) + return -EINVAL; + + mdev = alloc_dev(dev); + if (IS_ERR(mdev) && PTR_ERR(mdev) != -EEXIST) { + printf("%s: %s Couldn't create mmu context\n", __func__, + dev->name); + return PTR_ERR(mdev); + } else if (IS_ERR(mdev)) { // -EEXIST + return 0; + } + + if (find_smr(priv, mdev->sid) >= 0) { + debug("Found existing context bank for %s, skipping init\n", + dev->name); + return 0; + } + + ret = alloc_cb(priv); + if (ret < 0 || ret > 0xff) { + printf("Error: %s: failed to allocate context bank for %s\n", + __func__, dev->name); + return 0; + } + mdev->cbx = ret; + + /* Configure context bank registers */ + cbx_writel(priv, mdev->cbx, ARM_SMMU_CB_TTBR0, 0x0); + cbx_writel(priv, mdev->cbx, ARM_SMMU_CB_TTBR1, 0x0); + cbx_writel(priv, mdev->cbx, ARM_SMMU_CB_S1_MAIR0, 0x0); + cbx_writel(priv, mdev->cbx, ARM_SMMU_CB_S1_MAIR1, 0x0); + cbx_writel(priv, mdev->cbx, ARM_SMMU_CB_SCTLR, + ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE | + ARM_SMMU_SCTLR_CFCFG); + cbx_writel(priv, mdev->cbx, ARM_SMMU_CB_TCR, 0x0); + + /* Ensure that our writes went through */ + mb(); + + configure_smr_s2cr(priv, mdev); + + return 0; +} + +#ifdef DEBUG +static inline void dump_boot_mappings(struct arm_smmu_priv *priv) +{ + u32 val; + int i; + + debug(" SMMU dump boot mappings:\n"); + for (i = 0; i < priv->num_smr; i++) { + val = gr0_readl(priv, ARM_SMMU_GR0_SMR(i)); + if (val & ARM_SMMU_SMR_VALID) + debug("\tSMR %3d: SID: %#lx\n", i, + FIELD_GET(ARM_SMMU_SMR_ID, val)); + } +} +#else +#define dump_boot_mappings(priv) \ + do { \ + } while (0) +#endif + +static int qcom_smmu_probe(struct udevice *dev) +{ + struct qcom_smmu_priv *priv; + u32 val; + + priv = dev_get_priv(dev); + priv->dev = dev; + priv->base = dev_read_addr(dev); + INIT_LIST_HEAD(&priv->devices); + + /* Read SMMU config */ + val = gr0_readl(priv, ARM_SMMU_GR0_ID0); + priv->num_smr = FIELD_GET(ARM_SMMU_ID0_NUMSMRG, val); + + val = gr0_readl(priv, ARM_SMMU_GR0_ID1); + priv->num_cb = FIELD_GET(ARM_SMMU_ID1_NUMCB, val); + priv->pgshift = FIELD_GET(ARM_SMMU_ID1_PAGESIZE, val) ? 16 : 12; + priv->cb_pg_offset = 1 + << (FIELD_GET(ARM_SMMU_ID1_NUMPAGENDXB, val) + 1); + + dump_boot_mappings(priv); + + return 0; +} + +static int qcom_smmu_remove(struct udevice *dev) +{ + (void)dev; + /* + * We should probably try and de-configure things here, + * however I'm yet to find a way to do it without crashing + * and it seems like Linux doesn't care at all anyway. + */ + + return 0; +} + +static struct iommu_ops qcom_smmu_ops = { + .connect = qcom_smmu_connect, +}; + +static const struct udevice_id qcom_smmu500_ids[] = { + { .compatible = "qcom,sdm845-smmu-500" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(qcom_smmu500) = { + .name = "qcom_smmu500", + .id = UCLASS_IOMMU, + .of_match = qcom_smmu500_ids, + .priv_auto = sizeof(struct qcom_smmu_priv), + .ops = &qcom_smmu_ops, + .probe = qcom_smmu_probe, + .remove = qcom_smmu_remove, + .flags = DM_FLAG_OS_PREPARE, +}; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 97057de8bf9..ed7ecedd3ac 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -615,7 +615,7 @@ config FS_LOADER ie. the FPGA device. config SPL_FS_LOADER - bool "Enable loader driver for file system" + bool "Enable loader driver for file system in SPL" depends on SPL help This is file system generic loader which can be used to load diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index d21a30c9543..5a0c61daed5 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -1665,7 +1665,7 @@ static int msdc_drv_probe(struct udevice *dev) if (cfg->f_max < cfg->f_min || cfg->f_max > host->src_clk_freq) cfg->f_max = host->src_clk_freq; - cfg->b_max = 1024; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; host->mmc = &plat->mmc; diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index d507adbb363..c01fb3d0165 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -698,7 +698,7 @@ static int tegra_mmc_probe(struct udevice *dev) * (actually 52MHz) */ cfg->f_min = 375000; - cfg->f_max = 48000000; + cfg->f_max = dev_read_u32_default(dev, "max-frequency", 48000000); cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile index 3051de4f7ef..f172f4787f8 100644 --- a/drivers/mtd/nand/spi/Makefile +++ b/drivers/mtd/nand/spi/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o +spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o +spinand-objs += toshiba.o winbond.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 597b088ca7e..8ca33459f96 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -828,6 +828,7 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = { ¶gon_spinand_manufacturer, &toshiba_spinand_manufacturer, &winbond_spinand_manufacturer, + &esmt_c8_spinand_manufacturer, }; static int spinand_manufacturer_match(struct spinand_device *spinand, diff --git a/drivers/mtd/nand/spi/esmt.c b/drivers/mtd/nand/spi/esmt.c new file mode 100644 index 00000000000..7e07b26827a --- /dev/null +++ b/drivers/mtd/nand/spi/esmt.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Author: + * Chuanhong Guo <gch981213@gmail.com> - the main driver logic + * Martin Kurbanov <mmkurbanov@sberdevices.ru> - OOB layout + */ + +#ifndef __UBOOT__ +#include <linux/device.h> +#include <linux/kernel.h> +#endif +#include <linux/mtd/spinand.h> + +/* ESMT uses GigaDevice 0xc8 JECDEC ID on some SPI NANDs */ +#define SPINAND_MFR_ESMT_C8 0xc8 + +static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +static SPINAND_OP_VARIANTS(write_cache_variants, + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(update_cache_variants, + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + +/* + * OOB spare area map (64 bytes) + * + * Bad Block Markers + * filled by HW and kernel Reserved + * | +-----------------------+-----------------------+ + * | | | | + * | | OOB free data Area |non ECC protected | + * | +-------------|-----+-----------------|-----+-----------------|-----+ + * | | | | | | | | + * +-|---|----------+--|-----|--------------+--|-----|--------------+--|-----|--------------+ + * | | | section0 | | | section1 | | | section2 | | | section3 | + * +-v-+-v-+---+----+--v--+--v--+-----+-----+--v--+--v--+-----+-----+--v--+--v--+-----+-----+ + * | | | | | | | | | | | | | | | | | + * |0:1|2:3|4:7|8:15|16:17|18:19|20:23|24:31|32:33|34:35|36:39|40:47|48:49|50:51|52:55|56:63| + * | | | | | | | | | | | | | | | | | + * +---+---+-^-+--^-+-----+-----+--^--+--^--+-----+-----+--^--+--^--+-----+-----+--^--+--^--+ + * | | | | | | | | + * | +----------------|-----+-----------------|-----+-----------------|-----+ + * | ECC Area|(Main + Spare) - filled|by ESMT NAND HW | + * | | | | + * +---------------------+-----------------------+-----------------------+ + * OOB ECC protected Area - not used due to + * partial programming from some filesystems + * (like JFFS2 with cleanmarkers) + */ + +#define ESMT_OOB_SECTION_COUNT 4 +#define ESMT_OOB_SECTION_SIZE(nand) \ + (nanddev_per_page_oobsize(nand) / ESMT_OOB_SECTION_COUNT) +#define ESMT_OOB_FREE_SIZE(nand) \ + (ESMT_OOB_SECTION_SIZE(nand) / 2) +#define ESMT_OOB_ECC_SIZE(nand) \ + (ESMT_OOB_SECTION_SIZE(nand) - ESMT_OOB_FREE_SIZE(nand)) +#define ESMT_OOB_BBM_SIZE 2 + +static int f50l1g41lb_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + struct nand_device *nand = mtd_to_nanddev(mtd); + + if (section >= ESMT_OOB_SECTION_COUNT) + return -ERANGE; + + region->offset = section * ESMT_OOB_SECTION_SIZE(nand) + + ESMT_OOB_FREE_SIZE(nand); + region->length = ESMT_OOB_ECC_SIZE(nand); + + return 0; +} + +static int f50l1g41lb_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + struct nand_device *nand = mtd_to_nanddev(mtd); + + if (section >= ESMT_OOB_SECTION_COUNT) + return -ERANGE; + + /* + * Reserve space for bad blocks markers (section0) and + * reserved bytes (sections 1-3) + */ + region->offset = section * ESMT_OOB_SECTION_SIZE(nand) + 2; + + /* Use only 2 non-protected ECC bytes per each OOB section */ + region->length = 2; + + return 0; +} + +static const struct mtd_ooblayout_ops f50l1g41lb_ooblayout = { + .ecc = f50l1g41lb_ooblayout_ecc, + .rfree = f50l1g41lb_ooblayout_free, +}; + +static const struct spinand_info esmt_c8_spinand_table[] = { + SPINAND_INFO("F50L1G41LB", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(1, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)), + SPINAND_INFO("F50D1G41LB", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x11), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(1, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)), +}; + +static const struct spinand_manufacturer_ops esmt_spinand_manuf_ops = { +}; + +const struct spinand_manufacturer esmt_c8_spinand_manufacturer = { + .id = SPINAND_MFR_ESMT_C8, + .name = "ESMT", + .chips = esmt_c8_spinand_table, + .nchips = ARRAY_SIZE(esmt_c8_spinand_table), + .ops = &esmt_spinand_manuf_ops, +}; diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 732b0760452..d068b7860e1 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -176,6 +176,11 @@ config SPI_FLASH_MACRONIX help Add support for various Macronix SPI flash chips (MX25Lxxx) +config SPI_FLASH_SILICONKAISER + bool "Silicon Kaiser SPI flash support" + help + Add support for various Silicon Kaiser SPI flash chips (SK25Lxxx) + config SPI_FLASH_SPANSION bool "Spansion SPI flash support" help @@ -224,6 +229,11 @@ config SPI_FLASH_XTX Add support for various XTX (XTX Technology Limited) SPI flash chips (XT25xxx). +config SPI_FLASH_ZBIT + bool "ZBIT SPI flash support" + help + Add support for Zbit Semiconductor Inc. SPI flash chips (ZB25xxx). + endif config SPI_FLASH_USE_4K_SECTORS diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 9a1801ba93d..3f5f3c89ac1 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2089,6 +2089,36 @@ read_err: return ret; } +/** + * spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters. + * @nor: pointer to a 'struct spi_nor' + * @addr: offset in the SFDP area to start reading data from + * @len: number of bytes to read + * @buf: buffer where the SFDP data are copied into + * + * Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not + * guaranteed to be dma-safe. + * + * Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp() + * otherwise. + */ +static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr, + size_t len, void *buf) +{ + void *dma_safe_buf; + int ret; + + dma_safe_buf = kmalloc(len, GFP_KERNEL); + if (!dma_safe_buf) + return -ENOMEM; + + ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf); + memcpy(buf, dma_safe_buf, len); + kfree(dma_safe_buf); + + return ret; +} + /* Fast Read settings. */ static void @@ -2262,7 +2292,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, bfpt_header->length * sizeof(u32)); addr = SFDP_PARAM_HEADER_PTP(bfpt_header); memset(&bfpt, 0, sizeof(bfpt)); - err = spi_nor_read_sfdp(nor, addr, len, &bfpt); + err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt); if (err < 0) return err; @@ -2588,7 +2618,7 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor, int i, err; /* Get the SFDP header. */ - err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header); + err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header); if (err < 0) return err; diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3cb132dcffc..8db522fca06 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -200,6 +200,11 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, {INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + { + INFO("gd55lb02ge", 0xc8671c, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ @@ -287,6 +292,10 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25uw6345g", 0xc28437, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, #endif +#ifdef CONFIG_SPI_FLASH_SILICONKAISER + { INFO("sk25lp128", 0x257018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, +#endif + #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ /* Micron */ { INFO("n25q016a", 0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, @@ -300,6 +309,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) }, { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) }, + { INFO("mt25qu128ab", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, @@ -309,6 +319,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + { INFO6("mt25qu01g", 0x20bb21, 0x104400, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, #ifdef CONFIG_SPI_FLASH_MT35XU @@ -513,6 +524,16 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q01jvfim", 0xef7021, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25q02jv", 0xef7022, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, @@ -566,11 +587,18 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("xt25q01g", 0x0b601B, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("xt55q02g", 0x0b601C, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, /* adding these wide voltage QSPI flash parts */ { INFO("xt25w512", 0x0b651A, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("xt25w01g", 0x0b651B, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, #endif +#ifdef CONFIG_SPI_FLASH_ZBIT + /* Zbit Semiconductor Inc. */ + { INFO("zb25vq128", 0x5e4018, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, +#endif { }, }; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 23ad2c29d0a..b2d7b499766 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -980,4 +980,11 @@ config MDIO_MUX_MESON_G12A This driver is used for the MDIO mux found on the Amlogic G12A & compatible SoCs. +config MDIO_MUX_MESON_GXL + bool "MDIO MUX for Amlogic Meson GXL SoCs" + depends on DM_MDIO_MUX + help + This driver is used for the MDIO mux found on the Amlogic GXL & compatible + SoCs. + endif # NETDEVICES diff --git a/drivers/net/Makefile b/drivers/net/Makefile index f9aed1646c9..6677366ebd6 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o obj-$(CONFIG_MDIO_MUX_MESON_G12A) += mdio_mux_meson_g12a.o +obj-$(CONFIG_MDIO_MUX_MESON_GXL) += mdio_mux_meson_gxl.o obj-$(CONFIG_MDIO_MUX_MMIOREG) += mdio_mux_mmioreg.o obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h index a2d5b03429a..5c45ad56d0a 100644 --- a/drivers/net/fm/fm.h +++ b/drivers/net/fm/fm.h @@ -6,7 +6,6 @@ #ifndef __FM_H__ #define __FM_H__ -#include <common.h> #include <phy.h> #include <fm_eth.h> #include <fsl_fman.h> diff --git a/drivers/net/fsl-mc/dpio/qbman_private.h b/drivers/net/fsl-mc/dpio/qbman_private.h index 53f1300eaf8..f9dad178075 100644 --- a/drivers/net/fsl-mc/dpio/qbman_private.h +++ b/drivers/net/fsl-mc/dpio/qbman_private.h @@ -4,7 +4,6 @@ */ /* Perform extra checking */ -#include <common.h> #include <errno.h> #include <asm/io.h> #include <linux/bug.h> diff --git a/drivers/net/fsl-mc/dpio/qbman_sys.h b/drivers/net/fsl-mc/dpio/qbman_sys.h index 1c6e4891302..cac70a1291c 100644 --- a/drivers/net/fsl-mc/dpio/qbman_sys.h +++ b/drivers/net/fsl-mc/dpio/qbman_sys.h @@ -20,6 +20,7 @@ /* Trace the 3 different classes of read/write access to QBMan. #undef as * required. */ +#include <config.h> #include <linux/bug.h> #include <linux/printk.h> #undef QBMAN_CCSR_TRACE diff --git a/drivers/net/mdio_mux_meson_gxl.c b/drivers/net/mdio_mux_meson_gxl.c new file mode 100644 index 00000000000..8ef3ae598b7 --- /dev/null +++ b/drivers/net/mdio_mux_meson_gxl.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Baylibre, SAS. + * Author: Jerome Brunet <jbrunet@baylibre.com> + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org> + */ + +#include <dm.h> +#include <errno.h> +#include <log.h> +#include <miiphy.h> +#include <asm/io.h> +#include <linux/bitfield.h> +#include <linux/delay.h> + +#define ETH_REG2 0x0 +#define REG2_PHYID GENMASK(21, 0) +#define EPHY_GXL_ID 0x110181 +#define REG2_LEDACT GENMASK(23, 22) +#define REG2_LEDLINK GENMASK(25, 24) +#define REG2_DIV4SEL BIT(27) +#define REG2_ADCBYPASS BIT(30) +#define REG2_CLKINSEL BIT(31) +#define ETH_REG3 0x4 +#define REG3_ENH BIT(3) +#define REG3_CFGMODE GENMASK(6, 4) +#define REG3_AUTOMDIX BIT(7) +#define REG3_PHYADDR GENMASK(12, 8) +#define REG3_PWRUPRST BIT(21) +#define REG3_PWRDOWN BIT(22) +#define REG3_LEDPOL BIT(23) +#define REG3_PHYMDI BIT(26) +#define REG3_CLKINEN BIT(29) +#define REG3_PHYIP BIT(30) +#define REG3_PHYEN BIT(31) +#define ETH_REG4 0x8 +#define REG4_PWRUPRSTSIG BIT(0) + +#define MESON_GXL_MDIO_EXTERNAL_ID 0 +#define MESON_GXL_MDIO_INTERNAL_ID 1 + +struct mdio_mux_meson_gxl_priv { + phys_addr_t regs; +}; + +static int meson_gxl_enable_internal_mdio(struct mdio_mux_meson_gxl_priv *priv) +{ + u32 val; + + /* Setup the internal phy */ + val = (REG3_ENH | + FIELD_PREP(REG3_CFGMODE, 0x7) | + REG3_AUTOMDIX | + FIELD_PREP(REG3_PHYADDR, 8) | + REG3_LEDPOL | + REG3_PHYMDI | + REG3_CLKINEN | + REG3_PHYIP); + + writel(REG4_PWRUPRSTSIG, priv->regs + ETH_REG4); + writel(val, priv->regs + ETH_REG3); + mdelay(10); + + /* NOTE: The HW kept the phy id configurable at runtime. + * The id below is arbitrary. It is the one used in the vendor code. + * The only constraint is that it must match the one in + * drivers/net/phy/meson-gxl.c to properly match the PHY. + */ + writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID), + priv->regs + ETH_REG2); + + /* Enable the internal phy */ + val |= REG3_PHYEN; + writel(val, priv->regs + ETH_REG3); + writel(0, priv->regs + ETH_REG4); + + /* The phy needs a bit of time to power up */ + mdelay(10); + + return 0; +} + +static int meson_gxl_enable_external_mdio(struct mdio_mux_meson_gxl_priv *priv) +{ + /* Reset the mdio bus mux to the external phy */ + writel(0, priv->regs + ETH_REG3); + + return 0; +} + +static int mdio_mux_meson_gxl_select(struct udevice *mux, int cur, int sel) +{ + struct mdio_mux_meson_gxl_priv *priv = dev_get_priv(mux); + + debug("%s: %x -> %x\n", __func__, (u32)cur, (u32)sel); + + /* if last selection didn't change we're good to go */ + if (cur == sel) + return 0; + + switch (sel) { + case MESON_GXL_MDIO_EXTERNAL_ID: + return meson_gxl_enable_external_mdio(priv); + case MESON_GXL_MDIO_INTERNAL_ID: + return meson_gxl_enable_internal_mdio(priv); + default: + return -EINVAL; + } + + return 0; +} + +static const struct mdio_mux_ops mdio_mux_meson_gxl_ops = { + .select = mdio_mux_meson_gxl_select, +}; + +static int mdio_mux_meson_gxl_probe(struct udevice *dev) +{ + struct mdio_mux_meson_gxl_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr(dev); + + return 0; +} + +static const struct udevice_id mdio_mux_meson_gxl_ids[] = { + { .compatible = "amlogic,gxl-mdio-mux" }, + { } +}; + +U_BOOT_DRIVER(mdio_mux_meson_gxl) = { + .name = "mdio_mux_meson_gxl", + .id = UCLASS_MDIO_MUX, + .of_match = mdio_mux_meson_gxl_ids, + .probe = mdio_mux_meson_gxl_probe, + .ops = &mdio_mux_meson_gxl_ops, + .priv_auto = sizeof(struct mdio_mux_meson_gxl_priv), +}; diff --git a/drivers/net/mscc_eswitch/mscc_mac_table.c b/drivers/net/mscc_eswitch/mscc_mac_table.c index 25b9cad42c9..06e1f625fb7 100644 --- a/drivers/net/mscc_eswitch/mscc_mac_table.c +++ b/drivers/net/mscc_eswitch/mscc_mac_table.c @@ -3,6 +3,7 @@ * Copyright (c) 2018 Microsemi Corporation */ +#include <errno.h> #include <linux/bitops.h> #include <linux/io.h> #include "mscc_mac_table.h" diff --git a/drivers/net/mscc_eswitch/mscc_mac_table.h b/drivers/net/mscc_eswitch/mscc_mac_table.h index 17fed2e7925..5ec8db25417 100644 --- a/drivers/net/mscc_eswitch/mscc_mac_table.h +++ b/drivers/net/mscc_eswitch/mscc_mac_table.h @@ -3,8 +3,6 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include <common.h> - #define ETH_LEN 6 #define MAC_VID 1 diff --git a/drivers/net/mscc_eswitch/mscc_xfer.c b/drivers/net/mscc_eswitch/mscc_xfer.c index 6f747464571..ee6bf065d3a 100644 --- a/drivers/net/mscc_eswitch/mscc_xfer.c +++ b/drivers/net/mscc_eswitch/mscc_xfer.c @@ -3,6 +3,7 @@ * Copyright (c) 2018 Microsemi Corporation */ +#include <errno.h> #include <log.h> #include <linux/bitops.h> #include <linux/delay.h> diff --git a/drivers/net/mscc_eswitch/mscc_xfer.h b/drivers/net/mscc_eswitch/mscc_xfer.h index c880a4e7e6a..70f279401e1 100644 --- a/drivers/net/mscc_eswitch/mscc_xfer.h +++ b/drivers/net/mscc_eswitch/mscc_xfer.h @@ -3,8 +3,6 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include <common.h> - enum mscc_regs_qs { MSCC_QS_XTR_RD, MSCC_QS_XTR_FLUSH, diff --git a/drivers/pci/pcie_layerscape_fixup_common.h b/drivers/pci/pcie_layerscape_fixup_common.h index 70bd3f0cba3..3255b7648c0 100644 --- a/drivers/pci/pcie_layerscape_fixup_common.h +++ b/drivers/pci/pcie_layerscape_fixup_common.h @@ -9,8 +9,6 @@ #ifndef _PCIE_LAYERSCAPE_FIXUP_COMMON_H_ #define _PCIE_LAYERSCAPE_FIXUP_COMMON_H_ -#include <common.h> - void ft_pci_setup_ls(void *blob, struct bd_info *bd); #ifdef CONFIG_PCIE_LAYERSCAPE_GEN4 diff --git a/drivers/pci_endpoint/pcie-cadence.h b/drivers/pci_endpoint/pcie-cadence.h index 8a659c36aa2..dd0101a33af 100644 --- a/drivers/pci_endpoint/pcie-cadence.h +++ b/drivers/pci_endpoint/pcie-cadence.h @@ -11,7 +11,6 @@ #ifndef PCIE_CADENCE_H #define PCIE_CADENCE_H -#include <common.h> #include <pci_ep.h> #include <asm/io.h> #include <linux/bitops.h> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 75b3ff47a2e..fceafea24c2 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -358,6 +358,7 @@ source "drivers/pinctrl/nxp/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/rockchip/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" +source "drivers/pinctrl/tegra/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" source "drivers/pinctrl/starfive/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index fc1f01a02cb..96a0516fe08 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_RMOBILE) += renesas/ obj-$(CONFIG_ARCH_RZN1) += renesas/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ +obj-$(CONFIG_$(SPL_)PINCTRL_TEGRA) += tegra/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl_pic32.o obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/ diff --git a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h index 1f1023ef421..7a38f8d8753 100644 --- a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h +++ b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h @@ -8,8 +8,6 @@ #ifndef _PINCTRL_MTMIPS_COMMON_H_ #define _PINCTRL_MTMIPS_COMMON_H_ -#include <common.h> - struct mtmips_pmx_func { const char *name; int value; diff --git a/drivers/pinctrl/tegra/Kconfig b/drivers/pinctrl/tegra/Kconfig new file mode 100644 index 00000000000..669d8e258e4 --- /dev/null +++ b/drivers/pinctrl/tegra/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0 + +config PINCTRL_TEGRA + bool "Nvidia Tegra pinctrl driver" + depends on DM + help + Support pin multiplexing control on Nvidia Tegra SoCs. + The driver is an overlay to existing driver and allows + the usage of dedicated device tree node which contains + full description of each pin. + +config SPL_PINCTRL_TEGRA + bool "Nvidia Tegra SPL pinctrl driver" + depends on SPL_PINCTRL + help + Enables support of pre-DM version of pin multiplexing + control driver used on SPL stage for board setup and + available for backwards compatibility purpose. diff --git a/drivers/pinctrl/tegra/Makefile b/drivers/pinctrl/tegra/Makefile new file mode 100644 index 00000000000..75d3cabc62b --- /dev/null +++ b/drivers/pinctrl/tegra/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +ifndef CONFIG_SPL_BUILD +ifdef CONFIG_TEGRA20 +obj-y += pinctrl-tegra20.o +else +obj-y += pinctrl-tegra.o +endif +endif + +obj-y += pinmux-common.o + +obj-$(CONFIG_TEGRA20) += pinmux-tegra20.o funcmux-tegra20.o +obj-$(CONFIG_TEGRA30) += pinmux-tegra30.o funcmux-tegra30.o +obj-$(CONFIG_TEGRA114) += pinmux-tegra114.o funcmux-tegra114.o +obj-$(CONFIG_TEGRA124) += pinmux-tegra124.o funcmux-tegra124.o +obj-$(CONFIG_TEGRA210) += pinmux-tegra210.o funcmux-tegra210.o diff --git a/arch/arm/mach-tegra/tegra114/funcmux.c b/drivers/pinctrl/tegra/funcmux-tegra114.c index 23a27c86888..23a27c86888 100644 --- a/arch/arm/mach-tegra/tegra114/funcmux.c +++ b/drivers/pinctrl/tegra/funcmux-tegra114.c diff --git a/arch/arm/mach-tegra/tegra124/funcmux.c b/drivers/pinctrl/tegra/funcmux-tegra124.c index e7ad85fde2d..e7ad85fde2d 100644 --- a/arch/arm/mach-tegra/tegra124/funcmux.c +++ b/drivers/pinctrl/tegra/funcmux-tegra124.c diff --git a/arch/arm/mach-tegra/tegra20/funcmux.c b/drivers/pinctrl/tegra/funcmux-tegra20.c index 90fe0cba8ea..90fe0cba8ea 100644 --- a/arch/arm/mach-tegra/tegra20/funcmux.c +++ b/drivers/pinctrl/tegra/funcmux-tegra20.c diff --git a/arch/arm/mach-tegra/tegra210/funcmux.c b/drivers/pinctrl/tegra/funcmux-tegra210.c index 30d994a17ff..30d994a17ff 100644 --- a/arch/arm/mach-tegra/tegra210/funcmux.c +++ b/drivers/pinctrl/tegra/funcmux-tegra210.c diff --git a/arch/arm/mach-tegra/tegra30/funcmux.c b/drivers/pinctrl/tegra/funcmux-tegra30.c index c3ee787f33b..c3ee787f33b 100644 --- a/arch/arm/mach-tegra/tegra30/funcmux.c +++ b/drivers/pinctrl/tegra/funcmux-tegra30.c diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c new file mode 100644 index 00000000000..ad7112a05e6 --- /dev/null +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/pinctrl.h> +#include <stdlib.h> + +#include <asm/arch/pinmux.h> + +static void tegra_pinctrl_set_drive(struct udevice *config, int drvcnt) +{ + struct pmux_drvgrp_config *drive_group; + int i, ret, pad_id; + const char **pads; + + drive_group = kmalloc_array(drvcnt, sizeof(*drive_group), GFP_KERNEL); + if (!drive_group) { + log_debug("%s: cannot allocate drive group array\n", __func__); + return; + } + + drive_group[0].slwf = dev_read_u32_default(config, "nvidia,slew-rate-falling", 0); + drive_group[0].slwr = dev_read_u32_default(config, "nvidia,slew-rate-rising", 0); + drive_group[0].drvup = dev_read_u32_default(config, "nvidia,pull-up-strength", 0); + drive_group[0].drvdn = dev_read_u32_default(config, "nvidia,pull-down-strength", 0); +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD + drive_group[0].lpmd = dev_read_u32_default(config, "nvidia,low-power-mode", 0); +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT + drive_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0); +#endif +#ifdef TEGRA_PMX_GRPS_HAVE_HSM + drive_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0); +#endif + + for (i = 1; i < drvcnt; i++) + memcpy(&drive_group[i], &drive_group[0], sizeof(drive_group[0])); + + ret = dev_read_string_list(config, "nvidia,pins", &pads); + if (ret < 0) { + log_debug("%s: could not parse property nvidia,pins\n", __func__); + goto exit; + } + + for (i = 0; i < drvcnt; i++) { + for (pad_id = 0; pad_id < PMUX_DRVGRP_COUNT; pad_id++) + if (tegra_pinctrl_to_drvgrp[pad_id]) + if (!strcmp(pads[i], tegra_pinctrl_to_drvgrp[pad_id])) { + drive_group[i].drvgrp = pad_id; + break; + } + + debug("%s drvmap: %d, %d, %d, %d, %d\n", pads[i], + drive_group[i].drvgrp, drive_group[i].slwf, + drive_group[i].slwr, drive_group[i].drvup, + drive_group[i].drvdn); + } + + pinmux_config_drvgrp_table(drive_group, drvcnt); + + free(pads); +exit: + kfree(drive_group); +} + +static void tegra_pinctrl_set_pin(struct udevice *config, int pincnt) +{ + struct pmux_pingrp_config *pinmux_group; + int i, ret, pin_id; + const char *function; + const char **pins; + + pinmux_group = kmalloc_array(pincnt, sizeof(*pinmux_group), GFP_KERNEL); + if (!pinmux_group) { + log_debug("%s: cannot allocate pinmux group array\n", __func__); + return; + } + + /* decode function id and fill the first copy of pmux_pingrp_config */ + function = dev_read_string(config, "nvidia,function"); + if (function) + for (i = 0; i < PMUX_FUNC_COUNT; i++) + if (tegra_pinctrl_to_func[i]) + if (!strcmp(function, tegra_pinctrl_to_func[i])) + break; + + pinmux_group[0].func = i; + + pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", 0); + pinmux_group[0].tristate = dev_read_u32_default(config, "nvidia,tristate", 0); +#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT + pinmux_group[0].io = dev_read_u32_default(config, "nvidia,enable-input", 0); +#endif +#ifdef TEGRA_PMX_PINS_HAVE_LOCK + pinmux_group[0].lock = dev_read_u32_default(config, "nvidia,lock", 0); +#endif +#ifdef TEGRA_PMX_PINS_HAVE_OD + pinmux_group[0].od = dev_read_u32_default(config, "nvidia,open-drain", 0); +#endif +#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET + pinmux_group[0].ioreset = dev_read_u32_default(config, "nvidia,io-reset", 0); +#endif +#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL + pinmux_group[0].rcv_sel = dev_read_u32_default(config, "nvidia,rcv-sel", 0); +#endif +#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV + pinmux_group[0].e_io_hv = dev_read_u32_default(config, "nvidia,io-hv", 0); +#endif +#ifdef TEGRA_PMX_PINS_HAVE_SCHMT + pinmux_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0); +#endif +#ifdef TEGRA_PMX_PINS_HAVE_HSM + pinmux_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0); +#endif + + for (i = 1; i < pincnt; i++) + memcpy(&pinmux_group[i], &pinmux_group[0], sizeof(pinmux_group[0])); + + ret = dev_read_string_list(config, "nvidia,pins", &pins); + if (ret < 0) { + log_debug("%s: could not parse property nvidia,pins\n", __func__); + goto exit; + } + + for (i = 0; i < pincnt; i++) { + for (pin_id = 0; pin_id < PMUX_PINGRP_COUNT; pin_id++) + if (tegra_pinctrl_to_pingrp[pin_id]) + if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id])) { + pinmux_group[i].pingrp = pin_id; + break; + } + + debug("%s pinmap: %d, %d, %d, %d\n", pins[i], + pinmux_group[i].pingrp, pinmux_group[i].func, + pinmux_group[i].pull, pinmux_group[i].tristate); + } + + pinmux_config_pingrp_table(pinmux_group, pincnt); + + free(pins); +exit: + kfree(pinmux_group); +} + +static int tegra_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + struct udevice *child; + int ret; + const char *name; + + device_foreach_child(child, config) { + /* Pinmux node can contain pins and drives */ + ret = dev_read_string_index(child, "nvidia,pins", 0, + &name); + if (ret < 0) { + log_debug("%s: could not parse property nvidia,pins\n", __func__); + return ret; + } + + ret = dev_read_string_count(child, "nvidia,pins"); + if (ret < 0) { + log_debug("%s: could not count nvidia,pins\n", __func__); + return ret; + } + + if (!strncmp(name, "drive_", 6)) + /* Drive node is detected */ + tegra_pinctrl_set_drive(child, ret); + else + /* Pin node is detected */ + tegra_pinctrl_set_pin(child, ret); + } + + return 0; +} + +static int tegra_pinctrl_get_pins_count(struct udevice *dev) +{ + return PMUX_PINGRP_COUNT; +} + +static const char *tegra_pinctrl_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + return tegra_pinctrl_to_pingrp[selector]; +} + +static int tegra_pinctrl_get_groups_count(struct udevice *dev) +{ + return PMUX_DRVGRP_COUNT; +} + +static const char *tegra_pinctrl_get_group_name(struct udevice *dev, + unsigned int selector) +{ + return tegra_pinctrl_to_drvgrp[selector]; +} + +static int tegra_pinctrl_get_functions_count(struct udevice *dev) +{ + return PMUX_FUNC_COUNT; +} + +static const char *tegra_pinctrl_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return tegra_pinctrl_to_func[selector]; +} + +const struct pinctrl_ops tegra_pinctrl_ops = { + .get_pins_count = tegra_pinctrl_get_pins_count, + .get_pin_name = tegra_pinctrl_get_pin_name, + .get_groups_count = tegra_pinctrl_get_groups_count, + .get_group_name = tegra_pinctrl_get_group_name, + .get_functions_count = tegra_pinctrl_get_functions_count, + .get_function_name = tegra_pinctrl_get_function_name, + .set_state = tegra_pinctrl_set_state, +}; + +static int tegra_pinctrl_bind(struct udevice *dev) +{ + /* + * Make sure that the pinctrl driver gets probed after binding + * to provide initial configuration and assure that further + * probed devices are working correctly. + */ + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); + + return 0; +} + +static const struct udevice_id tegra_pinctrl_ids[] = { + { .compatible = "nvidia,tegra30-pinmux" }, + { .compatible = "nvidia,tegra114-pinmux" }, + { }, +}; + +U_BOOT_DRIVER(tegra_pinctrl) = { + .name = "tegra_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = tegra_pinctrl_ids, + .bind = tegra_pinctrl_bind, + .ops = &tegra_pinctrl_ops, +}; diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c new file mode 100644 index 00000000000..d5171b8be23 --- /dev/null +++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/pinctrl.h> +#include <stdlib.h> + +#include <asm/arch/pinmux.h> + +static void tegra_pinctrl_set_pin(struct udevice *config) +{ + int i, count, pin_id, ret; + int pull, tristate; + const char **pins; + + ret = dev_read_u32(config, "nvidia,pull", &pull); + if (ret) + pull = ret; + + ret = dev_read_u32(config, "nvidia,tristate", &tristate); + if (ret) + tristate = ret; + + count = dev_read_string_list(config, "nvidia,pins", &pins); + if (count < 0) { + log_debug("%s: could not parse property nvidia,pins\n", __func__); + return; + } + + for (i = 0; i < count; i++) { + for (pin_id = 0; pin_id < PMUX_PINGRP_COUNT; pin_id++) + if (tegra_pinctrl_to_pingrp[pin_id]) + if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id])) + break; + + if (pull >= 0) + pinmux_set_pullupdown(pin_id, pull); + + if (tristate >= 0) { + if (!tristate) + pinmux_tristate_disable(pin_id); + else + pinmux_tristate_enable(pin_id); + } + } + + free(pins); +} + +static void tegra_pinctrl_set_func(struct udevice *config) +{ + int i, count, func_id, pin_id; + const char *function; + const char **pins; + + function = dev_read_string(config, "nvidia,function"); + if (function) + for (i = 0; i < PMUX_FUNC_COUNT; i++) + if (tegra_pinctrl_to_func[i]) + if (!strcmp(function, tegra_pinctrl_to_func[i])) + break; + + func_id = i; + + count = dev_read_string_list(config, "nvidia,pins", &pins); + if (count < 0) { + log_debug("%s: could not parse property nvidia,pins\n", __func__); + return; + } + + for (i = 0; i < count; i++) { + for (pin_id = 0; pin_id < PMUX_PINGRP_COUNT; pin_id++) + if (tegra_pinctrl_to_pingrp[pin_id]) + if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id])) + break; + + debug("%s(%d) muxed to %s(%d)\n", pins[i], pin_id, function, func_id); + + pinmux_set_func(pin_id, func_id); + } + + free(pins); +} + +static int tegra_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + struct udevice *child; + + device_foreach_child(child, config) { + /* + * Tegra20 pinmux is set differently then any other + * Tegra SOC. Nodes are arranged by function muxing, + * then actual pins setup (with node name prefix + * conf_*) and then drive setup. + */ + if (!strncmp(child->name, "conf_", 5)) + tegra_pinctrl_set_pin(child); + else if (!strncmp(child->name, "drive_", 6)) + debug("%s: drive configuration is not supported\n", __func__); + else + tegra_pinctrl_set_func(child); + } + + return 0; +} + +static int tegra_pinctrl_get_pins_count(struct udevice *dev) +{ + return PMUX_PINGRP_COUNT; +} + +static const char *tegra_pinctrl_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + return tegra_pinctrl_to_pingrp[selector]; +} + +static int tegra_pinctrl_get_groups_count(struct udevice *dev) +{ + return PMUX_DRVGRP_COUNT; +} + +static const char *tegra_pinctrl_get_group_name(struct udevice *dev, + unsigned int selector) +{ + return tegra_pinctrl_to_drvgrp[selector]; +} + +static int tegra_pinctrl_get_functions_count(struct udevice *dev) +{ + return PMUX_FUNC_COUNT; +} + +static const char *tegra_pinctrl_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return tegra_pinctrl_to_func[selector]; +} + +const struct pinctrl_ops tegra_pinctrl_ops = { + .get_pins_count = tegra_pinctrl_get_pins_count, + .get_pin_name = tegra_pinctrl_get_pin_name, + .get_groups_count = tegra_pinctrl_get_groups_count, + .get_group_name = tegra_pinctrl_get_group_name, + .get_functions_count = tegra_pinctrl_get_functions_count, + .get_function_name = tegra_pinctrl_get_function_name, + .set_state = tegra_pinctrl_set_state, +}; + +static int tegra_pinctrl_bind(struct udevice *dev) +{ + /* + * Make sure that the pinctrl driver gets probed after binding + * to provide initial configuration and assure that further + * probed devices are working correctly. + */ + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); + + return 0; +} + +static const struct udevice_id tegra_pinctrl_ids[] = { + { .compatible = "nvidia,tegra20-pinmux" }, + { }, +}; + +U_BOOT_DRIVER(tegra_pinctrl) = { + .name = "tegra_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = tegra_pinctrl_ids, + .bind = tegra_pinctrl_bind, + .ops = &tegra_pinctrl_ops, +}; diff --git a/arch/arm/mach-tegra/pinmux-common.c b/drivers/pinctrl/tegra/pinmux-common.c index 16b03bfe7b0..16b03bfe7b0 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/drivers/pinctrl/tegra/pinmux-common.c diff --git a/arch/arm/mach-tegra/tegra114/pinmux.c b/drivers/pinctrl/tegra/pinmux-tegra114.c index 11796602c54..11796602c54 100644 --- a/arch/arm/mach-tegra/tegra114/pinmux.c +++ b/drivers/pinctrl/tegra/pinmux-tegra114.c diff --git a/arch/arm/mach-tegra/tegra124/pinmux.c b/drivers/pinctrl/tegra/pinmux-tegra124.c index 261ce64b205..261ce64b205 100644 --- a/arch/arm/mach-tegra/tegra124/pinmux.c +++ b/drivers/pinctrl/tegra/pinmux-tegra124.c diff --git a/arch/arm/mach-tegra/tegra20/pinmux.c b/drivers/pinctrl/tegra/pinmux-tegra20.c index 0af39e74c53..0af39e74c53 100644 --- a/arch/arm/mach-tegra/tegra20/pinmux.c +++ b/drivers/pinctrl/tegra/pinmux-tegra20.c diff --git a/drivers/pinctrl/tegra/pinmux-tegra210.c b/drivers/pinctrl/tegra/pinmux-tegra210.c new file mode 100644 index 00000000000..27abec274a3 --- /dev/null +++ b/drivers/pinctrl/tegra/pinmux-tegra210.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + */ + +#include <asm/io.h> +#include <asm/arch/pinmux.h> + +#define PIN(pin, f0, f1, f2, f3) \ + { \ + .funcs = { \ + PMUX_FUNC_##f0, \ + PMUX_FUNC_##f1, \ + PMUX_FUNC_##f2, \ + PMUX_FUNC_##f3, \ + }, \ + } + +#define PIN_RESERVED {} + +static const struct pmux_pingrp_desc tegra210_pingroups[] = { + /* pin, f0, f1, f2, f3 */ + /* Offset 0x3000 */ + PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3), + PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3), + PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3), + PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3), + PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3), + PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3), + PIN_RESERVED, + PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN_RESERVED, + PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3), + PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3), + PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3), + PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3), + PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3), + PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3), + PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3), + PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3), + PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3), + PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3), + PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3), + PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3), + PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3), + PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3), + PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3), + PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3), + PIN_RESERVED, + PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3), + PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3), + PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3), + PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3), + PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3), + PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3), + PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3), + PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3), + PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3), + PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3), + PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3), + PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3), + PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3), + PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3), + PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3), + PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3), + PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3), + PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3), + PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3), + PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3), + PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART), + PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART), + PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART), + PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART), + PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3), + PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3), + PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3), + PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3), + PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3), + PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3), + PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3), + PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3), + PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3), + PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3), + PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3), + PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3), + PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3), + PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3), + PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3), + PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3), + PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3), + PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3), + PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3), + PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3), + PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3), + PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3), + PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3), + PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3), + PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3), + PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3), + PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3), + PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3), + PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3), + PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3), + PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3), + PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3), + PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3), + PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3), + PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3), + PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3), + PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3), + PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3), + PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3), + PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3), + PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3), + PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3), + PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3), + PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3), + PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3), + PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3), + PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3), + PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3), + PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3), + PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3), + PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3), + PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3), + PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3), + PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3), + PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1), + PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3), + PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(PA6, SATA, RSVD1, RSVD2, RSVD3), + PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3), + PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3), + PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3), + PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3), + PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3), + PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3), + PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3), + PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3), + PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3), + PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3), + PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(PL1, SOC, RSVD1, RSVD2, RSVD3), + PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3), + PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3), + PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3), + PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3), + PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3), +}; +const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups; diff --git a/arch/arm/mach-tegra/tegra30/pinmux.c b/drivers/pinctrl/tegra/pinmux-tegra30.c index d11b2aa572d..d11b2aa572d 100644 --- a/arch/arm/mach-tegra/tegra30/pinmux.c +++ b/drivers/pinctrl/tegra/pinmux-tegra30.c diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 2395720c99c..33b8bc1214d 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -56,7 +56,6 @@ choice depends on ARCH_SUNXI default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40 - default AXP305_POWER if MACH_SUN50I_H616 default AXP818_POWER if MACH_SUN8I_A83T default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_V3S diff --git a/drivers/power/pmic/max77663.c b/drivers/power/pmic/max77663.c index 68c3cbbc646..cf08b6a7e1d 100644 --- a/drivers/power/pmic/max77663.c +++ b/drivers/power/pmic/max77663.c @@ -55,6 +55,15 @@ static int max77663_bind(struct udevice *dev) } } + if (IS_ENABLED(CONFIG_MAX77663_GPIO)) { + ret = device_bind_driver(dev, MAX77663_GPIO_DRIVER, + "gpio", NULL); + if (ret) { + log_err("cannot bind GPIOs (ret = %d)\n", ret); + return ret; + } + } + regulators_node = dev_read_subnode(dev, "regulators"); if (!ofnode_valid(regulators_node)) { log_err("%s regulators subnode not found!\n", dev->name); diff --git a/drivers/power/pmic/palmas.c b/drivers/power/pmic/palmas.c index 32f2a938b28..e340a32279f 100644 --- a/drivers/power/pmic/palmas.c +++ b/drivers/power/pmic/palmas.c @@ -46,7 +46,7 @@ static int palmas_read(struct udevice *dev, uint reg, uint8_t *buff, int len) static int palmas_bind(struct udevice *dev) { ofnode pmic_node = ofnode_null(), regulators_node; - ofnode subnode; + ofnode subnode, gpio_node; int children, ret; if (IS_ENABLED(CONFIG_SYSRESET_PALMAS)) { @@ -58,6 +58,14 @@ static int palmas_bind(struct udevice *dev) } } + gpio_node = ofnode_find_subnode(dev_ofnode(dev), "gpio"); + if (ofnode_valid(gpio_node)) { + ret = device_bind_driver_to_node(dev, PALMAS_GPIO_DRIVER, + "gpio", gpio_node, NULL); + if (ret) + log_err("cannot bind GPIOs (ret = %d)\n", ret); + } + dev_for_each_subnode(subnode, dev) { const char *name; char *temp; diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c index 576de4bb26e..1c6515f9ab7 100644 --- a/drivers/remoteproc/ti_k3_dsp_rproc.c +++ b/drivers/remoteproc/ti_k3_dsp_rproc.c @@ -56,6 +56,7 @@ struct k3_dsp_boot_data { * @data: Pointer to DSP specific boot data structure * @mem: Array of available memories * @num_mem: Number of available memories + * @in_use: flag to tell if the core is already in use. */ struct k3_dsp_privdata { struct reset_ctl dsp_rst; @@ -63,6 +64,7 @@ struct k3_dsp_privdata { struct k3_dsp_boot_data *data; struct k3_dsp_mem *mem; int num_mems; + bool in_use; }; /* @@ -128,6 +130,13 @@ static int k3_dsp_load(struct udevice *dev, ulong addr, ulong size) u32 boot_vector; int ret; + if (dsp->in_use) { + dev_err(dev, + "Invalid op: Trying to load/start on already running core %d\n", + dsp->tsp.proc_id); + return -EINVAL; + } + dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size); ret = ti_sci_proc_request(&dsp->tsp); if (ret) @@ -195,6 +204,7 @@ static int k3_dsp_start(struct udevice *dev) ti_sci_proc_power_domain_off(&dsp->tsp); } + dsp->in_use = true; proc_release: ti_sci_proc_release(&dsp->tsp); @@ -207,6 +217,7 @@ static int k3_dsp_stop(struct udevice *dev) dev_dbg(dev, "%s\n", __func__); + dsp->in_use = false; ti_sci_proc_request(&dsp->tsp); reset_assert(&dsp->dsp_rst); ti_sci_proc_power_domain_off(&dsp->tsp); diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index a24bb430cbb..19d9a5ae23c 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -295,7 +295,7 @@ static int bcm63xx_hsspi_xfer_dummy_cs(struct udevice *dev, unsigned int data_by /* transfer loop */ while (data_bytes > 0) { - size_t curr_step = min(step_size, data_bytes); + size_t curr_step = min(step_size, (size_t)data_bytes); int ret; /* copy tx data */ diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 2efd626852e..dfc74c882d2 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -39,6 +39,11 @@ __weak int cadence_qspi_versal_flash_reset(struct udevice *dev) return 0; } +__weak ofnode cadence_qspi_get_subnode(struct udevice *dev) +{ + return dev_read_first_subnode(dev); +} + static int cadence_spi_write_speed(struct udevice *bus, uint hz) { struct cadence_spi_priv *priv = dev_get_priv(bus); @@ -400,7 +405,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus) plat->is_dma = dev_read_bool(bus, "cdns,is-dma"); /* All other parameters are embedded in the child node */ - subnode = dev_read_first_subnode(bus); + subnode = cadence_qspi_get_subnode(bus); if (!ofnode_valid(subnode)) { printf("Error: subnode with SPI flash config missing!\n"); return -ENODEV; diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 1c59d1a9d9a..12825f8911c 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -304,6 +304,7 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv); int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg); int cadence_qspi_versal_flash_reset(struct udevice *dev); +ofnode cadence_qspi_get_subnode(struct udevice *dev); void cadence_qspi_apb_enable_linear_mode(bool enable); #endif /* __CADENCE_QSPI_H__ */ diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 9ce2c0f254f..d033184aa46 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -171,8 +171,7 @@ static unsigned int cadence_qspi_wait_idle(void *reg_base) } /* Timeout, still in busy mode. */ - printf("QSPI: QSPI is still busy after poll for %d times.\n", - CQSPI_REG_RETRY); + printf("QSPI: QSPI is still busy after poll for %d ms.\n", timeout); return 0; } diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index 89907cbbb02..9b3d5a94817 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -14,7 +14,6 @@ #include <common.h> #include <dm.h> #include <errno.h> -#include <common.h> #include <log.h> #include <spi.h> #include <malloc.h> diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c index 9a9b697e91f..47f845cffe3 100644 --- a/drivers/tee/optee/core.c +++ b/drivers/tee/optee/core.c @@ -139,6 +139,11 @@ static int enum_services(struct udevice *dev, struct tee_shm **shm, size_t *coun if (ret) return ret; + if (!shm_size) { + *count = 0; + return 0; + } + ret = tee_shm_alloc(dev, shm_size, 0, shm); if (ret) { dev_err(dev, "Failed to allocated shared memory: %d\n", ret); @@ -185,14 +190,15 @@ static int bind_service_drivers(struct udevice *dev) ret = enum_services(dev, &service_list, &service_count, tee_sess, PTA_CMD_GET_DEVICES); - if (!ret) + if (!ret && service_count) ret = bind_service_list(dev, service_list, service_count); tee_shm_free(service_list); + service_list = NULL; ret2 = enum_services(dev, &service_list, &service_count, tee_sess, PTA_CMD_GET_DEVICES_SUPP); - if (!ret2) + if (!ret2 && service_count) ret2 = bind_service_list(dev, service_list, service_count); tee_shm_free(service_list); @@ -841,7 +847,7 @@ static int optee_probe(struct udevice *dev) if (IS_ENABLED(CONFIG_OPTEE_SERVICE_DISCOVERY)) { ret = bind_service_drivers(dev); if (ret) - return ret; + dev_warn(dev, "optee service enumeration failed: %d\n", ret); } else if (IS_ENABLED(CONFIG_RNG_OPTEE)) { /* * Discovery of TAs on the TEE bus is not supported in U-Boot: diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c index b171232c484..6cd25251f94 100644 --- a/drivers/timer/dw-apb-timer.c +++ b/drivers/timer/dw-apb-timer.c @@ -13,7 +13,6 @@ #include <reset.h> #include <timer.h> #include <dm/device_compat.h> -#include <linux/kconfig.h> #include <asm/io.h> #include <asm/arch/timer.h> diff --git a/drivers/timer/starfive-timer.c b/drivers/timer/starfive-timer.c index 816402fdbf2..6ac7d7f1d0e 100644 --- a/drivers/timer/starfive-timer.c +++ b/drivers/timer/starfive-timer.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2022 StarFive, Inc. All rights reserved. - * Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com> + * Author: Kuan Lim Lee <kuanlim.lee@starfivetech.com> */ #include <common.h> @@ -48,8 +48,8 @@ static int starfive_probe(struct udevice *dev) int ret; priv->base = dev_read_addr_ptr(dev); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + if (!priv->base) + return -EINVAL; timer_channel = dev_read_u32_default(dev, "channel", 0); priv->base = priv->base + (0x40 * timer_channel); @@ -64,14 +64,16 @@ static int starfive_probe(struct udevice *dev) return ret; uc_priv->clock_rate = clk_get_rate(&clk); - /* Initiate timer, channel 0 */ - /* Unmask Interrupt Mask */ + /* + * Initiate timer, channel 0 + * Unmask Interrupt Mask + */ writel(0, priv->base + STF_TIMER_INT_MASK); /* Single run mode Setting */ if (dev_read_bool(dev, "single-run")) writel(1, priv->base + STF_TIMER_CTL); /* Set Reload value */ - priv->timer_size = dev_read_u32_default(dev, "timer-size", 0xffffffff); + priv->timer_size = dev_read_u32_default(dev, "timer-size", -1U); writel(priv->timer_size, priv->base + STF_TIMER_LOAD); /* Enable to start timer */ writel(1, priv->base + STF_TIMER_ENABLE); @@ -85,7 +87,7 @@ static const struct udevice_id starfive_ids[] = { }; U_BOOT_DRIVER(jh8100_starfive_timer) = { - .name = "jh8100_starfive_timer", + .name = "starfive_timer", .id = UCLASS_TIMER, .of_match = starfive_ids, .probe = starfive_probe, diff --git a/drivers/usb/gadget/bcm_udc_otg.h b/drivers/usb/gadget/bcm_udc_otg.h index 24cc936c6b4..48370f37d8a 100644 --- a/drivers/usb/gadget/bcm_udc_otg.h +++ b/drivers/usb/gadget/bcm_udc_otg.h @@ -6,8 +6,6 @@ #ifndef __BCM_UDC_OTG_H #define __BCM_UDC_OTG_H -#include <common.h> - static inline void wfld_set(uintptr_t addr, uint32_t fld_val, uint32_t fld_mask) { writel(((readl(addr) & ~(fld_mask)) | (fld_val)), (addr)); diff --git a/drivers/video/exynos/exynos_dp.c b/drivers/video/exynos/exynos_dp.c index a532d5ae1ab..59838da6c92 100644 --- a/drivers/video/exynos/exynos_dp.c +++ b/drivers/video/exynos/exynos_dp.c @@ -7,7 +7,6 @@ #include <common.h> #include <dm.h> -#include <common.h> #include <display.h> #include <fdtdec.h> #include <log.h> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 07fc4940e91..569726119ca 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -344,6 +344,13 @@ config WDT_STM32MP Enable the STM32 watchdog (IWDG) driver. Enable support to configure STM32's on-SoC watchdog. +config WDT_STARFIVE + bool "StarFive watchdog timer support" + depends on WDT + imply WATCHDOG + help + Enable support for the watchdog timer of StarFive JH7110 SoC. + config WDT_SUNXI bool "Allwinner sunxi watchdog timer support" depends on WDT && ARCH_SUNXI diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index eef786f5e74..5520d3d9ae8 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o obj-$(CONFIG_WDT_SP805) += sp805_wdt.o +obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o diff --git a/drivers/watchdog/starfive_wdt.c b/drivers/watchdog/starfive_wdt.c new file mode 100644 index 00000000000..ee9ec4cdc3a --- /dev/null +++ b/drivers/watchdog/starfive_wdt.c @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Starfive Watchdog driver + * + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#include <clk.h> +#include <dm.h> +#include <reset.h> +#include <wdt.h> +#include <linux/iopoll.h> + +/* JH7110 Watchdog register define */ +#define STARFIVE_WDT_JH7110_LOAD 0x000 +#define STARFIVE_WDT_JH7110_VALUE 0x004 +#define STARFIVE_WDT_JH7110_CONTROL 0x008 /* + * [0]: reset enable; + * [1]: interrupt enable && watchdog enable + * [31:2]: reserved. + */ +#define STARFIVE_WDT_JH7110_INTCLR 0x00c /* clear intterupt and reload the counter */ +#define STARFIVE_WDT_JH7110_IMS 0x014 +#define STARFIVE_WDT_JH7110_LOCK 0xc00 /* write 0x1ACCE551 to unlock */ + +/* WDOGCONTROL */ +#define STARFIVE_WDT_ENABLE 0x1 +#define STARFIVE_WDT_EN_SHIFT 0 +#define STARFIVE_WDT_RESET_EN 0x1 +#define STARFIVE_WDT_JH7110_RST_EN_SHIFT 1 + +/* WDOGLOCK */ +#define STARFIVE_WDT_JH7110_UNLOCK_KEY 0x1acce551 + +/* WDOGINTCLR */ +#define STARFIVE_WDT_INTCLR 0x1 +#define STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT 1 /* Watchdog can clear interrupt when 0 */ + +#define STARFIVE_WDT_MAXCNT 0xffffffff +#define STARFIVE_WDT_DEFAULT_TIME (15) +#define STARFIVE_WDT_DELAY_US 0 +#define STARFIVE_WDT_TIMEOUT_US 10000 + +/* module parameter */ +#define STARFIVE_WDT_EARLY_ENA 0 + +struct starfive_wdt_variant { + unsigned int control; /* Watchdog Control Resgister for reset enable */ + unsigned int load; /* Watchdog Load register */ + unsigned int reload; /* Watchdog Reload Control register */ + unsigned int enable; /* Watchdog Enable Register */ + unsigned int value; /* Watchdog Counter Value Register */ + unsigned int int_clr; /* Watchdog Interrupt Clear Register */ + unsigned int unlock; /* Watchdog Lock Register */ + unsigned int int_status; /* Watchdog Interrupt Status Register */ + + u32 unlock_key; + char enrst_shift; + char en_shift; + bool intclr_check; /* whether need to check it before clearing interrupt */ + char intclr_ava_shift; + bool double_timeout; /* The watchdog need twice timeout to reboot */ +}; + +struct starfive_wdt_priv { + void __iomem *base; + struct clk *core_clk; + struct clk *apb_clk; + struct reset_ctl_bulk *rst; + const struct starfive_wdt_variant *variant; + unsigned long freq; + u32 count; /* count of timeout */ + u32 reload; /* restore the count */ +}; + +/* Register layout and configuration for the JH7110 */ +static const struct starfive_wdt_variant starfive_wdt_jh7110_variant = { + .control = STARFIVE_WDT_JH7110_CONTROL, + .load = STARFIVE_WDT_JH7110_LOAD, + .enable = STARFIVE_WDT_JH7110_CONTROL, + .value = STARFIVE_WDT_JH7110_VALUE, + .int_clr = STARFIVE_WDT_JH7110_INTCLR, + .unlock = STARFIVE_WDT_JH7110_LOCK, + .unlock_key = STARFIVE_WDT_JH7110_UNLOCK_KEY, + .int_status = STARFIVE_WDT_JH7110_IMS, + .enrst_shift = STARFIVE_WDT_JH7110_RST_EN_SHIFT, + .en_shift = STARFIVE_WDT_EN_SHIFT, + .intclr_check = false, + .double_timeout = true, +}; + +static int starfive_wdt_enable_clock(struct starfive_wdt_priv *wdt) +{ + int ret; + + ret = clk_enable(wdt->apb_clk); + if (ret) + return ret; + + ret = clk_enable(wdt->core_clk); + if (ret) { + clk_disable(wdt->apb_clk); + return ret; + } + + return 0; +} + +static void starfive_wdt_disable_clock(struct starfive_wdt_priv *wdt) +{ + clk_disable(wdt->core_clk); + clk_disable(wdt->apb_clk); +} + +/* Write unlock-key to unlock. Write other value to lock. */ +static void starfive_wdt_unlock(struct starfive_wdt_priv *wdt) +{ + writel(wdt->variant->unlock_key, wdt->base + wdt->variant->unlock); +} + +static void starfive_wdt_lock(struct starfive_wdt_priv *wdt) +{ + writel(~wdt->variant->unlock_key, wdt->base + wdt->variant->unlock); +} + +/* enable watchdog interrupt to reset/reboot */ +static void starfive_wdt_enable_reset(struct starfive_wdt_priv *wdt) +{ + u32 val; + + val = readl(wdt->base + wdt->variant->control); + val |= STARFIVE_WDT_RESET_EN << wdt->variant->enrst_shift; + writel(val, wdt->base + wdt->variant->control); +} + +/* waiting interrupt can be free to clear */ +static int starfive_wdt_wait_int_free(struct starfive_wdt_priv *wdt) +{ + u32 value; + + return readl_poll_timeout(wdt->base + wdt->variant->int_clr, value, + !(value & BIT(wdt->variant->intclr_ava_shift)), + STARFIVE_WDT_TIMEOUT_US); +} + +/* clear interrupt signal before initialization or reload */ +static int starfive_wdt_int_clr(struct starfive_wdt_priv *wdt) +{ + int ret; + + if (wdt->variant->intclr_check) { + ret = starfive_wdt_wait_int_free(wdt); + if (ret) + return ret; + } + writel(STARFIVE_WDT_INTCLR, wdt->base + wdt->variant->int_clr); + + return 0; +} + +static inline void starfive_wdt_set_count(struct starfive_wdt_priv *wdt, + u32 val) +{ + writel(val, wdt->base + wdt->variant->load); +} + +/* enable watchdog */ +static inline void starfive_wdt_enable(struct starfive_wdt_priv *wdt) +{ + u32 val; + + val = readl(wdt->base + wdt->variant->enable); + val |= STARFIVE_WDT_ENABLE << wdt->variant->en_shift; + writel(val, wdt->base + wdt->variant->enable); +} + +/* disable watchdog */ +static inline void starfive_wdt_disable(struct starfive_wdt_priv *wdt) +{ + u32 val; + + val = readl(wdt->base + wdt->variant->enable); + val &= ~(STARFIVE_WDT_ENABLE << wdt->variant->en_shift); + writel(val, wdt->base + wdt->variant->enable); +} + +static inline void starfive_wdt_set_reload_count(struct starfive_wdt_priv *wdt, + u32 count) +{ + starfive_wdt_set_count(wdt, count); + + /* 7100 need set any value to reload register and could reload value to counter */ + if (wdt->variant->reload) + writel(0x1, wdt->base + wdt->variant->reload); +} + +static int starfive_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + int ret; + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + + starfive_wdt_unlock(wdt); + /* disable watchdog, to be safe */ + starfive_wdt_disable(wdt); + + starfive_wdt_enable_reset(wdt); + ret = starfive_wdt_int_clr(wdt); + if (ret) + goto exit; + + wdt->count = (timeout_ms / 1000) * wdt->freq; + if (wdt->variant->double_timeout) + wdt->count /= 2; + + starfive_wdt_set_count(wdt, wdt->count); + starfive_wdt_enable(wdt); + +exit: + starfive_wdt_lock(wdt); + return ret; +} + +static int starfive_wdt_stop(struct udevice *dev) +{ + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + + starfive_wdt_unlock(wdt); + starfive_wdt_disable(wdt); + starfive_wdt_lock(wdt); + + return 0; +} + +static int starfive_wdt_reset(struct udevice *dev) +{ + int ret; + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + + starfive_wdt_unlock(wdt); + ret = starfive_wdt_int_clr(wdt); + if (ret) + goto exit; + + starfive_wdt_set_reload_count(wdt, wdt->count); + +exit: + starfive_wdt_lock(wdt); + + return ret; +} + +static const struct wdt_ops starfive_wdt_ops = { + .start = starfive_wdt_start, + .stop = starfive_wdt_stop, + .reset = starfive_wdt_reset, +}; + +static int starfive_wdt_probe(struct udevice *dev) +{ + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + int ret; + + ret = starfive_wdt_enable_clock(wdt); + if (ret) + return ret; + + ret = reset_deassert_bulk(wdt->rst); + if (ret) + goto err_reset; + + wdt->variant = (const struct starfive_wdt_variant *)dev_get_driver_data(dev); + + wdt->freq = clk_get_rate(wdt->core_clk); + if (!wdt->freq) { + ret = -EINVAL; + goto err_get_freq; + } + + return 0; + +err_get_freq: + reset_assert_bulk(wdt->rst); +err_reset: + starfive_wdt_disable_clock(wdt); + + return ret; +} + +static int starfive_wdt_of_to_plat(struct udevice *dev) +{ + struct starfive_wdt_priv *wdt = dev_get_priv(dev); + + wdt->base = (void *)dev_read_addr(dev); + if (!wdt->base) + return -ENODEV; + + wdt->apb_clk = devm_clk_get(dev, "apb"); + if (IS_ERR(wdt->apb_clk)) + return -ENODEV; + + wdt->core_clk = devm_clk_get(dev, "core"); + if (IS_ERR(wdt->core_clk)) + return -ENODEV; + + wdt->rst = devm_reset_bulk_get(dev); + if (IS_ERR(wdt->rst)) + return -ENODEV; + + return 0; +} + +static const struct udevice_id starfive_wdt_ids[] = { + { + .compatible = "starfive,jh7110-wdt", + .data = (ulong)&starfive_wdt_jh7110_variant + }, { + /* sentinel */ + } +}; + +U_BOOT_DRIVER(starfive_wdt) = { + .name = "starfive_wdt", + .id = UCLASS_WDT, + .of_match = starfive_wdt_ids, + .priv_auto = sizeof(struct starfive_wdt_priv), + .probe = starfive_wdt_probe, + .of_to_plat = starfive_wdt_of_to_plat, + .ops = &starfive_wdt_ops, +}; diff --git a/env/embedded.c b/env/embedded.c index 7cbe54c56e0..5b488ef818e 100644 --- a/env/embedded.c +++ b/env/embedded.c @@ -4,7 +4,9 @@ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. */ +#ifdef USE_HOSTCC #include <linux/kconfig.h> +#endif #ifndef __ASSEMBLY__ #define __ASSEMBLY__ /* Dirty trick to get only #defines */ diff --git a/fs/btrfs/ctree.h b/fs/btrfs/ctree.h index ffd095ffdd2..59439552a45 100644 --- a/fs/btrfs/ctree.h +++ b/fs/btrfs/ctree.h @@ -9,7 +9,6 @@ #ifndef __BTRFS_CTREE_H__ #define __BTRFS_CTREE_H__ -#include <common.h> #include <compiler.h> #include <linux/rbtree.h> #include <linux/bug.h> @@ -256,7 +256,7 @@ static struct fstype_info fstypes[] = { .ln = fs_ln_unsupported, }, #endif -#ifdef CONFIG_SEMIHOSTING +#if CONFIG_IS_ENABLED(SEMIHOSTING) { .fstype = FS_TYPE_SEMIHOSTING, .name = "semihosting", diff --git a/fs/yaffs2/ydirectenv.h b/fs/yaffs2/ydirectenv.h index d274f22e84d..790f8512f74 100644 --- a/fs/yaffs2/ydirectenv.h +++ b/fs/yaffs2/ydirectenv.h @@ -20,7 +20,6 @@ #ifndef __YDIRECTENV_H__ #define __YDIRECTENV_H__ -#include <common.h> #include <malloc.h> #include <linux/compat.h> diff --git a/include/atmel_lcd.h b/include/atmel_lcd.h index 66436b9b277..a115d6c1701 100644 --- a/include/atmel_lcd.h +++ b/include/atmel_lcd.h @@ -9,6 +9,8 @@ #ifndef _ATMEL_LCD_H_ #define _ATMEL_LCD_H_ +#include <linux/types.h> + /** * struct atmel_lcd_plat - platform data for Atmel LCDs with driver model * diff --git a/include/bootflow.h b/include/bootflow.h index fede8f22a2b..42112874f64 100644 --- a/include/bootflow.h +++ b/include/bootflow.h @@ -45,10 +45,12 @@ enum bootflow_state_t { * CONFIG_OF_HAS_PRIOR_STAGE is enabled * @BOOTFLOWF_STATIC_BUF: Indicates that @bflow->buf is statically set, rather * than being allocated by malloc(). + * @BOOTFLOWF_USE_BUILTIN_FDT : Indicates that current bootflow uses built-in FDT */ enum bootflow_flags_t { BOOTFLOWF_USE_PRIOR_FDT = 1 << 0, BOOTFLOWF_STATIC_BUF = 1 << 1, + BOOTFLOWF_USE_BUILTIN_FDT = 1 << 2, }; /** diff --git a/include/bootstage.h b/include/bootstage.h index 59a76d0f0c4..f4e77b09d74 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -12,7 +12,9 @@ #define _BOOTSTAGE_H #include <linux/types.h> +#ifdef USE_HOSTCC #include <linux/kconfig.h> +#endif /* Flags for each bootstage record */ enum bootstage_flags { diff --git a/include/clk-uclass.h b/include/clk-uclass.h index a22f1a5d848..cd62848bece 100644 --- a/include/clk-uclass.h +++ b/include/clk-uclass.h @@ -25,6 +25,7 @@ struct ofnode_phandle_args; * @set_parent: Set current clock parent * @enable: Enable a clock. * @disable: Disable a clock. + * @dump: Print clock information. * * The individual methods are described more fully below. */ @@ -39,6 +40,9 @@ struct clk_ops { int (*set_parent)(struct clk *clk, struct clk *parent); int (*enable)(struct clk *clk); int (*disable)(struct clk *clk); +#if IS_ENABLED(CONFIG_CMD_CLK) + void (*dump)(struct udevice *dev); +#endif }; #if 0 /* For documentation only */ @@ -135,6 +139,15 @@ int enable(struct clk *clk); * Return: zero on success, or -ve error code. */ int disable(struct clk *clk); + +/** + * dump() - Print clock information. + * @dev: The clock device to dump. + * + * If present, this function is called by "clk dump" command for each + * bound device. + */ +void dump(struct udevice *dev); #endif #endif diff --git a/include/clk.h b/include/clk.h index 249c0e0ab42..3d6394477be 100644 --- a/include/clk.h +++ b/include/clk.h @@ -676,8 +676,6 @@ static inline bool clk_valid(struct clk *clk) return clk && !!clk->dev; } -int soc_clk_dump(void); - #endif #define clk_prepare_enable(clk) clk_enable(clk) diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 4aa876a9f79..81c76ef52a7 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -9,8 +9,6 @@ #ifndef __AT91_SAMA5_COMMON_H #define __AT91_SAMA5_COMMON_H -#include <linux/kconfig.h> - /* ARM asynchronous clock */ #define CFG_SYS_AT91_SLOW_CLOCK 32768 #define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 03f8ed14787..7a9f4afe7d1 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -101,7 +101,6 @@ UBI_BOOTCMD #elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) #define MODULE_EXTRA_ENV_SETTINGS \ - "variant=-emmc\0" \ EMMC_ANDROID_BOOTCMD #endif diff --git a/include/configs/mt8365.h b/include/configs/mt8365.h new file mode 100644 index 00000000000..e8aacf8c5df --- /dev/null +++ b/include/configs/mt8365.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for MT8365 based boards + * + * Copyright (C) 2023 BayLibre, SAS + * Author: Julien Masson <jmasson@baylibre.com> + */ + +#ifndef __MT8365_H +#define __MT8365_H + +#endif diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index de8bfc1123b..27e0912665b 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -13,41 +13,4 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -/* Environment options */ - -#define BOOT_TARGET_DEVICES(func) \ - func(NVME, nvme, 0) \ - func(NVME, nvme, 1) \ - func(USB, usb, 0) \ - func(MMC, mmc, 0) \ - func(SCSI, scsi, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include <config_distro_bootcmd.h> - -#define TYPE_GUID_LOADER1 "5B193300-FC78-40CD-8002-E86C45580B47" -#define TYPE_GUID_LOADER2 "2E54B353-1271-4842-806F-E436D6AF6985" -#define TYPE_GUID_SYSTEM "0FC63DAF-8483-4772-8E79-3D69D8477DE4" - -#define PARTS_DEFAULT \ - "name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \ - "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \ - "name=system,size=-,bootable,type=${type_guid_gpt_system};" - -#define CFG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x80200000\0" \ - "kernel_comp_addr_r=0x88000000\0" \ - "kernel_comp_size=0x4000000\0" \ - "fdt_addr_r=0x8c000000\0" \ - "scriptaddr=0x8c100000\0" \ - "pxefile_addr_r=0x8c200000\0" \ - "ramdisk_addr_r=0x8c300000\0" \ - "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \ - "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ - "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ - "partitions=" PARTS_DEFAULT "\0" \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - BOOTENV - #endif /* __SIFIVE_UNMATCHED_H */ diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index ff43113f243..29c74470c71 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -40,6 +40,7 @@ "kernel_comp_addr_r=0x88000000\0" \ "kernel_comp_size=0x4000000\0" \ "fdt_addr_r=0x46000000\0" \ + "fdtoverlay_addr_r=0x45800000\0" \ "scriptaddr=0x43900000\0" \ "pxefile_addr_r=0x45900000\0" \ "ramdisk_addr_r=0x46100000\0" \ diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 1318f5e5ee4..08b6f3219c3 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -21,25 +21,4 @@ */ #define CFG_SYS_NS16550_CLK 166666666 -/* - * Even though the board houses Realtek RTL8211E PHY - * corresponding PHY driver (drivers/net/phy/realtek.c) behaves unexpectedly. - * In particular "parse_status" reports link is down. - * - * Until Realtek PHY driver is fixed fall back to generic PHY driver - * which implements all required functionality and behaves much more stable. - * - * - */ - -/* - * Ethernet configuration - */ -#define ETH0_BASE_ADDRESS 0xFE100000 -#define ETH1_BASE_ADDRESS 0xFE110000 - -/* - * Console configuration - */ - #endif /* _CONFIG_TB100_H_ */ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 8c75a75a9e5..2da76f15431 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -8,7 +8,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <linux/kconfig.h> #include <linux/stringify.h> /* place code in last 4 MiB of RAM */ diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 24d8ca08665..8020689e39e 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -187,6 +187,7 @@ func(USB, usb, 0) \ func(SATA, sata, 0) \ func(SATA, sata, 1) \ + FUNC_VIRTIO(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) \ func(AFS, afs, na) diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h index d29ea700b2e..14532542ea6 100644 --- a/include/configs/x3-t30.h +++ b/include/configs/x3-t30.h @@ -14,19 +14,8 @@ #include "tegra30-common.h" -#define CFG_TEGRA_BOARD_STRING "LG X3 Board" - -#ifdef CONFIG_DEVICE_P880 /* High-level configuration options */ -#undef CFG_TEGRA_BOARD_STRING -#define CFG_TEGRA_BOARD_STRING "LG Optimus 4X HD" -#endif - -#ifdef CONFIG_DEVICE_P895 -/* High-level configuration options */ -#undef CFG_TEGRA_BOARD_STRING -#define CFG_TEGRA_BOARD_STRING "LG Optimus Vu" -#endif +#define CFG_TEGRA_BOARD_STRING "LG X3 Board" #define X3_FLASH_UBOOT \ "flash_uboot=echo Preparing RAM;" \ diff --git a/include/configs/xilinx_mbv.h b/include/configs/xilinx_mbv.h new file mode 100644 index 00000000000..dba398aeec4 --- /dev/null +++ b/include/configs/xilinx_mbv.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ diff --git a/include/dt-bindings/clock/mediatek,mt8365-clk.h b/include/dt-bindings/clock/mediatek,mt8365-clk.h new file mode 100644 index 00000000000..e5cb8a19ab9 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8365-clk.h @@ -0,0 +1,375 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + * + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_CLK_MT8365_H +#define _DT_BINDINGS_CLK_MT8365_H + +/* TOPCKGEN */ +#define CLK_TOP_CLK_NULL 0 +#define CLK_TOP_I2S0_BCK 1 +#define CLK_TOP_DSI0_LNTC_DSICK 2 +#define CLK_TOP_VPLL_DPIX 3 +#define CLK_TOP_LVDSTX_CLKDIG_CTS 4 +#define CLK_TOP_MFGPLL 5 +#define CLK_TOP_SYSPLL_D2 6 +#define CLK_TOP_SYSPLL1_D2 7 +#define CLK_TOP_SYSPLL1_D4 8 +#define CLK_TOP_SYSPLL1_D8 9 +#define CLK_TOP_SYSPLL1_D16 10 +#define CLK_TOP_SYSPLL_D3 11 +#define CLK_TOP_SYSPLL2_D2 12 +#define CLK_TOP_SYSPLL2_D4 13 +#define CLK_TOP_SYSPLL2_D8 14 +#define CLK_TOP_SYSPLL_D5 15 +#define CLK_TOP_SYSPLL3_D2 16 +#define CLK_TOP_SYSPLL3_D4 17 +#define CLK_TOP_SYSPLL_D7 18 +#define CLK_TOP_SYSPLL4_D2 19 +#define CLK_TOP_SYSPLL4_D4 20 +#define CLK_TOP_UNIVPLL 21 +#define CLK_TOP_UNIVPLL_D2 22 +#define CLK_TOP_UNIVPLL1_D2 23 +#define CLK_TOP_UNIVPLL1_D4 24 +#define CLK_TOP_UNIVPLL_D3 25 +#define CLK_TOP_UNIVPLL2_D2 26 +#define CLK_TOP_UNIVPLL2_D4 27 +#define CLK_TOP_UNIVPLL2_D8 28 +#define CLK_TOP_UNIVPLL2_D32 29 +#define CLK_TOP_UNIVPLL_D5 30 +#define CLK_TOP_UNIVPLL3_D2 31 +#define CLK_TOP_UNIVPLL3_D4 32 +#define CLK_TOP_MMPLL 33 +#define CLK_TOP_MMPLL_D2 34 +#define CLK_TOP_LVDSPLL_D2 35 +#define CLK_TOP_LVDSPLL_D4 36 +#define CLK_TOP_LVDSPLL_D8 37 +#define CLK_TOP_LVDSPLL_D16 38 +#define CLK_TOP_USB20_192M 39 +#define CLK_TOP_USB20_192M_D4 40 +#define CLK_TOP_USB20_192M_D8 41 +#define CLK_TOP_USB20_192M_D16 42 +#define CLK_TOP_USB20_192M_D32 43 +#define CLK_TOP_APLL1 44 +#define CLK_TOP_APLL1_D2 45 +#define CLK_TOP_APLL1_D4 46 +#define CLK_TOP_APLL1_D8 47 +#define CLK_TOP_APLL2 48 +#define CLK_TOP_APLL2_D2 49 +#define CLK_TOP_APLL2_D4 50 +#define CLK_TOP_APLL2_D8 51 +#define CLK_TOP_SYS_26M_D2 52 +#define CLK_TOP_MSDCPLL 53 +#define CLK_TOP_MSDCPLL_D2 54 +#define CLK_TOP_DSPPLL 55 +#define CLK_TOP_DSPPLL_D2 56 +#define CLK_TOP_DSPPLL_D4 57 +#define CLK_TOP_DSPPLL_D8 58 +#define CLK_TOP_APUPLL 59 +#define CLK_TOP_CLK26M_D52 60 +#define CLK_TOP_AXI_SEL 61 +#define CLK_TOP_MEM_SEL 62 +#define CLK_TOP_MM_SEL 63 +#define CLK_TOP_SCP_SEL 64 +#define CLK_TOP_MFG_SEL 65 +#define CLK_TOP_ATB_SEL 66 +#define CLK_TOP_CAMTG_SEL 67 +#define CLK_TOP_CAMTG1_SEL 68 +#define CLK_TOP_UART_SEL 69 +#define CLK_TOP_SPI_SEL 70 +#define CLK_TOP_MSDC50_0_HC_SEL 71 +#define CLK_TOP_MSDC2_2_HC_SEL 72 +#define CLK_TOP_MSDC50_0_SEL 73 +#define CLK_TOP_MSDC50_2_SEL 74 +#define CLK_TOP_MSDC30_1_SEL 75 +#define CLK_TOP_AUDIO_SEL 76 +#define CLK_TOP_AUD_INTBUS_SEL 77 +#define CLK_TOP_AUD_1_SEL 78 +#define CLK_TOP_AUD_2_SEL 79 +#define CLK_TOP_AUD_ENGEN1_SEL 80 +#define CLK_TOP_AUD_ENGEN2_SEL 81 +#define CLK_TOP_AUD_SPDIF_SEL 82 +#define CLK_TOP_DISP_PWM_SEL 83 +#define CLK_TOP_DXCC_SEL 84 +#define CLK_TOP_SSUSB_SYS_SEL 85 +#define CLK_TOP_SSUSB_XHCI_SEL 86 +#define CLK_TOP_SPM_SEL 87 +#define CLK_TOP_I2C_SEL 88 +#define CLK_TOP_PWM_SEL 89 +#define CLK_TOP_SENIF_SEL 90 +#define CLK_TOP_AES_FDE_SEL 91 +#define CLK_TOP_CAMTM_SEL 92 +#define CLK_TOP_DPI0_SEL 93 +#define CLK_TOP_DPI1_SEL 94 +#define CLK_TOP_DSP_SEL 95 +#define CLK_TOP_NFI2X_SEL 96 +#define CLK_TOP_NFIECC_SEL 97 +#define CLK_TOP_ECC_SEL 98 +#define CLK_TOP_ETH_SEL 99 +#define CLK_TOP_GCPU_SEL 100 +#define CLK_TOP_GCPU_CPM_SEL 101 +#define CLK_TOP_APU_SEL 102 +#define CLK_TOP_APU_IF_SEL 103 +#define CLK_TOP_MBIST_DIAG_SEL 104 +#define CLK_TOP_APLL_I2S0_SEL 105 +#define CLK_TOP_APLL_I2S1_SEL 106 +#define CLK_TOP_APLL_I2S2_SEL 107 +#define CLK_TOP_APLL_I2S3_SEL 108 +#define CLK_TOP_APLL_TDMOUT_SEL 109 +#define CLK_TOP_APLL_TDMIN_SEL 110 +#define CLK_TOP_APLL_SPDIF_SEL 111 +#define CLK_TOP_APLL12_CK_DIV0 112 +#define CLK_TOP_APLL12_CK_DIV1 113 +#define CLK_TOP_APLL12_CK_DIV2 114 +#define CLK_TOP_APLL12_CK_DIV3 115 +#define CLK_TOP_APLL12_CK_DIV4 116 +#define CLK_TOP_APLL12_CK_DIV4B 117 +#define CLK_TOP_APLL12_CK_DIV5 118 +#define CLK_TOP_APLL12_CK_DIV5B 119 +#define CLK_TOP_APLL12_CK_DIV6 120 +#define CLK_TOP_AUD_I2S0_M 121 +#define CLK_TOP_AUD_I2S1_M 122 +#define CLK_TOP_AUD_I2S2_M 123 +#define CLK_TOP_AUD_I2S3_M 124 +#define CLK_TOP_AUD_TDMOUT_M 125 +#define CLK_TOP_AUD_TDMOUT_B 126 +#define CLK_TOP_AUD_TDMIN_M 127 +#define CLK_TOP_AUD_TDMIN_B 128 +#define CLK_TOP_AUD_SPDIF_M 129 +#define CLK_TOP_USB20_48M_EN 130 +#define CLK_TOP_UNIVPLL_48M_EN 131 +#define CLK_TOP_LVDSTX_CLKDIG_EN 132 +#define CLK_TOP_VPLL_DPIX_EN 133 +#define CLK_TOP_SSUSB_TOP_CK_EN 134 +#define CLK_TOP_SSUSB_PHY_CK_EN 135 +#define CLK_TOP_CONN_32K 136 +#define CLK_TOP_CONN_26M 137 +#define CLK_TOP_DSP_32K 138 +#define CLK_TOP_DSP_26M 139 +#define CLK_TOP_NR_CLK 140 +#define CLK_TOP_CLK26M 141 +#define CLK_TOP_CLK32K 142 + +/* INFRACFG */ +#define CLK_IFR_PMIC_TMR 0 +#define CLK_IFR_PMIC_AP 1 +#define CLK_IFR_PMIC_MD 2 +#define CLK_IFR_PMIC_CONN 3 +#define CLK_IFR_ICUSB 4 +#define CLK_IFR_GCE 5 +#define CLK_IFR_THERM 6 +#define CLK_IFR_PWM_HCLK 7 +#define CLK_IFR_PWM1 8 +#define CLK_IFR_PWM2 9 +#define CLK_IFR_PWM3 10 +#define CLK_IFR_PWM4 11 +#define CLK_IFR_PWM5 12 +#define CLK_IFR_PWM 13 +#define CLK_IFR_UART0 14 +#define CLK_IFR_UART1 15 +#define CLK_IFR_UART2 16 +#define CLK_IFR_DSP_UART 17 +#define CLK_IFR_GCE_26M 18 +#define CLK_IFR_CQ_DMA_FPC 19 +#define CLK_IFR_BTIF 20 +#define CLK_IFR_SPI0 21 +#define CLK_IFR_MSDC0_HCLK 22 +#define CLK_IFR_MSDC2_HCLK 23 +#define CLK_IFR_MSDC1_HCLK 24 +#define CLK_IFR_DVFSRC 25 +#define CLK_IFR_GCPU 26 +#define CLK_IFR_TRNG 27 +#define CLK_IFR_AUXADC 28 +#define CLK_IFR_CPUM 29 +#define CLK_IFR_AUXADC_MD 30 +#define CLK_IFR_AP_DMA 31 +#define CLK_IFR_DEBUGSYS 32 +#define CLK_IFR_AUDIO 33 +#define CLK_IFR_PWM_FBCLK6 34 +#define CLK_IFR_DISP_PWM 35 +#define CLK_IFR_AUD_26M_BK 36 +#define CLK_IFR_CQ_DMA 37 +#define CLK_IFR_MSDC0_SF 38 +#define CLK_IFR_MSDC1_SF 39 +#define CLK_IFR_MSDC2_SF 40 +#define CLK_IFR_AP_MSDC0 41 +#define CLK_IFR_MD_MSDC0 42 +#define CLK_IFR_MSDC0_SRC 43 +#define CLK_IFR_MSDC1_SRC 44 +#define CLK_IFR_MSDC2_SRC 45 +#define CLK_IFR_PWRAP_TMR 46 +#define CLK_IFR_PWRAP_SPI 47 +#define CLK_IFR_PWRAP_SYS 48 +#define CLK_IFR_MCU_PM_BK 49 +#define CLK_IFR_IRRX_26M 50 +#define CLK_IFR_IRRX_32K 51 +#define CLK_IFR_I2C0_AXI 52 +#define CLK_IFR_I2C1_AXI 53 +#define CLK_IFR_I2C2_AXI 54 +#define CLK_IFR_I2C3_AXI 55 +#define CLK_IFR_NIC_AXI 56 +#define CLK_IFR_NIC_SLV_AXI 57 +#define CLK_IFR_APU_AXI 58 +#define CLK_IFR_NFIECC 59 +#define CLK_IFR_NFIECC_BK 60 +#define CLK_IFR_NFI1X_BK 61 +#define CLK_IFR_NFI_BK 62 +#define CLK_IFR_MSDC2_AP_BK 63 +#define CLK_IFR_MSDC2_MD_BK 64 +#define CLK_IFR_MSDC2_BK 65 +#define CLK_IFR_SUSB_133_BK 66 +#define CLK_IFR_SUSB_66_BK 67 +#define CLK_IFR_SSUSB_SYS 68 +#define CLK_IFR_SSUSB_REF 69 +#define CLK_IFR_SSUSB_XHCI 70 +#define CLK_IFR_NR_CLK 71 + +/* PERICFG */ +#define CLK_PERIAXI 0 +#define CLK_PERI_NR_CLK 1 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIVPLL 2 +#define CLK_APMIXED_MFGPLL 3 +#define CLK_APMIXED_MSDCPLL 4 +#define CLK_APMIXED_MMPLL 5 +#define CLK_APMIXED_APLL1 6 +#define CLK_APMIXED_APLL2 7 +#define CLK_APMIXED_LVDSPLL 8 +#define CLK_APMIXED_DSPPLL 9 +#define CLK_APMIXED_APUPLL 10 +#define CLK_APMIXED_UNIV_EN 11 +#define CLK_APMIXED_USB20_EN 12 +#define CLK_APMIXED_NR_CLK 13 + +/* GCE */ +#define CLK_GCE_FAXI 0 +#define CLK_GCE_NR_CLK 1 + +/* AUDIOTOP */ +#define CLK_AUD_AFE 0 +#define CLK_AUD_I2S 1 +#define CLK_AUD_22M 2 +#define CLK_AUD_24M 3 +#define CLK_AUD_INTDIR 4 +#define CLK_AUD_APLL2_TUNER 5 +#define CLK_AUD_APLL_TUNER 6 +#define CLK_AUD_SPDF 7 +#define CLK_AUD_HDMI 8 +#define CLK_AUD_HDMI_IN 9 +#define CLK_AUD_ADC 10 +#define CLK_AUD_DAC 11 +#define CLK_AUD_DAC_PREDIS 12 +#define CLK_AUD_TML 13 +#define CLK_AUD_I2S1_BK 14 +#define CLK_AUD_I2S2_BK 15 +#define CLK_AUD_I2S3_BK 16 +#define CLK_AUD_I2S4_BK 17 +#define CLK_AUD_NR_CLK 18 + +/* MIPI_CSI0A */ +#define CLK_MIPI0A_CSR_CSI_EN_0A 0 +#define CLK_MIPI_RX_ANA_CSI0A_NR_CLK 1 + +/* MIPI_CSI0B */ +#define CLK_MIPI0B_CSR_CSI_EN_0B 0 +#define CLK_MIPI_RX_ANA_CSI0B_NR_CLK 1 + +/* MIPI_CSI1A */ +#define CLK_MIPI1A_CSR_CSI_EN_1A 0 +#define CLK_MIPI_RX_ANA_CSI1A_NR_CLK 1 + +/* MIPI_CSI1B */ +#define CLK_MIPI1B_CSR_CSI_EN_1B 0 +#define CLK_MIPI_RX_ANA_CSI1B_NR_CLK 1 + +/* MIPI_CSI2A */ +#define CLK_MIPI2A_CSR_CSI_EN_2A 0 +#define CLK_MIPI_RX_ANA_CSI2A_NR_CLK 1 + +/* MIPI_CSI2B */ +#define CLK_MIPI2B_CSR_CSI_EN_2B 0 +#define CLK_MIPI_RX_ANA_CSI2B_NR_CLK 1 + +/* MCUCFG */ +#define CLK_MCU_BUS_SEL 0 +#define CLK_MCU_NR_CLK 1 + +/* MFGCFG */ +#define CLK_MFG_BG3D 0 +#define CLK_MFG_MBIST_DIAG 1 +#define CLK_MFG_NR_CLK 2 + +/* MMSYS */ +#define CLK_MM_MM_MDP_RDMA0 0 +#define CLK_MM_MM_MDP_CCORR0 1 +#define CLK_MM_MM_MDP_RSZ0 2 +#define CLK_MM_MM_MDP_RSZ1 3 +#define CLK_MM_MM_MDP_TDSHP0 4 +#define CLK_MM_MM_MDP_WROT0 5 +#define CLK_MM_MM_MDP_WDMA0 6 +#define CLK_MM_MM_DISP_OVL0 7 +#define CLK_MM_MM_DISP_OVL0_2L 8 +#define CLK_MM_MM_DISP_RSZ0 9 +#define CLK_MM_MM_DISP_RDMA0 10 +#define CLK_MM_MM_DISP_WDMA0 11 +#define CLK_MM_MM_DISP_COLOR0 12 +#define CLK_MM_MM_DISP_CCORR0 13 +#define CLK_MM_MM_DISP_AAL0 14 +#define CLK_MM_MM_DISP_GAMMA0 15 +#define CLK_MM_MM_DISP_DITHER0 16 +#define CLK_MM_MM_DSI0 17 +#define CLK_MM_MM_DISP_RDMA1 18 +#define CLK_MM_MM_MDP_RDMA1 19 +#define CLK_MM_DPI0_DPI0 20 +#define CLK_MM_MM_FAKE 21 +#define CLK_MM_MM_SMI_COMMON 22 +#define CLK_MM_MM_SMI_LARB0 23 +#define CLK_MM_MM_SMI_COMM0 24 +#define CLK_MM_MM_SMI_COMM1 25 +#define CLK_MM_MM_CAM_MDP 26 +#define CLK_MM_MM_SMI_IMG 27 +#define CLK_MM_MM_SMI_CAM 28 +#define CLK_MM_IMG_IMG_DL_RELAY 29 +#define CLK_MM_IMG_IMG_DL_ASYNC_TOP 30 +#define CLK_MM_DSI0_DIG_DSI 31 +#define CLK_MM_26M_HRTWT 32 +#define CLK_MM_MM_DPI0 33 +#define CLK_MM_LVDSTX_PXL 34 +#define CLK_MM_LVDSTX_CTS 35 +#define CLK_MM_NR_CLK 36 + +/* IMGSYS */ +#define CLK_CAM_LARB2 0 +#define CLK_CAM 1 +#define CLK_CAMTG 2 +#define CLK_CAM_SENIF 3 +#define CLK_CAMSV0 4 +#define CLK_CAMSV1 5 +#define CLK_CAM_FDVT 6 +#define CLK_CAM_WPE 7 +#define CLK_CAM_NR_CLK 8 + +/* VDECSYS */ +#define CLK_VDEC_VDEC 0 +#define CLK_VDEC_LARB1 1 +#define CLK_VDEC_NR_CLK 2 + +/* VENCSYS */ +#define CLK_VENC 0 +#define CLK_VENC_JPGENC 1 +#define CLK_VENC_NR_CLK 2 + +/* APUSYS */ +#define CLK_APU_IPU_CK 0 +#define CLK_APU_AXI 1 +#define CLK_APU_JTAG 2 +#define CLK_APU_IF_CK 3 +#define CLK_APU_EDMA 4 +#define CLK_APU_AHB 5 +#define CLK_APU_NR_CLK 6 + +#endif /* _DT_BINDINGS_CLK_MT8365_H */ diff --git a/include/dt-bindings/pinctrl/mt8365-pinfunc.h b/include/dt-bindings/pinctrl/mt8365-pinfunc.h new file mode 100644 index 00000000000..e2ec8af57dc --- /dev/null +++ b/include/dt-bindings/pinctrl/mt8365-pinfunc.h @@ -0,0 +1,858 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 MediaTek Inc. + */ +#ifndef __MT8365_PINFUNC_H +#define __MT8365_PINFUNC_H + +#include <dt-bindings/pinctrl/mt65xx.h> + +#define MT8365_PIN_0_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT8365_PIN_0_GPIO0__FUNC_DPI_D0 (MTK_PIN_NO(0) | 1) +#define MT8365_PIN_0_GPIO0__FUNC_PWM_A (MTK_PIN_NO(0) | 2) +#define MT8365_PIN_0_GPIO0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3) +#define MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4) +#define MT8365_PIN_0_GPIO0__FUNC_CONN_MCU_TDO (MTK_PIN_NO(0) | 5) +#define MT8365_PIN_0_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7) + +#define MT8365_PIN_1_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT8365_PIN_1_GPIO1__FUNC_DPI_D1 (MTK_PIN_NO(1) | 1) +#define MT8365_PIN_1_GPIO1__FUNC_PWM_B (MTK_PIN_NO(1) | 2) +#define MT8365_PIN_1_GPIO1__FUNC_I2S2_LRCK (MTK_PIN_NO(1) | 3) +#define MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4) +#define MT8365_PIN_1_GPIO1__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(1) | 5) +#define MT8365_PIN_1_GPIO1__FUNC_DBG_MON_A1 (MTK_PIN_NO(1) | 7) + +#define MT8365_PIN_2_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT8365_PIN_2_GPIO2__FUNC_DPI_D2 (MTK_PIN_NO(2) | 1) +#define MT8365_PIN_2_GPIO2__FUNC_PWM_C (MTK_PIN_NO(2) | 2) +#define MT8365_PIN_2_GPIO2__FUNC_I2S2_MCK (MTK_PIN_NO(2) | 3) +#define MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4) +#define MT8365_PIN_2_GPIO2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(2) | 5) +#define MT8365_PIN_2_GPIO2__FUNC_DBG_MON_A2 (MTK_PIN_NO(2) | 7) + +#define MT8365_PIN_3_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT8365_PIN_3_GPIO3__FUNC_DPI_D3 (MTK_PIN_NO(3) | 1) +#define MT8365_PIN_3_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 2) +#define MT8365_PIN_3_GPIO3__FUNC_I2S2_DI (MTK_PIN_NO(3) | 3) +#define MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4) +#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_TCK (MTK_PIN_NO(3) | 5) +#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(3) | 6) +#define MT8365_PIN_3_GPIO3__FUNC_DBG_MON_A3 (MTK_PIN_NO(3) | 7) + +#define MT8365_PIN_4_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT8365_PIN_4_GPIO4__FUNC_DPI_D4 (MTK_PIN_NO(4) | 1) +#define MT8365_PIN_4_GPIO4__FUNC_CLKM1 (MTK_PIN_NO(4) | 2) +#define MT8365_PIN_4_GPIO4__FUNC_I2S1_BCK (MTK_PIN_NO(4) | 3) +#define MT8365_PIN_4_GPIO4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4) +#define MT8365_PIN_4_GPIO4__FUNC_CONN_MCU_TDI (MTK_PIN_NO(4) | 5) +#define MT8365_PIN_4_GPIO4__FUNC_VDEC_TEST_CK (MTK_PIN_NO(4) | 6) +#define MT8365_PIN_4_GPIO4__FUNC_DBG_MON_A4 (MTK_PIN_NO(4) | 7) + +#define MT8365_PIN_5_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT8365_PIN_5_GPIO5__FUNC_DPI_D5 (MTK_PIN_NO(5) | 1) +#define MT8365_PIN_5_GPIO5__FUNC_CLKM2 (MTK_PIN_NO(5) | 2) +#define MT8365_PIN_5_GPIO5__FUNC_I2S1_LRCK (MTK_PIN_NO(5) | 3) +#define MT8365_PIN_5_GPIO5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4) +#define MT8365_PIN_5_GPIO5__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(5) | 5) +#define MT8365_PIN_5_GPIO5__FUNC_MM_TEST_CK (MTK_PIN_NO(5) | 6) +#define MT8365_PIN_5_GPIO5__FUNC_DBG_MON_A5 (MTK_PIN_NO(5) | 7) + +#define MT8365_PIN_6_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT8365_PIN_6_GPIO6__FUNC_DPI_D6 (MTK_PIN_NO(6) | 1) +#define MT8365_PIN_6_GPIO6__FUNC_CLKM3 (MTK_PIN_NO(6) | 2) +#define MT8365_PIN_6_GPIO6__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 3) +#define MT8365_PIN_6_GPIO6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4) +#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_TMS (MTK_PIN_NO(6) | 5) +#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(6) | 6) +#define MT8365_PIN_6_GPIO6__FUNC_DBG_MON_A6 (MTK_PIN_NO(6) | 7) + +#define MT8365_PIN_7_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT8365_PIN_7_GPIO7__FUNC_DPI_D7 (MTK_PIN_NO(7) | 1) +#define MT8365_PIN_7_GPIO7__FUNC_I2S1_DO (MTK_PIN_NO(7) | 3) +#define MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4) +#define MT8365_PIN_7_GPIO7__FUNC_CONN_DSP_JCK (MTK_PIN_NO(7) | 5) +#define MT8365_PIN_7_GPIO7__FUNC_DBG_MON_A7 (MTK_PIN_NO(7) | 7) + +#define MT8365_PIN_8_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT8365_PIN_8_GPIO8__FUNC_DPI_D8 (MTK_PIN_NO(8) | 1) +#define MT8365_PIN_8_GPIO8__FUNC_SPI_CLK (MTK_PIN_NO(8) | 2) +#define MT8365_PIN_8_GPIO8__FUNC_I2S0_BCK (MTK_PIN_NO(8) | 3) +#define MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4) +#define MT8365_PIN_8_GPIO8__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(8) | 5) +#define MT8365_PIN_8_GPIO8__FUNC_DBG_MON_A8 (MTK_PIN_NO(8) | 7) + +#define MT8365_PIN_9_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT8365_PIN_9_GPIO9__FUNC_DPI_D9 (MTK_PIN_NO(9) | 1) +#define MT8365_PIN_9_GPIO9__FUNC_SPI_CSB (MTK_PIN_NO(9) | 2) +#define MT8365_PIN_9_GPIO9__FUNC_I2S0_LRCK (MTK_PIN_NO(9) | 3) +#define MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4) +#define MT8365_PIN_9_GPIO9__FUNC_CONN_DSP_JDI (MTK_PIN_NO(9) | 5) +#define MT8365_PIN_9_GPIO9__FUNC_DBG_MON_A9 (MTK_PIN_NO(9) | 7) + +#define MT8365_PIN_10_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT8365_PIN_10_GPIO10__FUNC_DPI_D10 (MTK_PIN_NO(10) | 1) +#define MT8365_PIN_10_GPIO10__FUNC_SPI_MI (MTK_PIN_NO(10) | 2) +#define MT8365_PIN_10_GPIO10__FUNC_I2S0_MCK (MTK_PIN_NO(10) | 3) +#define MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4) +#define MT8365_PIN_10_GPIO10__FUNC_CONN_DSP_JMS (MTK_PIN_NO(10) | 5) +#define MT8365_PIN_10_GPIO10__FUNC_DBG_MON_A10 (MTK_PIN_NO(10) | 7) + +#define MT8365_PIN_11_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT8365_PIN_11_GPIO11__FUNC_DPI_D11 (MTK_PIN_NO(11) | 1) +#define MT8365_PIN_11_GPIO11__FUNC_SPI_MO (MTK_PIN_NO(11) | 2) +#define MT8365_PIN_11_GPIO11__FUNC_I2S0_DI (MTK_PIN_NO(11) | 3) +#define MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 4) +#define MT8365_PIN_11_GPIO11__FUNC_CONN_DSP_JDO (MTK_PIN_NO(11) | 5) +#define MT8365_PIN_11_GPIO11__FUNC_DBG_MON_A11 (MTK_PIN_NO(11) | 7) + +#define MT8365_PIN_12_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT8365_PIN_12_GPIO12__FUNC_DPI_DE (MTK_PIN_NO(12) | 1) +#define MT8365_PIN_12_GPIO12__FUNC_UCTS1 (MTK_PIN_NO(12) | 2) +#define MT8365_PIN_12_GPIO12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 3) +#define MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 4) +#define MT8365_PIN_12_GPIO12__FUNC_O_WIFI_TXD (MTK_PIN_NO(12) | 5) +#define MT8365_PIN_12_GPIO12__FUNC_DBG_MON_A12 (MTK_PIN_NO(12) | 7) + +#define MT8365_PIN_13_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC (MTK_PIN_NO(13) | 1) +#define MT8365_PIN_13_GPIO13__FUNC_URTS1 (MTK_PIN_NO(13) | 2) +#define MT8365_PIN_13_GPIO13__FUNC_I2S3_LRCK (MTK_PIN_NO(13) | 3) +#define MT8365_PIN_13_GPIO13__FUNC_EXT_COL (MTK_PIN_NO(13) | 4) +#define MT8365_PIN_13_GPIO13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 5) +#define MT8365_PIN_13_GPIO13__FUNC_DBG_MON_A13 (MTK_PIN_NO(13) | 7) + +#define MT8365_PIN_14_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT8365_PIN_14_GPIO14__FUNC_DPI_CK (MTK_PIN_NO(14) | 1) +#define MT8365_PIN_14_GPIO14__FUNC_UCTS2 (MTK_PIN_NO(14) | 2) +#define MT8365_PIN_14_GPIO14__FUNC_I2S3_MCK (MTK_PIN_NO(14) | 3) +#define MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO (MTK_PIN_NO(14) | 4) +#define MT8365_PIN_14_GPIO14__FUNC_SPDIF_OUT (MTK_PIN_NO(14) | 5) +#define MT8365_PIN_14_GPIO14__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(14) | 6) +#define MT8365_PIN_14_GPIO14__FUNC_DBG_MON_A14 (MTK_PIN_NO(14) | 7) + +#define MT8365_PIN_15_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC (MTK_PIN_NO(15) | 1) +#define MT8365_PIN_15_GPIO15__FUNC_URTS2 (MTK_PIN_NO(15) | 2) +#define MT8365_PIN_15_GPIO15__FUNC_I2S3_DO (MTK_PIN_NO(15) | 3) +#define MT8365_PIN_15_GPIO15__FUNC_EXT_MDC (MTK_PIN_NO(15) | 4) +#define MT8365_PIN_15_GPIO15__FUNC_IRRX (MTK_PIN_NO(15) | 5) +#define MT8365_PIN_15_GPIO15__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(15) | 6) +#define MT8365_PIN_15_GPIO15__FUNC_DBG_MON_A15 (MTK_PIN_NO(15) | 7) + +#define MT8365_PIN_16_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT8365_PIN_16_GPIO16__FUNC_DPI_D12 (MTK_PIN_NO(16) | 1) +#define MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS (MTK_PIN_NO(16) | 2) +#define MT8365_PIN_16_GPIO16__FUNC_PWM_A (MTK_PIN_NO(16) | 3) +#define MT8365_PIN_16_GPIO16__FUNC_CLKM0 (MTK_PIN_NO(16) | 4) +#define MT8365_PIN_16_GPIO16__FUNC_ANT_SEL0 (MTK_PIN_NO(16) | 5) +#define MT8365_PIN_16_GPIO16__FUNC_TSF_IN (MTK_PIN_NO(16) | 6) +#define MT8365_PIN_16_GPIO16__FUNC_DBG_MON_A16 (MTK_PIN_NO(16) | 7) + +#define MT8365_PIN_17_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT8365_PIN_17_GPIO17__FUNC_DPI_D13 (MTK_PIN_NO(17) | 1) +#define MT8365_PIN_17_GPIO17__FUNC_IDDIG (MTK_PIN_NO(17) | 2) +#define MT8365_PIN_17_GPIO17__FUNC_PWM_B (MTK_PIN_NO(17) | 3) +#define MT8365_PIN_17_GPIO17__FUNC_CLKM1 (MTK_PIN_NO(17) | 4) +#define MT8365_PIN_17_GPIO17__FUNC_ANT_SEL1 (MTK_PIN_NO(17) | 5) +#define MT8365_PIN_17_GPIO17__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(17) | 6) +#define MT8365_PIN_17_GPIO17__FUNC_DBG_MON_A17 (MTK_PIN_NO(17) | 7) + +#define MT8365_PIN_18_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT8365_PIN_18_GPIO18__FUNC_DPI_D14 (MTK_PIN_NO(18) | 1) +#define MT8365_PIN_18_GPIO18__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(18) | 2) +#define MT8365_PIN_18_GPIO18__FUNC_PWM_C (MTK_PIN_NO(18) | 3) +#define MT8365_PIN_18_GPIO18__FUNC_CLKM2 (MTK_PIN_NO(18) | 4) +#define MT8365_PIN_18_GPIO18__FUNC_ANT_SEL2 (MTK_PIN_NO(18) | 5) +#define MT8365_PIN_18_GPIO18__FUNC_MFG_TEST_CK (MTK_PIN_NO(18) | 6) +#define MT8365_PIN_18_GPIO18__FUNC_DBG_MON_A18 (MTK_PIN_NO(18) | 7) + +#define MT8365_PIN_19_DISP_PWM__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT8365_PIN_19_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(19) | 1) +#define MT8365_PIN_19_DISP_PWM__FUNC_PWM_A (MTK_PIN_NO(19) | 2) +#define MT8365_PIN_19_DISP_PWM__FUNC_DBG_MON_A19 (MTK_PIN_NO(19) | 7) + +#define MT8365_PIN_20_LCM_RST__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT8365_PIN_20_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(20) | 1) +#define MT8365_PIN_20_LCM_RST__FUNC_PWM_B (MTK_PIN_NO(20) | 2) +#define MT8365_PIN_20_LCM_RST__FUNC_DBG_MON_A20 (MTK_PIN_NO(20) | 7) + +#define MT8365_PIN_21_DSI_TE__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT8365_PIN_21_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(21) | 1) +#define MT8365_PIN_21_DSI_TE__FUNC_PWM_C (MTK_PIN_NO(21) | 2) +#define MT8365_PIN_21_DSI_TE__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 3) +#define MT8365_PIN_21_DSI_TE__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(21) | 4) +#define MT8365_PIN_21_DSI_TE__FUNC_DBG_MON_A21 (MTK_PIN_NO(21) | 7) + +#define MT8365_PIN_22_KPROW0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT8365_PIN_22_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(22) | 1) +#define MT8365_PIN_22_KPROW0__FUNC_DBG_MON_A22 (MTK_PIN_NO(22) | 7) + +#define MT8365_PIN_23_KPROW1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT8365_PIN_23_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(23) | 1) +#define MT8365_PIN_23_KPROW1__FUNC_IDDIG (MTK_PIN_NO(23) | 2) +#define MT8365_PIN_23_KPROW1__FUNC_WIFI_TXD (MTK_PIN_NO(23) | 3) +#define MT8365_PIN_23_KPROW1__FUNC_CLKM3 (MTK_PIN_NO(23) | 4) +#define MT8365_PIN_23_KPROW1__FUNC_ANT_SEL1 (MTK_PIN_NO(23) | 5) +#define MT8365_PIN_23_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 6) +#define MT8365_PIN_23_KPROW1__FUNC_DBG_MON_B0 (MTK_PIN_NO(23) | 7) + +#define MT8365_PIN_24_KPCOL0__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT8365_PIN_24_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(24) | 1) +#define MT8365_PIN_24_KPCOL0__FUNC_DBG_MON_A23 (MTK_PIN_NO(24) | 7) + +#define MT8365_PIN_25_KPCOL1__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT8365_PIN_25_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(25) | 1) +#define MT8365_PIN_25_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(25) | 2) +#define MT8365_PIN_25_KPCOL1__FUNC_APU_JTAG_TRST (MTK_PIN_NO(25) | 3) +#define MT8365_PIN_25_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(25) | 4) +#define MT8365_PIN_25_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(25) | 5) +#define MT8365_PIN_25_KPCOL1__FUNC_CONN_TEST_CK (MTK_PIN_NO(25) | 6) +#define MT8365_PIN_25_KPCOL1__FUNC_DBG_MON_B1 (MTK_PIN_NO(25) | 7) + +#define MT8365_PIN_26_SPI_CS__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT8365_PIN_26_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(26) | 1) +#define MT8365_PIN_26_SPI_CS__FUNC_APU_JTAG_TMS (MTK_PIN_NO(26) | 3) +#define MT8365_PIN_26_SPI_CS__FUNC_UDI_TMS_XI (MTK_PIN_NO(26) | 4) +#define MT8365_PIN_26_SPI_CS__FUNC_DFD_TMS_XI (MTK_PIN_NO(26) | 5) +#define MT8365_PIN_26_SPI_CS__FUNC_CONN_TEST_CK (MTK_PIN_NO(26) | 6) +#define MT8365_PIN_26_SPI_CS__FUNC_DBG_MON_A24 (MTK_PIN_NO(26) | 7) + +#define MT8365_PIN_27_SPI_CK__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT8365_PIN_27_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(27) | 1) +#define MT8365_PIN_27_SPI_CK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(27) | 3) +#define MT8365_PIN_27_SPI_CK__FUNC_UDI_TCK_XI (MTK_PIN_NO(27) | 4) +#define MT8365_PIN_27_SPI_CK__FUNC_DFD_TCK_XI (MTK_PIN_NO(27) | 5) +#define MT8365_PIN_27_SPI_CK__FUNC_APU_TEST_CK (MTK_PIN_NO(27) | 6) +#define MT8365_PIN_27_SPI_CK__FUNC_DBG_MON_A25 (MTK_PIN_NO(27) | 7) + +#define MT8365_PIN_28_SPI_MI__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(28) | 1) +#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(28) | 2) +#define MT8365_PIN_28_SPI_MI__FUNC_APU_JTAG_TDI (MTK_PIN_NO(28) | 3) +#define MT8365_PIN_28_SPI_MI__FUNC_UDI_TDI_XI (MTK_PIN_NO(28) | 4) +#define MT8365_PIN_28_SPI_MI__FUNC_DFD_TDI_XI (MTK_PIN_NO(28) | 5) +#define MT8365_PIN_28_SPI_MI__FUNC_DSP_TEST_CK (MTK_PIN_NO(28) | 6) +#define MT8365_PIN_28_SPI_MI__FUNC_DBG_MON_A26 (MTK_PIN_NO(28) | 7) + +#define MT8365_PIN_29_SPI_MO__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(29) | 1) +#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(29) | 2) +#define MT8365_PIN_29_SPI_MO__FUNC_APU_JTAG_TDO (MTK_PIN_NO(29) | 3) +#define MT8365_PIN_29_SPI_MO__FUNC_UDI_TDO (MTK_PIN_NO(29) | 4) +#define MT8365_PIN_29_SPI_MO__FUNC_DFD_TDO (MTK_PIN_NO(29) | 5) +#define MT8365_PIN_29_SPI_MO__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(29) | 6) +#define MT8365_PIN_29_SPI_MO__FUNC_DBG_MON_A27 (MTK_PIN_NO(29) | 7) + +#define MT8365_PIN_30_JTMS__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT8365_PIN_30_JTMS__FUNC_JTMS (MTK_PIN_NO(30) | 1) +#define MT8365_PIN_30_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(30) | 2) +#define MT8365_PIN_30_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(30) | 3) +#define MT8365_PIN_30_JTMS__FUNC_MCU_SPM_TMS (MTK_PIN_NO(30) | 4) +#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(30) | 5) +#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 6) + +#define MT8365_PIN_31_JTCK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT8365_PIN_31_JTCK__FUNC_JTCK (MTK_PIN_NO(31) | 1) +#define MT8365_PIN_31_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(31) | 2) +#define MT8365_PIN_31_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(31) | 3) +#define MT8365_PIN_31_JTCK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(31) | 4) +#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(31) | 5) +#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(31) | 6) + +#define MT8365_PIN_32_JTDI__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT8365_PIN_32_JTDI__FUNC_JTDI (MTK_PIN_NO(32) | 1) +#define MT8365_PIN_32_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(32) | 2) +#define MT8365_PIN_32_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(32) | 3) +#define MT8365_PIN_32_JTDI__FUNC_MCU_SPM_TDI (MTK_PIN_NO(32) | 4) +#define MT8365_PIN_32_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(32) | 5) + +#define MT8365_PIN_33_JTDO__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT8365_PIN_33_JTDO__FUNC_JTDO (MTK_PIN_NO(33) | 1) +#define MT8365_PIN_33_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(33) | 2) +#define MT8365_PIN_33_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(33) | 3) +#define MT8365_PIN_33_JTDO__FUNC_MCU_SPM_TDO (MTK_PIN_NO(33) | 4) +#define MT8365_PIN_33_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(33) | 5) + +#define MT8365_PIN_34_JTRST__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT8365_PIN_34_JTRST__FUNC_JTRST (MTK_PIN_NO(34) | 1) +#define MT8365_PIN_34_JTRST__FUNC_DFD_NTRST_XI (MTK_PIN_NO(34) | 2) +#define MT8365_PIN_34_JTRST__FUNC_UDI_NTRST_XI (MTK_PIN_NO(34) | 3) +#define MT8365_PIN_34_JTRST__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(34) | 4) +#define MT8365_PIN_34_JTRST__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(34) | 5) + +#define MT8365_PIN_35_URXD0__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT8365_PIN_35_URXD0__FUNC_URXD0 (MTK_PIN_NO(35) | 1) +#define MT8365_PIN_35_URXD0__FUNC_UTXD0 (MTK_PIN_NO(35) | 2) +#define MT8365_PIN_35_URXD0__FUNC_DSP_URXD0 (MTK_PIN_NO(35) | 7) + +#define MT8365_PIN_36_UTXD0__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT8365_PIN_36_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(36) | 1) +#define MT8365_PIN_36_UTXD0__FUNC_URXD0 (MTK_PIN_NO(36) | 2) +#define MT8365_PIN_36_UTXD0__FUNC_DSP_UTXD0 (MTK_PIN_NO(36) | 7) + +#define MT8365_PIN_37_URXD1__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT8365_PIN_37_URXD1__FUNC_URXD1 (MTK_PIN_NO(37) | 1) +#define MT8365_PIN_37_URXD1__FUNC_UTXD1 (MTK_PIN_NO(37) | 2) +#define MT8365_PIN_37_URXD1__FUNC_UCTS2 (MTK_PIN_NO(37) | 3) +#define MT8365_PIN_37_URXD1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(37) | 4) +#define MT8365_PIN_37_URXD1__FUNC_CONN_UART0_RXD (MTK_PIN_NO(37) | 5) +#define MT8365_PIN_37_URXD1__FUNC_I2S0_MCK (MTK_PIN_NO(37) | 6) +#define MT8365_PIN_37_URXD1__FUNC_DSP_URXD0 (MTK_PIN_NO(37) | 7) + +#define MT8365_PIN_38_UTXD1__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT8365_PIN_38_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(38) | 1) +#define MT8365_PIN_38_UTXD1__FUNC_URXD1 (MTK_PIN_NO(38) | 2) +#define MT8365_PIN_38_UTXD1__FUNC_URTS2 (MTK_PIN_NO(38) | 3) +#define MT8365_PIN_38_UTXD1__FUNC_ANT_SEL2 (MTK_PIN_NO(38) | 4) +#define MT8365_PIN_38_UTXD1__FUNC_CONN_UART0_TXD (MTK_PIN_NO(38) | 5) +#define MT8365_PIN_38_UTXD1__FUNC_I2S1_MCK (MTK_PIN_NO(38) | 6) +#define MT8365_PIN_38_UTXD1__FUNC_DSP_UTXD0 (MTK_PIN_NO(38) | 7) + +#define MT8365_PIN_39_URXD2__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT8365_PIN_39_URXD2__FUNC_URXD2 (MTK_PIN_NO(39) | 1) +#define MT8365_PIN_39_URXD2__FUNC_UTXD2 (MTK_PIN_NO(39) | 2) +#define MT8365_PIN_39_URXD2__FUNC_UCTS1 (MTK_PIN_NO(39) | 3) +#define MT8365_PIN_39_URXD2__FUNC_IDDIG (MTK_PIN_NO(39) | 4) +#define MT8365_PIN_39_URXD2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(39) | 5) +#define MT8365_PIN_39_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(39) | 6) +#define MT8365_PIN_39_URXD2__FUNC_DSP_URXD0 (MTK_PIN_NO(39) | 7) + +#define MT8365_PIN_40_UTXD2__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT8365_PIN_40_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(40) | 1) +#define MT8365_PIN_40_UTXD2__FUNC_URXD2 (MTK_PIN_NO(40) | 2) +#define MT8365_PIN_40_UTXD2__FUNC_URTS1 (MTK_PIN_NO(40) | 3) +#define MT8365_PIN_40_UTXD2__FUNC_USB_DRVVBUS (MTK_PIN_NO(40) | 4) +#define MT8365_PIN_40_UTXD2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(40) | 5) +#define MT8365_PIN_40_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(40) | 6) +#define MT8365_PIN_40_UTXD2__FUNC_DSP_UTXD0 (MTK_PIN_NO(40) | 7) + +#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(41) | 1) +#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(41) | 2) + +#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(42) | 1) +#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(42) | 2) + +#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(43) | 1) + +#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(44) | 1) + +#define MT8365_PIN_45_RTC32K_CK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT8365_PIN_45_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(45) | 1) + +#define MT8365_PIN_46_WATCHDOG__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT8365_PIN_46_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(46) | 1) + +#define MT8365_PIN_47_SRCLKENA0__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(47) | 1) +#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA1 (MTK_PIN_NO(47) | 2) + +#define MT8365_PIN_48_SRCLKENA1__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT8365_PIN_48_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(48) | 1) + +#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(49) | 1) +#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MISO (MTK_PIN_NO(49) | 2) +#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_I2S1_MCK (MTK_PIN_NO(49) | 3) + +#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(50) | 1) +#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(50) | 2) +#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_I2S1_BCK (MTK_PIN_NO(50) | 3) + +#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(51) | 1) +#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(51) | 2) +#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_I2S1_LRCK (MTK_PIN_NO(51) | 3) + +#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(52) | 1) +#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(52) | 2) +#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_I2S1_DO (MTK_PIN_NO(52) | 3) + +#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO (MTK_PIN_NO(53) | 1) +#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(53) | 2) +#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_I2S2_MCK (MTK_PIN_NO(53) | 3) + +#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(54) | 1) +#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(54) | 2) +#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_I2S2_BCK (MTK_PIN_NO(54) | 3) + +#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(55) | 1) +#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(55) | 2) +#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_I2S2_LRCK (MTK_PIN_NO(55) | 3) + +#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(56) | 1) +#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(56) | 2) +#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_I2S2_DI (MTK_PIN_NO(56) | 3) + +#define MT8365_PIN_57_SDA0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT8365_PIN_57_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(57) | 1) + +#define MT8365_PIN_58_SCL0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT8365_PIN_58_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(58) | 1) + +#define MT8365_PIN_59_SDA1__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT8365_PIN_59_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(59) | 1) +#define MT8365_PIN_59_SDA1__FUNC_USB_SDA (MTK_PIN_NO(59) | 6) +#define MT8365_PIN_59_SDA1__FUNC_DBG_SDA (MTK_PIN_NO(59) | 7) + +#define MT8365_PIN_60_SCL1__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT8365_PIN_60_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(60) | 1) +#define MT8365_PIN_60_SCL1__FUNC_USB_SCL (MTK_PIN_NO(60) | 6) +#define MT8365_PIN_60_SCL1__FUNC_DBG_SCL (MTK_PIN_NO(60) | 7) + +#define MT8365_PIN_61_SDA2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT8365_PIN_61_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(61) | 1) + +#define MT8365_PIN_62_SCL2__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT8365_PIN_62_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(62) | 1) + +#define MT8365_PIN_63_SDA3__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT8365_PIN_63_SDA3__FUNC_SDA3_0 (MTK_PIN_NO(63) | 1) + +#define MT8365_PIN_64_SCL3__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT8365_PIN_64_SCL3__FUNC_SCL3_0 (MTK_PIN_NO(64) | 1) + +#define MT8365_PIN_65_CMMCLK0__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK0 (MTK_PIN_NO(65) | 1) +#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK1 (MTK_PIN_NO(65) | 2) +#define MT8365_PIN_65_CMMCLK0__FUNC_DBG_MON_A28 (MTK_PIN_NO(65) | 7) + +#define MT8365_PIN_66_CMMCLK1__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK1 (MTK_PIN_NO(66) | 1) +#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK0 (MTK_PIN_NO(66) | 2) +#define MT8365_PIN_66_CMMCLK1__FUNC_DBG_MON_B2 (MTK_PIN_NO(66) | 7) + +#define MT8365_PIN_67_CMPCLK__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT8365_PIN_67_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(67) | 1) +#define MT8365_PIN_67_CMPCLK__FUNC_ANT_SEL0 (MTK_PIN_NO(67) | 2) +#define MT8365_PIN_67_CMPCLK__FUNC_TDM_RX_BCK (MTK_PIN_NO(67) | 4) +#define MT8365_PIN_67_CMPCLK__FUNC_I2S0_BCK (MTK_PIN_NO(67) | 5) +#define MT8365_PIN_67_CMPCLK__FUNC_DBG_MON_B3 (MTK_PIN_NO(67) | 7) + +#define MT8365_PIN_68_CMDAT0__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT8365_PIN_68_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(68) | 1) +#define MT8365_PIN_68_CMDAT0__FUNC_ANT_SEL1 (MTK_PIN_NO(68) | 2) +#define MT8365_PIN_68_CMDAT0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(68) | 4) +#define MT8365_PIN_68_CMDAT0__FUNC_I2S0_LRCK (MTK_PIN_NO(68) | 5) +#define MT8365_PIN_68_CMDAT0__FUNC_DBG_MON_B4 (MTK_PIN_NO(68) | 7) + +#define MT8365_PIN_69_CMDAT1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT8365_PIN_69_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(69) | 1) +#define MT8365_PIN_69_CMDAT1__FUNC_ANT_SEL2 (MTK_PIN_NO(69) | 2) +#define MT8365_PIN_69_CMDAT1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(69) | 3) +#define MT8365_PIN_69_CMDAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(69) | 4) +#define MT8365_PIN_69_CMDAT1__FUNC_I2S0_MCK (MTK_PIN_NO(69) | 5) +#define MT8365_PIN_69_CMDAT1__FUNC_DBG_MON_B5 (MTK_PIN_NO(69) | 7) + +#define MT8365_PIN_70_CMDAT2__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT8365_PIN_70_CMDAT2__FUNC_CMDAT2 (MTK_PIN_NO(70) | 1) +#define MT8365_PIN_70_CMDAT2__FUNC_ANT_SEL3 (MTK_PIN_NO(70) | 2) +#define MT8365_PIN_70_CMDAT2__FUNC_TDM_RX_DI (MTK_PIN_NO(70) | 4) +#define MT8365_PIN_70_CMDAT2__FUNC_I2S0_DI (MTK_PIN_NO(70) | 5) +#define MT8365_PIN_70_CMDAT2__FUNC_DBG_MON_B6 (MTK_PIN_NO(70) | 7) + +#define MT8365_PIN_71_CMDAT3__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT8365_PIN_71_CMDAT3__FUNC_CMDAT3 (MTK_PIN_NO(71) | 1) +#define MT8365_PIN_71_CMDAT3__FUNC_ANT_SEL4 (MTK_PIN_NO(71) | 2) +#define MT8365_PIN_71_CMDAT3__FUNC_DBG_MON_B7 (MTK_PIN_NO(71) | 7) + +#define MT8365_PIN_72_CMDAT4__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT8365_PIN_72_CMDAT4__FUNC_CMDAT4 (MTK_PIN_NO(72) | 1) +#define MT8365_PIN_72_CMDAT4__FUNC_ANT_SEL5 (MTK_PIN_NO(72) | 2) +#define MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK (MTK_PIN_NO(72) | 5) +#define MT8365_PIN_72_CMDAT4__FUNC_DBG_MON_B8 (MTK_PIN_NO(72) | 7) + +#define MT8365_PIN_73_CMDAT5__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT8365_PIN_73_CMDAT5__FUNC_CMDAT5 (MTK_PIN_NO(73) | 1) +#define MT8365_PIN_73_CMDAT5__FUNC_ANT_SEL6 (MTK_PIN_NO(73) | 2) +#define MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK (MTK_PIN_NO(73) | 5) +#define MT8365_PIN_73_CMDAT5__FUNC_DBG_MON_B9 (MTK_PIN_NO(73) | 7) + +#define MT8365_PIN_74_CMDAT6__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define MT8365_PIN_74_CMDAT6__FUNC_CMDAT6 (MTK_PIN_NO(74) | 1) +#define MT8365_PIN_74_CMDAT6__FUNC_ANT_SEL7 (MTK_PIN_NO(74) | 2) +#define MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK (MTK_PIN_NO(74) | 5) +#define MT8365_PIN_74_CMDAT6__FUNC_DBG_MON_B10 (MTK_PIN_NO(74) | 7) + +#define MT8365_PIN_75_CMDAT7__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define MT8365_PIN_75_CMDAT7__FUNC_CMDAT7 (MTK_PIN_NO(75) | 1) +#define MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO (MTK_PIN_NO(75) | 5) +#define MT8365_PIN_75_CMDAT7__FUNC_DBG_MON_B11 (MTK_PIN_NO(75) | 7) + +#define MT8365_PIN_76_CMDAT8__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define MT8365_PIN_76_CMDAT8__FUNC_CMDAT8 (MTK_PIN_NO(76) | 1) +#define MT8365_PIN_76_CMDAT8__FUNC_PCM_CLK (MTK_PIN_NO(76) | 5) +#define MT8365_PIN_76_CMDAT8__FUNC_DBG_MON_A29 (MTK_PIN_NO(76) | 7) + +#define MT8365_PIN_77_CMDAT9__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT8365_PIN_77_CMDAT9__FUNC_CMDAT9 (MTK_PIN_NO(77) | 1) +#define MT8365_PIN_77_CMDAT9__FUNC_PCM_SYNC (MTK_PIN_NO(77) | 5) +#define MT8365_PIN_77_CMDAT9__FUNC_DBG_MON_A30 (MTK_PIN_NO(77) | 7) + +#define MT8365_PIN_78_CMHSYNC__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT8365_PIN_78_CMHSYNC__FUNC_CMHSYNC (MTK_PIN_NO(78) | 1) +#define MT8365_PIN_78_CMHSYNC__FUNC_PCM_RX (MTK_PIN_NO(78) | 5) +#define MT8365_PIN_78_CMHSYNC__FUNC_DBG_MON_A31 (MTK_PIN_NO(78) | 7) + +#define MT8365_PIN_79_CMVSYNC__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define MT8365_PIN_79_CMVSYNC__FUNC_CMVSYNC (MTK_PIN_NO(79) | 1) +#define MT8365_PIN_79_CMVSYNC__FUNC_PCM_TX (MTK_PIN_NO(79) | 5) +#define MT8365_PIN_79_CMVSYNC__FUNC_DBG_MON_A32 (MTK_PIN_NO(79) | 7) + +#define MT8365_PIN_80_MSDC2_CMD__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(80) | 1) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_TDM_TX_LRCK (MTK_PIN_NO(80) | 2) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_UTXD1 (MTK_PIN_NO(80) | 3) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_DPI_D19 (MTK_PIN_NO(80) | 4) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_UDI_TMS_XI (MTK_PIN_NO(80) | 5) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(80) | 6) + +#define MT8365_PIN_81_MSDC2_CLK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(81) | 1) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_TDM_TX_BCK (MTK_PIN_NO(81) | 2) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_URXD1 (MTK_PIN_NO(81) | 3) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_DPI_D20 (MTK_PIN_NO(81) | 4) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_UDI_TCK_XI (MTK_PIN_NO(81) | 5) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(81) | 6) + +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(82) | 2) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UTXD2 (MTK_PIN_NO(82) | 3) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_DPI_D21 (MTK_PIN_NO(82) | 4) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UDI_TDI_XI (MTK_PIN_NO(82) | 5) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(82) | 6) + +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(83) | 1) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(83) | 2) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_URXD2 (MTK_PIN_NO(83) | 3) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_DPI_D22 (MTK_PIN_NO(83) | 4) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_UDI_TDO (MTK_PIN_NO(83) | 5) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(83) | 6) + +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(84) | 1) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(84) | 2) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_PWM_A (MTK_PIN_NO(84) | 3) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(84) | 4) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_UDI_NTRST_XI (MTK_PIN_NO(84) | 5) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(84) | 6) + +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(85) | 1) +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(85) | 2) +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_PWM_B (MTK_PIN_NO(85) | 3) +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(85) | 5) + +#define MT8365_PIN_86_MSDC2_DSL__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define MT8365_PIN_86_MSDC2_DSL__FUNC_MSDC2_DSL (MTK_PIN_NO(86) | 1) +#define MT8365_PIN_86_MSDC2_DSL__FUNC_TDM_TX_MCK (MTK_PIN_NO(86) | 2) +#define MT8365_PIN_86_MSDC2_DSL__FUNC_PWM_C (MTK_PIN_NO(86) | 3) + +#define MT8365_PIN_87_MSDC1_CMD__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(87) | 1) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(87) | 2) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_DFD_TMS_XI (MTK_PIN_NO(87) | 3) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_APU_JTAG_TMS (MTK_PIN_NO(87) | 4) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_MCU_SPM_TMS (MTK_PIN_NO(87) | 5) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_DSP_JMS (MTK_PIN_NO(87) | 6) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(87) | 7) + +#define MT8365_PIN_88_MSDC1_CLK__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(88) | 1) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(88) | 2) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 3) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(88) | 4) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(88) | 5) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(88) | 6) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(88) | 7) + +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(89) | 1) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_PWM_C (MTK_PIN_NO(89) | 2) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_DFD_TDI_XI (MTK_PIN_NO(89) | 3) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_APU_JTAG_TDI (MTK_PIN_NO(89) | 4) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MCU_SPM_TDI (MTK_PIN_NO(89) | 5) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_CONN_DSP_JDI (MTK_PIN_NO(89) | 6) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(89) | 7) + +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(90) | 1) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_SPDIF_IN (MTK_PIN_NO(90) | 2) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_DFD_TDO (MTK_PIN_NO(90) | 3) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_APU_JTAG_TDO (MTK_PIN_NO(90) | 4) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MCU_SPM_TDO (MTK_PIN_NO(90) | 5) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_CONN_DSP_JDO (MTK_PIN_NO(90) | 6) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(90) | 7) + +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(91) | 1) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_SPDIF_OUT (MTK_PIN_NO(91) | 2) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_DFD_NTRST_XI (MTK_PIN_NO(91) | 3) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_APU_JTAG_TRST (MTK_PIN_NO(91) | 4) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(91) | 5) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(91) | 6) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(91) | 7) + +#define MT8365_PIN_92_MSDC1_DAT3__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(92) | 1) +#define MT8365_PIN_92_MSDC1_DAT3__FUNC_IRRX (MTK_PIN_NO(92) | 2) +#define MT8365_PIN_92_MSDC1_DAT3__FUNC_PWM_A (MTK_PIN_NO(92) | 3) + +#define MT8365_PIN_93_MSDC0_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(93) | 1) +#define MT8365_PIN_93_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(93) | 2) + +#define MT8365_PIN_94_MSDC0_DAT6__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(94) | 1) +#define MT8365_PIN_94_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(94) | 2) + +#define MT8365_PIN_95_MSDC0_DAT5__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(95) | 1) +#define MT8365_PIN_95_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(95) | 2) + +#define MT8365_PIN_96_MSDC0_DAT4__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(96) | 1) +#define MT8365_PIN_96_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(96) | 2) + +#define MT8365_PIN_97_MSDC0_RSTB__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(97) | 1) +#define MT8365_PIN_97_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(97) | 2) + +#define MT8365_PIN_98_MSDC0_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(98) | 1) +#define MT8365_PIN_98_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(98) | 2) + +#define MT8365_PIN_99_MSDC0_CLK__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(99) | 1) +#define MT8365_PIN_99_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(99) | 2) + +#define MT8365_PIN_100_MSDC0_DAT3__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(100) | 1) +#define MT8365_PIN_100_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(100) | 2) + +#define MT8365_PIN_101_MSDC0_DAT2__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(101) | 1) +#define MT8365_PIN_101_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(101) | 2) + +#define MT8365_PIN_102_MSDC0_DAT1__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(102) | 1) +#define MT8365_PIN_102_MSDC0_DAT1__FUNC_NDQS (MTK_PIN_NO(102) | 2) + +#define MT8365_PIN_103_MSDC0_DAT0__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(103) | 1) +#define MT8365_PIN_103_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(103) | 2) + +#define MT8365_PIN_104_MSDC0_DSL__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(104) | 1) + +#define MT8365_PIN_105_NCLE__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT8365_PIN_105_NCLE__FUNC_NCLE (MTK_PIN_NO(105) | 1) +#define MT8365_PIN_105_NCLE__FUNC_TDM_RX_MCK (MTK_PIN_NO(105) | 2) +#define MT8365_PIN_105_NCLE__FUNC_DBG_MON_B12 (MTK_PIN_NO(105) | 7) + +#define MT8365_PIN_106_NCEB1__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT8365_PIN_106_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(106) | 1) +#define MT8365_PIN_106_NCEB1__FUNC_TDM_RX_BCK (MTK_PIN_NO(106) | 2) +#define MT8365_PIN_106_NCEB1__FUNC_DBG_MON_B13 (MTK_PIN_NO(106) | 7) + +#define MT8365_PIN_107_NCEB0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT8365_PIN_107_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(107) | 1) +#define MT8365_PIN_107_NCEB0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(107) | 2) +#define MT8365_PIN_107_NCEB0__FUNC_DBG_MON_B14 (MTK_PIN_NO(107) | 7) + +#define MT8365_PIN_108_NREB__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT8365_PIN_108_NREB__FUNC_NREB (MTK_PIN_NO(108) | 1) +#define MT8365_PIN_108_NREB__FUNC_TDM_RX_DI (MTK_PIN_NO(108) | 2) +#define MT8365_PIN_108_NREB__FUNC_DBG_MON_B15 (MTK_PIN_NO(108) | 7) + +#define MT8365_PIN_109_NRNB__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT8365_PIN_109_NRNB__FUNC_NRNB (MTK_PIN_NO(109) | 1) +#define MT8365_PIN_109_NRNB__FUNC_TSF_IN (MTK_PIN_NO(109) | 2) +#define MT8365_PIN_109_NRNB__FUNC_DBG_MON_B16 (MTK_PIN_NO(109) | 7) + +#define MT8365_PIN_110_PCM_CLK__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT8365_PIN_110_PCM_CLK__FUNC_PCM_CLK (MTK_PIN_NO(110) | 1) +#define MT8365_PIN_110_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(110) | 2) +#define MT8365_PIN_110_PCM_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 3) +#define MT8365_PIN_110_PCM_CLK__FUNC_SPDIF_IN (MTK_PIN_NO(110) | 4) +#define MT8365_PIN_110_PCM_CLK__FUNC_DPI_D15 (MTK_PIN_NO(110) | 5) + +#define MT8365_PIN_111_PCM_SYNC__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT8365_PIN_111_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(111) | 1) +#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(111) | 2) +#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 3) +#define MT8365_PIN_111_PCM_SYNC__FUNC_SPDIF_OUT (MTK_PIN_NO(111) | 4) +#define MT8365_PIN_111_PCM_SYNC__FUNC_DPI_D16 (MTK_PIN_NO(111) | 5) + +#define MT8365_PIN_112_PCM_RX__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT8365_PIN_112_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(112) | 1) +#define MT8365_PIN_112_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(112) | 2) +#define MT8365_PIN_112_PCM_RX__FUNC_I2S3_MCK (MTK_PIN_NO(112) | 3) +#define MT8365_PIN_112_PCM_RX__FUNC_IRRX (MTK_PIN_NO(112) | 4) +#define MT8365_PIN_112_PCM_RX__FUNC_DPI_D17 (MTK_PIN_NO(112) | 5) + +#define MT8365_PIN_113_PCM_TX__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT8365_PIN_113_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(113) | 1) +#define MT8365_PIN_113_PCM_TX__FUNC_I2S0_MCK (MTK_PIN_NO(113) | 2) +#define MT8365_PIN_113_PCM_TX__FUNC_I2S3_DO (MTK_PIN_NO(113) | 3) +#define MT8365_PIN_113_PCM_TX__FUNC_PWM_B (MTK_PIN_NO(113) | 4) +#define MT8365_PIN_113_PCM_TX__FUNC_DPI_D18 (MTK_PIN_NO(113) | 5) + +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(114) | 1) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S1_DO (MTK_PIN_NO(114) | 2) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S2_DI (MTK_PIN_NO(114) | 3) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(114) | 4) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(114) | 5) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_SPDIF_IN (MTK_PIN_NO(114) | 6) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_DBG_MON_B17 (MTK_PIN_NO(114) | 7) + +#define MT8365_PIN_115_I2S_LRCK__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(115) | 1) +#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(115) | 2) +#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S2_LRCK (MTK_PIN_NO(115) | 3) +#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(115) | 4) +#define MT8365_PIN_115_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(115) | 5) +#define MT8365_PIN_115_I2S_LRCK__FUNC_SPDIF_OUT (MTK_PIN_NO(115) | 6) +#define MT8365_PIN_115_I2S_LRCK__FUNC_DBG_MON_B18 (MTK_PIN_NO(115) | 7) + +#define MT8365_PIN_116_I2S_BCK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT8365_PIN_116_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(116) | 1) +#define MT8365_PIN_116_I2S_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(116) | 2) +#define MT8365_PIN_116_I2S_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(116) | 3) +#define MT8365_PIN_116_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(116) | 4) +#define MT8365_PIN_116_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(116) | 5) +#define MT8365_PIN_116_I2S_BCK__FUNC_IRRX (MTK_PIN_NO(116) | 6) +#define MT8365_PIN_116_I2S_BCK__FUNC_DBG_MON_B19 (MTK_PIN_NO(116) | 7) + +#define MT8365_PIN_117_DMIC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK (MTK_PIN_NO(117) | 1) +#define MT8365_PIN_117_DMIC0_CLK__FUNC_I2S2_BCK (MTK_PIN_NO(117) | 2) +#define MT8365_PIN_117_DMIC0_CLK__FUNC_DBG_MON_B20 (MTK_PIN_NO(117) | 7) + +#define MT8365_PIN_118_DMIC0_DAT0__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0 (MTK_PIN_NO(118) | 1) +#define MT8365_PIN_118_DMIC0_DAT0__FUNC_I2S2_DI (MTK_PIN_NO(118) | 2) +#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DBG_MON_B21 (MTK_PIN_NO(118) | 7) + +#define MT8365_PIN_119_DMIC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1 (MTK_PIN_NO(119) | 1) +#define MT8365_PIN_119_DMIC0_DAT1__FUNC_I2S2_LRCK (MTK_PIN_NO(119) | 2) +#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DBG_MON_B22 (MTK_PIN_NO(119) | 7) + +#define MT8365_PIN_120_DMIC1_CLK__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT8365_PIN_120_DMIC1_CLK__FUNC_DMIC1_CLK (MTK_PIN_NO(120) | 1) +#define MT8365_PIN_120_DMIC1_CLK__FUNC_I2S2_MCK (MTK_PIN_NO(120) | 2) +#define MT8365_PIN_120_DMIC1_CLK__FUNC_DBG_MON_B23 (MTK_PIN_NO(120) | 7) + +#define MT8365_PIN_121_DMIC1_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DMIC1_DAT0 (MTK_PIN_NO(121) | 1) +#define MT8365_PIN_121_DMIC1_DAT0__FUNC_I2S1_BCK (MTK_PIN_NO(121) | 2) +#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DBG_MON_B24 (MTK_PIN_NO(121) | 7) + +#define MT8365_PIN_122_DMIC1_DAT1__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DMIC1_DAT1 (MTK_PIN_NO(122) | 1) +#define MT8365_PIN_122_DMIC1_DAT1__FUNC_I2S1_LRCK (MTK_PIN_NO(122) | 2) +#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DBG_MON_B25 (MTK_PIN_NO(122) | 7) + +#define MT8365_PIN_123_DMIC2_CLK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT8365_PIN_123_DMIC2_CLK__FUNC_DMIC2_CLK (MTK_PIN_NO(123) | 1) +#define MT8365_PIN_123_DMIC2_CLK__FUNC_I2S1_MCK (MTK_PIN_NO(123) | 2) +#define MT8365_PIN_123_DMIC2_CLK__FUNC_DBG_MON_B26 (MTK_PIN_NO(123) | 7) + +#define MT8365_PIN_124_DMIC2_DAT0__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DMIC2_DAT0 (MTK_PIN_NO(124) | 1) +#define MT8365_PIN_124_DMIC2_DAT0__FUNC_I2S1_DO (MTK_PIN_NO(124) | 2) +#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DBG_MON_B27 (MTK_PIN_NO(124) | 7) + +#define MT8365_PIN_125_DMIC2_DAT1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DMIC2_DAT1 (MTK_PIN_NO(125) | 1) +#define MT8365_PIN_125_DMIC2_DAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(125) | 2) +#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DBG_MON_B28 (MTK_PIN_NO(125) | 7) + +#define MT8365_PIN_126_DMIC3_CLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define MT8365_PIN_126_DMIC3_CLK__FUNC_DMIC3_CLK (MTK_PIN_NO(126) | 1) +#define MT8365_PIN_126_DMIC3_CLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(126) | 2) + +#define MT8365_PIN_127_DMIC3_DAT0__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define MT8365_PIN_127_DMIC3_DAT0__FUNC_DMIC3_DAT0 (MTK_PIN_NO(127) | 1) +#define MT8365_PIN_127_DMIC3_DAT0__FUNC_TDM_RX_DI (MTK_PIN_NO(127) | 2) + +#define MT8365_PIN_128_DMIC3_DAT1__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define MT8365_PIN_128_DMIC3_DAT1__FUNC_DMIC3_DAT1 (MTK_PIN_NO(128) | 1) +#define MT8365_PIN_128_DMIC3_DAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(128) | 2) +#define MT8365_PIN_128_DMIC3_DAT1__FUNC_VAD_CLK (MTK_PIN_NO(128) | 3) + +#define MT8365_PIN_129_TDM_TX_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define MT8365_PIN_129_TDM_TX_BCK__FUNC_TDM_TX_BCK (MTK_PIN_NO(129) | 1) +#define MT8365_PIN_129_TDM_TX_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(129) | 2) +#define MT8365_PIN_129_TDM_TX_BCK__FUNC_ckmon1_ck (MTK_PIN_NO(129) | 3) + +#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_TDM_TX_LRCK (MTK_PIN_NO(130) | 1) +#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(130) | 2) +#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_ckmon2_ck (MTK_PIN_NO(130) | 3) + +#define MT8365_PIN_131_TDM_TX_MCK__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define MT8365_PIN_131_TDM_TX_MCK__FUNC_TDM_TX_MCK (MTK_PIN_NO(131) | 1) +#define MT8365_PIN_131_TDM_TX_MCK__FUNC_I2S3_MCK (MTK_PIN_NO(131) | 2) +#define MT8365_PIN_131_TDM_TX_MCK__FUNC_ckmon3_ck (MTK_PIN_NO(131) | 3) + +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(132) | 1) +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_I2S3_DO (MTK_PIN_NO(132) | 2) +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_ckmon4_ck (MTK_PIN_NO(132) | 3) +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_DBG_MON_B29 (MTK_PIN_NO(132) | 7) + +#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(133) | 1) +#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_DBG_MON_B30 (MTK_PIN_NO(133) | 7) + +#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(134) | 1) +#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_DBG_MON_B31 (MTK_PIN_NO(134) | 7) + +#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(135) | 1) +#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_DBG_MON_B32 (MTK_PIN_NO(135) | 7) + +#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_CONN_TOP_CLK (MTK_PIN_NO(136) | 1) + +#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_CONN_TOP_DATA (MTK_PIN_NO(137) | 1) + +#define MT8365_PIN_138_CONN_HRST_B__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define MT8365_PIN_138_CONN_HRST_B__FUNC_CONN_HRST_B (MTK_PIN_NO(138) | 1) + +#define MT8365_PIN_139_CONN_WB_PTA__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define MT8365_PIN_139_CONN_WB_PTA__FUNC_CONN_WB_PTA (MTK_PIN_NO(139) | 1) + +#define MT8365_PIN_140_CONN_BT_CLK__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define MT8365_PIN_140_CONN_BT_CLK__FUNC_CONN_BT_CLK (MTK_PIN_NO(140) | 1) + +#define MT8365_PIN_141_CONN_BT_DATA__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define MT8365_PIN_141_CONN_BT_DATA__FUNC_CONN_BT_DATA (MTK_PIN_NO(141) | 1) + +#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(142) | 1) + +#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(143) | 1) + +#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(144) | 1) + +#endif /* __MT8365_PINFUNC_H */ diff --git a/include/dt-bindings/pmic/max77663.h b/include/dt-bindings/pmic/max77663.h new file mode 100644 index 00000000000..ee169a83e3b --- /dev/null +++ b/include/dt-bindings/pmic/max77663.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef _DT_BINDINGS_MAX77663_H_ +#define _DT_BINDINGS_MAX77663_H_ + +/* + * MAX77663 has 8 GPIO (0 to 7) and 3 KEYS + * KEYS are appended after GPIOs + */ + +#define EN0 10 +#define ACOK 9 +#define LID 8 + +#endif diff --git a/include/dt-bindings/power/mediatek,mt8365-power.h b/include/dt-bindings/power/mediatek,mt8365-power.h new file mode 100644 index 00000000000..e6cfd0ec787 --- /dev/null +++ b/include/dt-bindings/power/mediatek,mt8365-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H +#define _DT_BINDINGS_POWER_MT8365_POWER_H + +#define MT8365_POWER_DOMAIN_MM 0 +#define MT8365_POWER_DOMAIN_CONN 1 +#define MT8365_POWER_DOMAIN_MFG 2 +#define MT8365_POWER_DOMAIN_AUDIO 3 +#define MT8365_POWER_DOMAIN_CAM 4 +#define MT8365_POWER_DOMAIN_DSP 5 +#define MT8365_POWER_DOMAIN_VDEC 6 +#define MT8365_POWER_DOMAIN_VENC 7 +#define MT8365_POWER_DOMAIN_APU 8 + +#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */ diff --git a/include/efi_loader.h b/include/efi_loader.h index 664dae28f88..34e7fbbf184 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -90,6 +90,8 @@ efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len); * back to u-boot world */ void efi_restore_gd(void); +/* Call this to unset the current device name */ +void efi_clear_bootdev(void); /* Call this to set the current device name */ void efi_set_bootdev(const char *dev, const char *devnr, const char *path, void *buffer, size_t buffer_size); @@ -114,6 +116,7 @@ static inline efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len) /* No loader configured, stub out EFI_ENTRY */ static inline void efi_restore_gd(void) { } +static inline void efi_clear_bootdev(void) { } static inline void efi_set_bootdev(const char *dev, const char *devnr, const char *path, void *buffer, size_t buffer_size) { } @@ -527,14 +530,21 @@ efi_status_t efi_bootmgr_get_unused_bootoption(u16 *buf, efi_status_t efi_bootmgr_update_media_device_boot_option(void); /* Delete selected boot option */ efi_status_t efi_bootmgr_delete_boot_option(u16 boot_index); +/* Invoke EFI boot manager */ +efi_status_t efi_bootmgr_run(void *fdt); /* search the boot option index in BootOrder */ bool efi_search_bootorder(u16 *bootorder, efi_uintn_t num, u32 target, u32 *index); /* Set up console modes */ void efi_setup_console_size(void); +/* Set up load options from environment variable */ +efi_status_t efi_env_set_load_options(efi_handle_t handle, const char *env_var, + u16 **load_options); /* Install device tree */ efi_status_t efi_install_fdt(void *fdt); /* Run loaded UEFI image */ efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size); +/* Run loaded UEFI image with given fdt */ +efi_status_t efi_binary_run(void *image, size_t size, void *fdt); /* Initialize variable services */ efi_status_t efi_init_variables(void); /* Notify ExitBootServices() is called */ @@ -879,14 +889,12 @@ efi_status_t __efi_runtime EFIAPI efi_get_time( efi_status_t __efi_runtime EFIAPI efi_set_time(struct efi_time *time); -#ifdef CONFIG_CMD_BOOTEFI_SELFTEST /* * Entry point for the tests of the EFI API. * It is called by 'bootefi selftest' */ efi_status_t EFIAPI efi_selftest(efi_handle_t image_handle, struct efi_system_table *systab); -#endif efi_status_t EFIAPI efi_get_variable(u16 *variable_name, const efi_guid_t *vendor, u32 *attributes, diff --git a/include/env/ti/ti_common.env b/include/env/ti/ti_common.env index f5d84216e3c..f0f89a22876 100644 --- a/include/env/ti/ti_common.env +++ b/include/env/ti/ti_common.env @@ -25,7 +25,10 @@ run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring} bootcmd_ti_mmc= run findfdt; run init_${boot}; #if CONFIG_CMD_REMOTEPROC - run main_cpsw0_qsgmii_phyinit; run boot_rprocs; + if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1; + then run main_cpsw0_qsgmii_phyinit; + fi + run boot_rprocs; #endif if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_fit_overlaystring; run run_fit; diff --git a/include/env_internal.h b/include/env_internal.h index 5c289d67f90..cbd1ef3e914 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -15,7 +15,6 @@ #ifndef _ENV_INTERNAL_H_ #define _ENV_INTERNAL_H_ -#include <linux/kconfig.h> /************************************************************************** * diff --git a/include/getopt.h b/include/getopt.h index 6f5811e64be..8645082da2a 100644 --- a/include/getopt.h +++ b/include/getopt.h @@ -9,6 +9,8 @@ #ifndef __GETOPT_H #define __GETOPT_H +#include <stdbool.h> + /** * struct getopt_state - Saved state across getopt() calls */ diff --git a/include/iommu.h b/include/iommu.h index cf9719c5e91..b8ba0b8e707 100644 --- a/include/iommu.h +++ b/include/iommu.h @@ -5,6 +5,15 @@ struct udevice; struct iommu_ops { /** + * init() - Connect a device to it's IOMMU, called before probe() + * The iommu device can be fetched through dev->iommu + * + * @iommu_dev: IOMMU device + * @dev: Device to connect + * @return 0 if OK, -errno on error + */ + int (*connect)(struct udevice *dev); + /** * map() - map DMA memory * * @dev: device for which to map DMA memory diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h index 45307f51c10..a692f5dfb37 100644 --- a/include/linux/immap_qe.h +++ b/include/linux/immap_qe.h @@ -11,6 +11,8 @@ #ifndef __IMMAP_QE_H__ #define __IMMAP_QE_H__ +#include <config.h> + #ifdef CONFIG_MPC83xx #if defined(CONFIG_ARCH_MPC8360) #define QE_MURAM_SIZE 0xc000UL diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 6d68514e07a..6f479fa5adc 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -250,6 +250,7 @@ extern const struct spinand_manufacturer micron_spinand_manufacturer; extern const struct spinand_manufacturer paragon_spinand_manufacturer; extern const struct spinand_manufacturer toshiba_spinand_manufacturer; extern const struct spinand_manufacturer winbond_spinand_manufacturer; +extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; /** * struct spinand_op_variants - SPI NAND operation variants diff --git a/include/mapmem.h b/include/mapmem.h index 2134c8004d9..bb68b4c11af 100644 --- a/include/mapmem.h +++ b/include/mapmem.h @@ -13,6 +13,8 @@ # ifdef CONFIG_ARCH_MAP_SYSMEM #include <asm/io.h> # else +#include <linux/types.h> + static inline void *map_sysmem(phys_addr_t paddr, unsigned long len) { return (void *)(uintptr_t)paddr; diff --git a/include/memalign.h b/include/memalign.h index f67f0a74f2e..eaa9f6b5cbd 100644 --- a/include/memalign.h +++ b/include/memalign.h @@ -11,6 +11,7 @@ * is used to align DMA buffers. */ #ifndef __ASSEMBLY__ +#include <linux/kernel.h> #include <asm/cache.h> #include <malloc.h> diff --git a/include/net6.h b/include/net6.h index 1e766aa7209..1ed989e584a 100644 --- a/include/net6.h +++ b/include/net6.h @@ -12,6 +12,7 @@ #include <net.h> #include <linux/ctype.h> +#include <linux/errno.h> /* struct in6_addr - 128 bits long IPv6 address */ struct in6_addr { diff --git a/include/power/max77663.h b/include/power/max77663.h index b3ae3dabf46..fcb5916f27e 100644 --- a/include/power/max77663.h +++ b/include/power/max77663.h @@ -13,6 +13,7 @@ #define MAX77663_LDO_DRIVER "max77663_ldo" #define MAX77663_SD_DRIVER "max77663_sd" #define MAX77663_RST_DRIVER "max77663_rst" +#define MAX77663_GPIO_DRIVER "max77663_gpio" /* Step-Down (SD) Regulator calculations */ #define SD_STATUS_MASK 0x30 diff --git a/include/power/palmas.h b/include/power/palmas.h index 0a612052f01..94c99dd4113 100644 --- a/include/power/palmas.h +++ b/include/power/palmas.h @@ -15,6 +15,7 @@ struct palmas_priv { #define PALMAS_LDO_DRIVER "palmas_ldo" #define PALMAS_SMPS_DRIVER "palmas_smps" #define PALMAS_RST_DRIVER "palmas_rst" +#define PALMAS_GPIO_DRIVER "palmas_gpio" #define PALMAS_SMPS_VOLT_MASK 0x7F #define PALMAS_SMPS_RANGE_MASK 0x80 @@ -35,3 +36,14 @@ struct palmas_priv { #define DEV_OFF 0x00 #define PALMAS_INT3_MASK 0x1B #define MASK_VBUS BIT(7) + +/* second chip */ +#define PALMAS_GPIO_DATA_IN 0x80 +#define PALMAS_GPIO_DATA_DIR 0x81 +#define PALMAS_GPIO_DATA_OUT 0x82 +#define PALMAS_GPIO_DEBOUNCE_EN 0x83 +#define PALMAS_GPIO_CLEAR_DATA_OUT 0x84 +#define PALMAS_GPIO_SET_DATA_OUT 0x85 +#define PALMAS_PU_PD_GPIO_CTRL1 0x86 +#define PALMAS_PU_PD_GPIO_CTRL2 0x87 +#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x88 diff --git a/include/rtc.h b/include/rtc.h index b6fdbb60dc2..22f6d370591 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -16,6 +16,7 @@ #include <bcd.h> #include <rtc_def.h> #include <linux/errno.h> +#include <linux/types.h> typedef int64_t time64_t; struct udevice; diff --git a/include/system-constants.h b/include/system-constants.h index d688629f119..e09fc418a47 100644 --- a/include/system-constants.h +++ b/include/system-constants.h @@ -3,6 +3,8 @@ #ifndef __SYSTEM_CONSTANTS_H__ #define __SYSTEM_CONSTANTS_H__ +#include <config.h> + /* * The most common case for our initial stack pointer address is to * say that we have defined a static intiial ram address location and diff --git a/include/u-boot/ecdsa.h b/include/u-boot/ecdsa.h index 6e0269e3aed..53490c6b287 100644 --- a/include/u-boot/ecdsa.h +++ b/include/u-boot/ecdsa.h @@ -8,7 +8,6 @@ #include <errno.h> #include <image.h> -#include <linux/kconfig.h> /** * crypto_algo API impementation for ECDSA; diff --git a/lib/Kconfig b/lib/Kconfig index 9ae846ea5f7..37ac14f7bab 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -1002,7 +1002,7 @@ config GENERATE_SMBIOS_TABLE Check http://www.dmtf.org/standards/smbios for details. - See also SMBIOS_SYSINFO which allows SMBIOS values to be provided in + See also SYSINFO_SMBIOS which allows SMBIOS values to be provided in the devicetree. endmenu diff --git a/lib/abuf.c b/lib/abuf.c index ce2cff53dc9..937c3df351e 100644 --- a/lib/abuf.c +++ b/lib/abuf.c @@ -7,7 +7,6 @@ */ #ifndef USE_HOSTCC -#include <common.h> #include <malloc.h> #include <mapmem.h> #include <string.h> diff --git a/lib/acpi/acpi.c b/lib/acpi/acpi.c index f21e5094615..939a638bb5b 100644 --- a/lib/acpi/acpi.c +++ b/lib/acpi/acpi.c @@ -5,7 +5,6 @@ * Copyright 2023 Google LLC */ -#include <common.h> #include <mapmem.h> #include <acpi/acpi_table.h> #include <asm/global_data.h> diff --git a/lib/acpi/acpi_device.c b/lib/acpi/acpi_device.c index 1b838fdbd6f..ed94194346d 100644 --- a/lib/acpi/acpi_device.c +++ b/lib/acpi/acpi_device.c @@ -6,7 +6,6 @@ * Mostly taken from coreboot file of the same name */ -#include <common.h> #include <dm.h> #include <irq.h> #include <log.h> diff --git a/lib/acpi/acpi_dp.c b/lib/acpi/acpi_dp.c index 7e3e3259d8d..6733809986a 100644 --- a/lib/acpi/acpi_dp.c +++ b/lib/acpi/acpi_dp.c @@ -6,7 +6,6 @@ * Mostly taken from coreboot file acpi_device.c */ -#include <common.h> #include <dm.h> #include <log.h> #include <malloc.h> diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index a8d4b470001..e74522e9972 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -5,7 +5,6 @@ * Copyright 2019 Google LLC */ -#include <common.h> #include <dm.h> #include <cpu.h> #include <log.h> diff --git a/lib/acpi/acpi_writer.c b/lib/acpi/acpi_writer.c index 946f90e8e7b..a8dc207557b 100644 --- a/lib/acpi/acpi_writer.c +++ b/lib/acpi/acpi_writer.c @@ -7,13 +7,13 @@ #define LOG_CATEGORY LOGC_ACPI -#include <common.h> #include <log.h> #include <malloc.h> #include <mapmem.h> #include <acpi/acpi_table.h> #include <asm/global_data.h> #include <dm/acpi.h> +#include <linux/errno.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c index e395226e3de..b95cabb9149 100644 --- a/lib/acpi/acpigen.c +++ b/lib/acpi/acpigen.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY LOGC_ACPI -#include <common.h> #include <dm.h> #include <log.h> #include <uuid.h> diff --git a/lib/acpi/base.c b/lib/acpi/base.c index 26bf0cb8d30..07b53e0c561 100644 --- a/lib/acpi/base.c +++ b/lib/acpi/base.c @@ -7,12 +7,13 @@ #define LOG_CATEGORY LOGC_ACPI -#include <common.h> #include <acpi/acpi_table.h> #include <dm/acpi.h> #include <mapmem.h> #include <tables_csum.h> #include <linux/sizes.h> +#include <linux/errno.h> +#include <linux/string.h> void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt, struct acpi_xsdt *xsdt) diff --git a/lib/acpi/csrt.c b/lib/acpi/csrt.c index 2ba86f22952..00927e53406 100644 --- a/lib/acpi/csrt.c +++ b/lib/acpi/csrt.c @@ -7,11 +7,11 @@ #define LOG_CATEGORY LOGC_ACPI -#include <common.h> #include <mapmem.h> #include <tables_csum.h> #include <acpi/acpi_table.h> #include <dm/acpi.h> +#include <linux/string.h> __weak int acpi_fill_csrt(struct acpi_ctx *ctx) { diff --git a/lib/acpi/dsdt.c b/lib/acpi/dsdt.c index db98cc20e1d..206e1e2678f 100644 --- a/lib/acpi/dsdt.c +++ b/lib/acpi/dsdt.c @@ -7,10 +7,10 @@ #define LOG_CATEGORY LOGC_ACPI -#include <common.h> #include <acpi/acpi_table.h> #include <dm/acpi.h> #include <tables_csum.h> +#include <linux/string.h> /* * IASL compiles the dsdt entries and writes the hex values diff --git a/lib/acpi/facs.c b/lib/acpi/facs.c index e89f43ca5c9..86c28120c7e 100644 --- a/lib/acpi/facs.c +++ b/lib/acpi/facs.c @@ -7,9 +7,9 @@ #define LOG_CATEGORY LOGC_ACPI -#include <common.h> #include <acpi/acpi_table.h> #include <dm/acpi.h> +#include <linux/string.h> int acpi_write_facs(struct acpi_ctx *ctx, const struct acpi_writer *entry) { diff --git a/lib/acpi/mcfg.c b/lib/acpi/mcfg.c index 7404ae586ab..8b8a5bfafae 100644 --- a/lib/acpi/mcfg.c +++ b/lib/acpi/mcfg.c @@ -7,11 +7,13 @@ #define LOG_CATEGORY LOGC_ACPI -#include <common.h> #include <mapmem.h> #include <tables_csum.h> #include <acpi/acpi_table.h> #include <dm/acpi.h> +#include <linux/errno.h> +#include <linux/string.h> +#include <linux/types.h> int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end) diff --git a/lib/acpi/ssdt.c b/lib/acpi/ssdt.c index b140b4b2ff6..b0a96f846e3 100644 --- a/lib/acpi/ssdt.c +++ b/lib/acpi/ssdt.c @@ -7,10 +7,11 @@ #define LOG_CATEGORY LOGC_ACPI -#include <common.h> #include <acpi/acpi_table.h> #include <dm/acpi.h> #include <tables_csum.h> +#include <linux/errno.h> +#include <linux/string.h> int acpi_write_ssdt(struct acpi_ctx *ctx, const struct acpi_writer *entry) { diff --git a/lib/addr_map.c b/lib/addr_map.c index 86e932e4b56..f85fb0c7fb1 100644 --- a/lib/addr_map.c +++ b/lib/addr_map.c @@ -3,7 +3,6 @@ * Copyright 2008 Freescale Semiconductor, Inc. */ -#include <common.h> #include <addr_map.h> #include <mapmem.h> diff --git a/lib/aes.c b/lib/aes.c index 4fca85ebee2..39ad4a990f0 100644 --- a/lib/aes.c +++ b/lib/aes.c @@ -22,9 +22,9 @@ */ #ifndef USE_HOSTCC -#include <common.h> #include <display_options.h> #include <log.h> +#include <linux/string.h> #else #include <string.h> #endif diff --git a/lib/aes/aes-decrypt.c b/lib/aes/aes-decrypt.c index 345029fa784..741102a4723 100644 --- a/lib/aes/aes-decrypt.c +++ b/lib/aes/aes-decrypt.c @@ -4,7 +4,6 @@ */ #ifndef USE_HOSTCC -#include <common.h> #include <malloc.h> #endif #include <image.h> diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c index 216d9716d0d..4e2dbda9a71 100644 --- a/lib/asm-offsets.c +++ b/lib/asm-offsets.c @@ -11,9 +11,9 @@ * #defines from the assembly-language output. */ -#include <common.h> #include <asm-offsets.h> #include <asm/global_data.h> +#include <asm/u-boot.h> #include <linux/kbuild.h> diff --git a/lib/at91/at91.c b/lib/at91/at91.c index 048597690b1..bd31e9e41dc 100644 --- a/lib/at91/at91.c +++ b/lib/at91/at91.c @@ -4,7 +4,6 @@ * Wenyou.Yang <wenyou.yang@microchip.com> */ -#include <common.h> #include <atmel_lcd.h> #include "atmel_logo_8bpp.h" diff --git a/lib/bch.c b/lib/bch.c index 72b4fdcc9c4..a309a8dfcba 100644 --- a/lib/bch.c +++ b/lib/bch.c @@ -54,7 +54,6 @@ */ #ifndef USE_HOSTCC -#include <common.h> #include <log.h> #include <malloc.h> #include <ubi_uboot.h> diff --git a/lib/binman.c b/lib/binman.c index cfe1e5f8071..9047f5275f3 100644 --- a/lib/binman.c +++ b/lib/binman.c @@ -6,7 +6,6 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include <common.h> #include <binman.h> #include <dm.h> #include <log.h> diff --git a/lib/bzip2/bzlib.c b/lib/bzip2/bzlib.c index bd589aa810c..f7318b7886e 100644 --- a/lib/bzip2/bzlib.c +++ b/lib/bzip2/bzlib.c @@ -1,7 +1,6 @@ -#include <config.h> -#include <common.h> #include <malloc.h> #include <watchdog.h> +#include <stdio.h> /* * This file is a modified version of bzlib.c from the bzip2-1.0.2 diff --git a/lib/bzip2/bzlib_decompress.c b/lib/bzip2/bzlib_decompress.c index 3b417d57b27..e56ab6674b0 100644 --- a/lib/bzip2/bzlib_decompress.c +++ b/lib/bzip2/bzlib_decompress.c @@ -1,5 +1,4 @@ #include <config.h> -#include <common.h> #include <watchdog.h> /*-------------------------------------------------------------*/ diff --git a/lib/charset.c b/lib/charset.c index 5e4c4f948a4..89057ef7ce2 100644 --- a/lib/charset.c +++ b/lib/charset.c @@ -5,7 +5,6 @@ * Copyright (c) 2017 Rob Clark */ -#include <common.h> #include <charset.h> #include <capitalization.h> #include <cp437.h> diff --git a/lib/circbuf.c b/lib/circbuf.c index fa79c148dae..2e161ae8d8b 100644 --- a/lib/circbuf.c +++ b/lib/circbuf.c @@ -4,7 +4,6 @@ * Gerry Hamel, geh@ti.com, Texas Instruments */ -#include <common.h> #include <log.h> #include <malloc.h> diff --git a/lib/crc16-ccitt.c b/lib/crc16-ccitt.c index 6cadbc103d3..6fa4e93ed17 100644 --- a/lib/crc16-ccitt.c +++ b/lib/crc16-ccitt.c @@ -24,8 +24,6 @@ #ifdef USE_HOSTCC #include <arpa/inet.h> -#else -#include <common.h> #endif #include <u-boot/crc.h> diff --git a/lib/crc32.c b/lib/crc32.c index f6fad8c15df..f36f1763064 100644 --- a/lib/crc32.c +++ b/lib/crc32.c @@ -11,7 +11,6 @@ #ifdef USE_HOSTCC #include <arpa/inet.h> #else -#include <common.h> #include <efi_loader.h> #endif #include <compiler.h> diff --git a/lib/crc32c.c b/lib/crc32c.c index 016b34a523b..7026ac4c330 100644 --- a/lib/crc32c.c +++ b/lib/crc32c.c @@ -10,7 +10,6 @@ * any later version. */ -#include <common.h> #include <compiler.h> uint32_t crc32c_cal(uint32_t crc, const char *data, int length, diff --git a/lib/crc8.c b/lib/crc8.c index 87b87b675b2..20d46d16147 100644 --- a/lib/crc8.c +++ b/lib/crc8.c @@ -5,8 +5,6 @@ #ifdef USE_HOSTCC #include <arpa/inet.h> -#else -#include <common.h> #endif #include <u-boot/crc.h> diff --git a/lib/crypt/crypt-port.h b/lib/crypt/crypt-port.h index 6b9542d75bc..50dde68b5cd 100644 --- a/lib/crypt/crypt-port.h +++ b/lib/crypt/crypt-port.h @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* Copyright (C) 2020 Steffen Jaeckel <jaeckel-floss@eyet-services.de> */ +#include <linux/errno.h> +#include <linux/kernel.h> +#include <linux/string.h> #include <linux/types.h> #include <vsprintf.h> diff --git a/lib/crypt/crypt.c b/lib/crypt/crypt.c index 247c34b2a9c..8f5fadb582e 100644 --- a/lib/crypt/crypt.c +++ b/lib/crypt/crypt.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* Copyright (C) 2020 Steffen Jaeckel <jaeckel-floss@eyet-services.de> */ -#include <common.h> #include <crypt.h> #include "crypt-port.h" diff --git a/lib/crypto/x509_public_key.c b/lib/crypto/x509_public_key.c index 30071233ee7..a10145a7cdc 100644 --- a/lib/crypto/x509_public_key.c +++ b/lib/crypto/x509_public_key.c @@ -7,7 +7,6 @@ #define pr_fmt(fmt) "X.509: "fmt #ifdef __UBOOT__ -#include <common.h> #include <image.h> #include <dm/devres.h> #include <linux/compat.h> diff --git a/lib/date.c b/lib/date.c index e3d22459cd0..0deac8a1bee 100644 --- a/lib/date.c +++ b/lib/date.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <command.h> #include <errno.h> #include <rtc.h> diff --git a/lib/dhry/cmd_dhry.c b/lib/dhry/cmd_dhry.c index 77b52a23003..e52beaeaadc 100644 --- a/lib/dhry/cmd_dhry.c +++ b/lib/dhry/cmd_dhry.c @@ -3,9 +3,10 @@ * (C) Copyright 2015 Google, Inc */ -#include <common.h> #include <command.h> #include <div64.h> +#include <time.h> +#include <vsprintf.h> #include "dhry.h" static int do_dhry(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/lib/dhry/dhry_1.c b/lib/dhry/dhry_1.c index dcc224fb387..252cd14a656 100644 --- a/lib/dhry/dhry_1.c +++ b/lib/dhry/dhry_1.c @@ -42,8 +42,8 @@ ***************************************************************************/ char SCCSid[] = "@(#) @(#)dhry_1.c:3.4 -- 5/15/91 19:30:21"; -#include <common.h> #include <malloc.h> +#include <stdio.h> #include "dhry.h" diff --git a/lib/dhry/dhry_2.c b/lib/dhry/dhry_2.c index 1ba879673e3..a74197d884d 100644 --- a/lib/dhry/dhry_2.c +++ b/lib/dhry/dhry_2.c @@ -39,7 +39,7 @@ ****************************************************************************/ /* SCCSid is defined in dhry_1.c */ -#include <common.h> +#include <linux/string.h> #include "dhry.h" #ifndef REG diff --git a/lib/display_options.c b/lib/display_options.c index 80def5201f9..d6b93553dcb 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -4,14 +4,15 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <compiler.h> #include <console.h> #include <display_options.h> #include <div64.h> #include <version_string.h> #include <linux/ctype.h> +#include <linux/kernel.h> #include <asm/io.h> +#include <vsprintf.h> char *display_options_get_banner_priv(bool newlines, const char *build_tag, char *buf, int size) diff --git a/lib/efi/efi.c b/lib/efi/efi.c index aa42f1842f3..bcb34d67465 100644 --- a/lib/efi/efi.c +++ b/lib/efi/efi.c @@ -10,7 +10,6 @@ * Common EFI functions */ -#include <common.h> #include <debug_uart.h> #include <errno.h> #include <malloc.h> diff --git a/lib/efi/efi_app.c b/lib/efi/efi_app.c index 2209410f35b..119db6602cf 100644 --- a/lib/efi/efi_app.c +++ b/lib/efi/efi_app.c @@ -8,22 +8,24 @@ * This file implements U-Boot running as an EFI application. */ -#include <common.h> #include <cpu_func.h> #include <debug_uart.h> #include <dm.h> +#include <efi.h> +#include <efi_api.h> #include <errno.h> #include <init.h> #include <malloc.h> +#include <sysreset.h> +#include <uuid.h> #include <asm/global_data.h> #include <linux/err.h> #include <linux/types.h> -#include <efi.h> -#include <efi_api.h> -#include <sysreset.h> +#include <asm/global_data.h> #include <dm/device-internal.h> #include <dm/lists.h> #include <dm/root.h> +#include <mapmem.h> DECLARE_GLOBAL_DATA_PTR; @@ -320,6 +322,19 @@ int dm_scan_other(bool pre_reloc_only) return 0; } +static void scan_tables(struct efi_system_table *sys_table) +{ + efi_guid_t acpi = EFI_ACPI_TABLE_GUID; + uint i; + + for (i = 0; i < sys_table->nr_tables; i++) { + struct efi_configuration_table *tab = &sys_table->tables[i]; + + if (!memcmp(&tab->guid, &acpi, sizeof(efi_guid_t))) + gd_set_acpi_start(map_to_sysmem(tab->table)); + } +} + /** * efi_main() - Start an EFI image * @@ -354,6 +369,8 @@ efi_status_t EFIAPI efi_main(efi_handle_t image, return ret; } + scan_tables(priv->sys_table); + /* * We could store the EFI memory map here, but it changes all the time, * so this is only useful for debugging. diff --git a/lib/efi/efi_info.c b/lib/efi/efi_info.c index 4d78923c4d4..5b564c5651d 100644 --- a/lib/efi/efi_info.c +++ b/lib/efi/efi_info.c @@ -5,7 +5,6 @@ * Access to the EFI information table */ -#include <common.h> #include <efi.h> #include <errno.h> #include <mapmem.h> diff --git a/lib/efi/efi_stub.c b/lib/efi/efi_stub.c index c9eb32ec104..40fc29d9adf 100644 --- a/lib/efi/efi_stub.c +++ b/lib/efi/efi_stub.c @@ -9,7 +9,6 @@ * EFI application. It can be built either in 32-bit or 64-bit mode. */ -#include <common.h> #include <debug_uart.h> #include <efi.h> #include <efi_api.h> diff --git a/lib/efi_driver/efi_block_device.c b/lib/efi_driver/efi_block_device.c index e3abd90275c..34a0365739d 100644 --- a/lib/efi_driver/efi_block_device.c +++ b/lib/efi_driver/efi_block_device.c @@ -28,7 +28,6 @@ * iPXE uses the simple file protocol to load Grub or the Linux Kernel. */ -#include <common.h> #include <blk.h> #include <dm.h> #include <efi_driver.h> diff --git a/lib/efi_driver/efi_uclass.c b/lib/efi_driver/efi_uclass.c index 66a45e156d6..e1e28df20b2 100644 --- a/lib/efi_driver/efi_uclass.c +++ b/lib/efi_driver/efi_uclass.c @@ -17,7 +17,6 @@ * controllers. */ -#include <common.h> #include <dm.h> #include <efi_driver.h> #include <log.h> diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 0a2cb6e3c47..24d33d54099 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -51,9 +51,7 @@ obj-y += efi_console.o obj-y += efi_device_path.o obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_device_path_to_text.o obj-$(CONFIG_EFI_DEVICE_PATH_UTIL) += efi_device_path_utilities.o -ifeq ($(CONFIG_GENERATE_ACPI_TABLE),) obj-y += efi_dt_fixup.o -endif obj-y += efi_file.o obj-$(CONFIG_EFI_LOADER_HII) += efi_hii.o obj-y += efi_image_loader.o diff --git a/lib/efi_loader/dtbdump.c b/lib/efi_loader/dtbdump.c index 3ce2a07f9eb..5f39cf22da7 100644 --- a/lib/efi_loader/dtbdump.c +++ b/lib/efi_loader/dtbdump.c @@ -6,7 +6,6 @@ * to a file. */ -#include <common.h> #include <efi_api.h> #include <efi_dt_fixup.h> #include <part.h> diff --git a/lib/efi_loader/efi_acpi.c b/lib/efi_loader/efi_acpi.c index f755af76f86..67bbd2a01c0 100644 --- a/lib/efi_loader/efi_acpi.c +++ b/lib/efi_loader/efi_acpi.c @@ -5,7 +5,6 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <efi_loader.h> #include <log.h> #include <mapmem.h> diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c index 48153bd5ffb..a032d3ae04e 100644 --- a/lib/efi_loader/efi_bootmgr.c +++ b/lib/efi_loader/efi_bootmgr.c @@ -3,13 +3,14 @@ * EFI boot manager * * Copyright (c) 2017 Rob Clark + * For the code moved from cmd/bootefi.c + * Copyright (c) 2016 Alexander Graf */ #define LOG_CATEGORY LOGC_EFI #include <blk.h> #include <blkmap.h> -#include <common.h> #include <charset.h> #include <dm.h> #include <log.h> @@ -20,6 +21,17 @@ #include <efi_variable.h> #include <asm/unaligned.h> +/* TODO: temporarily added here; clean up later */ +#include <bootm.h> +#include <efi_selftest.h> +#include <env.h> +#include <mapmem.h> +#include <asm/global_data.h> +#include <linux/libfdt.h> +#include <linux/libfdt_env.h> + +DECLARE_GLOBAL_DATA_PTR; + static const struct efi_boot_services *bs; static const struct efi_runtime_services *rs; @@ -1115,3 +1127,515 @@ out: return EFI_SUCCESS; return ret; } + +static struct efi_device_path *bootefi_image_path; +static struct efi_device_path *bootefi_device_path; +static void *image_addr; +static size_t image_size; + +/** + * efi_get_image_parameters() - return image parameters + * + * @img_addr: address of loaded image in memory + * @img_size: size of loaded image + */ +void efi_get_image_parameters(void **img_addr, size_t *img_size) +{ + *img_addr = image_addr; + *img_size = image_size; +} + +/** + * efi_clear_bootdev() - clear boot device + */ +void efi_clear_bootdev(void) +{ + efi_free_pool(bootefi_device_path); + efi_free_pool(bootefi_image_path); + bootefi_device_path = NULL; + bootefi_image_path = NULL; + image_addr = NULL; + image_size = 0; +} + +/** + * efi_set_bootdev() - set boot device + * + * This function is called when a file is loaded, e.g. via the 'load' command. + * We use the path to this file to inform the UEFI binary about the boot device. + * + * @dev: device, e.g. "MMC" + * @devnr: number of the device, e.g. "1:2" + * @path: path to file loaded + * @buffer: buffer with file loaded + * @buffer_size: size of file loaded + */ +void efi_set_bootdev(const char *dev, const char *devnr, const char *path, + void *buffer, size_t buffer_size) +{ + struct efi_device_path *device, *image; + efi_status_t ret; + + log_debug("dev=%s, devnr=%s, path=%s, buffer=%p, size=%zx\n", dev, + devnr, path, buffer, buffer_size); + + /* Forget overwritten image */ + if (buffer + buffer_size >= image_addr && + image_addr + image_size >= buffer) + efi_clear_bootdev(); + + /* Remember only PE-COFF and FIT images */ + if (efi_check_pe(buffer, buffer_size, NULL) != EFI_SUCCESS) { + if (IS_ENABLED(CONFIG_FIT) && + !fit_check_format(buffer, IMAGE_SIZE_INVAL)) { + /* + * FIT images of type EFI_OS are started via command + * bootm. We should not use their boot device with the + * bootefi command. + */ + buffer = 0; + buffer_size = 0; + } else { + log_debug("- not remembering image\n"); + return; + } + } + + /* efi_set_bootdev() is typically called repeatedly, recover memory */ + efi_clear_bootdev(); + + image_addr = buffer; + image_size = buffer_size; + + ret = efi_dp_from_name(dev, devnr, path, &device, &image); + if (ret == EFI_SUCCESS) { + bootefi_device_path = device; + if (image) { + /* FIXME: image should not contain device */ + struct efi_device_path *image_tmp = image; + + efi_dp_split_file_path(image, &device, &image); + efi_free_pool(image_tmp); + } + bootefi_image_path = image; + log_debug("- boot device %pD\n", device); + if (image) + log_debug("- image %pD\n", image); + } else { + log_debug("- efi_dp_from_name() failed, err=%lx\n", ret); + efi_clear_bootdev(); + } +} + +/** + * efi_env_set_load_options() - set load options from environment variable + * + * @handle: the image handle + * @env_var: name of the environment variable + * @load_options: pointer to load options (output) + * Return: status code + */ +efi_status_t efi_env_set_load_options(efi_handle_t handle, + const char *env_var, + u16 **load_options) +{ + const char *env = env_get(env_var); + size_t size; + u16 *pos; + efi_status_t ret; + + *load_options = NULL; + if (!env) + return EFI_SUCCESS; + size = sizeof(u16) * (utf8_utf16_strlen(env) + 1); + pos = calloc(size, 1); + if (!pos) + return EFI_OUT_OF_RESOURCES; + *load_options = pos; + utf8_utf16_strcpy(&pos, env); + ret = efi_set_load_options(handle, size, *load_options); + if (ret != EFI_SUCCESS) { + free(*load_options); + *load_options = NULL; + } + return ret; +} + +/** + * copy_fdt() - Copy the device tree to a new location available to EFI + * + * The FDT is copied to a suitable location within the EFI memory map. + * Additional 12 KiB are added to the space in case the device tree needs to be + * expanded later with fdt_open_into(). + * + * @fdtp: On entry a pointer to the flattened device tree. + * On exit a pointer to the copy of the flattened device tree. + * FDT start + * Return: status code + */ +static efi_status_t copy_fdt(void **fdtp) +{ + unsigned long fdt_ram_start = -1L, fdt_pages; + efi_status_t ret = 0; + void *fdt, *new_fdt; + u64 new_fdt_addr; + uint fdt_size; + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + u64 ram_start = gd->bd->bi_dram[i].start; + u64 ram_size = gd->bd->bi_dram[i].size; + + if (!ram_size) + continue; + + if (ram_start < fdt_ram_start) + fdt_ram_start = ram_start; + } + + /* + * Give us at least 12 KiB of breathing room in case the device tree + * needs to be expanded later. + */ + fdt = *fdtp; + fdt_pages = efi_size_in_pages(fdt_totalsize(fdt) + 0x3000); + fdt_size = fdt_pages << EFI_PAGE_SHIFT; + + ret = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES, + EFI_ACPI_RECLAIM_MEMORY, fdt_pages, + &new_fdt_addr); + if (ret != EFI_SUCCESS) { + log_err("ERROR: Failed to reserve space for FDT\n"); + goto done; + } + new_fdt = (void *)(uintptr_t)new_fdt_addr; + memcpy(new_fdt, fdt, fdt_totalsize(fdt)); + fdt_set_totalsize(new_fdt, fdt_size); + + *fdtp = (void *)(uintptr_t)new_fdt_addr; +done: + return ret; +} + +/** + * get_config_table() - get configuration table + * + * @guid: GUID of the configuration table + * Return: pointer to configuration table or NULL + */ +static void *get_config_table(const efi_guid_t *guid) +{ + size_t i; + + for (i = 0; i < systab.nr_tables; i++) { + if (!guidcmp(guid, &systab.tables[i].guid)) + return systab.tables[i].table; + } + return NULL; +} + +/** + * efi_install_fdt() - install device tree + * + * If fdt is not EFI_FDT_USE_INTERNAL, the device tree located at that memory + * address will be installed as configuration table, otherwise the device + * tree located at the address indicated by environment variable fdt_addr or as + * fallback fdtcontroladdr will be used. + * + * On architectures using ACPI tables device trees shall not be installed as + * configuration table. + * + * @fdt: address of device tree or EFI_FDT_USE_INTERNAL to use + * the hardware device tree as indicated by environment variable + * fdt_addr or as fallback the internal device tree as indicated by + * the environment variable fdtcontroladdr + * Return: status code + */ +efi_status_t efi_install_fdt(void *fdt) +{ + struct bootm_headers img = { 0 }; + efi_status_t ret; + + /* + * The EBBR spec requires that we have either an FDT or an ACPI table + * but not both. + */ + if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) && fdt) + log_warning("WARNING: Can't have ACPI table and device tree - ignoring DT.\n"); + + if (fdt == EFI_FDT_USE_INTERNAL) { + const char *fdt_opt; + uintptr_t fdt_addr; + + /* Look for device tree that is already installed */ + if (get_config_table(&efi_guid_fdt)) + return EFI_SUCCESS; + /* Check if there is a hardware device tree */ + fdt_opt = env_get("fdt_addr"); + /* Use our own device tree as fallback */ + if (!fdt_opt) { + fdt_opt = env_get("fdtcontroladdr"); + if (!fdt_opt) { + log_err("ERROR: need device tree\n"); + return EFI_NOT_FOUND; + } + } + fdt_addr = hextoul(fdt_opt, NULL); + if (!fdt_addr) { + log_err("ERROR: invalid $fdt_addr or $fdtcontroladdr\n"); + return EFI_LOAD_ERROR; + } + fdt = map_sysmem(fdt_addr, 0); + } + + /* Install device tree */ + if (fdt_check_header(fdt)) { + log_err("ERROR: invalid device tree\n"); + return EFI_LOAD_ERROR; + } + + /* Create memory reservations as indicated by the device tree */ + efi_carve_out_dt_rsv(fdt); + + if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)) + return EFI_SUCCESS; + + /* Prepare device tree for payload */ + ret = copy_fdt(&fdt); + if (ret) { + log_err("ERROR: out of memory\n"); + return EFI_OUT_OF_RESOURCES; + } + + if (image_setup_libfdt(&img, fdt, NULL)) { + log_err("ERROR: failed to process device tree\n"); + return EFI_LOAD_ERROR; + } + + efi_try_purge_kaslr_seed(fdt); + + if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) { + ret = efi_tcg2_measure_dtb(fdt); + if (ret == EFI_SECURITY_VIOLATION) { + log_err("ERROR: failed to measure DTB\n"); + return ret; + } + } + + /* Install device tree as UEFI table */ + ret = efi_install_configuration_table(&efi_guid_fdt, fdt); + if (ret != EFI_SUCCESS) { + log_err("ERROR: failed to install device tree\n"); + return ret; + } + + return EFI_SUCCESS; +} + +/** + * do_bootefi_exec() - execute EFI binary + * + * The image indicated by @handle is started. When it returns the allocated + * memory for the @load_options is freed. + * + * @handle: handle of loaded image + * @load_options: load options + * Return: status code + * + * Load the EFI binary into a newly assigned memory unwinding the relocation + * information, install the loaded image protocol, and call the binary. + */ +static efi_status_t do_bootefi_exec(efi_handle_t handle, void *load_options) +{ + efi_status_t ret; + efi_uintn_t exit_data_size = 0; + u16 *exit_data = NULL; + struct efi_event *evt; + + /* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */ + switch_to_non_secure_mode(); + + /* + * The UEFI standard requires that the watchdog timer is set to five + * minutes when invoking an EFI boot option. + * + * Unified Extensible Firmware Interface (UEFI), version 2.7 Errata A + * 7.5. Miscellaneous Boot Services - EFI_BOOT_SERVICES.SetWatchdogTimer + */ + ret = efi_set_watchdog(300); + if (ret != EFI_SUCCESS) { + log_err("ERROR: Failed to set watchdog timer\n"); + goto out; + } + + /* Call our payload! */ + ret = EFI_CALL(efi_start_image(handle, &exit_data_size, &exit_data)); + if (ret != EFI_SUCCESS) { + log_err("## Application failed, r = %lu\n", + ret & ~EFI_ERROR_MASK); + if (exit_data) { + log_err("## %ls\n", exit_data); + efi_free_pool(exit_data); + } + } + + efi_restore_gd(); + +out: + free(load_options); + + if (IS_ENABLED(CONFIG_EFI_LOAD_FILE2_INITRD)) { + if (efi_initrd_deregister() != EFI_SUCCESS) + log_err("Failed to remove loadfile2 for initrd\n"); + } + + /* Notify EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR event group. */ + list_for_each_entry(evt, &efi_events, link) { + if (evt->group && + !guidcmp(evt->group, + &efi_guid_event_group_return_to_efibootmgr)) { + efi_signal_event(evt); + EFI_CALL(systab.boottime->close_event(evt)); + break; + } + } + + /* Control is returned to U-Boot, disable EFI watchdog */ + efi_set_watchdog(0); + + return ret; +} + +/** + * efi_bootmgr_run() - execute EFI boot manager + * @fdt: Flat device tree + * + * Invoke EFI boot manager and execute a binary depending on + * boot options. If @fdt is not NULL, it will be passed to + * the executed binary. + * + * Return: status code + */ +efi_status_t efi_bootmgr_run(void *fdt) +{ + efi_handle_t handle; + void *load_options; + efi_status_t ret; + + /* Initialize EFI drivers */ + ret = efi_init_obj_list(); + if (ret != EFI_SUCCESS) { + log_err("Error: Cannot initialize UEFI sub-system, r = %lu\n", + ret & ~EFI_ERROR_MASK); + return CMD_RET_FAILURE; + } + + ret = efi_install_fdt(fdt); + if (ret != EFI_SUCCESS) + return ret; + + ret = efi_bootmgr_load(&handle, &load_options); + if (ret != EFI_SUCCESS) { + log_notice("EFI boot manager: Cannot load any image\n"); + return ret; + } + + return do_bootefi_exec(handle, load_options); +} + +/** + * efi_run_image() - run loaded UEFI image + * + * @source_buffer: memory address of the UEFI image + * @source_size: size of the UEFI image + * Return: status code + */ +efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size) +{ + efi_handle_t mem_handle = NULL, handle; + struct efi_device_path *file_path = NULL; + struct efi_device_path *msg_path; + efi_status_t ret, ret2; + u16 *load_options; + + if (!bootefi_device_path || !bootefi_image_path) { + log_debug("Not loaded from disk\n"); + /* + * Special case for efi payload not loaded from disk, + * such as 'bootefi hello' or for example payload + * loaded directly into memory via JTAG, etc: + */ + file_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, + (uintptr_t)source_buffer, + source_size); + /* + * Make sure that device for device_path exist + * in load_image(). Otherwise, shell and grub will fail. + */ + ret = efi_install_multiple_protocol_interfaces(&mem_handle, + &efi_guid_device_path, + file_path, NULL); + if (ret != EFI_SUCCESS) + goto out; + msg_path = file_path; + } else { + file_path = efi_dp_append(bootefi_device_path, + bootefi_image_path); + msg_path = bootefi_image_path; + log_debug("Loaded from disk\n"); + } + + log_info("Booting %pD\n", msg_path); + + ret = EFI_CALL(efi_load_image(false, efi_root, file_path, source_buffer, + source_size, &handle)); + if (ret != EFI_SUCCESS) { + log_err("Loading image failed\n"); + goto out; + } + + /* Transfer environment variable as load options */ + ret = efi_env_set_load_options(handle, "bootargs", &load_options); + if (ret != EFI_SUCCESS) + goto out; + + ret = do_bootefi_exec(handle, load_options); + +out: + ret2 = efi_uninstall_multiple_protocol_interfaces(mem_handle, + &efi_guid_device_path, + file_path, NULL); + efi_free_pool(file_path); + return (ret != EFI_SUCCESS) ? ret : ret2; +} + +/** + * efi_binary_run() - run loaded UEFI image + * + * @image: memory address of the UEFI image + * @size: size of the UEFI image + * @fdt: device-tree + * + * Execute an EFI binary image loaded at @image. + * @size may be zero if the binary is loaded with U-Boot load command. + * + * Return: status code + */ +efi_status_t efi_binary_run(void *image, size_t size, void *fdt) +{ + efi_status_t ret; + + /* Initialize EFI drivers */ + ret = efi_init_obj_list(); + if (ret != EFI_SUCCESS) { + log_err("Error: Cannot initialize UEFI sub-system, r = %lu\n", + ret & ~EFI_ERROR_MASK); + return -1; + } + + ret = efi_install_fdt(fdt); + if (ret != EFI_SUCCESS) + return ret; + + return efi_run_image(image, size); +} diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 3767fa2db42..c579d89211b 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -5,7 +5,6 @@ * Copyright (c) 2016 Alexander Graf */ -#include <common.h> #include <bootm.h> #include <div64.h> #include <dm/device.h> @@ -1342,7 +1341,7 @@ static efi_status_t efi_disconnect_all_drivers const efi_guid_t *protocol, efi_handle_t child_handle) { - efi_uintn_t number_of_drivers, tmp; + efi_uintn_t number_of_drivers; efi_handle_t *driver_handle_buffer; efi_status_t r, ret; @@ -1353,27 +1352,13 @@ static efi_status_t efi_disconnect_all_drivers if (!number_of_drivers) return EFI_SUCCESS; - tmp = number_of_drivers; while (number_of_drivers) { - ret = EFI_CALL(efi_disconnect_controller( + r = EFI_CALL(efi_disconnect_controller( handle, driver_handle_buffer[--number_of_drivers], child_handle)); - if (ret != EFI_SUCCESS) - goto reconnect; - } - - free(driver_handle_buffer); - return ret; - -reconnect: - /* Reconnect all disconnected drivers */ - for (; number_of_drivers < tmp; number_of_drivers++) { - r = EFI_CALL(efi_connect_controller(handle, - &driver_handle_buffer[number_of_drivers], - NULL, true)); if (r != EFI_SUCCESS) - EFI_PRINT("Failed to reconnect controller\n"); + ret = r; } free(driver_handle_buffer); @@ -1412,6 +1397,13 @@ static efi_status_t efi_uninstall_protocol r = efi_disconnect_all_drivers(handle, protocol, NULL); if (r != EFI_SUCCESS) { r = EFI_ACCESS_DENIED; + /* + * This will reconnect all controllers of the handle, even ones + * that were not connected before. This can be done better + * but we are following the EDKII implementation on this for + * now + */ + EFI_CALL(efi_connect_controller(handle, NULL, NULL, true)); goto out; } /* Close protocol */ diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c index af8a2ee940c..de0d49ebebd 100644 --- a/lib/efi_loader/efi_capsule.c +++ b/lib/efi_loader/efi_capsule.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY LOGC_EFI -#include <common.h> #include <efi_loader.h> #include <efi_variable.h> #include <env.h> diff --git a/lib/efi_loader/efi_conformance.c b/lib/efi_loader/efi_conformance.c index 0ca26f57a7f..167067e26cd 100644 --- a/lib/efi_loader/efi_conformance.c +++ b/lib/efi_loader/efi_conformance.c @@ -5,7 +5,6 @@ * Copyright (C) 2022 Arm Ltd. */ -#include <common.h> #include <efi_loader.h> #include <log.h> #include <efi_api.h> diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c index a2d137d7a9e..03dece51aea 100644 --- a/lib/efi_loader/efi_console.c +++ b/lib/efi_loader/efi_console.c @@ -8,7 +8,6 @@ #define LOG_CATEGORY LOGC_EFI #include <ansi.h> -#include <common.h> #include <charset.h> #include <malloc.h> #include <time.h> diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index ed7214f3a34..8dbd8105ae2 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY LOGC_EFI -#include <common.h> #include <blk.h> #include <dm.h> #include <dm/root.h> diff --git a/lib/efi_loader/efi_device_path_to_text.c b/lib/efi_loader/efi_device_path_to_text.c index 8c76d8be605..0c7b30a26e7 100644 --- a/lib/efi_loader/efi_device_path_to_text.c +++ b/lib/efi_loader/efi_device_path_to_text.c @@ -5,7 +5,6 @@ * Copyright (c) 2017 Heinrich Schuchardt */ -#include <common.h> #include <blk.h> #include <efi_loader.h> #include <malloc.h> diff --git a/lib/efi_loader/efi_device_path_utilities.c b/lib/efi_loader/efi_device_path_utilities.c index a07d9bab3a3..844d8acd67c 100644 --- a/lib/efi_loader/efi_device_path_utilities.c +++ b/lib/efi_loader/efi_device_path_utilities.c @@ -5,7 +5,6 @@ * Copyright (c) 2017 Leif Lindholm */ -#include <common.h> #include <efi_loader.h> const efi_guid_t efi_guid_device_path_utilities_protocol = diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c index b808a7fe627..ed997008c4e 100644 --- a/lib/efi_loader/efi_disk.c +++ b/lib/efi_loader/efi_disk.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY LOGC_EFI -#include <common.h> #include <blk.h> #include <dm.h> #include <dm/device-internal.h> diff --git a/lib/efi_loader/efi_dt_fixup.c b/lib/efi_loader/efi_dt_fixup.c index a0c889cf986..9886e6897cd 100644 --- a/lib/efi_loader/efi_dt_fixup.c +++ b/lib/efi_loader/efi_dt_fixup.c @@ -5,7 +5,6 @@ * Copyright (c) 2020 Heinrich Schuchardt */ -#include <common.h> #include <efi_dt_fixup.h> #include <efi_loader.h> #include <efi_rng.h> diff --git a/lib/efi_loader/efi_esrt.c b/lib/efi_loader/efi_esrt.c index 7f46d651e6f..dafd447b6d7 100644 --- a/lib/efi_loader/efi_esrt.c +++ b/lib/efi_loader/efi_esrt.c @@ -5,7 +5,6 @@ * Copyright (C) 2021 Arm Ltd. */ -#include <common.h> #include <efi_loader.h> #include <log.h> #include <efi_api.h> diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c index 3c56cebf965..222001d6a3b 100644 --- a/lib/efi_loader/efi_file.c +++ b/lib/efi_loader/efi_file.c @@ -5,7 +5,6 @@ * Copyright (c) 2017 Rob Clark */ -#include <common.h> #include <charset.h> #include <efi_loader.h> #include <log.h> diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c index 9abb29f1dff..1fde1885e3c 100644 --- a/lib/efi_loader/efi_firmware.c +++ b/lib/efi_loader/efi_firmware.c @@ -6,7 +6,6 @@ * Author: AKASHI Takahiro */ -#include <common.h> #include <charset.h> #include <dfu.h> #include <efi_loader.h> diff --git a/lib/efi_loader/efi_freestanding.c b/lib/efi_loader/efi_freestanding.c index 4b65fc64dd0..b2786095c32 100644 --- a/lib/efi_loader/efi_freestanding.c +++ b/lib/efi_loader/efi_freestanding.c @@ -8,7 +8,7 @@ * memset(), and memcmp(). */ -#include <common.h> +#include <linux/types.h> /** * memcmp() - compare memory areas diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c index a09db31eb46..41e12fa7246 100644 --- a/lib/efi_loader/efi_gop.c +++ b/lib/efi_loader/efi_gop.c @@ -5,7 +5,6 @@ * Copyright (c) 2016 Alexander Graf */ -#include <common.h> #include <dm.h> #include <efi_loader.h> #include <log.h> diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c index cdfd16ea774..17f27ca1a0b 100644 --- a/lib/efi_loader/efi_helper.c +++ b/lib/efi_loader/efi_helper.c @@ -4,7 +4,6 @@ */ #define LOG_CATEGORY LOGC_EFI -#include <common.h> #include <env.h> #include <malloc.h> #include <dm.h> diff --git a/lib/efi_loader/efi_hii.c b/lib/efi_loader/efi_hii.c index 3b54ecb11ac..74e402df1b8 100644 --- a/lib/efi_loader/efi_hii.c +++ b/lib/efi_loader/efi_hii.c @@ -6,7 +6,6 @@ * Copyright (c) 2018 AKASHI Takahiro, Linaro Limited */ -#include <common.h> #include <efi_loader.h> #include <malloc.h> #include <asm/unaligned.h> diff --git a/lib/efi_loader/efi_hii_config.c b/lib/efi_loader/efi_hii_config.c index 31b0c97eb28..ae0f3ecd3b1 100644 --- a/lib/efi_loader/efi_hii_config.c +++ b/lib/efi_loader/efi_hii_config.c @@ -10,7 +10,6 @@ * the Makefile. */ -#include <common.h> #include <efi_loader.h> const efi_guid_t efi_guid_hii_config_routing_protocol diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index 97547571ce3..60424360328 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -9,7 +9,6 @@ #define LOG_CATEGORY LOGC_EFI -#include <common.h> #include <cpu_func.h> #include <efi_loader.h> #include <log.h> diff --git a/lib/efi_loader/efi_load_initrd.c b/lib/efi_loader/efi_load_initrd.c index 193433782c2..2b467b55481 100644 --- a/lib/efi_loader/efi_load_initrd.c +++ b/lib/efi_loader/efi_load_initrd.c @@ -4,7 +4,6 @@ */ #define LOG_CATEGORY LOGC_EFI -#include <common.h> #include <efi_loader.h> #include <efi_load_initrd.h> #include <efi_variable.h> diff --git a/lib/efi_loader/efi_load_options.c b/lib/efi_loader/efi_load_options.c index 5f62184da1c..01984235e24 100644 --- a/lib/efi_loader/efi_load_options.c +++ b/lib/efi_loader/efi_load_options.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY LOGC_EFI -#include <common.h> #include <charset.h> #include <log.h> #include <malloc.h> diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index f752703b438..edfad2d95a1 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY LOGC_EFI -#include <common.h> #include <efi_loader.h> #include <init.h> #include <log.h> diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c index 96a5bcca275..7cd536705f4 100644 --- a/lib/efi_loader/efi_net.c +++ b/lib/efi_loader/efi_net.c @@ -15,7 +15,6 @@ * Reset(): EfiSimpleNetworkInitialized -> EfiSimpleNetworkInitialized */ -#include <common.h> #include <efi_loader.h> #include <malloc.h> #include <net.h> diff --git a/lib/efi_loader/efi_riscv.c b/lib/efi_loader/efi_riscv.c index 064172755b9..4d398c5be34 100644 --- a/lib/efi_loader/efi_riscv.c +++ b/lib/efi_loader/efi_riscv.c @@ -7,7 +7,6 @@ */ #define LOG_CATEGORY LOGC_EFI -#include <common.h> #include <efi_loader.h> #include <efi_variable.h> #include <log.h> diff --git a/lib/efi_loader/efi_rng.c b/lib/efi_loader/efi_rng.c index bb11d8d0e0c..9bad7ed6931 100644 --- a/lib/efi_loader/efi_rng.c +++ b/lib/efi_loader/efi_rng.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_EFI -#include <common.h> #include <dm.h> #include <efi_loader.h> #include <efi_rng.h> diff --git a/lib/efi_loader/efi_root_node.c b/lib/efi_loader/efi_root_node.c index 108c14b95bd..4d7fb74b5d6 100644 --- a/lib/efi_loader/efi_root_node.c +++ b/lib/efi_loader/efi_root_node.c @@ -5,7 +5,6 @@ * Copyright (c) 2018 Heinrich Schuchardt */ -#include <common.h> #include <malloc.h> #include <efi_dt_fixup.h> #include <efi_loader.h> diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c index bf54d6ad871..18da6892e79 100644 --- a/lib/efi_loader/efi_runtime.c +++ b/lib/efi_loader/efi_runtime.c @@ -5,7 +5,6 @@ * Copyright (c) 2016 Alexander Graf */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <dm.h> diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index 37359a77bbc..a610e032d2f 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY LOGC_EFI -#include <common.h> #include <efi_loader.h> #include <efi_variable.h> #include <log.h> diff --git a/lib/efi_loader/efi_signature.c b/lib/efi_loader/efi_signature.c index 742d8919402..f338e732759 100644 --- a/lib/efi_loader/efi_signature.c +++ b/lib/efi_loader/efi_signature.c @@ -4,7 +4,6 @@ * Copyright (c) 2019 Linaro Limited, Author: AKASHI Takahiro */ -#include <common.h> #include <charset.h> #include <efi_loader.h> #include <efi_variable.h> diff --git a/lib/efi_loader/efi_smbios.c b/lib/efi_loader/efi_smbios.c index 0fbf51b98d0..bbb8421ce14 100644 --- a/lib/efi_loader/efi_smbios.c +++ b/lib/efi_loader/efi_smbios.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY LOGC_EFI -#include <common.h> #include <efi_loader.h> #include <log.h> #include <malloc.h> diff --git a/lib/efi_loader/efi_string.c b/lib/efi_loader/efi_string.c index e21e09c9461..413e329b600 100644 --- a/lib/efi_loader/efi_string.c +++ b/lib/efi_loader/efi_string.c @@ -5,7 +5,6 @@ * Copyright (c) 2020 AKASHI Takahiro, Linaro Limited */ -#include <common.h> #include <charset.h> #include <efi_loader.h> #include <malloc.h> diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c index 463ea4c1541..8db35d0b3c8 100644 --- a/lib/efi_loader/efi_tcg2.c +++ b/lib/efi_loader/efi_tcg2.c @@ -8,7 +8,6 @@ */ #define LOG_CATEGORY LOGC_EFI -#include <common.h> #include <dm.h> #include <efi_loader.h> #include <efi_variable.h> diff --git a/lib/efi_loader/efi_unicode_collation.c b/lib/efi_loader/efi_unicode_collation.c index c4c75720634..2b6912c5092 100644 --- a/lib/efi_loader/efi_unicode_collation.c +++ b/lib/efi_loader/efi_unicode_collation.c @@ -5,7 +5,6 @@ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de> */ -#include <common.h> #include <charset.h> #include <cp1250.h> #include <cp437.h> diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c index ad50bffd2b2..d528747f3fb 100644 --- a/lib/efi_loader/efi_var_common.c +++ b/lib/efi_loader/efi_var_common.c @@ -6,7 +6,6 @@ * Copyright (c) 2020 Linaro Limited, Author: AKASHI Takahiro */ -#include <common.h> #include <efi_loader.h> #include <efi_variable.h> #include <stdlib.h> diff --git a/lib/efi_loader/efi_var_file.c b/lib/efi_loader/efi_var_file.c index d7dba050710..532b6b40eef 100644 --- a/lib/efi_loader/efi_var_file.c +++ b/lib/efi_loader/efi_var_file.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY LOGC_EFI -#include <common.h> #include <charset.h> #include <fs.h> #include <log.h> diff --git a/lib/efi_loader/efi_var_mem.c b/lib/efi_loader/efi_var_mem.c index 5fa7dcb8d3e..6c21cec5d45 100644 --- a/lib/efi_loader/efi_var_mem.c +++ b/lib/efi_loader/efi_var_mem.c @@ -5,7 +5,6 @@ * Copyright (c) 2020, Heinrich Schuchardt */ -#include <common.h> #include <efi_loader.h> #include <efi_variable.h> #include <u-boot/crc.h> diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index be95ed44e6e..40f7a0fb10d 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -7,7 +7,6 @@ #define LOG_CATEGORY LOGC_EFI -#include <common.h> #include <efi_loader.h> #include <efi_variable.h> #include <env.h> diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c index 09d03c0eee7..dde135fd9f8 100644 --- a/lib/efi_loader/efi_variable_tee.c +++ b/lib/efi_loader/efi_variable_tee.c @@ -10,7 +10,6 @@ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> */ -#include <common.h> #if CONFIG_IS_ENABLED(ARM_FFA_TRANSPORT) #include <arm_ffa.h> #endif diff --git a/lib/efi_loader/efi_watchdog.c b/lib/efi_loader/efi_watchdog.c index d741076dcdd..f5fb9117717 100644 --- a/lib/efi_loader/efi_watchdog.c +++ b/lib/efi_loader/efi_watchdog.c @@ -5,7 +5,6 @@ * Copyright (c) 2017 Heinrich Schuchardt */ -#include <common.h> #include <efi_loader.h> /* Conversion factor from seconds to multiples of 100ns */ diff --git a/lib/efi_loader/initrddump.c b/lib/efi_loader/initrddump.c index 5b470f48194..0004b6b042b 100644 --- a/lib/efi_loader/initrddump.c +++ b/lib/efi_loader/initrddump.c @@ -9,7 +9,6 @@ * clearing of the screen. */ -#include <common.h> #include <efi_api.h> #include <efi_load_initrd.h> diff --git a/lib/efi_selftest/efi_selftest_esrt.c b/lib/efi_selftest/efi_selftest_esrt.c index 922ff253c72..b7688deb496 100644 --- a/lib/efi_selftest/efi_selftest_esrt.c +++ b/lib/efi_selftest/efi_selftest_esrt.c @@ -4,7 +4,6 @@ * * Copyright (C) 2021 Arm Ltd. */ -#include <common.h> #include <efi_loader.h> #include <efi_selftest.h> diff --git a/lib/efi_selftest/efi_selftest_miniapp_exception.c b/lib/efi_selftest/efi_selftest_miniapp_exception.c index a9ad381001f..f668cdac4ab 100644 --- a/lib/efi_selftest/efi_selftest_miniapp_exception.c +++ b/lib/efi_selftest/efi_selftest_miniapp_exception.c @@ -7,7 +7,6 @@ * This EFI application triggers an exception. */ -#include <common.h> #include <efi_api.h> #include <host_arch.h> diff --git a/lib/efi_selftest/efi_selftest_miniapp_exit.c b/lib/efi_selftest/efi_selftest_miniapp_exit.c index 1c42d6dd400..8b2e60cc711 100644 --- a/lib/efi_selftest/efi_selftest_miniapp_exit.c +++ b/lib/efi_selftest/efi_selftest_miniapp_exit.c @@ -8,7 +8,6 @@ * It uses the Exit boot service to return. */ -#include <common.h> #include <efi_selftest.h> static efi_guid_t loaded_image_protocol_guid = EFI_LOADED_IMAGE_PROTOCOL_GUID; diff --git a/lib/efi_selftest/efi_selftest_miniapp_return.c b/lib/efi_selftest/efi_selftest_miniapp_return.c index 45366aa9c63..8792d78ab30 100644 --- a/lib/efi_selftest/efi_selftest_miniapp_return.c +++ b/lib/efi_selftest/efi_selftest_miniapp_return.c @@ -8,7 +8,6 @@ * It returns directly without calling the Exit boot service. */ -#include <common.h> #include <efi_api.h> /* diff --git a/lib/elf.c b/lib/elf.c index 0476b2614c3..9a794f9cba8 100644 --- a/lib/elf.c +++ b/lib/elf.c @@ -3,7 +3,6 @@ Copyright (c) 2001 William L. Pitts */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <elf.h> diff --git a/lib/errno_str.c b/lib/errno_str.c index 2e5f4a887d5..752d4eb47aa 100644 --- a/lib/errno_str.c +++ b/lib/errno_str.c @@ -4,8 +4,8 @@ * * SDPX-License-Identifier: GPL-2.0+ */ -#include <common.h> #include <errno.h> +#include <linux/kernel.h> #define ERRNO_MSG(errno, msg) msg #define SAME_AS(x) (const char *)&errno_message[x] diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 7a691676483..4016bf3c113 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -7,7 +7,6 @@ */ #ifndef USE_HOSTCC -#include <common.h> #include <boot_fit.h> #include <display_options.h> #include <dm.h> diff --git a/lib/fdtdec_common.c b/lib/fdtdec_common.c index ddaca0087e1..ca36ff15952 100644 --- a/lib/fdtdec_common.c +++ b/lib/fdtdec_common.c @@ -8,7 +8,6 @@ */ #ifndef USE_HOSTCC -#include <common.h> #include <log.h> #include <linux/libfdt.h> #include <fdtdec.h> diff --git a/lib/fdtdec_test.c b/lib/fdtdec_test.c index 85351c75ca2..1e4d5fc8326 100644 --- a/lib/fdtdec_test.c +++ b/lib/fdtdec_test.c @@ -6,7 +6,6 @@ * Copyright (c) 2011 The Chromium OS Authors. */ -#include <common.h> #include <command.h> #include <fdtdec.h> #include <linux/libfdt.h> diff --git a/lib/getopt.c b/lib/getopt.c index 8b4515dc196..e9175e2fff4 100644 --- a/lib/getopt.c +++ b/lib/getopt.c @@ -8,9 +8,9 @@ #define LOG_CATEGORY LOGC_CORE -#include <common.h> #include <getopt.h> #include <log.h> +#include <linux/string.h> void getopt_init_state(struct getopt_state *gs) { diff --git a/lib/gunzip.c b/lib/gunzip.c index 932e3e8036d..e71d8d00ccb 100644 --- a/lib/gunzip.c +++ b/lib/gunzip.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <blk.h> #include <command.h> #include <console.h> diff --git a/lib/gzip.c b/lib/gzip.c index 2595b2d04b4..5d9c19598d5 100644 --- a/lib/gzip.c +++ b/lib/gzip.c @@ -4,7 +4,6 @@ * Lei Wen <leiwen@marvell.com>, Marvell Inc. */ -#include <common.h> #include <watchdog.h> #include <command.h> #include <gzip.h> diff --git a/lib/hang.c b/lib/hang.c index 2735774f9a4..3cfb06e9ca8 100644 --- a/lib/hang.c +++ b/lib/hang.c @@ -7,9 +7,9 @@ * u-boot. */ -#include <common.h> #include <bootstage.h> #include <hang.h> +#include <stdio.h> #include <os.h> /** diff --git a/lib/hash-checksum.c b/lib/hash-checksum.c index 68c290d64d8..1970a741294 100644 --- a/lib/hash-checksum.c +++ b/lib/hash-checksum.c @@ -4,7 +4,6 @@ */ #ifndef USE_HOSTCC -#include <common.h> #include <fdtdec.h> #include <asm/byteorder.h> #include <linux/errno.h> diff --git a/lib/hashtable.c b/lib/hashtable.c index f2d36bd34b4..a0060f6a0d6 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -30,7 +30,6 @@ # endif # endif #else /* U-Boot build */ -# include <common.h> # include <linux/string.h> # include <linux/ctype.h> #endif diff --git a/lib/hexdump.c b/lib/hexdump.c index 149c93ead8b..33e3e6e5182 100644 --- a/lib/hexdump.c +++ b/lib/hexdump.c @@ -8,9 +8,9 @@ * more details. */ -#include <common.h> #include <hexdump.h> #include <mapmem.h> +#include <vsprintf.h> #include <linux/ctype.h> #include <linux/compat.h> #include <linux/log2.h> diff --git a/lib/image-sparse.c b/lib/image-sparse.c index 323aad981c6..f8289064692 100644 --- a/lib/image-sparse.c +++ b/lib/image-sparse.c @@ -35,7 +35,6 @@ */ #include <config.h> -#include <common.h> #include <blk.h> #include <image-sparse.h> #include <div64.h> diff --git a/lib/initcall.c b/lib/initcall.c index 33b7d761dc7..ce317af213a 100644 --- a/lib/initcall.c +++ b/lib/initcall.c @@ -3,7 +3,6 @@ * Copyright (c) 2013 The Chromium OS Authors. */ -#include <common.h> #include <efi.h> #include <initcall.h> #include <log.h> diff --git a/lib/libavb/avb_sysdeps.h b/lib/libavb/avb_sysdeps.h index f52428cc622..aece8e0a018 100644 --- a/lib/libavb/avb_sysdeps.h +++ b/lib/libavb/avb_sysdeps.h @@ -19,7 +19,9 @@ extern "C" { * like uint8_t, uint64_t, and bool (with |false|, |true| keywords) * must be present. */ -#include <common.h> +#include <stdio.h> +#include <stdbool.h> +#include <linux/types.h> /* If you don't have gcc or clang, these attribute macros may need to * be adjusted. diff --git a/lib/linux_compat.c b/lib/linux_compat.c index c83426f59dc..985e88eb397 100644 --- a/lib/linux_compat.c +++ b/lib/linux_compat.c @@ -1,5 +1,4 @@ -#include <common.h> #include <malloc.h> #include <memalign.h> #include <asm/cache.h> diff --git a/lib/list_sort.c b/lib/list_sort.c index 1c9e0617327..a6e54d5bc46 100644 --- a/lib/list_sort.c +++ b/lib/list_sort.c @@ -6,7 +6,6 @@ #include <linux/slab.h> #else #include <linux/compat.h> -#include <common.h> #include <malloc.h> #include <linux/printk.h> #endif diff --git a/lib/lmb.c b/lib/lmb.c index da924c6789a..44f98205310 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -6,7 +6,6 @@ * Copyright (C) 2001 Peter Bergner. */ -#include <common.h> #include <efi_loader.h> #include <image.h> #include <mapmem.h> diff --git a/lib/lz4.c b/lib/lz4.c index 5337842126c..d365dc727cf 100644 --- a/lib/lz4.c +++ b/lib/lz4.c @@ -27,7 +27,6 @@ * - LZ4 homepage : http://www.lz4.org * - LZ4 source repository : https://github.com/lz4/lz4 */ -#include <common.h> #include <compiler.h> #include <linux/kernel.h> #include <linux/types.h> diff --git a/lib/lz4_wrapper.c b/lib/lz4_wrapper.c index 67dea2ff390..4d48e7b0e8b 100644 --- a/lib/lz4_wrapper.c +++ b/lib/lz4_wrapper.c @@ -3,7 +3,6 @@ * Copyright 2015 Google Inc. */ -#include <common.h> #include <compiler.h> #include <image.h> #include <linux/kernel.h> diff --git a/lib/lzma/LzmaDec.c b/lib/lzma/LzmaDec.c index a90b35c6a99..1da3f0a14a7 100644 --- a/lib/lzma/LzmaDec.c +++ b/lib/lzma/LzmaDec.c @@ -2,7 +2,6 @@ 2009-09-20 : Igor Pavlov : Public domain */ #include <config.h> -#include <common.h> #include <watchdog.h> #include "LzmaDec.h" diff --git a/lib/lzma/LzmaTools.c b/lib/lzma/LzmaTools.c index 55f64cd2890..400d606784e 100644 --- a/lib/lzma/LzmaTools.c +++ b/lib/lzma/LzmaTools.c @@ -18,7 +18,6 @@ */ #include <config.h> -#include <common.h> #include <log.h> #include <watchdog.h> diff --git a/lib/lzo/lzo1x_decompress.c b/lib/lzo/lzo1x_decompress.c index 65fef0b0eb9..5d70fa41337 100644 --- a/lib/lzo/lzo1x_decompress.c +++ b/lib/lzo/lzo1x_decompress.c @@ -11,8 +11,9 @@ * Richard Purdie <rpurdie@openedhand.com> */ -#include <common.h> +#include <linux/kernel.h> #include <linux/lzo.h> +#include <linux/string.h> #include <asm/byteorder.h> #include <asm/unaligned.h> #include "lzodefs.h" diff --git a/lib/md5.c b/lib/md5.c index 1636ab93661..faf3f78ab1e 100644 --- a/lib/md5.c +++ b/lib/md5.c @@ -28,7 +28,6 @@ #include "compiler.h" #ifndef USE_HOSTCC -#include <common.h> #include <watchdog.h> #endif /* USE_HOSTCC */ #include <u-boot/md5.h> diff --git a/lib/membuff.c b/lib/membuff.c index 36dc43a523f..3c6c0ae125c 100644 --- a/lib/membuff.c +++ b/lib/membuff.c @@ -6,7 +6,6 @@ * Copyright (c) 1992 Simon Glass */ -#include <common.h> #include <errno.h> #include <log.h> #include <malloc.h> diff --git a/lib/net_utils.c b/lib/net_utils.c index 4283c13a31d..c70fef0d991 100644 --- a/lib/net_utils.c +++ b/lib/net_utils.c @@ -9,9 +9,9 @@ * Copyright 2009 Dirk Behme, dirk.behme@googlemail.com */ -#include <common.h> #include <net.h> #include <net6.h> +#include <vsprintf.h> struct in_addr string_to_ip(const char *s) { diff --git a/lib/of_live.c b/lib/of_live.c index 812c488f606..90b9459ede3 100644 --- a/lib/of_live.c +++ b/lib/of_live.c @@ -10,7 +10,6 @@ #define LOG_CATEGORY LOGC_DT -#include <common.h> #include <abuf.h> #include <log.h> #include <linux/libfdt.h> diff --git a/lib/optee/optee.c b/lib/optee/optee.c index b0362240446..393f2715a9c 100644 --- a/lib/optee/optee.c +++ b/lib/optee/optee.c @@ -4,7 +4,6 @@ * Bryan O'Donoghue <bryan.odonoghue@linaro.org> */ -#include <common.h> #include <fdtdec.h> #include <image.h> #include <log.h> diff --git a/lib/panic.c b/lib/panic.c index 66ae17f3df9..0f578b5b513 100644 --- a/lib/panic.c +++ b/lib/panic.c @@ -9,7 +9,6 @@ * Wirzenius wrote this portably, Torvalds fucked it up :-) */ -#include <common.h> #include <hang.h> #if !defined(CONFIG_PANIC_HANG) #include <command.h> diff --git a/lib/physmem.c b/lib/physmem.c index fc90ce4d7cf..562c74d37f3 100644 --- a/lib/physmem.c +++ b/lib/physmem.c @@ -8,11 +8,11 @@ * Software Foundation. */ -#include <common.h> #include <log.h> #include <mapmem.h> #include <physmem.h> #include <linux/compiler.h> +#include <linux/string.h> phys_addr_t __weak arch_phys_memset(phys_addr_t s, int c, phys_size_t n) { diff --git a/lib/qsort.c b/lib/qsort.c index 2f18588dfcc..a2562c4942e 100644 --- a/lib/qsort.c +++ b/lib/qsort.c @@ -17,7 +17,6 @@ #include <log.h> #include <linux/types.h> -#include <common.h> #include <exports.h> #include <sort.h> diff --git a/lib/rand.c b/lib/rand.c index d256baf5cee..d6f2977e8dc 100644 --- a/lib/rand.c +++ b/lib/rand.c @@ -7,7 +7,6 @@ * Michael Walle <michael@walle.cc> */ -#include <common.h> #include <rand.h> static unsigned int y = 1U; diff --git a/lib/rc4.c b/lib/rc4.c index 720112d1fd8..3839924a2b2 100644 --- a/lib/rc4.c +++ b/lib/rc4.c @@ -7,9 +7,6 @@ * Rivest Cipher 4 (RC4) implementation */ -#ifndef USE_HOSTCC -#include <common.h> -#endif #include <rc4.h> void rc4_encode(unsigned char *buf, unsigned int len, const unsigned char key[16]) diff --git a/lib/rsa/rsa-keyprop.c b/lib/rsa/rsa-keyprop.c index 98855f67b89..80d0594a430 100644 --- a/lib/rsa/rsa-keyprop.c +++ b/lib/rsa/rsa-keyprop.c @@ -9,7 +9,6 @@ * Copyright (c) 2016 Thomas Pornin <pornin@bolet.org> */ -#include <common.h> #include <image.h> #include <malloc.h> #include <crypto/internal/rsa.h> diff --git a/lib/rsa/rsa-mod-exp.c b/lib/rsa/rsa-mod-exp.c index d259b2aedf2..5b3ea02f82f 100644 --- a/lib/rsa/rsa-mod-exp.c +++ b/lib/rsa/rsa-mod-exp.c @@ -4,7 +4,6 @@ */ #ifndef USE_HOSTCC -#include <common.h> #include <fdtdec.h> #include <log.h> #include <asm/types.h> diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index d20bdb58a57..858ad92a6f6 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -116,15 +116,15 @@ static int rsa_engine_get_pub_key(const char *keydir, const char *name, if (keydir) if (strstr(keydir, "object=")) snprintf(key_id, sizeof(key_id), - "pkcs11:%s;type=public", + "%s;type=public", keydir); else snprintf(key_id, sizeof(key_id), - "pkcs11:%s;object=%s;type=public", + "%s;object=%s;type=public", keydir, name); else snprintf(key_id, sizeof(key_id), - "pkcs11:object=%s;type=public", + "object=%s;type=public", name); } else if (engine_id) { if (keydir) @@ -238,15 +238,15 @@ static int rsa_engine_get_priv_key(const char *keydir, const char *name, if (keydir) if (strstr(keydir, "object=")) snprintf(key_id, sizeof(key_id), - "pkcs11:%s;type=private", + "%s;type=private", keydir); else snprintf(key_id, sizeof(key_id), - "pkcs11:%s;object=%s;type=private", + "%s;object=%s;type=private", keydir, name); else snprintf(key_id, sizeof(key_id), - "pkcs11:object=%s;type=private", + "object=%s;type=private", name); } else if (engine_id) { if (keydir && name) @@ -317,7 +317,8 @@ static int rsa_engine_init(const char *engine_id, ENGINE **pe) e = ENGINE_by_id(engine_id); if (!e) { - fprintf(stderr, "Engine isn't available\n"); + fprintf(stderr, "Engine '%s' isn't available\n", engine_id); + ERR_print_errors_fp(stderr); return -1; } diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index 2f3b3440391..1007b6979a4 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -4,7 +4,6 @@ */ #ifndef USE_HOSTCC -#include <common.h> #include <fdtdec.h> #include <log.h> #include <malloc.h> @@ -17,9 +16,9 @@ #else #include "fdt_host.h" #include "mkimage.h" +#include <linux/kconfig.h> #include <fdt_support.h> #endif -#include <linux/kconfig.h> #include <u-boot/rsa-mod-exp.h> #include <u-boot/rsa.h> diff --git a/lib/rtc-lib.c b/lib/rtc-lib.c index 1f7bdade298..46dcfba2715 100644 --- a/lib/rtc-lib.c +++ b/lib/rtc-lib.c @@ -10,7 +10,6 @@ * - January is month 1. */ -#include <common.h> #include <rtc.h> #include <linux/math64.h> diff --git a/lib/semihosting.c b/lib/semihosting.c index 831774e3566..9be5bffd301 100644 --- a/lib/semihosting.c +++ b/lib/semihosting.c @@ -4,9 +4,10 @@ * Copyright 2014 Broadcom Corporation */ -#include <common.h> #include <log.h> #include <semihosting.h> +#include <linux/errno.h> +#include <linux/string.h> #define SYSOPEN 0x01 #define SYSCLOSE 0x02 diff --git a/lib/sha1.c b/lib/sha1.c index 8d074078934..7ef536f4b5d 100644 --- a/lib/sha1.c +++ b/lib/sha1.c @@ -17,12 +17,9 @@ #endif #ifndef USE_HOSTCC -#include <common.h> -#include <linux/string.h> -#else -#include <string.h> +#include <cyclic.h> #endif /* USE_HOSTCC */ -#include <watchdog.h> +#include <string.h> #include <u-boot/sha1.h> #include <linux/compiler_attributes.h> diff --git a/lib/sha256.c b/lib/sha256.c index 4d26aea1c8c..665ba6f152e 100644 --- a/lib/sha256.c +++ b/lib/sha256.c @@ -6,12 +6,9 @@ */ #ifndef USE_HOSTCC -#include <common.h> -#include <linux/string.h> -#else -#include <string.h> +#include <cyclic.h> #endif /* USE_HOSTCC */ -#include <watchdog.h> +#include <string.h> #include <u-boot/sha256.h> #include <linux/compiler_attributes.h> diff --git a/lib/sha512.c b/lib/sha512.c index fbe8d5f5bfe..ffe2c5cd964 100644 --- a/lib/sha512.c +++ b/lib/sha512.c @@ -11,13 +11,9 @@ */ #ifndef USE_HOSTCC -#include <common.h> -#include <linux/string.h> -#else -#include <string.h> +#include <cyclic.h> #endif /* USE_HOSTCC */ #include <compiler.h> -#include <watchdog.h> #include <u-boot/sha512.h> const uint8_t sha384_der_prefix[SHA384_DER_LEN] = { diff --git a/lib/slre.c b/lib/slre.c index e1a50443e04..277a59a03a7 100644 --- a/lib/slre.c +++ b/lib/slre.c @@ -21,8 +21,8 @@ #include <string.h> #else #include <log.h> -#include <common.h> #include <linux/ctype.h> +#include <linux/string.h> #endif /* SLRE_TEST */ #include <errno.h> diff --git a/lib/smbios-parser.c b/lib/smbios-parser.c index 2b9392936b9..b578c308408 100644 --- a/lib/smbios-parser.c +++ b/lib/smbios-parser.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY LOGC_BOOT -#include <common.h> #include <smbios.h> static inline int verify_checksum(const struct smbios_entry *e) diff --git a/lib/smbios.c b/lib/smbios.c index d7f4999e8b2..45480b01af4 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -5,15 +5,17 @@ * Adapted from coreboot src/arch/x86/smbios.c */ -#include <common.h> #include <dm.h> #include <env.h> #include <linux/stringify.h> +#include <linux/string.h> #include <mapmem.h> #include <smbios.h> #include <sysinfo.h> #include <tables_csum.h> #include <version.h> +#include <malloc.h> +#include <dm/ofnode.h> #ifdef CONFIG_CPU #include <cpu.h> #include <dm/uclass-internal.h> @@ -44,6 +46,25 @@ DECLARE_GLOBAL_DATA_PTR; /** + * struct map_sysinfo - Mapping of sysinfo strings to DT + * + * @sysinfo_str: sysinfo string + * @dt_str: DT string + * @max: Max index of the tokenized string to pick. Counting starts from 0 + * + */ +struct map_sysinfo { + const char *sysinfo_str; + const char *dt_str; + int max; +}; + +static const struct map_sysinfo sysinfo_to_dt[] = { + { .sysinfo_str = "product", .dt_str = "model", 2 }, + { .sysinfo_str = "manufacturer", .dt_str = "compatible", 1 }, +}; + +/** * struct smbios_ctx - context for writing SMBIOS tables * * @node: node containing the information to write (ofnode_null() if none) @@ -87,6 +108,18 @@ struct smbios_write_method { const char *subnode_name; }; +static const struct map_sysinfo *convert_sysinfo_to_dt(const char *sysinfo_str) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(sysinfo_to_dt); i++) { + if (!strcmp(sysinfo_str, sysinfo_to_dt[i].sysinfo_str)) + return &sysinfo_to_dt[i]; + } + + return NULL; +} + /** * smbios_add_string() - add a string to the string area * @@ -102,9 +135,6 @@ static int smbios_add_string(struct smbios_ctx *ctx, const char *str) int i = 1; char *p = ctx->eos; - if (!*str) - str = "Unknown"; - for (;;) { if (!*p) { ctx->last_str = p; @@ -128,31 +158,88 @@ static int smbios_add_string(struct smbios_ctx *ctx, const char *str) } /** + * get_str_from_dt - Get a substring from a DT property. + * After finding the property in the DT, the function + * will parse comma-separated values and return the value. + * If nprop->max exceeds the number of comma-separated + * elements, the last non NULL value will be returned. + * Counting starts from zero. + * + * @nprop: sysinfo property to use + * @str: pointer to fill with data + * @size: str buffer length + */ +static +void get_str_from_dt(const struct map_sysinfo *nprop, char *str, size_t size) +{ + const char *dt_str; + int cnt = 0; + char *token; + + memset(str, 0, size); + if (!nprop || !nprop->max) + return; + + dt_str = ofnode_read_string(ofnode_root(), nprop->dt_str); + if (!dt_str) + return; + + memcpy(str, dt_str, size); + token = strtok(str, ","); + while (token && cnt < nprop->max) { + strlcpy(str, token, strlen(token) + 1); + token = strtok(NULL, ","); + cnt++; + } +} + +/** * smbios_add_prop_si() - Add a property from the devicetree or sysinfo * * Sysinfo is used if available, with a fallback to devicetree * * @ctx: context for writing the tables * @prop: property to write + * @dval: Default value to use if the string is not found or is empty * Return: 0 if not found, else SMBIOS string number (1 or more) */ static int smbios_add_prop_si(struct smbios_ctx *ctx, const char *prop, - int sysinfo_id) + int sysinfo_id, const char *dval) { + int ret; + + if (!dval || !*dval) + dval = "Unknown"; + + if (!prop) + return smbios_add_string(ctx, dval); + if (sysinfo_id && ctx->dev) { char val[SMBIOS_STR_MAX]; - int ret; ret = sysinfo_get_str(ctx->dev, sysinfo_id, sizeof(val), val); if (!ret) return smbios_add_string(ctx, val); } if (IS_ENABLED(CONFIG_OF_CONTROL)) { - const char *str; + const char *str = NULL; + char str_dt[128] = { 0 }; + /* + * If the node is not valid fallback and try the entire DT + * so we can at least fill in manufacturer and board type + */ + if (ofnode_valid(ctx->node)) { + str = ofnode_read_string(ctx->node, prop); + } else { + const struct map_sysinfo *nprop; + + nprop = convert_sysinfo_to_dt(prop); + get_str_from_dt(nprop, str_dt, sizeof(str_dt)); + str = (const char *)str_dt; + } - str = ofnode_read_string(ctx->node, prop); - if (str) - return smbios_add_string(ctx, str); + ret = smbios_add_string(ctx, str && *str ? str : dval); + return ret; } return 0; @@ -161,12 +248,15 @@ static int smbios_add_prop_si(struct smbios_ctx *ctx, const char *prop, /** * smbios_add_prop() - Add a property from the devicetree * - * @prop: property to write + * @prop: property to write. The default string will be written if + * prop is NULL + * @dval: Default value to use if the string is not found or is empty * Return: 0 if not found, else SMBIOS string number (1 or more) */ -static int smbios_add_prop(struct smbios_ctx *ctx, const char *prop) +static int smbios_add_prop(struct smbios_ctx *ctx, const char *prop, + const char *dval) { - return smbios_add_prop_si(ctx, prop, SYSINFO_ID_NONE); + return smbios_add_prop_si(ctx, prop, SYSINFO_ID_NONE, dval); } static void smbios_set_eos(struct smbios_ctx *ctx, char *eos) @@ -228,11 +318,9 @@ static int smbios_write_type0(ulong *current, int handle, memset(t, 0, sizeof(struct smbios_type0)); fill_smbios_header(t, SMBIOS_BIOS_INFORMATION, len, handle); smbios_set_eos(ctx, t->eos); - t->vendor = smbios_add_string(ctx, "U-Boot"); + t->vendor = smbios_add_prop(ctx, NULL, "U-Boot"); - t->bios_ver = smbios_add_prop(ctx, "version"); - if (!t->bios_ver) - t->bios_ver = smbios_add_string(ctx, PLAIN_VERSION); + t->bios_ver = smbios_add_prop(ctx, "version", PLAIN_VERSION); if (t->bios_ver) gd->smbios_version = ctx->last_str; log_debug("smbios_version = %p: '%s'\n", gd->smbios_version, @@ -241,7 +329,7 @@ static int smbios_write_type0(ulong *current, int handle, print_buffer((ulong)gd->smbios_version, gd->smbios_version, 1, strlen(gd->smbios_version) + 1, 0); #endif - t->bios_release_date = smbios_add_string(ctx, U_BOOT_DMI_DATE); + t->bios_release_date = smbios_add_prop(ctx, NULL, U_BOOT_DMI_DATE); #ifdef CONFIG_ROM_SIZE t->bios_rom_size = (CONFIG_ROM_SIZE / 65536) - 1; #endif @@ -280,22 +368,19 @@ static int smbios_write_type1(ulong *current, int handle, memset(t, 0, sizeof(struct smbios_type1)); fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle); smbios_set_eos(ctx, t->eos); - t->manufacturer = smbios_add_prop(ctx, "manufacturer"); - if (!t->manufacturer) - t->manufacturer = smbios_add_string(ctx, "Unknown"); - t->product_name = smbios_add_prop(ctx, "product"); - if (!t->product_name) - t->product_name = smbios_add_string(ctx, "Unknown Product"); + t->manufacturer = smbios_add_prop(ctx, "manufacturer", "Unknown"); + t->product_name = smbios_add_prop(ctx, "product", "Unknown"); t->version = smbios_add_prop_si(ctx, "version", - SYSINFO_ID_SMBIOS_SYSTEM_VERSION); + SYSINFO_ID_SMBIOS_SYSTEM_VERSION, + "Unknown"); if (serial_str) { - t->serial_number = smbios_add_string(ctx, serial_str); + t->serial_number = smbios_add_prop(ctx, NULL, serial_str); strncpy((char *)t->uuid, serial_str, sizeof(t->uuid)); } else { - t->serial_number = smbios_add_prop(ctx, "serial"); + t->serial_number = smbios_add_prop(ctx, "serial", "Unknown"); } - t->sku_number = smbios_add_prop(ctx, "sku"); - t->family = smbios_add_prop(ctx, "family"); + t->sku_number = smbios_add_prop(ctx, "sku", "Unknown"); + t->family = smbios_add_prop(ctx, "family", "Unknown"); len = t->length + smbios_string_table_len(ctx); *current += len; @@ -314,15 +399,12 @@ static int smbios_write_type2(ulong *current, int handle, memset(t, 0, sizeof(struct smbios_type2)); fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle); smbios_set_eos(ctx, t->eos); - t->manufacturer = smbios_add_prop(ctx, "manufacturer"); - if (!t->manufacturer) - t->manufacturer = smbios_add_string(ctx, "Unknown"); - t->product_name = smbios_add_prop(ctx, "product"); - if (!t->product_name) - t->product_name = smbios_add_string(ctx, "Unknown Product"); + t->manufacturer = smbios_add_prop(ctx, "manufacturer", "Unknown"); + t->product_name = smbios_add_prop(ctx, "product", "Unknown"); t->version = smbios_add_prop_si(ctx, "version", - SYSINFO_ID_SMBIOS_BASEBOARD_VERSION); - t->asset_tag_number = smbios_add_prop(ctx, "asset-tag"); + SYSINFO_ID_SMBIOS_BASEBOARD_VERSION, + "Unknown"); + t->asset_tag_number = smbios_add_prop(ctx, "asset-tag", "Unknown"); t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING; t->board_type = SMBIOS_BOARD_MOTHERBOARD; @@ -343,9 +425,7 @@ static int smbios_write_type3(ulong *current, int handle, memset(t, 0, sizeof(struct smbios_type3)); fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle); smbios_set_eos(ctx, t->eos); - t->manufacturer = smbios_add_prop(ctx, "manufacturer"); - if (!t->manufacturer) - t->manufacturer = smbios_add_string(ctx, "Unknown"); + t->manufacturer = smbios_add_prop(ctx, "manufacturer", "Unknown"); t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP; t->bootup_state = SMBIOS_STATE_SAFE; t->power_supply_state = SMBIOS_STATE_SAFE; @@ -388,8 +468,8 @@ static void smbios_write_type4_dm(struct smbios_type4 *t, #endif t->processor_family = processor_family; - t->processor_manufacturer = smbios_add_string(ctx, vendor); - t->processor_version = smbios_add_string(ctx, name); + t->processor_manufacturer = smbios_add_prop(ctx, NULL, vendor); + t->processor_version = smbios_add_prop(ctx, NULL, name); } static int smbios_write_type4(ulong *current, int handle, diff --git a/lib/strto.c b/lib/strto.c index 154921165cb..5157332d6c1 100644 --- a/lib/strto.c +++ b/lib/strto.c @@ -9,9 +9,9 @@ * Wirzenius wrote this portably, Torvalds fucked it up :-) */ -#include <common.h> #include <errno.h> #include <malloc.h> +#include <vsprintf.h> #include <linux/ctype.h> /* from lib/kstrtox.c */ diff --git a/lib/tables_csum.c b/lib/tables_csum.c index e2630d57d91..636aa596768 100644 --- a/lib/tables_csum.c +++ b/lib/tables_csum.c @@ -3,8 +3,7 @@ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> -#include <linux/ctype.h> +#include <linux/types.h> u8 table_compute_checksum(void *v, int len) { diff --git a/lib/time.c b/lib/time.c index 00f4a1ac8fb..872f73d521e 100644 --- a/lib/time.c +++ b/lib/time.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <clock_legacy.h> #include <bootstage.h> #include <dm.h> diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c index f661fc65054..9a70c6095b3 100644 --- a/lib/tiny-printf.c +++ b/lib/tiny-printf.c @@ -8,7 +8,6 @@ * Copyright (C) 2004,2008 Kustaa Nyholm */ -#include <common.h> #include <log.h> #include <serial.h> #include <stdarg.h> diff --git a/lib/tpm-common.c b/lib/tpm-common.c index 82ffdc5341b..b592c22bfc1 100644 --- a/lib/tpm-common.c +++ b/lib/tpm-common.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_TPM -#include <common.h> #include <dm.h> #include <log.h> #include <asm/unaligned.h> diff --git a/lib/tpm-v1.c b/lib/tpm-v1.c index 60a18ca5040..e66023da5e6 100644 --- a/lib/tpm-v1.c +++ b/lib/tpm-v1.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY UCLASS_TPM -#include <common.h> #include <dm.h> #include <log.h> #include <asm/unaligned.h> diff --git a/lib/tpm-v2.c b/lib/tpm-v2.c index bd0fb078dc3..68eaaa639f8 100644 --- a/lib/tpm-v2.c +++ b/lib/tpm-v2.c @@ -5,7 +5,6 @@ * Author: Miquel Raynal <miquel.raynal@bootlin.com> */ -#include <common.h> #include <dm.h> #include <dm/of_access.h> #include <tpm_api.h> diff --git a/lib/tpm_api.c b/lib/tpm_api.c index 3ef5e811794..39a5121e302 100644 --- a/lib/tpm_api.c +++ b/lib/tpm_api.c @@ -3,7 +3,6 @@ * Copyright 2019 Google LLC */ -#include <common.h> #include <dm.h> #include <log.h> #include <tpm_api.h> diff --git a/lib/trace.c b/lib/trace.c index 4874bef861b..cabbe47b58a 100644 --- a/lib/trace.c +++ b/lib/trace.c @@ -3,10 +3,10 @@ * Copyright (c) 2012 The Chromium OS Authors. */ -#include <common.h> #include <mapmem.h> #include <time.h> #include <trace.h> +#include <linux/errno.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/sections.h> diff --git a/lib/uuid.c b/lib/uuid.c index afb40bff507..0be22bc05f7 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -9,7 +9,6 @@ #define LOG_CATEGOT LOGC_CORE -#include <common.h> #include <command.h> #include <efi_api.h> #include <env.h> @@ -18,7 +17,6 @@ #include <uuid.h> #include <linux/ctype.h> #include <errno.h> -#include <common.h> #include <asm/io.h> #include <part_efi.h> #include <malloc.h> diff --git a/lib/vsprintf.c b/lib/vsprintf.c index e14c6ca9f96..27ea9c907a3 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -13,7 +13,6 @@ * from hush: simple_itoa() was lifted from boa-0.93.15 */ -#include <common.h> #include <charset.h> #include <efi_loader.h> #include <div64.h> diff --git a/lib/zlib/zlib.h b/lib/zlib/zlib.h index af3703e6d77..560e7be97d3 100644 --- a/lib/zlib/zlib.h +++ b/lib/zlib/zlib.h @@ -2,7 +2,6 @@ #ifndef __GLUE_ZLIB_H__ #define __GLUE_ZLIB_H__ -#include <common.h> #include <linux/compiler.h> #include <asm/unaligned.h> #include <watchdog.h> diff --git a/lib/zstd/zstd.c b/lib/zstd/zstd.c index 3a2abc83673..14bde369068 100644 --- a/lib/zstd/zstd.c +++ b/lib/zstd/zstd.c @@ -5,10 +5,10 @@ #define LOG_CATEGORY LOGC_BOOT -#include <common.h> #include <abuf.h> #include <log.h> #include <malloc.h> +#include <linux/errno.h> #include <linux/zstd.h> int zstd_decompress(struct abuf *in, struct abuf *out) diff --git a/net/arp.h b/net/arp.h index 25b3c00d5c5..c50885fb9a5 100644 --- a/net/arp.h +++ b/net/arp.h @@ -12,8 +12,6 @@ #ifndef __ARP_H__ #define __ARP_H__ -#include <common.h> - extern struct in_addr net_arp_wait_packet_ip; /* MAC address of waiting packet's destination */ extern uchar *arp_wait_packet_ethaddr; diff --git a/net/link_local.h b/net/link_local.h index bb998164df9..d8701255142 100644 --- a/net/link_local.h +++ b/net/link_local.h @@ -10,15 +10,12 @@ * Licensed under the GPL v2 or later */ -#if defined(CONFIG_CMD_LINK_LOCAL) - #ifndef __LINK_LOCAL_H__ #define __LINK_LOCAL_H__ -#include <common.h> +struct arp_hdr; void link_local_receive_arp(struct arp_hdr *arp, int len); void link_local_start(void); #endif /* __LINK_LOCAL_H__ */ -#endif diff --git a/net/net_rand.h b/net/net_rand.h index 6a52cda85e0..d3c5559adfd 100644 --- a/net/net_rand.h +++ b/net/net_rand.h @@ -9,7 +9,6 @@ #ifndef __NET_RAND_H__ #define __NET_RAND_H__ -#include <common.h> #include <dm/uclass.h> #include <rng.h> diff --git a/net/ping.h b/net/ping.h index 7b6f4e566db..76ac225fc07 100644 --- a/net/ping.h +++ b/net/ping.h @@ -12,7 +12,6 @@ #ifndef __PING_H__ #define __PING_H__ -#include <common.h> #include <net.h> /* diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 8dc6ec82cd5..16bbc277a9f 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -339,7 +339,12 @@ cmd_capsule_esl_gen = \ $(shell sed "s:ESL_BIN_FILE:$(capsule_esl_path):" $(capsule_esl_input_file) > $@) $(obj)/.capsule_esl.dtsi: FORCE +ifeq ($(CONFIG_EFI_CAPSULE_ESL_FILE),"") + $(error "CONFIG_EFI_CAPSULE_ESL_FILE is empty, EFI capsule authentication \ + public key must be specified when CONFIG_EFI_CAPSULE_AUTHENTICATE is enabled") +else $(call cmd_capsule_esl_gen) +endif capsule_esl_input_file=$(srctree)/lib/efi_loader/capsule_esl.dtsi.in capsule_esl_dtsi = .capsule_esl.dtsi diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index 597f624d036..a9b555c7794 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -374,7 +374,7 @@ static int bootflow_system(struct unit_test_state *uts) { struct udevice *bootstd, *dev; - if (!IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR)) + if (!IS_ENABLED(CONFIG_BOOTEFI_BOOTMGR)) return -EAGAIN; ut_assertok(uclass_first_device_err(UCLASS_BOOTSTD, &bootstd)); ut_assertok(device_bind(bootstd, DM_DRIVER_GET(bootmeth_efi_mgr), @@ -1095,6 +1095,10 @@ static int bootflow_cmdline(struct unit_test_state *uts) ut_asserteq(0, run_command("bootflow cmdline get mary", 0)); ut_assert_nextline_empty(); + ut_asserteq(0, run_command("bootflow cmdline set mary abc", 0)); + ut_asserteq(0, run_command("bootflow cmdline set mary", 0)); + ut_assert_nextline_empty(); + ut_assert_console_end(); return 0; diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c index e4ebb93cdad..61dad8d8527 100644 --- a/test/dm/clk_ccf.c +++ b/test/dm/clk_ccf.c @@ -19,16 +19,18 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) { struct clk *clk, *pclk; - struct udevice *dev; + struct udevice *dev, *test_dev; long long rate; int ret; #if CONFIG_IS_ENABLED(CLK_CCF) + struct clk clk_ccf; const char *clkname; int clkid, i; #endif /* Get the device using the clk device */ ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test", &test_dev)); /* Test for clk_get_by_id() */ ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk); @@ -63,6 +65,9 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) rate = clk_get_parent_rate(clk); ut_asserteq(rate, 60000000); + rate = clk_set_rate(clk, 60000000); + ut_asserteq(rate, -ENOSYS); + rate = clk_get_rate(clk); ut_asserteq(rate, 60000000); @@ -87,6 +92,9 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) ut_asserteq_str("pll3_80m", pclk->dev->name); ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags); + rate = clk_set_rate(clk, 80000000); + ut_asserteq(rate, -ENOSYS); + rate = clk_get_rate(clk); ut_asserteq(rate, 80000000); @@ -108,13 +116,23 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) rate = clk_get_rate(clk); ut_asserteq(rate, 60000000); + rate = clk_set_rate(clk, 60000000); + ut_asserteq(rate, 60000000); + #if CONFIG_IS_ENABLED(CLK_CCF) /* Test clk tree enable/disable */ + + ret = clk_get_by_index(test_dev, SANDBOX_CLK_TEST_ID_I2C_ROOT, &clk_ccf); + ut_assertok(ret); + ut_asserteq_str("clk-ccf", clk_ccf.dev->name); + ut_asserteq(clk_ccf.id, SANDBOX_CLK_I2C_ROOT); + ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk); ut_assertok(ret); ut_asserteq_str("i2c_root", clk->dev->name); + ut_asserteq(clk->id, SANDBOX_CLK_I2C_ROOT); - ret = clk_enable(clk); + ret = clk_enable(&clk_ccf); ut_assertok(ret); ret = sandbox_clk_enable_count(clk); diff --git a/test/dm/scmi.c b/test/dm/scmi.c index e80667ef72a..adf36ffaab1 100644 --- a/test/dm/scmi.c +++ b/test/dm/scmi.c @@ -23,7 +23,6 @@ #include <asm/scmi_test.h> #include <dm/device-internal.h> #include <dm/test.h> -#include <linux/kconfig.h> #include <power/regulator.h> #include <test/ut.h> diff --git a/test/py/tests/test_fit.py b/test/py/tests/test_fit.py index 04f64fd4bc6..8f9c4b26411 100755 --- a/test/py/tests/test_fit.py +++ b/test/py/tests/test_fit.py @@ -339,6 +339,14 @@ def test_fit(u_boot_console): 'U-Boot loaded FDT from offset %#x, FDT is actually at %#x' % (fit_offset, real_fit_offset)) + # Check if bootargs strings substitution works + output = cons.run_command_list([ + 'env set bootargs \\\"\'my_boot_var=${foo}\'\\\"', + 'env set foo bar', + 'bootm prep', + 'env print bootargs']) + assert 'bootargs="my_boot_var=bar"' in output, "Bootargs strings not substituted" + # Now a kernel and an FDT with cons.log.section('Kernel + FDT load'): params['fdt_load'] = 'load = <%#x>;' % params['fdt_addr'] diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c index b8fc6069b58..6a261ff549d 100644 --- a/tools/mkeficapsule.c +++ b/tools/mkeficapsule.c @@ -16,7 +16,6 @@ #include <sys/stat.h> #include <sys/types.h> #include <uuid/uuid.h> -#include <linux/kconfig.h> #include <gnutls/gnutls.h> #include <gnutls/pkcs7.h> |