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-rw-r--r--.azure-pipelines.yml3
-rw-r--r--.gitlab-ci.yml3
-rw-r--r--MAINTAINERS5
-rw-r--r--Makefile4
-rw-r--r--arch/arm/Kconfig108
-rw-r--r--arch/arm/cpu/armv7/iproc-common/armpll.c29
-rw-r--r--arch/arm/dts/Makefile3
-rw-r--r--arch/arm/dts/at91-sama5d27_som1_ek.dts3
-rw-r--r--arch/arm/dts/at91-sama5d27_wlsom1_ek.dts3
-rw-r--r--arch/arm/dts/at91-sama5d2_ptc_ek.dts2
-rw-r--r--arch/arm/dts/at91-sama5d2_xplained.dts3
-rw-r--r--arch/arm/dts/at91-sama5d3_xplained.dts2
-rw-r--r--arch/arm/dts/at91-sama5d4_xplained.dts2
-rw-r--r--arch/arm/dts/dragonboard410c.dts4
-rw-r--r--arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi7
-rw-r--r--arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts40
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi9
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi9
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi9
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi9
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi9
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi9
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi9
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi9
-rw-r--r--arch/arm/dts/fsl-ls1028a-qds.dtsi2
-rw-r--r--arch/arm/dts/fsl-ls1028a.dtsi12
-rw-r--r--arch/arm/dts/lpc3250-ea3250-u-boot.dtsi15
-rw-r--r--arch/arm/dts/lpc3250-ea3250.dts273
-rw-r--r--arch/arm/dts/lpc32xx.dtsi508
-rw-r--r--arch/arm/dts/sam9x60ek.dts2
-rw-r--r--arch/arm/dts/synquacer-sc2a11-caches.dtsi73
-rw-r--r--arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi75
-rw-r--r--arch/arm/dts/synquacer-sc2a11-developerbox.dts56
-rw-r--r--arch/arm/dts/synquacer-sc2a11.dtsi595
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/config.h4
-rw-r--r--arch/arm/include/asm/gpio.h8
-rw-r--r--arch/arm/mach-lpc32xx/Kconfig4
-rw-r--r--arch/arm/mach-lpc32xx/devices.c3
-rw-r--r--arch/arm/mach-snapdragon/clock-snapdragon.c10
-rw-r--r--arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h2
-rw-r--r--arch/powerpc/cpu/mpc83xx/pci.c2
-rw-r--r--arch/powerpc/dts/mpc8379erdb.dts52
-rw-r--r--arch/riscv/Kconfig4
-rw-r--r--arch/riscv/cpu/fu740/Kconfig3
-rw-r--r--arch/riscv/dts/Makefile3
-rw-r--r--arch/riscv/dts/fu740-c000-u-boot.dtsi4
-rw-r--r--arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi1489
-rw-r--r--arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi7
-rw-r--r--arch/riscv/dts/hifive-unmatched-a00-rev1.dts4
-rw-r--r--arch/riscv/dts/openpiton-riscv64.dts153
-rw-r--r--arch/riscv/include/asm/arch-fu740/eeprom.h15
-rw-r--r--arch/x86/cpu/cpu.c2
-rw-r--r--arch/x86/lib/bios.c2
-rw-r--r--board/BuS/eb_cpu5282/eb_cpu5282.c4
-rw-r--r--board/Seagate/dockstar/dockstar.c2
-rw-r--r--board/Seagate/goflexhome/goflexhome.c2
-rw-r--r--board/armltd/integrator/Makefile1
-rw-r--r--board/armltd/integrator/integrator.c1
-rw-r--r--board/armltd/integrator/pci.c462
-rw-r--r--board/armltd/integrator/pci_v3.h187
-rw-r--r--board/bosch/shc/board.c6
-rw-r--r--board/buffalo/lsxl/lsxl.c2
-rw-r--r--board/ea/ea-lpc3250devkitv2/Kconfig15
-rw-r--r--board/ea/ea-lpc3250devkitv2/MAINTAINERS9
-rw-r--r--board/ea/ea-lpc3250devkitv2/Makefile4
-rw-r--r--board/ea/ea-lpc3250devkitv2/README.rst186
-rw-r--r--board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c41
-rw-r--r--board/freescale/mpc837xerdb/mpc837xerdb.c11
-rw-r--r--board/freescale/t102xrdb/cpld.h2
-rw-r--r--board/freescale/t104xrdb/cpld.h3
-rw-r--r--board/freescale/t208xrdb/cpld.h2
-rw-r--r--board/k+p/kp_imx53/kp_imx53.c2
-rw-r--r--board/openpiton/riscv64/Kconfig40
-rw-r--r--board/openpiton/riscv64/MAINTAINERS9
-rw-r--r--board/openpiton/riscv64/Makefile5
-rw-r--r--board/openpiton/riscv64/openpiton-riscv64.c33
-rw-r--r--board/sifive/unmatched/Kconfig1
-rw-r--r--board/sifive/unmatched/Makefile1
-rw-r--r--board/sifive/unmatched/hifive-platform-i2c-eeprom.c574
-rw-r--r--board/sifive/unmatched/spl.c28
-rw-r--r--board/socionext/developerbox/Kconfig36
-rw-r--r--board/socionext/developerbox/MAINTAINERS14
-rw-r--r--board/socionext/developerbox/Makefile9
-rw-r--r--board/socionext/developerbox/developerbox.c146
-rw-r--r--board/st/stv0991/stv0991.c2
-rw-r--r--board/timll/devkit3250/devkit3250.c2
-rw-r--r--board/timll/devkit3250/devkit3250_spl.c2
-rw-r--r--board/work-microwave/work_92105/work_92105.c2
-rw-r--r--board/work-microwave/work_92105/work_92105_spl.c2
-rw-r--r--cmd/net.c46
-rw-r--r--common/init/board_init.c2
-rw-r--r--common/spl/spl.c2
-rw-r--r--configs/MPC837XERDB_defconfig18
-rw-r--r--configs/devkit3250_defconfig3
-rw-r--r--configs/ea-lpc3250devkitv2_defconfig26
-rw-r--r--configs/integratorap_cm720t_defconfig4
-rw-r--r--configs/integratorap_cm920t_defconfig4
-rw-r--r--configs/integratorap_cm926ejs_defconfig4
-rw-r--r--configs/integratorap_cm946es_defconfig4
-rw-r--r--configs/openpiton_riscv64_defconfig76
-rw-r--r--configs/openpiton_riscv64_spl_defconfig87
-rw-r--r--configs/sifive_unleashed_defconfig1
-rw-r--r--configs/sifive_unmatched_defconfig5
-rw-r--r--configs/synquacer_developerbox_defconfig129
-rw-r--r--configs/work_92105_defconfig3
-rw-r--r--doc/board/emulation/qemu_capsule_update.rst11
-rw-r--r--doc/board/index.rst2
-rw-r--r--doc/board/openpiton/index.rst9
-rw-r--r--doc/board/openpiton/riscv64.rst376
-rw-r--r--doc/board/socionext/developerbox.rst87
-rw-r--r--doc/board/socionext/index.rst9
-rw-r--r--drivers/ata/ahci-pci.c2
-rw-r--r--drivers/clk/sifive/fu740-prci.c6
-rw-r--r--drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h10
-rw-r--r--drivers/i2c/Kconfig13
-rw-r--r--drivers/i2c/Makefile1
-rw-r--r--drivers/i2c/lpc32xx_i2c.c15
-rw-r--r--drivers/i2c/synquacer_i2c.c338
-rw-r--r--drivers/mmc/Kconfig19
-rw-r--r--drivers/mmc/Makefile2
-rw-r--r--drivers/mmc/f_sdh30.c81
-rw-r--r--drivers/mmc/piton_mmc.c161
-rw-r--r--drivers/net/Kconfig17
-rw-r--r--drivers/net/dwc_eth_qos.c2
-rw-r--r--drivers/net/fsl_enetc.c59
-rw-r--r--drivers/net/fsl_enetc.h7
-rw-r--r--drivers/net/phy/Kconfig6
-rw-r--r--drivers/net/phy/Makefile1
-rw-r--r--drivers/net/phy/nxp-c45-tja11xx.c348
-rw-r--r--drivers/net/phy/phy.c3
-rw-r--r--drivers/net/smc911x.c41
-rw-r--r--drivers/pci/Kconfig12
-rw-r--r--drivers/pci/Makefile1
-rw-r--r--drivers/pci/pci-uclass.c3
-rw-r--r--drivers/pci/pcie_ecam_synquacer.c600
-rw-r--r--drivers/pinctrl/mscc/mscc-common.h4
-rw-r--r--drivers/serial/serial_msm.c4
-rw-r--r--drivers/spi/Kconfig8
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/spi-synquacer.c491
-rw-r--r--drivers/w1/w1-gpio.c2
-rw-r--r--include/bootstage.h4
-rw-r--r--include/configs/devkit3250.h6
-rw-r--r--include/configs/ea-lpc3250devkitv2.h37
-rw-r--r--include/configs/openpiton-riscv64.h61
-rw-r--r--include/configs/sifive-unleashed.h1
-rw-r--r--include/configs/sifive-unmatched.h7
-rw-r--r--include/configs/synquacer.h115
-rw-r--r--include/configs/work_92105.h6
-rw-r--r--include/dt-bindings/clock/lpc32xx-clock.h58
-rw-r--r--include/phy.h5
-rw-r--r--scripts/config_whitelist.txt2
-rw-r--r--tools/docker/Dockerfile85
153 files changed, 8189 insertions, 887 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 06c4a2ffd01..48a7b024f6d 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -2,7 +2,7 @@ variables:
windows_vm: vs2017-win2016
ubuntu_vm: ubuntu-18.04
macos_vm: macOS-10.15
- ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210609-01Jul2021
+ ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210609-06Jul2021
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
@@ -300,7 +300,6 @@ jobs:
cp ~/grub_x86.efi ${UBOOT_TRAVIS_BUILD_DIR}/
cp ~/grub_x64.efi ${UBOOT_TRAVIS_BUILD_DIR}/
cp /opt/grub/grubriscv64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi
- cp /opt/grub/grubriscv32.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv32.efi
cp /opt/grub/grubaa64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi
cp /opt/grub/grubarm.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi
virtualenv -p /usr/bin/python3 /tmp/venv
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 94c73330560..86026a15f9d 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -2,7 +2,7 @@
# Grab our configured image. The source for this is found at:
# https://source.denx.de/u-boot/gitlab-ci-runner
-image: trini/u-boot-gitlab-ci-runner:focal-20210609-01Jul2021
+image: trini/u-boot-gitlab-ci-runner:focal-20210609-06Jul2021
# We run some tests in different order, to catch some failures quicker.
stages:
@@ -38,7 +38,6 @@ stages:
- cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/
- cp ~/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/
- cp /opt/grub/grubriscv64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv64.efi
- - cp /opt/grub/grubriscv32.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv32.efi
- cp /opt/grub/grubaa64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi
- cp /opt/grub/grubarm.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi
- virtualenv -p /usr/bin/python3 /tmp/venv
diff --git a/MAINTAINERS b/MAINTAINERS
index 4be95cc8456..fbe6623d994 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -922,6 +922,11 @@ F: cmd/nvme.c
F: include/nvme.h
F: doc/develop/driver-model/nvme.rst
+NXP C45 TJA11XX PHY DRIVER
+M: Radu Pirea <radu-nicolae.pirea@oss.nxp.com>
+S: Maintained
+F: drivers/net/phy/nxp-c45-tja11xx.c
+
ONENAND
#M: Lukasz Majewski <l.majewski@majess.pl>
S: Orphaned (Since 2017-01)
diff --git a/Makefile b/Makefile
index 2ab9c531923..d9473fb572a 100644
--- a/Makefile
+++ b/Makefile
@@ -712,6 +712,10 @@ KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks)
# disable stringop warnings in gcc 8+
KBUILD_CFLAGS += $(call cc-disable-warning, stringop-truncation)
+KBUILD_CFLAGS += $(call cc-disable-warning, zero-length-bounds)
+KBUILD_CFLAGS += $(call cc-disable-warning, array-bounds)
+KBUILD_CFLAGS += $(call cc-disable-warning, stringop-overflow)
+
# Enabled with W=2, disabled by default as noisy
KBUILD_CFLAGS += $(call cc-disable-warning, maybe-uninitialized)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0448787b8bc..03529d7b46e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -90,6 +90,9 @@ config HAS_VBAR
config HAS_THUMB2
bool
+config GPIO_EXTRA_HEADER
+ bool
+
# Used for compatibility with asm files copied from the kernel
config ARM_ASM_UNIFIED
bool
@@ -518,25 +521,30 @@ choice
config ARCH_AT91
bool "Atmel AT91"
+ select GPIO_EXTRA_HEADER
select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
select SPL_SEPARATE_BSS if SPL
config TARGET_EDB93XX
bool "Support edb93xx"
select CPU_ARM920T
+ select GPIO_EXTRA_HEADER
select PL010_SERIAL
config TARGET_ASPENITE
bool "Support aspenite"
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
config TARGET_GPLUGD
bool "Support gplugd"
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
config ARCH_DAVINCI
bool "TI DaVinci"
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
select SPL_DM_SPI if SPL
imply CMD_SAVES
help
@@ -547,6 +555,7 @@ config ARCH_KIRKWOOD
select ARCH_MISC_INIT
select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
config ARCH_MVEBU
bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
@@ -555,6 +564,7 @@ config ARCH_MVEBU
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
+ select GPIO_EXTRA_HEADER
select SPL_DM_SPI if SPL
select SPL_DM_SPI_FLASH if SPL
select OF_CONTROL
@@ -565,11 +575,13 @@ config ARCH_MVEBU
config ARCH_ORION5X
bool "Marvell Orion"
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
config TARGET_SPEAR300
bool "Support spear300"
select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
select PL011_SERIAL
imply CMD_SAVES
@@ -577,6 +589,7 @@ config TARGET_SPEAR310
bool "Support spear310"
select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
select PL011_SERIAL
imply CMD_SAVES
@@ -584,6 +597,7 @@ config TARGET_SPEAR320
bool "Support spear320"
select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
select PL011_SERIAL
imply CMD_SAVES
@@ -591,6 +605,7 @@ config TARGET_SPEAR600
bool "Support spear600"
select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
select PL011_SERIAL
imply CMD_SAVES
@@ -601,6 +616,7 @@ config TARGET_STV0991
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
+ select GPIO_EXTRA_HEADER
select PL01X_SERIAL
select SPI
select SPI_FLASH
@@ -610,18 +626,21 @@ config TARGET_X600
bool "Support x600"
select BOARD_LATE_INIT
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
select PL011_SERIAL
select SUPPORT_SPL
config TARGET_FLEA3
bool "Support flea3"
select CPU_ARM1136
+ select GPIO_EXTRA_HEADER
config ARCH_BCM283X
bool "Broadcom BCM283X family"
select DM
select DM_GPIO
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select PL01X_SERIAL
select SERIAL_SEARCH_ALL
@@ -650,6 +669,7 @@ config ARCH_BCMSTB
bool "Broadcom BCM7XXX family"
select CPU_V7A
select DM
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select OF_PRIOR_STAGE
imply CMD_DM
@@ -660,6 +680,7 @@ config ARCH_BCMSTB
config TARGET_BCMCYGNUS
bool "Support bcmcygnus"
select CPU_V7A
+ select GPIO_EXTRA_HEADER
imply BCM_SF2_ETH
imply BCM_SF2_ETH_GMAC
imply CMD_HASH
@@ -671,6 +692,7 @@ config TARGET_BCMCYGNUS
config TARGET_BCMNS2
bool "Support Broadcom Northstar2"
select ARM64
+ select GPIO_EXTRA_HEADER
help
Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
ARMv8 Cortex-A57 processors targeting a broad range of networking
@@ -695,6 +717,7 @@ config ARCH_EXYNOS
select DM_SPI
select DM_SPI_FLASH
select SPI
+ select GPIO_EXTRA_HEADER
imply SYS_THUMB_BUILD
imply CMD_DM
imply FAT_WRITE
@@ -706,6 +729,7 @@ config ARCH_S5PC1XX
select DM_GPIO
select DM_I2C
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
imply CMD_DM
config ARCH_HIGHBANK
@@ -726,6 +750,7 @@ config ARCH_INTEGRATOR
bool "ARM Ltd. Integrator family"
select DM
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select PL01X_SERIAL
imply CMD_DM
@@ -736,6 +761,7 @@ config ARCH_IPQ40XX
select DM_GPIO
select DM_SERIAL
select DM_RESET
+ select GPIO_EXTRA_HEADER
select MSM_SMEM
select PINCTRL
select CLK
@@ -747,6 +773,7 @@ config ARCH_KEYSTONE
bool "TI Keystone"
select CMD_POWEROFF
select CPU_V7A
+ select GPIO_EXTRA_HEADER
select SUPPORT_SPL
select SYS_ARCH_TIMER
select SYS_THUMB_BUILD
@@ -763,6 +790,7 @@ config ARCH_K3
config ARCH_OMAP2PLUS
bool "TI OMAP2+"
select CPU_V7A
+ select GPIO_EXTRA_HEADER
select SPL_BOARD_INIT if SPL
select SPL_STACK_R if SPL
select SUPPORT_SPL
@@ -771,6 +799,7 @@ config ARCH_OMAP2PLUS
config ARCH_MESON
bool "Amlogic Meson"
+ select GPIO_EXTRA_HEADER
imply DISTRO_DEFAULTS
imply DM_RNG
help
@@ -781,6 +810,7 @@ config ARCH_MESON
config ARCH_MEDIATEK
bool "MediaTek SoCs"
select DM
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select SPL_DM if SPL
select SPL_LIBCOMMON_SUPPORT if SPL
@@ -797,6 +827,7 @@ config ARCH_LPC32XX
select DM
select DM_GPIO
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select SPL_DM if SPL
select SUPPORT_SPL
imply CMD_DM
@@ -805,12 +836,14 @@ config ARCH_IMX8
bool "NXP i.MX8 platform"
select ARM64
select DM
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select ENABLE_ARM_SOC_BOOT0_HOOK
config ARCH_IMX8M
bool "NXP i.MX8M platform"
select ARM64
+ select GPIO_EXTRA_HEADER
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
@@ -823,33 +856,39 @@ config ARCH_IMXRT
select CPU_V7M
select DM
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select SUPPORT_SPL
imply CMD_DM
config ARCH_MX23
bool "NXP i.MX23 family"
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
select PL011_SERIAL
select SUPPORT_SPL
config ARCH_MX25
bool "NXP MX25"
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
imply MXC_GPIO
config ARCH_MX28
bool "NXP i.MX28 family"
select CPU_ARM926EJS
+ select GPIO_EXTRA_HEADER
select PL011_SERIAL
select SUPPORT_SPL
config ARCH_MX31
bool "NXP i.MX31 family"
select CPU_ARM1136
+ select GPIO_EXTRA_HEADER
config ARCH_MX7ULP
bool "NXP MX7ULP"
select CPU_V7A
+ select GPIO_EXTRA_HEADER
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
@@ -861,6 +900,7 @@ config ARCH_MX7
bool "Freescale MX7"
select ARCH_MISC_INIT
select CPU_V7A
+ select GPIO_EXTRA_HEADER
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
@@ -871,6 +911,7 @@ config ARCH_MX7
config ARCH_MX6
bool "Freescale MX6"
select CPU_V7A
+ select GPIO_EXTRA_HEADER
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
@@ -886,18 +927,21 @@ config ARCH_MX5
bool "Freescale MX5"
select BOARD_EARLY_INIT_F
select CPU_V7A
+ select GPIO_EXTRA_HEADER
imply MXC_GPIO
config ARCH_NEXELL
bool "Nexell S5P4418/S5P6818 SoC"
select ENABLE_ARM_SOC_BOOT0_HOOK
select DM
+ select GPIO_EXTRA_HEADER
config ARCH_OWL
bool "Actions Semi OWL SoCs"
select DM
select DM_ETH
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select OWL_SERIAL
select CLK
select CLK_OWL
@@ -920,6 +964,7 @@ config ARCH_RMOBILE
bool "Renesas ARM SoCs"
select DM
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
imply BOARD_EARLY_INIT_F
imply CMD_DM
imply FAT_WRITE
@@ -932,6 +977,7 @@ config ARCH_SNAPDRAGON
select DM
select DM_GPIO
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select MSM_SMEM
select OF_CONTROL
select OF_SEPARATE
@@ -947,6 +993,7 @@ config ARCH_SOCFPGA
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
select SPL_DM_RESET if DM_RESET
@@ -998,6 +1045,7 @@ config ARCH_SUNXI
select DM_SCSI if SCSI
select DM_SERIAL
select DM_USB if DISTRO_DEFAULTS
+ select GPIO_EXTRA_HEADER
select OF_BOARD_SETUP
select OF_CONTROL
select OF_SEPARATE
@@ -1057,6 +1105,7 @@ config ARCH_VERSAL
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
imply BOARD_LATE_INIT
imply ENV_VARS_UBOOT_RUNTIME_CONFIG
@@ -1064,6 +1113,7 @@ config ARCH_VERSAL
config ARCH_VF610
bool "Freescale Vybrid"
select CPU_V7A
+ select GPIO_EXTRA_HEADER
select SYS_FSL_ERRATUM_ESDHC111
imply CMD_MTDPARTS
imply MTD_RAW_NAND
@@ -1080,6 +1130,7 @@ config ARCH_ZYNQ
select DM_SPI
select DM_SPI_FLASH
select DM_USB if USB
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select SPI
select SPL_BOARD_INIT if SPL
@@ -1106,6 +1157,7 @@ config ARCH_ZYNQMP_R5
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
imply CMD_DM
imply DM_USB_GADGET
@@ -1123,6 +1175,7 @@ config ARCH_ZYNQMP
select DM_SPI_FLASH if DM_SPI
select DM_USB if USB
select FIRMWARE
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select SPL_BOARD_INIT if SPL
select SPL_CLK if SPL
@@ -1143,23 +1196,27 @@ config ARCH_ZYNQMP
config ARCH_TEGRA
bool "NVIDIA Tegra"
+ select GPIO_EXTRA_HEADER
imply DISTRO_DEFAULTS
imply FAT_WRITE
config TARGET_VEXPRESS64_AEMV8A
bool "Support vexpress_aemv8a"
select ARM64
+ select GPIO_EXTRA_HEADER
select PL01X_SERIAL
config TARGET_VEXPRESS64_BASE_FVP
bool "Support Versatile Express ARMv8a FVP BASE model"
select ARM64
+ select GPIO_EXTRA_HEADER
select PL01X_SERIAL
select SEMIHOSTING
config TARGET_VEXPRESS64_JUNO
bool "Support Versatile Express Juno Development Platform"
select ARM64
+ select GPIO_EXTRA_HEADER
select PL01X_SERIAL
select DM
select OF_CONTROL
@@ -1188,6 +1245,7 @@ config TARGET_LS2080A_EMU
select ARM64
select ARMV8_MULTIENTRY
select FSL_DDR_SYNC_REFRESH
+ select GPIO_EXTRA_HEADER
help
Support for Freescale LS2080A_EMU platform.
The LS2080A Development System (EMULATOR) is a pre-silicon
@@ -1201,6 +1259,7 @@ config TARGET_LS1088AQDS
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SD_BOOT
help
@@ -1216,6 +1275,7 @@ config TARGET_LS2080AQDS
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
select SUPPORT_SPL
imply SCSI
imply SCSI_AHCI
@@ -1237,6 +1297,7 @@ config TARGET_LS2080ARDB
select SUPPORT_SPL
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE if !SPL
+ select GPIO_EXTRA_HEADER
imply SCSI
imply SCSI_AHCI
help
@@ -1251,6 +1312,7 @@ config TARGET_LS2081ARDB
select ARM64
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
select SUPPORT_SPL
help
Support for Freescale LS2081ARDB platform.
@@ -1265,6 +1327,7 @@ config TARGET_LX2160ARDB
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
help
Support for NXP LX2160ARDB platform.
The lx2160ardb (LX2160A Reference design board (RDB)
@@ -1278,6 +1341,7 @@ config TARGET_LX2160AQDS
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
help
Support for NXP LX2160AQDS platform.
The lx2160aqds (LX2160A QorIQ Development System (QDS)
@@ -1292,6 +1356,7 @@ config TARGET_LX2162AQDS
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
help
Support for NXP LX2162AQDS platform.
The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
@@ -1302,6 +1367,7 @@ config TARGET_HIKEY
select DM
select DM_GPIO
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select PL01X_SERIAL
select SPECIFY_CONSOLE_INDEX
@@ -1315,6 +1381,7 @@ config TARGET_HIKEY960
select ARM64
select DM
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select PL01X_SERIAL
imply CMD_DM
@@ -1328,6 +1395,7 @@ config TARGET_POPLAR
select DM
select DM_SERIAL
select DM_USB
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select PL01X_SERIAL
imply CMD_DM
@@ -1343,6 +1411,7 @@ config TARGET_LS1012AQDS
select ARM64
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
help
Support for Freescale LS1012AQDS platform.
The LS1012A Development System (QDS) is a high-performance
@@ -1355,6 +1424,7 @@ config TARGET_LS1012ARDB
select ARM64
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
imply SCSI
imply SCSI_AHCI
help
@@ -1369,6 +1439,7 @@ config TARGET_LS1012A2G5RDB
select ARM64
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
imply SCSI
help
Support for Freescale LS1012A2G5RDB platform.
@@ -1382,6 +1453,7 @@ config TARGET_LS1012AFRWY
select ARM64
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
imply SCSI
imply SCSI_AHCI
help
@@ -1395,6 +1467,7 @@ config TARGET_LS1012AFRDM
select ARCH_LS1012A
select ARM64
select ARCH_SUPPORT_TFABOOT
+ select GPIO_EXTRA_HEADER
help
Support for Freescale LS1012AFRDM platform.
The LS1012A Freedom board (FRDM) is a high-performance
@@ -1408,6 +1481,7 @@ config TARGET_LS1028AQDS
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
help
Support for Freescale LS1028AQDS platform
The LS1028A Development System (QDS) is a high-performance
@@ -1421,6 +1495,7 @@ config TARGET_LS1028ARDB
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select GPIO_EXTRA_HEADER
help
Support for Freescale LS1028ARDB platform
The LS1028A Development System (RDB) is a high-performance
@@ -1436,6 +1511,7 @@ config TARGET_LS1088ARDB
select BOARD_LATE_INIT
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SD_BOOT
+ select GPIO_EXTRA_HEADER
help
Support for NXP LS1088ARDB platform.
The LS1088A Reference design board (RDB) is a high-performance
@@ -1456,6 +1532,7 @@ config TARGET_LS1021AQDS
select SYS_FSL_DDR
select FSL_DDR_INTERACTIVE
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
+ select GPIO_EXTRA_HEADER
select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
imply SCSI
@@ -1471,6 +1548,7 @@ config TARGET_LS1021ATWR
select LS1_DEEP_SLEEP
select SUPPORT_SPL
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
+ select GPIO_EXTRA_HEADER
imply SCSI
config TARGET_PG_WCOM_SELI8
@@ -1484,6 +1562,7 @@ config TARGET_PG_WCOM_SELI8
select CPU_V7_HAS_VIRT
select SYS_FSL_DDR
select FSL_DDR_INTERACTIVE
+ select GPIO_EXTRA_HEADER
select VENDOR_KM
imply SCSI
help
@@ -1520,6 +1599,7 @@ config TARGET_LS1021ATSN
select CPU_V7_HAS_VIRT
select LS1_DEEP_SLEEP
select SUPPORT_SPL
+ select GPIO_EXTRA_HEADER
imply SCSI
config TARGET_LS1021AIOT
@@ -1532,6 +1612,7 @@ config TARGET_LS1021AIOT
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
+ select GPIO_EXTRA_HEADER
imply SCSI
help
Support for Freescale LS1021AIOT platform.
@@ -1551,6 +1632,7 @@ config TARGET_LS1043AQDS
select FSL_DDR_INTERACTIVE if !SPL
select FSL_DSPI if !SPL_NO_DSPI
select DM_SPI_FLASH if FSL_DSPI
+ select GPIO_EXTRA_HEADER
imply SCSI
imply SCSI_AHCI
help
@@ -1567,6 +1649,7 @@ config TARGET_LS1043ARDB
select SUPPORT_SPL
select FSL_DSPI if !SPL_NO_DSPI
select DM_SPI_FLASH if FSL_DSPI
+ select GPIO_EXTRA_HEADER
help
Support for Freescale LS1043ARDB platform.
@@ -1583,6 +1666,7 @@ config TARGET_LS1046AQDS
select FSL_DDR_BIST if !SPL
select FSL_DDR_INTERACTIVE if !SPL
select FSL_DDR_INTERACTIVE if !SPL
+ select GPIO_EXTRA_HEADER
imply SCSI
help
Support for Freescale LS1046AQDS platform.
@@ -1603,6 +1687,7 @@ config TARGET_LS1046ARDB
select SUPPORT_SPL
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE if !SPL
+ select GPIO_EXTRA_HEADER
imply SCSI
help
Support for Freescale LS1046ARDB platform.
@@ -1619,6 +1704,7 @@ config TARGET_LS1046AFRWY
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select DM_SPI_FLASH if DM_SPI
+ select GPIO_EXTRA_HEADER
imply SCSI
help
Support for Freescale LS1046AFRWY platform.
@@ -1647,6 +1733,7 @@ config TARGET_SL28
select DM_SERIAL
select DM_SPI
select DM_USB
+ select GPIO_EXTRA_HEADER
select SPL_DM if SPL
select SPL_DM_SPI if SPL
select SPL_DM_SPI_FLASH if SPL
@@ -1659,6 +1746,7 @@ config TARGET_SL28
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
+ select GPIO_EXTRA_HEADER
config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
@@ -1690,11 +1778,25 @@ config ARCH_UNIPHIER
Support for UniPhier SoC family developed by Socionext Inc.
(formerly, System LSI Business Division of Panasonic Corporation)
+config ARCH_SYNQUACER
+ bool "Socionext SynQuacer SoCs"
+ select ARM64
+ select DM
+ select GIC_V3
+ select PSCI_RESET
+ select SYSRESET
+ select SYSRESET_PSCI
+ select OF_CONTROL
+ help
+ Support for SynQuacer SoC family developed by Socionext Inc.
+ This SoC is used on 96boards EE DeveloperBox.
+
config ARCH_STM32
bool "Support STMicroelectronics STM32 MCU with cortex M"
select CPU_V7M
select DM
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
imply CMD_DM
config ARCH_STI
@@ -1720,6 +1822,7 @@ config ARCH_STM32MP
select DM_GPIO
select DM_RESET
select DM_SERIAL
+ select GPIO_EXTRA_HEADER
select MISC
select OF_CONTROL
select OF_LIBFDT
@@ -1782,6 +1885,7 @@ config ARCH_OCTEONTX
bool "Support OcteonTX SoCs"
select CLK
select DM
+ select GPIO_EXTRA_HEADER
select ARM64
select OF_CONTROL
select OF_LIVE
@@ -1792,6 +1896,7 @@ config ARCH_OCTEONTX2
bool "Support OcteonTX2 SoCs"
select CLK
select DM
+ select GPIO_EXTRA_HEADER
select ARM64
select OF_CONTROL
select OF_LIVE
@@ -1801,6 +1906,7 @@ config ARCH_OCTEONTX2
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
select ARM64
+ select GPIO_EXTRA_HEADER
select OF_CONTROL
select PL01X_SERIAL
select SYS_CACHE_SHIFT_7
@@ -1814,6 +1920,7 @@ config ARCH_ASPEED
config TARGET_DURIAN
bool "Support Phytium Durian Platform"
select ARM64
+ select GPIO_EXTRA_HEADER
help
Support for durian platform.
It has 2GB Sdram, uart and pcie.
@@ -2027,6 +2134,7 @@ source "board/isee/igep003x/Kconfig"
source "board/kontron/sl28/Kconfig"
source "board/myir/mys_6ulx/Kconfig"
source "board/seeed/npi_imx6ull/Kconfig"
+source "board/socionext/developerbox/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"
source "board/spear/spear320/Kconfig"
diff --git a/arch/arm/cpu/armv7/iproc-common/armpll.c b/arch/arm/cpu/armv7/iproc-common/armpll.c
index efa3d9e5a9b..8c3a323f065 100644
--- a/arch/arm/cpu/armv7/iproc-common/armpll.c
+++ b/arch/arm/cpu/armv7/iproc-common/armpll.c
@@ -19,19 +19,22 @@ struct armpll_parameters {
};
struct armpll_parameters armpll_clk_tab[] = {
- { 25, 64, 1, 1, 0},
- { 100, 64, 1, 1, 2},
- { 400, 64, 1, 1, 6},
- { 448, 71, 713050, 1, 6},
- { 500, 80, 1, 1, 6},
- { 560, 89, 629145, 1, 6},
- { 600, 96, 1, 1, 6},
- { 800, 64, 1, 1, 7},
- { 896, 71, 713050, 1, 7},
- { 1000, 80, 1, 1, 7},
- { 1100, 88, 1, 1, 7},
- { 1120, 89, 629145, 1, 7},
- { 1200, 96, 1, 1, 7},
+ { 25, 64, 1, 1, 0},
+ { 100, 64, 1, 1, 2},
+ { 400, 64, 1, 1, 6},
+ { 448, 71, 713050, 1, 6},
+ { 500, 80, 1, 1, 6},
+ { 560, 89, 629145, 1, 6},
+ { 600, 96, 1, 1, 6},
+ { 800, 64, 1, 1, 7},
+ { 896, 71, 713050, 1, 7},
+ { 1000, 80, 1, 1, 7},
+ { 1100, 88, 1, 1, 7},
+ { 1120, 89, 629145, 1, 7},
+ { 1200, 96, 1, 1, 7},
+ { 1300, 104, 1, 1, 7},
+ { 1350, 108, 1, 1, 7},
+ { 1400, 112, 1, 1, 7},
};
uint32_t armpll_config(uint32_t clkmhz)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index eef94c47068..59d8078558a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -249,6 +249,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
cn9130-crb-A.dtb \
cn9130-crb-B.dtb
+dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \
uniphier-ld11-ref.dtb
@@ -1116,6 +1117,8 @@ dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
+dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/at91-sama5d27_som1_ek.dts b/arch/arm/dts/at91-sama5d27_som1_ek.dts
index 4cd6db66fe5..ee851a1befc 100644
--- a/arch/arm/dts/at91-sama5d27_som1_ek.dts
+++ b/arch/arm/dts/at91-sama5d27_som1_ek.dts
@@ -43,6 +43,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "sama5d27_som1.dtsi"
/ {
@@ -55,7 +56,7 @@
};
onewire_tm: onewire {
- gpios = <&pioA 17 0>;
+ gpios = <&pioA 17 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_onewire_tm_default>;
status = "okay";
diff --git a/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts
index ab23f5c209d..f3f6942143d 100644
--- a/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts
+++ b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts
@@ -7,6 +7,7 @@
* Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
*/
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "sama5d27_wlsom1.dtsi"
/ {
@@ -18,7 +19,7 @@
};
onewire_tm: onewire {
- gpios = <&pioA PIN_PC9 0>;
+ gpios = <&pioA PIN_PC9 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_onewire_tm_default>;
status = "okay";
diff --git a/arch/arm/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/dts/at91-sama5d2_ptc_ek.dts
index 068a117585f..cd3711a02a5 100644
--- a/arch/arm/dts/at91-sama5d2_ptc_ek.dts
+++ b/arch/arm/dts/at91-sama5d2_ptc_ek.dts
@@ -57,7 +57,7 @@
};
onewire_tm: onewire {
- gpios = <&pioA PIN_PB31 0>;
+ gpios = <&pioA PIN_PB31 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_onewire_tm_default>;
status = "okay";
diff --git a/arch/arm/dts/at91-sama5d2_xplained.dts b/arch/arm/dts/at91-sama5d2_xplained.dts
index 7f0d1696ba3..b733c4d4cee 100644
--- a/arch/arm/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/dts/at91-sama5d2_xplained.dts
@@ -1,4 +1,5 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "sama5d2.dtsi"
#include "sama5d2-pinfunc.h"
@@ -12,7 +13,7 @@
};
onewire_tm: onewire {
- gpios = <&pioA PIN_PB0 0>;
+ gpios = <&pioA PIN_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_onewire_tm_default>;
status = "okay";
diff --git a/arch/arm/dts/at91-sama5d3_xplained.dts b/arch/arm/dts/at91-sama5d3_xplained.dts
index 20fba5f067c..fc508002a72 100644
--- a/arch/arm/dts/at91-sama5d3_xplained.dts
+++ b/arch/arm/dts/at91-sama5d3_xplained.dts
@@ -37,7 +37,7 @@
};
onewire_tm: onewire {
- gpios = <&pioE 23 GPIO_ACTIVE_LOW>;
+ gpios = <&pioE 23 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_onewire_tm_default>;
status = "okay";
diff --git a/arch/arm/dts/at91-sama5d4_xplained.dts b/arch/arm/dts/at91-sama5d4_xplained.dts
index 7da5086865b..74959253dc8 100644
--- a/arch/arm/dts/at91-sama5d4_xplained.dts
+++ b/arch/arm/dts/at91-sama5d4_xplained.dts
@@ -59,7 +59,7 @@
};
onewire_tm: onewire {
- gpios = <&pioE 15 GPIO_ACTIVE_LOW>;
+ gpios = <&pioE 15 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_onewire_tm_default>;
status = "okay";
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index fa348bc621e..7e56140df26 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include "skeleton64.dtsi"
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
/ {
@@ -91,7 +92,7 @@
gpio-controller;
gpio-count = <122>;
gpio-bank-name="soc";
- #gpio-cells = <1>;
+ #gpio-cells = <2>;
};
ehci@78d9000 {
@@ -123,6 +124,7 @@
bus-width = <0x4>;
clock = <&clkc 1>;
clock-frequency = <200000000>;
+ cd-gpios = <&soc_gpios 38 GPIO_ACTIVE_LOW>;
};
wcnss {
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi
index 79b771e0746..4e0ce3f77d3 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi
@@ -1,2 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi"
+
+/ {
+ aliases {
+ ethernet0 = &mscc_felix_port0;
+ ethernet1 = &mscc_felix_port1;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts
index 1ea1265bcf5..7a3aa21408e 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts
@@ -22,4 +22,44 @@
/delete-property/ phy-handle;
};
+&enetc2 {
+ status = "okay";
+};
+
+&mscc_felix {
+ status = "okay";
+};
+
+&mscc_felix_port0 {
+ label = "gbe0";
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+&mscc_felix_port1 {
+ label = "gbe1";
+ phy-handle = <&phy1>;
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+&mscc_felix_port4 {
+ ethernet = <&enetc2>;
+ status = "okay";
+};
+
/delete-node/ &phy0;
+&mdio0 {
+ phy0: ethernet-phy@5 {
+ reg = <0x5>;
+ eee-broken-1000t;
+ eee-broken-100tx;
+ };
+
+ phy1: ethernet-phy@4 {
+ reg = <0x4>;
+ eee-broken-1000t;
+ eee-broken-100tx;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
index fb1836a8aef..5a0f060c16e 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
@@ -20,6 +20,10 @@
#include "fsl-sch-30841.dtsi"
};
+&enetc2 {
+ status = "okay";
+};
+
&mscc_felix {
status = "okay";
};
@@ -47,3 +51,8 @@
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};
+
+&mscc_felix_port4 {
+ ethernet = <&enetc2>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
index 1d02a3e11de..39a83e10c4c 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
@@ -9,6 +9,10 @@
#include "fsl-sch-30841.dtsi"
};
+&enetc2 {
+ status = "okay";
+};
+
&mscc_felix {
status = "okay";
};
@@ -24,3 +28,8 @@
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};
+
+&mscc_felix_port4 {
+ ethernet = <&enetc2>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
index c92dd1bd2e9..021fe3fbc67 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
@@ -34,6 +34,10 @@
#include "fsl-sch-24801.dtsi"
};
+&enetc2 {
+ status = "okay";
+};
+
&mscc_felix {
status = "okay";
};
@@ -61,3 +65,8 @@
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
};
+
+&mscc_felix_port4 {
+ ethernet = <&enetc2>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
index 941f7472eb0..b6704d8089a 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
@@ -19,6 +19,10 @@
#include "fsl-sch-24801.dtsi"
};
+&enetc2 {
+ status = "okay";
+};
+
&mscc_felix {
status = "okay";
};
@@ -46,3 +50,8 @@
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
};
+
+&mscc_felix_port4 {
+ ethernet = <&enetc2>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
index 7e483e656e2..8c10897e565 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
@@ -19,6 +19,10 @@
#include "fsl-sch-30841.dtsi"
};
+&enetc2 {
+ status = "okay";
+};
+
&mscc_felix {
status = "okay";
};
@@ -46,3 +50,8 @@
phy-mode = "usxgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
};
+
+&mscc_felix_port4 {
+ ethernet = <&enetc2>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
index 49fffdb9cb2..1d800dacef8 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
@@ -13,6 +13,10 @@
#include "fsl-sch-28021.dtsi"
};
+&enetc2 {
+ status = "okay";
+};
+
&mscc_felix {
status = "okay";
};
@@ -40,3 +44,8 @@
phy-mode = "qsgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
};
+
+&mscc_felix_port4 {
+ ethernet = <&enetc2>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
index 8347462f4cb..1fb2cdf0c24 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
@@ -9,6 +9,10 @@
#include "fsl-sch-30842.dtsi"
};
+&enetc2 {
+ status = "okay";
+};
+
&mscc_felix {
status = "okay";
};
@@ -18,3 +22,8 @@
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};
+
+&mscc_felix_port4 {
+ ethernet = <&enetc2>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
index 6be3b5094c8..2333f74e5ae 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
@@ -9,6 +9,10 @@
#include "fsl-sch-30842.dtsi"
};
+&enetc2 {
+ status = "okay";
+};
+
&mscc_felix {
status = "okay";
};
@@ -18,3 +22,8 @@
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
};
+
+&mscc_felix_port4 {
+ ethernet = <&enetc2>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi
index da89ff96e98..69632fa796b 100644
--- a/arch/arm/dts/fsl-ls1028a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi
@@ -251,7 +251,7 @@
&enetc1 {
status = "okay";
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-handle = <&qds_phy0>;
};
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index c7c725a4fc8..50f9b527cde 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -142,14 +142,24 @@
};
enetc2: pci@0,2 {
reg = <0x000200 0 0 0 0>;
- status = "okay";
+ status = "disabled";
phy-mode = "internal";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
};
mdio0: pci@0,3 {
#address-cells=<0>;
#size-cells=<1>;
reg = <0x000300 0 0 0 0>;
status = "disabled";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
};
mscc_felix: pci@0,5 {
diff --git a/arch/arm/dts/lpc3250-ea3250-u-boot.dtsi b/arch/arm/dts/lpc3250-ea3250-u-boot.dtsi
new file mode 100644
index 00000000000..0c82e512c68
--- /dev/null
+++ b/arch/arm/dts/lpc3250-ea3250-u-boot.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Trevor Woerner <twoerner@gmail.com>
+ */
+
+/{
+ model = "Embedded Artists LPC3250 DevKit v2 board based on the NXP LPC3250 SoC";
+ chosen {
+ stdout-path = &uart5;
+ };
+};
+
+&uart5 {
+ compatible = "nxp,lpc3220-uart", "ns16550a";
+};
diff --git a/arch/arm/dts/lpc3250-ea3250.dts b/arch/arm/dts/lpc3250-ea3250.dts
new file mode 100644
index 00000000000..63c6f17bb7c
--- /dev/null
+++ b/arch/arm/dts/lpc3250-ea3250.dts
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Embedded Artists LPC3250 board
+ *
+ * Copyright 2012 Roland Stigge <stigge@antcom.de>
+ */
+
+/dts-v1/;
+#include "lpc32xx.dtsi"
+
+/ {
+ model = "Embedded Artists LPC3250 board based on NXP LPC3250";
+ compatible = "ea,ea3250", "nxp,lpc3250";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x4000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ button {
+ label = "Interrupt Key";
+ linux,code = <103>;
+ gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
+ };
+
+ key1 {
+ label = "KEY1";
+ linux,code = <1>;
+ gpios = <&pca9532 0 0>;
+ };
+
+ key2 {
+ label = "KEY2";
+ linux,code = <2>;
+ gpios = <&pca9532 1 0>;
+ };
+
+ key3 {
+ label = "KEY3";
+ linux,code = <3>;
+ gpios = <&pca9532 2 0>;
+ };
+
+ key4 {
+ label = "KEY4";
+ linux,code = <4>;
+ gpios = <&pca9532 3 0>;
+ };
+
+ joy0 {
+ label = "Joystick Key 0";
+ linux,code = <10>;
+ gpios = <&gpio 2 0 0>; /* P2.0 */
+ };
+
+ joy1 {
+ label = "Joystick Key 1";
+ linux,code = <11>;
+ gpios = <&gpio 2 1 0>; /* P2.1 */
+ };
+
+ joy2 {
+ label = "Joystick Key 2";
+ linux,code = <12>;
+ gpios = <&gpio 2 2 0>; /* P2.2 */
+ };
+
+ joy3 {
+ label = "Joystick Key 3";
+ linux,code = <13>;
+ gpios = <&gpio 2 3 0>; /* P2.3 */
+ };
+
+ joy4 {
+ label = "Joystick Key 4";
+ linux,code = <14>;
+ gpios = <&gpio 2 4 0>; /* P2.4 */
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ /* LEDs on OEM Board */
+
+ led1 {
+ gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
+ linux,default-trigger = "timer";
+ default-state = "off";
+ };
+
+ led2 {
+ gpios = <&gpio 2 10 1>; /* P2.10, active low */
+ default-state = "off";
+ };
+
+ led3 {
+ gpios = <&gpio 2 11 1>; /* P2.11, active low */
+ default-state = "off";
+ };
+
+ led4 {
+ gpios = <&gpio 2 12 1>; /* P2.12, active low */
+ default-state = "off";
+ };
+
+ /* LEDs on Base Board */
+
+ lede1 {
+ gpios = <&pca9532 8 0>;
+ default-state = "off";
+ };
+ lede2 {
+ gpios = <&pca9532 9 0>;
+ default-state = "off";
+ };
+ lede3 {
+ gpios = <&pca9532 10 0>;
+ default-state = "off";
+ };
+ lede4 {
+ gpios = <&pca9532 11 0>;
+ default-state = "off";
+ };
+ lede5 {
+ gpios = <&pca9532 12 0>;
+ default-state = "off";
+ };
+ lede6 {
+ gpios = <&pca9532 13 0>;
+ default-state = "off";
+ };
+ lede7 {
+ gpios = <&pca9532 14 0>;
+ default-state = "off";
+ };
+ lede8 {
+ gpios = <&pca9532 15 0>;
+ default-state = "off";
+ };
+ };
+};
+
+/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */
+&adc {
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+
+ uda1380: uda1380@18 {
+ compatible = "nxp,uda1380";
+ reg = <0x18>;
+ power-gpio = <&gpio 3 10 0>;
+ reset-gpio = <&gpio 3 2 0>;
+ dac-clk = "wspll";
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ };
+
+ eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ };
+
+ pca9532: pca9532@60 {
+ compatible = "nxp,pca9532";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x60>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+};
+
+&i2cusb {
+ clock-frequency = <100000>;
+
+ isp1301: usb-transceiver@2d {
+ compatible = "nxp,isp1301";
+ reg = <0x2d>;
+ };
+};
+
+&mac {
+ phy-mode = "rmii";
+ use-iram;
+ status = "okay";
+};
+
+/* Here, choose exactly one from: ohci, usbd */
+&ohci /* &usbd */ {
+ transceiver = <&isp1301>;
+ status = "okay";
+};
+
+&sd {
+ wp-gpios = <&pca9532 5 0>;
+ cd-gpios = <&pca9532 4 0>;
+ cd-inverted;
+ bus-width = <4>;
+ status = "okay";
+};
+
+/* 128MB Flash via SLC NAND controller */
+&slc {
+ status = "okay";
+
+ nxp,wdr-clks = <14>;
+ nxp,wwidth = <260000000>;
+ nxp,whold = <104000000>;
+ nxp,wsetup = <200000000>;
+ nxp,rdr-clks = <14>;
+ nxp,rwidth = <34666666>;
+ nxp,rhold = <104000000>;
+ nxp,rsetup = <200000000>;
+ nand-on-flash-bbt;
+ gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mtd0@0 {
+ label = "ea3250-boot";
+ reg = <0x00000000 0x00080000>;
+ read-only;
+ };
+
+ mtd1@80000 {
+ label = "ea3250-uboot";
+ reg = <0x00080000 0x000c0000>;
+ read-only;
+ };
+
+ mtd2@140000 {
+ label = "ea3250-kernel";
+ reg = <0x00140000 0x00400000>;
+ };
+
+ mtd3@540000 {
+ label = "ea3250-rootfs";
+ reg = <0x00540000 0x07ac0000>;
+ };
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&uart6 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/lpc32xx.dtsi b/arch/arm/dts/lpc32xx.dtsi
new file mode 100644
index 00000000000..c87066d6c99
--- /dev/null
+++ b/arch/arm/dts/lpc32xx.dtsi
@@ -0,0 +1,508 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NXP LPC32xx SoC
+ *
+ * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright 2012 Roland Stigge <stigge@antcom.de>
+ */
+
+#include <dt-bindings/clock/lpc32xx-clock.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "nxp,lpc3220";
+ interrupt-parent = <&mic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ reg = <0x0>;
+ };
+ };
+
+ clocks {
+ xtal_32k: xtal_32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xtal_32k";
+ };
+
+ xtal: xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13000000>;
+ clock-output-names = "xtal";
+ };
+ };
+
+ ahb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x00000000 0x00000000 0x10000000>,
+ <0x20000000 0x20000000 0x30000000>,
+ <0xe0000000 0xe0000000 0x04000000>;
+
+ iram: sram@8000000 {
+ compatible = "mmio-sram";
+ reg = <0x08000000 0x20000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x08000000 0x20000>;
+ };
+
+ /*
+ * Enable either SLC or MLC
+ */
+ slc: flash@20020000 {
+ compatible = "nxp,lpc3220-slc";
+ reg = <0x20020000 0x1000>;
+ clocks = <&clk LPC32XX_CLK_SLC>;
+ status = "disabled";
+ };
+
+ mlc: flash@200a8000 {
+ compatible = "nxp,lpc3220-mlc";
+ reg = <0x200a8000 0x11000>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_MLC>;
+ status = "disabled";
+ };
+
+ dma: dma@31000000 {
+ compatible = "arm,pl080", "arm,primecell";
+ reg = <0x31000000 0x1000>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_DMA>;
+ clock-names = "apb_pclk";
+ };
+
+ usb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x31020000 0x00001000>;
+
+ /*
+ * Enable either ohci or usbd (gadget)!
+ */
+ ohci: ohci@0 {
+ compatible = "nxp,ohci-nxp", "usb-ohci";
+ reg = <0x0 0x300>;
+ interrupt-parent = <&sic1>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
+ status = "disabled";
+ };
+
+ usbd: usbd@0 {
+ compatible = "nxp,lpc3220-udc";
+ reg = <0x0 0x300>;
+ interrupt-parent = <&sic1>;
+ interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
+ <30 IRQ_TYPE_LEVEL_HIGH>,
+ <28 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
+ status = "disabled";
+ };
+
+ i2cusb: i2c@300 {
+ compatible = "nxp,pnx-i2c";
+ reg = <0x300 0x100>;
+ interrupt-parent = <&sic1>;
+ interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usbclk: clock-controller@f00 {
+ compatible = "nxp,lpc3220-usb-clk";
+ reg = <0xf00 0x100>;
+ #clock-cells = <1>;
+ };
+ };
+
+ clcd: clcd@31040000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x31040000 0x1000>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>;
+ clock-names = "clcdclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ mac: ethernet@31060000 {
+ compatible = "nxp,lpc-eth";
+ reg = <0x31060000 0x1000>;
+ interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_MAC>;
+ status = "disabled";
+ };
+
+ emc: memory-controller@31080000 {
+ compatible = "arm,pl175", "arm,primecell";
+ reg = <0x31080000 0x1000>;
+ clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
+ clock-names = "mpmcclk", "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0xe0000000 0x01000000>,
+ <1 0xe1000000 0x01000000>,
+ <2 0xe2000000 0x01000000>,
+ <3 0xe3000000 0x01000000>;
+ status = "disabled";
+ };
+
+ apb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x20000000 0x20000000 0x30000000>;
+
+ /*
+ * ssp0 and spi1 are shared pins;
+ * enable one in your board dts, as needed.
+ */
+ ssp0: spi@20084000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x20084000 0x1000>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_SSP0>;
+ clock-names = "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@20088000 {
+ compatible = "nxp,lpc3220-spi";
+ reg = <0x20088000 0x1000>;
+ clocks = <&clk LPC32XX_CLK_SPI1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /*
+ * ssp1 and spi2 are shared pins;
+ * enable one in your board dts, as needed.
+ */
+ ssp1: spi@2008c000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x2008c000 0x1000>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_SSP1>;
+ clock-names = "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@20090000 {
+ compatible = "nxp,lpc3220-spi";
+ reg = <0x20090000 0x1000>;
+ clocks = <&clk LPC32XX_CLK_SPI2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s0: i2s@20094000 {
+ compatible = "nxp,lpc3220-i2s";
+ reg = <0x20094000 0x1000>;
+ status = "disabled";
+ };
+
+ sd: sd@20098000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ reg = <0x20098000 0x1000>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+ <13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_SD>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ i2s1: i2s@2009c000 {
+ compatible = "nxp,lpc3220-i2s";
+ reg = <0x2009c000 0x1000>;
+ status = "disabled";
+ };
+
+ /* UART5 first since it is the default console, ttyS0 */
+ uart5: serial@40090000 {
+ /* actually, ns16550a w/ 64 byte fifos! */
+ compatible = "nxp,lpc3220-uart";
+ reg = <0x40090000 0x1000>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ clocks = <&clk LPC32XX_CLK_UART5>;
+ status = "disabled";
+ };
+
+ uart3: serial@40080000 {
+ compatible = "nxp,lpc3220-uart";
+ reg = <0x40080000 0x1000>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ clocks = <&clk LPC32XX_CLK_UART3>;
+ status = "disabled";
+ };
+
+ uart4: serial@40088000 {
+ compatible = "nxp,lpc3220-uart";
+ reg = <0x40088000 0x1000>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ clocks = <&clk LPC32XX_CLK_UART4>;
+ status = "disabled";
+ };
+
+ uart6: serial@40098000 {
+ compatible = "nxp,lpc3220-uart";
+ reg = <0x40098000 0x1000>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ clocks = <&clk LPC32XX_CLK_UART6>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@400a0000 {
+ compatible = "nxp,pnx-i2c";
+ reg = <0x400a0000 0x100>;
+ interrupt-parent = <&sic1>;
+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk LPC32XX_CLK_I2C1>;
+ };
+
+ i2c2: i2c@400a8000 {
+ compatible = "nxp,pnx-i2c";
+ reg = <0x400a8000 0x100>;
+ interrupt-parent = <&sic1>;
+ interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk LPC32XX_CLK_I2C2>;
+ };
+
+ mpwm: mpwm@400e8000 {
+ compatible = "nxp,lpc3220-motor-pwm";
+ reg = <0x400e8000 0x78>;
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+ };
+
+ fab {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x20000000 0x20000000 0x30000000>;
+
+ /* System Control Block */
+ scb {
+ compatible = "simple-bus";
+ ranges = <0x0 0x040004000 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk: clock-controller@0 {
+ compatible = "nxp,lpc3220-clk";
+ reg = <0x00 0x114>;
+ #clock-cells = <1>;
+
+ clocks = <&xtal_32k>, <&xtal>;
+ clock-names = "xtal_32k", "xtal";
+ };
+ };
+
+ mic: interrupt-controller@40008000 {
+ compatible = "nxp,lpc3220-mic";
+ reg = <0x40008000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sic1: interrupt-controller@4000c000 {
+ compatible = "nxp,lpc3220-sic";
+ reg = <0x4000c000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&mic>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+ <30 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ sic2: interrupt-controller@40010000 {
+ compatible = "nxp,lpc3220-sic";
+ reg = <0x40010000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&mic>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+ <31 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ uart1: serial@40014000 {
+ compatible = "nxp,lpc3220-hsuart";
+ reg = <0x40014000 0x1000>;
+ interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart2: serial@40018000 {
+ compatible = "nxp,lpc3220-hsuart";
+ reg = <0x40018000 0x1000>;
+ interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart7: serial@4001c000 {
+ compatible = "nxp,lpc3220-hsuart";
+ reg = <0x4001c000 0x1000>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ rtc: rtc@40024000 {
+ compatible = "nxp,lpc3220-rtc";
+ reg = <0x40024000 0x1000>;
+ interrupt-parent = <&sic1>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_RTC>;
+ };
+
+ gpio: gpio@40028000 {
+ compatible = "nxp,lpc3220-gpio";
+ reg = <0x40028000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <3>; /* bank, pin, flags */
+ };
+
+ timer4: timer@4002c000 {
+ compatible = "nxp,lpc3220-timer";
+ reg = <0x4002c000 0x1000>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk LPC32XX_CLK_TIMER4>;
+ clock-names = "timerclk";
+ status = "disabled";
+ };
+
+ timer5: timer@40030000 {
+ compatible = "nxp,lpc3220-timer";
+ reg = <0x40030000 0x1000>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk LPC32XX_CLK_TIMER5>;
+ clock-names = "timerclk";
+ status = "disabled";
+ };
+
+ watchdog: watchdog@4003c000 {
+ compatible = "nxp,pnx4008-wdt";
+ reg = <0x4003c000 0x1000>;
+ clocks = <&clk LPC32XX_CLK_WDOG>;
+ };
+
+ timer0: timer@40044000 {
+ compatible = "nxp,lpc3220-timer";
+ reg = <0x40044000 0x1000>;
+ clocks = <&clk LPC32XX_CLK_TIMER0>;
+ clock-names = "timerclk";
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ /*
+ * TSC vs. ADC: Since those two share the same
+ * hardware, you need to choose from one of the
+ * following two and do 'status = "okay";' for one of
+ * them
+ */
+
+ adc: adc@40048000 {
+ compatible = "nxp,lpc3220-adc";
+ reg = <0x40048000 0x1000>;
+ interrupt-parent = <&sic1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_ADC>;
+ status = "disabled";
+ };
+
+ tsc: tsc@40048000 {
+ compatible = "nxp,lpc3220-tsc";
+ reg = <0x40048000 0x1000>;
+ interrupt-parent = <&sic1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_ADC>;
+ status = "disabled";
+ };
+
+ timer1: timer@4004c000 {
+ compatible = "nxp,lpc3220-timer";
+ reg = <0x4004c000 0x1000>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk LPC32XX_CLK_TIMER1>;
+ clock-names = "timerclk";
+ };
+
+ key: key@40050000 {
+ compatible = "nxp,lpc3220-key";
+ reg = <0x40050000 0x1000>;
+ clocks = <&clk LPC32XX_CLK_KEY>;
+ interrupt-parent = <&sic1>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer2: timer@40058000 {
+ compatible = "nxp,lpc3220-timer";
+ reg = <0x40058000 0x1000>;
+ interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk LPC32XX_CLK_TIMER2>;
+ clock-names = "timerclk";
+ status = "disabled";
+ };
+
+ pwm1: pwm@4005c000 {
+ compatible = "nxp,lpc3220-pwm";
+ reg = <0x4005c000 0x4>;
+ clocks = <&clk LPC32XX_CLK_PWM1>;
+ assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
+ assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@4005c004 {
+ compatible = "nxp,lpc3220-pwm";
+ reg = <0x4005c004 0x4>;
+ clocks = <&clk LPC32XX_CLK_PWM2>;
+ assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
+ assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
+ status = "disabled";
+ };
+
+ timer3: timer@40060000 {
+ compatible = "nxp,lpc3220-timer";
+ reg = <0x40060000 0x1000>;
+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk LPC32XX_CLK_TIMER3>;
+ clock-names = "timerclk";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts
index 96914b3ea2c..77edd593b41 100644
--- a/arch/arm/dts/sam9x60ek.dts
+++ b/arch/arm/dts/sam9x60ek.dts
@@ -29,7 +29,7 @@
};
onewire_tm: onewire {
- gpios = <&pioD 14 0>;
+ gpios = <&pioD 14 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_onewire_tm_default>;
status = "okay";
diff --git a/arch/arm/dts/synquacer-sc2a11-caches.dtsi b/arch/arm/dts/synquacer-sc2a11-caches.dtsi
new file mode 100644
index 00000000000..177ddf8c2bb
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-caches.dtsi
@@ -0,0 +1,73 @@
+/** @file
+ * Copyright (c) 2018, Linaro Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ */
+
+#define __L1(cpuref, l2ref) \
+cpuref { \
+ i-cache-size = <0x8000>; \
+ i-cache-line-size = <64>; \
+ i-cache-sets = <256>; \
+ d-cache-size = <0x8000>; \
+ d-cache-line-size = <64>; \
+ d-cache-sets = <128>; \
+ l2-cache = <l2ref>; \
+};
+
+#define __L2(idx) \
+L2_##idx: l2-cache##idx { \
+ cache-size = <0x40000>; \
+ cache-line-size = <64>; \
+ cache-sets = <256>; \
+ cache-unified; \
+ next-level-cache = <&L3>; \
+};
+
+/ {
+ __L2(0)
+ __L2(1)
+ __L2(2)
+ __L2(3)
+ __L2(4)
+ __L2(5)
+ __L2(6)
+ __L2(7)
+ __L2(8)
+ __L2(9)
+ __L2(10)
+ __L2(11)
+
+ L3: l3-cache {
+ cache-level = <3>;
+ cache-size = <0x400000>;
+ cache-line-size = <64>;
+ cache-sets = <4096>;
+ cache-unified;
+ };
+};
+
+__L1(&CPU0, &L2_0)
+__L1(&CPU1, &L2_0)
+__L1(&CPU2, &L2_1)
+__L1(&CPU3, &L2_1)
+__L1(&CPU4, &L2_2)
+__L1(&CPU5, &L2_2)
+__L1(&CPU6, &L2_3)
+__L1(&CPU7, &L2_3)
+__L1(&CPU8, &L2_4)
+__L1(&CPU9, &L2_4)
+__L1(&CPU10, &L2_5)
+__L1(&CPU11, &L2_5)
+__L1(&CPU12, &L2_6)
+__L1(&CPU13, &L2_6)
+__L1(&CPU14, &L2_7)
+__L1(&CPU15, &L2_7)
+__L1(&CPU16, &L2_8)
+__L1(&CPU17, &L2_8)
+__L1(&CPU18, &L2_9)
+__L1(&CPU19, &L2_9)
+__L1(&CPU20, &L2_10)
+__L1(&CPU21, &L2_10)
+__L1(&CPU22, &L2_11)
+__L1(&CPU23, &L2_11)
diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
new file mode 100644
index 00000000000..2f13a422357
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// Copyright (c) 2021, Linaro Limited. All rights reserved.
+//
+
+/ {
+ aliases {
+ spi_nor = &spi_nor;
+ i2c0 = &i2c0;
+ };
+
+ spi_nor: spi@54800000 {
+ compatible = "socionext,synquacer-spi";
+ reg = <0x00 0x54800000 0x00 0x1000>;
+ interrupts = <0x00 0x9c 0x04 0x00 0x9d 0x04 0x00 0x9e 0x04>;
+ clocks = <&clk_alw_1_8>;
+ clock-names = "iHCLK";
+ socionext,use-rtm;
+ socionext,set-aces;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ active_clk_edges;
+ chipselect_num = <1>;
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <31250000>;
+ spi-rx-bus-width = <0x1>;
+ spi-tx-bus-width = <0x1>;
+ };
+ };
+
+ i2c0: i2c@51200000 {
+ compatible = "socionext,synquacer-i2c";
+ reg = <0x0 0x51200000 0x0 0x1000>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_i2c>;
+ clock-names = "pclk";
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+ };
+
+ firmware {
+ optee {
+ status = "okay";
+ };
+ };
+};
+
+&smmu {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&sdhci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox.dts b/arch/arm/dts/synquacer-sc2a11-developerbox.dts
new file mode 100644
index 00000000000..42b6cbbb825
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11-developerbox.dts
@@ -0,0 +1,56 @@
+/** @file
+ * Copyright (c) 2017, Linaro Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ */
+
+/dts-v1/;
+
+#include "synquacer-sc2a11.dtsi"
+
+#define KEY_POWER 116
+
+/ {
+ model = "Socionext Developer Box";
+ compatible = "socionext,developer-box", "socionext,synquacer";
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ interrupt-parent = <&exiu>;
+
+ power {
+ label = "Power Button";
+ linux,code = <KEY_POWER>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ };
+ };
+};
+
+#ifdef TPM2_ENABLE
+&tpm {
+ status = "okay";
+};
+#endif
+
+&gpio {
+ gpio-line-names = "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4",
+ "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8",
+ "PSIN#", "PWROFF#", "GPIO-A", "GPIO-B",
+ "GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT",
+ "PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F",
+ "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J",
+ "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27",
+ "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31";
+};
+
+&netsec {
+ phy-mode = "rgmii-id";
+};
+
+&mdio_netsec {
+ phy_netsec: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
diff --git a/arch/arm/dts/synquacer-sc2a11.dtsi b/arch/arm/dts/synquacer-sc2a11.dtsi
new file mode 100644
index 00000000000..1fe7d214b9c
--- /dev/null
+++ b/arch/arm/dts/synquacer-sc2a11.dtsi
@@ -0,0 +1,595 @@
+/** @file
+ * Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ */
+
+/* These are added for U-Boot to avoid compilation error */
+#define PcdNetsecEepromBase 0x08080000
+#define FixedPcdGet32(n) n
+
+#define GIC_SPI 0
+#define GIC_PPI 1
+
+#define IRQ_TYPE_NONE 0
+#define IRQ_TYPE_EDGE_RISING 1
+#define IRQ_TYPE_EDGE_FALLING 2
+#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH 4
+#define IRQ_TYPE_LEVEL_LOW 8
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &soc_uart0;
+ serial1 = &fuart;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x1>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU4: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x200>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU5: cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x201>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU6: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x300>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU7: cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x301>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU8: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x400>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU9: cpu@401 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x401>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU10: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x500>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU11: cpu@501 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x501>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU12: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x600>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU13: cpu@601 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x601>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU14: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x700>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU15: cpu@701 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x701>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU16: cpu@800 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x800>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU17: cpu@801 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x801>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU18: cpu@900 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x900>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU19: cpu@901 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x901>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU20: cpu@a00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0xa00>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU21: cpu@a01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0xa01>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU22: cpu@b00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0xb00>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+ CPU23: cpu@b01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0xb01>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+ core1 {
+ cpu = <&CPU1>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&CPU2>;
+ };
+ core1 {
+ cpu = <&CPU3>;
+ };
+ };
+ cluster2 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+ core1 {
+ cpu = <&CPU5>;
+ };
+ };
+ cluster3 {
+ core0 {
+ cpu = <&CPU6>;
+ };
+ core1 {
+ cpu = <&CPU7>;
+ };
+ };
+ cluster4 {
+ core0 {
+ cpu = <&CPU8>;
+ };
+ core1 {
+ cpu = <&CPU9>;
+ };
+ };
+ cluster5 {
+ core0 {
+ cpu = <&CPU10>;
+ };
+ core1 {
+ cpu = <&CPU11>;
+ };
+ };
+ cluster6 {
+ core0 {
+ cpu = <&CPU12>;
+ };
+ core1 {
+ cpu = <&CPU13>;
+ };
+ };
+ cluster7 {
+ core0 {
+ cpu = <&CPU14>;
+ };
+ core1 {
+ cpu = <&CPU15>;
+ };
+ };
+ cluster8 {
+ core0 {
+ cpu = <&CPU16>;
+ };
+ core1 {
+ cpu = <&CPU17>;
+ };
+ };
+ cluster9 {
+ core0 {
+ cpu = <&CPU18>;
+ };
+ core1 {
+ cpu = <&CPU19>;
+ };
+ };
+ cluster10 {
+ core0 {
+ cpu = <&CPU20>;
+ };
+ core1 {
+ cpu = <&CPU21>;
+ };
+ };
+ cluster11 {
+ core0 {
+ cpu = <&CPU22>;
+ };
+ core1 {
+ cpu = <&CPU23>;
+ };
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <300>;
+ exit-latency-us = <1200>;
+ min-residency-us = <2000>;
+ local-timer-stop;
+ };
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <400>;
+ exit-latency-us = <1200>;
+ min-residency-us = <2500>;
+ local-timer-stop;
+ };
+ };
+
+ gic: interrupt-controller@30000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x30000000 0x0 0x10000>, // GICD
+ <0x0 0x30400000 0x0 0x300000>, // GICR
+ <0x0 0x2c000000 0x0 0x2000>, // GICC
+ <0x0 0x2c010000 0x0 0x1000>, // GICH
+ <0x0 0x2c020000 0x0 0x10000>; // GICV
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+
+ its: gic-its@30020000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30020000 0x0 0x20000>;
+ #msi-cells = <1>;
+ msi-controller;
+ socionext,synquacer-pre-its = <0x58000000 0x200000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, // secure
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, // non-secure
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, // virtual
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; // HYP
+ };
+
+ mmio-timer@2a810000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x2a810000 0x0 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ frame@2a830000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x2a830000 0x0 0x10000>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ clk_uart: refclk62500khz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <62500000>;
+ clock-output-names = "uartclk";
+ };
+
+ clk_apb: refclk100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "apb_pclk";
+ };
+
+ soc_uart0: uart@2a400000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x2a400000 0x0 0x1000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_uart>, <&clk_apb>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ fuart: uart@51040000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x51040000 0x0 0x1000>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_uart>, <&clk_apb>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ };
+
+ clk_netsec: refclk250mhz {
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ #clock-cells = <0>;
+ };
+
+ netsec: ethernet@522d0000 {
+ compatible = "socionext,synquacer-netsec";
+ reg = <0 0x522d0000 0x0 0x10000>,
+ <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_netsec>;
+ clock-names = "phy_ref_clk";
+ max-speed = <1000>;
+ max-frame-size = <9000>;
+ phy-handle = <&phy_netsec>;
+ dma-coherent;
+
+ mdio_netsec: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ smmu: iommu@582c0000 {
+ compatible = "arm,mmu-500", "arm,smmu-v2";
+ reg = <0x0 0x582c0000 0x0 0x10000>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ pcie0: pcie@60000000 {
+ compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
+ device_type = "pci";
+ reg = <0x0 0x60000000 0x0 0x7f00000>;
+ bus-range = <0x0 0x7e>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x1000000 0x00 0x00000000 0x00 0x67f00000 0x0 0x00010000>,
+ <0x2000000 0x00 0x68000000 0x00 0x68000000 0x0 0x08000000>,
+ <0x3000000 0x3e 0x00000000 0x3e 0x00000000 0x1 0x00000000>;
+
+ #interrupt-cells = <0x1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+
+ msi-map = <0x000 &its 0x0 0x7f00>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ pcie1: pcie@70000000 {
+ compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
+ device_type = "pci";
+ reg = <0x0 0x70000000 0x0 0x7f00000>;
+ bus-range = <0x0 0x7e>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>,
+ <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>,
+ <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
+
+ #interrupt-cells = <0x1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+
+ msi-map = <0x0 &its 0x10000 0x7f00>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ gpio: gpio@51000000 {
+ compatible = "socionext,synquacer-gpio", "fujitsu,mb86s70-gpio";
+ reg = <0x0 0x51000000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&clk_apb>;
+ base = <0>;
+ };
+
+ exiu: interrupt-controller@510c0000 {
+ compatible = "socionext,synquacer-exiu";
+ reg = <0x0 0x510c0000 0x0 0x20>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <3>;
+ socionext,spi-base = <112>;
+ };
+
+ clk_alw_b_0: bclk200 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "sd_bclk";
+ };
+
+ clk_alw_c_0: sd4clk800 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <800000000>;
+ clock-output-names = "sd_sd4clk";
+ };
+
+ sdhci: sdhci@52300000 {
+ compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0";
+ reg = <0 0x52300000 0x0 0x1000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ fujitsu,cmd-dat-delay-select;
+ clocks = <&clk_alw_c_0 &clk_alw_b_0>;
+ clock-names = "core", "iface";
+ dma-coherent;
+ status = "disabled";
+ };
+
+ clk_alw_1_8: spi_ihclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "iHCLK";
+ };
+
+ spi: spi@54810000 {
+ compatible = "socionext,synquacer-spi";
+ reg = <0x0 0x54810000 0x0 0x1000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_alw_1_8>;
+ clock-names = "iHCLK";
+ socionext,use-rtm;
+ socionext,set-aces;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ clk_i2c: i2c_pclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <62500000>;
+ clock-output-names = "pclk";
+ };
+
+ i2c: i2c@51210000 {
+ compatible = "socionext,synquacer-i2c";
+ reg = <0x0 0x51210000 0x0 0x1000>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_i2c>;
+ clock-names = "pclk";
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ tpm: tpm_tis@10000000 {
+ compatible = "socionext,synquacer-tpm-mmio";
+ reg = <0x0 0x10000000 0x0 0x5000>;
+ status = "disabled";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ status = "disabled";
+ };
+ };
+};
+
+#include "synquacer-sc2a11-caches.dtsi"
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index 0836091af24..45e46f99463 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -12,8 +12,8 @@
/* Basic CPU architecture */
/* UART configuration */
-#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
- (CONFIG_SYS_LPC32XX_UART == 7)
+#if (CONFIG_CONS_INDEX == 1) || (CONFIG_CONS_INDEX == 2) || \
+ (CONFIG_CONS_INDEX == 7)
#if !defined(CONFIG_LPC32XX_HSUART)
#define CONFIG_LPC32XX_HSUART
#endif
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index 7609367884f..650783ae732 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -1,10 +1,4 @@
-#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
- !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \
- !defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \
- !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \
- !defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM) && \
- !defined(CONFIG_TARGET_BCMNS3) && !defined(CONFIG_TARGET_TOTAL_COMPUTE) && \
- !defined(CONFIG_ARCH_QEMU)
+#ifdef CONFIG_GPIO_EXTRA_HEADER
#include <asm/arch/gpio.h>
#endif
#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
index 986ad738ac1..185bda41c22 100644
--- a/arch/arm/mach-lpc32xx/Kconfig
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -12,9 +12,13 @@ config TARGET_DEVKIT3250
config TARGET_WORK_92105
bool "Work Microwave Work_92105"
+config TARGET_EA_LPC3250DEVKITV2
+ bool "Embedded Artists LPC3250 Developer's Kit v2"
+
endchoice
source "board/timll/devkit3250/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
+source "board/ea/ea-lpc3250devkitv2/Kconfig"
endif
diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c
index e1e2e0d0949..0a4fef295a3 100644
--- a/arch/arm/mach-lpc32xx/devices.c
+++ b/arch/arm/mach-lpc32xx/devices.c
@@ -23,8 +23,7 @@ void lpc32xx_uart_init(unsigned int uart_id)
return;
/* Disable loopback mode, if it is set by S1L bootloader */
- clrbits_le32(&ctrl->loop,
- UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
+ clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id));
if (uart_id < 3 || uart_id > 6)
return;
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c
index fbe0b5212f9..2b76371718c 100644
--- a/arch/arm/mach-snapdragon/clock-snapdragon.c
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.c
@@ -56,15 +56,15 @@ void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
} while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
}
-#define APPS_CMD_RGCR_UPDATE BIT(0)
+#define APPS_CMD_RCGR_UPDATE BIT(0)
-/* Update clock command via CMD_RGCR */
-void clk_bcr_update(phys_addr_t apps_cmd_rgcr)
+/* Update clock command via CMD_RCGR */
+void clk_bcr_update(phys_addr_t apps_cmd_rcgr)
{
- setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE);
+ setbits_le32(apps_cmd_rcgr, APPS_CMD_RCGR_UPDATE);
/* Wait for frequency to be updated. */
- while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE)
+ while (readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE)
;
}
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h
index 520e2e6bd7c..d9a3b1af986 100644
--- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h
+++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h
@@ -8,7 +8,7 @@
#define _MACH_SYSMAP_APQ8016_H
#define GICD_BASE (0x0b000000)
-#define GICC_BASE (0x0a20c000)
+#define GICC_BASE (0x0b002000)
/* Clocks: (from CLK_CTL_BASE) */
#define GPLL0_STATUS (0x2101C)
diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c
index 5c289d00226..507ab3417b3 100644
--- a/arch/powerpc/cpu/mpc83xx/pci.c
+++ b/arch/powerpc/cpu/mpc83xx/pci.c
@@ -27,6 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
static struct pci_controller pci_hose[MAX_BUSES];
static int pci_num_buses;
+#if !defined(CONFIG_DM_PCI)
static void pci_init_bus(int bus, struct pci_region *reg)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
@@ -184,6 +185,7 @@ void mpc83xx_pcislave_unlock(int bus)
hose->last_busno = pci_hose_scan(hose);
}
#endif
+#endif /* CONFIG_DM_PCI */
#if defined(CONFIG_OF_LIBFDT)
void ft_pci_setup(void *blob, struct bd_info *bd)
diff --git a/arch/powerpc/dts/mpc8379erdb.dts b/arch/powerpc/dts/mpc8379erdb.dts
index b1881b161cb..2e7c8f103c3 100644
--- a/arch/powerpc/dts/mpc8379erdb.dts
+++ b/arch/powerpc/dts/mpc8379erdb.dts
@@ -69,6 +69,58 @@
device_type = "ipic";
};
+ usb@23000 {
+ compatible = "fsl-usb2-dr";
+ reg = <0x23000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&ipic>;
+ interrupts = <38 0x8>;
+ phy_type = "ulpi";
+ };
+
+ enet0: ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <32 0x8 33 0x8 34 0x8>;
+ phy-connection-type = "mii";
+ interrupt-parent = <&ipic>;
+ fixed-link = <1 0 1000 0 0>;
+ phy-handle = <&phy>;
+ fsl,magic-packet;
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-mdio";
+ reg = <0x520 0x20>;
+
+ phy: ethernet-phy@2 {
+ interrupt-parent = <&ipic>;
+ interrupts = <17 0x8>;
+ reg = <0x2>;
+ device_type = "ethernet-phy";
+ };
+ };
+ };
+
+ pci0: pci@e0008300 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ reg = <0x0 0xe0008300 0x0 0x00000fff>;
+ compatible = "fsl,mpc837x-pci";
+ clock-frequency = <0>;
+ };
+
};
};
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b3d7fd84cec..4b0c3dffa6b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -26,6 +26,9 @@ config TARGET_SIFIVE_UNMATCHED
config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
+config TARGET_OPENPITON_RISCV64
+ bool "Support RISC-V cores on OpenPiton SoC"
+
endchoice
config SYS_ICACHE_OFF
@@ -60,6 +63,7 @@ source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/unleashed/Kconfig"
source "board/sifive/unmatched/Kconfig"
+source "board/openpiton/riscv64/Kconfig"
source "board/sipeed/maix/Kconfig"
# platform-specific options below
diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
index 3a5f6e47f5f..8e54310b9cb 100644
--- a/arch/riscv/cpu/fu740/Kconfig
+++ b/arch/riscv/cpu/fu740/Kconfig
@@ -35,3 +35,6 @@ config SIFIVE_FU740
imply SIFIVE_OTP
imply DM_PWM
imply PWM_SIFIVE
+ imply DM_I2C
+ imply SYS_I2C_OCORES
+ imply SPL_I2C_SUPPORT
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 77788748312..ba69894eb59 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -3,8 +3,9 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb
+dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
-dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
+dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb hifive-unmatched-a00-rev1.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
targets += $(dtb-y)
diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi
index a5d0688b06e..a6f7a0873ee 100644
--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi
@@ -95,6 +95,10 @@
u-boot,dm-spl;
};
+&i2c0 {
+ u-boot,dm-spl;
+};
+
&eth0 {
assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
assigned-clock-rates = <125125000>;
diff --git a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
new file mode 100644
index 00000000000..0c4dedd1666
--- /dev/null
+++ b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi
@@ -0,0 +1,1489 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2020 SiFive, Inc
+ */
+
+&dmc {
+ sifive,ddr-params = <
+ 0x00000a00 /* DENALI_CTL_00_DATA */
+ 0x00000000 /* DENALI_CTL_01_DATA */
+ 0x00000000 /* DENALI_CTL_02_DATA */
+ 0x00000000 /* DENALI_CTL_03_DATA */
+ 0x00000000 /* DENALI_CTL_04_DATA */
+ 0x00000000 /* DENALI_CTL_05_DATA */
+ 0x0000000b /* DENALI_CTL_06_DATA */
+ 0x00033f1e /* DENALI_CTL_07_DATA */
+ 0x00081dcb /* DENALI_CTL_08_DATA */
+ 0x0b200300 /* DENALI_CTL_09_DATA */
+ 0x1c1c0400 /* DENALI_CTL_10_DATA */
+ 0x04049a0d /* DENALI_CTL_11_DATA */
+ 0x32060406 /* DENALI_CTL_12_DATA */
+ 0x100d0823 /* DENALI_CTL_13_DATA */
+ 0x080a0a17 /* DENALI_CTL_14_DATA */
+ 0x0123b818 /* DENALI_CTL_15_DATA */
+ 0x00180b06 /* DENALI_CTL_16_DATA */
+ 0x00a01510 /* DENALI_CTL_17_DATA */
+ 0x01000118 /* DENALI_CTL_18_DATA */
+ 0x10032501 /* DENALI_CTL_19_DATA */
+ 0x00000000 /* DENALI_CTL_20_DATA */
+ 0x00000101 /* DENALI_CTL_21_DATA */
+ 0x00000000 /* DENALI_CTL_22_DATA */
+ 0x0a000000 /* DENALI_CTL_23_DATA */
+ 0x00000000 /* DENALI_CTL_24_DATA */
+ 0x01750100 /* DENALI_CTL_25_DATA */
+ 0x00002069 /* DENALI_CTL_26_DATA */
+ 0x00000005 /* DENALI_CTL_27_DATA */
+ 0x001a0007 /* DENALI_CTL_28_DATA */
+ 0x017f0300 /* DENALI_CTL_29_DATA */
+ 0x03010000 /* DENALI_CTL_30_DATA */
+ 0x000b0f00 /* DENALI_CTL_31_DATA */
+ 0x04030200 /* DENALI_CTL_32_DATA */
+ 0x0000031f /* DENALI_CTL_33_DATA */
+ 0x00070004 /* DENALI_CTL_34_DATA */
+ 0x00000000 /* DENALI_CTL_35_DATA */
+ 0x00000000 /* DENALI_CTL_36_DATA */
+ 0x00000000 /* DENALI_CTL_37_DATA */
+ 0x00000000 /* DENALI_CTL_38_DATA */
+ 0x00000000 /* DENALI_CTL_39_DATA */
+ 0x00000000 /* DENALI_CTL_40_DATA */
+ 0x00000000 /* DENALI_CTL_41_DATA */
+ 0x00000000 /* DENALI_CTL_42_DATA */
+ 0x00000000 /* DENALI_CTL_43_DATA */
+ 0x00000000 /* DENALI_CTL_44_DATA */
+ 0x00000000 /* DENALI_CTL_45_DATA */
+ 0x00000000 /* DENALI_CTL_46_DATA */
+ 0x00000000 /* DENALI_CTL_47_DATA */
+ 0x00000000 /* DENALI_CTL_48_DATA */
+ 0x00000000 /* DENALI_CTL_49_DATA */
+ 0x00000000 /* DENALI_CTL_50_DATA */
+ 0x00000000 /* DENALI_CTL_51_DATA */
+ 0x00000000 /* DENALI_CTL_52_DATA */
+ 0x00000000 /* DENALI_CTL_53_DATA */
+ 0x00000000 /* DENALI_CTL_54_DATA */
+ 0x00000000 /* DENALI_CTL_55_DATA */
+ 0x00000000 /* DENALI_CTL_56_DATA */
+ 0x00000000 /* DENALI_CTL_57_DATA */
+ 0x00000000 /* DENALI_CTL_58_DATA */
+ 0x00000000 /* DENALI_CTL_59_DATA */
+ 0x00000634 /* DENALI_CTL_60_DATA */
+ 0x00000201 /* DENALI_CTL_61_DATA */
+ 0x00001010 /* DENALI_CTL_62_DATA */
+ 0x00000000 /* DENALI_CTL_63_DATA */
+ 0x00000200 /* DENALI_CTL_64_DATA */
+ 0x00000000 /* DENALI_CTL_65_DATA */
+ 0x00000481 /* DENALI_CTL_66_DATA */
+ 0x00000800 /* DENALI_CTL_67_DATA */
+ 0x00000634 /* DENALI_CTL_68_DATA */
+ 0x00000201 /* DENALI_CTL_69_DATA */
+ 0x00001010 /* DENALI_CTL_70_DATA */
+ 0x00000000 /* DENALI_CTL_71_DATA */
+ 0x00000200 /* DENALI_CTL_72_DATA */
+ 0x00000000 /* DENALI_CTL_73_DATA */
+ 0x00000481 /* DENALI_CTL_74_DATA */
+ 0x00000800 /* DENALI_CTL_75_DATA */
+ 0x01010000 /* DENALI_CTL_76_DATA */
+ 0x00000000 /* DENALI_CTL_77_DATA */
+ 0x00000000 /* DENALI_CTL_78_DATA */
+ 0x00000000 /* DENALI_CTL_79_DATA */
+ 0x00000000 /* DENALI_CTL_80_DATA */
+ 0x00000000 /* DENALI_CTL_81_DATA */
+ 0x00000000 /* DENALI_CTL_82_DATA */
+ 0x00000000 /* DENALI_CTL_83_DATA */
+ 0x00000000 /* DENALI_CTL_84_DATA */
+ 0x00000000 /* DENALI_CTL_85_DATA */
+ 0x00000000 /* DENALI_CTL_86_DATA */
+ 0x00000000 /* DENALI_CTL_87_DATA */
+ 0x00000000 /* DENALI_CTL_88_DATA */
+ 0x00000000 /* DENALI_CTL_89_DATA */
+ 0x00000000 /* DENALI_CTL_90_DATA */
+ 0x00000000 /* DENALI_CTL_91_DATA */
+ 0x00000000 /* DENALI_CTL_92_DATA */
+ 0x00000000 /* DENALI_CTL_93_DATA */
+ 0x00000000 /* DENALI_CTL_94_DATA */
+ 0x00000000 /* DENALI_CTL_95_DATA */
+ 0x00000000 /* DENALI_CTL_96_DATA */
+ 0x00000000 /* DENALI_CTL_97_DATA */
+ 0x00000000 /* DENALI_CTL_98_DATA */
+ 0x00000000 /* DENALI_CTL_99_DATA */
+ 0x00000000 /* DENALI_CTL_100_DATA */
+ 0x00000000 /* DENALI_CTL_101_DATA */
+ 0x00000000 /* DENALI_CTL_102_DATA */
+ 0x00000000 /* DENALI_CTL_103_DATA */
+ 0x00000000 /* DENALI_CTL_104_DATA */
+ 0x00000003 /* DENALI_CTL_105_DATA */
+ 0x00000000 /* DENALI_CTL_106_DATA */
+ 0x00000000 /* DENALI_CTL_107_DATA */
+ 0x00000000 /* DENALI_CTL_108_DATA */
+ 0x00000000 /* DENALI_CTL_109_DATA */
+ 0x01000000 /* DENALI_CTL_110_DATA */
+ 0x00040000 /* DENALI_CTL_111_DATA */
+ 0x00800200 /* DENALI_CTL_112_DATA */
+ 0x00000200 /* DENALI_CTL_113_DATA */
+ 0x00000040 /* DENALI_CTL_114_DATA */
+ 0x01000100 /* DENALI_CTL_115_DATA */
+ 0x0a000002 /* DENALI_CTL_116_DATA */
+ 0x0101ffff /* DENALI_CTL_117_DATA */
+ 0x01010101 /* DENALI_CTL_118_DATA */
+ 0x01010101 /* DENALI_CTL_119_DATA */
+ 0x0000010b /* DENALI_CTL_120_DATA */
+ 0x00000c01 /* DENALI_CTL_121_DATA */
+ 0x00000000 /* DENALI_CTL_122_DATA */
+ 0x00000000 /* DENALI_CTL_123_DATA */
+ 0x00000000 /* DENALI_CTL_124_DATA */
+ 0x00000000 /* DENALI_CTL_125_DATA */
+ 0x00030300 /* DENALI_CTL_126_DATA */
+ 0x00000000 /* DENALI_CTL_127_DATA */
+ 0x00010001 /* DENALI_CTL_128_DATA */
+ 0x00000000 /* DENALI_CTL_129_DATA */
+ 0x00000000 /* DENALI_CTL_130_DATA */
+ 0x00000000 /* DENALI_CTL_131_DATA */
+ 0x00000000 /* DENALI_CTL_132_DATA */
+ 0x00000000 /* DENALI_CTL_133_DATA */
+ 0x00000000 /* DENALI_CTL_134_DATA */
+ 0x00000000 /* DENALI_CTL_135_DATA */
+ 0x00000000 /* DENALI_CTL_136_DATA */
+ 0x00000000 /* DENALI_CTL_137_DATA */
+ 0x00000000 /* DENALI_CTL_138_DATA */
+ 0x00000000 /* DENALI_CTL_139_DATA */
+ 0x00000000 /* DENALI_CTL_140_DATA */
+ 0x00000000 /* DENALI_CTL_141_DATA */
+ 0x00000000 /* DENALI_CTL_142_DATA */
+ 0x00000000 /* DENALI_CTL_143_DATA */
+ 0x00000000 /* DENALI_CTL_144_DATA */
+ 0x00000000 /* DENALI_CTL_145_DATA */
+ 0x00000000 /* DENALI_CTL_146_DATA */
+ 0x00000000 /* DENALI_CTL_147_DATA */
+ 0x00000000 /* DENALI_CTL_148_DATA */
+ 0x00000000 /* DENALI_CTL_149_DATA */
+ 0x00000000 /* DENALI_CTL_150_DATA */
+ 0x00000000 /* DENALI_CTL_151_DATA */
+ 0x00000000 /* DENALI_CTL_152_DATA */
+ 0x00000000 /* DENALI_CTL_153_DATA */
+ 0x00000000 /* DENALI_CTL_154_DATA */
+ 0x00000000 /* DENALI_CTL_155_DATA */
+ 0x00000000 /* DENALI_CTL_156_DATA */
+ 0x00000000 /* DENALI_CTL_157_DATA */
+ 0x00000000 /* DENALI_CTL_158_DATA */
+ 0x00000000 /* DENALI_CTL_159_DATA */
+ 0x00000000 /* DENALI_CTL_160_DATA */
+ 0x02010102 /* DENALI_CTL_161_DATA */
+ 0x0107070e /* DENALI_CTL_162_DATA */
+ 0x04040500 /* DENALI_CTL_163_DATA */
+ 0x03000502 /* DENALI_CTL_164_DATA */
+ 0x00000000 /* DENALI_CTL_165_DATA */
+ 0x00000000 /* DENALI_CTL_166_DATA */
+ 0x00000000 /* DENALI_CTL_167_DATA */
+ 0x00000000 /* DENALI_CTL_168_DATA */
+ 0x280d0000 /* DENALI_CTL_169_DATA */
+ 0x01000000 /* DENALI_CTL_170_DATA */
+ 0x00000000 /* DENALI_CTL_171_DATA */
+ 0x00010001 /* DENALI_CTL_172_DATA */
+ 0x00000000 /* DENALI_CTL_173_DATA */
+ 0x00000000 /* DENALI_CTL_174_DATA */
+ 0x00000000 /* DENALI_CTL_175_DATA */
+ 0x00000000 /* DENALI_CTL_176_DATA */
+ 0x00000000 /* DENALI_CTL_177_DATA */
+ 0x00000000 /* DENALI_CTL_178_DATA */
+ 0x00000000 /* DENALI_CTL_179_DATA */
+ 0x00000000 /* DENALI_CTL_180_DATA */
+ 0x01000000 /* DENALI_CTL_181_DATA */
+ 0x00000001 /* DENALI_CTL_182_DATA */
+ 0x00000100 /* DENALI_CTL_183_DATA */
+ 0x00010101 /* DENALI_CTL_184_DATA */
+ 0x67676701 /* DENALI_CTL_185_DATA */
+ 0x67676767 /* DENALI_CTL_186_DATA */
+ 0x67676767 /* DENALI_CTL_187_DATA */
+ 0x67676767 /* DENALI_CTL_188_DATA */
+ 0x67676767 /* DENALI_CTL_189_DATA */
+ 0x67676767 /* DENALI_CTL_190_DATA */
+ 0x67676767 /* DENALI_CTL_191_DATA */
+ 0x67676767 /* DENALI_CTL_192_DATA */
+ 0x67676767 /* DENALI_CTL_193_DATA */
+ 0x01000067 /* DENALI_CTL_194_DATA */
+ 0x00000001 /* DENALI_CTL_195_DATA */
+ 0x00000101 /* DENALI_CTL_196_DATA */
+ 0x00000000 /* DENALI_CTL_197_DATA */
+ 0x00000000 /* DENALI_CTL_198_DATA */
+ 0x00000000 /* DENALI_CTL_199_DATA */
+ 0x00000000 /* DENALI_CTL_200_DATA */
+ 0x00000000 /* DENALI_CTL_201_DATA */
+ 0x00000000 /* DENALI_CTL_202_DATA */
+ 0x00000000 /* DENALI_CTL_203_DATA */
+ 0x00000000 /* DENALI_CTL_204_DATA */
+ 0x00000000 /* DENALI_CTL_205_DATA */
+ 0x00000000 /* DENALI_CTL_206_DATA */
+ 0x00000000 /* DENALI_CTL_207_DATA */
+ 0x00000001 /* DENALI_CTL_208_DATA */
+ 0x00000000 /* DENALI_CTL_209_DATA */
+ 0x007fffff /* DENALI_CTL_210_DATA */
+ 0x00000000 /* DENALI_CTL_211_DATA */
+ 0x007fffff /* DENALI_CTL_212_DATA */
+ 0x00000000 /* DENALI_CTL_213_DATA */
+ 0x007fffff /* DENALI_CTL_214_DATA */
+ 0x00000000 /* DENALI_CTL_215_DATA */
+ 0x007fffff /* DENALI_CTL_216_DATA */
+ 0x00000000 /* DENALI_CTL_217_DATA */
+ 0x007fffff /* DENALI_CTL_218_DATA */
+ 0x00000000 /* DENALI_CTL_219_DATA */
+ 0x007fffff /* DENALI_CTL_220_DATA */
+ 0x00000000 /* DENALI_CTL_221_DATA */
+ 0x007fffff /* DENALI_CTL_222_DATA */
+ 0x00000000 /* DENALI_CTL_223_DATA */
+ 0x037fffff /* DENALI_CTL_224_DATA */
+ 0xffffffff /* DENALI_CTL_225_DATA */
+ 0x000f000f /* DENALI_CTL_226_DATA */
+ 0x00ffff03 /* DENALI_CTL_227_DATA */
+ 0x000fffff /* DENALI_CTL_228_DATA */
+ 0x0003000f /* DENALI_CTL_229_DATA */
+ 0xffffffff /* DENALI_CTL_230_DATA */
+ 0x000f000f /* DENALI_CTL_231_DATA */
+ 0x00ffff03 /* DENALI_CTL_232_DATA */
+ 0x000fffff /* DENALI_CTL_233_DATA */
+ 0x0003000f /* DENALI_CTL_234_DATA */
+ 0xffffffff /* DENALI_CTL_235_DATA */
+ 0x000f000f /* DENALI_CTL_236_DATA */
+ 0x00ffff03 /* DENALI_CTL_237_DATA */
+ 0x000fffff /* DENALI_CTL_238_DATA */
+ 0x0003000f /* DENALI_CTL_239_DATA */
+ 0xffffffff /* DENALI_CTL_240_DATA */
+ 0x000f000f /* DENALI_CTL_241_DATA */
+ 0x00ffff03 /* DENALI_CTL_242_DATA */
+ 0x000fffff /* DENALI_CTL_243_DATA */
+ 0x6407000f /* DENALI_CTL_244_DATA */
+ 0x01640001 /* DENALI_CTL_245_DATA */
+ 0x00000000 /* DENALI_CTL_246_DATA */
+ 0x00000000 /* DENALI_CTL_247_DATA */
+ 0x00001900 /* DENALI_CTL_248_DATA */
+ 0x0040d205 /* DENALI_CTL_249_DATA */
+ 0x02000200 /* DENALI_CTL_250_DATA */
+ 0x02000200 /* DENALI_CTL_251_DATA */
+ 0x000040d2 /* DENALI_CTL_252_DATA */
+ 0x00028834 /* DENALI_CTL_253_DATA */
+ 0x02020e11 /* DENALI_CTL_254_DATA */
+ 0x00140303 /* DENALI_CTL_255_DATA */
+ 0x00000000 /* DENALI_CTL_256_DATA */
+ 0x00000000 /* DENALI_CTL_257_DATA */
+ 0x00001403 /* DENALI_CTL_258_DATA */
+ 0x00000000 /* DENALI_CTL_259_DATA */
+ 0x00000000 /* DENALI_CTL_260_DATA */
+ 0x00000000 /* DENALI_CTL_261_DATA */
+ 0x00000000 /* DENALI_CTL_262_DATA */
+ 0x0f010000 /* DENALI_CTL_263_DATA */
+ 0x00000009 /* DENALI_CTL_264_DATA */
+ 0x01375642 /* DENALI_PHY_00_DATA */
+ 0x0004c008 /* DENALI_PHY_01_DATA */
+ 0x00000120 /* DENALI_PHY_02_DATA */
+ 0x00000000 /* DENALI_PHY_03_DATA */
+ 0x00000000 /* DENALI_PHY_04_DATA */
+ 0x00010000 /* DENALI_PHY_05_DATA */
+ 0x01DDDD90 /* DENALI_PHY_06_DATA */
+ 0x01DDDD90 /* DENALI_PHY_07_DATA */
+ 0x01030000 /* DENALI_PHY_08_DATA */
+ 0x01000000 /* DENALI_PHY_09_DATA */
+ 0x00c00000 /* DENALI_PHY_10_DATA */
+ 0x00000007 /* DENALI_PHY_11_DATA */
+ 0x00000000 /* DENALI_PHY_12_DATA */
+ 0x00000000 /* DENALI_PHY_13_DATA */
+ 0x04000408 /* DENALI_PHY_14_DATA */
+ 0x00000408 /* DENALI_PHY_15_DATA */
+ 0x00e4e400 /* DENALI_PHY_16_DATA */
+ 0x00000000 /* DENALI_PHY_17_DATA */
+ 0x00000000 /* DENALI_PHY_18_DATA */
+ 0x00000000 /* DENALI_PHY_19_DATA */
+ 0x00000000 /* DENALI_PHY_20_DATA */
+ 0x00000000 /* DENALI_PHY_21_DATA */
+ 0x00000000 /* DENALI_PHY_22_DATA */
+ 0x00000000 /* DENALI_PHY_23_DATA */
+ 0x00000000 /* DENALI_PHY_24_DATA */
+ 0x00000000 /* DENALI_PHY_25_DATA */
+ 0x00000000 /* DENALI_PHY_26_DATA */
+ 0x00000000 /* DENALI_PHY_27_DATA */
+ 0x00000000 /* DENALI_PHY_28_DATA */
+ 0x00000000 /* DENALI_PHY_29_DATA */
+ 0x00000000 /* DENALI_PHY_30_DATA */
+ 0x00000000 /* DENALI_PHY_31_DATA */
+ 0x00000000 /* DENALI_PHY_32_DATA */
+ 0x00200000 /* DENALI_PHY_33_DATA */
+ 0x00000000 /* DENALI_PHY_34_DATA */
+ 0x00000000 /* DENALI_PHY_35_DATA */
+ 0x00000000 /* DENALI_PHY_36_DATA */
+ 0x00000000 /* DENALI_PHY_37_DATA */
+ 0x00000000 /* DENALI_PHY_38_DATA */
+ 0x00000000 /* DENALI_PHY_39_DATA */
+ 0x02800280 /* DENALI_PHY_40_DATA */
+ 0x02800280 /* DENALI_PHY_41_DATA */
+ 0x02800280 /* DENALI_PHY_42_DATA */
+ 0x02800280 /* DENALI_PHY_43_DATA */
+ 0x00000280 /* DENALI_PHY_44_DATA */
+ 0x00000000 /* DENALI_PHY_45_DATA */
+ 0x00000000 /* DENALI_PHY_46_DATA */
+ 0x00000000 /* DENALI_PHY_47_DATA */
+ 0x00000000 /* DENALI_PHY_48_DATA */
+ 0x00000000 /* DENALI_PHY_49_DATA */
+ 0x00800080 /* DENALI_PHY_50_DATA */
+ 0x00800080 /* DENALI_PHY_51_DATA */
+ 0x00800080 /* DENALI_PHY_52_DATA */
+ 0x00800080 /* DENALI_PHY_53_DATA */
+ 0x00800080 /* DENALI_PHY_54_DATA */
+ 0x00800080 /* DENALI_PHY_55_DATA */
+ 0x00800080 /* DENALI_PHY_56_DATA */
+ 0x00800080 /* DENALI_PHY_57_DATA */
+ 0x00800080 /* DENALI_PHY_58_DATA */
+ 0x00010120 /* DENALI_PHY_59_DATA */
+ 0x000001d0 /* DENALI_PHY_60_DATA */
+ 0x01000000 /* DENALI_PHY_61_DATA */
+ 0x00000000 /* DENALI_PHY_62_DATA */
+ 0x00000002 /* DENALI_PHY_63_DATA */
+ 0x51313152 /* DENALI_PHY_64_DATA */
+ 0x80013130 /* DENALI_PHY_65_DATA */
+ 0x03000080 /* DENALI_PHY_66_DATA */
+ 0x00100002 /* DENALI_PHY_67_DATA */
+ 0x0c064208 /* DENALI_PHY_68_DATA */
+ 0x000f0c0f /* DENALI_PHY_69_DATA */
+ 0x01000140 /* DENALI_PHY_70_DATA */
+ 0x0000000c /* DENALI_PHY_71_DATA */
+ 0x00000000 /* DENALI_PHY_72_DATA */
+ 0x00000000 /* DENALI_PHY_73_DATA */
+ 0x00000000 /* DENALI_PHY_74_DATA */
+ 0x00000000 /* DENALI_PHY_75_DATA */
+ 0x00000000 /* DENALI_PHY_76_DATA */
+ 0x00000000 /* DENALI_PHY_77_DATA */
+ 0x00000000 /* DENALI_PHY_78_DATA */
+ 0x00000000 /* DENALI_PHY_79_DATA */
+ 0x00000000 /* DENALI_PHY_80_DATA */
+ 0x00000000 /* DENALI_PHY_81_DATA */
+ 0x00000000 /* DENALI_PHY_82_DATA */
+ 0x00000000 /* DENALI_PHY_83_DATA */
+ 0x00000000 /* DENALI_PHY_84_DATA */
+ 0x00000000 /* DENALI_PHY_85_DATA */
+ 0x00000000 /* DENALI_PHY_86_DATA */
+ 0x00000000 /* DENALI_PHY_87_DATA */
+ 0x00000000 /* DENALI_PHY_88_DATA */
+ 0x00000000 /* DENALI_PHY_89_DATA */
+ 0x00000000 /* DENALI_PHY_90_DATA */
+ 0x00000000 /* DENALI_PHY_91_DATA */
+ 0x00000000 /* DENALI_PHY_92_DATA */
+ 0x00000000 /* DENALI_PHY_93_DATA */
+ 0x00000000 /* DENALI_PHY_94_DATA */
+ 0x00000000 /* DENALI_PHY_95_DATA */
+ 0x00000000 /* DENALI_PHY_96_DATA */
+ 0x00000000 /* DENALI_PHY_97_DATA */
+ 0x00000000 /* DENALI_PHY_98_DATA */
+ 0x00000000 /* DENALI_PHY_99_DATA */
+ 0x00000000 /* DENALI_PHY_100_DATA */
+ 0x00000000 /* DENALI_PHY_101_DATA */
+ 0x00000000 /* DENALI_PHY_102_DATA */
+ 0x00000000 /* DENALI_PHY_103_DATA */
+ 0x00000000 /* DENALI_PHY_104_DATA */
+ 0x00000000 /* DENALI_PHY_105_DATA */
+ 0x00000000 /* DENALI_PHY_106_DATA */
+ 0x00000000 /* DENALI_PHY_107_DATA */
+ 0x00000000 /* DENALI_PHY_108_DATA */
+ 0x00000000 /* DENALI_PHY_109_DATA */
+ 0x00000000 /* DENALI_PHY_110_DATA */
+ 0x00000000 /* DENALI_PHY_111_DATA */
+ 0x00000000 /* DENALI_PHY_112_DATA */
+ 0x00000000 /* DENALI_PHY_113_DATA */
+ 0x00000000 /* DENALI_PHY_114_DATA */
+ 0x00000000 /* DENALI_PHY_115_DATA */
+ 0x00000000 /* DENALI_PHY_116_DATA */
+ 0x00000000 /* DENALI_PHY_117_DATA */
+ 0x00000000 /* DENALI_PHY_118_DATA */
+ 0x00000000 /* DENALI_PHY_119_DATA */
+ 0x00000000 /* DENALI_PHY_120_DATA */
+ 0x00000000 /* DENALI_PHY_121_DATA */
+ 0x00000000 /* DENALI_PHY_122_DATA */
+ 0x00000000 /* DENALI_PHY_123_DATA */
+ 0x00000000 /* DENALI_PHY_124_DATA */
+ 0x00000000 /* DENALI_PHY_125_DATA */
+ 0x00000000 /* DENALI_PHY_126_DATA */
+ 0x00000000 /* DENALI_PHY_127_DATA */
+ 0x40263571 /* DENALI_PHY_128_DATA */
+ 0x0004c008 /* DENALI_PHY_129_DATA */
+ 0x00000120 /* DENALI_PHY_130_DATA */
+ 0x00000000 /* DENALI_PHY_131_DATA */
+ 0x00000000 /* DENALI_PHY_132_DATA */
+ 0x00010000 /* DENALI_PHY_133_DATA */
+ 0x01DDDD90 /* DENALI_PHY_134_DATA */
+ 0x01DDDD90 /* DENALI_PHY_135_DATA */
+ 0x01030000 /* DENALI_PHY_136_DATA */
+ 0x01000000 /* DENALI_PHY_137_DATA */
+ 0x00c00000 /* DENALI_PHY_138_DATA */
+ 0x00000007 /* DENALI_PHY_139_DATA */
+ 0x00000000 /* DENALI_PHY_140_DATA */
+ 0x00000000 /* DENALI_PHY_141_DATA */
+ 0x04000408 /* DENALI_PHY_142_DATA */
+ 0x00000408 /* DENALI_PHY_143_DATA */
+ 0x00e4e400 /* DENALI_PHY_144_DATA */
+ 0x00000000 /* DENALI_PHY_145_DATA */
+ 0x00000000 /* DENALI_PHY_146_DATA */
+ 0x00000000 /* DENALI_PHY_147_DATA */
+ 0x00000000 /* DENALI_PHY_148_DATA */
+ 0x00000000 /* DENALI_PHY_149_DATA */
+ 0x00000000 /* DENALI_PHY_150_DATA */
+ 0x00000000 /* DENALI_PHY_151_DATA */
+ 0x00000000 /* DENALI_PHY_152_DATA */
+ 0x00000000 /* DENALI_PHY_153_DATA */
+ 0x00000000 /* DENALI_PHY_154_DATA */
+ 0x00000000 /* DENALI_PHY_155_DATA */
+ 0x00000000 /* DENALI_PHY_156_DATA */
+ 0x00000000 /* DENALI_PHY_157_DATA */
+ 0x00000000 /* DENALI_PHY_158_DATA */
+ 0x00000000 /* DENALI_PHY_159_DATA */
+ 0x00000000 /* DENALI_PHY_160_DATA */
+ 0x00200000 /* DENALI_PHY_161_DATA */
+ 0x00000000 /* DENALI_PHY_162_DATA */
+ 0x00000000 /* DENALI_PHY_163_DATA */
+ 0x00000000 /* DENALI_PHY_164_DATA */
+ 0x00000000 /* DENALI_PHY_165_DATA */
+ 0x00000000 /* DENALI_PHY_166_DATA */
+ 0x00000000 /* DENALI_PHY_167_DATA */
+ 0x02800280 /* DENALI_PHY_168_DATA */
+ 0x02800280 /* DENALI_PHY_169_DATA */
+ 0x02800280 /* DENALI_PHY_170_DATA */
+ 0x02800280 /* DENALI_PHY_171_DATA */
+ 0x00000280 /* DENALI_PHY_172_DATA */
+ 0x00000000 /* DENALI_PHY_173_DATA */
+ 0x00000000 /* DENALI_PHY_174_DATA */
+ 0x00000000 /* DENALI_PHY_175_DATA */
+ 0x00000000 /* DENALI_PHY_176_DATA */
+ 0x00000000 /* DENALI_PHY_177_DATA */
+ 0x00800080 /* DENALI_PHY_178_DATA */
+ 0x00800080 /* DENALI_PHY_179_DATA */
+ 0x00800080 /* DENALI_PHY_180_DATA */
+ 0x00800080 /* DENALI_PHY_181_DATA */
+ 0x00800080 /* DENALI_PHY_182_DATA */
+ 0x00800080 /* DENALI_PHY_183_DATA */
+ 0x00800080 /* DENALI_PHY_184_DATA */
+ 0x00800080 /* DENALI_PHY_185_DATA */
+ 0x00800080 /* DENALI_PHY_186_DATA */
+ 0x00010120 /* DENALI_PHY_187_DATA */
+ 0x000001d0 /* DENALI_PHY_188_DATA */
+ 0x01000000 /* DENALI_PHY_189_DATA */
+ 0x00000000 /* DENALI_PHY_190_DATA */
+ 0x00000002 /* DENALI_PHY_191_DATA */
+ 0x51313152 /* DENALI_PHY_192_DATA */
+ 0x80013130 /* DENALI_PHY_193_DATA */
+ 0x03000080 /* DENALI_PHY_194_DATA */
+ 0x00100002 /* DENALI_PHY_195_DATA */
+ 0x0c064208 /* DENALI_PHY_196_DATA */
+ 0x000f0c0f /* DENALI_PHY_197_DATA */
+ 0x01000140 /* DENALI_PHY_198_DATA */
+ 0x0000000c /* DENALI_PHY_199_DATA */
+ 0x00000000 /* DENALI_PHY_200_DATA */
+ 0x00000000 /* DENALI_PHY_201_DATA */
+ 0x00000000 /* DENALI_PHY_202_DATA */
+ 0x00000000 /* DENALI_PHY_203_DATA */
+ 0x00000000 /* DENALI_PHY_204_DATA */
+ 0x00000000 /* DENALI_PHY_205_DATA */
+ 0x00000000 /* DENALI_PHY_206_DATA */
+ 0x00000000 /* DENALI_PHY_207_DATA */
+ 0x00000000 /* DENALI_PHY_208_DATA */
+ 0x00000000 /* DENALI_PHY_209_DATA */
+ 0x00000000 /* DENALI_PHY_210_DATA */
+ 0x00000000 /* DENALI_PHY_211_DATA */
+ 0x00000000 /* DENALI_PHY_212_DATA */
+ 0x00000000 /* DENALI_PHY_213_DATA */
+ 0x00000000 /* DENALI_PHY_214_DATA */
+ 0x00000000 /* DENALI_PHY_215_DATA */
+ 0x00000000 /* DENALI_PHY_216_DATA */
+ 0x00000000 /* DENALI_PHY_217_DATA */
+ 0x00000000 /* DENALI_PHY_218_DATA */
+ 0x00000000 /* DENALI_PHY_219_DATA */
+ 0x00000000 /* DENALI_PHY_220_DATA */
+ 0x00000000 /* DENALI_PHY_221_DATA */
+ 0x00000000 /* DENALI_PHY_222_DATA */
+ 0x00000000 /* DENALI_PHY_223_DATA */
+ 0x00000000 /* DENALI_PHY_224_DATA */
+ 0x00000000 /* DENALI_PHY_225_DATA */
+ 0x00000000 /* DENALI_PHY_226_DATA */
+ 0x00000000 /* DENALI_PHY_227_DATA */
+ 0x00000000 /* DENALI_PHY_228_DATA */
+ 0x00000000 /* DENALI_PHY_229_DATA */
+ 0x00000000 /* DENALI_PHY_230_DATA */
+ 0x00000000 /* DENALI_PHY_231_DATA */
+ 0x00000000 /* DENALI_PHY_232_DATA */
+ 0x00000000 /* DENALI_PHY_233_DATA */
+ 0x00000000 /* DENALI_PHY_234_DATA */
+ 0x00000000 /* DENALI_PHY_235_DATA */
+ 0x00000000 /* DENALI_PHY_236_DATA */
+ 0x00000000 /* DENALI_PHY_237_DATA */
+ 0x00000000 /* DENALI_PHY_238_DATA */
+ 0x00000000 /* DENALI_PHY_239_DATA */
+ 0x00000000 /* DENALI_PHY_240_DATA */
+ 0x00000000 /* DENALI_PHY_241_DATA */
+ 0x00000000 /* DENALI_PHY_242_DATA */
+ 0x00000000 /* DENALI_PHY_243_DATA */
+ 0x00000000 /* DENALI_PHY_244_DATA */
+ 0x00000000 /* DENALI_PHY_245_DATA */
+ 0x00000000 /* DENALI_PHY_246_DATA */
+ 0x00000000 /* DENALI_PHY_247_DATA */
+ 0x00000000 /* DENALI_PHY_248_DATA */
+ 0x00000000 /* DENALI_PHY_249_DATA */
+ 0x00000000 /* DENALI_PHY_250_DATA */
+ 0x00000000 /* DENALI_PHY_251_DATA */
+ 0x00000000 /* DENALI_PHY_252_DATA */
+ 0x00000000 /* DENALI_PHY_253_DATA */
+ 0x00000000 /* DENALI_PHY_254_DATA */
+ 0x00000000 /* DENALI_PHY_255_DATA */
+ 0x46052371 /* DENALI_PHY_256_DATA */
+ 0x0004c008 /* DENALI_PHY_257_DATA */
+ 0x00000120 /* DENALI_PHY_258_DATA */
+ 0x00000000 /* DENALI_PHY_259_DATA */
+ 0x00000000 /* DENALI_PHY_260_DATA */
+ 0x00010000 /* DENALI_PHY_261_DATA */
+ 0x01DDDD90 /* DENALI_PHY_262_DATA */
+ 0x01DDDD90 /* DENALI_PHY_263_DATA */
+ 0x01030000 /* DENALI_PHY_264_DATA */
+ 0x01000000 /* DENALI_PHY_265_DATA */
+ 0x00c00000 /* DENALI_PHY_266_DATA */
+ 0x00000007 /* DENALI_PHY_267_DATA */
+ 0x00000000 /* DENALI_PHY_268_DATA */
+ 0x00000000 /* DENALI_PHY_269_DATA */
+ 0x04000408 /* DENALI_PHY_270_DATA */
+ 0x00000408 /* DENALI_PHY_271_DATA */
+ 0x00e4e400 /* DENALI_PHY_272_DATA */
+ 0x00000000 /* DENALI_PHY_273_DATA */
+ 0x00000000 /* DENALI_PHY_274_DATA */
+ 0x00000000 /* DENALI_PHY_275_DATA */
+ 0x00000000 /* DENALI_PHY_276_DATA */
+ 0x00000000 /* DENALI_PHY_277_DATA */
+ 0x00000000 /* DENALI_PHY_278_DATA */
+ 0x00000000 /* DENALI_PHY_279_DATA */
+ 0x00000000 /* DENALI_PHY_280_DATA */
+ 0x00000000 /* DENALI_PHY_281_DATA */
+ 0x00000000 /* DENALI_PHY_282_DATA */
+ 0x00000000 /* DENALI_PHY_283_DATA */
+ 0x00000000 /* DENALI_PHY_284_DATA */
+ 0x00000000 /* DENALI_PHY_285_DATA */
+ 0x00000000 /* DENALI_PHY_286_DATA */
+ 0x00000000 /* DENALI_PHY_287_DATA */
+ 0x00000000 /* DENALI_PHY_288_DATA */
+ 0x00200000 /* DENALI_PHY_289_DATA */
+ 0x00000000 /* DENALI_PHY_290_DATA */
+ 0x00000000 /* DENALI_PHY_291_DATA */
+ 0x00000000 /* DENALI_PHY_292_DATA */
+ 0x00000000 /* DENALI_PHY_293_DATA */
+ 0x00000000 /* DENALI_PHY_294_DATA */
+ 0x00000000 /* DENALI_PHY_295_DATA */
+ 0x02800280 /* DENALI_PHY_296_DATA */
+ 0x02800280 /* DENALI_PHY_297_DATA */
+ 0x02800280 /* DENALI_PHY_298_DATA */
+ 0x02800280 /* DENALI_PHY_299_DATA */
+ 0x00000280 /* DENALI_PHY_300_DATA */
+ 0x00000000 /* DENALI_PHY_301_DATA */
+ 0x00000000 /* DENALI_PHY_302_DATA */
+ 0x00000000 /* DENALI_PHY_303_DATA */
+ 0x00000000 /* DENALI_PHY_304_DATA */
+ 0x00000000 /* DENALI_PHY_305_DATA */
+ 0x00800080 /* DENALI_PHY_306_DATA */
+ 0x00800080 /* DENALI_PHY_307_DATA */
+ 0x00800080 /* DENALI_PHY_308_DATA */
+ 0x00800080 /* DENALI_PHY_309_DATA */
+ 0x00800080 /* DENALI_PHY_310_DATA */
+ 0x00800080 /* DENALI_PHY_311_DATA */
+ 0x00800080 /* DENALI_PHY_312_DATA */
+ 0x00800080 /* DENALI_PHY_313_DATA */
+ 0x00800080 /* DENALI_PHY_314_DATA */
+ 0x00010120 /* DENALI_PHY_315_DATA */
+ 0x000001d0 /* DENALI_PHY_316_DATA */
+ 0x01000000 /* DENALI_PHY_317_DATA */
+ 0x00000000 /* DENALI_PHY_318_DATA */
+ 0x00000002 /* DENALI_PHY_319_DATA */
+ 0x51313152 /* DENALI_PHY_320_DATA */
+ 0x80013130 /* DENALI_PHY_321_DATA */
+ 0x03000080 /* DENALI_PHY_322_DATA */
+ 0x00100002 /* DENALI_PHY_323_DATA */
+ 0x0c064208 /* DENALI_PHY_324_DATA */
+ 0x000f0c0f /* DENALI_PHY_325_DATA */
+ 0x01000140 /* DENALI_PHY_326_DATA */
+ 0x0000000c /* DENALI_PHY_327_DATA */
+ 0x00000000 /* DENALI_PHY_328_DATA */
+ 0x00000000 /* DENALI_PHY_329_DATA */
+ 0x00000000 /* DENALI_PHY_330_DATA */
+ 0x00000000 /* DENALI_PHY_331_DATA */
+ 0x00000000 /* DENALI_PHY_332_DATA */
+ 0x00000000 /* DENALI_PHY_333_DATA */
+ 0x00000000 /* DENALI_PHY_334_DATA */
+ 0x00000000 /* DENALI_PHY_335_DATA */
+ 0x00000000 /* DENALI_PHY_336_DATA */
+ 0x00000000 /* DENALI_PHY_337_DATA */
+ 0x00000000 /* DENALI_PHY_338_DATA */
+ 0x00000000 /* DENALI_PHY_339_DATA */
+ 0x00000000 /* DENALI_PHY_340_DATA */
+ 0x00000000 /* DENALI_PHY_341_DATA */
+ 0x00000000 /* DENALI_PHY_342_DATA */
+ 0x00000000 /* DENALI_PHY_343_DATA */
+ 0x00000000 /* DENALI_PHY_344_DATA */
+ 0x00000000 /* DENALI_PHY_345_DATA */
+ 0x00000000 /* DENALI_PHY_346_DATA */
+ 0x00000000 /* DENALI_PHY_347_DATA */
+ 0x00000000 /* DENALI_PHY_348_DATA */
+ 0x00000000 /* DENALI_PHY_349_DATA */
+ 0x00000000 /* DENALI_PHY_350_DATA */
+ 0x00000000 /* DENALI_PHY_351_DATA */
+ 0x00000000 /* DENALI_PHY_352_DATA */
+ 0x00000000 /* DENALI_PHY_353_DATA */
+ 0x00000000 /* DENALI_PHY_354_DATA */
+ 0x00000000 /* DENALI_PHY_355_DATA */
+ 0x00000000 /* DENALI_PHY_356_DATA */
+ 0x00000000 /* DENALI_PHY_357_DATA */
+ 0x00000000 /* DENALI_PHY_358_DATA */
+ 0x00000000 /* DENALI_PHY_359_DATA */
+ 0x00000000 /* DENALI_PHY_360_DATA */
+ 0x00000000 /* DENALI_PHY_361_DATA */
+ 0x00000000 /* DENALI_PHY_362_DATA */
+ 0x00000000 /* DENALI_PHY_363_DATA */
+ 0x00000000 /* DENALI_PHY_364_DATA */
+ 0x00000000 /* DENALI_PHY_365_DATA */
+ 0x00000000 /* DENALI_PHY_366_DATA */
+ 0x00000000 /* DENALI_PHY_367_DATA */
+ 0x00000000 /* DENALI_PHY_368_DATA */
+ 0x00000000 /* DENALI_PHY_369_DATA */
+ 0x00000000 /* DENALI_PHY_370_DATA */
+ 0x00000000 /* DENALI_PHY_371_DATA */
+ 0x00000000 /* DENALI_PHY_372_DATA */
+ 0x00000000 /* DENALI_PHY_373_DATA */
+ 0x00000000 /* DENALI_PHY_374_DATA */
+ 0x00000000 /* DENALI_PHY_375_DATA */
+ 0x00000000 /* DENALI_PHY_376_DATA */
+ 0x00000000 /* DENALI_PHY_377_DATA */
+ 0x00000000 /* DENALI_PHY_378_DATA */
+ 0x00000000 /* DENALI_PHY_379_DATA */
+ 0x00000000 /* DENALI_PHY_380_DATA */
+ 0x00000000 /* DENALI_PHY_381_DATA */
+ 0x00000000 /* DENALI_PHY_382_DATA */
+ 0x00000000 /* DENALI_PHY_383_DATA */
+ 0x37651240 /* DENALI_PHY_384_DATA */
+ 0x0004c008 /* DENALI_PHY_385_DATA */
+ 0x00000120 /* DENALI_PHY_386_DATA */
+ 0x00000000 /* DENALI_PHY_387_DATA */
+ 0x00000000 /* DENALI_PHY_388_DATA */
+ 0x00010000 /* DENALI_PHY_389_DATA */
+ 0x01DDDD90 /* DENALI_PHY_390_DATA */
+ 0x01DDDD90 /* DENALI_PHY_391_DATA */
+ 0x01030000 /* DENALI_PHY_392_DATA */
+ 0x01000000 /* DENALI_PHY_393_DATA */
+ 0x00c00000 /* DENALI_PHY_394_DATA */
+ 0x00000007 /* DENALI_PHY_395_DATA */
+ 0x00000000 /* DENALI_PHY_396_DATA */
+ 0x00000000 /* DENALI_PHY_397_DATA */
+ 0x04000408 /* DENALI_PHY_398_DATA */
+ 0x00000408 /* DENALI_PHY_399_DATA */
+ 0x00e4e400 /* DENALI_PHY_400_DATA */
+ 0x00000000 /* DENALI_PHY_401_DATA */
+ 0x00000000 /* DENALI_PHY_402_DATA */
+ 0x00000000 /* DENALI_PHY_403_DATA */
+ 0x00000000 /* DENALI_PHY_404_DATA */
+ 0x00000000 /* DENALI_PHY_405_DATA */
+ 0x00000000 /* DENALI_PHY_406_DATA */
+ 0x00000000 /* DENALI_PHY_407_DATA */
+ 0x00000000 /* DENALI_PHY_408_DATA */
+ 0x00000000 /* DENALI_PHY_409_DATA */
+ 0x00000000 /* DENALI_PHY_410_DATA */
+ 0x00000000 /* DENALI_PHY_411_DATA */
+ 0x00000000 /* DENALI_PHY_412_DATA */
+ 0x00000000 /* DENALI_PHY_413_DATA */
+ 0x00000000 /* DENALI_PHY_414_DATA */
+ 0x00000000 /* DENALI_PHY_415_DATA */
+ 0x00000000 /* DENALI_PHY_416_DATA */
+ 0x00200000 /* DENALI_PHY_417_DATA */
+ 0x00000000 /* DENALI_PHY_418_DATA */
+ 0x00000000 /* DENALI_PHY_419_DATA */
+ 0x00000000 /* DENALI_PHY_420_DATA */
+ 0x00000000 /* DENALI_PHY_421_DATA */
+ 0x00000000 /* DENALI_PHY_422_DATA */
+ 0x00000000 /* DENALI_PHY_423_DATA */
+ 0x02800280 /* DENALI_PHY_424_DATA */
+ 0x02800280 /* DENALI_PHY_425_DATA */
+ 0x02800280 /* DENALI_PHY_426_DATA */
+ 0x02800280 /* DENALI_PHY_427_DATA */
+ 0x00000280 /* DENALI_PHY_428_DATA */
+ 0x00000000 /* DENALI_PHY_429_DATA */
+ 0x00000000 /* DENALI_PHY_430_DATA */
+ 0x00000000 /* DENALI_PHY_431_DATA */
+ 0x00000000 /* DENALI_PHY_432_DATA */
+ 0x00000000 /* DENALI_PHY_433_DATA */
+ 0x00800080 /* DENALI_PHY_434_DATA */
+ 0x00800080 /* DENALI_PHY_435_DATA */
+ 0x00800080 /* DENALI_PHY_436_DATA */
+ 0x00800080 /* DENALI_PHY_437_DATA */
+ 0x00800080 /* DENALI_PHY_438_DATA */
+ 0x00800080 /* DENALI_PHY_439_DATA */
+ 0x00800080 /* DENALI_PHY_440_DATA */
+ 0x00800080 /* DENALI_PHY_441_DATA */
+ 0x00800080 /* DENALI_PHY_442_DATA */
+ 0x00010120 /* DENALI_PHY_443_DATA */
+ 0x000001d0 /* DENALI_PHY_444_DATA */
+ 0x01000000 /* DENALI_PHY_445_DATA */
+ 0x00000000 /* DENALI_PHY_446_DATA */
+ 0x00000002 /* DENALI_PHY_447_DATA */
+ 0x51313152 /* DENALI_PHY_448_DATA */
+ 0x80013130 /* DENALI_PHY_449_DATA */
+ 0x03000080 /* DENALI_PHY_450_DATA */
+ 0x00100002 /* DENALI_PHY_451_DATA */
+ 0x0c064208 /* DENALI_PHY_452_DATA */
+ 0x000f0c0f /* DENALI_PHY_453_DATA */
+ 0x01000140 /* DENALI_PHY_454_DATA */
+ 0x0000000c /* DENALI_PHY_455_DATA */
+ 0x00000000 /* DENALI_PHY_456_DATA */
+ 0x00000000 /* DENALI_PHY_457_DATA */
+ 0x00000000 /* DENALI_PHY_458_DATA */
+ 0x00000000 /* DENALI_PHY_459_DATA */
+ 0x00000000 /* DENALI_PHY_460_DATA */
+ 0x00000000 /* DENALI_PHY_461_DATA */
+ 0x00000000 /* DENALI_PHY_462_DATA */
+ 0x00000000 /* DENALI_PHY_463_DATA */
+ 0x00000000 /* DENALI_PHY_464_DATA */
+ 0x00000000 /* DENALI_PHY_465_DATA */
+ 0x00000000 /* DENALI_PHY_466_DATA */
+ 0x00000000 /* DENALI_PHY_467_DATA */
+ 0x00000000 /* DENALI_PHY_468_DATA */
+ 0x00000000 /* DENALI_PHY_469_DATA */
+ 0x00000000 /* DENALI_PHY_470_DATA */
+ 0x00000000 /* DENALI_PHY_471_DATA */
+ 0x00000000 /* DENALI_PHY_472_DATA */
+ 0x00000000 /* DENALI_PHY_473_DATA */
+ 0x00000000 /* DENALI_PHY_474_DATA */
+ 0x00000000 /* DENALI_PHY_475_DATA */
+ 0x00000000 /* DENALI_PHY_476_DATA */
+ 0x00000000 /* DENALI_PHY_477_DATA */
+ 0x00000000 /* DENALI_PHY_478_DATA */
+ 0x00000000 /* DENALI_PHY_479_DATA */
+ 0x00000000 /* DENALI_PHY_480_DATA */
+ 0x00000000 /* DENALI_PHY_481_DATA */
+ 0x00000000 /* DENALI_PHY_482_DATA */
+ 0x00000000 /* DENALI_PHY_483_DATA */
+ 0x00000000 /* DENALI_PHY_484_DATA */
+ 0x00000000 /* DENALI_PHY_485_DATA */
+ 0x00000000 /* DENALI_PHY_486_DATA */
+ 0x00000000 /* DENALI_PHY_487_DATA */
+ 0x00000000 /* DENALI_PHY_488_DATA */
+ 0x00000000 /* DENALI_PHY_489_DATA */
+ 0x00000000 /* DENALI_PHY_490_DATA */
+ 0x00000000 /* DENALI_PHY_491_DATA */
+ 0x00000000 /* DENALI_PHY_492_DATA */
+ 0x00000000 /* DENALI_PHY_493_DATA */
+ 0x00000000 /* DENALI_PHY_494_DATA */
+ 0x00000000 /* DENALI_PHY_495_DATA */
+ 0x00000000 /* DENALI_PHY_496_DATA */
+ 0x00000000 /* DENALI_PHY_497_DATA */
+ 0x00000000 /* DENALI_PHY_498_DATA */
+ 0x00000000 /* DENALI_PHY_499_DATA */
+ 0x00000000 /* DENALI_PHY_500_DATA */
+ 0x00000000 /* DENALI_PHY_501_DATA */
+ 0x00000000 /* DENALI_PHY_502_DATA */
+ 0x00000000 /* DENALI_PHY_503_DATA */
+ 0x00000000 /* DENALI_PHY_504_DATA */
+ 0x00000000 /* DENALI_PHY_505_DATA */
+ 0x00000000 /* DENALI_PHY_506_DATA */
+ 0x00000000 /* DENALI_PHY_507_DATA */
+ 0x00000000 /* DENALI_PHY_508_DATA */
+ 0x00000000 /* DENALI_PHY_509_DATA */
+ 0x00000000 /* DENALI_PHY_510_DATA */
+ 0x00000000 /* DENALI_PHY_511_DATA */
+ 0x34216750 /* DENALI_PHY_512_DATA */
+ 0x0004c008 /* DENALI_PHY_513_DATA */
+ 0x00000120 /* DENALI_PHY_514_DATA */
+ 0x00000000 /* DENALI_PHY_515_DATA */
+ 0x00000000 /* DENALI_PHY_516_DATA */
+ 0x00010000 /* DENALI_PHY_517_DATA */
+ 0x01DDDD90 /* DENALI_PHY_518_DATA */
+ 0x01DDDD90 /* DENALI_PHY_519_DATA */
+ 0x01030000 /* DENALI_PHY_520_DATA */
+ 0x01000000 /* DENALI_PHY_521_DATA */
+ 0x00c00000 /* DENALI_PHY_522_DATA */
+ 0x00000007 /* DENALI_PHY_523_DATA */
+ 0x00000000 /* DENALI_PHY_524_DATA */
+ 0x00000000 /* DENALI_PHY_525_DATA */
+ 0x04000408 /* DENALI_PHY_526_DATA */
+ 0x00000408 /* DENALI_PHY_527_DATA */
+ 0x00e4e400 /* DENALI_PHY_528_DATA */
+ 0x00000000 /* DENALI_PHY_529_DATA */
+ 0x00000000 /* DENALI_PHY_530_DATA */
+ 0x00000000 /* DENALI_PHY_531_DATA */
+ 0x00000000 /* DENALI_PHY_532_DATA */
+ 0x00000000 /* DENALI_PHY_533_DATA */
+ 0x00000000 /* DENALI_PHY_534_DATA */
+ 0x00000000 /* DENALI_PHY_535_DATA */
+ 0x00000000 /* DENALI_PHY_536_DATA */
+ 0x00000000 /* DENALI_PHY_537_DATA */
+ 0x00000000 /* DENALI_PHY_538_DATA */
+ 0x00000000 /* DENALI_PHY_539_DATA */
+ 0x00000000 /* DENALI_PHY_540_DATA */
+ 0x00000000 /* DENALI_PHY_541_DATA */
+ 0x00000000 /* DENALI_PHY_542_DATA */
+ 0x00000000 /* DENALI_PHY_543_DATA */
+ 0x00000000 /* DENALI_PHY_544_DATA */
+ 0x00200000 /* DENALI_PHY_545_DATA */
+ 0x00000000 /* DENALI_PHY_546_DATA */
+ 0x00000000 /* DENALI_PHY_547_DATA */
+ 0x00000000 /* DENALI_PHY_548_DATA */
+ 0x00000000 /* DENALI_PHY_549_DATA */
+ 0x00000000 /* DENALI_PHY_550_DATA */
+ 0x00000000 /* DENALI_PHY_551_DATA */
+ 0x02800280 /* DENALI_PHY_552_DATA */
+ 0x02800280 /* DENALI_PHY_553_DATA */
+ 0x02800280 /* DENALI_PHY_554_DATA */
+ 0x02800280 /* DENALI_PHY_555_DATA */
+ 0x00000280 /* DENALI_PHY_556_DATA */
+ 0x00000000 /* DENALI_PHY_557_DATA */
+ 0x00000000 /* DENALI_PHY_558_DATA */
+ 0x00000000 /* DENALI_PHY_559_DATA */
+ 0x00000000 /* DENALI_PHY_560_DATA */
+ 0x00000000 /* DENALI_PHY_561_DATA */
+ 0x00800080 /* DENALI_PHY_562_DATA */
+ 0x00800080 /* DENALI_PHY_563_DATA */
+ 0x00800080 /* DENALI_PHY_564_DATA */
+ 0x00800080 /* DENALI_PHY_565_DATA */
+ 0x00800080 /* DENALI_PHY_566_DATA */
+ 0x00800080 /* DENALI_PHY_567_DATA */
+ 0x00800080 /* DENALI_PHY_568_DATA */
+ 0x00800080 /* DENALI_PHY_569_DATA */
+ 0x00800080 /* DENALI_PHY_570_DATA */
+ 0x00010120 /* DENALI_PHY_571_DATA */
+ 0x000001d0 /* DENALI_PHY_572_DATA */
+ 0x01000000 /* DENALI_PHY_573_DATA */
+ 0x00000000 /* DENALI_PHY_574_DATA */
+ 0x00000002 /* DENALI_PHY_575_DATA */
+ 0x51313152 /* DENALI_PHY_576_DATA */
+ 0x80013130 /* DENALI_PHY_577_DATA */
+ 0x03000080 /* DENALI_PHY_578_DATA */
+ 0x00100002 /* DENALI_PHY_579_DATA */
+ 0x0c064208 /* DENALI_PHY_580_DATA */
+ 0x000f0c0f /* DENALI_PHY_581_DATA */
+ 0x01000140 /* DENALI_PHY_582_DATA */
+ 0x0000000c /* DENALI_PHY_583_DATA */
+ 0x00000000 /* DENALI_PHY_584_DATA */
+ 0x00000000 /* DENALI_PHY_585_DATA */
+ 0x00000000 /* DENALI_PHY_586_DATA */
+ 0x00000000 /* DENALI_PHY_587_DATA */
+ 0x00000000 /* DENALI_PHY_588_DATA */
+ 0x00000000 /* DENALI_PHY_589_DATA */
+ 0x00000000 /* DENALI_PHY_590_DATA */
+ 0x00000000 /* DENALI_PHY_591_DATA */
+ 0x00000000 /* DENALI_PHY_592_DATA */
+ 0x00000000 /* DENALI_PHY_593_DATA */
+ 0x00000000 /* DENALI_PHY_594_DATA */
+ 0x00000000 /* DENALI_PHY_595_DATA */
+ 0x00000000 /* DENALI_PHY_596_DATA */
+ 0x00000000 /* DENALI_PHY_597_DATA */
+ 0x00000000 /* DENALI_PHY_598_DATA */
+ 0x00000000 /* DENALI_PHY_599_DATA */
+ 0x00000000 /* DENALI_PHY_600_DATA */
+ 0x00000000 /* DENALI_PHY_601_DATA */
+ 0x00000000 /* DENALI_PHY_602_DATA */
+ 0x00000000 /* DENALI_PHY_603_DATA */
+ 0x00000000 /* DENALI_PHY_604_DATA */
+ 0x00000000 /* DENALI_PHY_605_DATA */
+ 0x00000000 /* DENALI_PHY_606_DATA */
+ 0x00000000 /* DENALI_PHY_607_DATA */
+ 0x00000000 /* DENALI_PHY_608_DATA */
+ 0x00000000 /* DENALI_PHY_609_DATA */
+ 0x00000000 /* DENALI_PHY_610_DATA */
+ 0x00000000 /* DENALI_PHY_611_DATA */
+ 0x00000000 /* DENALI_PHY_612_DATA */
+ 0x00000000 /* DENALI_PHY_613_DATA */
+ 0x00000000 /* DENALI_PHY_614_DATA */
+ 0x00000000 /* DENALI_PHY_615_DATA */
+ 0x00000000 /* DENALI_PHY_616_DATA */
+ 0x00000000 /* DENALI_PHY_617_DATA */
+ 0x00000000 /* DENALI_PHY_618_DATA */
+ 0x00000000 /* DENALI_PHY_619_DATA */
+ 0x00000000 /* DENALI_PHY_620_DATA */
+ 0x00000000 /* DENALI_PHY_621_DATA */
+ 0x00000000 /* DENALI_PHY_622_DATA */
+ 0x00000000 /* DENALI_PHY_623_DATA */
+ 0x00000000 /* DENALI_PHY_624_DATA */
+ 0x00000000 /* DENALI_PHY_625_DATA */
+ 0x00000000 /* DENALI_PHY_626_DATA */
+ 0x00000000 /* DENALI_PHY_627_DATA */
+ 0x00000000 /* DENALI_PHY_628_DATA */
+ 0x00000000 /* DENALI_PHY_629_DATA */
+ 0x00000000 /* DENALI_PHY_630_DATA */
+ 0x00000000 /* DENALI_PHY_631_DATA */
+ 0x00000000 /* DENALI_PHY_632_DATA */
+ 0x00000000 /* DENALI_PHY_633_DATA */
+ 0x00000000 /* DENALI_PHY_634_DATA */
+ 0x00000000 /* DENALI_PHY_635_DATA */
+ 0x00000000 /* DENALI_PHY_636_DATA */
+ 0x00000000 /* DENALI_PHY_637_DATA */
+ 0x00000000 /* DENALI_PHY_638_DATA */
+ 0x00000000 /* DENALI_PHY_639_DATA */
+ 0x35176402 /* DENALI_PHY_640_DATA */
+ 0x0004c008 /* DENALI_PHY_641_DATA */
+ 0x00000120 /* DENALI_PHY_642_DATA */
+ 0x00000000 /* DENALI_PHY_643_DATA */
+ 0x00000000 /* DENALI_PHY_644_DATA */
+ 0x00010000 /* DENALI_PHY_645_DATA */
+ 0x01DDDD90 /* DENALI_PHY_646_DATA */
+ 0x01DDDD90 /* DENALI_PHY_647_DATA */
+ 0x01030000 /* DENALI_PHY_648_DATA */
+ 0x01000000 /* DENALI_PHY_649_DATA */
+ 0x00c00000 /* DENALI_PHY_650_DATA */
+ 0x00000007 /* DENALI_PHY_651_DATA */
+ 0x00000000 /* DENALI_PHY_652_DATA */
+ 0x00000000 /* DENALI_PHY_653_DATA */
+ 0x04000408 /* DENALI_PHY_654_DATA */
+ 0x00000408 /* DENALI_PHY_655_DATA */
+ 0x00e4e400 /* DENALI_PHY_656_DATA */
+ 0x00000000 /* DENALI_PHY_657_DATA */
+ 0x00000000 /* DENALI_PHY_658_DATA */
+ 0x00000000 /* DENALI_PHY_659_DATA */
+ 0x00000000 /* DENALI_PHY_660_DATA */
+ 0x00000000 /* DENALI_PHY_661_DATA */
+ 0x00000000 /* DENALI_PHY_662_DATA */
+ 0x00000000 /* DENALI_PHY_663_DATA */
+ 0x00000000 /* DENALI_PHY_664_DATA */
+ 0x00000000 /* DENALI_PHY_665_DATA */
+ 0x00000000 /* DENALI_PHY_666_DATA */
+ 0x00000000 /* DENALI_PHY_667_DATA */
+ 0x00000000 /* DENALI_PHY_668_DATA */
+ 0x00000000 /* DENALI_PHY_669_DATA */
+ 0x00000000 /* DENALI_PHY_670_DATA */
+ 0x00000000 /* DENALI_PHY_671_DATA */
+ 0x00000000 /* DENALI_PHY_672_DATA */
+ 0x00200000 /* DENALI_PHY_673_DATA */
+ 0x00000000 /* DENALI_PHY_674_DATA */
+ 0x00000000 /* DENALI_PHY_675_DATA */
+ 0x00000000 /* DENALI_PHY_676_DATA */
+ 0x00000000 /* DENALI_PHY_677_DATA */
+ 0x00000000 /* DENALI_PHY_678_DATA */
+ 0x00000000 /* DENALI_PHY_679_DATA */
+ 0x02800280 /* DENALI_PHY_680_DATA */
+ 0x02800280 /* DENALI_PHY_681_DATA */
+ 0x02800280 /* DENALI_PHY_682_DATA */
+ 0x02800280 /* DENALI_PHY_683_DATA */
+ 0x00000280 /* DENALI_PHY_684_DATA */
+ 0x00000000 /* DENALI_PHY_685_DATA */
+ 0x00000000 /* DENALI_PHY_686_DATA */
+ 0x00000000 /* DENALI_PHY_687_DATA */
+ 0x00000000 /* DENALI_PHY_688_DATA */
+ 0x00000000 /* DENALI_PHY_689_DATA */
+ 0x00800080 /* DENALI_PHY_690_DATA */
+ 0x00800080 /* DENALI_PHY_691_DATA */
+ 0x00800080 /* DENALI_PHY_692_DATA */
+ 0x00800080 /* DENALI_PHY_693_DATA */
+ 0x00800080 /* DENALI_PHY_694_DATA */
+ 0x00800080 /* DENALI_PHY_695_DATA */
+ 0x00800080 /* DENALI_PHY_696_DATA */
+ 0x00800080 /* DENALI_PHY_697_DATA */
+ 0x00800080 /* DENALI_PHY_698_DATA */
+ 0x00010120 /* DENALI_PHY_699_DATA */
+ 0x000001d0 /* DENALI_PHY_700_DATA */
+ 0x01000000 /* DENALI_PHY_701_DATA */
+ 0x00000000 /* DENALI_PHY_702_DATA */
+ 0x00000002 /* DENALI_PHY_703_DATA */
+ 0x51313152 /* DENALI_PHY_704_DATA */
+ 0x80013130 /* DENALI_PHY_705_DATA */
+ 0x03000080 /* DENALI_PHY_706_DATA */
+ 0x00100002 /* DENALI_PHY_707_DATA */
+ 0x0c064208 /* DENALI_PHY_708_DATA */
+ 0x000f0c0f /* DENALI_PHY_709_DATA */
+ 0x01000140 /* DENALI_PHY_710_DATA */
+ 0x0000000c /* DENALI_PHY_711_DATA */
+ 0x00000000 /* DENALI_PHY_712_DATA */
+ 0x00000000 /* DENALI_PHY_713_DATA */
+ 0x00000000 /* DENALI_PHY_714_DATA */
+ 0x00000000 /* DENALI_PHY_715_DATA */
+ 0x00000000 /* DENALI_PHY_716_DATA */
+ 0x00000000 /* DENALI_PHY_717_DATA */
+ 0x00000000 /* DENALI_PHY_718_DATA */
+ 0x00000000 /* DENALI_PHY_719_DATA */
+ 0x00000000 /* DENALI_PHY_720_DATA */
+ 0x00000000 /* DENALI_PHY_721_DATA */
+ 0x00000000 /* DENALI_PHY_722_DATA */
+ 0x00000000 /* DENALI_PHY_723_DATA */
+ 0x00000000 /* DENALI_PHY_724_DATA */
+ 0x00000000 /* DENALI_PHY_725_DATA */
+ 0x00000000 /* DENALI_PHY_726_DATA */
+ 0x00000000 /* DENALI_PHY_727_DATA */
+ 0x00000000 /* DENALI_PHY_728_DATA */
+ 0x00000000 /* DENALI_PHY_729_DATA */
+ 0x00000000 /* DENALI_PHY_730_DATA */
+ 0x00000000 /* DENALI_PHY_731_DATA */
+ 0x00000000 /* DENALI_PHY_732_DATA */
+ 0x00000000 /* DENALI_PHY_733_DATA */
+ 0x00000000 /* DENALI_PHY_734_DATA */
+ 0x00000000 /* DENALI_PHY_735_DATA */
+ 0x00000000 /* DENALI_PHY_736_DATA */
+ 0x00000000 /* DENALI_PHY_737_DATA */
+ 0x00000000 /* DENALI_PHY_738_DATA */
+ 0x00000000 /* DENALI_PHY_739_DATA */
+ 0x00000000 /* DENALI_PHY_740_DATA */
+ 0x00000000 /* DENALI_PHY_741_DATA */
+ 0x00000000 /* DENALI_PHY_742_DATA */
+ 0x00000000 /* DENALI_PHY_743_DATA */
+ 0x00000000 /* DENALI_PHY_744_DATA */
+ 0x00000000 /* DENALI_PHY_745_DATA */
+ 0x00000000 /* DENALI_PHY_746_DATA */
+ 0x00000000 /* DENALI_PHY_747_DATA */
+ 0x00000000 /* DENALI_PHY_748_DATA */
+ 0x00000000 /* DENALI_PHY_749_DATA */
+ 0x00000000 /* DENALI_PHY_750_DATA */
+ 0x00000000 /* DENALI_PHY_751_DATA */
+ 0x00000000 /* DENALI_PHY_752_DATA */
+ 0x00000000 /* DENALI_PHY_753_DATA */
+ 0x00000000 /* DENALI_PHY_754_DATA */
+ 0x00000000 /* DENALI_PHY_755_DATA */
+ 0x00000000 /* DENALI_PHY_756_DATA */
+ 0x00000000 /* DENALI_PHY_757_DATA */
+ 0x00000000 /* DENALI_PHY_758_DATA */
+ 0x00000000 /* DENALI_PHY_759_DATA */
+ 0x00000000 /* DENALI_PHY_760_DATA */
+ 0x00000000 /* DENALI_PHY_761_DATA */
+ 0x00000000 /* DENALI_PHY_762_DATA */
+ 0x00000000 /* DENALI_PHY_763_DATA */
+ 0x00000000 /* DENALI_PHY_764_DATA */
+ 0x00000000 /* DENALI_PHY_765_DATA */
+ 0x00000000 /* DENALI_PHY_766_DATA */
+ 0x00000000 /* DENALI_PHY_767_DATA */
+ 0x10526347 /* DENALI_PHY_768_DATA */
+ 0x0004c008 /* DENALI_PHY_769_DATA */
+ 0x00000120 /* DENALI_PHY_770_DATA */
+ 0x00000000 /* DENALI_PHY_771_DATA */
+ 0x00000000 /* DENALI_PHY_772_DATA */
+ 0x00010000 /* DENALI_PHY_773_DATA */
+ 0x01DDDD90 /* DENALI_PHY_774_DATA */
+ 0x01DDDD90 /* DENALI_PHY_775_DATA */
+ 0x01030000 /* DENALI_PHY_776_DATA */
+ 0x01000000 /* DENALI_PHY_777_DATA */
+ 0x00c00000 /* DENALI_PHY_778_DATA */
+ 0x00000007 /* DENALI_PHY_779_DATA */
+ 0x00000000 /* DENALI_PHY_780_DATA */
+ 0x00000000 /* DENALI_PHY_781_DATA */
+ 0x04000408 /* DENALI_PHY_782_DATA */
+ 0x00000408 /* DENALI_PHY_783_DATA */
+ 0x00e4e400 /* DENALI_PHY_784_DATA */
+ 0x00000000 /* DENALI_PHY_785_DATA */
+ 0x00000000 /* DENALI_PHY_786_DATA */
+ 0x00000000 /* DENALI_PHY_787_DATA */
+ 0x00000000 /* DENALI_PHY_788_DATA */
+ 0x00000000 /* DENALI_PHY_789_DATA */
+ 0x00000000 /* DENALI_PHY_790_DATA */
+ 0x00000000 /* DENALI_PHY_791_DATA */
+ 0x00000000 /* DENALI_PHY_792_DATA */
+ 0x00000000 /* DENALI_PHY_793_DATA */
+ 0x00000000 /* DENALI_PHY_794_DATA */
+ 0x00000000 /* DENALI_PHY_795_DATA */
+ 0x00000000 /* DENALI_PHY_796_DATA */
+ 0x00000000 /* DENALI_PHY_797_DATA */
+ 0x00000000 /* DENALI_PHY_798_DATA */
+ 0x00000000 /* DENALI_PHY_799_DATA */
+ 0x00000000 /* DENALI_PHY_800_DATA */
+ 0x00200000 /* DENALI_PHY_801_DATA */
+ 0x00000000 /* DENALI_PHY_802_DATA */
+ 0x00000000 /* DENALI_PHY_803_DATA */
+ 0x00000000 /* DENALI_PHY_804_DATA */
+ 0x00000000 /* DENALI_PHY_805_DATA */
+ 0x00000000 /* DENALI_PHY_806_DATA */
+ 0x00000000 /* DENALI_PHY_807_DATA */
+ 0x02800280 /* DENALI_PHY_808_DATA */
+ 0x02800280 /* DENALI_PHY_809_DATA */
+ 0x02800280 /* DENALI_PHY_810_DATA */
+ 0x02800280 /* DENALI_PHY_811_DATA */
+ 0x00000280 /* DENALI_PHY_812_DATA */
+ 0x00000000 /* DENALI_PHY_813_DATA */
+ 0x00000000 /* DENALI_PHY_814_DATA */
+ 0x00000000 /* DENALI_PHY_815_DATA */
+ 0x00000000 /* DENALI_PHY_816_DATA */
+ 0x00000000 /* DENALI_PHY_817_DATA */
+ 0x00800080 /* DENALI_PHY_818_DATA */
+ 0x00800080 /* DENALI_PHY_819_DATA */
+ 0x00800080 /* DENALI_PHY_820_DATA */
+ 0x00800080 /* DENALI_PHY_821_DATA */
+ 0x00800080 /* DENALI_PHY_822_DATA */
+ 0x00800080 /* DENALI_PHY_823_DATA */
+ 0x00800080 /* DENALI_PHY_824_DATA */
+ 0x00800080 /* DENALI_PHY_825_DATA */
+ 0x00800080 /* DENALI_PHY_826_DATA */
+ 0x00010120 /* DENALI_PHY_827_DATA */
+ 0x000001d0 /* DENALI_PHY_828_DATA */
+ 0x01000000 /* DENALI_PHY_829_DATA */
+ 0x00000000 /* DENALI_PHY_830_DATA */
+ 0x00000002 /* DENALI_PHY_831_DATA */
+ 0x51313152 /* DENALI_PHY_832_DATA */
+ 0x80013130 /* DENALI_PHY_833_DATA */
+ 0x03000080 /* DENALI_PHY_834_DATA */
+ 0x00100002 /* DENALI_PHY_835_DATA */
+ 0x0c064208 /* DENALI_PHY_836_DATA */
+ 0x000f0c0f /* DENALI_PHY_837_DATA */
+ 0x01000140 /* DENALI_PHY_838_DATA */
+ 0x0000000c /* DENALI_PHY_839_DATA */
+ 0x00000000 /* DENALI_PHY_840_DATA */
+ 0x00000000 /* DENALI_PHY_841_DATA */
+ 0x00000000 /* DENALI_PHY_842_DATA */
+ 0x00000000 /* DENALI_PHY_843_DATA */
+ 0x00000000 /* DENALI_PHY_844_DATA */
+ 0x00000000 /* DENALI_PHY_845_DATA */
+ 0x00000000 /* DENALI_PHY_846_DATA */
+ 0x00000000 /* DENALI_PHY_847_DATA */
+ 0x00000000 /* DENALI_PHY_848_DATA */
+ 0x00000000 /* DENALI_PHY_849_DATA */
+ 0x00000000 /* DENALI_PHY_850_DATA */
+ 0x00000000 /* DENALI_PHY_851_DATA */
+ 0x00000000 /* DENALI_PHY_852_DATA */
+ 0x00000000 /* DENALI_PHY_853_DATA */
+ 0x00000000 /* DENALI_PHY_854_DATA */
+ 0x00000000 /* DENALI_PHY_855_DATA */
+ 0x00000000 /* DENALI_PHY_856_DATA */
+ 0x00000000 /* DENALI_PHY_857_DATA */
+ 0x00000000 /* DENALI_PHY_858_DATA */
+ 0x00000000 /* DENALI_PHY_859_DATA */
+ 0x00000000 /* DENALI_PHY_860_DATA */
+ 0x00000000 /* DENALI_PHY_861_DATA */
+ 0x00000000 /* DENALI_PHY_862_DATA */
+ 0x00000000 /* DENALI_PHY_863_DATA */
+ 0x00000000 /* DENALI_PHY_864_DATA */
+ 0x00000000 /* DENALI_PHY_865_DATA */
+ 0x00000000 /* DENALI_PHY_866_DATA */
+ 0x00000000 /* DENALI_PHY_867_DATA */
+ 0x00000000 /* DENALI_PHY_868_DATA */
+ 0x00000000 /* DENALI_PHY_869_DATA */
+ 0x00000000 /* DENALI_PHY_870_DATA */
+ 0x00000000 /* DENALI_PHY_871_DATA */
+ 0x00000000 /* DENALI_PHY_872_DATA */
+ 0x00000000 /* DENALI_PHY_873_DATA */
+ 0x00000000 /* DENALI_PHY_874_DATA */
+ 0x00000000 /* DENALI_PHY_875_DATA */
+ 0x00000000 /* DENALI_PHY_876_DATA */
+ 0x00000000 /* DENALI_PHY_877_DATA */
+ 0x00000000 /* DENALI_PHY_878_DATA */
+ 0x00000000 /* DENALI_PHY_879_DATA */
+ 0x00000000 /* DENALI_PHY_880_DATA */
+ 0x00000000 /* DENALI_PHY_881_DATA */
+ 0x00000000 /* DENALI_PHY_882_DATA */
+ 0x00000000 /* DENALI_PHY_883_DATA */
+ 0x00000000 /* DENALI_PHY_884_DATA */
+ 0x00000000 /* DENALI_PHY_885_DATA */
+ 0x00000000 /* DENALI_PHY_886_DATA */
+ 0x00000000 /* DENALI_PHY_887_DATA */
+ 0x00000000 /* DENALI_PHY_888_DATA */
+ 0x00000000 /* DENALI_PHY_889_DATA */
+ 0x00000000 /* DENALI_PHY_890_DATA */
+ 0x00000000 /* DENALI_PHY_891_DATA */
+ 0x00000000 /* DENALI_PHY_892_DATA */
+ 0x00000000 /* DENALI_PHY_893_DATA */
+ 0x00000000 /* DENALI_PHY_894_DATA */
+ 0x00000000 /* DENALI_PHY_895_DATA */
+ 0x41753260 /* DENALI_PHY_896_DATA */
+ 0x0004c008 /* DENALI_PHY_897_DATA */
+ 0x00000120 /* DENALI_PHY_898_DATA */
+ 0x00000000 /* DENALI_PHY_899_DATA */
+ 0x00000000 /* DENALI_PHY_900_DATA */
+ 0x00010000 /* DENALI_PHY_901_DATA */
+ 0x01DDDD90 /* DENALI_PHY_902_DATA */
+ 0x01DDDD90 /* DENALI_PHY_903_DATA */
+ 0x01030000 /* DENALI_PHY_904_DATA */
+ 0x01000000 /* DENALI_PHY_905_DATA */
+ 0x00c00000 /* DENALI_PHY_906_DATA */
+ 0x00000007 /* DENALI_PHY_907_DATA */
+ 0x00000000 /* DENALI_PHY_908_DATA */
+ 0x00000000 /* DENALI_PHY_909_DATA */
+ 0x04000408 /* DENALI_PHY_910_DATA */
+ 0x00000408 /* DENALI_PHY_911_DATA */
+ 0x00e4e400 /* DENALI_PHY_912_DATA */
+ 0x00000000 /* DENALI_PHY_913_DATA */
+ 0x00000000 /* DENALI_PHY_914_DATA */
+ 0x00000000 /* DENALI_PHY_915_DATA */
+ 0x00000000 /* DENALI_PHY_916_DATA */
+ 0x00000000 /* DENALI_PHY_917_DATA */
+ 0x00000000 /* DENALI_PHY_918_DATA */
+ 0x00000000 /* DENALI_PHY_919_DATA */
+ 0x00000000 /* DENALI_PHY_920_DATA */
+ 0x00000000 /* DENALI_PHY_921_DATA */
+ 0x00000000 /* DENALI_PHY_922_DATA */
+ 0x00000000 /* DENALI_PHY_923_DATA */
+ 0x00000000 /* DENALI_PHY_924_DATA */
+ 0x00000000 /* DENALI_PHY_925_DATA */
+ 0x00000000 /* DENALI_PHY_926_DATA */
+ 0x00000000 /* DENALI_PHY_927_DATA */
+ 0x00000000 /* DENALI_PHY_928_DATA */
+ 0x00200000 /* DENALI_PHY_929_DATA */
+ 0x00000000 /* DENALI_PHY_930_DATA */
+ 0x00000000 /* DENALI_PHY_931_DATA */
+ 0x00000000 /* DENALI_PHY_932_DATA */
+ 0x00000000 /* DENALI_PHY_933_DATA */
+ 0x00000000 /* DENALI_PHY_934_DATA */
+ 0x00000000 /* DENALI_PHY_935_DATA */
+ 0x02800280 /* DENALI_PHY_936_DATA */
+ 0x02800280 /* DENALI_PHY_937_DATA */
+ 0x02800280 /* DENALI_PHY_938_DATA */
+ 0x02800280 /* DENALI_PHY_939_DATA */
+ 0x00000280 /* DENALI_PHY_940_DATA */
+ 0x00000000 /* DENALI_PHY_941_DATA */
+ 0x00000000 /* DENALI_PHY_942_DATA */
+ 0x00000000 /* DENALI_PHY_943_DATA */
+ 0x00000000 /* DENALI_PHY_944_DATA */
+ 0x00000000 /* DENALI_PHY_945_DATA */
+ 0x00800080 /* DENALI_PHY_946_DATA */
+ 0x00800080 /* DENALI_PHY_947_DATA */
+ 0x00800080 /* DENALI_PHY_948_DATA */
+ 0x00800080 /* DENALI_PHY_949_DATA */
+ 0x00800080 /* DENALI_PHY_950_DATA */
+ 0x00800080 /* DENALI_PHY_951_DATA */
+ 0x00800080 /* DENALI_PHY_952_DATA */
+ 0x00800080 /* DENALI_PHY_953_DATA */
+ 0x00800080 /* DENALI_PHY_954_DATA */
+ 0x00010120 /* DENALI_PHY_955_DATA */
+ 0x000001d0 /* DENALI_PHY_956_DATA */
+ 0x01000000 /* DENALI_PHY_957_DATA */
+ 0x00000000 /* DENALI_PHY_958_DATA */
+ 0x00000002 /* DENALI_PHY_959_DATA */
+ 0x51313152 /* DENALI_PHY_960_DATA */
+ 0x80013130 /* DENALI_PHY_961_DATA */
+ 0x03000080 /* DENALI_PHY_962_DATA */
+ 0x00100002 /* DENALI_PHY_963_DATA */
+ 0x0c064208 /* DENALI_PHY_964_DATA */
+ 0x000f0c0f /* DENALI_PHY_965_DATA */
+ 0x01000140 /* DENALI_PHY_966_DATA */
+ 0x0000000c /* DENALI_PHY_967_DATA */
+ 0x00000000 /* DENALI_PHY_968_DATA */
+ 0x00000000 /* DENALI_PHY_969_DATA */
+ 0x00000000 /* DENALI_PHY_970_DATA */
+ 0x00000000 /* DENALI_PHY_971_DATA */
+ 0x00000000 /* DENALI_PHY_972_DATA */
+ 0x00000000 /* DENALI_PHY_973_DATA */
+ 0x00000000 /* DENALI_PHY_974_DATA */
+ 0x00000000 /* DENALI_PHY_975_DATA */
+ 0x00000000 /* DENALI_PHY_976_DATA */
+ 0x00000000 /* DENALI_PHY_977_DATA */
+ 0x00000000 /* DENALI_PHY_978_DATA */
+ 0x00000000 /* DENALI_PHY_979_DATA */
+ 0x00000000 /* DENALI_PHY_980_DATA */
+ 0x00000000 /* DENALI_PHY_981_DATA */
+ 0x00000000 /* DENALI_PHY_982_DATA */
+ 0x00000000 /* DENALI_PHY_983_DATA */
+ 0x00000000 /* DENALI_PHY_984_DATA */
+ 0x00000000 /* DENALI_PHY_985_DATA */
+ 0x00000000 /* DENALI_PHY_986_DATA */
+ 0x00000000 /* DENALI_PHY_987_DATA */
+ 0x00000000 /* DENALI_PHY_988_DATA */
+ 0x00000000 /* DENALI_PHY_989_DATA */
+ 0x00000000 /* DENALI_PHY_990_DATA */
+ 0x00000000 /* DENALI_PHY_991_DATA */
+ 0x00000000 /* DENALI_PHY_992_DATA */
+ 0x00000000 /* DENALI_PHY_993_DATA */
+ 0x00000000 /* DENALI_PHY_994_DATA */
+ 0x00000000 /* DENALI_PHY_995_DATA */
+ 0x00000000 /* DENALI_PHY_996_DATA */
+ 0x00000000 /* DENALI_PHY_997_DATA */
+ 0x00000000 /* DENALI_PHY_998_DATA */
+ 0x00000000 /* DENALI_PHY_999_DATA */
+ 0x00000000 /* DENALI_PHY_1000_DATA */
+ 0x00000000 /* DENALI_PHY_1001_DATA */
+ 0x00000000 /* DENALI_PHY_1002_DATA */
+ 0x00000000 /* DENALI_PHY_1003_DATA */
+ 0x00000000 /* DENALI_PHY_1004_DATA */
+ 0x00000000 /* DENALI_PHY_1005_DATA */
+ 0x00000000 /* DENALI_PHY_1006_DATA */
+ 0x00000000 /* DENALI_PHY_1007_DATA */
+ 0x00000000 /* DENALI_PHY_1008_DATA */
+ 0x00000000 /* DENALI_PHY_1009_DATA */
+ 0x00000000 /* DENALI_PHY_1010_DATA */
+ 0x00000000 /* DENALI_PHY_1011_DATA */
+ 0x00000000 /* DENALI_PHY_1012_DATA */
+ 0x00000000 /* DENALI_PHY_1013_DATA */
+ 0x00000000 /* DENALI_PHY_1014_DATA */
+ 0x00000000 /* DENALI_PHY_1015_DATA */
+ 0x00000000 /* DENALI_PHY_1016_DATA */
+ 0x00000000 /* DENALI_PHY_1017_DATA */
+ 0x00000000 /* DENALI_PHY_1018_DATA */
+ 0x00000000 /* DENALI_PHY_1019_DATA */
+ 0x00000000 /* DENALI_PHY_1020_DATA */
+ 0x00000000 /* DENALI_PHY_1021_DATA */
+ 0x00000000 /* DENALI_PHY_1022_DATA */
+ 0x00000000 /* DENALI_PHY_1023_DATA */
+ 0x76543210 /* DENALI_PHY_1024_DATA */
+ 0x0004c008 /* DENALI_PHY_1025_DATA */
+ 0x00000120 /* DENALI_PHY_1026_DATA */
+ 0x00000000 /* DENALI_PHY_1027_DATA */
+ 0x00000000 /* DENALI_PHY_1028_DATA */
+ 0x00010000 /* DENALI_PHY_1029_DATA */
+ 0x01DDDD90 /* DENALI_PHY_1030_DATA */
+ 0x01DDDD90 /* DENALI_PHY_1031_DATA */
+ 0x01030000 /* DENALI_PHY_1032_DATA */
+ 0x01000000 /* DENALI_PHY_1033_DATA */
+ 0x00c00000 /* DENALI_PHY_1034_DATA */
+ 0x00000007 /* DENALI_PHY_1035_DATA */
+ 0x00000000 /* DENALI_PHY_1036_DATA */
+ 0x00000000 /* DENALI_PHY_1037_DATA */
+ 0x04000408 /* DENALI_PHY_1038_DATA */
+ 0x00000408 /* DENALI_PHY_1039_DATA */
+ 0x00e4e400 /* DENALI_PHY_1040_DATA */
+ 0x00000000 /* DENALI_PHY_1041_DATA */
+ 0x00000000 /* DENALI_PHY_1042_DATA */
+ 0x00000000 /* DENALI_PHY_1043_DATA */
+ 0x00000000 /* DENALI_PHY_1044_DATA */
+ 0x00000000 /* DENALI_PHY_1045_DATA */
+ 0x00000000 /* DENALI_PHY_1046_DATA */
+ 0x00000000 /* DENALI_PHY_1047_DATA */
+ 0x00000000 /* DENALI_PHY_1048_DATA */
+ 0x00000000 /* DENALI_PHY_1049_DATA */
+ 0x00000000 /* DENALI_PHY_1050_DATA */
+ 0x00000000 /* DENALI_PHY_1051_DATA */
+ 0x00000000 /* DENALI_PHY_1052_DATA */
+ 0x00000000 /* DENALI_PHY_1053_DATA */
+ 0x00000000 /* DENALI_PHY_1054_DATA */
+ 0x00000000 /* DENALI_PHY_1055_DATA */
+ 0x00000000 /* DENALI_PHY_1056_DATA */
+ 0x00200000 /* DENALI_PHY_1057_DATA */
+ 0x00000000 /* DENALI_PHY_1058_DATA */
+ 0x00000000 /* DENALI_PHY_1059_DATA */
+ 0x00000000 /* DENALI_PHY_1060_DATA */
+ 0x00000000 /* DENALI_PHY_1061_DATA */
+ 0x00000000 /* DENALI_PHY_1062_DATA */
+ 0x00000000 /* DENALI_PHY_1063_DATA */
+ 0x02800280 /* DENALI_PHY_1064_DATA */
+ 0x02800280 /* DENALI_PHY_1065_DATA */
+ 0x02800280 /* DENALI_PHY_1066_DATA */
+ 0x02800280 /* DENALI_PHY_1067_DATA */
+ 0x00000280 /* DENALI_PHY_1068_DATA */
+ 0x00000000 /* DENALI_PHY_1069_DATA */
+ 0x00000000 /* DENALI_PHY_1070_DATA */
+ 0x00000000 /* DENALI_PHY_1071_DATA */
+ 0x00000000 /* DENALI_PHY_1072_DATA */
+ 0x00000000 /* DENALI_PHY_1073_DATA */
+ 0x00800080 /* DENALI_PHY_1074_DATA */
+ 0x00800080 /* DENALI_PHY_1075_DATA */
+ 0x00800080 /* DENALI_PHY_1076_DATA */
+ 0x00800080 /* DENALI_PHY_1077_DATA */
+ 0x00800080 /* DENALI_PHY_1078_DATA */
+ 0x00800080 /* DENALI_PHY_1079_DATA */
+ 0x00800080 /* DENALI_PHY_1080_DATA */
+ 0x00800080 /* DENALI_PHY_1081_DATA */
+ 0x00800080 /* DENALI_PHY_1082_DATA */
+ 0x00010120 /* DENALI_PHY_1083_DATA */
+ 0x000001d0 /* DENALI_PHY_1084_DATA */
+ 0x01000000 /* DENALI_PHY_1085_DATA */
+ 0x00000000 /* DENALI_PHY_1086_DATA */
+ 0x00000002 /* DENALI_PHY_1087_DATA */
+ 0x51313152 /* DENALI_PHY_1088_DATA */
+ 0x80013130 /* DENALI_PHY_1089_DATA */
+ 0x03000080 /* DENALI_PHY_1090_DATA */
+ 0x00100002 /* DENALI_PHY_1091_DATA */
+ 0x0c064208 /* DENALI_PHY_1092_DATA */
+ 0x000f0c0f /* DENALI_PHY_1093_DATA */
+ 0x01000140 /* DENALI_PHY_1094_DATA */
+ 0x0000000c /* DENALI_PHY_1095_DATA */
+ 0x00000000 /* DENALI_PHY_1096_DATA */
+ 0x00000000 /* DENALI_PHY_1097_DATA */
+ 0x00000000 /* DENALI_PHY_1098_DATA */
+ 0x00000000 /* DENALI_PHY_1099_DATA */
+ 0x00000000 /* DENALI_PHY_1100_DATA */
+ 0x00000000 /* DENALI_PHY_1101_DATA */
+ 0x00000000 /* DENALI_PHY_1102_DATA */
+ 0x00000000 /* DENALI_PHY_1103_DATA */
+ 0x00000000 /* DENALI_PHY_1104_DATA */
+ 0x00000000 /* DENALI_PHY_1105_DATA */
+ 0x00000000 /* DENALI_PHY_1106_DATA */
+ 0x00000000 /* DENALI_PHY_1107_DATA */
+ 0x00000000 /* DENALI_PHY_1108_DATA */
+ 0x00000000 /* DENALI_PHY_1109_DATA */
+ 0x00000000 /* DENALI_PHY_1110_DATA */
+ 0x00000000 /* DENALI_PHY_1111_DATA */
+ 0x00000000 /* DENALI_PHY_1112_DATA */
+ 0x00000000 /* DENALI_PHY_1113_DATA */
+ 0x00000000 /* DENALI_PHY_1114_DATA */
+ 0x00000000 /* DENALI_PHY_1115_DATA */
+ 0x00000000 /* DENALI_PHY_1116_DATA */
+ 0x00000000 /* DENALI_PHY_1117_DATA */
+ 0x00000000 /* DENALI_PHY_1118_DATA */
+ 0x00000000 /* DENALI_PHY_1119_DATA */
+ 0x00000000 /* DENALI_PHY_1120_DATA */
+ 0x00000000 /* DENALI_PHY_1121_DATA */
+ 0x00000000 /* DENALI_PHY_1122_DATA */
+ 0x00000000 /* DENALI_PHY_1123_DATA */
+ 0x00000000 /* DENALI_PHY_1124_DATA */
+ 0x00000000 /* DENALI_PHY_1125_DATA */
+ 0x00000000 /* DENALI_PHY_1126_DATA */
+ 0x00000000 /* DENALI_PHY_1127_DATA */
+ 0x00000000 /* DENALI_PHY_1128_DATA */
+ 0x00000000 /* DENALI_PHY_1129_DATA */
+ 0x00000000 /* DENALI_PHY_1130_DATA */
+ 0x00000000 /* DENALI_PHY_1131_DATA */
+ 0x00000000 /* DENALI_PHY_1132_DATA */
+ 0x00000000 /* DENALI_PHY_1133_DATA */
+ 0x00000000 /* DENALI_PHY_1134_DATA */
+ 0x00000000 /* DENALI_PHY_1135_DATA */
+ 0x00000000 /* DENALI_PHY_1136_DATA */
+ 0x00000000 /* DENALI_PHY_1137_DATA */
+ 0x00000000 /* DENALI_PHY_1138_DATA */
+ 0x00000000 /* DENALI_PHY_1139_DATA */
+ 0x00000000 /* DENALI_PHY_1140_DATA */
+ 0x00000000 /* DENALI_PHY_1141_DATA */
+ 0x00000000 /* DENALI_PHY_1142_DATA */
+ 0x00000000 /* DENALI_PHY_1143_DATA */
+ 0x00000000 /* DENALI_PHY_1144_DATA */
+ 0x00000000 /* DENALI_PHY_1145_DATA */
+ 0x00000000 /* DENALI_PHY_1146_DATA */
+ 0x00000000 /* DENALI_PHY_1147_DATA */
+ 0x00000000 /* DENALI_PHY_1148_DATA */
+ 0x00000000 /* DENALI_PHY_1149_DATA */
+ 0x00000000 /* DENALI_PHY_1150_DATA */
+ 0x00000000 /* DENALI_PHY_1151_DATA */
+ 0x00000000 /* DENALI_PHY_1152_DATA */
+ 0x00000000 /* DENALI_PHY_1153_DATA */
+ 0x00050000 /* DENALI_PHY_1154_DATA */
+ 0x00000000 /* DENALI_PHY_1155_DATA */
+ 0x00000000 /* DENALI_PHY_1156_DATA */
+ 0x00000000 /* DENALI_PHY_1157_DATA */
+ 0x00000100 /* DENALI_PHY_1158_DATA */
+ 0x00000000 /* DENALI_PHY_1159_DATA */
+ 0x00000000 /* DENALI_PHY_1160_DATA */
+ 0x00506401 /* DENALI_PHY_1161_DATA */
+ 0x01221102 /* DENALI_PHY_1162_DATA */
+ 0x00000122 /* DENALI_PHY_1163_DATA */
+ 0x00000000 /* DENALI_PHY_1164_DATA */
+ 0x000B1F00 /* DENALI_PHY_1165_DATA */
+ 0x0B1F0B1F /* DENALI_PHY_1166_DATA */
+ 0x0B1F0B1F /* DENALI_PHY_1167_DATA */
+ 0x0B1F0B1F /* DENALI_PHY_1168_DATA */
+ 0x0B1F0B1F /* DENALI_PHY_1169_DATA */
+ 0x00000B00 /* DENALI_PHY_1170_DATA */
+ 0x42080010 /* DENALI_PHY_1171_DATA */
+ 0x01000100 /* DENALI_PHY_1172_DATA */
+ 0x01000100 /* DENALI_PHY_1173_DATA */
+ 0x01000100 /* DENALI_PHY_1174_DATA */
+ 0x01000100 /* DENALI_PHY_1175_DATA */
+ 0x00000000 /* DENALI_PHY_1176_DATA */
+ 0x00000000 /* DENALI_PHY_1177_DATA */
+ 0x00000000 /* DENALI_PHY_1178_DATA */
+ 0x00000000 /* DENALI_PHY_1179_DATA */
+ 0x00000000 /* DENALI_PHY_1180_DATA */
+ 0x00000903 /* DENALI_PHY_1181_DATA */
+ 0x223FFF00 /* DENALI_PHY_1182_DATA */
+ 0x000008FF /* DENALI_PHY_1183_DATA */
+ 0x0000057F /* DENALI_PHY_1184_DATA */
+ 0x0000057F /* DENALI_PHY_1185_DATA */
+ 0x00037FFF /* DENALI_PHY_1186_DATA */
+ 0x00037FFF /* DENALI_PHY_1187_DATA */
+ 0x00004410 /* DENALI_PHY_1188_DATA */
+ 0x00004410 /* DENALI_PHY_1189_DATA */
+ 0x00004410 /* DENALI_PHY_1190_DATA */
+ 0x00004410 /* DENALI_PHY_1191_DATA */
+ 0x00004410 /* DENALI_PHY_1192_DATA */
+ 0x00000111 /* DENALI_PHY_1193_DATA */
+ 0x00000111 /* DENALI_PHY_1194_DATA */
+ 0x00000000 /* DENALI_PHY_1195_DATA */
+ 0x00000000 /* DENALI_PHY_1196_DATA */
+ 0x00000000 /* DENALI_PHY_1197_DATA */
+ 0x04000000 /* DENALI_PHY_1198_DATA */
+ 0x00000000 /* DENALI_PHY_1199_DATA */
+ 0x00000000 /* DENALI_PHY_1200_DATA */
+ 0x00000108 /* DENALI_PHY_1201_DATA */
+ 0x00000000 /* DENALI_PHY_1202_DATA */
+ 0x00000000 /* DENALI_PHY_1203_DATA */
+ 0x00000000 /* DENALI_PHY_1204_DATA */
+ 0x00000001 /* DENALI_PHY_1205_DATA */
+ 0x00000000 /* DENALI_PHY_1206_DATA */
+ 0x00000000 /* DENALI_PHY_1207_DATA */
+ 0x00000000 /* DENALI_PHY_1208_DATA */
+ 0x00000000 /* DENALI_PHY_1209_DATA */
+ 0x00000000 /* DENALI_PHY_1210_DATA */
+ 0x00000000 /* DENALI_PHY_1211_DATA */
+ 0x00020100 /* DENALI_PHY_1212_DATA */
+ 0x00000000 /* DENALI_PHY_1213_DATA */
+ 0x00000000 /* DENALI_PHY_1214_DATA */
+ >;
+};
diff --git a/arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi b/arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi
new file mode 100644
index 00000000000..70c9526f906
--- /dev/null
+++ b/arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 SiFive, Inc
+ */
+
+#include "hifive-unmatched-a00-u-boot.dtsi"
+#include "fu740-hifive-unmatched-a00-ddr-rev1.dtsi"
diff --git a/arch/riscv/dts/hifive-unmatched-a00-rev1.dts b/arch/riscv/dts/hifive-unmatched-a00-rev1.dts
new file mode 100644
index 00000000000..02edc4e60fd
--- /dev/null
+++ b/arch/riscv/dts/hifive-unmatched-a00-rev1.dts
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2021 SiFive, Inc */
+
+#include "hifive-unmatched-a00.dts"
diff --git a/arch/riscv/dts/openpiton-riscv64.dts b/arch/riscv/dts/openpiton-riscv64.dts
new file mode 100644
index 00000000000..abc6016a0b4
--- /dev/null
+++ b/arch/riscv/dts/openpiton-riscv64.dts
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2021 Tianrui Wei <tianrui-wei@outlook.com> */
+
+/*
+ * This dts is for a dual core instance of OpenPiton+Ariane built
+ * to run on a Digilent Genesys 2 FPGA at 66.67MHz. These files
+ * are automatically generated by the OpenPiton build system and
+ * this configuration may not be what you need if your configuration
+ * is different from the below.
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "openpiton,riscv64";
+
+ chosen {
+ stdout-path = "uart0:115200";
+ };
+
+ aliases {
+ console = &uart0;
+ serial0 = &uart0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <520835>;
+
+ CPU0: cpu@0 {
+ clocks = <&clk0>;
+ u-boot,dm-spl;
+ device_type = "cpu";
+ reg = <0>;
+ compatible = "openhwgroup,cva6", "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ tlb-split;
+ // HLIC - hart local interrupt controller
+ CPU0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+
+ CPU1: cpu@1 {
+ clocks = <&clk0>;
+ device_type = "cpu";
+ reg = <1>;
+ compatible = "openhwgroup,cva6", "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ tlb-split;
+ // HLIC - hart local interrupt controller
+ CPU1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+
+ };
+
+ clocks {
+ clk0: osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <66667000>;
+ };
+ };
+
+ memory@80000000 {
+ u-boot,dm-spl;
+ device_type = "memory";
+ reg = < 0x00000000 0x80000000 0x00000000 0x40000000 >;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "openpiton,chipset", "simple-bus";
+ ranges;
+
+ uart0: uart@fff0c2c000 {
+ compatible = "ns16550", "openpiton,ns16550";
+ reg = < 0x000000ff 0xf0c2c000 0x00000000 0x000d4000 >;
+ interrupt-parent = <&PLIC0>;
+ interrupts = <1>;
+ reg-shift = <0>;
+ // regs are spaced on 8 bit boundary
+ };
+
+ eth: ethernet@fff0d00000 {
+ compatible = "xlnx,xps-ethernetlite-1.00.a", "openpiton,ethernet";
+ device_type = "network";
+ reg = < 0x000000ff 0xf0d00000 0x00000000 0x00100000 >;
+ interrupt-parent = <&PLIC0>;
+ interrupts = <2>;
+ phy-handle = <&phy0>;
+ xlnx,duplex = <0x1>;
+ xlnx,include-global-buffers = <0x1>;
+ xlnx,include-internal-loopback = <0x0>;
+ xlnx,include-mdio = <0x1>;
+ xlnx,rx-ping-pong = <0x1>;
+ xlnx,s-axi-id-width = <0x1>;
+ xlnx,tx-ping-pong = <0x1>;
+ xlnx,use-internal = <0x0>;
+ axi_ethernetlite_0_mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: phy@1 {
+ compatible = "ethernet-phy-id001C.C915";
+ device_type = "ethernet-phy";
+ reg = <1>;
+ };
+ };
+ };
+
+ sdhci_0: sdhci@f000000000 {
+ u-boot,dm-spl;
+ compatible = "openpiton,piton-mmc", "openpiton,mmc";
+ reg = < 0x000000f0 0x00000000 0x00000000 0x00300000 >;
+ };
+
+ clint@fff1020000 {
+ compatible = "sifive,clint0", "openpiton,clint";
+ interrupts-extended = < &CPU0_intc 3
+ &CPU0_intc 7
+ &CPU1_intc 3
+ &CPU1_intc 7 >;
+ reg = < 0x000000ff 0xf1020000 0x00000000 0x000c0000 >;
+ clocks = <&clk0>;
+ };
+
+ PLIC0: plic@fff1100000 {
+ u-boot,dm-spl;
+ #interrupt-cells = <1>;
+ compatible = "sifive,plic-1.0.0", "openpiton,plic";
+ interrupt-controller;
+ interrupts-extended = < &CPU0_intc 11
+ &CPU0_intc 9
+ &CPU1_intc 11
+ &CPU1_intc 9 >;
+ reg = < 0x000000ff 0xf1100000 0x00000000 0x04000000 >;
+ riscv,max-priority = <7>;
+ riscv,ndev = <2>;
+ };
+ };
+};
diff --git a/arch/riscv/include/asm/arch-fu740/eeprom.h b/arch/riscv/include/asm/arch-fu740/eeprom.h
new file mode 100644
index 00000000000..0e1220e558e
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu740/eeprom.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 SiFive, Inc.
+ *
+ * Zong Li <zong.li@sifve.com>
+ */
+
+#ifndef _ASM_RISCV_EEPROM_H
+#define _ASM_RISCV_EEPROM_H
+
+#define PCB_REVISION_REV3 0x3
+
+u8 get_pcb_revision_from_eeprom(void);
+
+#endif /* _ASM_RISCV_EEPROM_H */
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 9c4edfcbfda..01dece5769c 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -178,10 +178,12 @@ int default_print_cpuinfo(void)
return 0;
}
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
void show_boot_progress(int val)
{
outb(val, POST_PORT);
}
+#endif
#if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
/*
diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c
index fbdc3b04e36..98cc05de2eb 100644
--- a/arch/x86/lib/bios.c
+++ b/arch/x86/lib/bios.c
@@ -23,7 +23,9 @@
static int (*int_handler[256])(void);
/* to have a common register file for interrupt handlers */
+#ifndef CONFIG_BIOSEMU
X86EMU_sysEnv _X86EMU_env;
+#endif
asmlinkage void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
u32 esi, u32 edi);
diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c
index 153ed0e963b..144a08922b1 100644
--- a/board/BuS/eb_cpu5282/eb_cpu5282.c
+++ b/board/BuS/eb_cpu5282/eb_cpu5282.c
@@ -22,8 +22,8 @@
DECLARE_GLOBAL_DATA_PTR;
#if IS_ENABLED(CONFIG_VIDEO_VCXK)
-unsigned long display_width;
-unsigned long display_height;
+extern unsigned long display_width;
+extern unsigned long display_height;
#endif
/*---------------------------------------------------------------------------*/
diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c
index 380e37be550..fb691931580 100644
--- a/board/Seagate/dockstar/dockstar.c
+++ b/board/Seagate/dockstar/dockstar.c
@@ -140,6 +140,7 @@ void reset_phy(void)
}
#endif /* CONFIG_RESET_PHY_R */
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
#define GREEN_LED (1 << 14)
#define ORANGE_LED (1 << 15)
#define BOTH_LEDS (GREEN_LED | ORANGE_LED)
@@ -169,3 +170,4 @@ void show_boot_progress(int val)
break;
}
}
+#endif
diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c
index 4c19fa7195e..af8cab7bdc7 100644
--- a/board/Seagate/goflexhome/goflexhome.c
+++ b/board/Seagate/goflexhome/goflexhome.c
@@ -142,6 +142,7 @@ void reset_phy(void)
}
#endif /* CONFIG_RESET_PHY_R */
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
#define GREEN_LED (1 << 14)
#define ORANGE_LED (1 << 15)
#define BOTH_LEDS (GREEN_LED | ORANGE_LED)
@@ -175,3 +176,4 @@ void show_boot_progress(int val)
break;
}
}
+#endif
diff --git a/board/armltd/integrator/Makefile b/board/armltd/integrator/Makefile
index 8c906e3f072..107e59bf0fa 100644
--- a/board/armltd/integrator/Makefile
+++ b/board/armltd/integrator/Makefile
@@ -10,5 +10,4 @@
obj-y := lowlevel_init.o
obj-y += integrator.o
-obj-$(CONFIG_PCI) += pci.o
obj-y += timer.o
diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
index 3e864e8e7a5..388795809df 100644
--- a/board/armltd/integrator/integrator.c
+++ b/board/armltd/integrator/integrator.c
@@ -181,7 +181,6 @@ int board_eth_init(struct bd_info *bis)
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
- rc += pci_eth_init(bis);
return rc;
}
#endif
diff --git a/board/armltd/integrator/pci.c b/board/armltd/integrator/pci.c
deleted file mode 100644
index 28efc33f1f4..00000000000
--- a/board/armltd/integrator/pci.c
+++ /dev/null
@@ -1,462 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * (C) Copyright 2004
- * ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * (C) Copyright 2011
- * Linaro
- * Linus Walleij <linus.walleij@linaro.org>
- */
-#include <common.h>
-#include <init.h>
-#include <log.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <linux/bug.h>
-#include <linux/delay.h>
-#include "integrator-sc.h"
-#include "pci_v3.h"
-
-#define INTEGRATOR_BOOT_ROM_BASE 0x20000000
-#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
-
-/*
- * These are in the physical addresses on the CPU side, i.e.
- * where we read and write stuff - you don't want to try to
- * move these around
- */
-#define PHYS_PCI_MEM_BASE 0x40000000
-#define PHYS_PCI_IO_BASE 0x60000000 /* PCI I/O space base */
-#define PHYS_PCI_CONFIG_BASE 0x61000000
-#define PHYS_PCI_V3_BASE 0x62000000 /* V360EPC registers */
-#define SZ_256M 0x10000000
-
-/*
- * These are in the PCI BUS address space
- * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor
- * we follow the example of the kernel, because that is the address
- * range that devices actually use - what would they be doing at
- * 0x40000000?
- */
-#define PCI_BUS_NONMEM_START 0x00000000
-#define PCI_BUS_NONMEM_SIZE SZ_256M
-
-#define PCI_BUS_PREMEM_START (PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE)
-#define PCI_BUS_PREMEM_SIZE SZ_256M
-
-#if PCI_BUS_NONMEM_START & 0x000fffff
-#error PCI_BUS_NONMEM_START must be megabyte aligned
-#endif
-#if PCI_BUS_PREMEM_START & 0x000fffff
-#error PCI_BUS_PREMEM_START must be megabyte aligned
-#endif
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-#define PCI_ENET0_IOADDR 0x60000000 /* First card in PCI I/O space */
-#define PCI_ENET0_MEMADDR 0x40000000 /* First card in PCI memory space */
-static struct pci_config_table pci_integrator_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
- { }
-};
-#endif /* CONFIG_PCI_PNP */
-
-/* V3 access routines */
-#define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
-#define v3_readb(o) (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o)))
-
-#define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
-#define v3_readw(o) (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o)))
-
-#define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
-#define v3_readl(o) (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o)))
-
-static unsigned long v3_open_config_window(pci_dev_t bdf, int offset)
-{
- unsigned int address, mapaddress;
- unsigned int busnr = PCI_BUS(bdf);
- unsigned int devfn = PCI_FUNC(bdf);
-
- /*
- * Trap out illegal values
- */
- if (offset > 255)
- BUG();
- if (busnr > 255)
- BUG();
- if (devfn > 255)
- BUG();
-
- if (busnr == 0) {
- /*
- * Linux calls the thing U-Boot calls "DEV" "SLOT"
- * instead, but it's the same 5 bits
- */
- int slot = PCI_DEV(bdf);
-
- /*
- * local bus segment so need a type 0 config cycle
- *
- * build the PCI configuration "address" with one-hot in
- * A31-A11
- *
- * mapaddress:
- * 3:1 = config cycle (101)
- * 0 = PCI A1 & A0 are 0 (0)
- */
- address = PCI_FUNC(bdf) << 8;
- mapaddress = V3_LB_MAP_TYPE_CONFIG;
-
- if (slot > 12)
- /*
- * high order bits are handled by the MAP register
- */
- mapaddress |= 1 << (slot - 5);
- else
- /*
- * low order bits handled directly in the address
- */
- address |= 1 << (slot + 11);
- } else {
- /*
- * not the local bus segment so need a type 1 config cycle
- *
- * address:
- * 23:16 = bus number
- * 15:11 = slot number (7:3 of devfn)
- * 10:8 = func number (2:0 of devfn)
- *
- * mapaddress:
- * 3:1 = config cycle (101)
- * 0 = PCI A1 & A0 from host bus (1)
- */
- mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
- address = (busnr << 16) | (devfn << 8);
- }
-
- /*
- * Set up base0 to see all 512Mbytes of memory space (not
- * prefetchable), this frees up base1 for re-use by
- * configuration memory
- */
- v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
- V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
-
- /*
- * Set up base1/map1 to point into configuration space.
- */
- v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
- V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
- v3_writew(V3_LB_MAP1, mapaddress);
-
- return PHYS_PCI_CONFIG_BASE + address + offset;
-}
-
-static void v3_close_config_window(void)
-{
- /*
- * Reassign base1 for use by prefetchable PCI memory
- */
- v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
- V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
- V3_LB_BASE_ENABLE);
- v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
- V3_LB_MAP_TYPE_MEM_MULTIPLE);
-
- /*
- * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
- */
- v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
- V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
-}
-
-static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf,
- int offset, unsigned char *val)
-{
- unsigned long addr;
-
- addr = v3_open_config_window(bdf, offset);
- *val = __raw_readb(addr);
- v3_close_config_window();
- return 0;
-}
-
-static int pci_integrator_read__word(struct pci_controller *hose,
- pci_dev_t bdf, int offset,
- unsigned short *val)
-{
- unsigned long addr;
-
- addr = v3_open_config_window(bdf, offset);
- *val = __raw_readw(addr);
- v3_close_config_window();
- return 0;
-}
-
-static int pci_integrator_read_dword(struct pci_controller *hose,
- pci_dev_t bdf, int offset,
- unsigned int *val)
-{
- unsigned long addr;
-
- addr = v3_open_config_window(bdf, offset);
- *val = __raw_readl(addr);
- v3_close_config_window();
- return 0;
-}
-
-static int pci_integrator_write_byte(struct pci_controller *hose,
- pci_dev_t bdf, int offset,
- unsigned char val)
-{
- unsigned long addr;
-
- addr = v3_open_config_window(bdf, offset);
- __raw_writeb((u8)val, addr);
- __raw_readb(addr);
- v3_close_config_window();
- return 0;
-}
-
-static int pci_integrator_write_word(struct pci_controller *hose,
- pci_dev_t bdf, int offset,
- unsigned short val)
-{
- unsigned long addr;
-
- addr = v3_open_config_window(bdf, offset);
- __raw_writew((u8)val, addr);
- __raw_readw(addr);
- v3_close_config_window();
- return 0;
-}
-
-static int pci_integrator_write_dword(struct pci_controller *hose,
- pci_dev_t bdf, int offset,
- unsigned int val)
-{
- unsigned long addr;
-
- addr = v3_open_config_window(bdf, offset);
- __raw_writel((u8)val, addr);
- __raw_readl(addr);
- v3_close_config_window();
- return 0;
-}
-
-struct pci_controller integrator_hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_integrator_config_table,
-#endif
-};
-
-void pci_init_board(void)
-{
- struct pci_controller *hose = &integrator_hose;
- u16 val;
-
- /* setting this register will take the V3 out of reset */
- __raw_writel(SC_PCI_PCIEN, SC_PCI);
-
- /* Wait for 230 ms (from spec) before accessing any V3 registers */
- mdelay(230);
-
- /* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */
- v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16));
-
- /* Wait for the mailbox to settle */
- do {
- v3_writeb(V3_MAIL_DATA, 0xAA);
- v3_writeb(V3_MAIL_DATA + 4, 0x55);
- } while (v3_readb(V3_MAIL_DATA) != 0xAA ||
- v3_readb(V3_MAIL_DATA + 4) != 0x55);
-
- /* Make sure that V3 register access is not locked, if it is, unlock it */
- if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
- v3_writew(V3_SYSTEM, 0xA05F);
-
- /*
- * Ensure that the slave accesses from PCI are disabled while we
- * setup memory windows
- */
- val = v3_readw(V3_PCI_CMD);
- val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
- v3_writew(V3_PCI_CMD, val);
-
- /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
- val = v3_readw(V3_SYSTEM);
- val &= ~V3_SYSTEM_M_RST_OUT;
- v3_writew(V3_SYSTEM, val);
-
- /* Make all accesses from PCI space retry until we're ready for them */
- val = v3_readw(V3_PCI_CFG);
- val |= V3_PCI_CFG_M_RETRY_EN;
- v3_writew(V3_PCI_CFG, val);
-
- /*
- * Set up any V3 PCI Configuration Registers that we absolutely have to.
- * LB_CFG controls Local Bus protocol.
- * Enable LocalBus byte strobes for READ accesses too.
- * set bit 7 BE_IMODE and bit 6 BE_OMODE
- */
- val = v3_readw(V3_LB_CFG);
- val |= 0x0C0;
- v3_writew(V3_LB_CFG, val);
-
- /* PCI_CMD controls overall PCI operation. Enable PCI bus master. */
- val = v3_readw(V3_PCI_CMD);
- val |= V3_COMMAND_M_MASTER_EN;
- v3_writew(V3_PCI_CMD, val);
-
- /*
- * PCI_MAP0 controls where the PCI to CPU memory window is on
- * Local Bus
- */
- v3_writel(V3_PCI_MAP0,
- (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB |
- V3_PCI_MAP_M_REG_EN |
- V3_PCI_MAP_M_ENABLE));
-
- /* PCI_BASE0 is the PCI address of the start of the window */
- v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE);
-
- /* PCI_MAP1 is LOCAL address of the start of the window */
- v3_writel(V3_PCI_MAP1,
- (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB |
- V3_PCI_MAP_M_REG_EN |
- V3_PCI_MAP_M_ENABLE));
-
- /* PCI_BASE1 is the PCI address of the start of the window */
- v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE);
-
- /*
- * Set up memory the windows from local bus memory into PCI
- * configuration, I/O and Memory regions.
- * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this.
- */
- v3_writew(V3_LB_BASE2,
- v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE);
- v3_writew(V3_LB_MAP2, 0);
-
- /* PCI Configuration, use LB_BASE1/LB_MAP1. */
-
- /*
- * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1
- * Map first 256Mbytes as non-prefetchable via BASE0/MAP0
- */
- v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
- V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
- v3_writew(V3_LB_MAP0,
- v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM);
-
- /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
- v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
- V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
- V3_LB_BASE_ENABLE);
- v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
- V3_LB_MAP_TYPE_MEM_MULTIPLE);
-
- /* Dump PCI to local address space mappings */
- debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0));
- debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0));
- debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1));
- debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1));
- debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2));
- debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2));
- debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE));
-
- /*
- * Allow accesses to PCI Configuration space and set up A1, A0 for
- * type 1 config cycles
- */
- val = v3_readw(V3_PCI_CFG);
- val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1);
- val |= V3_PCI_CFG_M_AD_LOW0;
- v3_writew(V3_PCI_CFG, val);
-
- /* now we can allow incoming PCI MEMORY accesses */
- val = v3_readw(V3_PCI_CMD);
- val |= V3_COMMAND_M_MEM_EN;
- v3_writew(V3_PCI_CMD, val);
-
- /*
- * Set RST_OUT to take the PCI bus is out of reset, PCI devices can
- * now initialise.
- */
- val = v3_readw(V3_SYSTEM);
- val |= V3_SYSTEM_M_RST_OUT;
- v3_writew(V3_SYSTEM, val);
-
- /* Lock the V3 system register so that no one else can play with it */
- val = v3_readw(V3_SYSTEM);
- val |= V3_SYSTEM_M_LOCK;
- v3_writew(V3_SYSTEM, val);
-
- /*
- * Configure and register the PCI hose
- */
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* System memory space, window 0 256 MB non-prefetchable */
- pci_set_region(hose->regions + 0,
- PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE,
- SZ_256M,
- PCI_REGION_MEM);
-
- /* System memory space, window 1 256 MB prefetchable */
- pci_set_region(hose->regions + 1,
- PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M,
- SZ_256M,
- PCI_REGION_MEM |
- PCI_REGION_PREFETCH);
-
- /* PCI I/O space */
- pci_set_region(hose->regions + 2,
- 0x00000000, PHYS_PCI_IO_BASE, 0x01000000,
- PCI_REGION_IO);
-
- /* PCI Memory - config space */
- pci_set_region(hose->regions + 3,
- 0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000,
- PCI_REGION_MEM);
- /* PCI V3 regs */
- pci_set_region(hose->regions + 4,
- 0x00000000, PHYS_PCI_V3_BASE, 0x01000000,
- PCI_REGION_MEM);
-
- hose->region_count = 5;
-
- pci_set_ops(hose,
- pci_integrator_read_byte,
- pci_integrator_read__word,
- pci_integrator_read_dword,
- pci_integrator_write_byte,
- pci_integrator_write_word,
- pci_integrator_write_dword);
-
- pci_register_hose(hose);
-
- pciauto_config_init(hose);
- pciauto_config_device(hose, 0);
-
- hose->last_busno = pci_hose_scan(hose);
-}
diff --git a/board/armltd/integrator/pci_v3.h b/board/armltd/integrator/pci_v3.h
deleted file mode 100644
index 8d09e6966db..00000000000
--- a/board/armltd/integrator/pci_v3.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * arch/arm/include/asm/hardware/pci_v3.h
- *
- * Internal header file PCI V3 chip
- *
- * Copyright (C) ARM Limited
- * Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
- */
-#ifndef ASM_ARM_HARDWARE_PCI_V3_H
-#define ASM_ARM_HARDWARE_PCI_V3_H
-
-/* -------------------------------------------------------------------------------
- * V3 Local Bus to PCI Bridge definitions
- * -------------------------------------------------------------------------------
- * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
- * All V3 register names are prefaced by V3_ to avoid clashing with any other
- * PCI definitions. Their names match the user's manual.
- *
- * I'm assuming that I20 is disabled.
- *
- */
-#define V3_PCI_VENDOR 0x00000000
-#define V3_PCI_DEVICE 0x00000002
-#define V3_PCI_CMD 0x00000004
-#define V3_PCI_STAT 0x00000006
-#define V3_PCI_CC_REV 0x00000008
-#define V3_PCI_HDR_CFG 0x0000000C
-#define V3_PCI_IO_BASE 0x00000010
-#define V3_PCI_BASE0 0x00000014
-#define V3_PCI_BASE1 0x00000018
-#define V3_PCI_SUB_VENDOR 0x0000002C
-#define V3_PCI_SUB_ID 0x0000002E
-#define V3_PCI_ROM 0x00000030
-#define V3_PCI_BPARAM 0x0000003C
-#define V3_PCI_MAP0 0x00000040
-#define V3_PCI_MAP1 0x00000044
-#define V3_PCI_INT_STAT 0x00000048
-#define V3_PCI_INT_CFG 0x0000004C
-#define V3_LB_BASE0 0x00000054
-#define V3_LB_BASE1 0x00000058
-#define V3_LB_MAP0 0x0000005E
-#define V3_LB_MAP1 0x00000062
-#define V3_LB_BASE2 0x00000064
-#define V3_LB_MAP2 0x00000066
-#define V3_LB_SIZE 0x00000068
-#define V3_LB_IO_BASE 0x0000006E
-#define V3_FIFO_CFG 0x00000070
-#define V3_FIFO_PRIORITY 0x00000072
-#define V3_FIFO_STAT 0x00000074
-#define V3_LB_ISTAT 0x00000076
-#define V3_LB_IMASK 0x00000077
-#define V3_SYSTEM 0x00000078
-#define V3_LB_CFG 0x0000007A
-#define V3_PCI_CFG 0x0000007C
-#define V3_DMA_PCI_ADR0 0x00000080
-#define V3_DMA_PCI_ADR1 0x00000090
-#define V3_DMA_LOCAL_ADR0 0x00000084
-#define V3_DMA_LOCAL_ADR1 0x00000094
-#define V3_DMA_LENGTH0 0x00000088
-#define V3_DMA_LENGTH1 0x00000098
-#define V3_DMA_CSR0 0x0000008B
-#define V3_DMA_CSR1 0x0000009B
-#define V3_DMA_CTLB_ADR0 0x0000008C
-#define V3_DMA_CTLB_ADR1 0x0000009C
-#define V3_DMA_DELAY 0x000000E0
-#define V3_MAIL_DATA 0x000000C0
-#define V3_PCI_MAIL_IEWR 0x000000D0
-#define V3_PCI_MAIL_IERD 0x000000D2
-#define V3_LB_MAIL_IEWR 0x000000D4
-#define V3_LB_MAIL_IERD 0x000000D6
-#define V3_MAIL_WR_STAT 0x000000D8
-#define V3_MAIL_RD_STAT 0x000000DA
-#define V3_QBA_MAP 0x000000DC
-
-/* PCI COMMAND REGISTER bits
- */
-#define V3_COMMAND_M_FBB_EN (1 << 9)
-#define V3_COMMAND_M_SERR_EN (1 << 8)
-#define V3_COMMAND_M_PAR_EN (1 << 6)
-#define V3_COMMAND_M_MASTER_EN (1 << 2)
-#define V3_COMMAND_M_MEM_EN (1 << 1)
-#define V3_COMMAND_M_IO_EN (1 << 0)
-
-/* SYSTEM REGISTER bits
- */
-#define V3_SYSTEM_M_RST_OUT (1 << 15)
-#define V3_SYSTEM_M_LOCK (1 << 14)
-
-/* PCI_CFG bits
- */
-#define V3_PCI_CFG_M_I2O_EN (1 << 15)
-#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
-#define V3_PCI_CFG_M_IO_DIS (1 << 13)
-#define V3_PCI_CFG_M_EN3V (1 << 12)
-#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
-#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
-#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
-
-/* PCI_BASE register bits (PCI -> Local Bus)
- */
-#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
-#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
-#define V3_PCI_BASE_M_PREFETCH (1 << 3)
-#define V3_PCI_BASE_M_TYPE (3 << 1)
-#define V3_PCI_BASE_M_IO (1 << 0)
-
-/* PCI MAP register bits (PCI -> Local bus)
- */
-#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
-#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
-#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
-#define V3_PCI_MAP_M_SWAP (3 << 8)
-#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
-#define V3_PCI_MAP_M_REG_EN (1 << 1)
-#define V3_PCI_MAP_M_ENABLE (1 << 0)
-
-#define V3_PCI_MAP_M_ADR_SIZE_1MB (0 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_2MB (1 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_4MB (2 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_8MB (3 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_16MB (4 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_32MB (5 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_64MB (6 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_128MB (7 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_256MB (8 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_512MB (9 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_1GB (10 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_2GB (11 << 4)
-
-/*
- * LB_BASE0,1 register bits (Local bus -> PCI)
- */
-#define V3_LB_BASE_ADR_BASE 0xfff00000
-#define V3_LB_BASE_SWAP (3 << 8)
-#define V3_LB_BASE_ADR_SIZE (15 << 4)
-#define V3_LB_BASE_PREFETCH (1 << 3)
-#define V3_LB_BASE_ENABLE (1 << 0)
-
-#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
-#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
-#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
-#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
-#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
-#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
-#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
-#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
-#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
-#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
-#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
-#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
-
-#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
-
-/*
- * LB_MAP0,1 register bits (Local bus -> PCI)
- */
-#define V3_LB_MAP_MAP_ADR 0xfff0
-#define V3_LB_MAP_TYPE (7 << 1)
-#define V3_LB_MAP_AD_LOW_EN (1 << 0)
-
-#define V3_LB_MAP_TYPE_IACK (0 << 1)
-#define V3_LB_MAP_TYPE_IO (1 << 1)
-#define V3_LB_MAP_TYPE_MEM (3 << 1)
-#define V3_LB_MAP_TYPE_CONFIG (5 << 1)
-#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
-
-/* PCI MAP register bits (PCI -> Local bus) */
-#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
-
-/*
- * LB_BASE2 register bits (Local bus -> PCI IO)
- */
-#define V3_LB_BASE2_ADR_BASE 0xff00
-#define V3_LB_BASE2_SWAP (3 << 6)
-#define V3_LB_BASE2_ENABLE (1 << 0)
-
-#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
-
-/*
- * LB_MAP2 register bits (Local bus -> PCI IO)
- */
-#define V3_LB_MAP2_MAP_ADR 0xff00
-
-#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
-
-#endif
diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c
index 86356e38751..13fd25e4071 100644
--- a/board/bosch/shc/board.c
+++ b/board/bosch/shc/board.c
@@ -188,7 +188,7 @@ static void __maybe_unused leds_set_booting(void)
/*
* Function to set the LEDs in the state "Bootloader error"
*/
-static void leds_set_failure(int state)
+static void __maybe_unused leds_set_failure(int state)
{
#if defined(CONFIG_B_SAMPLE)
/* Turn all blue and green LEDs off */
@@ -479,7 +479,7 @@ int board_eth_init(struct bd_info *bis)
}
#endif
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
static void bosch_check_reset_pin(void)
{
if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
@@ -525,9 +525,9 @@ void show_boot_progress(int val)
break;
}
}
+#endif
void arch_preboot_os(void)
{
leds_set_finish();
}
-#endif
diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c
index 34be601fdde..738b6bc25ce 100644
--- a/board/buffalo/lsxl/lsxl.c
+++ b/board/buffalo/lsxl/lsxl.c
@@ -271,7 +271,7 @@ int misc_init_r(void)
}
#endif
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
void show_boot_progress(int progress)
{
if (progress > 0)
diff --git a/board/ea/ea-lpc3250devkitv2/Kconfig b/board/ea/ea-lpc3250devkitv2/Kconfig
new file mode 100644
index 00000000000..368ce027e62
--- /dev/null
+++ b/board/ea/ea-lpc3250devkitv2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EA_LPC3250DEVKITV2
+
+config SYS_BOARD
+ default "ea-lpc3250devkitv2"
+
+config SYS_VENDOR
+ default "ea"
+
+config SYS_SOC
+ default "lpc32xx"
+
+config SYS_CONFIG_NAME
+ default "ea-lpc3250devkitv2"
+
+endif
diff --git a/board/ea/ea-lpc3250devkitv2/MAINTAINERS b/board/ea/ea-lpc3250devkitv2/MAINTAINERS
new file mode 100644
index 00000000000..b4b9362f5b2
--- /dev/null
+++ b/board/ea/ea-lpc3250devkitv2/MAINTAINERS
@@ -0,0 +1,9 @@
+EMBEDDED ARTISTS LPC3250 DEVKIT v2
+M: Trevor Woerner <twoerner@gmail.com>
+S: Maintained
+F: board/ea/ea-lpc3250devkitv2
+F: include/configs/ea-lpc3250devkitv2.h
+F: configs/ea-lpc3250devkitv2_defconfig
+F: arch/arm/dts/lpc32xx.dtsi
+F: arch/arm/dts/lpc3250-ea3250.dts
+F: arch/arm/dts/lpc3250-ea3250-u-boot.dtsi
diff --git a/board/ea/ea-lpc3250devkitv2/Makefile b/board/ea/ea-lpc3250devkitv2/Makefile
new file mode 100644
index 00000000000..a4a40b6d4fb
--- /dev/null
+++ b/board/ea/ea-lpc3250devkitv2/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2021 Trevor Woerner <twoerner@gmail.com>
+
+obj-y += ea-lpc3250devkitv2.o
diff --git a/board/ea/ea-lpc3250devkitv2/README.rst b/board/ea/ea-lpc3250devkitv2/README.rst
new file mode 100644
index 00000000000..1b780003317
--- /dev/null
+++ b/board/ea/ea-lpc3250devkitv2/README.rst
@@ -0,0 +1,186 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+ToC:
+- Introduction
+- Booting
+- Debugging
+- i2c
+
+
+Introduction
+============
+The Embedded Artists LPC3250 Developer's Kit v2 features the LPC3250 SoC
+which is based on the ARM926EJ-S CPU. The kit features a base board and
+a removable OEM board which features the SoC. Details, schematics, and
+documentation are available from the Embedded Artists product website:
+
+ https://www.embeddedartists.com/products/lpc3250-developers-kit-v2/
+
+The base board includes::
+- 200 pos, 0.6mm pitch SODIMM connector for OEM Board
+- LCD expansion connector with control signals for touch screen interface
+- Expansion connector with all OEM Board signals
+- Ethernet connector (RJ45)
+- CAN interface & connector (provision for second CAN interface, but not mounted)
+- MMC/SD interface & connector
+- USB1: OTG or Host interface & connector
+- USB2: Device or Host interface & connector
+- Provision for NXP JN5148 RF module (former Jennic) interface (RF module not included)
+- Full modem RS232 (cannot be fully used on 32-bit databus OEM boards)
+- RS422/485 interface & connector
+- Provision for IrDA transceiver interface (transceiver not mounted)
+- I2S audio codec (mic in, line in, line out, headphone out)
+- SWD/JTAG connector
+- Trace connector and pads for ETM connector
+- Serial Expansion Connector, 14-pos connector with UART/I2C/SPI/GPIO pins
+- Power supply, either via USB or external 5V DC
+- Optional coin cell battery for RTC and LED on ALARM output (coin cell not included)
+- OEM Board current measuring
+- Parallel NOR flash on external memory bus
+- 16-bit register and LEDs on external memory bus
+- 5-key joystick
+- LM75 temperature sensor (I2C connected)
+- 5 push-button keys (four via I2C and one on ISP-ENABLE)
+- 9 LEDs (8 via I2C and one on ISP-ENABLE)
+- Trimming potentiometer to analog input
+- USB-to-serial bridge on UART #0 (FT232R) and ISP functionality
+- Reset push-button and LED
+- Speaker output on analog output from OEM Board, or from I2S audio codec
+- 160x150 mm in size
+
+The OEM board::
+- ARMv5 ARM926EJ-S @ 266 MHz with hard-float VFPv2
+- 256 KByte IRAM, 64 MByte SDRAM
+- 128 MByte NAND flash
+- 4 MByte NOR Flash
+- Graphics Output: Parallel RGB
+- Hardware 2D/3D Graphic: No
+- Hardware Video: SW only
+- Graphics input: No
+- Audio: I2S
+- Ethernet: 10/100 Mbps
+- USB: 1x FS USB 2.0 OTG
+- Wi-Fi: No
+- FlexIO: No
+- Serial: 2x I2C, 2x SPI, 7x UART
+- ADC/PWM: 3 ch (10-bit) / 2 ch
+- SD: MCI
+- PCIe: No
+- Serial ATA: No
+- Size: 68 x 48 mm
+- Connector: 200 pos SODIMM
+
+
+Booting
+=======
+The processor will start its code execution from an internal ROM,
+containing the boot code. This boot loader can load code from one of four
+external sources to internal RAM (IRAM) at address 0x0::
+- UART5
+- SSP0 (in SPI mode)
+- EMC Static CS0 memory
+- NAND FLASH
+
+The ROM boot loader loads code as a single contiguous block at a maximum
+size of 56 kByte. Programs larger than this size must be loaded in more
+steps, for example, by a secondary boot loader.
+
+Kickstart Loader
+----------------
+By default the Embedded Artists LPC3250 OEM Board is programmed with the
+kickstart loader in block 0 of the NAND flash. The responsibility of this
+loader is to load an application stored in block 1 and onwards of the NAND
+flash. The kickstart loader will load the application into internal RAM
+(IRAM) at address 0x0.
+
+Stage 1 Loader (s1l)
+--------------------
+By default the Embedded Artists LPC3250 OEM Board is programmed with the
+stage 1 loader (s1l) in block 1 of the NAND flash. This application will be
+loaded by the kickstart loader when the LPC3250 OEM Board powers up. The
+S1L loader will initialize the board, such as clocks and external memory
+and then start a console where you can give input commands to the loader.
+S1L offers the following booting options::
+- MMC/SD card
+- UART5
+- NAND Flash
+
+U-Boot with kickstart+s1l
+-------------------------
+Out of the box, the easiest way to get U-Boot running on the EA LPC3250
+DevKit v2 board is to build the ea-lpc3250devkitv2_defconfig, copy the
+resulting u-boot.bin to a vfat-formatted MMC/SD card, insert the MMC/SD card
+into the MMC/SD card slot on the board, reset the board (SW1), and::
+
+ Embedded Artist 3250 Board (S1L 2.0)
+ Build date: Oct 31 2016 13:00:37
+
+ EA3250>load blk u-boot.bin raw 0x83000000
+ File loaded successfully
+
+ EA3250>exec 0x83000000
+
+
+Debugging
+=========
+JTAG debugging of the Embedded Artists LPC3250 Developer's Kit v2 board is
+easy thanks to the included/populated 20-pin JTAG port on the main board (J8).
+openocd 0.11 has been used with this board along with the ARM-USB-OCD-H JTAG
+dongle from Olimex successfully as follows:
+
+ # openocd \
+ -f interface/ftdi/olimex-arm-usb-ocd-h.cfg \
+ -f board/phytec_lpc3250.cfg
+
+
+i2c
+===
+Some of the LEDs on the board are connected via an I/O Expander (PCA9532) that
+is attached to the i2c1 bus. Here is a sample session of toggling some of
+these LEDs via i2c in U-Boot:
+
+show the existing i2c busses:
+ EA-LPC3250v2=> i2c bus
+ Bus 0: i2c@300
+ Bus 1: i2c@400a0000
+ Bus 2: i2c@400a8000
+
+set i2c1 as the current bus:
+ EA-LPC3250v2=> i2c dev 1
+ Setting bus to 1
+
+see what potential devices are found with rudimentary probing on i2c1:
+ EA-LPC3250v2=> i2c probe
+ Valid chip addresses: 1A 1D 48 50 57 60 66 6E
+
+According to the schematics the i2c slave address of the PCA9532 is 0x60.
+
+dump all of the 10 registers from the I/O Expander; NOTE that the 0x10 in the
+command specifies the self-incrementing mode of the PCA9532; also NOTE that
+the values repeat themseves to fill out a full 16 bytes:
+ EA-LPC3250v2=> i2c md 0x60 0x10 10
+ 0010: 00 ff 00 80 00 80 00 00 00 00 4f ff 00 80 00 80 ..........O.....
+
+turn on LEDs 23, 25, 27, and 29 (green):
+ EA-LPC3250v2=> i2c mw 0x60 9 0x55
+
+turn on LEDs 22, 24, 26, and 28 (red):
+ EA-LPC3250v2=> i2c mw 0x60 8 0x55
+
+dim the green LEDs (23, 25, 27, 29):
+ EA-LPC3250v2=> i2c mw 0x60 3 0x20
+ EA-LPC3250v2=> i2c mw 0x60 9 0xaa
+
+turn off all LEDs (23-29):
+ EA-LPC3250v2=> i2c mw 0x60 8 0
+ EA-LPC3250v2=> i2c mw 0x60 9 0
+
+read value of switches (input):
+ EA-LPC3250v2=> i2c md 0x60 0 1
+ 0000: 4f O
+[none are pressed]
+
+press and hold SW2 while running the following:
+ EA-LPC3250v2=> i2c md 0x60 0 1
+ 0000: 4e N
+[SW2 is pressed]
diff --git a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c
new file mode 100644
index 00000000000..72cf46c749f
--- /dev/null
+++ b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board init file for Embedded Artists LPC3250 DevKit v2
+ * Copyright (C) 2021 Trevor Woerner <twoerner@gmail.com>
+ */
+
+#include <init.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/global_data.h>
+
+#include <asm/arch/clk.h>
+#include <asm/arch/wdt.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int
+board_early_init_f(void)
+{
+ lpc32xx_uart_init(CONFIG_CONS_INDEX);
+ if (IS_ENABLED(CONFIG_SYS_I2C_LPC32XX)) {
+ lpc32xx_i2c_init(1);
+ lpc32xx_i2c_init(2);
+ }
+ return 0;
+}
+
+int
+board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x2000;
+ return 0;
+}
+
+int
+dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_64M);
+ return 0;
+}
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 624e92ef9c2..66b3d9a4651 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -176,7 +176,7 @@ int board_early_init_f(void)
}
#ifdef CONFIG_FSL_ESDHC
-#if !(CONFIG_IS_ENABLED(DM_MMC))
+#if !(CONFIG_IS_ENABLED(DM_MMC) || CONFIG_IS_ENABLED(DM_USB))
int board_mmc_init(struct bd_info *bd)
{
struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
@@ -217,6 +217,15 @@ int misc_init_r(void)
return rc;
}
+int board_late_init(void)
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+#ifdef CONFIG_USB
+ clrsetbits_be32(&immap->sysconf.sicrl, SICRL_USB_A, 0x40000000);
+#endif
+ return 0;
+}
+
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
diff --git a/board/freescale/t102xrdb/cpld.h b/board/freescale/t102xrdb/cpld.h
index c05f536806f..bd40cc319a8 100644
--- a/board/freescale/t102xrdb/cpld.h
+++ b/board/freescale/t102xrdb/cpld.h
@@ -21,7 +21,7 @@ struct cpld_data {
u8 boot_override; /* 0x18 - Boot override register */
u8 boot_config1; /* 0x19 - Boot config override register*/
u8 boot_config2; /* 0x1A - Boot config override register*/
-} cpld_data_t;
+};
/* Pointer to the CPLD register set */
diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h
index a816aef10a4..769883f9461 100644
--- a/board/freescale/t104xrdb/cpld.h
+++ b/board/freescale/t104xrdb/cpld.h
@@ -30,8 +30,7 @@ struct cpld_data {
u8 boot_override; /* 0x18 - Boot override register */
u8 boot_config1; /* 0x19 - Boot config override register*/
u8 boot_config2; /* 0x1A - Boot config override register*/
-} cpld_data_t;
-
+};
/* Pointer to the CPLD register set */
diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h
index bd6c203742e..a623b1811fa 100644
--- a/board/freescale/t208xrdb/cpld.h
+++ b/board/freescale/t208xrdb/cpld.h
@@ -21,7 +21,7 @@ struct cpld_data {
u8 boot_or; /* 0x16 - Boot config override register */
u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */
u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */
-} cpld_data_t;
+};
u8 cpld_read(unsigned int reg);
void cpld_write(unsigned int reg, u8 value);
diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c
index cc8118b4ad4..7c3a695cb25 100644
--- a/board/k+p/kp_imx53/kp_imx53.c
+++ b/board/k+p/kp_imx53/kp_imx53.c
@@ -155,6 +155,7 @@ int board_late_init(void)
return ret;
}
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
#define GPIO_DR 0x0
#define GPIO_GDIR 0x4
#define GPIO_ALT1 0x1
@@ -203,3 +204,4 @@ void show_boot_progress(int status)
gpio_direction_output(LED_RED, 1);
}
}
+#endif
diff --git a/board/openpiton/riscv64/Kconfig b/board/openpiton/riscv64/Kconfig
new file mode 100644
index 00000000000..193c890046e
--- /dev/null
+++ b/board/openpiton/riscv64/Kconfig
@@ -0,0 +1,40 @@
+if TARGET_OPENPITON_RISCV64
+
+config SYS_BOARD
+ default "riscv64"
+
+config SYS_VENDOR
+ default "openpiton"
+
+config SYS_CPU
+ default "generic"
+
+config SYS_CONFIG_NAME
+ default "openpiton-riscv64"
+
+config SYS_TEXT_BASE
+ default 0x81000000 if SPL
+ default 0x80000000 if !RISCV_SMODE
+ default 0x81000000 if RISCV_SMODE
+
+config SPL_TEXT_BASE
+ default 0x82000000
+
+config SPL_OPENSBI_LOAD_ADDR
+ default 0x80000000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_EARLY_INIT_R
+ select SUPPORT_SPL
+ imply CPU_RISCV
+ imply RISCV_TIMER
+ imply SPL_SIFIVE_CLINT
+ imply CMD_CPU
+ imply SPL_CPU_SUPPORT
+ imply SPL_SMP
+ imply SPL_MMC
+ imply SMP
+ imply SPL_RISCV_MMODE
+
+endif
diff --git a/board/openpiton/riscv64/MAINTAINERS b/board/openpiton/riscv64/MAINTAINERS
new file mode 100644
index 00000000000..f80f5b04957
--- /dev/null
+++ b/board/openpiton/riscv64/MAINTAINERS
@@ -0,0 +1,9 @@
+Openpiton BOARD
+M: Tianrui Wei <tianrui-wei@outlook.com>
+S: Maintained
+F: board/openpiton/riscv64/
+F: include/configs/openpiton-riscv64.h
+F: configs/openpiton_riscv64_defconfig
+F: configs/openpiton_riscv64_spl_defconfig
+F: drivers/mmc/piton_mmc.c
+F: arch/riscv/dts/openpiton-riscv64.dts
diff --git a/board/openpiton/riscv64/Makefile b/board/openpiton/riscv64/Makefile
new file mode 100644
index 00000000000..3bffa75a9a4
--- /dev/null
+++ b/board/openpiton/riscv64/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021 Tianrui Wei
+# Tianrui Wei <tianrui-wei@outlook.com>
+obj-y += openpiton-riscv64.o
diff --git a/board/openpiton/riscv64/openpiton-riscv64.c b/board/openpiton/riscv64/openpiton-riscv64.c
new file mode 100644
index 00000000000..f2282d15488
--- /dev/null
+++ b/board/openpiton/riscv64/openpiton-riscv64.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ * Copyright (c) 2021 Tianrui Wei
+ *
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ * Tianrui Wei <tianrui-wei@outlook.com>
+ */
+#include <common.h>
+#include <init.h>
+#include <configs/openpiton-riscv64.h>
+#include <dm.h>
+#include <spl.h>
+
+#ifdef CONFIG_SPL
+void board_boot_order(u32 *spl_boot_list)
+{
+ u8 i;
+ u32 boot_devices[] = {
+ BOOT_DEVICE_MMC1,
+ };
+
+ for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
+ spl_boot_list[i] = boot_devices[i];
+}
+#endif
+
+int board_init(void)
+{
+ return 0;
+}
diff --git a/board/sifive/unmatched/Kconfig b/board/sifive/unmatched/Kconfig
index 88b5883cae7..fb2c1fbb58a 100644
--- a/board/sifive/unmatched/Kconfig
+++ b/board/sifive/unmatched/Kconfig
@@ -47,5 +47,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply PHY_MSCC
imply SYSRESET
imply SYSRESET_GPIO
+ imply CMD_I2C
endif
diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile
index 6308c80d643..e00b330e8ce 100644
--- a/board/sifive/unmatched/Makefile
+++ b/board/sifive/unmatched/Makefile
@@ -3,6 +3,7 @@
# Copyright (c) 2020-2021 SiFive, Inc
obj-y += unmatched.o
+obj-$(CONFIG_ID_EEPROM) += hifive-platform-i2c-eeprom.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
diff --git a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
new file mode 100644
index 00000000000..a2151f15e04
--- /dev/null
+++ b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
@@ -0,0 +1,574 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 SiFive, Inc.
+ *
+ * Based on board/freescale/common/sys_eeprom.c:
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ * York Sun (yorksun@freescale.com)
+ * Haiying Wang (haiying.wang@freescale.com)
+ * Timur Tabi (timur@freescale.com)
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+#include <i2c.h>
+#include <init.h>
+#include <linux/ctype.h>
+#include <linux/delay.h>
+#include <u-boot/crc.h>
+
+#ifndef CONFIG_SYS_EEPROM_BUS_NUM
+#error Requires CONFIG_SYS_EEPROM_BUS_NUM to be defined
+#endif
+
+#define FORMAT_VERSION 0x1
+
+/* Options for the manuf_test_status field */
+#define SIFIVE_MANUF_TEST_STATUS_UNKNOWN 0
+#define SIFIVE_MANUF_TEST_STATUS_PASS 1
+#define SIFIVE_MANUF_TEST_STATUS_FAIL 2
+
+/*
+ * BYTES_PER_EEPROM_PAGE: the AT24C02 datasheet says that data can
+ * only be written in page mode, which means 8 bytes at a time
+ */
+#define BYTES_PER_EEPROM_PAGE 8
+
+/*
+ * EEPROM_WRITE_DELAY_MS: the AT24C02 datasheet says it takes up to
+ * 5ms to complete a given write
+ */
+#define EEPROM_WRITE_DELAY_MS 5000
+
+/*
+ * MAGIC_NUMBER_BYTES: number of bytes used by the magic number
+ */
+#define MAGIC_NUMBER_BYTES 4
+
+/*
+ * SERIAL_NUMBER_BYTES: number of bytes used by the board serial
+ * number
+ */
+#define SERIAL_NUMBER_BYTES 16
+
+/*
+ * MAC_ADDR_BYTES: number of bytes used by the Ethernet MAC address
+ */
+#define MAC_ADDR_BYTES 6
+
+/*
+ * MAC_ADDR_STRLEN: length of mac address string
+ */
+#define MAC_ADDR_STRLEN 17
+
+/*
+ * SiFive OUI. Registration Date is 2018-02-15
+ */
+#define SIFIVE_OUI_PREFIX "70:B3:D5:92:F"
+
+/**
+ * static eeprom: EEPROM layout for the SiFive platform I2C format
+ */
+static struct __attribute__ ((__packed__)) sifive_eeprom {
+ u8 magic[MAGIC_NUMBER_BYTES];
+ u8 format_ver;
+ u16 product_id;
+ u8 pcb_revision;
+ u8 bom_revision;
+ u8 bom_variant;
+ u8 serial[SERIAL_NUMBER_BYTES];
+ u8 manuf_test_status;
+ u8 mac_addr[MAC_ADDR_BYTES];
+ u32 crc;
+} e;
+
+struct sifive_product {
+ u16 id;
+ const char *name;
+};
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read;
+
+/* Magic number at the first four bytes of EEPROM */
+static const unsigned char magic[MAGIC_NUMBER_BYTES] = { 0xf1, 0x5e, 0x50, 0x45 };
+
+/* Does the magic number match that of a SiFive EEPROM? */
+static inline int is_match_magic(void)
+{
+ return (memcmp(&e.magic, &magic, MAGIC_NUMBER_BYTES) == 0);
+}
+
+/* Calculate the current CRC */
+static inline u32 calculate_crc32(void)
+{
+ return crc32(0, (void *)&e, sizeof(struct sifive_eeprom) - sizeof(e.crc));
+}
+
+/* This function should be called after each update to the EEPROM structure */
+static inline void update_crc(void)
+{
+ e.crc = calculate_crc32();
+}
+
+static struct sifive_product sifive_products[] = {
+ { 0, "Unknown"},
+ { 2, "HiFive Unmatched" },
+};
+
+/**
+ * dump_raw_eeprom - display the raw contents of the EEPROM
+ */
+static void dump_raw_eeprom(void)
+{
+ unsigned int i;
+
+ printf("EEPROM dump: (0x%lx bytes)\n", sizeof(e));
+ for (i = 0; i < sizeof(e); i++) {
+ if ((i % 16) == 0)
+ printf("%02X: ", i);
+ printf("%02X ", ((u8 *)&e)[i]);
+ if (((i % 16) == 15) || (i == sizeof(e) - 1))
+ printf("\n");
+ }
+}
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
+{
+ unsigned int i;
+ u32 crc;
+ const char *product_name = "Unknown";
+ char board_serial[SERIAL_NUMBER_BYTES + 1] = { 0 };
+
+ if (!is_match_magic()) {
+ printf("Not a SiFive HiFive EEPROM data format - magic bytes don't match\n");
+ dump_raw_eeprom();
+ return;
+ };
+
+ snprintf(board_serial, sizeof(board_serial), "%s", e.serial);
+
+ for (i = 0; i < ARRAY_SIZE(sifive_products); i++) {
+ if (sifive_products[i].id == e.product_id) {
+ product_name = sifive_products[i].name;
+ break;
+ }
+ };
+
+ printf("SiFive PCB EEPROM format v%u\n", e.format_ver);
+ printf("Product ID: %04hx (%s)\n", e.product_id, product_name);
+ printf("PCB revision: %x\n", e.pcb_revision);
+ printf("BOM revision: %c\n", e.bom_revision);
+ printf("BOM variant: %x\n", e.bom_variant);
+ printf("Serial number: %s\n", board_serial);
+ printf("Ethernet MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ e.mac_addr[0], e.mac_addr[1], e.mac_addr[2],
+ e.mac_addr[3], e.mac_addr[4], e.mac_addr[5]);
+
+ crc = calculate_crc32();
+ if (crc == e.crc) {
+ printf("CRC: %08x\n", e.crc);
+ } else {
+ printf("CRC: %08x (should be %08x)\n", e.crc, crc);
+ dump_raw_eeprom();
+ }
+}
+
+/**
+ * read_eeprom() - read the EEPROM into memory, if it hasn't been read already
+ */
+static int read_eeprom(void)
+{
+ int ret;
+ struct udevice *dev;
+
+ if (has_been_read)
+ return 0;
+
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ 1,
+ &dev);
+ if (!ret)
+ dm_i2c_read(dev, 0, (void *)&e,
+ sizeof(struct sifive_eeprom));
+
+ show_eeprom();
+
+ has_been_read = (ret == 0) ? 1 : 0;
+
+ return ret;
+}
+
+/**
+ * prog_eeprom() - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
+{
+ int ret = 0;
+ unsigned int i;
+ void *p;
+
+ if (!is_match_magic()) {
+ printf("Please read the EEPROM ('read_eeprom') and/or initialize the EEPROM ('initialize') first.\n");
+ return 0;
+ }
+
+ for (i = 0, p = &e; i < sizeof(e);
+ i += BYTES_PER_EEPROM_PAGE, p += BYTES_PER_EEPROM_PAGE) {
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, i, p,
+ min((int)(sizeof(e) - i),
+ BYTES_PER_EEPROM_PAGE));
+
+ if (ret)
+ break;
+
+ udelay(EEPROM_WRITE_DELAY_MS);
+ }
+
+ if (!ret) {
+ /* Verify the write by reading back the EEPROM and comparing */
+ struct sifive_eeprom e2;
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, 0, (void *)&e2, sizeof(e2));
+ if (!ret && memcmp(&e, &e2, sizeof(e)))
+ ret = -1;
+ }
+
+ if (ret) {
+ printf("Programming failed.\n");
+ has_been_read = 0;
+ return -1;
+ }
+
+ printf("Programming passed.\n");
+ return 0;
+}
+
+/**
+ * set_mac_address() - stores a MAC address into the local EEPROM copy
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number),
+ * stores it in the MAC address field of the EEPROM local copy, and
+ * updates the local copy of the CRC.
+ */
+static void set_mac_address(char *string)
+{
+ unsigned int i;
+
+ if (strncasecmp(SIFIVE_OUI_PREFIX, string, 13)) {
+ printf("The MAC address doesn't match SiFive OUI %s\n",
+ SIFIVE_OUI_PREFIX);
+ return;
+ }
+
+ for (i = 0; *string && (i < MAC_ADDR_BYTES); i++) {
+ e.mac_addr[i] = simple_strtoul(string, &string, 16);
+ if (*string == ':')
+ string++;
+ }
+
+ update_crc();
+}
+
+/**
+ * set_manuf_test_status() - stores a test status byte into the in-memory copy
+ *
+ * Takes a pointer to a manufacturing test status string ("unknown",
+ * "pass", "fail") and stores the corresponding numeric ID to the
+ * manuf_test_status field of the EEPROM local copy, and updates the
+ * CRC of the local copy.
+ */
+static void set_manuf_test_status(char *string)
+{
+ if (!strcasecmp(string, "unknown")) {
+ e.manuf_test_status = SIFIVE_MANUF_TEST_STATUS_UNKNOWN;
+ } else if (!strcasecmp(string, "pass")) {
+ e.manuf_test_status = SIFIVE_MANUF_TEST_STATUS_PASS;
+ } else if (!strcasecmp(string, "fail")) {
+ e.manuf_test_status = SIFIVE_MANUF_TEST_STATUS_FAIL;
+ } else {
+ printf("Usage: mac manuf_test_status (unknown|pass|fail)\n");
+ return;
+ }
+
+ update_crc();
+}
+
+/**
+ * set_pcb_revision() - stores a SiFive PCB revision into the local EEPROM copy
+ *
+ * Takes a pointer to a string representing the numeric PCB revision in
+ * decimal ("0" - "255"), stores it in the pcb_revision field of the
+ * EEPROM local copy, and updates the CRC of the local copy.
+ */
+static void set_pcb_revision(char *string)
+{
+ unsigned long p;
+
+ p = simple_strtoul(string, &string, 10);
+ if (p > U8_MAX) {
+ printf("%s must not be greater than %d\n", "PCB revision",
+ U8_MAX);
+ return;
+ }
+
+ e.pcb_revision = p;
+
+ update_crc();
+}
+
+/**
+ * set_bom_revision() - stores a SiFive BOM revision into the local EEPROM copy
+ *
+ * Takes a pointer to a uppercase ASCII character representing the BOM
+ * revision ("A" - "Z"), stores it in the bom_revision field of the
+ * EEPROM local copy, and updates the CRC of the local copy.
+ */
+static void set_bom_revision(char *string)
+{
+ if (string[0] < 'A' || string[0] > 'Z') {
+ printf("BOM revision must be an uppercase letter between A and Z\n");
+ return;
+ }
+
+ e.bom_revision = string[0];
+
+ update_crc();
+}
+
+/**
+ * set_bom_variant() - stores a SiFive BOM variant into the local EEPROM copy
+ *
+ * Takes a pointer to a string representing the numeric BOM variant in
+ * decimal ("0" - "255"), stores it in the bom_variant field of the
+ * EEPROM local copy, and updates the CRC of the local copy.
+ */
+static void set_bom_variant(char *string)
+{
+ unsigned long p;
+
+ p = simple_strtoul(string, &string, 10);
+ if (p > U8_MAX) {
+ printf("%s must not be greater than %d\n", "BOM variant",
+ U8_MAX);
+ return;
+ }
+
+ e.bom_variant = p;
+
+ update_crc();
+}
+
+/**
+ * set_product_id() - stores a SiFive product ID into the local EEPROM copy
+ *
+ * Takes a pointer to a string representing the numeric product ID in
+ * decimal ("0" - "65535"), stores it in the product ID field of the
+ * EEPROM local copy, and updates the CRC of the local copy.
+ */
+static void set_product_id(char *string)
+{
+ unsigned long p;
+
+ p = simple_strtoul(string, &string, 10);
+ if (p > U16_MAX) {
+ printf("%s must not be greater than %d\n", "Product ID",
+ U16_MAX);
+ return;
+ }
+
+ e.product_id = p;
+
+ update_crc();
+}
+
+/**
+ * set_serial_number() - set the PCB serial number in the in-memory copy
+ *
+ * Set the board serial number in the in-memory EEPROM copy from the supplied
+ * string argument, and update the CRC.
+ */
+static void set_serial_number(char *string)
+{
+ if (strlen(string) > SERIAL_NUMBER_BYTES) {
+ printf("Serial number must not be greater than 16 bytes\n");
+ return;
+ }
+
+ memset(e.serial, 0, sizeof(e.serial));
+ strncpy((char *)e.serial, string, sizeof(e.serial));
+ update_crc();
+}
+
+/**
+ * init_local_copy() - initialize the in-memory EEPROM copy
+ *
+ * Initialize the in-memory EEPROM copy with the magic number. Must
+ * be done when preparing to initialize a blank EEPROM, or overwrite
+ * one with a corrupted magic number.
+ */
+static void init_local_copy(void)
+{
+ memset(&e, 0, sizeof(e));
+ memcpy(e.magic, magic, sizeof(e.magic));
+ e.format_ver = FORMAT_VERSION;
+ update_crc();
+}
+
+int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ char *cmd;
+
+ if (argc == 1) {
+ show_eeprom();
+ return 0;
+ }
+
+ if (argc > 3)
+ return cmd_usage(cmdtp);
+
+ cmd = argv[1];
+
+ /* Commands with no argument */
+ if (!strcmp(cmd, "read_eeprom")) {
+ read_eeprom();
+ return 0;
+ } else if (!strcmp(cmd, "initialize")) {
+ init_local_copy();
+ return 0;
+ } else if (!strcmp(cmd, "write_eeprom")) {
+ prog_eeprom();
+ return 0;
+ }
+
+ if (argc != 3)
+ return cmd_usage(cmdtp);
+
+ if (!is_match_magic()) {
+ printf("Please read the EEPROM ('read_eeprom') and/or initialize the EEPROM ('initialize') first.\n");
+ return 0;
+ }
+
+ if (!strcmp(cmd, "serial_number")) {
+ set_serial_number(argv[2]);
+ return 0;
+ } else if (!strcmp(cmd, "manuf_test_status")) {
+ set_manuf_test_status(argv[2]);
+ return 0;
+ } else if (!strcmp(cmd, "mac_address")) {
+ set_mac_address(argv[2]);
+ return 0;
+ } else if (!strcmp(cmd, "pcb_revision")) {
+ set_pcb_revision(argv[2]);
+ return 0;
+ } else if (!strcmp(cmd, "bom_variant")) {
+ set_bom_variant(argv[2]);
+ return 0;
+ } else if (!strcmp(cmd, "bom_revision")) {
+ set_bom_revision(argv[2]);
+ return 0;
+ } else if (!strcmp(cmd, "product_id")) {
+ set_product_id(argv[2]);
+ return 0;
+ }
+
+ return cmd_usage(cmdtp);
+}
+
+/**
+ * mac_read_from_eeprom() - read the MAC address from EEPROM
+ *
+ * This function reads the MAC address from EEPROM and sets the
+ * appropriate environment variables for each one read.
+ *
+ * The environment variables are only set if they haven't been set already.
+ * This ensures that any user-saved variables are never overwritten.
+ *
+ * This function must be called after relocation.
+ */
+int mac_read_from_eeprom(void)
+{
+ u32 crc;
+ char board_serial[SERIAL_NUMBER_BYTES + 1] = { 0 };
+
+ puts("EEPROM: ");
+
+ if (read_eeprom()) {
+ printf("Read failed.\n");
+ return 0;
+ }
+
+ if (!is_match_magic()) {
+ printf("Invalid ID (%02x %02x %02x %02x)\n",
+ e.magic[0], e.magic[1], e.magic[2], e.magic[3]);
+ dump_raw_eeprom();
+ return 0;
+ }
+
+ crc = calculate_crc32();
+ if (crc != e.crc) {
+ printf("CRC mismatch (%08x != %08x)\n", crc, e.crc);
+ dump_raw_eeprom();
+ return 0;
+ }
+
+ eth_env_set_enetaddr("ethaddr", e.mac_addr);
+
+ if (!env_get("serial#")) {
+ snprintf(board_serial, sizeof(board_serial), "%s", e.serial);
+ env_set("serial#", board_serial);
+ }
+
+ return 0;
+}
+
+/**
+ * get_pcb_revision_from_eeprom - get the PCB revision
+ *
+ * Read the EEPROM to determine the board revision.
+ *
+ * This function is called before relocation, so we need to read a private
+ * copy of the EEPROM into a local variable on the stack.
+ */
+u8 get_pcb_revision_from_eeprom(void)
+{
+ struct __attribute__ ((__packed__)) board_eeprom {
+ u8 magic[MAGIC_NUMBER_BYTES];
+ u8 format_ver;
+ u16 product_id;
+ u8 pcb_revision;
+ } be;
+
+ int ret;
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ 1,
+ &dev);
+
+ if (!ret)
+ dm_i2c_read(dev, 0, (void *)&be,
+ sizeof(struct board_eeprom));
+
+ return be.pcb_revision;
+}
diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
index 5e1333b09a8..74134b03ee6 100644
--- a/board/sifive/unmatched/spl.c
+++ b/board/sifive/unmatched/spl.c
@@ -10,11 +10,14 @@
#include <spl.h>
#include <misc.h>
#include <log.h>
+#include <fdtdec.h>
+#include <dm/root.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/spl.h>
+#include <asm/arch/eeprom.h>
#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
@@ -26,6 +29,16 @@ int spl_board_init_f(void)
{
int ret;
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT)
+ int rescan;
+
+ ret = fdtdec_resetup(&rescan);
+ if (!ret && rescan) {
+ dm_uninit();
+ dm_init_and_scan(true);
+ }
+#endif
+
ret = spl_soc_init();
if (ret) {
debug("HiFive Unmatched FU740 SPL init failed: %d\n", ret);
@@ -79,7 +92,18 @@ u32 spl_boot_device(void)
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
- /* boot using first FIT config */
- return 0;
+ /*
+ * Apply different DDR params on different board revision.
+ * Use PCB revision which is byte 0x7 in I2C platform EEPROM
+ * to distinguish that.
+ */
+ if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3 &&
+ !strcmp(name, "hifive-unmatched-a00"))
+ return 0;
+ else if (get_pcb_revision_from_eeprom() != PCB_REVISION_REV3 &&
+ !strcmp(name, "hifive-unmatched-a00-rev1"))
+ return 0;
+
+ return -1;
}
#endif
diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig
new file mode 100644
index 00000000000..706b8dc0f1c
--- /dev/null
+++ b/board/socionext/developerbox/Kconfig
@@ -0,0 +1,36 @@
+if ARCH_SYNQUACER
+
+choice
+ prompt "SC2A11 Cortex-A53 MPCore 24cores"
+ optional
+
+config TARGET_DEVELOPERBOX
+ bool "Socionext DeveloperBox"
+ select PCI
+ select DM_PCI
+ select PCIE_ECAM_SYNQUACER
+ select SYS_DISABLE_DCACHE_OPS
+ select OF_BOARD_SETUP
+ help
+ Choose this option if you build the U-Boot for the DeveloperBox
+ 96boards Enterprise Edition.
+ This board will booted from SCP firmware and it enables SMMU, thus
+ the dcache is updated automatically when DMA operation is executed.
+endchoice
+
+config SYS_SOC
+ default "sc2a11"
+
+if TARGET_DEVELOPERBOX
+
+config SYS_BOARD
+ default "developerbox"
+
+config SYS_VENDOR
+ default "socionext"
+
+config SYS_CONFIG_NAME
+ default "synquacer"
+
+endif
+endif
diff --git a/board/socionext/developerbox/MAINTAINERS b/board/socionext/developerbox/MAINTAINERS
new file mode 100644
index 00000000000..aa672b6e052
--- /dev/null
+++ b/board/socionext/developerbox/MAINTAINERS
@@ -0,0 +1,14 @@
+DEVELOPER BOX
+M: Masami Hiramatsu <masami.hiramatsu@linaro.org>
+M: Jassi Brar <jaswinder.singh@linaro.org>
+S: Maintained
+F: arch/arm/dts/synquacer-*
+F: board/socionext/developerbox/*
+F: configs/synquacer_developerbox_defconfig
+F: drivers/i2c/synquacer_i2c.c
+F: drivers/mmc/f_sdh30.c
+F: drivers/net/sni_netsec.c
+F: drivers/pci/pcie_ecam_synquacer.c
+F: drivers/spi/spi-synquacer.c
+F: include/configs/synquacer.h
+F: doc/board/socionext/developerbox.rst
diff --git a/board/socionext/developerbox/Makefile b/board/socionext/developerbox/Makefile
new file mode 100644
index 00000000000..4a46de995a0
--- /dev/null
+++ b/board/socionext/developerbox/Makefile
@@ -0,0 +1,9 @@
+#
+# Author: Masami Hiramatsu <masami.hiramatsu@linaro.org>
+#
+# Copyright (C) 2021 Linaro Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := developerbox.o
diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c
new file mode 100644
index 00000000000..34335baec36
--- /dev/null
+++ b/board/socionext/developerbox/developerbox.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * u-boot/board/socionext/developerbox/developerbox.c
+ *
+ * Copyright (C) 2016-2017 Socionext Inc.
+ * Copyright (C) 2021 Linaro Ltd.
+ */
+#include <asm/types.h>
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <common.h>
+#include <env_internal.h>
+#include <fdt_support.h>
+#include <log.h>
+
+static struct mm_region sc2a11_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+ /* 1st DDR block */
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = PHYS_SDRAM_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+ /* 2nd DDR place holder */
+ 0,
+ }, {
+ /* 3rd DDR place holder */
+ 0,
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = sc2a11_mem_map;
+
+#define DDR_REGION_INDEX(i) (1 + (i))
+#define MAX_DDR_REGIONS 3
+
+struct draminfo_entry {
+ u64 base;
+ u64 size;
+};
+
+struct draminfo {
+ u32 nr_regions;
+ u32 reserved;
+ struct draminfo_entry entry[3];
+};
+
+struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LOAD_OFFSET 0x100
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
+
+ gd->env_addr = (ulong)&default_environment[0];
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /* Remove SPI NOR and I2C0 for making DT compatible with EDK2 */
+ fdt_del_node_and_alias(blob, "spi_nor");
+ fdt_del_node_and_alias(blob, "i2c0");
+
+ return 0;
+}
+
+/*
+ * DRAM configuration
+ */
+
+int dram_init(void)
+{
+ struct draminfo_entry *ent = synquacer_draminfo->entry;
+ struct mm_region *mr;
+ int i, ri;
+
+ if (synquacer_draminfo->nr_regions < 1) {
+ log_err("Failed to get correct DRAM information\n");
+ return -1;
+ }
+
+ /*
+ * U-Boot RAM size must be under the first DRAM region so that it doesn't
+ * access secure memory which is at the end of the first DRAM region.
+ */
+ gd->ram_size = ent[0].size;
+
+ /* Update memory region maps */
+ for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
+ if (i >= MAX_DDR_REGIONS)
+ break;
+
+ ri = DDR_REGION_INDEX(i);
+ mem_map[ri].phys = ent[i].base;
+ mem_map[ri].size = ent[i].size;
+ if (i == 0)
+ continue;
+
+ mr = &mem_map[DDR_REGION_INDEX(0)];
+ mem_map[ri].virt = mr->virt + mr->size;
+ mem_map[ri].attrs = mr->attrs;
+ }
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ struct draminfo_entry *ent = synquacer_draminfo->entry;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
+ if (i < synquacer_draminfo->nr_regions) {
+ debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base);
+ gd->bd->bi_dram[i].start = ent[i].base;
+ gd->bd->bi_dram[i].size = ent[i].size;
+ }
+ }
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: SC2A11:Cortex-A53 MPCore 24cores\n");
+ return 0;
+}
diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c
index 3b0de82db28..57ca9f659c1 100644
--- a/board/st/stv0991/stv0991.c
+++ b/board/st/stv0991/stv0991.c
@@ -37,7 +37,7 @@ U_BOOT_DRVINFO(stv09911_serials) = {
};
#endif
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
void show_boot_progress(int progress)
{
printf("%i\n", progress);
diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c
index 3c744b943f4..9d4ffb0f979 100644
--- a/board/timll/devkit3250/devkit3250.c
+++ b/board/timll/devkit3250/devkit3250.c
@@ -38,7 +38,7 @@ void reset_periph(void)
int board_early_init_f(void)
{
- lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+ lpc32xx_uart_init(CONFIG_CONS_INDEX);
lpc32xx_i2c_init(1);
lpc32xx_i2c_init(2);
lpc32xx_ssp_init();
diff --git a/board/timll/devkit3250/devkit3250_spl.c b/board/timll/devkit3250/devkit3250_spl.c
index 47af78ae0b1..12e8ae9c39c 100644
--- a/board/timll/devkit3250/devkit3250_spl.c
+++ b/board/timll/devkit3250/devkit3250_spl.c
@@ -49,7 +49,7 @@ void spl_board_init(void)
/* First of all silence buzzer controlled by GPO_20 */
writel((1 << 20), &gpio->p3_outp_clr);
- lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+ lpc32xx_uart_init(CONFIG_CONS_INDEX);
preloader_console_init();
ddr_init(&dram_64mb);
diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c
index bdcecff7308..5d12f84cfea 100644
--- a/board/work-microwave/work_92105/work_92105.c
+++ b/board/work-microwave/work_92105/work_92105.c
@@ -37,7 +37,7 @@ void reset_periph(void)
int board_early_init_f(void)
{
/* initialize serial port for console */
- lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+ lpc32xx_uart_init(CONFIG_CONS_INDEX);
/* enable I2C, SSP, MAC, NAND */
lpc32xx_i2c_init(1); /* only I2C1 has devices, I2C2 has none */
lpc32xx_ssp_init();
diff --git a/board/work-microwave/work_92105/work_92105_spl.c b/board/work-microwave/work_92105/work_92105_spl.c
index a31553a2d25..d9401145f27 100644
--- a/board/work-microwave/work_92105/work_92105_spl.c
+++ b/board/work-microwave/work_92105/work_92105_spl.c
@@ -58,7 +58,7 @@ const struct emc_dram_settings dram_128mb = {
void spl_board_init(void)
{
/* initialize serial port for console */
- lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+ lpc32xx_uart_init(CONFIG_CONS_INDEX);
/* initialize console */
preloader_console_init();
/* init DDR and NAND to chainload U-Boot */
diff --git a/cmd/net.c b/cmd/net.c
index beb2877dfd5..76c7e751250 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <bootstage.h>
#include <command.h>
+#include <dm.h>
#include <env.h>
#include <image.h>
#include <net.h>
@@ -480,3 +481,48 @@ U_BOOT_CMD(
);
#endif /* CONFIG_CMD_LINK_LOCAL */
+
+#ifdef CONFIG_DM_ETH
+static int do_net_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ const struct udevice *current = eth_get_dev();
+ unsigned char env_enetaddr[ARP_HLEN];
+ const struct udevice *dev;
+ struct uclass *uc;
+
+ uclass_id_foreach_dev(UCLASS_ETH, dev, uc) {
+ eth_env_get_enetaddr_by_index("eth", dev_seq(dev), env_enetaddr);
+ printf("eth%d : %s %pM %s\n", dev_seq(dev), dev->name, env_enetaddr,
+ current == dev ? "active" : "");
+ }
+ return CMD_RET_SUCCESS;
+}
+
+static struct cmd_tbl cmd_net[] = {
+ U_BOOT_CMD_MKENT(list, 1, 0, do_net_list, "", ""),
+};
+
+static int do_net(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct cmd_tbl *cp;
+
+ cp = find_cmd_tbl(argv[1], cmd_net, ARRAY_SIZE(cmd_net));
+
+ /* Drop the net command */
+ argc--;
+ argv++;
+
+ if (!cp || argc > cp->maxargs)
+ return CMD_RET_USAGE;
+ if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp))
+ return CMD_RET_SUCCESS;
+
+ return cp->cmd(cmdtp, flag, argc, argv);
+}
+
+U_BOOT_CMD(
+ net, 2, 1, do_net,
+ "NET sub-system",
+ "list - list available devices\n"
+);
+#endif // CONFIG_DM_ETH
diff --git a/common/init/board_init.c b/common/init/board_init.c
index 3f183ee1132..0965b96fa3a 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -166,7 +166,9 @@ void board_init_f_init_reserve(ulong base)
board_init_f_init_stack_protection();
}
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
/*
* Board-specific Platform code can reimplement show_boot_progress () if needed
*/
__weak void show_boot_progress(int val) {}
+#endif
diff --git a/common/spl/spl.c b/common/spl/spl.c
index a0a608fd772..eba77cace6d 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -58,10 +58,12 @@ binman_sym_declare(ulong, spl, size);
/* Define board data structure */
static struct bd_info bdata __attribute__ ((section(".data")));
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
/*
* Board-specific Platform code can reimplement show_boot_progress () if needed
*/
__weak void show_boot_progress(int val) {}
+#endif
#if defined(CONFIG_SPL_OS_BOOT) || CONFIG_IS_ENABLED(HANDOFF) || \
defined(CONFIG_SPL_ATF)
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 003ebd8c6bf..446d5948da3 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -147,7 +147,9 @@ CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCIE"
CONFIG_BOOTDELAY=6
+CONFIG_BOARD_LATE_INIT=y
CONFIG_MISC_INIT_R=y
+CONFIG_PCI_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
@@ -172,16 +174,14 @@ CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_RGMII=y
+CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_PCI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index 93c048cee86..c0354bce1a2 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -38,6 +38,7 @@ CONFIG_CMD_JFFS2=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SYS_I2C_LPC32XX=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
@@ -51,6 +52,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ADDR=31
CONFIG_PHY_SMSC=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=5
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_USB=y
diff --git a/configs/ea-lpc3250devkitv2_defconfig b/configs/ea-lpc3250devkitv2_defconfig
new file mode 100644
index 00000000000..e8d60b573ea
--- /dev/null
+++ b/configs/ea-lpc3250devkitv2_defconfig
@@ -0,0 +1,26 @@
+CONFIG_ARM=y
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_LPC32XX=y
+CONFIG_SYS_TEXT_BASE=0x83000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_EA_LPC3250DEVKITV2=y
+CONFIG_DEFAULT_DEVICE_TREE="lpc3250-ea3250"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+# CONFIG_AUTOBOOT is not set
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="EA-LPC3250v2=> "
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_OF_CONTROL=y
+# CONFIG_NET is not set
+CONFIG_LPC32XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_LPC32XX=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=5
+CONFIG_SYS_NS16550=y
+CONFIG_PANIC_HANG=y
diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig
index 5d28135a822..378bf936d73 100644
--- a/configs/integratorap_cm720t_defconfig
+++ b/configs/integratorap_cm720t_defconfig
@@ -16,7 +16,6 @@ CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-AP # "
CONFIG_CMD_IMLS=y
CONFIG_CMD_ARMFLASH=y
-CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_MMC is not set
@@ -24,8 +23,5 @@ CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_EEPRO100=y
-CONFIG_TULIP=y
-CONFIG_PCI=y
CONFIG_BAUDRATE=38400
CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig
index 0e914e91ebe..4ec2961a4ec 100644
--- a/configs/integratorap_cm920t_defconfig
+++ b/configs/integratorap_cm920t_defconfig
@@ -16,7 +16,6 @@ CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-AP # "
CONFIG_CMD_IMLS=y
CONFIG_CMD_ARMFLASH=y
-CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_MMC is not set
@@ -24,8 +23,5 @@ CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_EEPRO100=y
-CONFIG_TULIP=y
-CONFIG_PCI=y
CONFIG_BAUDRATE=38400
CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig
index d28bc0f976c..012d346500f 100644
--- a/configs/integratorap_cm926ejs_defconfig
+++ b/configs/integratorap_cm926ejs_defconfig
@@ -16,7 +16,6 @@ CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-AP # "
CONFIG_CMD_IMLS=y
CONFIG_CMD_ARMFLASH=y
-CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_MMC is not set
@@ -24,8 +23,5 @@ CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_EEPRO100=y
-CONFIG_TULIP=y
-CONFIG_PCI=y
CONFIG_BAUDRATE=38400
CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig
index ae44f01ff50..1868c7024f0 100644
--- a/configs/integratorap_cm946es_defconfig
+++ b/configs/integratorap_cm946es_defconfig
@@ -16,7 +16,6 @@ CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-AP # "
CONFIG_CMD_IMLS=y
CONFIG_CMD_ARMFLASH=y
-CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_MMC is not set
@@ -24,8 +23,5 @@ CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_EEPRO100=y
-CONFIG_TULIP=y
-CONFIG_PCI=y
CONFIG_BAUDRATE=38400
CONFIG_OF_LIBFDT=y
diff --git a/configs/openpiton_riscv64_defconfig b/configs/openpiton_riscv64_defconfig
new file mode 100644
index 00000000000..cd66db2fe52
--- /dev/null
+++ b/configs/openpiton_riscv64_defconfig
@@ -0,0 +1,76 @@
+CONFIG_RISCV=y
+CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64"
+CONFIG_TARGET_OPENPITON_RISCV64=y
+CONFIG_ARCH_RV64I=y
+CONFIG_CMODEL_MEDANY=y
+CONFIG_RISCV_SMODE=y
+CONFIG_OF_BOARD_FIXUP=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+# CONFIG_EXPERT is not set
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SYS_PROMPT="openpiton$ "
+# CONFIG_CMD_CPU is not set
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNLZ4 is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_READ=y
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_BLOCK_CACHE is not set
+# CONFIG_CMD_DATE is not set
+# CONFIG_CMD_SLEEP is not set
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+CONFIG_OF_EMBED=y
+# CONFIG_NET is not set
+CONFIG_CPU=y
+CONFIG_MMC=y
+# CONFIG_MMC_WRITE is not set
+# CONFIG_MMC_HW_PARTITIONING is not set
+# CONFIG_MMC_VERBOSE is not set
+CONFIG_MMC_PITON=y
+CONFIG_RAM=y
+# CONFIG_RAM_SIFIVE is not set
+CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_FS_SQUASHFS=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+CONFIG_MD5=y
+CONFIG_GETOPT=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SPL_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/openpiton_riscv64_spl_defconfig b/configs/openpiton_riscv64_spl_defconfig
new file mode 100644
index 00000000000..16195be0d8f
--- /dev/null
+++ b/configs/openpiton_riscv64_spl_defconfig
@@ -0,0 +1,87 @@
+CONFIG_RISCV=y
+CONFIG_SYS_TEXT_BASE=0x80000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
+CONFIG_SPL=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_PAYLOAD=""
+CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64"
+CONFIG_TARGET_OPENPITON_RISCV64=y
+CONFIG_NR_CPUS=32
+CONFIG_ARCH_RV64I=y
+CONFIG_CMODEL_MEDANY=y
+CONFIG_RISCV_SMODE=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+# CONFIG_EXPERT is not set
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+# CONFIG_SPL_BANNER_PRINT is not set
+CONFIG_SPL_CPU=y
+CONFIG_SPL_FS_EXT4=y
+CONFIG_SPL_RTC_SUPPORT=y
+CONFIG_SYS_PROMPT="openpiton$ "
+# CONFIG_CMD_CPU is not set
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNLZ4 is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_READ=y
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_BLOCK_CACHE is not set
+# CONFIG_CMD_DATE is not set
+# CONFIG_CMD_SLEEP is not set
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
+# CONFIG_NET is not set
+CONFIG_CPU=y
+CONFIG_MMC=y
+# CONFIG_MMC_WRITE is not set
+# CONFIG_MMC_HW_PARTITIONING is not set
+# CONFIG_MMC_VERBOSE is not set
+CONFIG_MMC_PITON=y
+CONFIG_RAM=y
+# CONFIG_RAM_SIFIVE is not set
+CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_FS_SQUASHFS=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+CONFIG_MD5=y
+CONFIG_GETOPT=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig
index 5bf40cee08c..d665c8f5d94 100644
--- a/configs/sifive_unleashed_defconfig
+++ b/configs/sifive_unleashed_defconfig
@@ -14,6 +14,7 @@ CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
+CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unleashed-a00.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_MISC_INIT_R=y
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index 4c265048672..3a456702803 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -14,6 +14,7 @@ CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
+CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -40,3 +41,7 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_SPL_OF_LIST="hifive-unmatched-a00 hifive-unmatched-a00-rev1"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig
new file mode 100644
index 00000000000..d42db9a1d69
--- /dev/null
+++ b/configs/synquacer_developerbox_defconfig
@@ -0,0 +1,129 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SYNQUACER=y
+CONFIG_SYS_TEXT_BASE=0x08200000
+CONFIG_ENV_SIZE=0x30000
+CONFIG_ENV_OFFSET=0x300000
+CONFIG_DEBUG_UART_BASE=0x2a400000
+CONFIG_DEBUG_UART_CLOCK=62500000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_DEVELOPERBOX=y
+CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox"
+CONFIG_AHCI=y
+CONFIG_BOOTSTAGE_STASH_SIZE=4096
+CONFIG_BOOTM_EFI=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTEFI=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_NVEDIT_INFO=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_BOOTP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DATE=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_NVME=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDPARTS_DEFAULT="nor1:448k(BootStrap-BL1),576k(Flash-Writer),512k(SCP-BL2),480k(FIP-TFA),32k(Stg2-Tables),1m@2m(U-Boot),1m@3m(UBoot-Env),2m@5m(Ex-OPTEE)"
+CONFIG_MTDIDS_DEFAULT="nor1=nor1"
+CONFIG_CMD_LOG=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_EFI_PARTITION=y
+CONFIG_EFI_LOADER=y
+CONFIG_EFI_DEVICE_PATH_TO_TEXT=y
+CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2=y
+CONFIG_EFI_UNICODE_CAPITALIZATION=y
+CONFIG_EFI_HAVE_RUNTIME_RESET=y
+CONFIG_EFI_GET_TIME=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_CMD_EFI_VARIABLE_FILE_STORE=Y
+CONFIG_OF_SEPARATE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=0
+CONFIG_USE_ENV_SPI_CS=y
+CONFIG_ENV_SPI_CS=0
+CONFIG_PROT_UDP=y
+CONFIG_BAUDRATE=115200
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SATA=y
+CONFIG_NVME=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_SYNQUACER=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_F_SDH30=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=31250000
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_SNI_NETSEC=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_PCF8563=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SYNQUACER_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT=y
+CONFIG_EFI_CAPSULE_FIRMWARE=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
+CONFIG_EFI_CAPSULE_FMP_HEADER=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_CMD_DFU=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_DFU_SF_PART=y
+CONFIG_FIT=y
+CONFIG_OF_LIBFDT=y
+CONFIG_CMD_ERASEENV=y
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index c3f666dcfe9..507f24fc375 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -42,11 +42,14 @@ CONFIG_DOS_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_VERSION_VARIABLE=y
+CONFIG_SYS_I2C_LPC32XX=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_SMSC=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=5
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/doc/board/emulation/qemu_capsule_update.rst b/doc/board/emulation/qemu_capsule_update.rst
index 33ce4bcd32e..0a2286d039d 100644
--- a/doc/board/emulation/qemu_capsule_update.rst
+++ b/doc/board/emulation/qemu_capsule_update.rst
@@ -39,16 +39,9 @@ In addition, the following config needs to be disabled(QEMU ARM specific)::
CONFIG_TFABOOT
-The capsule file can be generated by using the GenerateCapsule.py
-script in EDKII::
-
- $ ./BaseTools/BinWrappers/PosixLike/GenerateCapsule -e -o \
- <capsule_file_name> --fw-version <val> --lsv <val> --guid \
- e2bb9c06-70e9-4b14-97a3-5a7913176e3f --verbose --update-image-index \
- <val> --verbose <u-boot.bin>
+The capsule file can be generated by using the tools/mkeficapsule::
-The above is a wrapper script(GenerateCapsule) which eventually calls
-the actual GenerateCapsule.py script.
+ $ mkeficapsule --raw <u-boot.bin> --index 1 <capsule_file_name>
As per the UEFI specification, the capsule file needs to be placed on
the EFI System Partition, under the \EFI\UpdateCapsule directory. The
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 747511f7ddd..196b5976098 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -19,9 +19,11 @@ Board-specific doc
intel/index
kontron/index
microchip/index
+ openpiton/index
rockchip/index
sifive/index
sipeed/index
+ socionext/index
st/index
tbs/index
toradex/index
diff --git a/doc/board/openpiton/index.rst b/doc/board/openpiton/index.rst
new file mode 100644
index 00000000000..c469102c4b0
--- /dev/null
+++ b/doc/board/openpiton/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+OpenPiton
+=========
+
+.. toctree::
+ :maxdepth: 2
+
+ riscv64
diff --git a/doc/board/openpiton/riscv64.rst b/doc/board/openpiton/riscv64.rst
new file mode 100644
index 00000000000..253b37c41cd
--- /dev/null
+++ b/doc/board/openpiton/riscv64.rst
@@ -0,0 +1,376 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Openpiton RISC-V SoC
+====================
+
+OpenPiton RISC-V SoC
+--------------------
+OpenPiton is an open source, manycore processor and research platform. It is a
+tiled manycore framework scalable from one to 1/2 billion cores. It supports a
+number of ISAs including RISC-V with its P-Mesh cache coherence protocol and
+networks on chip. It is highly configurable in both core and uncore components.
+OpenPiton has been verified in both ASIC and multiple Xilinx FPGA prototypes
+running full-stack Debian linux.
+
+RISC-V Standard Bootflow
+-------------------------
+Currently, OpenPiton implements RISC-V standard bootflow in the following steps
+mover.S -> u-boot-spl -> opensbi -> u-boot -> Linux
+This board supports S-mode u-boot as well as M-mode SPL
+
+Building OpenPition
+---------------------
+If you'd like to build OpenPiton, please go to OpenPiton github repo
+(at https://github.com/PrincetonUniversity/openpiton) to build from the latest
+changes
+
+Building Images
+---------------------------
+
+SPL
+---
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=<riscv64 toolchain prefix>
+ export ARCH=riscv
+
+3. make openpiton_riscv64_spl_defconfig
+4. make
+
+U-Boot
+------
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=<riscv64 toolchain prefix>
+ export ARCH=riscv
+
+3. make openpiton_riscv64_defconfig
+4. make
+
+
+opensbi
+-------
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=<riscv64 toolchain prefix>
+ export ARCH=riscv
+
+3. Go to OpenSBI directory
+4. make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<path to u-boot-nodtb.bin>
+
+
+Using fw_payload.bin with linux
+-------------------------------
+Put the generated fw_payload.bin into the /boot directory on the root filesystem,
+plug in the SD card, then flash the bitstream. Linux will boot automatically.
+
+Booting
+-------
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+Sample Dual-core Debian boot log from OpenPiton
+-----------------------------------------------
+
+.. code-block:: none
+
+ Trying to boot from MMC1
+
+ OpenSBI v0.9-5-gd06cb61
+ ____ _____ ____ _____
+ / __ \ / ____| _ \_ _|
+ | | | |_ __ ___ _ __ | (___ | |_) || |
+ | | | | '_ \ / _ \ '_ \ \___ \| _ < | |
+ | |__| | |_) | __/ | | |____) | |_) || |_
+ \____/| .__/ \___|_| |_|_____/|____/_____|
+ | |
+ |_|
+
+ Platform Name : OPENPITON RISC-V
+ Platform Features : timer,mfdeleg
+ Platform HART Count : 3
+ Firmware Base : 0x80000000
+ Firmware Size : 104 KB
+ Runtime SBI Version : 0.2
+
+ Domain0 Name : root
+ Domain0 Boot HART : 0
+ Domain0 HARTs : 0*,1*,2*
+ Domain0 Region00 : 0x0000000080000000-0x000000008001ffff ()
+ Domain0 Region01 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
+ Domain0 Next Address : 0x0000000080200000
+ Domain0 Next Arg1 : 0x0000000082200000
+ Domain0 Next Mode : S-mode
+ Domain0 SysReset : yes
+
+ Boot HART ID : 0
+ Boot HART Domain : root
+ Boot HART ISA : rv64imafdcsu
+ Boot HART Features : scounteren,mcounteren
+ Boot HART PMP Count : 0
+ Boot HART PMP Granularity : 0
+ Boot HART PMP Address Bits: 0
+ Boot HART MHPM Count : 0
+ Boot HART MHPM Count : 0
+ Boot HART MIDELEG : 0x0000000000000222
+ Boot HART MEDELEG : 0x000000000000b109
+
+
+ U-Boot 2021.01+ (Jun 12 2021 - 10:31:34 +0800)
+
+ DRAM: 1 GiB
+ MMC: sdhci@f000000000: 0 (eMMC)
+ In: uart@fff0c2c000
+ Out: uart@fff0c2c000
+ Err: uart@fff0c2c000
+ Hit any key to stop autoboot: 0
+ 6492992 bytes read in 5310 ms (1.2 MiB/s)
+ ## Flattened Device Tree blob at 86000000
+ Booting using the fdt blob at 0x86000000
+ Loading Device Tree to 00000000bfffa000, end 00000000bffff007 ... OK
+
+ Starting kernel ...
+
+ [ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
+ [ 0.000000] Linux version 5.6.0-rc4-gb9d34f7e294d-dirty
+ [ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
+ [ 0.000000] printk: bootconsole [sbi0] enabled
+ [ 0.000000] Zone ranges:
+ [ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000bfffffff]
+ [ 0.000000] Normal empty
+ [ 0.000000] Movable zone start for each node
+ [ 0.000000] Early memory node ranges
+ [ 0.000000] node 0: [mem 0x0000000080200000-0x00000000bfffffff]
+ [ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000bfffffff]
+ [ 0.000000] On node 0 totalpages: 261632
+ [ 0.000000] DMA32 zone: 4088 pages used for memmap
+ [ 0.000000] DMA32 zone: 0 pages reserved
+ [ 0.000000] DMA32 zone: 261632 pages, LIFO batch:63
+ [ 0.000000] software IO TLB: mapped [mem 0xbaffa000-0xbeffa000] (64MB)
+ [ 0.000000] SBI specification v0.2 detected
+ [ 0.000000] SBI implementation ID=0x1 Version=0x9
+ [ 0.000000] SBI v0.2 TIME extension detected
+ [ 0.000000] SBI v0.2 IPI extension detected
+ [ 0.000000] SBI v0.2 RFENCE extension detected
+ [ 0.000000] SBI v0.2 HSM extension detected
+ [ 0.000000] elf_hwcap is 0x112d
+ [ 0.000000] percpu: Embedded 16 pages/cpu s25368 r8192 d31976 u65536
+ [ 0.000000] pcpu-alloc: s25368 r8192 d31976 u65536 alloc=16*4096
+ [ 0.000000] pcpu-alloc: [0] 0
+ [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 257544
+ [ 0.000000] Kernel command line: earlycon=sbi root=/dev/piton_sd1
+ [ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
+ [ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
+ [ 0.000000] Sorting __ex_table...
+ [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
+ [ 0.000000] Memory: 956252K/1046528K available (4357K kernel code, 286K rwdata, 1200K rodata, 168K init, 311K bss, 90276K re)
+ [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
+ [ 0.000000] rcu: Hierarchical RCU implementation.
+ [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
+ [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
+ [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
+ [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
+ [ 0.000000] plic: mapped 2 interrupts with 1 handlers for 2 contexts.
+ [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0]
+ [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1ec037a6a, max_idle_ns: 7052723236599 ns
+ [ 0.000138] sched_clock: 64 bits at 520kHz, resolution 1919ns, wraps every 4398046510738ns
+ [ 0.009429] printk: console [hvc0] enabled
+ [ 0.009429] printk: console [hvc0] enabled
+ [ 0.017850] printk: bootconsole [sbi0] disabled
+ [ 0.017850] printk: bootconsole [sbi0] disabled
+ [ 0.028029] Calibrating delay loop (skipped), value calculated using timer frequency.. 1.04 BogoMIPS (lpj=5208)
+ [ 0.038753] pid_max: default: 32768 minimum: 301
+ [ 0.050248] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
+ [ 0.058661] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
+ [ 0.069359] *** VALIDATE tmpfs ***
+ [ 0.089093] *** VALIDATE proc ***
+ [ 0.101135] *** VALIDATE cgroup ***
+ [ 0.105019] *** VALIDATE cgroup2 ***
+ [ 0.144310] rcu: Hierarchical SRCU implementation.
+ [ 0.162836] smp: Bringing up secondary CPUs ...
+ [ 0.167736] smp: Brought up 1 node, 1 CPU
+ [ 0.185982] devtmpfs: initialized
+ [ 0.216237] random: get_random_u32 called from bucket_table_alloc.isra.25+0x4e/0x15c with crng_init=0
+ [ 0.236026] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
+ [ 0.246916] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
+ [ 0.266994] NET: Registered protocol family 16
+ [ 0.763362] clocksource: Switched to clocksource riscv_clocksource
+ [ 0.770122] *** VALIDATE bpf ***
+ [ 0.782837] *** VALIDATE ramfs ***
+ [ 0.829997] NET: Registered protocol family 2
+ [ 0.853577] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
+ [ 0.864085] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
+ [ 0.875373] TCP bind hash table entries: 8192 (order: 5, 131072 bytes, linear)
+ [ 0.887958] TCP: Hash tables configured (established 8192 bind 8192)
+ [ 0.902149] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
+ [ 0.909904] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
+ [ 0.924809] NET: Registered protocol family 1
+ [ 0.948605] RPC: Registered named UNIX socket transport module.
+ [ 0.956003] RPC: Registered udp transport module.
+ [ 0.961565] RPC: Registered tcp transport module.
+ [ 0.966432] RPC: Registered tcp NFSv4.1 backchannel transport module.
+ [ 0.987180] Initialise system trusted keyrings
+ [ 0.998953] workingset: timestamp_bits=46 max_order=18 bucket_order=0
+ [ 1.323977] *** VALIDATE nfs ***
+ [ 1.328520] *** VALIDATE nfs4 ***
+ [ 1.334422] NFS: Registering the id_resolver key type
+ [ 1.340148] Key type id_resolver registered
+ [ 1.345280] Key type id_legacy registered
+ [ 1.349820] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
+ [ 1.357610] Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+ [ 1.866909] Key type asymmetric registered
+ [ 1.872460] Asymmetric key parser 'x509' registered
+ [ 1.878750] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
+ [ 1.887480] io scheduler mq-deadline registered
+ [ 1.892864] io scheduler kyber registered
+ [ 3.905595] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+ [ 3.954332] fff0c2c000.uart: ttyS0 at MMIO 0xfff0c2c000 (irq = 1, base_baud = 4166687) is a 16550
+ [ 4.254794] loop: module loaded
+ [ 4.258269] piton_sd:v1.0 Apr 26, 2019
+ [ 4.258269]
+ [ 4.265170] gpt partition table header:
+ [ 4.265283] signature: 5452415020494645
+ [ 4.269258] revision: 10000
+ [ 4.273746] size: 5c
+ [ 4.276659] crc_header: 26b42404
+ [ 4.278911] reserved: 0
+ [ 4.282730] current lba: 1
+ [ 4.285311] backup lda: 3b723ff
+ [ 4.288093] partition entries lba: 2
+ [ 4.291835] number partition entries: 80
+ [ 4.295529] size partition entries: 80
+ [ 9.473253] piton_sd: piton_sd1
+ [ 10.099676] libphy: Fixed MDIO Bus: probed
+ [ 10.148782] NET: Registered protocol family 10
+ [ 10.183418] Segment Routing with IPv6
+ [ 10.189384] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
+ [ 10.214449] NET: Registered protocol family 17
+ [ 10.227413] Key type dns_resolver registered
+ [ 10.240561] Loading compiled-in X.509 certificates
+ [ 10.465264] EXT4-fs (piton_sd1): mounted filesystem with ordered data mode. Opts: (null)
+ [ 10.475922] VFS: Mounted root (ext4 filesystem) readonly on device 254:1.
+ [ 10.551865] devtmpfs: mounted
+ [ 10.562744] Freeing unused kernel memory: 168K
+ [ 10.567450] This architecture does not have kernel memory protection.
+ [ 10.574688] Run /sbin/init as init process
+ [ 10.578916] with arguments:
+ [ 10.582489] /sbin/init
+ [ 10.585312] with environment:
+ [ 10.588518] HOME=/
+ [ 10.591459] TERM=linux
+ [ 18.154373] systemd[1]: System time before build time, advancing clock.
+ [ 18.565415] systemd[1]: systemd 238 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIB)
+ [ 18.596359] systemd[1]: Detected architecture riscv64.
+
+ Welcome to Debian GNU/Linux buster/sid!
+
+ [ 18.797150] systemd[1]: Set hostname to <openpiton>.
+ [ 31.609244] random: systemd: uninitialized urandom read (16 bytes read)
+ [ 31.630366] systemd[1]: Listening on /dev/initctl Compatibility Named Pipe.
+ [ OK ] Listening on /dev/initctl Compatibility Named Pipe.
+ [ 31.674820] random: systemd: uninitialized urandom read (16 bytes read)
+ [ 31.806800] systemd[1]: Created slice system-serial\x2dgetty.slice.
+ [ OK ] Created slice system-serial\x2dgetty.slice.
+ [ 31.839855] random: systemd: uninitialized urandom read (16 bytes read)
+ [ 31.850670] systemd[1]: Reached target Slices.
+ [ OK ] Reached target Slices.
+ [ 32.128005] systemd[1]: Reached target Swap.
+ [ OK ] Reached target Swap.
+ [ 32.180337] systemd[1]: Listening on Journal Socket.
+ [ OK ] Listening on Journal Socket.
+ [ 32.416448] systemd[1]: Mounting Kernel Debug File System...
+ Mounting Kernel Debug File System...
+ [ 32.937934] systemd[1]: Starting Remount Root and Kernel File Systems...
+ Starting Remount Root and Kernel File Systems...
+ [ 33.117472] urandom_read: 4 callbacks suppressed
+ [ 33.117645] random: systemd: uninitialized urandom read (16 bytes read)
+ [ 33.214868] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
+ [ OK ] Started Forward Password Requests to Wall Directory Watch.
+ [ 33.366745] random: systemd: uninitialized urandom read (16 bytes read)
+ [ 33.453262] systemd[1]: Listening on Journal Socket (/dev/log).
+ [ OK ] Listening on Journal Socket (/dev/log).
+ [ 33.627020] random: systemd: uninitialized urandom read (16 bytes read)
+ [ 34.029973] systemd[1]: Starting Load Kernel Modules...
+ Starting Load Kernel Modules...
+ [ OK ] Created slice system-getty.slice.
+ [ OK ] Started Dispatch Password Requests to Console Directory Watch.
+ [ OK ] Reached target Local Encrypted Volumes.
+ [ OK ] Reached target Paths.
+ [ OK ] Reached target Remote File Systems.
+ [ OK ] Listening on udev Kernel Socket.
+ [ OK ] Listening on udev Control Socket.
+ [ OK ] Reached target Sockets.
+ Starting udev Coldplug all Devices...
+ Starting Journal Service...
+ [ 37.108761] systemd[1]: Starting Create Static Device Nodes in /dev...
+ Starting Create Static Device Nodes in /dev...
+ [ 37.941929] systemd[1]: Mounted Kernel Debug File System.
+ [ OK ] Mounted Kernel Debug File System.
+ [ 38.463855] systemd[1]: Started Remount Root and Kernel File Systems.
+ [ OK ] Started Remount Root and Kernel File Systems.
+ [ 39.614728] systemd[1]: Started Load Kernel Modules.
+ [ OK ] Started Load Kernel Modules.
+ [ 40.794332] systemd[1]: Starting Apply Kernel Variables...
+ Starting Apply Kernel Variables...
+ [ 41.928338] systemd[1]: Starting Load/Save Random Seed...
+ Starting Load/Save Random Seed...
+ [ 43.494757] systemd[1]: Started Create Static Device Nodes in /dev.
+ [ OK ] Started Create Static Device Nodes in /dev.
+ [ 44.795372] systemd[1]: Starting udev Kernel Device Manager...
+ Starting udev Kernel Device Manager...
+ [ 45.043065] systemd[1]: Reached target Local File Systems (Pre).
+ [ OK ] Reached target Local File Systems (Pre).
+ [ 45.224716] systemd[1]: Reached target Local File Systems.
+ [ OK ] Reached target Local File Systems.
+ [ 46.036491] systemd[1]: Started Apply Kernel Variables.
+ [ OK ] Started Apply Kernel Variables.
+ [ 46.947879] systemd[1]: Started Load/Save Random Seed.
+ [ OK ] Started Load/Save Random Seed.
+ [ 47.910242] systemd[1]: Starting Raise network interfaces...
+ Starting Raise network interfaces...
+ [ 48.119915] systemd[1]: Started Journal Service.
+ [ OK ] Started Journal Service.
+ Starting Flush Journal to Persistent Storage...
+ [ OK ] Started udev Kernel Device Manager.
+ [ 55.369915] systemd-journald[88]: Received request to flush runtime journal from PID 1
+ [ OK ] Started Flush Journal to Persistent Storage.
+ Starting Create Volatile Files and Directories...
+ [ OK ] Started Raise network interfaces.
+ [ OK ] Reached target Network.
+ [FAILED] Failed to start Create Volatile Files and Directories.
+ See 'systemctl status systemd-tmpfiles-setup.service' for details.
+ Starting Update UTMP about System Boot/Shutdown...
+ [FAILED] Failed to start Network Time Synchronization.
+ See 'systemctl status systemd-timesyncd.service' for details.
+ [ OK ] Reached target System Time Synchronized.
+ [ OK ] Stopped Network Time Synchronization.
+ [ OK ] Started udev Coldplug all Devices.
+ [ OK ] Found device /dev/hvc0.
+ [ OK ] Reached target System Initialization.
+ [ OK ] Reached target Basic System.
+ [ OK ] Started Regular background program processing daemon.
+ [ OK ] Started Daily Cleanup of Temporary Directories.
+ Starting Permit User Sessions...
+ [ OK ] Started Daily apt download activities.
+ [ OK ] Started Daily apt upgrade and clean activities.
+ [ OK ] Reached target Timers.
+ [ OK ] Started Permit User Sessions.
+ [ OK ] Started Serial Getty on hvc0.
+ [ OK ] Reached target Login Prompts.
+ [ OK ] Reached target Multi-User System.
+ [ OK ] Reached target Graphical Interface.
+
+ Debian GNU/Linux buster/sid openpiton hvc0
+
+ openpiton login:
diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst
new file mode 100644
index 00000000000..2d943c23be7
--- /dev/null
+++ b/doc/board/socionext/developerbox.rst
@@ -0,0 +1,87 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Introduction
+============
+
+DeveloperBox is a certified 96boards Enterprise Edition board. The board/SoC has: -
+
+* Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor motherboard
+* 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default)
+* 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots
+ (1x slots are connected via PCIe bridge chip)
+* 4 USB-3.0 ports
+* 2 SATA ports
+* 1 GbE network port
+* 1 USB-UART serial port (micro USB)
+* 64MB SPI NOR Flash
+* 8GB eMMC Flash Storage
+* 96boards LS connector
+
+The DeveloperBox schematic can be found here: -
+https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf
+
+And the other documents can be found here: -
+https://www.96boards.org/documentation/enterprise/developerbox/
+
+
+Currently, the U-Boot port supports: -
+
+* USB
+* eMMC
+* SPI-NOR
+* SATA
+* GbE
+
+The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default.
+The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as
+BL33, but no need to combine with it.
+
+Compile from source
+===================
+
+You can build U-Boot without any additinal source code.::
+
+ cd u-boot
+ export ARCH=arm64
+ export CROSS_COMPILE=aarch64-linux-gnu-
+ make SynQuacer_defconfig
+ make -j `noproc`
+
+Then, expand the binary to 1MB for preparing flash.::
+
+ cp u-boot.bin SPI_NOR_UBOOT.fd
+ truncate -s 1M SPI_NOR_UBOOT.fd
+
+Installation
+============
+
+You can install the SNI_NOR_UBOOT.fd via NOR flash writer.
+
+Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine or other mezzanine which can connect to LS-UART0 port.
+Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the board on again. The flash writer program will be started automatically; don’t forget to turn the DSW2-7 off again after flashing.
+
+*!!CAUTION!! If you failed to write the U-Boot image on wrong address, the board can be bricked. See below page if you need to recover the bricked board. See the following page for more detail*
+
+https://www.96boards.org/documentation/enterprise/developerbox/installation/board-recovery.md.html
+
+When the serial flasher is running correctly is will show the following boot messages shown via LS-UART0::
+
+
+ /*------------------------------------------*/
+ /* SC2A11 "SynQuacer" series Flash writer */
+ /* */
+ /* Version: cd254ac */
+ /* Build: 12/15/17 11:25:45 */
+ /*------------------------------------------*/
+
+ Command Input >
+
+Once the flasher tool is running we are ready flash the UEFI image::
+
+ flash rawwrite 200000 100000
+ >> Send SPI_NOR_UBOOT.fd via XMODEM (Control-A S in minicom) <<
+
+*!!NOTE!! The flasher command parameter is different from the command for board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the size 100000 (1-five-0, 1M in hex).*
+
+After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and reset the board.
+
diff --git a/doc/board/socionext/index.rst b/doc/board/socionext/index.rst
new file mode 100644
index 00000000000..4673dcc45be
--- /dev/null
+++ b/doc/board/socionext/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Socionext
+=========
+
+.. toctree::
+ :maxdepth: 2
+
+ developerbox
diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c
index 11ec98b56f9..b1d231e0f9e 100644
--- a/drivers/ata/ahci-pci.c
+++ b/drivers/ata/ahci-pci.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <ahci.h>
+#include <scsi.h>
#include <dm.h>
#include <pci.h>
@@ -28,6 +29,7 @@ static const struct udevice_id ahci_pci_ids[] = {
U_BOOT_DRIVER(ahci_pci) = {
.name = "ahci_pci",
.id = UCLASS_AHCI,
+ .ops = &scsi_ops,
.of_match = ahci_pci_ids,
.bind = ahci_pci_bind,
.probe = ahci_pci_probe,
diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c
index 9a642c1c99c..b025050e224 100644
--- a/drivers/clk/sifive/fu740-prci.c
+++ b/drivers/clk/sifive/fu740-prci.c
@@ -20,7 +20,7 @@
#include "sifive-prci.h"
#include <asm/io.h>
-int sifive_prci_fu740_pciauxclk_enable(struct __prci_clock *pc, bool enable)
+int sifive_prci_fu740_pcieauxclk_enable(struct __prci_clock *pc, bool enable)
{
struct __prci_wrpll_data *pwd = pc->pwd;
struct __prci_data *pd = pc->pd;
@@ -98,7 +98,7 @@ static const struct __prci_clock_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
};
static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = {
- .enable_clk = sifive_prci_fu740_pciauxclk_enable,
+ .enable_clk = sifive_prci_fu740_pcieauxclk_enable,
};
/* List of clock controls provided by the PRCI */
@@ -150,7 +150,7 @@ struct __prci_clock __prci_init_clocks_fu740[] = {
.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
},
[PRCI_CLK_PCIEAUX] {
- .name = "pciaux",
+ .name = "pcieaux",
.parent_name = "",
.ops = &sifive_fu740_prci_pcieaux_clk_ops,
.pwd = &__prci_pcieaux_data,
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h
index ab152cb455e..55832a55405 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h
@@ -8,6 +8,7 @@
#include "ddr3_training_ip.h"
#include "ddr3_training_ip_db.h"
+#include "mv_ddr_plat.h"
#define KILLER_PATTERN_LENGTH 32
#define EXT_ACCESS_BURST_LENGTH 8
@@ -112,9 +113,12 @@ int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type,
int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask);
int ddr3_tip_write_cs_result(u32 dev_num, u32 offset);
int ddr3_tip_reset_fifo_ptr(u32 dev_num);
-int ddr3_tip_read_pup_value(u32 dev_num, u32 pup_values[], int reg_addr, u32 mask);
-int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr, u32 mask);
-int ddr3_tip_write_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr);
+int ddr3_tip_read_adll_value(u32 dev_num,
+ u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
+ u32 reg_addr, u32 mask);
+int ddr3_tip_write_adll_value(u32 dev_num,
+ u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
+ u32 reg_addr);
int ddr3_tip_tune_training_params(u32 dev_num, struct tune_train_params *params);
#endif /* _DDR3_TRAINING_IP_FLOW_H_ */
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 57a4efb88ed..41065dd5026 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -169,6 +169,12 @@ config SYS_I2C_IMX_LPI2C
help
Add support for the NXP i.MX LPI2C driver.
+config SYS_I2C_LPC32XX
+ bool "LPC32XX I2C driver"
+ depends on ARCH_LPC32XX
+ help
+ Enable support for the LPC32xx I2C driver.
+
config SYS_I2C_MESON
bool "Amlogic Meson I2C driver"
depends on DM_I2C && ARCH_MESON
@@ -455,6 +461,13 @@ config SYS_I2C_STM32F7
_ Optional clock stretching
_ Software reset
+config SYS_I2C_SYNQUACER
+ bool "Socionext SynQuacer I2C controller"
+ depends on ARCH_SYNQUACER && DM_I2C
+ help
+ Support for Socionext Synquacer I2C controller. This I2C controller
+ will be used for RTC and LS-connector on DeveloperBox.
+
config SYS_I2C_TEGRA
bool "NVIDIA Tegra internal I2C controller"
depends on ARCH_TEGRA
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 8c9f1fcd8b9..06a1150f03d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o
+obj-$(CONFIG_SYS_I2C_SYNQUACER) += synquacer_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index f89f7955e4c..774129ad8ea 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -38,7 +38,6 @@
/* Status register values */
#define LPC32XX_I2C_STAT_TFF 0x00000400
#define LPC32XX_I2C_STAT_RFE 0x00000200
-#define LPC32XX_I2C_STAT_DRMI 0x00000008
#define LPC32XX_I2C_STAT_NAI 0x00000004
#define LPC32XX_I2C_STAT_TDI 0x00000001
@@ -283,11 +282,7 @@ static int lpc32xx_i2c_probe(struct udevice *bus)
{
struct lpc32xx_i2c_dev *dev = dev_get_plat(bus);
- /*
- * FIXME: This is not permitted
- * dev_seq(bus) = dev->index;
- */
-
+ dev->base = dev_read_addr_ptr(bus);
__i2c_init(dev->base, dev->speed, 0, dev->index);
return 0;
}
@@ -353,9 +348,15 @@ static const struct dm_i2c_ops lpc32xx_i2c_ops = {
.set_bus_speed = lpc32xx_i2c_set_bus_speed,
};
+static const struct udevice_id lpc32xx_i2c_ids[] = {
+ { .compatible = "nxp,pnx-i2c" },
+ { }
+};
+
U_BOOT_DRIVER(i2c_lpc32xx) = {
- .id = UCLASS_I2C,
.name = "i2c_lpc32xx",
+ .id = UCLASS_I2C,
+ .of_match = lpc32xx_i2c_ids,
.probe = lpc32xx_i2c_probe,
.ops = &lpc32xx_i2c_ops,
};
diff --git a/drivers/i2c/synquacer_i2c.c b/drivers/i2c/synquacer_i2c.c
new file mode 100644
index 00000000000..6672d9435e3
--- /dev/null
+++ b/drivers/i2c/synquacer_i2c.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ */
+
+#include <dm/device_compat.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <linux/types.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <clk.h>
+
+#define REG_BSR 0x0
+#define REG_BCR 0x4
+#define REG_CCR 0x8
+#define REG_ADR 0xc
+#define REG_DAR 0x10
+#define REG_CSR 0x14
+#define REG_FSR 0x18
+#define REG_BC2R 0x1c
+
+/* I2C register bit definitions */
+#define BSR_FBT BIT(0) // First Byte Transfer
+#define BSR_GCA BIT(1) // General Call Address
+#define BSR_AAS BIT(2) // Address as Slave
+#define BSR_TRX BIT(3) // Transfer/Receive
+#define BSR_LRB BIT(4) // Last Received Bit
+#define BSR_AL BIT(5) // Arbitration Lost
+#define BSR_RSC BIT(6) // Repeated Start Cond.
+#define BSR_BB BIT(7) // Bus Busy
+
+#define BCR_INT BIT(0) // Interrupt
+#define BCR_INTE BIT(1) // Interrupt Enable
+#define BCR_GCAA BIT(2) // Gen. Call Access Ack.
+#define BCR_ACK BIT(3) // Acknowledge
+#define BCR_MSS BIT(4) // Master Slave Select
+#define BCR_SCC BIT(5) // Start Condition Cont.
+#define BCR_BEIE BIT(6) // Bus Error Int Enable
+#define BCR_BER BIT(7) // Bus Error
+
+#define CCR_CS_MASK (0x1f) // CCR Clock Period Sel.
+#define CCR_EN BIT(5) // Enable
+#define CCR_FM BIT(6) // Speed Mode Select
+
+#define CSR_CS_MASK (0x3f) // CSR Clock Period Sel.
+
+#define BC2R_SCLL BIT(0) // SCL Low Drive
+#define BC2R_SDAL BIT(1) // SDA Low Drive
+#define BC2R_SCLS BIT(4) // SCL Status
+#define BC2R_SDAS BIT(5) // SDA Status
+
+/* PCLK frequency */
+#define BUS_CLK_FR(rate) (((rate) / 20000000) + 1)
+
+#define I2C_CLK_DEF 62500000
+
+/* STANDARD MODE frequency */
+#define CLK_MASTER_STD(rate) \
+ DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_SPEED_STANDARD_RATE) - 2, 2)
+/* FAST MODE frequency */
+#define CLK_MASTER_FAST(rate) \
+ DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_SPEED_FAST_RATE) - 2) * 2, 3)
+
+/* (clkrate <= 18000000) */
+/* calculate the value of CS bits in CCR register on standard mode */
+#define CCR_CS_STD_MAX_18M(rate) \
+ ((CLK_MASTER_STD(rate) - 65) \
+ & CCR_CS_MASK)
+
+/* calculate the value of CS bits in CSR register on standard mode */
+#define CSR_CS_STD_MAX_18M(rate) 0x00
+
+/* calculate the value of CS bits in CCR register on fast mode */
+#define CCR_CS_FAST_MAX_18M(rate) \
+ ((CLK_MASTER_FAST(rate) - 1) \
+ & CCR_CS_MASK)
+
+/* calculate the value of CS bits in CSR register on fast mode */
+#define CSR_CS_FAST_MAX_18M(rate) 0x00
+
+/* (clkrate > 18000000) */
+/* calculate the value of CS bits in CCR register on standard mode */
+#define CCR_CS_STD_MIN_18M(rate) \
+ ((CLK_MASTER_STD(rate) - 1) \
+ & CCR_CS_MASK)
+
+/* calculate the value of CS bits in CSR register on standard mode */
+#define CSR_CS_STD_MIN_18M(rate) \
+ (((CLK_MASTER_STD(rate) - 1) >> 5) \
+ & CSR_CS_MASK)
+
+/* calculate the value of CS bits in CCR register on fast mode */
+#define CCR_CS_FAST_MIN_18M(rate) \
+ ((CLK_MASTER_FAST(rate) - 1) \
+ & CCR_CS_MASK)
+
+/* calculate the value of CS bits in CSR register on fast mode */
+#define CSR_CS_FAST_MIN_18M(rate) \
+ (((CLK_MASTER_FAST(rate) - 1) >> 5) \
+ & CSR_CS_MASK)
+
+/* min I2C clock frequency 14M */
+#define MIN_CLK_RATE (14 * 1000000)
+/* max I2C clock frequency 200M */
+#define MAX_CLK_RATE (200 * 1000000)
+/* I2C clock frequency 18M */
+#define CLK_RATE_18M (18 * 1000000)
+
+#define SPEED_FM 400 // Fast Mode
+#define SPEED_SM 100 // Standard Mode
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct synquacer_i2c {
+ void __iomem *base;
+ unsigned long pclkrate;
+ unsigned long speed_khz;
+};
+
+static int wait_irq(struct udevice *dev)
+{
+ struct synquacer_i2c *i2c = dev_get_priv(dev);
+ int timeout = 500000;
+
+ do {
+ if (readb(i2c->base + REG_BCR) & BCR_INT)
+ return 0;
+ } while (timeout--);
+
+ pr_err("%s: timeout\n", __func__);
+ return -1;
+}
+
+static int synquacer_i2c_xfer_start(struct synquacer_i2c *i2c,
+ int addr, int read)
+{
+ u8 bsr, bcr;
+
+ writeb((addr << 1) | (read ? 1 : 0), i2c->base + REG_DAR);
+
+ bsr = readb(i2c->base + REG_BSR);
+ bcr = readb(i2c->base + REG_BCR);
+
+ if ((bsr & BSR_BB) && !(bcr & BCR_MSS))
+ return -EBUSY;
+
+ if (bsr & BSR_BB) {
+ writeb(bcr | BCR_SCC, i2c->base + REG_BCR);
+ } else {
+ if (bcr & BCR_MSS)
+ return -EAGAIN;
+ /* Start Condition + Enable Interrupts */
+ writeb(bcr | BCR_MSS | BCR_INTE | BCR_BEIE, i2c->base + REG_BCR);
+ }
+
+ udelay(100);
+ return 0;
+}
+
+static int synquacer_i2c_xfer(struct udevice *bus,
+ struct i2c_msg *msg, int nmsgs)
+{
+ struct synquacer_i2c *i2c = dev_get_priv(bus);
+ u8 bsr, bcr;
+ int idx;
+
+ for (; nmsgs > 0; nmsgs--, msg++) {
+ synquacer_i2c_xfer_start(i2c, msg->addr, msg->flags & I2C_M_RD);
+ if (wait_irq(bus))
+ return -EREMOTEIO;
+
+ bsr = readb(i2c->base + REG_BSR);
+ if (bsr & BSR_LRB) {
+ debug("%s: No ack received\n", __func__);
+ return -EREMOTEIO;
+ }
+
+ idx = 0;
+ do {
+ bsr = readb(i2c->base + REG_BSR);
+ bcr = readb(i2c->base + REG_BCR);
+ if (bcr & BCR_BER) {
+ debug("%s: Bus error detected\n", __func__);
+ return -EREMOTEIO;
+ }
+ if ((bsr & BSR_AL) || !(bcr & BCR_MSS)) {
+ debug("%s: Arbitration lost\n", __func__);
+ return -EREMOTEIO;
+ }
+
+ if (msg->flags & I2C_M_RD) {
+ bcr = BCR_MSS | BCR_INTE | BCR_BEIE;
+ if (idx < msg->len - 1)
+ bcr |= BCR_ACK;
+ writeb(bcr, i2c->base + REG_BCR);
+ if (wait_irq(bus))
+ return -EREMOTEIO;
+ bsr = readb(i2c->base + REG_BSR);
+ if (!(bsr & BSR_FBT))
+ msg->buf[idx++] = readb(i2c->base + REG_DAR);
+ } else {
+ writeb(msg->buf[idx++], i2c->base + REG_DAR);
+ bcr = BCR_MSS | BCR_INTE | BCR_BEIE;
+ writeb(bcr, i2c->base + REG_BCR);
+ if (wait_irq(bus))
+ return -EREMOTEIO;
+ bsr = readb(i2c->base + REG_BSR);
+ if (bsr & BSR_LRB) {
+ debug("%s: no ack\n", __func__);
+ return -EREMOTEIO;
+ }
+ }
+ } while (idx < msg->len);
+ }
+
+ /* Force bus state to idle, terminating any ongoing transfer */
+ writeb(0, i2c->base + REG_BCR);
+ udelay(100);
+
+ return 0;
+}
+
+static void synquacer_i2c_hw_reset(struct synquacer_i2c *i2c)
+{
+ /* Disable clock */
+ writeb(0, i2c->base + REG_CCR);
+ writeb(0, i2c->base + REG_CSR);
+
+ /* Set own Address */
+ writeb(0, i2c->base + REG_ADR);
+
+ /* Set PCLK frequency */
+ writeb(BUS_CLK_FR(i2c->pclkrate), i2c->base + REG_FSR);
+
+ /* clear IRQ (INT=0, BER=0), Interrupt Disable */
+ writeb(0, i2c->base + REG_BCR);
+ writeb(0, i2c->base + REG_BC2R);
+}
+
+static int synquacer_i2c_get_bus_speed(struct udevice *bus)
+{
+ struct synquacer_i2c *i2c = dev_get_priv(bus);
+
+ return i2c->speed_khz * 1000;
+}
+
+static int synquacer_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+ struct synquacer_i2c *i2c = dev_get_priv(bus);
+ u32 rt = i2c->pclkrate;
+ u8 ccr_cs, csr_cs;
+
+ /* Set PCLK frequency */
+ writeb(BUS_CLK_FR(i2c->pclkrate), i2c->base + REG_FSR);
+
+ if (speed >= SPEED_FM * 1000) {
+ i2c->speed_khz = SPEED_FM;
+ if (i2c->pclkrate <= CLK_RATE_18M) {
+ ccr_cs = CCR_CS_FAST_MAX_18M(rt);
+ csr_cs = CSR_CS_FAST_MAX_18M(rt);
+ } else {
+ ccr_cs = CCR_CS_FAST_MIN_18M(rt);
+ csr_cs = CSR_CS_FAST_MIN_18M(rt);
+ }
+
+ /* Set Clock and enable, Set fast mode */
+ writeb(ccr_cs | CCR_FM | CCR_EN, i2c->base + REG_CCR);
+ writeb(csr_cs, i2c->base + REG_CSR);
+ } else {
+ i2c->speed_khz = SPEED_SM;
+ if (i2c->pclkrate <= CLK_RATE_18M) {
+ ccr_cs = CCR_CS_STD_MAX_18M(rt);
+ csr_cs = CSR_CS_STD_MAX_18M(rt);
+ } else {
+ ccr_cs = CCR_CS_STD_MIN_18M(rt);
+ csr_cs = CSR_CS_STD_MIN_18M(rt);
+ }
+
+ /* Set Clock and enable, Set standard mode */
+ writeb(ccr_cs | CCR_EN, i2c->base + REG_CCR);
+ writeb(csr_cs, i2c->base + REG_CSR);
+ }
+
+ return 0;
+}
+
+static int synquacer_i2c_of_to_plat(struct udevice *bus)
+{
+ struct synquacer_i2c *priv = dev_get_priv(bus);
+ struct clk ck;
+ int ret;
+
+ ret = clk_get_by_index(bus, 0, &ck);
+ if (ret < 0) {
+ priv->pclkrate = I2C_CLK_DEF;
+ } else {
+ clk_enable(&ck);
+ priv->pclkrate = clk_get_rate(&ck);
+ }
+
+ return 0;
+}
+
+static int synquacer_i2c_probe(struct udevice *bus)
+{
+ struct synquacer_i2c *i2c = dev_get_priv(bus);
+
+ i2c->base = dev_read_addr_ptr(bus);
+ synquacer_i2c_hw_reset(i2c);
+ synquacer_i2c_set_bus_speed(bus, 400000); /* set default speed */
+ return 0;
+}
+
+static const struct dm_i2c_ops synquacer_i2c_ops = {
+ .xfer = synquacer_i2c_xfer,
+ .set_bus_speed = synquacer_i2c_set_bus_speed,
+ .get_bus_speed = synquacer_i2c_get_bus_speed,
+};
+
+static const struct udevice_id synquacer_i2c_ids[] = {
+ {
+ .compatible = "socionext,synquacer-i2c",
+ },
+ { }
+};
+
+U_BOOT_DRIVER(sni_synquacer_i2c) = {
+ .name = "sni_synquacer_i2c",
+ .id = UCLASS_I2C,
+ .of_match = synquacer_i2c_ids,
+ .of_to_plat = synquacer_i2c_of_to_plat,
+ .probe = synquacer_i2c_probe,
+ .priv_auto = sizeof(struct synquacer_i2c),
+ .ops = &synquacer_i2c_ops,
+};
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 0909f502a16..717ce5a62f4 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -561,6 +561,16 @@ config MMC_SDHCI_IPROC
If unsure, say N.
+config MMC_SDHCI_F_SDH30
+ bool "SDHCI support for Fujitsu Semiconductor F_SDH30"
+ depends on BLK && DM_MMC
+ depends on MMC_SDHCI
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ Needed by some Fujitsu SoC for MMC / SD / SDIO support.
+ If you have a controller with this interface, say Y or M here.
+ If unsure, say N.
+
config MMC_SDHCI_KONA
bool "SDHCI support on Broadcom KONA platform"
depends on MMC_SDHCI
@@ -727,6 +737,15 @@ config MMC_SUNXI_HAS_MODE_SWITCH
bool
depends on MMC_SUNXI
+config MMC_PITON
+ bool "MMC support for OpenPiton SoC"
+ depends on DM_MMC && BLK
+ help
+ This selects support for the SD host controller on OpenPiton SoC.
+ Note that this SD controller directly exposes the contents of the
+ SD card as memory mapped, so there is no manual configuration
+ required
+
config GENERIC_ATMEL_MCI
bool "Atmel Multimedia Card Interface support"
depends on DM_MMC && BLK && ARCH_AT91
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 89d6af3db30..dde6cd563ff 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -72,7 +72,9 @@ obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o
obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o
obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
+obj-$(CONFIG_MMC_PITON) += piton_mmc.o
obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o
obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o
obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o
obj-$(CONFIG_MMC_MTK) += mtk-sd.o
+obj-$(CONFIG_MMC_SDHCI_F_SDH30) += f_sdh30.o
diff --git a/drivers/mmc/f_sdh30.c b/drivers/mmc/f_sdh30.c
new file mode 100644
index 00000000000..3a85d9e348a
--- /dev/null
+++ b/drivers/mmc/f_sdh30.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Socionext F_SDH30 eMMC driver
+ * Copyright 2021 Linaro Ltd.
+ * Copyright 2021 Socionext, Inc.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <malloc.h>
+#include <sdhci.h>
+
+struct f_sdh30_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int f_sdh30_sdhci_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct f_sdh30_plat *plat = dev_get_plat(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ int ret;
+
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
+
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
+ host->mmc->priv = host;
+
+ ret = sdhci_setup_cfg(&plat->cfg, host, 200000000, 400000);
+ if (ret)
+ return ret;
+
+ upriv->mmc = host->mmc;
+
+ mmc_set_clock(host->mmc, host->mmc->cfg->f_min, MMC_CLK_ENABLE);
+
+ return sdhci_probe(dev);
+}
+
+static int f_sdh30_of_to_plat(struct udevice *dev)
+{
+ struct sdhci_host *host = dev_get_priv(dev);
+
+ host->name = strdup(dev->name);
+ host->ioaddr = dev_read_addr_ptr(dev);
+ host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
+ host->index = dev_read_u32_default(dev, "index", 0);
+
+ return 0;
+}
+
+static int f_sdh30_bind(struct udevice *dev)
+{
+ struct f_sdh30_plat *plat = dev_get_plat(dev);
+
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id f_sdh30_mmc_ids[] = {
+ { .compatible = "fujitsu,mb86s70-sdhci-3.0" },
+ { }
+};
+
+U_BOOT_DRIVER(f_sdh30_drv) = {
+ .name = "f_sdh30_sdhci",
+ .id = UCLASS_MMC,
+ .of_match = f_sdh30_mmc_ids,
+ .of_to_plat = f_sdh30_of_to_plat,
+ .ops = &sdhci_ops,
+ .bind = f_sdh30_bind,
+ .probe = f_sdh30_sdhci_probe,
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct f_sdh30_plat),
+};
diff --git a/drivers/mmc/piton_mmc.c b/drivers/mmc/piton_mmc.c
new file mode 100644
index 00000000000..9f5da6d6339
--- /dev/null
+++ b/drivers/mmc/piton_mmc.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ * Portions Copyright 2011-2019 NVIDIA Corporation
+ * Portions Copyright 2021 Tianrui Wei
+ * This file is adapted from tegra_mmc.c
+ * Tianrui Wei <tianrui-wei@outlook.com>
+ */
+
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <common.h>
+#include <div64.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/types.h>
+#include <linux/sizes.h>
+#include <log.h>
+#include <mmc.h>
+
+
+#define PITON_MMC_DUMMY_F_MAX 20000000
+#define PITON_MMC_DUMMY_F_MIN 10000000
+#define PITON_MMC_DUMMY_CAPACITY SZ_4G << 3
+#define PITON_MMC_DUMMY_B_MAX SZ_4G
+
+struct piton_mmc_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct piton_mmc_priv {
+ void __iomem *base_addr;
+};
+
+static int piton_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ if (!data)
+ return 0;
+
+ struct piton_mmc_priv *priv = dev_get_priv(dev);
+ u32 *buff, *start_addr, *write_src;
+ size_t byte_cnt, start_block;
+
+ buff = (u32 *)data->dest;
+ write_src = (u32 *)data->src;
+ start_block = cmd->cmdarg;
+ start_addr = priv->base_addr + start_block;
+
+ /* if there is a read */
+ for (byte_cnt = data->blocks * data->blocksize; byte_cnt;
+ byte_cnt -= sizeof(u32)) {
+ if (data->flags & MMC_DATA_READ) {
+ *buff++ = readl(start_addr++);
+ }
+ else if (data->flags & MMC_DATA_WRITE) {
+ writel(*write_src++,start_addr++);
+ }
+ }
+ return 0;
+}
+
+static int piton_mmc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct piton_mmc_priv *priv = dev_get_priv(dev);
+ struct piton_mmc_plat *plat = dev_get_plat(dev);
+ struct mmc_config *cfg;
+ struct mmc *mmc;
+ struct blk_desc *bdesc;
+
+ priv->base_addr = (void *)dev_read_addr(dev);
+ cfg = &plat->cfg;
+ cfg->name = "PITON MMC";
+ cfg->host_caps = MMC_MODE_8BIT;
+ cfg->f_max = PITON_MMC_DUMMY_F_MAX;
+ cfg->f_min = PITON_MMC_DUMMY_F_MIN;
+ cfg->voltages = MMC_VDD_21_22;
+
+ mmc = &plat->mmc;
+ mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
+ mmc->capacity_user = PITON_MMC_DUMMY_CAPACITY;
+ mmc->capacity_user *= mmc->read_bl_len;
+ mmc->capacity_boot = 0;
+ mmc->capacity_rpmb = 0;
+ for (int i = 0; i < 4; i++)
+ mmc->capacity_gp[i] = 0;
+ mmc->capacity = PITON_MMC_DUMMY_CAPACITY;
+ mmc->has_init = 1;
+
+ bdesc = mmc_get_blk_desc(mmc);
+ bdesc->lun = 0;
+ bdesc->hwpart = 0;
+ bdesc->type = 0;
+ bdesc->blksz = mmc->read_bl_len;
+ bdesc->log2blksz = LOG2(bdesc->blksz);
+ bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
+
+ return 0;
+}
+
+static int piton_mmc_getcd(struct udevice *dev)
+{
+ return 1;
+}
+
+static const struct dm_mmc_ops piton_mmc_ops = {
+ .send_cmd = piton_mmc_send_cmd,
+ .get_cd = piton_mmc_getcd,
+};
+
+static int piton_mmc_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct piton_mmc_plat *plat = dev_get_plat(dev);
+ struct mmc_config *cfg = &plat->cfg;
+
+ cfg->name = dev->name;
+ upriv->mmc = &plat->mmc;
+ upriv->mmc->has_init = 1;
+ upriv->mmc->capacity = PITON_MMC_DUMMY_CAPACITY;
+ upriv->mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
+ return 0;
+}
+
+static int piton_mmc_bind(struct udevice *dev)
+{
+ struct piton_mmc_plat *plat = dev_get_plat(dev);
+ struct mmc_config *cfg = &plat->cfg;
+
+ cfg->name = dev->name;
+ cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT;
+ cfg->voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
+ cfg->f_min = PITON_MMC_DUMMY_F_MIN;
+ cfg->f_max = PITON_MMC_DUMMY_F_MAX;
+ cfg->b_max = MMC_MAX_BLOCK_LEN;
+
+ return mmc_bind(dev, &plat->mmc, cfg);
+}
+
+static const struct udevice_id piton_mmc_ids[] = {
+ {.compatible = "openpiton,piton-mmc"},
+ {/* sentinel */}
+};
+
+U_BOOT_DRIVER(piton_mmc_drv) = {
+ .name = "piton_mmc",
+ .id = UCLASS_MMC,
+ .of_match = piton_mmc_ids,
+ .of_to_plat = piton_mmc_ofdata_to_platdata,
+ .bind = piton_mmc_bind,
+ .probe = piton_mmc_probe,
+ .ops = &piton_mmc_ops,
+ .plat_auto = sizeof(struct piton_mmc_plat),
+ .priv_auto = sizeof(struct piton_mmc_priv),
+};
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 9fc28b149d0..2a7c8f9a7ff 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -548,21 +548,14 @@ config SMC911X_BASE
of the device (I/O space)
endif #DM_ETH
-choice
- prompt "SMC911X bus width"
- default SMC911X_16_BIT
-
config SMC911X_32_BIT
- bool "Enable 32-bit interface"
-
-config SMC911X_16_BIT
- bool "Enable 16-bit interface"
+ bool "Enable SMC911X 32-bit interface"
+ default n
help
- Define this if data bus is 16 bits. If your processor
- automatically converts one 32 bit word to two 16 bit
- words you may also try CONFIG_SMC911X_32_BIT.
+ Define this if data bus is 32 bits. If your processor use a
+ narrower 16 bit bus or cannot convert one 32 bit word to two 16 bit
+ words, leave this to "n".
-endchoice
endif #SMC911X
config SUN7I_GMAC
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index b012bed517d..f048e9d5851 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -238,8 +238,6 @@ struct eqos_tegra186_regs {
#define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
/* Descriptors */
-/* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
-#define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
#define EQOS_DESCRIPTORS_TX 4
#define EQOS_DESCRIPTORS_RX 4
#define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
index f6fc7801b95..566cdc7e546 100644
--- a/drivers/net/fsl_enetc.c
+++ b/drivers/net/fsl_enetc.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ENETC ethernet controller driver
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2021 NXP
*/
#include <common.h>
@@ -178,21 +178,43 @@ static int enetc_init_sgmii(struct udevice *dev)
}
/* set up MAC for RGMII */
-static int enetc_init_rgmii(struct udevice *dev)
+static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev)
{
struct enetc_priv *priv = dev_get_priv(dev);
- u32 if_mode;
+ u32 old_val, val;
- /* enable RGMII AN */
- if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
- if_mode |= ENETC_PM_IF_MODE_AN_ENA;
- enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
+ old_val = val = enetc_read_port(priv, ENETC_PM_IF_MODE);
- return 0;
+ /* disable unreliable RGMII in-band signaling and force the MAC into
+ * the speed negotiated by the PHY.
+ */
+ val &= ~ENETC_PM_IF_MODE_AN_ENA;
+
+ if (phydev->speed == SPEED_1000) {
+ val &= ~ENETC_PM_IFM_SSP_MASK;
+ val |= ENETC_PM_IFM_SSP_1000;
+ } else if (phydev->speed == SPEED_100) {
+ val &= ~ENETC_PM_IFM_SSP_MASK;
+ val |= ENETC_PM_IFM_SSP_100;
+ } else if (phydev->speed == SPEED_10) {
+ val &= ~ENETC_PM_IFM_SSP_MASK;
+ val |= ENETC_PM_IFM_SSP_10;
+ }
+
+ if (phydev->duplex == DUPLEX_FULL)
+ val |= ENETC_PM_IFM_FULL_DPX;
+ else
+ val &= ~ENETC_PM_IFM_FULL_DPX;
+
+ if (val == old_val)
+ return;
+
+ enetc_write_port(priv, ENETC_PM_IF_MODE, val);
}
/* set up MAC configuration for the given interface type */
-static void enetc_setup_mac_iface(struct udevice *dev)
+static void enetc_setup_mac_iface(struct udevice *dev,
+ struct phy_device *phydev)
{
struct enetc_priv *priv = dev_get_priv(dev);
u32 if_mode;
@@ -202,7 +224,7 @@ static void enetc_setup_mac_iface(struct udevice *dev)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
- enetc_init_rgmii(dev);
+ enetc_init_rgmii(dev, phydev);
break;
case PHY_INTERFACE_MODE_XGMII:
case PHY_INTERFACE_MODE_USXGMII:
@@ -281,21 +303,20 @@ static void enetc_start_pcs(struct udevice *dev)
}
/* Configure the actual/external ethernet PHY, if one is found */
-static void enetc_config_phy(struct udevice *dev)
+static int enetc_config_phy(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
int supported;
priv->phy = dm_eth_phy_connect(dev);
-
if (!priv->phy)
- return;
+ return -ENODEV;
supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
priv->phy->supported &= supported;
priv->phy->advertising &= supported;
- phy_config(priv->phy);
+ return phy_config(priv->phy);
}
/*
@@ -335,9 +356,8 @@ static int enetc_probe(struct udevice *dev)
dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
enetc_start_pcs(dev);
- enetc_config_phy(dev);
- return 0;
+ return enetc_config_phy(dev);
}
/*
@@ -548,12 +568,9 @@ static int enetc_start(struct udevice *dev)
enetc_setup_tx_bdr(dev);
enetc_setup_rx_bdr(dev);
- enetc_setup_mac_iface(dev);
-
- if (priv->phy)
- phy_startup(priv->phy);
+ enetc_setup_mac_iface(dev, priv->phy);
- return 0;
+ return phy_startup(priv->phy);
}
/*
diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h
index 110c1d78fbc..69f2f4aaff1 100644
--- a/drivers/net/fsl_enetc.h
+++ b/drivers/net/fsl_enetc.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* ENETC ethernet controller driver
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2021 NXP
*/
#ifndef _ENETC_H
@@ -77,6 +77,11 @@ enum enetc_bdr_type {TX, RX};
#define ENETC_PM_IF_MODE 0x8300
#define ENETC_PM_IF_MODE_RG BIT(2)
#define ENETC_PM_IF_MODE_AN_ENA BIT(15)
+#define ENETC_PM_IFM_SSP_MASK GENMASK(14, 13)
+#define ENETC_PM_IFM_SSP_1000 (2 << 13)
+#define ENETC_PM_IFM_SSP_100 (0 << 13)
+#define ENETC_PM_IFM_SSP_10 (1 << 13)
+#define ENETC_PM_IFM_FULL_DPX BIT(12)
#define ENETC_PM_IF_IFMODE_MASK GENMASK(1, 0)
/* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 070ffa82cb9..405bf767530 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -197,6 +197,12 @@ config PHY_MSCC
config PHY_NATSEMI
bool "National Semiconductor Ethernet PHYs support"
+config PHY_NXP_C45_TJA11XX
+ tristate "NXP C45 TJA11XX PHYs"
+ help
+ Enable support for NXP C45 TJA11XX PHYs.
+ Currently supports only the TJA1103 PHY.
+
config PHY_REALTEK
bool "Realtek Ethernet PHYs support"
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index e967f822016..218b8c7669b 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o
obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
+obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o
obj-$(CONFIG_PHY_REALTEK) += realtek.o
obj-$(CONFIG_PHY_SMSC) += smsc.o
obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c
new file mode 100644
index 00000000000..f86e31f0d9e
--- /dev/null
+++ b/drivers/net/phy/nxp-c45-tja11xx.c
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NXP C45 PHY driver
+ *
+ * Copyright 2021 NXP
+ * Author: Radu Pirea <radu-nicolae.pirea@oss.nxp.com>
+ */
+#include <common.h>
+#include <dm.h>
+#include <dm/devres.h>
+#include <linux/delay.h>
+#include <linux/math64.h>
+#include <linux/mdio.h>
+#include <phy.h>
+
+#define PHY_ID_TJA_1103 0x001BB010
+
+#define VEND1_DEVICE_CONTROL 0x0040
+#define DEVICE_CONTROL_RESET BIT(15)
+#define DEVICE_CONTROL_CONFIG_GLOBAL_EN BIT(14)
+#define DEVICE_CONTROL_CONFIG_ALL_EN BIT(13)
+
+#define VEND1_PORT_CONTROL 0x8040
+#define PORT_CONTROL_EN BIT(14)
+
+#define VEND1_PHY_CONTROL 0x8100
+#define PHY_CONFIG_EN BIT(14)
+#define PHY_START_OP BIT(0)
+
+#define VEND1_PHY_CONFIG 0x8108
+#define PHY_CONFIG_AUTO BIT(0)
+
+#define VEND1_PORT_INFRA_CONTROL 0xAC00
+#define PORT_INFRA_CONTROL_EN BIT(14)
+
+#define VEND1_RXID 0xAFCC
+#define VEND1_TXID 0xAFCD
+#define ID_ENABLE BIT(15)
+
+#define VEND1_ABILITIES 0xAFC4
+#define RGMII_ID_ABILITY BIT(15)
+#define RGMII_ABILITY BIT(14)
+#define RMII_ABILITY BIT(10)
+#define REVMII_ABILITY BIT(9)
+#define MII_ABILITY BIT(8)
+#define SGMII_ABILITY BIT(0)
+
+#define VEND1_MII_BASIC_CONFIG 0xAFC6
+#define MII_BASIC_CONFIG_REV BIT(8)
+#define MII_BASIC_CONFIG_SGMII 0x9
+#define MII_BASIC_CONFIG_RGMII 0x7
+#define MII_BASIC_CONFIG_RMII 0x5
+#define MII_BASIC_CONFIG_MII 0x4
+
+#define RGMII_PERIOD_PS 8000U
+#define PS_PER_DEGREE div_u64(RGMII_PERIOD_PS, 360)
+#define MIN_ID_PS 1644U
+#define MAX_ID_PS 2260U
+#define DEFAULT_ID_PS 2000U
+
+#define RESET_DELAY_MS 25
+#define CONF_EN_DELAY_US 450
+
+struct nxp_c45_phy {
+ u32 tx_delay;
+ u32 rx_delay;
+};
+
+static int nxp_c45_soft_reset(struct phy_device *phydev)
+{
+ int tries = 10, ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL,
+ DEVICE_CONTROL_RESET);
+ if (ret)
+ return ret;
+
+ do {
+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
+ VEND1_DEVICE_CONTROL);
+ if (!(ret & DEVICE_CONTROL_RESET))
+ return 0;
+ mdelay(RESET_DELAY_MS);
+ } while (tries--);
+
+ return -EIO;
+}
+
+static int nxp_c45_start_op(struct phy_device *phydev)
+{
+ return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL,
+ PHY_START_OP);
+}
+
+static int nxp_c45_config_enable(struct phy_device *phydev)
+{
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL,
+ DEVICE_CONTROL_CONFIG_GLOBAL_EN |
+ DEVICE_CONTROL_CONFIG_ALL_EN);
+ udelay(CONF_EN_DELAY_US);
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL,
+ PORT_CONTROL_EN);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL,
+ PHY_CONFIG_EN);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_INFRA_CONTROL,
+ PORT_INFRA_CONTROL_EN);
+
+ return 0;
+}
+
+static u64 nxp_c45_get_phase_shift(u64 phase_offset_raw)
+{
+ /* The delay in degree phase is 73.8 + phase_offset_raw * 0.9.
+ * To avoid floating point operations we'll multiply by 10
+ * and get 1 decimal point precision.
+ */
+ phase_offset_raw *= 10;
+ phase_offset_raw -= 738;
+ return div_u64(phase_offset_raw, 9);
+}
+
+static void nxp_c45_disable_delays(struct phy_device *phydev)
+{
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, 0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, 0);
+}
+
+static int nxp_c45_check_delay(struct phy_device *phydev, u32 delay)
+{
+ if (delay < MIN_ID_PS) {
+ pr_err("%s: delay value smaller than %u\n",
+ phydev->drv->name, MIN_ID_PS);
+ return -EINVAL;
+ }
+
+ if (delay > MAX_ID_PS) {
+ pr_err("%s: delay value higher than %u\n",
+ phydev->drv->name, MAX_ID_PS);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int nxp_c45_get_delays(struct phy_device *phydev)
+{
+ struct nxp_c45_phy *priv = phydev->priv;
+ int ret;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
+ ret = dev_read_u32(phydev->dev, "tx-internal-delay-ps",
+ &priv->tx_delay);
+ if (ret)
+ priv->tx_delay = DEFAULT_ID_PS;
+
+ ret = nxp_c45_check_delay(phydev, priv->tx_delay);
+ if (ret) {
+ pr_err("%s: tx-internal-delay-ps invalid value\n",
+ phydev->drv->name);
+ return ret;
+ }
+ }
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
+ ret = dev_read_u32(phydev->dev, "rx-internal-delay-ps",
+ &priv->rx_delay);
+ if (ret)
+ priv->rx_delay = DEFAULT_ID_PS;
+
+ ret = nxp_c45_check_delay(phydev, priv->rx_delay);
+ if (ret) {
+ pr_err("%s: rx-internal-delay-ps invalid value\n",
+ phydev->drv->name);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static void nxp_c45_set_delays(struct phy_device *phydev)
+{
+ struct nxp_c45_phy *priv = phydev->priv;
+ u64 tx_delay = priv->tx_delay;
+ u64 rx_delay = priv->rx_delay;
+ u64 degree;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
+ degree = div_u64(tx_delay, PS_PER_DEGREE);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID,
+ ID_ENABLE | nxp_c45_get_phase_shift(degree));
+ } else {
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, 0);
+ }
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
+ degree = div_u64(rx_delay, PS_PER_DEGREE);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID,
+ ID_ENABLE | nxp_c45_get_phase_shift(degree));
+ } else {
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, 0);
+ }
+}
+
+static int nxp_c45_set_phy_mode(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_ABILITIES);
+ pr_debug("%s: Clause 45 managed PHY abilities 0x%x\n",
+ phydev->drv->name, ret);
+
+ switch (phydev->interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ if (!(ret & RGMII_ABILITY)) {
+ pr_err("%s: rgmii mode not supported\n",
+ phydev->drv->name);
+ return -EINVAL;
+ }
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
+ MII_BASIC_CONFIG_RGMII);
+ nxp_c45_disable_delays(phydev);
+ break;
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ if (!(ret & RGMII_ID_ABILITY)) {
+ pr_err("%s: rgmii-id, rgmii-txid, rgmii-rxid modes are not supported\n",
+ phydev->drv->name);
+ return -EINVAL;
+ }
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
+ MII_BASIC_CONFIG_RGMII);
+ ret = nxp_c45_get_delays(phydev);
+ if (ret)
+ return ret;
+
+ nxp_c45_set_delays(phydev);
+ break;
+ case PHY_INTERFACE_MODE_MII:
+ if (!(ret & MII_ABILITY)) {
+ pr_err("%s: mii mode not supported\n",
+ phydev->drv->name);
+ return -EINVAL;
+ }
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
+ MII_BASIC_CONFIG_MII);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ if (!(ret & RMII_ABILITY)) {
+ pr_err("%s: rmii mode not supported\n",
+ phydev->drv->name);
+ return -EINVAL;
+ }
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
+ MII_BASIC_CONFIG_RMII);
+ break;
+ case PHY_INTERFACE_MODE_SGMII:
+ if (!(ret & SGMII_ABILITY)) {
+ pr_err("%s: sgmii mode not supported\n",
+ phydev->drv->name);
+ return -EINVAL;
+ }
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
+ MII_BASIC_CONFIG_SGMII);
+ break;
+ case PHY_INTERFACE_MODE_INTERNAL:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int nxp_c45_config(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = nxp_c45_soft_reset(phydev);
+ if (ret)
+ return ret;
+
+ ret = nxp_c45_config_enable(phydev);
+ if (ret) {
+ pr_err("%s: Failed to enable config\n", phydev->drv->name);
+ return ret;
+ }
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG,
+ PHY_CONFIG_AUTO);
+
+ ret = nxp_c45_set_phy_mode(phydev);
+ if (ret) {
+ pr_err("%s: Failed to set phy mode\n", phydev->drv->name);
+ return ret;
+ }
+
+ phydev->autoneg = AUTONEG_DISABLE;
+
+ return nxp_c45_start_op(phydev);
+}
+
+static int nxp_c45_startup(struct phy_device *phydev)
+{
+ u32 reg;
+
+ reg = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);
+ phydev->link = !!(reg & MDIO_STAT1_LSTATUS);
+ phydev->speed = SPEED_100;
+ phydev->duplex = DUPLEX_FULL;
+ return 0;
+}
+
+static int nxp_c45_probe(struct phy_device *phydev)
+{
+ struct nxp_c45_phy *priv;
+
+ priv = devm_kzalloc(phydev->priv, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ phydev->priv = priv;
+
+ return 0;
+}
+
+static struct phy_driver nxp_tja11xx = {
+ .name = "NXP C45 TJA1103",
+ .uid = PHY_ID_TJA_1103,
+ .mask = 0xfffff0,
+ .features = PHY_100BT1_FEATURES,
+ .probe = &nxp_c45_probe,
+ .config = &nxp_c45_config,
+ .startup = &nxp_c45_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+int phy_nxp_tja11xx_init(void)
+{
+ phy_register(&nxp_tja11xx);
+ return 0;
+}
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index ed197fa46d7..69acb694606 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -529,6 +529,9 @@ int phy_init(void)
#ifdef CONFIG_PHY_NATSEMI
phy_natsemi_init();
#endif
+#ifdef CONFIG_NXP_C45_TJA11XX_PHY
+ phy_nxp_tja11xx_init();
+#endif
#ifdef CONFIG_PHY_REALTEK
phy_realtek_init();
#endif
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 7b79831c281..3afebee4402 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -28,6 +28,7 @@ struct smc911x_priv {
phys_addr_t iobase;
const struct chip_id *chipid;
unsigned char enetaddr[6];
+ bool use_32_bit_io;
};
static const struct chip_id chip_ids[] = {
@@ -48,36 +49,24 @@ static const struct chip_id chip_ids[] = {
#define DRIVERNAME "smc911x"
-#if defined (CONFIG_SMC911X_32_BIT) && \
- defined (CONFIG_SMC911X_16_BIT)
-#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
- CONFIG_SMC911X_16_BIT shall be set"
-#endif
-
-#if defined (CONFIG_SMC911X_32_BIT)
static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
{
- return readl(priv->iobase + offset);
-}
+ if (priv->use_32_bit_io)
+ return readl(priv->iobase + offset);
-static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
-{
- writel(val, priv->iobase + offset);
-}
-#elif defined (CONFIG_SMC911X_16_BIT)
-static u32 smc911x_reg_read(struct smc911x_priv *priv, u32 offset)
-{
return (readw(priv->iobase + offset) & 0xffff) |
(readw(priv->iobase + offset + 2) << 16);
}
+
static void smc911x_reg_write(struct smc911x_priv *priv, u32 offset, u32 val)
{
- writew(val & 0xffff, priv->iobase + offset);
- writew(val >> 16, priv->iobase + offset + 2);
+ if (priv->use_32_bit_io) {
+ writel(val, priv->iobase + offset);
+ } else {
+ writew(val & 0xffff, priv->iobase + offset);
+ writew(val >> 16, priv->iobase + offset + 2);
+ }
}
-#else
-#error "SMC911X: undefined bus width"
-#endif /* CONFIG_SMC911X_16_BIT */
static u32 smc911x_get_mac_csr(struct smc911x_priv *priv, u8 reg)
{
@@ -501,6 +490,8 @@ int smc911x_initialize(u8 dev_num, int base_addr)
priv->iobase = base_addr;
priv->dev.iobase = base_addr;
+ priv->use_32_bit_io = CONFIG_IS_ENABLED(SMC911X_32_BIT);
+
/* Try to detect chip. Will fail if not present. */
ret = smc911x_detect_chip(priv);
if (ret) {
@@ -611,10 +602,18 @@ static int smc911x_of_to_plat(struct udevice *dev)
{
struct smc911x_priv *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_plat(dev);
+ u32 io_width;
+ int ret;
pdata->iobase = dev_read_addr(dev);
priv->iobase = pdata->iobase;
+ ret = dev_read_u32(dev, "reg-io-width", &io_width);
+ if (!ret)
+ priv->use_32_bit_io = (io_width == 4);
+ else
+ priv->use_32_bit_io = CONFIG_IS_ENABLED(SMC911X_32_BIT);
+
return 0;
}
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index b2b7b253f84..782179eb0f6 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -81,6 +81,18 @@ config PCIE_ECAM_GENERIC
Say Y here if you want to enable support for generic ECAM-based
PCIe host controllers, such as the one emulated by QEMU.
+config PCIE_ECAM_SYNQUACER
+ bool "SynQuacer ECAM-based PCI host controller support"
+ default n
+ depends on DM_PCI
+ select PCI_INIT_R
+ select PCI_REGION_MULTI_ENTRY
+ help
+ Say Y here if you want to enable support for Socionext
+ SynQuacer SoC's ECAM-based PCIe host controllers.
+ Note that this must be configured when boot because Linux driver
+ expects the PCIe RC has been configured in the bootloader.
+
config PCI_PHYTIUM
bool "Phytium PCIe support"
depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c742bb2c94d..6568dc9a088 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -16,6 +16,7 @@ endif
obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o
obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
+obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o
obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 0bd604d061d..cb9aa818359 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -552,6 +552,9 @@ int pci_auto_config_devices(struct udevice *bus)
max_bus = ret;
sub_bus = max(sub_bus, max_bus);
+ if (dev_get_parent(dev) == bus)
+ continue;
+
pplat = dev_get_parent_plat(dev);
if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
set_vga_bridge_bits(dev);
diff --git a/drivers/pci/pcie_ecam_synquacer.c b/drivers/pci/pcie_ecam_synquacer.c
new file mode 100644
index 00000000000..c6e7c59f8a6
--- /dev/null
+++ b/drivers/pci/pcie_ecam_synquacer.c
@@ -0,0 +1,600 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SynQuacer PCIE host driver
+ *
+ * Based on drivers/pci/pcie_ecam_generic.c
+ *
+ * Copyright (C) 2016 Imagination Technologies
+ * Copyright (C) 2021 Linaro Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include <log.h>
+
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+/* iATU registers */
+#define IATU_VIEWPORT_OFF 0x900
+#define IATU_VIEWPORT_INBOUND BIT(31)
+#define IATU_VIEWPORT_OUTBOUND 0
+#define IATU_VIEWPORT_REGION_INDEX(idx) ((idx) & 7)
+
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH BIT(12)
+
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT(31)
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE BIT(28)
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT 0xF
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT 0xFF
+
+#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C
+#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910
+#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914
+#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918
+#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C
+
+/* Clock and resets */
+#define CORE_CONTROL 0x000
+#define APP_LTSSM_ENABLE BIT(4)
+#define DEVICE_TYPE (BIT(3) | BIT(2) | BIT(1) | BIT(0))
+
+#define AXI_CLK_STOP 0x004
+#define DBI_ACLK_STOP BIT(8)
+#define SLV_ACLK_STOP BIT(4)
+#define MSTR_ACLK_STOP BIT(0)
+#define DBI_CSYSREQ_REG BIT(9)
+#define SLV_CSYSREQ_REG BIT(5)
+#define MSTR_CSYSREQ_REG BIT(1)
+
+#define RESET_CONTROL_1 0x00C
+#define PERST_N_O_REG BIT(5)
+#define PERST_N_I_REG BIT(4)
+#define BUTTON_RST_N_REG BIT(1)
+#define PWUP_RST_N_REG BIT(0)
+
+#define RESET_CONTROL_2 0x010
+
+#define RESET_SELECT_1 0x014
+#define SQU_RST_SEL BIT(29)
+#define PHY_RST_SEL BIT(28)
+#define PWR_RST_SEL BIT(24)
+#define STI_RST_SEL BIT(20)
+#define N_STI_RST_SEL BIT(16)
+#define CORE_RST_SEL BIT(12)
+#define PERST_SEL BIT(4)
+#define BUTTON_RST_SEL BIT(1)
+#define PWUP_RST_SEL BIT(0)
+
+#define RESET_SELECT_2 0x018
+#define DBI_ARST_SEL BIT(8)
+#define SLV_ARST_SEL BIT(4)
+#define MSTR_ARST_SEL BIT(0)
+
+#define EM_CONTROL 0x030
+#define PRE_DET_STT_REG BIT(4)
+
+#define EM_SELECT 0x034
+#define PRE_DET_STT_SEL BIT(4)
+
+#define PM_CONTROL_2 0x050
+#define SYS_AUX_PWR_DET BIT(8)
+
+#define PHY_CONFIG_COM_6 0x114
+#define PIPE_PORT_SEL GENMASK(1, 0)
+
+#define LINK_MONITOR 0x210
+#define SMLH_LINK_UP BIT(0)
+
+#define LINK_CAPABILITIES_REG 0x07C
+#define PCIE_CAP_MAX_LINK_WIDTH GENMASK(7, 4)
+#define PCIE_CAP_MAX_LINK_SPEED GENMASK(3, 0)
+
+#define LINK_CONTROL_LINK_STATUS_REG 0x080
+#define PCIE_CAP_NEGO_LINK_WIDTH GENMASK(23, 20)
+#define PCIE_CAP_LINK_SPEED GENMASK(19, 16)
+
+#define TYPE1_CLASS_CODE_REV_ID_REG 0x008
+#define BASE_CLASS_CODE 0xFF000000
+#define BASE_CLASS_CODE_VALUE 0x06
+#define SUBCLASS_CODE 0x00FF0000
+#define SUBCLASS_CODE_VALUE 0x04
+#define PROGRAM_INTERFACE 0x0000FF00
+#define PROGRAM_INTERFACE_VALUE 0x00
+
+#define GEN2_CONTROL_OFF 0x80c
+#define DIRECT_SPEED_CHANGE BIT(17)
+
+#define MISC_CONTROL_1_OFF 0x8BC
+#define DBI_RO_WR_EN BIT(0)
+
+static void or_writel(void *base, u32 offs, u32 val)
+{
+ writel(readl(base + offs) | val, base + offs);
+}
+
+static void masked_writel(void *base, u32 offs, u32 mask, u32 val)
+{
+ u32 data;
+ int shift = ffs(mask); /* Note that ffs() returns 1 for 0x1 */
+
+ if (val && shift > 1)
+ val <<= shift - 1;
+
+ if (mask != ~0)
+ data = (readl(base + offs) & ~mask) | val;
+ else
+ data = val;
+
+ writel(data, base + offs);
+}
+
+static u32 masked_readl(void *base, u32 offs, u32 mask)
+{
+ u32 data;
+ int shift = ffs(mask); /* Note that ffs() returns 1 for 0x1 */
+
+ data = readl(base + offs);
+
+ if (mask != ~0)
+ data &= mask;
+ if (shift > 1)
+ data >>= shift - 1;
+
+ return data;
+}
+
+/*
+ * Since SynQuacer's PCIe RC is expected to be initialized in the
+ * firmware (including U-Boot), devicetree doesn't have control
+ * blocks.
+ *
+ * Thus, this will initialize the PCIe RC with fixed addresses.
+ */
+
+#define SYNQUACER_PCI_SEG0_CONFIG_BASE 0x60000000
+#define SYNQUACER_PCI_SEG0_CONFIG_SIZE 0x07f00000
+#define SYNQUACER_PCI_SEG0_DBI_BASE 0x583d0000
+#define SYNQUACER_PCI_SEG0_EXS_BASE 0x58390000
+
+#define SYNQUACER_PCI_SEG1_CONFIG_BASE 0x70000000
+#define SYNQUACER_PCI_SEG1_CONFIG_SIZE 0x07f00000
+#define SYNQUACER_PCI_SEG1_DBI_BASE 0x583c0000
+#define SYNQUACER_PCI_SEG1_EXS_BASE 0x58380000
+
+#define SIZE_16KB 0x00004000
+#define SIZE_64KB 0x00010000
+#define SIZE_1MB 0x00100000
+
+#define SYNQUACER_PCI_DBI_SIZE SIZE_16KB
+#define SYNQUACER_PCI_EXS_SIZE SIZE_64KB
+
+#define NUM_SQ_PCI_RC 2
+
+static const struct synquacer_pcie_base {
+ phys_addr_t cfg_base;
+ phys_addr_t dbi_base;
+ phys_addr_t exs_base;
+} synquacer_pci_bases[NUM_SQ_PCI_RC] = {
+ {
+ .cfg_base = SYNQUACER_PCI_SEG0_CONFIG_BASE,
+ .dbi_base = SYNQUACER_PCI_SEG0_DBI_BASE,
+ .exs_base = SYNQUACER_PCI_SEG0_EXS_BASE,
+ }, {
+ .cfg_base = SYNQUACER_PCI_SEG1_CONFIG_BASE,
+ .dbi_base = SYNQUACER_PCI_SEG1_DBI_BASE,
+ .exs_base = SYNQUACER_PCI_SEG1_EXS_BASE,
+ },
+};
+
+/**
+ * struct synquacer_ecam_pcie - synquacer_ecam PCIe controller state
+ * @cfg_base: The base address of memory mapped configuration space
+ */
+struct synquacer_ecam_pcie {
+ void *cfg_base;
+ pci_size_t size;
+ void *dbi_base;
+ void *exs_base;
+ int first_busno;
+
+ struct pci_region mem;
+ struct pci_region io;
+ struct pci_region mem64;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * pci_synquacer_ecam_conf_address() - Calculate the address of a config access
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @paddress: Pointer to the pointer to write the calculates address to
+ *
+ * Calculates the address that should be accessed to perform a PCIe
+ * configuration space access for a given device identified by the PCIe
+ * controller device @pcie and the bus, device & function numbers in @bdf. If
+ * access to the device is not valid then the function will return an error
+ * code. Otherwise the address to access will be written to the pointer pointed
+ * to by @paddress.
+ */
+static int pci_synquacer_ecam_conf_address(const struct udevice *bus,
+ pci_dev_t bdf, uint offset,
+ void **paddress)
+{
+ struct synquacer_ecam_pcie *pcie = dev_get_priv(bus);
+ void *addr;
+
+ addr = pcie->cfg_base;
+ addr += (PCI_BUS(bdf) - pcie->first_busno) << 20;
+ addr += PCI_DEV(bdf) << 15;
+ addr += PCI_FUNC(bdf) << 12;
+ addr += offset;
+ *paddress = addr;
+
+ return 0;
+}
+
+static bool pci_synquacer_ecam_addr_valid(const struct udevice *bus,
+ pci_dev_t bdf)
+{
+ struct synquacer_ecam_pcie *pcie = dev_get_priv(bus);
+ int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
+
+ /*
+ * The Synopsys DesignWare PCIe controller in ECAM mode will not filter
+ * type 0 config TLPs sent to devices 1 and up on its downstream port,
+ * resulting in devices appearing multiple times on bus 0 unless we
+ * filter out those accesses here.
+ */
+ if (PCI_BUS(bdf) == pcie->first_busno && PCI_DEV(bdf) > 0)
+ return false;
+
+ return (PCI_BUS(bdf) >= pcie->first_busno &&
+ PCI_BUS(bdf) < pcie->first_busno + num_buses);
+}
+
+/**
+ * pci_synquacer_ecam_read_config() - Read from configuration space
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @valuep: A pointer at which to store the read value
+ * @size: Indicates the size of access to perform
+ *
+ * Read a value of size @size from offset @offset within the configuration
+ * space of the device identified by the bus, device & function numbers in @bdf
+ * on the PCI bus @bus.
+ */
+static int pci_synquacer_ecam_read_config(const struct udevice *bus,
+ pci_dev_t bdf, uint offset,
+ ulong *valuep, enum pci_size_t size)
+{
+ if (!pci_synquacer_ecam_addr_valid(bus, bdf)) {
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
+ return pci_generic_mmap_read_config(bus, pci_synquacer_ecam_conf_address,
+ bdf, offset, valuep, size);
+}
+
+/**
+ * pci_synquacer_ecam_write_config() - Write to configuration space
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @value: The value to write
+ * @size: Indicates the size of access to perform
+ *
+ * Write the value @value of size @size from offset @offset within the
+ * configuration space of the device identified by the bus, device & function
+ * numbers in @bdf on the PCI bus @bus.
+ */
+static int pci_synquacer_ecam_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ if (!pci_synquacer_ecam_addr_valid(bus, bdf))
+ return 0;
+
+ return pci_generic_mmap_write_config(bus, pci_synquacer_ecam_conf_address,
+ bdf, offset, value, size);
+}
+
+/**
+ * pci_synquacer_ecam_of_to_plat() - Translate from DT to device state
+ * @dev: A pointer to the device being operated on
+ *
+ * Translate relevant data from the device tree pertaining to device @dev into
+ * state that the driver will later make use of. This state is stored in the
+ * device's private data structure.
+ *
+ * Return: 0 on success, else -EINVAL
+ */
+static int pci_synquacer_ecam_of_to_plat(struct udevice *dev)
+{
+ struct synquacer_ecam_pcie *pcie = dev_get_priv(dev);
+ struct fdt_resource reg_res;
+ int i, err;
+
+ debug("%s: called for %s\n", __func__, dev->name);
+
+ err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
+ 0, &reg_res);
+ if (err < 0) {
+ pr_err("\"reg\" resource not found\n");
+ return err;
+ }
+
+ /* Find the correct pair of the DBI/EXS base address */
+ for (i = 0; i < NUM_SQ_PCI_RC; i++) {
+ if (synquacer_pci_bases[i].cfg_base == reg_res.start)
+ break;
+ }
+ if (i == NUM_SQ_PCI_RC) {
+ pr_err("Unknown ECAM base address %lx.\n",
+ (unsigned long)reg_res.start);
+ return -ENOENT;
+ }
+ pcie->dbi_base = map_physmem(synquacer_pci_bases[i].dbi_base,
+ SYNQUACER_PCI_DBI_SIZE, MAP_NOCACHE);
+ if (!pcie->dbi_base) {
+ pr_err("Failed to map DBI for %s\n", dev->name);
+ return -ENOMEM;
+ }
+
+ pcie->exs_base = map_physmem(synquacer_pci_bases[i].exs_base,
+ SYNQUACER_PCI_EXS_SIZE, MAP_NOCACHE);
+ if (!pcie->exs_base) {
+ pr_err("Failed to map EXS for %s\n", dev->name);
+ return -ENOMEM;
+ }
+
+ pcie->size = fdt_resource_size(&reg_res);
+ pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE);
+ if (!pcie->cfg_base) {
+ pr_err("Failed to map config space for %s\n", dev->name);
+ return -ENOMEM;
+ }
+ debug("mappings DBI: %p EXS: %p CFG: %p\n", pcie->dbi_base, pcie->exs_base, pcie->cfg_base);
+
+ return 0;
+}
+
+static void pci_synquacer_pre_init(struct synquacer_ecam_pcie *pcie)
+{
+ void *base = pcie->exs_base;
+
+ masked_writel(base, EM_SELECT, PRE_DET_STT_SEL, 0);
+ masked_writel(base, EM_CONTROL, PRE_DET_STT_REG, 0);
+ masked_writel(base, EM_CONTROL, PRE_DET_STT_REG, 1);
+
+ /* 1: Assert all PHY / LINK resets */
+ masked_writel(base, RESET_SELECT_1, PERST_SEL, 0);
+ masked_writel(base, RESET_CONTROL_1, PERST_N_I_REG, 0);
+ masked_writel(base, RESET_CONTROL_1, PERST_N_O_REG, 0);
+
+ /* Device Reset(PERST#) is effective afrer Set device_type (RC) */
+ masked_writel(base, RESET_SELECT_1, PWUP_RST_SEL, 0);
+ masked_writel(base, RESET_CONTROL_1, PWUP_RST_N_REG, 0);
+ masked_writel(base, RESET_SELECT_1, BUTTON_RST_SEL, 0);
+ masked_writel(base, RESET_CONTROL_1, BUTTON_RST_N_REG, 0);
+ masked_writel(base, RESET_SELECT_1, PWR_RST_SEL, 1);
+ masked_writel(base, RESET_SELECT_2, MSTR_ARST_SEL, 1);
+ masked_writel(base, RESET_SELECT_2, SLV_ARST_SEL, 1);
+ masked_writel(base, RESET_SELECT_2, DBI_ARST_SEL, 1);
+ masked_writel(base, RESET_SELECT_1, CORE_RST_SEL, 1);
+ masked_writel(base, RESET_SELECT_1, STI_RST_SEL, 1);
+ masked_writel(base, RESET_SELECT_1, N_STI_RST_SEL, 1);
+ masked_writel(base, RESET_SELECT_1, SQU_RST_SEL, 1);
+ masked_writel(base, RESET_SELECT_1, PHY_RST_SEL, 1);
+
+ /* 2: Set P<n>_app_ltssm_enable='0' for reprogramming before linkup. */
+ masked_writel(base, CORE_CONTROL, APP_LTSSM_ENABLE, 0);
+
+ /* 3: Set device_type (RC) */
+ masked_writel(base, CORE_CONTROL, DEVICE_TYPE, 4);
+}
+
+static void pci_synquacer_dbi_init(void *dbi_base)
+{
+ masked_writel(dbi_base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 1);
+ /* 4 Lanes */
+ masked_writel(dbi_base, LINK_CAPABILITIES_REG,
+ PCIE_CAP_MAX_LINK_WIDTH, 4);
+ /* Gen 2 */
+ masked_writel(dbi_base, LINK_CAPABILITIES_REG,
+ PCIE_CAP_MAX_LINK_SPEED, 2);
+
+ masked_writel(dbi_base, TYPE1_CLASS_CODE_REV_ID_REG,
+ BASE_CLASS_CODE, BASE_CLASS_CODE_VALUE);
+ masked_writel(dbi_base, TYPE1_CLASS_CODE_REV_ID_REG,
+ SUBCLASS_CODE, SUBCLASS_CODE_VALUE);
+ masked_writel(dbi_base, TYPE1_CLASS_CODE_REV_ID_REG,
+ PROGRAM_INTERFACE, PROGRAM_INTERFACE_VALUE);
+
+ masked_writel(dbi_base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 0);
+}
+
+static void pcie_sq_prog_outbound_atu(void *dbi_base, int index,
+ u64 cpu_base, u64 pci_base, u64 size,
+ u32 type, u32 flags)
+{
+ debug("%s: %p, %d, %llx, %llx, %llx, %x, %x\n", __func__,
+ dbi_base, index, cpu_base, pci_base, size, type, flags);
+
+ writel(IATU_VIEWPORT_OUTBOUND | IATU_VIEWPORT_REGION_INDEX(index),
+ dbi_base + IATU_VIEWPORT_OFF);
+
+ writel((u32)(cpu_base & 0xffffffff),
+ dbi_base + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0);
+ writel((u32)(cpu_base >> 32),
+ dbi_base + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0);
+ writel((u32)(cpu_base + size - 1),
+ dbi_base + IATU_LIMIT_ADDR_OFF_OUTBOUND_0);
+
+ writel((u32)(pci_base & 0xffffffff),
+ dbi_base + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0);
+ writel((u32)(pci_base >> 32),
+ dbi_base + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0);
+
+ writel(type, dbi_base + IATU_REGION_CTRL_1_OFF_OUTBOUND_0);
+ writel(IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN | flags,
+ dbi_base + IATU_REGION_CTRL_2_OFF_OUTBOUND_0);
+}
+
+static void pci_synquacer_post_init(struct synquacer_ecam_pcie *pcie)
+{
+ void *base = pcie->exs_base;
+
+ /*
+ * 4: Set Bifurcation 1=disable 4=able
+ * 5: Supply Reference (It has executed)
+ * 6: Wait for 10usec (Reference Clocks is stable)
+ * 7: De assert PERST#
+ */
+ masked_writel(base, RESET_CONTROL_1, PERST_N_I_REG, 1);
+ masked_writel(base, RESET_CONTROL_1, PERST_N_O_REG, 1);
+
+ /* 8: Assert SYS_AUX_PWR_DET */
+ masked_writel(base, PM_CONTROL_2, SYS_AUX_PWR_DET, 1);
+
+ /* 9: Supply following clocks */
+ masked_writel(base, AXI_CLK_STOP, MSTR_CSYSREQ_REG, 1);
+ masked_writel(base, AXI_CLK_STOP, MSTR_ACLK_STOP, 0);
+ masked_writel(base, AXI_CLK_STOP, SLV_CSYSREQ_REG, 1);
+ masked_writel(base, AXI_CLK_STOP, SLV_ACLK_STOP, 0);
+ masked_writel(base, AXI_CLK_STOP, DBI_CSYSREQ_REG, 1);
+ masked_writel(base, AXI_CLK_STOP, DBI_ACLK_STOP, 0);
+
+ /*
+ * 10: De assert PHY reset
+ * 11: De assert LINK's PMC reset
+ */
+ masked_writel(base, RESET_CONTROL_1, PWUP_RST_N_REG, 1);
+ masked_writel(base, RESET_CONTROL_1, BUTTON_RST_N_REG, 1);
+
+ /* 12: PHY auto
+ * 13: Wrapper auto
+ * 14-17: PHY auto
+ * 18: Wrapper auto
+ * 19: Update registers through DBI AXI Slave interface
+ */
+ pci_synquacer_dbi_init(pcie->dbi_base);
+
+ or_writel(pcie->dbi_base, PCI_COMMAND,
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* Force link speed change to Gen2 at link up */
+ or_writel(pcie->dbi_base, GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE);
+
+ /* Region 0: MMIO32 range */
+ pcie_sq_prog_outbound_atu(pcie->dbi_base, 0,
+ pcie->mem.phys_start,
+ pcie->mem.bus_start,
+ pcie->mem.size,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH,
+ IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT);
+
+ /* Region 1: Type 0 config space */
+ pcie_sq_prog_outbound_atu(pcie->dbi_base, 1,
+ (u64)pcie->cfg_base,
+ 0,
+ SIZE_64KB,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
+ IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
+
+ /* Region 2: Type 1 config space */
+ pcie_sq_prog_outbound_atu(pcie->dbi_base, 2,
+ (u64)pcie->cfg_base + SIZE_64KB,
+ 0,
+ (u64)pcie->io.phys_start - (u64)pcie->cfg_base - SIZE_64KB,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
+ IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
+
+ /* Region 3: port I/O range */
+ pcie_sq_prog_outbound_atu(pcie->dbi_base, 3,
+ pcie->io.phys_start,
+ pcie->io.bus_start,
+ pcie->io.size,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
+ 0);
+
+ /* Region 4: MMIO64 range */
+ pcie_sq_prog_outbound_atu(pcie->dbi_base, 4,
+ pcie->mem64.phys_start,
+ pcie->mem64.bus_start,
+ pcie->mem64.size,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH,
+ IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT);
+
+ /* enable link */
+ if (masked_readl(base, CORE_CONTROL, APP_LTSSM_ENABLE) == 0)
+ masked_writel(base, CORE_CONTROL, APP_LTSSM_ENABLE, 1);
+}
+
+static int pci_synquacer_ecam_probe(struct udevice *dev)
+{
+ struct synquacer_ecam_pcie *pcie = dev_get_priv(dev);
+ struct udevice *ctlr = pci_get_controller(dev);
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+
+ debug("Probe synquacer pcie for bus %d\n", dev_seq(dev));
+ pcie->first_busno = dev_seq(dev);
+
+ /* Store the IO and MEM windows settings for configuring ATU */
+ pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */
+ pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */
+ pcie->io.size = hose->regions[0].size; /* IO size */
+
+ pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
+ pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */
+ pcie->mem.size = hose->regions[1].size; /* MEM size */
+
+ pcie->mem64.phys_start = hose->regions[2].phys_start; /* MEM64 base */
+ pcie->mem64.bus_start = hose->regions[2].bus_start; /* MEM64_bus_addr */
+ pcie->mem64.size = hose->regions[2].size; /* MEM64 size */
+
+ pci_synquacer_pre_init(pcie);
+
+ mdelay(150);
+
+ pci_synquacer_post_init(pcie);
+
+ /* It takes a while to stabilize the PCIe bus for scanning */
+ mdelay(100);
+
+ return 0;
+}
+
+static const struct dm_pci_ops pci_synquacer_ecam_ops = {
+ .read_config = pci_synquacer_ecam_read_config,
+ .write_config = pci_synquacer_ecam_write_config,
+};
+
+static const struct udevice_id pci_synquacer_ecam_ids[] = {
+ { .compatible = "socionext,synquacer-pcie-ecam" },
+ { }
+};
+
+U_BOOT_DRIVER(pci_synquacer_ecam) = {
+ .name = "pci_synquacer_ecam",
+ .id = UCLASS_PCI,
+ .of_match = pci_synquacer_ecam_ids,
+ .ops = &pci_synquacer_ecam_ops,
+ .probe = pci_synquacer_ecam_probe,
+ .of_to_plat = pci_synquacer_ecam_of_to_plat,
+ .priv_auto = sizeof(struct synquacer_ecam_pcie),
+};
diff --git a/drivers/pinctrl/mscc/mscc-common.h b/drivers/pinctrl/mscc/mscc-common.h
index 3c5c1faf840..49c84a9f410 100644
--- a/drivers/pinctrl/mscc/mscc-common.h
+++ b/drivers/pinctrl/mscc/mscc-common.h
@@ -61,6 +61,6 @@ int mscc_pinctrl_probe(struct udevice *dev, int num_func,
const struct mscc_pin_data *mscc_pins, int num_pins,
char * const *function_names,
const unsigned long *mscc_gpios);
-const struct pinctrl_ops mscc_pinctrl_ops;
+extern const struct pinctrl_ops mscc_pinctrl_ops;
-const struct dm_gpio_ops mscc_gpio_ops;
+extern const struct dm_gpio_ops mscc_gpio_ops;
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index d8c6c2f6b5f..d8dd5c1104b 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -23,6 +23,7 @@
/* Serial registers - this driver works in uartdm mode*/
#define UARTDM_DMRX 0x34 /* Max RX transfer length */
+#define UARTDM_DMEN 0x3C /* DMA/data-packing mode */
#define UARTDM_NCF_TX 0x40 /* Number of chars to TX */
#define UARTDM_RXFS 0x50 /* RX channel status register */
@@ -197,6 +198,9 @@ static void uart_dm_init(struct msm_serial_data *priv)
writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2);
writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR);
writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR);
+
+ /* Make sure BAM/single character mode is disabled */
+ writel(0x0, priv->base + UARTDM_DMEN);
}
static int msm_serial_probe(struct udevice *dev)
{
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index e317d8a2c64..5c2a60a2142 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -488,4 +488,12 @@ config MXC_SPI
Enable the MXC SPI controller driver. This driver can be used
on various i.MX SoCs such as i.MX31/35/51/6/7.
+config SYNQUACER_SPI
+ bool "Socionext SynQuacer HS-SPI driver"
+ depends on ARCH_SYNQUACER
+ help
+ Enable the Socionext HS-SPI driver for SynQuacer. This driver can
+ be used to access the SPI interface and SPI NOR flash on platforms
+ embedding this HS-SPI IP core.
+
endif # menu "SPI Support"
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3dc83089b8f..f70851e4bc6 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
+obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
new file mode 100644
index 00000000000..ce558c4bc07
--- /dev/null
+++ b/drivers/spi/spi-synquacer.c
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * spi-synquacer.c - Socionext Synquacer SPI driver
+ * Copyright 2021 Linaro Ltd.
+ * Copyright 2021 Socionext, Inc.
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <time.h>
+#include <dm/device_compat.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <spi.h>
+#include <wait_bit.h>
+
+#define MCTRL 0x0
+#define MEN 0
+#define CSEN 1
+#define IPCLK 3
+#define MES 4
+#define SYNCON 5
+
+#define PCC0 0x4
+#define PCC(n) (PCC0 + (n) * 4)
+#define RTM 3
+#define ACES 2
+#define SAFESYNC 16
+#define CPHA 0
+#define CPOL 1
+#define SSPOL 4
+#define SDIR 7
+#define SS2CD 5
+#define SENDIAN 8
+#define CDRS_SHIFT 9
+#define CDRS_MASK 0x7f
+
+#define TXF 0x14
+#define TXE 0x18
+#define TXC 0x1c
+#define RXF 0x20
+#define RXE 0x24
+#define RXC 0x28
+#define TFLETE 4
+#define RFMTE 5
+
+#define FAULTF 0x2c
+#define FAULTC 0x30
+
+#define DMCFG 0x34
+#define SSDC 1
+#define MSTARTEN 2
+
+#define DMSTART 0x38
+#define TRIGGER 0
+#define DMSTOP 8
+#define CS_MASK 3
+#define CS_SHIFT 16
+#define DATA_TXRX 0
+#define DATA_RX 1
+#define DATA_TX 2
+#define DATA_MASK 3
+#define DATA_SHIFT 26
+#define BUS_WIDTH 24
+
+#define DMBCC 0x3c
+#define DMSTATUS 0x40
+#define RX_DATA_MASK 0x1f
+#define RX_DATA_SHIFT 8
+#define TX_DATA_MASK 0x1f
+#define TX_DATA_SHIFT 16
+
+#define TXBITCNT 0x44
+
+#define FIFOCFG 0x4c
+#define BPW_MASK 0x3
+#define BPW_SHIFT 8
+#define RX_FLUSH 11
+#define TX_FLUSH 12
+#define RX_TRSHLD_MASK 0xf
+#define RX_TRSHLD_SHIFT 0
+#define TX_TRSHLD_MASK 0xf
+#define TX_TRSHLD_SHIFT 4
+
+#define TXFIFO 0x50
+#define RXFIFO 0x90
+#define MID 0xfc
+
+#define FIFO_DEPTH 16
+#define TX_TRSHLD 4
+#define RX_TRSHLD (FIFO_DEPTH - TX_TRSHLD)
+
+#define TXBIT 1
+#define RXBIT 2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct synquacer_spi_plat {
+ void __iomem *base;
+ bool aces, rtm;
+};
+
+struct synquacer_spi_priv {
+ void __iomem *base;
+ bool aces, rtm;
+ int speed, cs, mode, rwflag;
+ void *rx_buf;
+ const void *tx_buf;
+ unsigned int tx_words, rx_words;
+};
+
+static void read_fifo(struct synquacer_spi_priv *priv)
+{
+ u32 len = readl(priv->base + DMSTATUS);
+ u8 *buf = priv->rx_buf;
+ int i;
+
+ len = (len >> RX_DATA_SHIFT) & RX_DATA_MASK;
+ len = min_t(unsigned int, len, priv->rx_words);
+
+ for (i = 0; i < len; i++)
+ *buf++ = readb(priv->base + RXFIFO);
+
+ priv->rx_buf = buf;
+ priv->rx_words -= len;
+}
+
+static void write_fifo(struct synquacer_spi_priv *priv)
+{
+ u32 len = readl(priv->base + DMSTATUS);
+ const u8 *buf = priv->tx_buf;
+ int i;
+
+ len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK;
+ len = min_t(unsigned int, FIFO_DEPTH - len, priv->tx_words);
+
+ for (i = 0; i < len; i++)
+ writeb(*buf++, priv->base + TXFIFO);
+
+ priv->tx_buf = buf;
+ priv->tx_words -= len;
+}
+
+static void synquacer_cs_set(struct synquacer_spi_priv *priv, bool active)
+{
+ u32 val;
+
+ val = readl(priv->base + DMSTART);
+ val &= ~(CS_MASK << CS_SHIFT);
+ val |= priv->cs << CS_SHIFT;
+
+ if (active) {
+ writel(val, priv->base + DMSTART);
+
+ val = readl(priv->base + DMSTART);
+ val &= ~BIT(DMSTOP);
+ writel(val, priv->base + DMSTART);
+ } else {
+ val |= BIT(DMSTOP);
+ writel(val, priv->base + DMSTART);
+
+ if (priv->rx_buf) {
+ u32 buf[16];
+
+ priv->rx_buf = buf;
+ priv->rx_words = 16;
+ read_fifo(priv);
+ }
+ }
+}
+
+static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx)
+{
+ struct udevice *bus = dev->parent;
+ struct synquacer_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+ u32 val, div, bus_width;
+ int rwflag;
+
+ rwflag = (rx ? 1 : 0) | (tx ? 2 : 0);
+
+ /* if nothing to do */
+ if (slave_plat->mode == priv->mode &&
+ rwflag == priv->rwflag &&
+ slave_plat->cs == priv->cs &&
+ slave_plat->max_hz == priv->speed)
+ return;
+
+ priv->rwflag = rwflag;
+ priv->cs = slave_plat->cs;
+ priv->mode = slave_plat->mode;
+ priv->speed = slave_plat->max_hz;
+
+ if (priv->mode & SPI_TX_BYTE)
+ bus_width = 1;
+ else if (priv->mode & SPI_TX_DUAL)
+ bus_width = 2;
+ else if (priv->mode & SPI_TX_QUAD)
+ bus_width = 4;
+ else if (priv->mode & SPI_TX_OCTAL)
+ bus_width = 8;
+
+ div = DIV_ROUND_UP(125000000, priv->speed);
+
+ val = readl(priv->base + PCC(priv->cs));
+ val &= ~BIT(RTM);
+ val &= ~BIT(ACES);
+ val &= ~BIT(SAFESYNC);
+ if ((priv->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) && div < 3)
+ val |= BIT(SAFESYNC);
+ if ((priv->mode & (SPI_TX_QUAD | SPI_RX_QUAD)) && div < 6)
+ val |= BIT(SAFESYNC);
+
+ if (priv->mode & SPI_CPHA)
+ val |= BIT(CPHA);
+ else
+ val &= ~BIT(CPHA);
+
+ if (priv->mode & SPI_CPOL)
+ val |= BIT(CPOL);
+ else
+ val &= ~BIT(CPOL);
+
+ if (priv->mode & SPI_CS_HIGH)
+ val |= BIT(SSPOL);
+ else
+ val &= ~BIT(SSPOL);
+
+ if (priv->mode & SPI_LSB_FIRST)
+ val |= BIT(SDIR);
+ else
+ val &= ~BIT(SDIR);
+
+ if (priv->aces)
+ val |= BIT(ACES);
+
+ if (priv->rtm)
+ val |= BIT(RTM);
+
+ val |= (3 << SS2CD);
+ val |= BIT(SENDIAN);
+
+ val &= ~(CDRS_MASK << CDRS_SHIFT);
+ val |= ((div >> 1) << CDRS_SHIFT);
+
+ writel(val, priv->base + PCC(priv->cs));
+
+ val = readl(priv->base + FIFOCFG);
+ val &= ~(BPW_MASK << BPW_SHIFT);
+ val |= (0 << BPW_SHIFT);
+ writel(val, priv->base + FIFOCFG);
+
+ val = readl(priv->base + DMSTART);
+ val &= ~(DATA_MASK << DATA_SHIFT);
+
+ if (tx && rx)
+ val |= (DATA_TXRX << DATA_SHIFT);
+ else if (rx)
+ val |= (DATA_RX << DATA_SHIFT);
+ else
+ val |= (DATA_TX << DATA_SHIFT);
+
+ val &= ~(3 << BUS_WIDTH);
+ val |= ((bus_width >> 1) << BUS_WIDTH);
+ writel(val, priv->base + DMSTART);
+}
+
+static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *tx_buf, void *rx_buf,
+ unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct synquacer_spi_priv *priv = dev_get_priv(bus);
+ u32 val, words, busy;
+
+ val = readl(priv->base + FIFOCFG);
+ val |= (1 << RX_FLUSH);
+ val |= (1 << TX_FLUSH);
+ writel(val, priv->base + FIFOCFG);
+
+ synquacer_spi_config(dev, rx_buf, tx_buf);
+
+ priv->tx_buf = tx_buf;
+ priv->rx_buf = rx_buf;
+
+ words = bitlen / 8;
+
+ if (tx_buf) {
+ busy |= BIT(TXBIT);
+ priv->tx_words = words;
+ } else {
+ busy &= ~BIT(TXBIT);
+ priv->tx_words = 0;
+ }
+
+ if (rx_buf) {
+ busy |= BIT(RXBIT);
+ priv->rx_words = words;
+ } else {
+ busy &= ~BIT(RXBIT);
+ priv->rx_words = 0;
+ }
+
+ if (flags & SPI_XFER_BEGIN)
+ synquacer_cs_set(priv, true);
+
+ if (tx_buf)
+ write_fifo(priv);
+
+ if (rx_buf) {
+ val = readl(priv->base + FIFOCFG);
+ val &= ~(RX_TRSHLD_MASK << RX_TRSHLD_SHIFT);
+ val |= ((priv->rx_words > FIFO_DEPTH ?
+ RX_TRSHLD : priv->rx_words) << RX_TRSHLD_SHIFT);
+ writel(val, priv->base + FIFOCFG);
+ }
+
+ writel(~0, priv->base + TXC);
+ writel(~0, priv->base + RXC);
+
+ /* Trigger */
+ val = readl(priv->base + DMSTART);
+ val |= BIT(TRIGGER);
+ writel(val, priv->base + DMSTART);
+
+ while (busy & (BIT(RXBIT) | BIT(TXBIT))) {
+ if (priv->rx_words)
+ read_fifo(priv);
+ else
+ busy &= ~BIT(RXBIT);
+
+ if (priv->tx_words) {
+ write_fifo(priv);
+ } else {
+ u32 len;
+
+ do { /* wait for shifter to empty out */
+ cpu_relax();
+ len = readl(priv->base + DMSTATUS);
+ len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK;
+ } while (tx_buf && len);
+ busy &= ~BIT(TXBIT);
+ }
+ }
+
+ if (flags & SPI_XFER_END)
+ synquacer_cs_set(priv, false);
+
+ return 0;
+}
+
+static int synquacer_spi_set_speed(struct udevice *bus, uint speed)
+{
+ return 0;
+}
+
+static int synquacer_spi_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
+
+static int synquacer_spi_claim_bus(struct udevice *dev)
+{
+ return 0;
+}
+
+static int synquacer_spi_release_bus(struct udevice *dev)
+{
+ return 0;
+}
+
+static void synquacer_spi_disable_module(struct synquacer_spi_priv *priv)
+{
+ writel(0, priv->base + MCTRL);
+ while (readl(priv->base + MCTRL) & BIT(MES))
+ cpu_relax();
+}
+
+static void synquacer_spi_init(struct synquacer_spi_priv *priv)
+{
+ u32 val;
+
+ synquacer_spi_disable_module(priv);
+
+ writel(0, priv->base + TXE);
+ writel(0, priv->base + RXE);
+ val = readl(priv->base + TXF);
+ writel(val, priv->base + TXC);
+ val = readl(priv->base + RXF);
+ writel(val, priv->base + RXC);
+ val = readl(priv->base + FAULTF);
+ writel(val, priv->base + FAULTC);
+
+ val = readl(priv->base + DMCFG);
+ val &= ~BIT(SSDC);
+ val &= ~BIT(MSTARTEN);
+ writel(val, priv->base + DMCFG);
+
+ /* Enable module with direct mode */
+ val = readl(priv->base + MCTRL);
+ val &= ~BIT(IPCLK);
+ val &= ~BIT(CSEN);
+ val |= BIT(MEN);
+ val |= BIT(SYNCON);
+ writel(val, priv->base + MCTRL);
+}
+
+static void synquacer_spi_exit(struct synquacer_spi_priv *priv)
+{
+ u32 val;
+
+ synquacer_spi_disable_module(priv);
+
+ /* Enable module with command sequence mode */
+ val = readl(priv->base + MCTRL);
+ val &= ~BIT(IPCLK);
+ val |= BIT(CSEN);
+ val |= BIT(MEN);
+ val |= BIT(SYNCON);
+ writel(val, priv->base + MCTRL);
+
+ while (!(readl(priv->base + MCTRL) & BIT(MES)))
+ cpu_relax();
+}
+
+static int synquacer_spi_probe(struct udevice *bus)
+{
+ struct synquacer_spi_plat *plat = dev_get_plat(bus);
+ struct synquacer_spi_priv *priv = dev_get_priv(bus);
+
+ priv->base = plat->base;
+ priv->aces = plat->aces;
+ priv->rtm = plat->rtm;
+
+ synquacer_spi_init(priv);
+ return 0;
+}
+
+static int synquacer_spi_remove(struct udevice *bus)
+{
+ struct synquacer_spi_priv *priv = dev_get_priv(bus);
+
+ synquacer_spi_exit(priv);
+ return 0;
+}
+
+static int synquacer_spi_of_to_plat(struct udevice *bus)
+{
+ struct synquacer_spi_plat *plat = dev_get_plat(bus);
+ struct clk clk;
+
+ plat->base = dev_read_addr_ptr(bus);
+
+ plat->aces = dev_read_bool(bus, "socionext,set-aces");
+ plat->rtm = dev_read_bool(bus, "socionext,use-rtm");
+
+ clk_get_by_name(bus, "iHCLK", &clk);
+ clk_enable(&clk);
+
+ return 0;
+}
+
+static const struct dm_spi_ops synquacer_spi_ops = {
+ .claim_bus = synquacer_spi_claim_bus,
+ .release_bus = synquacer_spi_release_bus,
+ .xfer = synquacer_spi_xfer,
+ .set_speed = synquacer_spi_set_speed,
+ .set_mode = synquacer_spi_set_mode,
+};
+
+static const struct udevice_id synquacer_spi_ids[] = {
+ { .compatible = "socionext,synquacer-spi" },
+ { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(synquacer_spi) = {
+ .name = "synquacer_spi",
+ .id = UCLASS_SPI,
+ .of_match = synquacer_spi_ids,
+ .ops = &synquacer_spi_ops,
+ .of_to_plat = synquacer_spi_of_to_plat,
+ .plat_auto = sizeof(struct synquacer_spi_plat),
+ .priv_auto = sizeof(struct synquacer_spi_priv),
+ .probe = synquacer_spi_probe,
+ .flags = DM_FLAG_OS_PREPARE,
+ .remove = synquacer_spi_remove,
+};
diff --git a/drivers/w1/w1-gpio.c b/drivers/w1/w1-gpio.c
index 3b0ead6f6dc..9346f810ce1 100644
--- a/drivers/w1/w1-gpio.c
+++ b/drivers/w1/w1-gpio.c
@@ -156,7 +156,7 @@ static int w1_gpio_of_to_plat(struct udevice *dev)
struct w1_gpio_pdata *pdata = dev_get_plat(dev);
int ret;
- ret = gpio_request_by_name(dev, "gpios", 0, &pdata->gpio, 0);
+ ret = gpio_request_by_name(dev, "gpios", 0, &pdata->gpio, GPIOD_IS_IN);
if (ret < 0)
printf("Error claiming GPIO %d\n", ret);
diff --git a/include/bootstage.h b/include/bootstage.h
index 00c85fb86aa..f837a387c8c 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -11,6 +11,8 @@
#ifndef _BOOTSTAGE_H
#define _BOOTSTAGE_H
+#include <linux/kconfig.h>
+
/* Flags for each bootstage record */
enum bootstage_flags {
BOOTSTAGEF_ERROR = 1 << 0, /* Error record */
@@ -218,7 +220,7 @@ enum bootstage_id {
*/
ulong timer_get_boot_us(void);
-#if defined(USE_HOSTCC)
+#if defined(USE_HOSTCC) || !CONFIG_IS_ENABLED(BOOTSTAGE)
#define show_boot_progress(val) do {} while (0)
#else
/**
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 5d2b77b4a37..465d9ce8e99 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -31,11 +31,6 @@
- GENERATED_GBL_DATA_SIZE)
/*
- * Serial Driver
- */
-#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */
-
-/*
* DMA
*/
#if !defined(CONFIG_SPL_BUILD)
@@ -46,7 +41,6 @@
* I2C
*/
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_LPC32XX
#define CONFIG_SYS_I2C_SPEED 100000
/*
diff --git a/include/configs/ea-lpc3250devkitv2.h b/include/configs/ea-lpc3250devkitv2.h
new file mode 100644
index 00000000000..c1a37c8a790
--- /dev/null
+++ b/include/configs/ea-lpc3250devkitv2.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Embedded Artists LPC3250 DevKit v2
+ * Copyright (C) 2021 Trevor Woerner <twoerner@gmail.com>
+ */
+
+#ifndef __CONFIG_EA_LPC3250DEVKITV2_H__
+#define __CONFIG_EA_LPC3250DEVKITV2_H__
+
+#include <linux/sizes.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * SoC and board defines
+ */
+#define CONFIG_MACH_TYPE MACH_TYPE_LPC3XXX
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_SIZE_LIMIT 0x000fffff /* maximum allowable size for full U-Boot binary */
+
+/*
+ * RAM
+ */
+#define CONFIG_SYS_MALLOC_LEN SZ_4M
+#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
+
+/*
+ * cmd
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x80100000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * SoC-specific config
+ */
+#include <asm/arch/config.h>
+
+#endif
diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h
new file mode 100644
index 00000000000..42c64f3ca5e
--- /dev/null
+++ b/include/configs/openpiton-riscv64.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2021 Tianrui Wei
+ *
+ * Authors:
+ * Anup Patel <anup.patel@wdc.com>
+ * Tianrui Wei <tianrui-wei@outlook.com>
+ */
+
+#ifndef __OPENPITON_RISCV64_CONFIG_H
+#define __OPENPITON_RISCV64_CONFIG_H
+
+#include <linux/sizes.h>
+
+/* Environment options */
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32M)
+#define CONFIG_SYS_LOAD_ADDR 0x87000000
+#define CONFIG_SYS_MALLOC_LEN SZ_256M
+#define CONFIG_SYS_BOOTM_LEN SZ_256M
+
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_MAX_SIZE 0x00100000
+#define CONFIG_SPL_BSS_START_ADDR 0x82000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0100000
+#define CONFIG_SPL_STACK (0x80000000 + 0x04000000 - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "boot/fw_payload.bin"
+#define CONFIG_SPL_GD_ADDR 0x85000000
+#endif
+
+/* -------------------------------------------------
+ * Environment
+ */
+//Disable persistent environment variable storage
+#define CONFIG_ENV_IS_NOWHERE 1
+
+/* ---------------------------------------------------------------------
+ * Board boot configuration
+ */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_addr_r=0x86000000\0" \
+ "kernel_addr_r=0x80200000\0" \
+ "image=boot/Image\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0"
+
+#define CONFIG_USE_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND \
+ "fdt addr ${fdtcontroladdr}; " \
+ "fdt move ${fdtcontroladdr} ${fdt_addr_r}; " \
+ "load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; " \
+ "booti ${kernel_addr_r} - ${fdt_addr_r}; "
+
+#endif/* __CONFIG_H */
diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
index 0d69d1c5482..b6c29f8c604 100644
--- a/include/configs/sifive-unleashed.h
+++ b/include/configs/sifive-unleashed.h
@@ -75,6 +75,7 @@
"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
"partitions=" PARTS_DEFAULT "\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
BOOTENV \
BOOTENV_SF
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 4fad69bb199..d63a5f62fbc 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -73,6 +73,7 @@
"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
"partitions=" PARTS_DEFAULT "\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
BOOTENV
#define CONFIG_PREBOOT \
@@ -80,4 +81,10 @@
"fdt addr ${fdtcontroladdr};"
#endif /* CONFIG_SPL_BUILD */
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 0x1
+
+#define CONFIG_ID_EEPROM
+
#endif /* __SIFIVE_UNMATCHED_H */
diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h
new file mode 100644
index 00000000000..8fe10d74853
--- /dev/null
+++ b/include/configs/synquacer.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016-2017 Socionext Inc.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Timers for fasp(TIMCLK) */
+#define CONFIG_SYS_HZ 1000 /* 1 msec */
+#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
+
+/*
+ * SDRAM (for initialize)
+ */
+#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
+#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
+
+#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */
+#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
+
+#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */
+
+/*
+ * Boot info
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */
+#define CONFIG_SYS_MALLOC_LEN (0x01000000) /* 16Mbyte size of malloc() */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */
+
+/*
+ * Hardware drivers support
+ */
+
+/* RTC */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51
+
+/* Serial (pl011) */
+#define UART_CLK (62500000)
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK UART_CLK
+#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
+
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+
+/* Support MTD */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BASE (0x08000000)
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024))
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_MAXARGS 128
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
+/* #define CONFIG_SYS_PCI_64BIT 1 */
+
+#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
+ "mtd nor1=u-boot.bin raw 200000 100000;" \
+ "fip.bin raw 180000 78000;" \
+ "optee.bin raw 500000 100000\0"
+
+/* Distro boot settings */
+#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_CMD_USB
+#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICE_USB(func)
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICE_MMC(func)
+#endif
+
+#ifdef CONFIG_CMD_NVME
+#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0)
+#else
+#define BOOT_TARGET_DEVICE_NVME(func)
+#endif
+
+#ifdef CONFIG_CMD_SCSI
+#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1)
+#else
+#define BOOT_TARGET_DEVICE_SCSI(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_DEVICE_USB(func) \
+ BOOT_TARGET_DEVICE_MMC(func) \
+ BOOT_TARGET_DEVICE_SCSI(func) \
+ BOOT_TARGET_DEVICE_NVME(func) \
+
+#include <config_distro_bootcmd.h>
+#else /* CONFIG_SPL_BUILD */
+#define BOOTENV
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_addr_r=0x9fe00000\0" \
+ "kernel_addr_r=0x90000000\0" \
+ "ramdisk_addr_r=0xa0000000\0" \
+ "scriptaddr=0x88000000\0" \
+ "pxefile_addr_r=0x88100000\0" \
+ DEFAULT_DFU_ALT_INFO \
+ BOOTENV
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index 7874b77f3f8..d498c8f3bc6 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -36,11 +36,6 @@
- GENERATED_GBL_DATA_SIZE)
/*
- * Serial Driver
- */
-#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */
-
-/*
* Ethernet Driver
*/
@@ -52,7 +47,6 @@
* I2C driver
*/
-#define CONFIG_SYS_I2C_LPC32XX
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SPEED 350000
diff --git a/include/dt-bindings/clock/lpc32xx-clock.h b/include/dt-bindings/clock/lpc32xx-clock.h
new file mode 100644
index 00000000000..e624d3a5279
--- /dev/null
+++ b/include/dt-bindings/clock/lpc32xx-clock.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This code is released using a dual license strategy: BSD/GPL
+ * You can choose the licence that better fits your requirements.
+ *
+ * Released under the terms of 3-clause BSD License
+ * Released under the terms of GNU General Public License Version 2.0
+ *
+ */
+
+#ifndef __DT_BINDINGS_LPC32XX_CLOCK_H
+#define __DT_BINDINGS_LPC32XX_CLOCK_H
+
+/* LPC32XX System Control Block clocks */
+#define LPC32XX_CLK_RTC 1
+#define LPC32XX_CLK_DMA 2
+#define LPC32XX_CLK_MLC 3
+#define LPC32XX_CLK_SLC 4
+#define LPC32XX_CLK_LCD 5
+#define LPC32XX_CLK_MAC 6
+#define LPC32XX_CLK_SD 7
+#define LPC32XX_CLK_DDRAM 8
+#define LPC32XX_CLK_SSP0 9
+#define LPC32XX_CLK_SSP1 10
+#define LPC32XX_CLK_UART3 11
+#define LPC32XX_CLK_UART4 12
+#define LPC32XX_CLK_UART5 13
+#define LPC32XX_CLK_UART6 14
+#define LPC32XX_CLK_IRDA 15
+#define LPC32XX_CLK_I2C1 16
+#define LPC32XX_CLK_I2C2 17
+#define LPC32XX_CLK_TIMER0 18
+#define LPC32XX_CLK_TIMER1 19
+#define LPC32XX_CLK_TIMER2 20
+#define LPC32XX_CLK_TIMER3 21
+#define LPC32XX_CLK_TIMER4 22
+#define LPC32XX_CLK_TIMER5 23
+#define LPC32XX_CLK_WDOG 24
+#define LPC32XX_CLK_I2S0 25
+#define LPC32XX_CLK_I2S1 26
+#define LPC32XX_CLK_SPI1 27
+#define LPC32XX_CLK_SPI2 28
+#define LPC32XX_CLK_MCPWM 29
+#define LPC32XX_CLK_HSTIMER 30
+#define LPC32XX_CLK_KEY 31
+#define LPC32XX_CLK_PWM1 32
+#define LPC32XX_CLK_PWM2 33
+#define LPC32XX_CLK_ADC 34
+#define LPC32XX_CLK_HCLK_PLL 35
+#define LPC32XX_CLK_PERIPH 36
+
+/* LPC32XX USB clocks */
+#define LPC32XX_USB_CLK_I2C 1
+#define LPC32XX_USB_CLK_DEVICE 2
+#define LPC32XX_USB_CLK_HOST 3
+
+#endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */
diff --git a/include/phy.h b/include/phy.h
index 2754421ed4f..6b928636b6d 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -51,6 +51,10 @@ struct udevice;
PHY_100BT_FEATURES | \
PHY_DEFAULT_FEATURES)
+#define PHY_100BT1_FEATURES (SUPPORTED_TP | \
+ SUPPORTED_MII | \
+ SUPPORTED_100baseT_Full)
+
#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \
PHY_1000BT_FEATURES)
@@ -523,6 +527,7 @@ int phy_micrel_ksz8xxx_init(void);
int phy_micrel_ksz90x1_init(void);
int phy_meson_gxl_init(void);
int phy_natsemi_init(void);
+int phy_nxp_tja11xx_init(void);
int phy_realtek_init(void);
int phy_smsc_init(void);
int phy_teranetics_init(void);
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index e549a5557f5..ca6066b85ef 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -2542,7 +2542,6 @@ CONFIG_SYS_I2C_INIT_BOARD
CONFIG_SYS_I2C_LDI_ADDR
CONFIG_SYS_I2C_LM75_ADDR
CONFIG_SYS_I2C_LM90_ADDR
-CONFIG_SYS_I2C_LPC32XX
CONFIG_SYS_I2C_LPC32XX_SLAVE
CONFIG_SYS_I2C_LPC32XX_SPEED
CONFIG_SYS_I2C_MAC1_BUS
@@ -2734,7 +2733,6 @@ CONFIG_SYS_LOW
CONFIG_SYS_LOWMEM_BASE
CONFIG_SYS_LOW_RES_TIMER
CONFIG_SYS_LPAE_SDRAM_BASE
-CONFIG_SYS_LPC32XX_UART
CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH
CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS
diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile
index de0c6cee8c7..ced4457ab20 100644
--- a/tools/docker/Dockerfile
+++ b/tools/docker/Dockerfile
@@ -12,24 +12,23 @@ ENV DEBIAN_FRONTEND=noninteractive
# Add LLVM repository
RUN apt-get update && apt-get install -y gnupg2 wget xz-utils && rm -rf /var/lib/apt/lists/*
RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add -
-RUN echo deb http://apt.llvm.org/focal/ llvm-toolchain-focal-10 main | tee /etc/apt/sources.list.d/llvm.list
+RUN echo deb http://apt.llvm.org/focal/ llvm-toolchain-focal-11 main | tee /etc/apt/sources.list.d/llvm.list
-# Manually install the kernel.org "Crosstool" based toolchains for gcc-7.3
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/9.2.0/x86_64-gcc-9.2.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/9.2.0/x86_64-gcc-9.2.0-nolibc-arm-linux-gnueabi.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/9.2.0/x86_64-gcc-9.2.0-nolibc-i386-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/9.2.0/x86_64-gcc-9.2.0-nolibc-m68k-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/9.2.0/x86_64-gcc-9.2.0-nolibc-mips-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/9.2.0/x86_64-gcc-9.2.0-nolibc-microblaze-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/9.2.0/x86_64-gcc-9.2.0-nolibc-nios2-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/9.2.0/x86_64-gcc-9.2.0-nolibc-powerpc-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/9.2.0/x86_64-gcc-9.2.0-nolibc-riscv32-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/9.2.0/x86_64-gcc-9.2.0-nolibc-riscv64-linux.tar.xz | tar -C /opt -xJ
-RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/9.2.0/x86_64-gcc-9.2.0-nolibc-sh2-linux.tar.xz | tar -C /opt -xJ
+# Manually install the kernel.org "Crosstool" based toolchains for gcc-11.1.0
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-arm-linux-gnueabi.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-i386-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-m68k-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-mips-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-microblaze-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-nios2-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-powerpc-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-riscv64-linux.tar.xz | tar -C /opt -xJ
+RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-sh2-linux.tar.xz | tar -C /opt -xJ
# Manually install other toolchains
-RUN wget -O - https://github.com/foss-xtensa/toolchain/releases/download/2018.02/x86_64-2018.02-xtensa-dc233c-elf.tar.gz | tar -C /opt -xz
-RUN wget -O - https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2019.09-release/arc_gnu_2019.09_prebuilt_uclibc_le_archs_linux_install.tar.gz | tar --no-same-owner -C /opt -xz
+RUN wget -O - https://github.com/foss-xtensa/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc233c-elf.tar.gz | tar -C /opt -xz
+RUN wget -O - https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2021.03-release/arc_gnu_2021.03_prebuilt_uclibc_le_archs_linux_install.tar.gz | tar --no-same-owner -C /opt -xz
RUN wget -O - https://github.com/vincentzwc/prebuilt-nds32-toolchain/releases/download/20180521/nds32le-linux-glibc-v3-upstream.tar.gz | tar -C /opt -xz
# Update and install things from apt now
@@ -98,15 +97,13 @@ RUN apt-get update && apt-get install -y \
util-linux \
uuid-dev \
virtualenv \
+ xxd \
zip \
&& rm -rf /var/lib/apt/lists/*
# Make kernels readable for libguestfs tools to work correctly
RUN chmod +r /boot/vmlinu*
-# Manually install libmpfr4 for the toolchains
-RUN wget http://mirrors.kernel.org/ubuntu/pool/main/m/mpfr4/libmpfr4_3.1.4-1_amd64.deb && dpkg -i libmpfr4_3.1.4-1_amd64.deb && rm libmpfr4_3.1.4-1_amd64.deb
-
# Manually install a new enough version of sbsigntools (must be v0.9.4 or later)
RUN git clone https://git.kernel.org/pub/scm/linux/kernel/git/jejb/sbsigntools.git /tmp/sbsigntools && \
cd /tmp/sbsigntools && \
@@ -120,16 +117,16 @@ RUN git clone https://git.kernel.org/pub/scm/linux/kernel/git/jejb/sbsigntools.g
# Build GRUB UEFI targets for ARM & RISC-V, 32-bit and 64-bit
RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \
cd /tmp/grub && \
- git checkout grub-2.04 && \
+ git checkout grub-2.06 && \
./bootstrap && \
mkdir -p /opt/grub && \
./configure --target=aarch64 --with-platform=efi \
CC=gcc \
- TARGET_CC=/opt/gcc-9.2.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc \
- TARGET_OBJCOPY=/opt/gcc-9.2.0-nolibc/aarch64-linux/bin/aarch64-linux-objcopy \
- TARGET_STRIP=/opt/gcc-9.2.0-nolibc/aarch64-linux/bin/aarch64-linux-strip \
- TARGET_NM=/opt/gcc-9.2.0-nolibc/aarch64-linux/bin/aarch64-linux-nm \
- TARGET_RANLIB=/opt/gcc-9.2.0-nolibc/aarch64-linux/bin/aarch64-linux-ranlib && \
+ TARGET_CC=/opt/gcc-11.1.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc \
+ TARGET_OBJCOPY=/opt/gcc-11.1.0-nolibc/aarch64-linux/bin/aarch64-linux-objcopy \
+ TARGET_STRIP=/opt/gcc-11.1.0-nolibc/aarch64-linux/bin/aarch64-linux-strip \
+ TARGET_NM=/opt/gcc-11.1.0-nolibc/aarch64-linux/bin/aarch64-linux-nm \
+ TARGET_RANLIB=/opt/gcc-11.1.0-nolibc/aarch64-linux/bin/aarch64-linux-ranlib && \
make && \
./grub-mkimage -O arm64-efi -o /opt/grub/grubaa64.efi --prefix= -d \
grub-core cat chain configfile echo efinet ext2 fat halt help linux \
@@ -139,11 +136,11 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \
make clean && \
./configure --target=arm --with-platform=efi \
CC=gcc \
- TARGET_CC=/opt/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc \
- TARGET_OBJCOPY=/opt/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-objcopy \
- TARGET_STRIP=/opt/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-strip \
- TARGET_NM=/opt/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-nm \
- TARGET_RANLIB=/opt/gcc-9.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ranlib && \
+ TARGET_CC=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc \
+ TARGET_OBJCOPY=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-objcopy \
+ TARGET_STRIP=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-strip \
+ TARGET_NM=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-nm \
+ TARGET_RANLIB=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ranlib && \
make && \
./grub-mkimage -O arm-efi -o /opt/grub/grubarm.efi --prefix= -d \
grub-core cat chain configfile echo efinet ext2 fat halt help linux \
@@ -153,31 +150,17 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \
make clean && \
./configure --target=riscv64 --with-platform=efi \
CC=gcc \
- TARGET_CC=/opt/gcc-9.2.0-nolibc/riscv64-linux/bin/riscv64-linux-gcc \
- TARGET_OBJCOPY=/opt/gcc-9.2.0-nolibc/riscv64-linux/bin/riscv64-linux-objcopy \
- TARGET_STRIP=/opt/gcc-9.2.0-nolibc/riscv64-linux/bin/riscv64-linux-strip \
- TARGET_NM=/opt/gcc-9.2.0-nolibc/riscv64-linux/bin/riscv64-linux-nm \
- TARGET_RANLIB=/opt/gcc-9.2.0-nolibc/riscv64-linux/bin/riscv64-linux-ranlib && \
+ TARGET_CC=/opt/gcc-11.1.0-nolibc/riscv64-linux/bin/riscv64-linux-gcc \
+ TARGET_OBJCOPY=/opt/gcc-11.1.0-nolibc/riscv64-linux/bin/riscv64-linux-objcopy \
+ TARGET_STRIP=/opt/gcc-11.1.0-nolibc/riscv64-linux/bin/riscv64-linux-strip \
+ TARGET_NM=/opt/gcc-11.1.0-nolibc/riscv64-linux/bin/riscv64-linux-nm \
+ TARGET_RANLIB=/opt/gcc-11.1.0-nolibc/riscv64-linux/bin/riscv64-linux-ranlib && \
make && \
./grub-mkimage -O riscv64-efi -o /opt/grub/grubriscv64.efi --prefix= -d \
grub-core cat chain configfile echo efinet ext2 fat halt help linux \
lsefisystab loadenv lvm minicmd normal part_msdos part_gpt reboot \
search search_fs_file search_fs_uuid search_label serial sleep test \
true && \
- make clean && \
- ./configure --target=riscv32 --with-platform=efi \
- CC=gcc \
- TARGET_CC=/opt/gcc-9.2.0-nolibc/riscv32-linux/bin/riscv32-linux-gcc \
- TARGET_OBJCOPY=/opt/gcc-9.2.0-nolibc/riscv32-linux/bin/riscv32-linux-objcopy \
- TARGET_STRIP=/opt/gcc-9.2.0-nolibc/riscv32-linux/bin/riscv32-linux-strip \
- TARGET_NM=/opt/gcc-9.2.0-nolibc/riscv32-linux/bin/riscv32-linux-nm \
- TARGET_RANLIB=/opt/gcc-9.2.0-nolibc/riscv32-linux/bin/riscv32-linux-ranlib && \
- make && \
- ./grub-mkimage -O riscv32-efi -o /opt/grub/grubriscv32.efi --prefix= -d \
- grub-core cat chain configfile echo efinet ext2 fat halt help linux \
- lsefisystab loadenv lvm minicmd normal part_msdos part_gpt reboot \
- search search_fs_file search_fs_uuid search_label serial sleep test \
- true && \
rm -rf /tmp/grub
RUN git clone git://git.qemu.org/qemu.git /tmp/qemu && \
@@ -195,9 +178,9 @@ USER uboot:uboot
# Create the buildman config file
RUN /bin/echo -e "[toolchain]\nroot = /usr" > ~/.buildman
-RUN /bin/echo -e "kernelorg = /opt/gcc-9.2.0-nolibc/*" >> ~/.buildman
-RUN /bin/echo -e "arc = /opt/arc_gnu_2019.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
-RUN /bin/echo -e "\n[toolchain-prefix]\nxtensa = /opt/2018.02/xtensa-dc233c-elf/bin/xtensa-dc233c-elf-" >> ~/.buildman;
+RUN /bin/echo -e "kernelorg = /opt/gcc-11.1.0-nolibc/*" >> ~/.buildman
+RUN /bin/echo -e "arc = /opt/arc_gnu_2021.03_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
+RUN /bin/echo -e "\n[toolchain-prefix]\nxtensa = /opt/2020.07/xtensa-dc233c-elf/bin/xtensa-dc233c-elf-" >> ~/.buildman;
RUN /bin/echo -e "\nnds32 = /opt/nds32le-linux-glibc-v3-upstream/bin/nds32le-linux-" >> ~/.buildman;
RUN /bin/echo -e "\n[toolchain-alias]\nsh = sh2" >> ~/.buildman
RUN /bin/echo -e "\nriscv = riscv64" >> ~/.buildman