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-rw-r--r--drivers/pci/pcie_dw_mvebu.c6
-rw-r--r--drivers/spi/cadence_qspi.c3
2 files changed, 4 insertions, 5 deletions
diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
index a0b82c78321..3b2ada5464e 100644
--- a/drivers/pci/pcie_dw_mvebu.c
+++ b/drivers/pci/pcie_dw_mvebu.c
@@ -569,9 +569,9 @@ static int pcie_dw_mvebu_of_to_plat(struct udevice *dev)
return -EINVAL;
/* Get the config space base address and size */
- pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1,
- &pcie->cfg_size);
- if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
+ pcie->cfg_base = devfdt_get_addr_size_index_ptr(dev, 1,
+ &pcie->cfg_size);
+ if (!pcie->cfg_base)
return -EINVAL;
return 0;
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index f931e4cf3e2..ac81468a184 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -390,8 +390,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus)
ofnode subnode;
plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
- plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
- &plat->ahbsize);
+ plat->ahbbase = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahbsize);
plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);