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-rw-r--r--MAINTAINERS7
-rw-r--r--arch/riscv/cpu/th1520/Makefile2
-rw-r--r--arch/riscv/cpu/th1520/cache.c2
-rw-r--r--arch/riscv/dts/thead-th1520-binman.dtsi32
-rw-r--r--common/spl/Kconfig2
-rw-r--r--configs/starfive_visionfive2_defconfig1
-rw-r--r--configs/th1520_lpi4a_defconfig2
-rw-r--r--configs/xilinx_mbv32_defconfig1
-rw-r--r--configs/xilinx_mbv32_smode_defconfig1
-rw-r--r--configs/xilinx_mbv64_defconfig1
-rw-r--r--configs/xilinx_mbv64_smode_defconfig1
-rw-r--r--doc/board/thead/lpi4a.rst125
12 files changed, 76 insertions, 101 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 111e2767917..503b07149d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1569,6 +1569,13 @@ F: drivers/clk/clk_k210.c
F: drivers/pinctrl/pinctrl-k210.c
F: include/k210/
+RISC-V T-HEAD TH1520
+M: Yao Zi <ziyao@disroot.org>
+S: Maintained
+F: arch/riscv/cpu/th1520/
+F: drivers/clk/thead/clk-th1520-ap.c
+F: drivers/ram/thead/th1520_ddr.c
+
RNG
M: Sughosh Ganu <sughosh.ganu@linaro.org>
R: Heinrich Schuchardt <xypron.glpk@gmx.de>
diff --git a/arch/riscv/cpu/th1520/Makefile b/arch/riscv/cpu/th1520/Makefile
index 5d806c06e2e..d971ea7390d 100644
--- a/arch/riscv/cpu/th1520/Makefile
+++ b/arch/riscv/cpu/th1520/Makefile
@@ -5,4 +5,4 @@
obj-y += cache.o
obj-y += cpu.o
obj-y += dram.o
-obj-y += spl.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/arch/riscv/cpu/th1520/cache.c b/arch/riscv/cpu/th1520/cache.c
index 08aa1f789fd..b2fec229363 100644
--- a/arch/riscv/cpu/th1520/cache.c
+++ b/arch/riscv/cpu/th1520/cache.c
@@ -11,6 +11,7 @@
#define CSR_MHCR_IE BIT(0)
#define CSR_MHCR_DE BIT(1)
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
void icache_enable(void)
{
csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_IE);
@@ -30,3 +31,4 @@ int dcache_status(void)
{
return (csr_read(CSR_MHCR) & CSR_MHCR_DE) != 0;
}
+#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
diff --git a/arch/riscv/dts/thead-th1520-binman.dtsi b/arch/riscv/dts/thead-th1520-binman.dtsi
index f060639e1c6..7b535e8402c 100644
--- a/arch/riscv/dts/thead-th1520-binman.dtsi
+++ b/arch/riscv/dts/thead-th1520-binman.dtsi
@@ -30,24 +30,48 @@
fit,fdt-list = "of-list";
images {
+ opensbi {
+ description = "OpenSBI fw_dynamic Firmware";
+ type = "firmware";
+ os = "opensbi";
+ arch = "riscv";
+ load = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
+ entry = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
+
+ opensbi_blob: opensbi {
+ filename = "fw_dynamic.bin";
+ missing-msg = "opensbi";
+ };
+ };
+
uboot {
description = "U-Boot";
type = "standalone";
+ firmware = "opensbi";
os = "U-boot";
arch = "riscv";
compression = "none";
load = /bits/ 64 <CONFIG_TEXT_BASE>;
- uboot_blob: u-boot {
+ uboot_nodtb_blob: u-boot-nodtb {
};
};
+
+ @fdt-SEQ {
+ fit,operation = "gen-fdt-nodes";
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+ };
};
configurations {
- default = "conf-th1520-lichee-pi-4a";
+ default = "@conf-DEFAULT-SEQ";
- conf-th1520-lichee-pi-4a {
- description = "th1520-lichee-pi-4a";
+ @conf-SEQ {
+ description = "NAME";
+ fdt = "fdt-SEQ";
+ firmware = "opensbi";
loadables = "uboot";
};
};
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index be87b3e63fd..880192043c4 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -488,7 +488,7 @@ config SPL_CUSTOM_SYS_MALLOC_ADDR
config SPL_SYS_MALLOC_SIZE
hex "Size of the SPL malloc pool"
depends on SPL_SYS_MALLOC
- default 0x180000 if BIOSEMU && RISCV
+ default 0x800000 if RISCV
default 0x100000
config SPL_READ_ONLY
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index e145ced8db8..6982d422a82 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -56,7 +56,6 @@ CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x400000
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig
index b19dc009fde..68745395293 100644
--- a/configs/th1520_lpi4a_defconfig
+++ b/configs/th1520_lpi4a_defconfig
@@ -11,6 +11,7 @@ CONFIG_SYS_LOAD_ADDR=0x80200000
# CONFIG_SMP is not set
CONFIG_TARGET_TH1520_LPI4A=y
CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_SYS_BOOT_GET_CMDLINE=y
CONFIG_SYS_BOOT_GET_KBD=y
@@ -107,4 +108,3 @@ CONFIG_SPL_MMC_y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x10000000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x400000
diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index 861d1475453..c3f33d6454d 100644
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -29,7 +29,6 @@ CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_CMD_MII is not set
CONFIG_CMD_TIMER=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig
index 9398b4c240d..c588bd563ac 100644
--- a/configs/xilinx_mbv32_smode_defconfig
+++ b/configs/xilinx_mbv32_smode_defconfig
@@ -30,7 +30,6 @@ CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
# CONFIG_CMD_MII is not set
CONFIG_CMD_TIMER=y
diff --git a/configs/xilinx_mbv64_defconfig b/configs/xilinx_mbv64_defconfig
index c39925bd86a..c2c677d7443 100644
--- a/configs/xilinx_mbv64_defconfig
+++ b/configs/xilinx_mbv64_defconfig
@@ -30,7 +30,6 @@ CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_CMD_MII is not set
CONFIG_CMD_TIMER=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/xilinx_mbv64_smode_defconfig b/configs/xilinx_mbv64_smode_defconfig
index 811f93a2671..7a26c85dfb7 100644
--- a/configs/xilinx_mbv64_smode_defconfig
+++ b/configs/xilinx_mbv64_smode_defconfig
@@ -31,7 +31,6 @@ CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
# CONFIG_CMD_MII is not set
CONFIG_CMD_TIMER=y
diff --git a/doc/board/thead/lpi4a.rst b/doc/board/thead/lpi4a.rst
index 7e4c4ea81ee..acd7ac2698d 100644
--- a/doc/board/thead/lpi4a.rst
+++ b/doc/board/thead/lpi4a.rst
@@ -55,123 +55,70 @@ DDR driver requires a firmware to function, to build it:
cd th1520-firmware
lua5.4 ddr-generate.lua src/<CONFIGURATION_NAME>.lua th1520-ddr-firmware.bin
-4. Build U-Boot images
+4. Build OpenSBI Firmware
-The U-Boot is capable of running in M-Mode, so we can directly build it without
-OpenSBI. The DDR firmware should be copied to U-Boot source directory before
+TH1520 port of proper U-Boot runs in S mode, thus OpenSBI is required as
+SBI firmware to setup S-mode environment and provide SBI calls. It could
+be cloned and built for TH1520 as below,
+
+.. code-block:: bash
+
+ git clone https://github.com/riscv-software-src/opensbi.git
+ cd opensbi
+ make PLATFORM=generic
+
+TH1520 support in OpenSBI requires v1.2 or a more recent version.
+
+More detailed description of steps required to build fw_dynamic firmware
+is beyond the scope of this document. Please refer to OpenSBI
+documenation.
+
+5. Build U-Boot images
+
+The DDR firmware should be copied to U-Boot source directory before
building.
-.. code-block:: console
+.. code-block:: bash
cd <U-Boot-dir>
cp <path-to-ddr-firmware> th1520-ddr-firmware.bin
make th1520_lpi4a_defconfig
- make
+ make OPENSBI=<opensbi_dir>/build/platform/generic/firmware/fw_dynamic.bin
-This will generate u-boot-dtb.bin and u-boot-with-spl.bin. The former contains
-only proper U-Boot and is for chainloading; the later contains also SPL and
-DDR firmware and is ready for booting by BROM directly.
+This will generate u-boot-with-spl.bin, which contains SPL, DDR firmware,
+OpenSBI firmware and proper U-Boot.
Booting
~~~~~~~
-Currently, we rely on vendor u-boot to initialize the clock, pinctrl subsystem,
-and chain load the mainline u-boot image either via tftp or emmc storage,
-then bootup from it.
-
-Sample boot log from Lichee PI 4A board via tftp
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-.. code-block:: none
-
- brom_ver 8
- [APP][E] protocol_connect failed, exit.
-
- U-Boot SPL 2020.01-00016-g8c870a6be8 (May 20 2023 - 01:04:49 +0000)
- FM[1] lpddr4x dualrank freq=3733 64bit dbi_off=n sdram init
- ddr initialized, jump to uboot
- image has no header
+u-boot-with-spl.bin should be loaded to SRAM through fastboot. Connect
+the board to computer with Type-C cable and run
+.. code-block:: bash
- U-Boot 2020.01-00016-g8c870a6be8 (May 20 2023 - 01:04:49 +0000)
+ fastboot flash ram u-boot-with-spl.bin
+ fastboot reboot
- CPU: rv64imafdcvsu
- Model: T-HEAD c910 light
- DRAM: 8 GiB
- C910 CPU FREQ: 750MHz
- AHB2_CPUSYS_HCLK FREQ: 250MHz
- AHB3_CPUSYS_PCLK FREQ: 125MHz
- PERISYS_AHB_HCLK FREQ: 250MHz
- PERISYS_APB_PCLK FREQ: 62MHz
- GMAC PLL POSTDIV FREQ: 1000MHZ
- DPU0 PLL POSTDIV FREQ: 1188MHZ
- DPU1 PLL POSTDIV FREQ: 1188MHZ
- MMC: sdhci@ffe7080000: 0, sd@ffe7090000: 1
- Loading Environment from MMC... OK
- Error reading output register
- Warning: cannot get lcd-en GPIO
- LCD panel cannot be found : -121
- splash screen startup cost 16 ms
- In: serial
- Out: serial
- Err: serial
- Net:
- Warning: ethernet@ffe7070000 using MAC address from ROM
- eth0: ethernet@ffe7070000ethernet@ffe7070000:0 is connected to ethernet@ffe7070000. Reconnecting to ethernet@ffe7060000
-
- Warning: ethernet@ffe7060000 (eth1) using random MAC address - 42:25:d4:16:5f:fc
- , eth1: ethernet@ffe7060000
- Hit any key to stop autoboot: 2
- ethernet@ffe7060000 Waiting for PHY auto negotiation to complete.. done
- Speed: 1000, full duplex
- Using ethernet@ffe7070000 device
- TFTP from server 192.168.8.50; our IP address is 192.168.8.45
- Filename 'u-boot-dtb.bin'.
- Load address: 0x1c00000
- Loading: * #########################
- 8 MiB/s
- done
- Bytes transferred = 376686 (5bf6e hex)
- ## Starting application at 0x01C00000 ...
-
- U-Boot 2023.07-rc2-00004-g1befbe31c1 (May 23 2023 - 18:40:01 +0800)
-
- CPU: rv64imafdc
- Model: Sipeed Lichee Pi 4A
- DRAM: 8 GiB
- Core: 13 devices, 6 uclasses, devicetree: separate
- Loading Environment from <NULL>... OK
- In: serial@ffe7014000
- Out: serial@ffe7014000
- Err: serial@ffe7014000
- Model: Sipeed Lichee Pi 4A
- LPI4A=>
-
-SPL support is still in an early stage and not all of the functionalities are
-available when booting from mainline SPL. When using mainline SPL,
-u-boot-with-spl.bin should be loaded to SRAM through fastboot.
-
-Sample boot log from Lichee PI 4A board via fastboot and mainline SPL
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Sample boot log from Lichee PI 4A board via fastboot
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
.. code-block:: none
- brom_ver 8
[APP][E] protocol_connect failed, exit.
- Starting download of 636588 bytes
+ Starting download of 940681 bytes
- downloading of 636588 bytes finished
+ downloading of 940681 bytes finished
- U-Boot SPL 2025.04-rc2-00049-geaa9fc99d4cd-dirty (Apr 26 2025 - 13:31:41 +0000)
+ U-Boot SPL 2025.07-rc3-00005-g3a0ef515b8bb (May 29 2025 - 10:42:46 +0000)
Trying to boot from RAM
- U-Boot 2025.04-rc2-00049-geaa9fc99d4cd-dirty (Apr 26 2025 - 13:31:41 +0000)
+ U-Boot 2025.07-rc3-00005-g3a0ef515b8bb (May 29 2025 - 10:42:46 +0000)
CPU: thead,c910
Model: Sipeed Lichee Pi 4A
DRAM: 8 GiB
- Core: 30 devices, 9 uclasses, devicetree: separate
+ Core: 110 devices, 9 uclasses, devicetree: separate
MMC: mmc@ffe7080000: 0, mmc@ffe7090000: 1
Loading Environment from <NULL>... OK
In: serial@ffe7014000
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-04 00:02:15 +0000