diff options
297 files changed, 7473 insertions, 2640 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index ba351b9802d..bd197cd6e66 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -89,6 +89,7 @@ stages: options: $(container_option) steps: - script: | + set -e virtualenv -p /usr/bin/python3 /tmp/venvhtml . /tmp/venvhtml/bin/activate pip install -r doc/sphinx/requirements.txt @@ -295,7 +296,7 @@ stages: export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:\${PATH} export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci # "\${var:+"-k \$var"}" expands to "" if \$var is empty, "-k \$var" if not - ./test/py/test.py -ra -o cache_dir="\$UBOOT_TRAVIS_BUILD_DIR"/.pytest_cache --bd \${TEST_PY_BD} \${TEST_PY_ID} \${TEST_PY_TEST_SPEC:+"-k \${TEST_PY_TEST_SPEC}"} --build-dir "\$UBOOT_TRAVIS_BUILD_DIR" --report-dir "\$UBOOT_TRAVIS_BUILD_DIR" --junitxml=\$(System.DefaultWorkingDirectory)/results.xml + ./test/py/test.py -ra -o cache_dir="\$UBOOT_TRAVIS_BUILD_DIR"/.pytest_cache --bd \${TEST_PY_BD} \${TEST_PY_ID} \${TEST_PY_EXTRA} \${TEST_PY_TEST_SPEC:+"-k \${TEST_PY_TEST_SPEC}"} --build-dir "\$UBOOT_TRAVIS_BUILD_DIR" --report-dir "\$UBOOT_TRAVIS_BUILD_DIR" --junitxml=\$(System.DefaultWorkingDirectory)/results.xml # the below corresponds to .gitlab-ci.yml "after_script" rm -rf /tmp/uboot-test-hooks /tmp/venv EOF @@ -318,6 +319,7 @@ stages: matrix: sandbox: TEST_PY_BD: "sandbox" + TEST_PY_EXTRA: "--timing" sandbox_asan: TEST_PY_BD: "sandbox" OVERRIDE: "-a ASAN" diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 74dc05d58a7..920f61eaa09 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -96,7 +96,7 @@ stages: # "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not - export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH}; export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci; - ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID} + ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID} ${TEST_PY_EXTRA} ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"} --build-dir "$UBOOT_TRAVIS_BUILD_DIR" --junitxml=/tmp/${TEST_PY_BD}/results.xml @@ -105,6 +105,7 @@ stages: paths: - "*.html" - "*.css" + - results.xml reports: junit: results.xml expire_in: 1 week @@ -230,30 +231,47 @@ Check packing of Python tools: # Test sandbox with test.py sandbox test.py: + parallel: + matrix: + - HOST: "fast arm64" + - HOST: "fast amd64" tags: - - ${DEFAULT_AMD64_TAG} + - ${HOST} variables: TEST_PY_BD: "sandbox" + TEST_PY_EXTRA: "--timing" <<: *buildman_and_testpy_dfn sandbox with clang test.py: + parallel: + matrix: + - HOST: "fast arm64" + - HOST: "fast amd64" tags: - - ${DEFAULT_AMD64_TAG} + - ${HOST} variables: TEST_PY_BD: "sandbox" OVERRIDE: "-O clang-17" <<: *buildman_and_testpy_dfn sandbox64 test.py: + parallel: + matrix: + - HOST: "fast arm64" + - HOST: "fast amd64" tags: - - ${DEFAULT_AMD64_TAG} + - ${HOST} variables: TEST_PY_BD: "sandbox64" <<: *buildman_and_testpy_dfn sandbox64 with clang test.py: + parallel: + matrix: + - HOST: "fast arm64" + - HOST: "fast amd64" tags: - - ${DEFAULT_AMD64_TAG} + - ${HOST} variables: TEST_PY_BD: "sandbox64" OVERRIDE: "-O clang-17" @@ -522,9 +540,6 @@ coreboot test.py: dependencies: [] tags: [ 'lab' ] script: - - if [[ -z "${SJG_LAB}" ]]; then - exit 0; - fi # Environment: # SRC - source tree # OUT - output directory for builds diff --git a/MAINTAINERS b/MAINTAINERS index dc8e048dde4..10f7f1fd180 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -386,6 +386,14 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git F: drivers/pci/pci-aardvark.c F: drivers/pci/pci_mvebu.c +ARM MARVELL PXA1908 +M: Duje Mihanović <duje.mihanovic@skole.hr> +S: Maintained +T: git git://git.dujemihanovic.xyz/u-boot.git +F: arch/arm/dts/pxa1908* +F: arch/arm/mach-mmp/ +F: include/configs/pxa1908.h + ARM MARVELL SERIAL DRIVERS M: Pali Rohár <pali@kernel.org> M: Stefan Roese <sr@denx.de> @@ -1798,6 +1806,13 @@ M: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> S: Maintained F: test/lib/uuid.c +VBE +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: boot/vbe* +F: common/spl_reloc.c +F: include/vbe.h + VIDEO M: Anatolij Gustschin <agust@denx.de> S: Maintained @@ -3,7 +3,7 @@ VERSION = 2025 PATCHLEVEL = 04 SUBLEVEL = -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc2 NAME = # *DOCUMENTATION* diff --git a/api/Kconfig b/api/Kconfig index b5a7399d7f3..8cfd98ad6a6 100644 --- a/api/Kconfig +++ b/api/Kconfig @@ -19,24 +19,4 @@ config EXAMPLES U-Boot provides an API for standalone applications. Examples are provided in directory examples/. -config STANDALONE_LOAD_ADDR - depends on EXAMPLES - hex "Address in memory to link standalone applications to" - default 0xffffffff80200000 if MIPS && 64BIT - default 0x8c000000 if SH - default 0x82000000 if ARC - default 0x80f00000 if MICROBLAZE - default 0x80300000 if ARCH_OMAP2PLUS || FSL_LSCH2 || FSL_LSCH3 - default 0x80200000 if MIPS && 32BIT - default 0x0c100000 if ARM - default 0x02000000 if NIOS2 - default 0x00040000 if PPC || X86 - default 0x00020000 if M68K - default 0x0 if RISCV - default SYS_LOAD_ADDR - help - This option defines a board specific value for the address where - standalone program gets loaded, thus overwriting the architecture - dependent default settings. - endmenu diff --git a/api/api_platform.c b/api/api_platform.c index 7a789bd2016..d5cbcd6e201 100644 --- a/api/api_platform.c +++ b/api/api_platform.c @@ -17,9 +17,15 @@ int platform_sys_info(struct sys_info *si) { int i; + si->clk_bus = gd->bus_clk; + si->clk_cpu = gd->cpu_clk; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) platform_set_mr(si, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size, MR_ATTR_DRAM); + platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM); + platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH); + return 1; } diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 314916527c9..da6f1174934 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -108,6 +108,9 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE The value subtracted from CONFIG_TEXT_BASE to calculate the TEXT_OFFSET value written to the Linux kernel image header. +config NVIC + bool + config GICV2 bool @@ -117,6 +120,7 @@ config GICV3 config DRIVER_GICV2 bool "ARM GICV2 driver" select IRQ + depends on !NVIC help ARM GICV2 driver. Basic support for parsing the GICV2 node and generate ACPI tables. @@ -124,6 +128,7 @@ config DRIVER_GICV2 config GIC_V3_ITS bool "ARM GICV3 ITS" select IRQ + depends on !NVIC help ARM GICV3 Interrupt translation service (ITS). Basic support for programming locality specific peripheral @@ -134,6 +139,7 @@ config GIC_V3_ITS config GICV3_SUPPORT_GIC600 bool "ARM GICV3 GIC600 SUPPORT" + depends on !NVIC help ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, implements a power control register in the Redistributor frame.This @@ -193,6 +199,7 @@ config SPL_SYS_DCACHE_OFF config SYS_ARM_CACHE_CP15 bool "CP15 based cache enabling support" + depends on !CPU_V7M help Select this if your processor suports enabling caches by using CP15 registers. @@ -200,6 +207,7 @@ config SYS_ARM_CACHE_CP15 config SYS_ARM_MMU bool "MMU-based Paged Memory Management Support" select SYS_ARM_CACHE_CP15 + depends on !CPU_V7M help Select if you want MMU-based virtualised addressing space support via paged memory management. @@ -350,6 +358,7 @@ config CPU_V7M select SYS_CACHE_SHIFT_5 select SYS_THUMB_BUILD select THUMB2_KERNEL + select NVIC config CPU_V7R bool @@ -842,6 +851,15 @@ config ARCH_MEDIATEK Support for the MediaTek SoCs family developed by MediaTek Inc. Please refer to doc/README.mediatek for more information. +config ARCH_MMP + bool "Marvell MMP" + select ARM64 + select DM + select DM_SERIAL + select OF_CONTROL + select SAVE_PREV_BL_FDT_ADDR + select SAVE_PREV_BL_INITRAMFS_START_ADDR + config ARCH_LPC32XX bool "NXP LPC32xx platform" select CPU_ARM926EJS @@ -2184,6 +2202,7 @@ config SERIAL_TAG config STATIC_MACH_TYPE bool "Statically define the Machine ID number" default y if TARGET_DS109 || TARGET_DS414 || DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac" + depends on SUPPORT_PASSING_ATAGS help When booting via ATAGs, enable this option if we know the correct machine ID number to use at compile time. Some systems will be @@ -2310,6 +2329,8 @@ source "arch/arm/mach-meson/Kconfig" source "arch/arm/mach-mediatek/Kconfig" +source "arch/arm/mach-mmp/Kconfig" + source "arch/arm/mach-qemu/Kconfig" source "arch/arm/mach-rockchip/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index cb87a684754..7334e79965f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -69,6 +69,7 @@ machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx machine-$(CONFIG_ARCH_MEDIATEK) += mediatek machine-$(CONFIG_ARCH_MESON) += meson +machine-$(CONFIG_ARCH_MMP) += mmp machine-$(CONFIG_ARCH_MVEBU) += mvebu machine-$(CONFIG_ARCH_NEXELL) += nexell machine-$(CONFIG_ARCH_NPCM) += npcm diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b7df72453ac..0bf3697bdbe 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1226,6 +1226,8 @@ dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \ corstone1000-fvp.dtb +dtb-$(CONFIG_TARGET_COREPRIMEVELTE) += pxa1908-samsung-coreprimevelte.dtb + include $(srctree)/scripts/Makefile.dts # Add any required device tree compiler flags here diff --git a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi index 8f3c3a185ae..c68a48678a2 100644 --- a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi @@ -72,6 +72,14 @@ bootph-all; }; +&main_i2c0 { + bootph-all; +}; + +&main_i2c0_pins_default { + bootph-all; +}; + &main_mmc1_pins_default { bootph-all; }; diff --git a/arch/arm/dts/mt7981-emmc-rfb.dts b/arch/arm/dts/mt7981-emmc-rfb.dts index d6590f01cf8..ebfcee5a2ea 100644 --- a/arch/arm/dts/mt7981-emmc-rfb.dts +++ b/arch/arm/dts/mt7981-emmc-rfb.dts @@ -47,8 +47,8 @@ status = "okay"; mediatek,gmac-id = <0>; phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; + mediatek,switch = "auto"; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; @@ -56,7 +56,7 @@ }; }; -&pinctrl { +&pio { spic_pins: spi1-pins-func-1 { mux { function = "spi"; diff --git a/arch/arm/dts/mt7981-rfb.dts b/arch/arm/dts/mt7981-rfb.dts index d6ebd6539c3..17e6b5af7a2 100644 --- a/arch/arm/dts/mt7981-rfb.dts +++ b/arch/arm/dts/mt7981-rfb.dts @@ -38,8 +38,8 @@ status = "okay"; mediatek,gmac-id = <0>; phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; + mediatek,switch = "auto"; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; @@ -47,7 +47,7 @@ }; }; -&pinctrl { +&pio { spi_flash_pins: spi0-pins-func-1 { mux { function = "flash"; diff --git a/arch/arm/dts/mt7981-sd-rfb.dts b/arch/arm/dts/mt7981-sd-rfb.dts index 2adbc374725..672124657ca 100644 --- a/arch/arm/dts/mt7981-sd-rfb.dts +++ b/arch/arm/dts/mt7981-sd-rfb.dts @@ -47,8 +47,8 @@ status = "okay"; mediatek,gmac-id = <0>; phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; + mediatek,switch = "auto"; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; @@ -56,7 +56,7 @@ }; }; -&pinctrl { +&pio { spic_pins: spi1-pins-func-1 { mux { function = "spi"; diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi index 2844ab010de..5b4cadc22f7 100644 --- a/arch/arm/dts/mt7981.dtsi +++ b/arch/arm/dts/mt7981.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h> #include <dt-bindings/clock/mt7981-clk.h> #include <dt-bindings/reset/mt7629-reset.h> #include <dt-bindings/pinctrl/mt65xx.h> @@ -106,7 +107,7 @@ bootph-all; }; - pinctrl: pinctrl@11d00000 { + pio: pinctrl@11d00000 { compatible = "mediatek,mt7981-pinctrl"; reg = <0x11d00000 0x1000>, <0x11c00000 0x1000>, @@ -117,13 +118,11 @@ <0x11f00000 0x1000>, <0x11f10000 0x1000>, <0x1000b000 0x1000>; - reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base", - "iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base", - "iocfg_tm_base", "iocfg_tl_base", "eint"; - gpio: gpio-controller { - gpio-controller; - #gpio-cells = <2>; - }; + reg-names = "gpio", "iocfg_rt", "iocfg_rm", + "iocfg_rb", "iocfg_lb", "iocfg_bl", + "iocfg_tm", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; }; pwm: pwm@10048000 { @@ -317,4 +316,86 @@ status = "disabled"; }; + xhci: xhci@11200000 { + compatible = "mediatek,mt7981-xhci", + "mediatek,mtk-xhci"; + reg = <0x11200000 0x2e00>, + <0x11203e00 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, + <&infracfg CLK_INFRA_IUSB_CK>, + <&infracfg CLK_INFRA_IUSB_133_CK>, + <&infracfg CLK_INFRA_IUSB_66M_CK>, + <&topckgen CLK_TOP_U2U3_XHCI_SEL>; + clock-names = "sys_ck", + "ref_ck", + "mcu_ck", + "dma_ck", + "xhci_ck"; + mediatek,u3p-dis-msk = <0x1>; + status = "okay"; + }; + + pcie: pcie@11280000 { + compatible = "mediatek,mt8192-pcie"; + device_type = "pci"; + reg = <0x11280000 0x4000>; + reg-names = "pcie-mac"; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_IPCIE_CK>, + <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, + <&infracfg CLK_INFRA_IPCIER_CK>, + <&infracfg CLK_INFRA_IPCIEB_CK>; + clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + phys = <&u3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; + + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + + status = "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <0>; + }; + }; + + usbtphy: usb-phy@11e10000 { + compatible = "mediatek,mt7981", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + u2port0: usb-phy@11e10000 { + reg = <0x11e10000 0x700>; + clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@11e10700 { + reg = <0x11e10700 0x900>; + clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,syscon-type = <&topmisc 0x218 0>; + status = "okay"; + }; + }; }; diff --git a/arch/arm/dts/mt7986-u-boot.dtsi b/arch/arm/dts/mt7986-u-boot.dtsi index 096b97371b8..71e83304c74 100644 --- a/arch/arm/dts/mt7986-u-boot.dtsi +++ b/arch/arm/dts/mt7986-u-boot.dtsi @@ -28,6 +28,6 @@ bootph-all; }; -&pinctrl { +&pio { bootph-all; }; diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi index f871f2394c5..b2c57098a5e 100644 --- a/arch/arm/dts/mt7986.dtsi +++ b/arch/arm/dts/mt7986.dtsi @@ -122,7 +122,7 @@ #clock-cells = <1>; }; - pinctrl: pinctrl@1001f000 { + pio: pinctrl@1001f000 { compatible = "mediatek,mt7986-pinctrl"; reg = <0x1001f000 0x1000>, <0x11c30000 0x1000>, @@ -132,13 +132,11 @@ <0x11f00000 0x1000>, <0x11f10000 0x1000>, <0x1000b000 0x1000>; - reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base", - "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base", - "iocfg_tl_base", "eint"; - gpio: gpio-controller { - gpio-controller; - #gpio-cells = <2>; - }; + reg-names = "gpio", "iocfg_rt", "iocfg_rb", + "iocfg_lt", "iocfg_lb", "iocfg_tr", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; }; pwm: pwm@10048000 { diff --git a/arch/arm/dts/mt7986a-bpi-r3-sd.dts b/arch/arm/dts/mt7986a-bpi-r3-sd.dts index c156a813634..e01ae4c3dc7 100644 --- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts +++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts @@ -38,12 +38,12 @@ factory { label = "reset"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; }; wps { label = "wps"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; }; }; @@ -52,12 +52,12 @@ led_status_green: green { label = "green:status"; - gpios = <&gpio 69 GPIO_ACTIVE_HIGH>; + gpios = <&pio 69 GPIO_ACTIVE_HIGH>; }; led_status_blue: blue { label = "blue:status"; - gpios = <&gpio 86 GPIO_ACTIVE_HIGH>; + gpios = <&pio 86 GPIO_ACTIVE_HIGH>; }; }; @@ -78,7 +78,7 @@ mediatek,gmac-id = <0>; phy-mode = "2500base-x"; mediatek,switch = "mt7531"; - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; @@ -86,7 +86,7 @@ }; }; -&pinctrl { +&pio { spic_pins: spi1-pins-func-1 { mux { function = "spi"; diff --git a/arch/arm/dts/mt7986a-rfb.dts b/arch/arm/dts/mt7986a-rfb.dts index 67d14a99dae..d4bbb23204a 100644 --- a/arch/arm/dts/mt7986a-rfb.dts +++ b/arch/arm/dts/mt7986a-rfb.dts @@ -57,7 +57,7 @@ mediatek,gmac-id = <0>; phy-mode = "2500base-x"; mediatek,switch = "mt7531"; - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; @@ -65,7 +65,7 @@ }; }; -&pinctrl { +&pio { spi_flash_pins: spi0-pins-func-1 { mux { function = "flash"; diff --git a/arch/arm/dts/mt7986a-sd-rfb.dts b/arch/arm/dts/mt7986a-sd-rfb.dts index 4f8fa70ec99..11823e05bda 100644 --- a/arch/arm/dts/mt7986a-sd-rfb.dts +++ b/arch/arm/dts/mt7986a-sd-rfb.dts @@ -49,7 +49,7 @@ mediatek,gmac-id = <0>; phy-mode = "2500base-x"; mediatek,switch = "mt7531"; - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; @@ -57,7 +57,7 @@ }; }; -&pinctrl { +&pio { spi_flash_pins: spi0-pins-func-1 { mux { function = "flash"; diff --git a/arch/arm/dts/mt7986b-rfb.dts b/arch/arm/dts/mt7986b-rfb.dts index f98b04ab140..0a731fe87fd 100644 --- a/arch/arm/dts/mt7986b-rfb.dts +++ b/arch/arm/dts/mt7986b-rfb.dts @@ -48,7 +48,7 @@ mediatek,gmac-id = <0>; phy-mode = "2500base-x"; mediatek,switch = "mt7531"; - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; @@ -56,7 +56,7 @@ }; }; -&pinctrl { +&pio { spi_flash_pins: spi0-pins-func-1 { mux { function = "flash"; diff --git a/arch/arm/dts/mt7986b-sd-rfb.dts b/arch/arm/dts/mt7986b-sd-rfb.dts index ec80a2fb710..e5fb4d73e70 100644 --- a/arch/arm/dts/mt7986b-sd-rfb.dts +++ b/arch/arm/dts/mt7986b-sd-rfb.dts @@ -49,7 +49,7 @@ mediatek,gmac-id = <0>; phy-mode = "2500base-x"; mediatek,switch = "mt7531"; - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; @@ -57,7 +57,7 @@ }; }; -&pinctrl { +&pio { spi_flash_pins: spi0-pins-func-1 { mux { function = "flash"; diff --git a/arch/arm/dts/mt7987-emmc.dtsi b/arch/arm/dts/mt7987-emmc.dtsi new file mode 100644 index 00000000000..80ab04d9d20 --- /dev/null +++ b/arch/arm/dts/mt7987-emmc.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) + +#include "mt7987-pinctrl.dtsi" + +/ { + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +/* Disable spi0/spi1 node since MSDC shares pins with spi0 and spi1*/ +&spi0 { + status = "disabled"; +}; + +&spi1 { + status = "disabled"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc_pins_default>; + pinctrl-1 = <&mmc_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x12814>; + vqmmc-supply = <®_1p8v>; + vmmc-supply = <®_3p3v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7987-netsys-u-boot.dtsi b/arch/arm/dts/mt7987-netsys-u-boot.dtsi new file mode 100644 index 00000000000..3d6640b33ab --- /dev/null +++ b/arch/arm/dts/mt7987-netsys-u-boot.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +#include <dt-bindings/clock/mediatek,mt7987-clk.h> +#include <dt-bindings/reset/mt7988-reset.h> + +&netsys { + eth0: ethernet@15110100 { + compatible = "mediatek,mt7987-eth", "syscon"; + reg = <0 0x15100000 0 0x20000>; + mediatek,gmac-id = <0>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>; + mediatek,infracfg = <&topmisc>; + resets = <ðsys ETHDMA_FE_RST>; + reset-names = "fe"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth1: ethernet@15110200 { + compatible = "mediatek,mt7987-eth", "syscon"; + reg = <0 0x15100000 0 0x20000>; + mediatek,gmac-id = <1>; + mediatek,ethsys = <ðsys>; + mediatek,infracfg = <&topmisc>; + resets = <ðsys ETHDMA_FE_RST>; + reset-names = "fe"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth2: ethernet@15110300 { + compatible = "mediatek,mt7987-eth", "syscon"; + reg = <0 0x15100000 0 0x20000>; + mediatek,gmac-id = <2>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys1>; + mediatek,infracfg = <&topmisc>; + resets = <ðsys ETHDMA_FE_RST>; + reset-names = "fe"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/mt7987-pinctrl-u-boot.dtsi b/arch/arm/dts/mt7987-pinctrl-u-boot.dtsi new file mode 100644 index 00000000000..991f38efef9 --- /dev/null +++ b/arch/arm/dts/mt7987-pinctrl-u-boot.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/mt65xx.h> + +&pio { + /delete-node/ mmc-pins-default; + /delete-node/ mmc-pins-uhs; + /delete-node/ sd-pins-default; + /delete-node/ sd-pins-uhs; + /delete-node/ spi0-pins; + /delete-node/ spi2-pins; + + mmc_pins_default: mmc0default { + mux { + function = "flash"; + groups = "emmc_45"; + }; + + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI0_HOLD", "SPI0_WP", + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + + conf-rst { + pins = "USB_VBUS"; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + }; + + mmc_pins_uhs: mmc-pins-uhs { + mux { + function = "flash"; + groups = "emmc_45"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI0_HOLD", "SPI0_WP", + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-rst { + pins = "USB_VBUS"; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + }; + + sd_pins_default: sd-pins-default { + mux { + function = "flash"; + groups = "sd"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + }; + + sd_pins_uhs: sd-pins-uhs { + mux { + function = "flash"; + groups = "sd"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + }; + + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_11>; + }; + }; + + spi2_flash_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_11>; + }; + }; +}; diff --git a/arch/arm/dts/mt7987-pinctrl.dtsi b/arch/arm/dts/mt7987-pinctrl.dtsi new file mode 100644 index 00000000000..b5e643feffe --- /dev/null +++ b/arch/arm/dts/mt7987-pinctrl.dtsi @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +&pio { + mmc_pins_default: mmc-pins-default { + mux { + function = "flash"; + groups = "emmc_45"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI0_HOLD", "SPI0_WP", + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "USB_VBUS"; + drive-strength = <MTK_DRIVE_4mA>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + mmc_pins_uhs: mmc-pins-uhs { + mux { + function = "flash"; + groups = "emmc_45"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI0_HOLD", "SPI0_WP", + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "USB_VBUS"; + drive-strength = <MTK_DRIVE_4mA>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + sd_pins_default: sd-pins-default { + mux { + function = "flash"; + groups = "sd"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + }; + + sd_pins_uhs: sd-pins-uhs { + mux { + function = "flash"; + groups = "sd"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + }; + + mdio0_pins: mdio0-pins { + mux { + function = "eth"; + groups = "mdc_mdio"; + }; + + conf { + groups = "mdc_mdio"; + drive-strength = <MTK_DRIVE_6mA>; + }; + }; + + i2p5gbe_led0_pins: i2p5gbe0-pins { + mux { + function = "led"; + groups = "2p5gbe_led0"; + }; + }; + + i2p5gbe_led1_0_pins: i2p5gbe1-pins { + mux { + function = "led"; + groups = "2p5gbe_led1_0"; + }; + }; + + i2p5gbe_led1_1_pins: i2p5gbe2-pins { + mux { + function = "led"; + groups = "2p5gbe_led1_1"; + }; + }; + + i2c0_pins: i2c0-pins-g2 { + mux { + function = "i2c"; + groups = "i2c0_2"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie0_pereset", "pcie0_clkreq", + "pcie0_wake"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie1_pereset", "pcie1_clkreq", + "pcie1_wake"; + }; + }; + + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spic_pins: spi1-pins { + mux { + function = "spi"; + groups = "spi1"; + }; + }; + + spi2_flash_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + }; + + i2c1_pins: i2c1-pins { + mux { + function = "i2c"; + groups = "i2c0_2"; + }; + }; + + i2s_pins: i2s-pins { + mux { + function = "i2s"; + groups = "pcm0_1"; + }; + }; + + pcm_pins: pcm-pins { + mux { + function = "pcm"; + groups = "pcm0_1"; + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1_2"; + }; + }; +}; diff --git a/arch/arm/dts/mt7987-sd.dtsi b/arch/arm/dts/mt7987-sd.dtsi new file mode 100644 index 00000000000..4c8ca48c293 --- /dev/null +++ b/arch/arm/dts/mt7987-sd.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include "mt7987-pinctrl.dtsi" + +/ { + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +/* Disable spi0/spi1 node since MSDC shares pins with spi0 and spi1*/ +&spi0 { + status = "disabled"; +}; + +&spi1 { + status = "disabled"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&sd_pins_default>; + pinctrl-1 = <&sd_pins_uhs>; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + no-mmc; + no-sdio; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7987.dtsi b/arch/arm/dts/mt7987.dtsi new file mode 100644 index 00000000000..fd1585f658d --- /dev/null +++ b/arch/arm/dts/mt7987.dtsi @@ -0,0 +1,808 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/reset/ti-syscon.h> +#include <dt-bindings/clock/mediatek,mt7987-clk.h> +#include <dt-bindings/pinctrl/mt65xx.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/regulator/richtek,rt5190a-regulator.h> + +/ { + compatible = "mediatek,mt7987"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clkxtal: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "clkxtal"; + }; + + vproc: regulator-vproc { + compatible = "regulator-fixed"; + regulator-name = "proc"; + regulator-min-microvolt = <8500000>; + regulator-max-microvolt = <8500000>; + regulator-boot-on; + regulator-always-on; + }; + + firmware { + optee { + method = "smc"; + compatible = "linaro,optee-tz"; + status = "okay"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + reg = <0x0>; + clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&apmixedsys CLK_APMIXED_ARM_LL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + reg = <0x1>; + clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&apmixedsys CLK_APMIXED_ARM_LL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + reg = <0x2>; + clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&apmixedsys CLK_APMIXED_ARM_LL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + reg = <0x3>; + clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&apmixedsys CLK_APMIXED_ARM_LL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + opp00 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <850000>; + }; + opp01 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <850000>; + }; + opp02 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <850000>; + }; + opp03 { + opp-hz = /bits/ 64 <2000000000>; + opp-microvolt = <850000>; + }; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + clk40m: clk40m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + + clkitg: clkitg { + compatible = "simple-bus"; + status = "disabled"; + }; + + clksys: soc_clksys { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt7987-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + topckgen: topckgen@1001b000 { + compatible = "mediatek,mt7987-topckgen", "syscon"; + reg = <0 0x1001b000 0 0x1000>; + #clock-cells = <1>; + }; + + apmixedsys: apmixedsys@1001e000 { + compatible = "mediatek,mt7987-apmixedsys", "syscon"; + reg = <0 0x1001e000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7987-sgmiisys", + "mediatek,mt7987-sgmiisys_0", + "syscon"; + reg = <0 0x10060000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7987-sgmiisys", + "mediatek,mt7987-sgmiisys_1", + "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + + mcusys: mcusys@10400000 { + compatible = "mediatek,mt7987-mcusys", "syscon"; + reg = <0 0x10400000 0 0x1000>; + #clock-cells = <1>; + }; + + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7987-ethdma", + "mediatek,mt7987-ethsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + ethsysrst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = + <0x34 4 0x34 4 0x34 4 + (ASSERT_SET | DEASSERT_CLEAR | + STATUS_SET)>; + }; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 128 255>; + #cooling-cells = <2>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + wmcpu_emi: wmcpu-reserved@50000000 { + compatible = "mediatek,wmcpu-reserved"; + no-map; + reg = <0 0x50000000 0 0x00100000>; + }; + }; + + thermal-zones { + thermal_zone0: soc_thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&lvts 0>; + trips { + cpu_trip_crit: crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active1: active1 { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active0: active0 { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_passive: passive { + temperature = <40000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu-active-high { + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active1>; + }; + + cpu-active-low { + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active0>; + }; + + cpu-passive { + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_passive>; + }; + }; + }; + + thermal_zone1: mcusys_thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&lvts 1>; + }; + + thermal_zone2: eth2p5g_thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&lvts 2>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + hwver: hwver@8000000 { + compatible = "mediatek,hwver", "syscon"; + reg = <0 0x8000000 0 0x1000>; + }; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c080000 0 0x200000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + infra_bus_prot: infra_bus_prot@1000310c { + compatible = "mediatek,infracfg_ao_bus_hang_prot"; + reg = <0 0x1000310c 0 0x14>; + status = "disabled"; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7622-wdt", + "mediatek,mt6589-wdt", + "syscon"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + status = "disabled"; + }; + + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7987-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11d00000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f40000 0 0x1000>, + <0 0x11f60000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rb", "iocfg_lb", "iocfg_rt1", + "iocfg_rt2", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 50>; + interrupt-controller; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + + pcie1pereset { + gpio-hog; + gpios = <36 GPIO_ACTIVE_HIGH>; + output-high; + }; + }; + + boottrap: boottrap@1001f6f0 { + compatible = "mediatek,boottrap"; + reg = <0 0x1001f6f0 0 0x20>; + status = "disabled"; + }; + + trng: trng@1020f000 { + compatible = "mediatek,mt7987-rng"; + status = "disabled"; + }; + + pwm: pwm@10048000 { + compatible = "mediatek,mt7988-pwm"; + reg = <0 0x10048000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, + <&infracfg CLK_INFRA_66M_PWM_HCK>, + <&clkxtal>, + <&clkxtal>, + <&clkxtal>, + <&clkxtal>, + <&clkxtal>, + <&clkxtal>, + <&clkxtal>, + <&clkxtal>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4","pwm5","pwm6","pwm7","pwm8"; + status = "disabled"; + }; + + uart0: serial@11000000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11000000 0 0x100>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_52M_UART0_CK>, + <&infracfg CLK_INFRA_66M_UART0_PCK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_MUX_UART0_SEL>; + assigned-clock-parents = <&topckgen + CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + uart1: serial@11000100 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11000100 0 0x100>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_52M_UART1_CK>, + <&infracfg CLK_INFRA_66M_UART1_PCK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_MUX_UART1_SEL>; + assigned-clock-parents = <&topckgen + CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + uart2: serial@11000200 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11000200 0 0x100>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_52M_UART2_CK>, + <&infracfg CLK_INFRA_66M_UART2_PCK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_MUX_UART2_SEL>; + assigned-clock-parents = <&topckgen + CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + i2c0: i2c@11003000 { + compatible = "mediatek,mt7988-i2c", + "mediatek,mt7981-i2c"; + reg = <0 0x11003000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + clock-div = <1>; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@11007800 { + compatible = "mediatek,ipm-spi-quad", + "mediatek,spi-ipm"; + reg = <0 0x11007800 0 0x100>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_104M_SPI0>, + <&infracfg CLK_INFRA_66M_SPI0_HCK>; + assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_MUX_SPI0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>; + clock-names = "parent-clk", "sel-clk", "spi-clk", + "hclk"; + status = "disabled"; + }; + + spi1: spi@11008800 { + compatible = "mediatek,ipm-spi-single", + "mediatek,spi-ipm"; + reg = <0 0x11008800 0 0x100>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_104M_SPI1>, + <&infracfg CLK_INFRA_66M_SPI1_HCK>; + assigned-clocks = <&topckgen CLK_TOP_SPIM_MST_SEL>, + <&infracfg CLK_INFRA_MUX_SPI1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen + CLK_TOP_SPIM_MST_SEL>; + clock-names = "parent-clk", "sel-clk", "spi-clk", + "hclk"; + status = "disabled"; + }; + + spi2: spi@11009800 { + compatible = "mediatek,ipm-spi-quad", + "mediatek,spi-ipm"; + reg = <0 0x11009800 0 0x100>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_104M_SPI2_BCK>, + <&infracfg CLK_INFRA_66M_SPI2_HCK>; + assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg + CLK_INFRA_MUX_SPI2_BCK_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>; + clock-names = "parent-clk", "sel-clk", "spi-clk", + "hclk"; + status = "disabled"; + }; + + lvts: lvts@1100a000 { + compatible = "mediatek,mt7987-lvts"; + #thermal-sensor-cells = <1>; + reg = <0 0x1100a000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; + clock-names = "lvts_clk"; + nvmem-cells = <&lvts_calibration>; + nvmem-cell-names = "e_data1"; + status = "disabled"; + }; + + usbtphy: usb-phy@11c50000 { + compatible = "mediatek,mt7987", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tphyu2port0: usb-phy@11c50000 { + reg = <0 0x11c50000 0 0x700>; + clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; + clock-names = "ref"; + #phy-cells = <1>; + + auto_load_valid; + nvmem-cells = <&u2_intr_p0>, + <&u2_auto_load_valid_p0>; + nvmem-cell-names = "intr", "auto_load_valid"; + }; + + tphyu3port0: usb-phy@11c50700 { + reg = <0 0x11c50700 0 0x900>; + clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; + clock-names = "ref"; + #phy-cells = <1>; + + auto_load_valid; + nvmem-cells = <&comb_intr_p0>, + <&comb_rx_imp_p0>, + <&comb_tx_imp_p0>, + <&comb_auto_load_valid>; + nvmem-cell-names = "intr", "rx_imp", "tx_imp", + "auto_load_valid"; + + /* MT7987: 4'b0010 default USB30 + * Don't change the '0' + */ + mediatek,syscon-type = <&topmisc 0x218 0>; + + status = "disabled"; + }; + }; + + xhci: xhci@11200000 { + compatible = "mediatek,mt7987-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + usb2-lpm-disable; + status = "disabled"; + }; + + afe: audio-controller@11210000 { + compatible = "mediatek,mt79xx-audio"; + reg = <0 0x11210000 0 0x9000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>, + <&infracfg CLK_INFRA_AUD_26M>, + <&infracfg CLK_INFRA_AUD_L>, + <&infracfg CLK_INFRA_AUD_AUD>, + <&infracfg CLK_INFRA_AUD_EG2>, + <&topckgen CLK_TOP_AUD_SEL>, + <&topckgen CLK_TOP_AUD_I2S_M>; + clock-names = "aud_bus_ck", + "aud_26m_ck", + "aud_l_ck", + "aud_aud_ck", + "aud_eg2_ck", + "aud_sel", + "aud_i2s_m"; + assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, + <&topckgen CLK_TOP_A1SYS_SEL>, + <&topckgen CLK_TOP_AUD_L_SEL>, + <&topckgen CLK_TOP_A_TUNER_SEL>; + assigned-clock-parents = <&apmixedsys + CLK_APMIXED_APLL2>, + <&topckgen + CLK_TOP_CB_APLL2_D4>, + <&apmixedsys + CLK_APMIXED_APLL2>, + <&topckgen + CLK_TOP_CB_APLL2_D4>; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mediatek,mt7986-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11f50000 0 0x1000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_EMMC_200M_SEL>, + <&infracfg CLK_INFRA_MSDC400>, + <&infracfg CLK_INFRA_133M_MSDC_0_HCK>, + <&infracfg CLK_INFRA_MSDC2_HCK>, + <&infracfg CLK_INFRA_MSDC200_SRC>, + <&infracfg CLK_INFRA_66M_MSDC_0_HCK>; + clock-names = "source", "bus_clk", "axi_cg", "hclk", + "source_cg", "ahb_cg"; + status = "disabled"; + }; + + wed: wed { + compatible = "mediatek,wed"; + wed_num = <1>; + }; + + wed0: wed0@15010000 { + compatible = "mediatek,wed0"; + /* add this property for wed get the pci slot number */ + pci_slot_map = <0>; + reg = <0 0x15010000 0 0x2000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + }; + + wdma: wdma@15104800 { + compatible = "mediatek,wed-wdma"; + reg = <0 0x15104800 0 0x400>; + }; + + pcie0: pcie@11280000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7987-pcie", + "mediatek,mt7986-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11280000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <0>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x20000000 0x00 + 0x20000000 0x00 0x00200000>, + <0x82000000 0x00 0x20200000 0x00 + 0x20200000 0x00 0x0fe00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + status = "disabled"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc2 0>, + <0 0 0 2 &pcie_intc2 1>, + <0 0 0 3 &pcie_intc2 2>, + <0 0 0 4 &pcie_intc2 3>; + pcie_intc2: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie1: pcie@11290000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7987-pcie", + "mediatek,mt7986-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11290000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <1>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x30000000 0x00 + 0x30000000 0x00 0x00200000>, + <0x82000000 0x00 0x30200000 0x00 + 0x30200000 0x00 0x0fe00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + status = "disabled"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + slot1: pcie@0,0 { + reg = <0x0000 0 0 0 0>; + }; + }; + + topmisc: topmisc@10021000 { + compatible = "mediatek,mt7987-topmisc", "syscon", + "mediatek,mt7987-power-controller"; + reg = <0 0x10021000 0 0x10000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + /* power domain of the SoC */ + /* eth2p5@MT7988_POWER_DOMAIN_ETH2P5 { + * reg = <MT7988_POWER_DOMAIN_ETH2P5>; + * #power-domain-cells = <0>; + * }; + */ + }; + + efuse: efuse@11d30000 { + compatible = "mediatek,efuse"; + reg = <0 0x11d30000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + lvts_calibration: calib@918 { + reg = <0x918 0x10>; + }; + + comb_auto_load_valid: usb3-alv-imp@8ee { + reg = <0x8ee 1>; + bits = <0 1>; + }; + + comb_rx_imp_p0: usb3-rx-imp@8ec { + reg = <0x8ec 1>; + bits = <0 5>; + }; + + comb_tx_imp_p0: usb3-tx-imp@8ec { + reg = <0x8ec 2>; + bits = <5 5>; + }; + + comb_intr_p0: usb3-intr@8ec { + reg = <0x8ec 2>; + bits = <10 6>; + }; + + u2_auto_load_valid_p0: usb2-alv-p0@8cc { + reg = <0x8cc 1>; + bits = <0 1>; + }; + + u2_intr_p0: usb2-intr-p0@8cc { + reg = <0x8cc 1>; + bits = <1 5>; + }; + }; + + devapc: devapc@1a110000 { + compatible = "mediatek,mt7987-devapc"; + reg = <0 0x1a110000 0 0x1000>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + netsys: soc_netsys { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + }; +}; diff --git a/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi new file mode 100644 index 00000000000..54cf72b3bf8 --- /dev/null +++ b/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "mt7987a-u-boot.dtsi" +#include "mt7987-netsys-u-boot.dtsi" + +/ { + model = "mt7987"; + compatible = "mediatek,mt7987", "mediatek,mt7987-emmc-rfb"; +}; + +ð0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins>; + phy-mode = "2500base-x"; + mediatek,switch = "auto"; + reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pins_default>; + max-frequency = <48000000>; + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + /delete-node/ spi_nor@0; + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; diff --git a/arch/arm/dts/mt7987a-emmc-rfb.dts b/arch/arm/dts/mt7987a-emmc-rfb.dts new file mode 100644 index 00000000000..f59e5bd97bf --- /dev/null +++ b/arch/arm/dts/mt7987a-emmc-rfb.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include "mt7987a.dtsi" +#include "mt7987-emmc.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "MediaTek MT7987 EMMC RFB"; + compatible = "mediatek,mt7987a-emmc", + "mediatek,mt7987a", "mediatek,mt7987"; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11000000 \ + pci=pcie_bus_perf ubi.block=0,firmware \ + root=/dev/fit0 rootwait"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + + wps { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + }; +}; diff --git a/arch/arm/dts/mt7987a-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-rfb-u-boot.dtsi new file mode 100644 index 00000000000..f1ed51e21c4 --- /dev/null +++ b/arch/arm/dts/mt7987a-rfb-u-boot.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include "mt7987a-u-boot.dtsi" +#include "mt7987-netsys-u-boot.dtsi" + +ð0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins>; + phy-mode = "2500base-x"; + mediatek,switch = "auto"; + reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + /delete-node/ spi_nand@0; + spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + /delete-node/ spi_nor@0; + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; diff --git a/arch/arm/dts/mt7987a-rfb.dts b/arch/arm/dts/mt7987a-rfb.dts new file mode 100644 index 00000000000..0ba6b8d9ad7 --- /dev/null +++ b/arch/arm/dts/mt7987a-rfb.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include "mt7987a.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "MediaTek MT7987A RFB"; + compatible = "mediatek,mt7987a", "mediatek,mt7987"; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11000000 \ + pci=pcie_bus_perf"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + + wps { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + }; +}; diff --git a/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi new file mode 100644 index 00000000000..b07e6da41e2 --- /dev/null +++ b/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "mt7987a-u-boot.dtsi" +#include "mt7987-netsys-u-boot.dtsi" + +/ { + model = "mt7987"; + compatible = "mediatek,mt7987", "mediatek,mt7987-sd-rfb"; +}; + +ð0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins>; + phy-mode = "2500base-x"; + mediatek,switch = "auto"; + reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&sd_pins_default>; + max-frequency = <48000000>; + bus-width = <4>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + /delete-node/ spi_nor@0; + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; diff --git a/arch/arm/dts/mt7987a-sd-rfb.dts b/arch/arm/dts/mt7987a-sd-rfb.dts new file mode 100644 index 00000000000..85de4990682 --- /dev/null +++ b/arch/arm/dts/mt7987a-sd-rfb.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include "mt7987a.dtsi" +#include "mt7987-sd.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "MediaTek MT7987 SD RFB"; + compatible = "mediatek,mt7987a-sd", + "mediatek,mt7987a", "mediatek,mt7987"; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11000000 \ + pci=pcie_bus_perf ubi.block=0,firmware \ + root=/dev/fit0 rootwait"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + + wps { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + }; +}; diff --git a/arch/arm/dts/mt7987a-u-boot.dtsi b/arch/arm/dts/mt7987a-u-boot.dtsi new file mode 100644 index 00000000000..ec0a6389d8b --- /dev/null +++ b/arch/arm/dts/mt7987a-u-boot.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include "mt7987-pinctrl-u-boot.dtsi" + +/ { + cpus { + cpu@0 { + mediatek,hwver = <&hwver>; + }; + + cpu@1 { + mediatek,hwver = <&hwver>; + }; + + cpu@2 { + mediatek,hwver = <&hwver>; + }; + + cpu@3 { + mediatek,hwver = <&hwver>; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "disabled"; +}; + +&spi0 { + compatible = "mediatek,ipm-spi"; + clocks = <&infracfg CLK_INFRA_104M_SPI0>, + <&topckgen CLK_TOP_SPI_SEL>; + clock-names = "spi-clk", "sel-clk"; +}; + +&spi1 { + compatible = "mediatek,ipm-spi"; + clocks = <&infracfg CLK_INFRA_104M_SPI1>, + <&topckgen CLK_TOP_SPIM_MST_SEL>; + clock-names = "spi-clk", "sel-clk"; +}; + +&spi2 { + compatible = "mediatek,ipm-spi"; + clocks = <&infracfg CLK_INFRA_104M_SPI2_BCK>, + <&topckgen CLK_TOP_SPI_SEL>; + clock-names = "spi-clk", "sel-clk"; +}; diff --git a/arch/arm/dts/mt7987a.dtsi b/arch/arm/dts/mt7987a.dtsi new file mode 100644 index 00000000000..028f563fb39 --- /dev/null +++ b/arch/arm/dts/mt7987a.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7987.dtsi" +#include "mt7987-pinctrl.dtsi" + +/ { + compatible = "mediatek,mt7987a", "mediatek,mt7987"; + + memory { + reg = <0 0x40000000 0 0x10000000>; + }; + +}; + +&afe { + pinctrl-names = "default"; + pinctrl-0 = <&pcm_pins>; + status = "okay"; +}; + +&boottrap { + status = "okay"; +}; + +&fan { + pwms = <&pwm 0 50000 0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&infra_bus_prot { + status = "okay"; +}; + +&lvts { + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "disabled"; +}; + +&pwm { + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins>; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&xhci { + mediatek,u3p-dis-msk = <0x00000001>; + phys = <&tphyu2port0 PHY_TYPE_USB2>; + + clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, + <&infracfg CLK_INFRA_USB_XHCI_CK_P1>, + <&infracfg CLK_INFRA_USB_CK_P1>, + <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>; + clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck", + "dma_ck"; + + status = "okay"; +}; diff --git a/arch/arm/dts/mt7988-rfb.dts b/arch/arm/dts/mt7988-rfb.dts index 2579d7099fb..1694ef8d9c3 100644 --- a/arch/arm/dts/mt7988-rfb.dts +++ b/arch/arm/dts/mt7988-rfb.dts @@ -80,7 +80,7 @@ status = "disabled"; }; -&pinctrl { +&pio { i2c1_pins: i2c1-pins { mux { function = "i2c"; diff --git a/arch/arm/dts/mt7988-sd-rfb.dts b/arch/arm/dts/mt7988-sd-rfb.dts index 38727a271b2..63e923137c2 100644 --- a/arch/arm/dts/mt7988-sd-rfb.dts +++ b/arch/arm/dts/mt7988-sd-rfb.dts @@ -53,7 +53,7 @@ }; }; -&pinctrl { +&pio { i2c1_pins: i2c1-pins { mux { function = "i2c"; diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi index f2bfde547e6..2d57c6f5709 100644 --- a/arch/arm/dts/mt7988.dtsi +++ b/arch/arm/dts/mt7988.dtsi @@ -110,7 +110,7 @@ #clock-cells = <1>; }; - pinctrl: pinctrl@1001f000 { + pio: pinctrl@1001f000 { compatible = "mediatek,mt7988-pinctrl"; reg = <0 0x1001f000 0 0x1000>, <0 0x11c10000 0 0x1000>, @@ -119,13 +119,11 @@ <0 0x11e00000 0 0x1000>, <0 0x11f00000 0 0x1000>, <0 0x1000b000 0 0x1000>; - reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base", - "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", + reg-names = "gpio", "iocfg_tr", "iocfg_br", + "iocfg_rb", "iocfg_lb", "iocfg_tl", "eint"; - gpio: gpio-controller { - gpio-controller; - #gpio-cells = <2>; - }; + gpio-controller; + #gpio-cells = <2>; }; sgmiisys0: syscon@10060000 { diff --git a/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts b/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts new file mode 100644 index 00000000000..588e39e9265 --- /dev/null +++ b/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "pxa1908.dtsi" + +/ { + pxa,rev-id = <3928 2>; + model = "Samsung Galaxy Core Prime VE LTE"; + compatible = "samsung,coreprimevelte", "marvell,pxa1908"; + + aliases { + serial0 = &uart0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + + /* S-Boot places the initramfs here */ + linux,initrd-start = <0x4d70000>; + linux,initrd-end = <0x5000000>; + + fb0: framebuffer@17177000 { + compatible = "simple-framebuffer"; + reg = <0 0x17177000 0 (480 * 800 * 4)>; + width = <480>; + height = <800>; + stride = <(480 * 4)>; + format = "a8r8g8b8"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0x1000000 0 0x3f000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@17000000 { + reg = <0 0x17000000 0 0x1800000>; + no-map; + }; + + gpu@9000000 { + reg = <0 0x9000000 0 0x1000000>; + }; + + /* Communications processor, aka modem */ + cp@5000000 { + reg = <0 0x5000000 0 0x3000000>; + }; + + cm3@a000000 { + reg = <0 0xa000000 0 0x80000>; + }; + + seclog@8000000 { + reg = <0 0x8000000 0 0x100000>; + }; + + ramoops@8100000 { + compatible = "ramoops"; + reg = <0 0x8100000 0 0x40000>; + record-size = <0x8000>; + console-size = <0x20000>; + max-reason = <5>; + }; + }; +}; diff --git a/arch/arm/dts/pxa1908.dtsi b/arch/arm/dts/pxa1908.dtsi new file mode 100644 index 00000000000..e8ec2606c25 --- /dev/null +++ b/arch/arm/dts/pxa1908.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Marvell Armada PXA1908"; + compatible = "marvell,pxa1908"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0 0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0 1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0 2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0 3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@d1df9000 { + compatible = "arm,gic-400"; + reg = <0 0xd1df9000 0 0x1000>, + <0 0xd1dfa000 0 0x2000>, + /* The subsequent registers are guesses. */ + <0 0xd1dfc000 0 0x2000>, + <0 0xd1dfe000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + apb@d4000000 { + compatible = "simple-bus"; + reg = <0 0xd4000000 0 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xd4000000 0x200000>; + + uart0: serial@17000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0x17000 0x1000>; + clock-frequency = <14745600>; + reg-shift = <2>; + }; + + uart1: serial@18000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0x18000 0x1000>; + clock-frequency = <14745600>; + reg-shift = <2>; + }; + + uart2: serial@36000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0x36000 0x1000>; + clock-frequency = <117000000>; + reg-shift = <2>; + }; + }; + }; +}; diff --git a/arch/arm/dts/r8a779f4-s4sk-u-boot.dtsi b/arch/arm/dts/r8a779f4-s4sk-u-boot.dtsi new file mode 100644 index 00000000000..c2c743ba501 --- /dev/null +++ b/arch/arm/dts/r8a779f4-s4sk-u-boot.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the S4SK board + * + * Copyright (C) 2024-2025 Renesas Electronics Corp. + */ + +#include "r8a779f0-u-boot.dtsi" + +/ { + aliases { + spi0 = &rpc; + /delete-property/ ethernet0; + }; +}; + +&pfc { + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; +}; + +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <40000000>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + spi-max-frequency = <40000000>; + }; +}; diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi index aa5cfc6e41d..af7edc7e2b2 100644 --- a/arch/arm/dts/stm32mp13-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13-u-boot.dtsi @@ -111,3 +111,8 @@ &syscfg { bootph-all; }; + +&usbphyc { + /* stm32-usbphyc-clk = ck_usbo_48m is a source clock of RCC CCF */ + bootph-all; +}; diff --git a/arch/arm/dts/stm32mp251.dtsi b/arch/arm/dts/stm32mp251.dtsi index 44eb664fb51..e2d1c88a57f 100644 --- a/arch/arm/dts/stm32mp251.dtsi +++ b/arch/arm/dts/stm32mp251.dtsi @@ -38,7 +38,7 @@ ck_flexgen_08: ck-flexgen-08 { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <100000000>; + clock-frequency = <64000000>; }; ck_flexgen_51: ck-flexgen-51 { diff --git a/arch/arm/dts/zynqmp-binman-som.dts b/arch/arm/dts/zynqmp-binman-som.dts index 3d9d8476c98..d5b63ef604b 100644 --- a/arch/arm/dts/zynqmp-binman-som.dts +++ b/arch/arm/dts/zynqmp-binman-som.dts @@ -13,6 +13,8 @@ / { binman: binman { multiple-images; + +#ifdef CONFIG_SPL fit-dtb.blob { filename = "fit-dtb.blob"; pad-byte = <0>; @@ -146,8 +148,11 @@ arch = "arm64"; compression = "none"; os = "tee"; - load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; - entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + load = /bits/ 64 <CONFIG_BL32_LOAD_ADDR>; + entry = /bits/ 64 <CONFIG_BL32_LOAD_ADDR>; + hash { + algo = "md5"; + }; tee-os { optional; }; @@ -157,7 +162,9 @@ type = "flat_dt"; arch = "arm64"; compression = "none"; - load = <0x0 0x100000>; +#if CONFIG_XILINX_OF_BOARD_DTB_ADDR + load = /bits/ 64 <CONFIG_XILINX_OF_BOARD_DTB_ADDR>; +#endif hash { algo = "md5"; }; @@ -171,8 +178,13 @@ default = "conf-1"; conf-1 { description = "Multi DTB with TF-A/TEE"; +#if CONFIG_BL31_LOAD_ADDR firmware = "atf"; loadables = "tee", "uboot", "fdt"; +#else + firmware = "uboot"; + loadables = "fdt"; +#endif }; }; }; @@ -221,5 +233,6 @@ }; }; #endif +#endif }; }; diff --git a/arch/arm/dts/zynqmp-binman.dts b/arch/arm/dts/zynqmp-binman.dts index 675f6bf51eb..252c2ad552b 100644 --- a/arch/arm/dts/zynqmp-binman.dts +++ b/arch/arm/dts/zynqmp-binman.dts @@ -14,6 +14,7 @@ binman: binman { multiple-images; +#ifdef CONFIG_SPL /* u-boot.itb generation in a static way */ itb { filename = "u-boot.itb"; @@ -60,8 +61,11 @@ arch = "arm64"; compression = "none"; os = "tee"; - load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; - entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + load = /bits/ 64 <CONFIG_BL32_LOAD_ADDR>; + entry = /bits/ 64 <CONFIG_BL32_LOAD_ADDR>; + hash { + algo = "md5"; + }; tee-os { optional; }; @@ -71,8 +75,10 @@ type = "flat_dt"; arch = "arm64"; compression = "none"; - load = <0x0 0x100000>; - hash-1 { +#if CONFIG_XILINX_OF_BOARD_DTB_ADDR + load = /bits/ 64 <CONFIG_XILINX_OF_BOARD_DTB_ADDR>; +#endif + hash { algo = "md5"; }; }; @@ -81,9 +87,15 @@ default = "@conf-DEFAULT-SEQ"; @conf-SEQ { description = "NAME"; +#if CONFIG_BL31_LOAD_ADDR firmware = "atf"; loadables = "tee", "uboot"; fdt = "fdt-SEQ"; +#else + firmware = "uboot"; + loadables = "fdt"; +#endif + }; }; }; @@ -134,8 +146,11 @@ arch = "arm64"; compression = "none"; os = "tee"; - load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; - entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + load = /bits/ 64 <CONFIG_BL32_LOAD_ADDR>; + entry = /bits/ 64 <CONFIG_BL32_LOAD_ADDR>; + hash { + algo = "md5"; + }; tee-os { optional; }; @@ -145,15 +160,16 @@ type = "flat_dt"; arch = "arm64"; compression = "none"; - load = <0x0 0x100000>; +#if CONFIG_XILINX_OF_BOARD_DTB_ADDR + load = /bits/ 64 <CONFIG_XILINX_OF_BOARD_DTB_ADDR>; +#endif + hash { + algo = "md5"; + }; uboot-fdt-blob { filename = "u-boot.dtb"; type = "blob-ext"; }; - hash-1 { - algo = "md5"; - }; - }; }; configurations { @@ -202,5 +218,6 @@ }; }; #endif +#endif }; }; diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index d56e863ce1c..02be5e1e868 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -22,6 +22,10 @@ "xlnx,zynqmp-sk-kd240", "xlnx,zynqmp"; model = "ZynqMP KD240 revA/B/1"; + aliases { + ethernet0 = "/axi/ethernet@ff0c0000"; /* &gem1 */ + }; + ina260-u3 { compatible = "iio-hwmon"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 9d0c0c2885d..fbacfa984d7 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -20,6 +20,11 @@ "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; model = "ZynqMP KR260 revA"; + aliases { + ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */ + ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */ + }; + ina260-u14 { compatible = "iio-hwmon"; io-channels = <&u14 0>, <&u14 1>, <&u14 2>; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index a98a888d138..3c36eb52e96 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -28,6 +28,10 @@ "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; model = "ZynqMP KV260 revA"; + aliases { + ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */ + }; + ina260-u14 { compatible = "iio-hwmon"; io-channels = <&u14 0>, <&u14 1>, <&u14 2>; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 7490efea98b..078d98e8ff3 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -23,6 +23,10 @@ "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; model = "ZynqMP KV260 revB"; + aliases { + ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */ + }; + ina260-u14 { compatible = "iio-hwmon"; io-channels = <&u14 0>, <&u14 1>, <&u14 2>; diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index 345e282e3e6..bffadfecba1 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -83,8 +83,6 @@ relocate_base: add r1, r3 /* r1 <- Run &__image_copy_start */ subs r4, r0, r1 /* r4 <- Run to copy offset */ beq relocate_done /* skip relocation */ - ldr r1, _image_copy_start_ofs - add r1, r3 /* r1 <- Run &__image_copy_start */ ldr r2, _image_copy_end_ofs add r2, r3 /* r2 <- Run &__image_copy_end */ copy_loop: diff --git a/arch/arm/mach-k3/am62ax/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c index 78153c97a58..698e6d5c587 100644 --- a/arch/arm/mach-k3/am62ax/am62a7_init.c +++ b/arch/arm/mach-k3/am62ax/am62a7_init.c @@ -15,6 +15,9 @@ #include "../sysfw-loader.h" #include "../common.h" +#define CTRLMMR_MCU_RST_CTRL 0x04518170 +#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK 0xFFFDFFFF + struct fwl_data cbass_main_fwls[] = { { "FSS_DAT_REG3", 7, 8 }, }; @@ -70,6 +73,15 @@ static void ctrl_mmr_unlock(void) mmr_unlock(PADCFG_MMR1_BASE, 1); } +static __maybe_unused void enable_mcu_esm_reset(void) +{ + /* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */ + u32 stat = readl(CTRLMMR_MCU_RST_CTRL); + + stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK; + writel(stat, CTRLMMR_MCU_RST_CTRL); +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -160,6 +172,20 @@ void board_init_f(ulong dummy) /* Output System Firmware version info */ k3_sysfw_print_ver(); + if (IS_ENABLED(CONFIG_ESM_K3)) { + /* Probe/configure ESM0 */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev); + if (ret) + printf("esm main init failed: %d\n", ret); + + /* Probe/configure MCUESM */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev); + if (ret) + printf("esm mcu init failed: %d\n", ret); + + enable_mcu_esm_reset(); + } + #if defined(CONFIG_K3_AM62A_DDRSS) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) diff --git a/arch/arm/mach-k3/am62px/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c index 7a24cf39c7b..14a46fa28d2 100644 --- a/arch/arm/mach-k3/am62px/am62p5_init.c +++ b/arch/arm/mach-k3/am62px/am62p5_init.c @@ -19,6 +19,9 @@ /* TISCI DEV ID for A53 Clock */ #define AM62PX_DEV_A53SS0_CORE_0_DEV_ID 135 +#define CTRLMMR_MCU_RST_CTRL 0x04518170 +#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK 0xFFFDFFFF + struct fwl_data cbass_main_fwls[] = { { "FSS_DAT_REG3", 7, 8 }, }; @@ -127,6 +130,15 @@ static void fixup_a53_cpu_freq_by_speed_grade(void) } #endif +static __maybe_unused void enable_mcu_esm_reset(void) +{ + /* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */ + u32 stat = readl(CTRLMMR_MCU_RST_CTRL); + + stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK; + writel(stat, CTRLMMR_MCU_RST_CTRL); +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -218,6 +230,20 @@ void board_init_f(ulong dummy) panic("DRAM init failed: %d\n", ret); } + if (IS_ENABLED(CONFIG_ESM_K3)) { + /* Probe/configure ESM0 */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev); + if (ret) + printf("esm main init failed: %d\n", ret); + + /* Probe/configure MCUESM */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev); + if (ret) + printf("esm mcu init failed: %d\n", ret); + + enable_mcu_esm_reset(); + } + spl_enable_cache(); setup_qos(); diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 031d4e5ecd3..6761a9cb393 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -38,6 +38,7 @@ config TARGET_OPENRD bool "Marvell OpenRD Board" select KW88F6281 select SHEEVA_88SV131 + select KIRKWOOD_COMMON config TARGET_DREAMPLUG bool "DreamPlug Board" diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index ff1fdee5c8d..39eea055f70 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -59,6 +59,16 @@ config TARGET_MT7986 including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe, Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe. +config TARGET_MT7987 + bool "MediaTek MT7987 SoC" + select ARM64 + select CPU + select MTK_TZ_MOVABLE + help + The MediaTek MT7987 is a ARM64-based SoC with a quad-core Cortex-A53. + including UART, I2C, PWM, SPI controller which support SPI flash, + USB3.0, MMC, PCIe, SGMII and built-in Ethernet PHY. + config TARGET_MT7988 bool "MediaTek MT7988 SoC" select ARM64 @@ -122,6 +132,7 @@ config SYS_BOARD default "mt7629" if TARGET_MT7629 default "mt7981" if TARGET_MT7981 default "mt7986" if TARGET_MT7986 + default "mt7987" if TARGET_MT7987 default "mt7988" if TARGET_MT7988 default "mt8183" if TARGET_MT8183 default "mt8512" if TARGET_MT8512 @@ -139,6 +150,7 @@ config SYS_CONFIG_NAME default "mt7629" if TARGET_MT7629 default "mt7981" if TARGET_MT7981 default "mt7986" if TARGET_MT7986 + default "mt7987" if TARGET_MT7987 default "mt7988" if TARGET_MT7988 default "mt8183" if TARGET_MT8183 default "mt8365" if TARGET_MT8365 @@ -150,7 +162,12 @@ config MTK_BROM_HEADER_INFO string default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 - default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988 + default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7987 || TARGET_MT7988 default "lk=1" if TARGET_MT7623 +config MTK_TZ_MOVABLE + select ARCH_MISC_INIT + select OF_SYSTEM_SETUP + bool + endif diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index 3d9e4684fb4..344434c6029 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-y += cpu.o +obj-$(CONFIG_MTK_TZ_MOVABLE) += tzcfg.o obj-$(CONFIG_XPL_BUILD) += spl.o obj-$(CONFIG_MT8512) += mt8512/ @@ -9,6 +10,7 @@ obj-$(CONFIG_TARGET_MT7623) += mt7623/ obj-$(CONFIG_TARGET_MT7629) += mt7629/ obj-$(CONFIG_TARGET_MT7981) += mt7981/ obj-$(CONFIG_TARGET_MT7986) += mt7986/ +obj-$(CONFIG_TARGET_MT7987) += mt7987/ obj-$(CONFIG_TARGET_MT7988) += mt7988/ obj-$(CONFIG_TARGET_MT8183) += mt8183/ obj-$(CONFIG_TARGET_MT8365) += mt8365/ diff --git a/arch/arm/mach-mediatek/mt7987/Makefile b/arch/arm/mach-mediatek/mt7987/Makefile new file mode 100644 index 00000000000..007eb4a3679 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7987/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += lowlevel_init.o diff --git a/arch/arm/mach-mediatek/mt7987/init.c b/arch/arm/mach-mediatek/mt7987/init.c new file mode 100644 index 00000000000..8b268297809 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7987/init.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <fdtdec.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/global_data.h> +#include <asm/u-boot.h> +#include <asm/system.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_mem_size_base(); + if (ret) + return ret; + + gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_4G); + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} + +static struct mm_region mt7987_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x200000000ULL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = mt7987_mem_map; diff --git a/arch/arm/mach-mediatek/mt7987/lowlevel_init.S b/arch/arm/mach-mediatek/mt7987/lowlevel_init.S new file mode 100644 index 00000000000..2f972551277 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7987/lowlevel_init.S @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/* + * Switch from AArch64 EL2 to AArch32 EL2 + * @param inputs: + * x0: argument, zero + * x1: machine nr + * x2: fdt address + * x3: input argument + * x4: kernel entry point + * @param outputs for secure firmware: + * x0: function id + * x1: kernel entry point + * x2: machine nr + * x3: fdt address +*/ + +.global armv8_el2_to_aarch32 +armv8_el2_to_aarch32: + mov x3, x2 + mov x2, x1 + mov x1, x4 + mov x4, #0 + ldr x0, =0x82000200 + SMC #0 + ret diff --git a/arch/arm/mach-mediatek/tzcfg.c b/arch/arm/mach-mediatek/tzcfg.c new file mode 100644 index 00000000000..71982ba4d20 --- /dev/null +++ b/arch/arm/mach-mediatek/tzcfg.c @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <errno.h> +#include <stdio.h> +#include <asm/global_data.h> +#include <linux/kernel.h> +#include <linux/arm-smccc.h> +#include <linux/sizes.h> +#include <command.h> +#include <fdtdec.h> +#include <fdt_support.h> +#include <lmb.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define MTK_SIP_GET_BL31_REGION 0x82000300 +#define MTK_SIP_GET_BL32_REGION 0x82000301 + +#define BL31_DEFAULT_ADDR 0x43000000 +#define BL31_DEFAULT_SIZE 0x80000 + +#define TZ_REGION_MAX_SIZE SZ_16M +#define U_BOOT_MIN_SIZE SZ_4M +#define U_BOOT_MIN_STACK_SIZE SZ_1M +#define REGION_ALIGNMENT SZ_64K + +struct tz_reserved_region { + phys_addr_t addr; + phys_addr_t size; +}; + +static bool fix_tz_region(struct tz_reserved_region region[], + uint32_t used_regions) +{ + phys_addr_t size; + + if (region[0].addr + region[0].size > gd->ram_top) { + if (region[0].addr >= gd->ram_top) { + debug("Discarded region 0x%08llx, size 0x%llx\n", + region[0].addr, region[0].size); + + if (used_regions > 1) + region[0] = region[1]; + + return true; + } + + size = gd->ram_top - region[0].addr; + + debug("Truncated region 0x%08llx, size 0x%llx -> 0x%llx\n", + region[0].addr, region[0].size, size); + + region[0].size = size; + } + + return false; +} + +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + phys_addr_t uboot_ram_top, pstore_size, uboot_size = 0; + struct tz_reserved_region region[2], tmp; + phys_addr_t top_addr, low_addr; + struct arm_smccc_res res; + u32 used_regions = 1; + + /* BL31 region */ + arm_smccc_smc(MTK_SIP_GET_BL31_REGION, 0, 0, 0, 0, 0, 0, 0, &res); + if (res.a0) { + /* Assume PIE is not enabled for BL31 */ + region[0].addr = BL31_DEFAULT_ADDR; + region[0].size = BL31_DEFAULT_SIZE; + } else { + region[0].addr = res.a1; + region[0].size = res.a2; + } + + debug("BL31 @ 0x%08llx, size 0x%llx\n", region[0].addr, + region[0].size); + + /* BL32 region is optional */ + arm_smccc_smc(MTK_SIP_GET_BL32_REGION, 0, 0, 0, 0, 0, 0, 0, &res); + if (!res.a0 && res.a1 && res.a2) { + region[used_regions].addr = res.a1; + region[used_regions].size = res.a2; + + debug("BL32 @ 0x%08llx, size 0x%llx\n", + region[used_regions].addr, region[used_regions].size); + + used_regions++; + } + + if (used_regions == 2) { + if (region[0].addr < region[1].addr) { + /* Make sure region[0] is higher than region[1] */ + tmp = region[0]; + region[0] = region[1]; + region[1] = tmp; + } + + top_addr = region[0].addr + region[0].size; + low_addr = min_t(phys_addr_t, region[0].addr, region[1].addr); + + if (top_addr - low_addr <= TZ_REGION_MAX_SIZE) { + /* Merge region if they're overlapped or close enough */ + region[0].size = top_addr - low_addr; + region[0].addr = low_addr; + + debug("Merged region @ 0x%08llx, size 0x%llx\n", + region[0].addr, region[0].size); + + used_regions = 1; + } + } + + debug("Effective memory @ 0x%08zx, size 0x%llx\n", gd->ram_base, + gd->ram_top - gd->ram_base); + + /* Discard/fix region which is outside the effective memory */ + if (fix_tz_region(region, used_regions)) { + used_regions--; + + if (used_regions) { + if (fix_tz_region(region, used_regions)) + used_regions--; + } + } + + /* Size needed for u-boot & pstore */ +#if IS_ENABLED(CONFIG_CMD_PSTORE) + /* pstore will be placed under ram top */ + pstore_size = (CONFIG_CMD_PSTORE_MEM_SIZE + REGION_ALIGNMENT - 1) & + ~(REGION_ALIGNMENT - 1); + /* u-boot will be placed under pstore */ + uboot_size += pstore_size; +#endif + + uboot_size += max_t(uintptr_t, U_BOOT_MIN_SIZE, total_size); + uboot_size += U_BOOT_MIN_STACK_SIZE + REGION_ALIGNMENT - 1; + uboot_size &= ~(REGION_ALIGNMENT - 1); + + uboot_ram_top = gd->ram_top & ~(REGION_ALIGNMENT - 1); + + if (!used_regions || + (uboot_ram_top - region[0].addr - region[0].size >= uboot_size)) { + /* No reserved region present, + * or gap between high region and ram top is large enough + */ + uboot_ram_top -= pstore_size; + return uboot_ram_top; + } + + uboot_ram_top = region[0].addr & ~(REGION_ALIGNMENT - 1); + + if (used_regions == 2 && + (uboot_ram_top - region[1].addr - region[1].size >= uboot_size)) { + /* Gap between high region and low region is large enough */ + uboot_ram_top -= pstore_size; + return uboot_ram_top; + } + + uboot_ram_top = region[used_regions - 1].addr & ~(REGION_ALIGNMENT - 1); + + /* Under low region */ + uboot_ram_top -= pstore_size; + return uboot_ram_top; +} + +int arch_misc_init(void) +{ + struct arm_smccc_res res; + + /* + * Since board_get_usable_ram_top is be called before arch_misc_init, + * there's no need to check the result + */ + arm_smccc_smc(MTK_SIP_GET_BL31_REGION, 0, 0, 0, 0, 0, 0, 0, &res); + lmb_reserve(res.a1, res.a2, LMB_NOMAP); + + arm_smccc_smc(MTK_SIP_GET_BL32_REGION, 0, 0, 0, 0, 0, 0, 0, &res); + if (!res.a0 && res.a1 && res.a2) + lmb_reserve(res.a1, res.a2, LMB_NOMAP); + +#if IS_ENABLED(CONFIG_CMD_PSTORE) + char cmd[64]; + + /* Override default pstore address */ + snprintf(cmd, sizeof(cmd), "pstore set 0x%llx 0x%x", gd->ram_top, + CONFIG_CMD_PSTORE_MEM_SIZE); + run_command(cmd, 0); +#endif + + return 0; +} + +/* For board-level setup */ +__weak int mtk_ft_system_setup(void *blob, struct bd_info *bd) +{ + return 0; +} + +int ft_system_setup(void *blob, struct bd_info *bd) +{ + struct arm_smccc_res res; + struct fdt_memory mem; + int ret; + + arm_smccc_smc(MTK_SIP_GET_BL31_REGION, 0, 0, 0, 0, 0, 0, 0, &res); + + mem.start = res.a1; + mem.end = res.a1 + res.a2 - 1; + + ret = fdtdec_add_reserved_memory(blob, "secmon", &mem, NULL, 0, NULL, + FDTDEC_RESERVED_MEMORY_NO_MAP); + if (ret < 0) { + log_err("Failed to add reserved-memory for BL31: %s\n", + fdt_strerror(ret)); + return ret; + } + + arm_smccc_smc(MTK_SIP_GET_BL32_REGION, 0, 0, 0, 0, 0, 0, 0, &res); + if (!res.a0 && res.a1 && res.a2) { + mem.start = res.a1; + mem.end = res.a1 + res.a2 - 1; + + ret = fdtdec_add_reserved_memory(blob, "trustzone", &mem, NULL, + 0, NULL, + FDTDEC_RESERVED_MEMORY_NO_MAP); + if (ret < 0) { + log_err("Failed to add reserved-memory for BL32: %s\n", + fdt_strerror(ret)); + return ret; + } + } + + return mtk_ft_system_setup(blob, bd); +} diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig new file mode 100644 index 00000000000..889f127fe82 --- /dev/null +++ b/arch/arm/mach-mmp/Kconfig @@ -0,0 +1,12 @@ +if ARCH_MMP + +config TARGET_COREPRIMEVELTE + bool "Support coreprimevelte" + select LINUX_KERNEL_IMAGE_HEADER + +config LNX_KRNL_IMG_TEXT_OFFSET_BASE + default TEXT_BASE + +source "board/samsung/coreprimevelte/Kconfig" + +endif diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile new file mode 100644 index 00000000000..99beaed05c2 --- /dev/null +++ b/arch/arm/mach-mmp/Makefile @@ -0,0 +1 @@ +obj-y += board.o mmu.o diff --git a/arch/arm/mach-mmp/board.c b/arch/arm/mach-mmp/board.c new file mode 100644 index 00000000000..3384e5377a7 --- /dev/null +++ b/arch/arm/mach-mmp/board.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 + * Duje Mihanović <duje.mihanovic@skole.hr> + */ +#include <errno.h> +#include <init.h> +#include <fdt_support.h> +#include <asm/io.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Timer constants */ +#define APBC_COUNTER_CLK_SEL 0xd4015064 +#define COUNTER_BASE 0xd4101000 +#define COUNTER_EN BIT(0) +#define COUNTER_HALT_ON_DEBUG BIT(1) + +int timer_init(void) +{ + u32 tmp = readl(APBC_COUNTER_CLK_SEL); + + if ((tmp >> 16) != 0x319) + return -1; + + /* Set timer frequency to 26MHz */ + writel(tmp | 1, APBC_COUNTER_CLK_SEL); + writel(COUNTER_EN | COUNTER_HALT_ON_DEBUG, COUNTER_BASE); + + gd->arch.timer_rate_hz = 26000000; + + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + puts("fdtdec_setup_mem_size_base() has failed\n"); + + return 0; +} + +#ifndef CONFIG_SYSRESET +void reset_cpu(void) +{ +} +#endif + +/* Stolen from arch/arm/mach-snapdragon/board.c */ +int board_fdt_blob_setup(void **fdtp) +{ + struct fdt_header *fdt; + bool internal_valid, external_valid; + int ret = 0; + + fdt = (struct fdt_header *)get_prev_bl_fdt_addr(); + external_valid = fdt && !fdt_check_header(fdt); + internal_valid = !fdt_check_header(*fdtp); + + /* + * There is no point returning an error here, U-Boot can't do anything useful in this situation. + * Bail out while we can still print a useful error message. + */ + if (!internal_valid && !external_valid) + panic("Internal FDT is invalid and no external FDT was provided! (fdt=%#llx)\n", + (phys_addr_t)fdt); + + if (internal_valid) { + debug("Using built in FDT\n"); + ret = -EEXIST; + } else { + debug("Using external FDT\n"); + /* So we can use it before returning */ + *fdtp = fdt; + } + + return ret; +} diff --git a/arch/arm/mach-mmp/mmu.c b/arch/arm/mach-mmp/mmu.c new file mode 100644 index 00000000000..ad2f1e3d994 --- /dev/null +++ b/arch/arm/mach-mmp/mmu.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 + * Duje Mihanović <duje.mihanovic@skole.hr> + */ +#include <asm/armv8/mmu.h> +#include <linux/sizes.h> + +static struct mm_region pxa1908_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 2UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 2UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + 0, + } +}; + +struct mm_region *mem_map = pxa1908_mem_map; diff --git a/arch/arm/mach-renesas/Kconfig.rcar4 b/arch/arm/mach-renesas/Kconfig.rcar4 index c2812fd75e4..c42bb9765ef 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar4 +++ b/arch/arm/mach-renesas/Kconfig.rcar4 @@ -54,6 +54,12 @@ config TARGET_SPIDER help Support for Renesas R-Car Gen4 Spider platform +config TARGET_S4SK + bool "S4SK board" + imply R8A779F0 + help + Support for Renesas R-Car Gen4 S4SK platform + config TARGET_WHITEHAWK bool "White Hawk board" imply R8A779G0 @@ -70,6 +76,7 @@ endchoice source "board/renesas/falcon/Kconfig" source "board/renesas/spider/Kconfig" +source "board/renesas/s4sk/Kconfig" source "board/renesas/whitehawk/Kconfig" source "board/renesas/grayhawk/Kconfig" diff --git a/arch/arm/mach-renesas/include/mach/boot0.h b/arch/arm/mach-renesas/include/mach/boot0.h index fc68ffc0945..b71c157149e 100644 --- a/arch/arm/mach-renesas/include/mach/boot0.h +++ b/arch/arm/mach-renesas/include/mach/boot0.h @@ -34,7 +34,7 @@ _start: .inst 0xe380070a /* orr r0, r0, #0x280000 */ /* APMU_RVBARPLC0 = (address of 'b reset' below) | CA_CORE0_VLD_RVBARP */ - .inst 0xe28f3088 /* add r3, pc, #0x88 */ + .inst 0xe28f30a8 /* add r3, pc, #0xa8 */ .inst 0xe3833001 /* orr r3, r3, #1 */ .inst 0xe5843038 /* str r3, [r4, #56] @ 0x38 */ @@ -75,12 +75,22 @@ _start: .inst 0xe20230ff /* and r3, r2, #255 @ 0xff */ .inst 0xe3530011 /* cmp r3, #17 */ .inst 0x1afffffb /* bne 78 <reset-0x28> */ + /* Invalidate icache before jump to follow up software */ + .inst 0xe3a00000 /* mov r0, #0 */ + .inst 0xee070f15 /* mcr 15, 0, r0, cr7, cr5, {0} */ + .inst 0xf57ff04f /* dsb sy */ + .inst 0xf57ff06f /* isb sy */ + /* Jump to follow up software */ .inst 0xe1a02922 /* lsr r2, r2, #18 */ .inst 0xe1a02902 /* lsl r2, r2, #18 */ .inst 0xe1a0f002 /* mov pc, r2 */ .inst 0xeafffffe /* b 94 <reset-0xc> */ .inst 0xe1a00000 /* nop @ (mov r0, r0) */ .inst 0xe1a00000 /* nop @ (mov r0, r0) */ + .inst 0xe1a00000 /* nop @ (mov r0, r0) */ + .inst 0xe1a00000 /* nop @ (mov r0, r0) */ + .inst 0xe1a00000 /* nop @ (mov r0, r0) */ + .inst 0xe1a00000 /* nop @ (mov r0, r0) */ /* Offset 0xa0 */ #endif b reset diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 393f9a1b411..353aecc09de 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -790,8 +790,8 @@ static int init_device(struct stm32prog_data *data, last_addr = (u64)(block_dev->lba - GPT_HEADER_SZ - 1) * block_dev->blksz; } - log_debug("MMC %d: lba=%ld blksz=%ld\n", dev->dev_id, - block_dev->lba, block_dev->blksz); + log_debug("MMC %d: lba=%lld blksz=%ld\n", dev->dev_id, + (u64)block_dev->lba, block_dev->blksz); log_debug(" available address = 0x%llx..0x%llx\n", first_addr, last_addr); log_debug(" full_update = %d\n", dev->full_update); @@ -1229,7 +1229,10 @@ static int stm32prog_alt_add(struct stm32prog_data *data, char multiplier, type; /* max 3 digit for sector size */ - if (part->size > SZ_1M) { + if (part->size > SZ_1G) { + size = (u32)(part->size / SZ_1G); + multiplier = 'G'; + } else if (part->size > SZ_1M) { size = (u32)(part->size / SZ_1M); multiplier = 'M'; } else if (part->size > SZ_1K) { diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index b06105768b3..34b958d7afd 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -81,7 +81,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) /* add 8M for U-Boot reserved memory: display, fdt, gd,... */ size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE); - reg = gd->ram_top - size; + reg = ALIGN(gd->ram_top - size, MMU_SECTION_SIZE); /* Reserved memory for OP-TEE at END of DDR for STM32MP1 SoC */ if (IS_ENABLED(CONFIG_STM32MP13X) || IS_ENABLED(CONFIG_STM32MP15X)) { diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 265e9ce588a..376d1bc7131 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -43,9 +43,6 @@ config SYS_VENDOR config SYS_SOC default "zynq" -config SYS_MALLOC_F_LEN - default 0x800 - config SYS_MALLOC_LEN default 0x1400000 diff --git a/arch/arm/mach-zynqmp-r5/Kconfig b/arch/arm/mach-zynqmp-r5/Kconfig index b2ba896e9b4..45d8c053577 100644 --- a/arch/arm/mach-zynqmp-r5/Kconfig +++ b/arch/arm/mach-zynqmp-r5/Kconfig @@ -19,7 +19,4 @@ config CPU_FREQ_HZ help The value, in Hz, that the CPU clock is running at. -config SYS_MALLOC_F_LEN - default 0x600 - endif diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 92d61e84319..151cfada436 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -93,9 +93,6 @@ config SPL_ZYNQMP_DRAM_BANK2_LEN help Size in bytes of the DRAM ECC bank2. A null size takes no action. -config SYS_MALLOC_F_LEN - default 0x600 - config DEFINE_TCM_OCM_MMAP bool "Define TCM and OCM memory in MMU Table" default y if MP diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index faf70cb5d4c..b24623590f2 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -459,6 +459,7 @@ config SPL_XIP config AVAILABLE_HARTS bool "Send IPI by available harts" + depends on !XIP default y help By default, IPI sending mechanism will depend on available_harts. @@ -587,4 +588,10 @@ config SPL_LOAD_FIT_OPENSBI_OS_BOOT This is a shortcut boot flow, from u-boot SPL -> OpenSBI -> u-boot proper -> linux to u-boot SPL -> OpenSBI -> linux. +config SPL_OPTEE_LOAD_ADDR + hex "OP-TEE Trusted OS image load address" + depends on OPTEE + help + Load address of the OP-TEE binary. + endmenu diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 06ecd92b9bc..5b31da64cbd 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -11,11 +11,13 @@ #include <event.h> #include <hang.h> #include <init.h> +#include <irq_func.h> #include <log.h> #include <asm/encoding.h> #include <asm/system.h> #include <asm/hwcap.h> #include <asm/cpufeature.h> +#include <asm/cache.h> #include <dm/uclass-internal.h> #include <linux/bitops.h> #include <linux/log2.h> @@ -729,3 +731,18 @@ void reset_cpu(void) hang(); } #endif + +/* + * cleanup_before_linux() is called just before we call linux, which prepares + * the processor for linux. + * this weak implementation is used by default. we disable interrupts and flush + * the cache. + */ +__weak int cleanup_before_linux(void) +{ + disable_interrupts(); + + cache_flush(); + + return 0; +} diff --git a/arch/riscv/cpu/generic/Makefile b/arch/riscv/cpu/generic/Makefile index 258e4620dd4..a9be44ec387 100644 --- a/arch/riscv/cpu/generic/Makefile +++ b/arch/riscv/cpu/generic/Makefile @@ -3,4 +3,3 @@ # Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> obj-y += dram.o -obj-y += cpu.o diff --git a/arch/riscv/cpu/generic/cpu.c b/arch/riscv/cpu/generic/cpu.c deleted file mode 100644 index f13c18942f3..00000000000 --- a/arch/riscv/cpu/generic/cpu.c +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> - */ - -#include <irq_func.h> -#include <asm/cache.h> - -/* - * cleanup_before_linux() is called just before we call linux - * it prepares the processor for linux - * - * we disable interrupt and caches. - */ -int cleanup_before_linux(void) -{ - disable_interrupts(); - - cache_flush(); - - return 0; -} diff --git a/arch/riscv/cpu/jh7110/Makefile b/arch/riscv/cpu/jh7110/Makefile index 0939c1061d0..4f91aafa9da 100644 --- a/arch/riscv/cpu/jh7110/Makefile +++ b/arch/riscv/cpu/jh7110/Makefile @@ -5,6 +5,5 @@ ifeq ($(CONFIG_XPL_BUILD),y) obj-y += spl.o else -obj-y += cpu.o obj-y += dram.o endif diff --git a/arch/riscv/cpu/jh7110/cpu.c b/arch/riscv/cpu/jh7110/cpu.c deleted file mode 100644 index 1d7c026584a..00000000000 --- a/arch/riscv/cpu/jh7110/cpu.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - * Author: Yanhong Wang <yanhong.wang@starfivetech.com> - */ - -#include <asm/cache.h> -#include <irq_func.h> - -/* - * cleanup_before_linux() is called just before we call linux - * it prepares the processor for linux - * - * we disable interrupt and caches. - */ -int cleanup_before_linux(void) -{ - disable_interrupts(); - - cache_flush(); - - return 0; -} diff --git a/arch/riscv/cpu/k1/dram.c b/arch/riscv/cpu/k1/dram.c index c477c15cbfb..cc1e903c9dd 100644 --- a/arch/riscv/cpu/k1/dram.c +++ b/arch/riscv/cpu/k1/dram.c @@ -4,17 +4,53 @@ */ #include <asm/global_data.h> +#include <asm/io.h> #include <config.h> +#include <bitfield.h> #include <fdt_support.h> #include <linux/sizes.h> +#define DDR_BASE 0xC0000000 DECLARE_GLOBAL_DATA_PTR; +static phys_size_t ddr_map_size(u32 val) +{ + u32 tmp; + + if (!(val & 0x1)) + return 0; + + tmp = bitfield_extract(val, 16, 5); + switch (tmp) { + case 0xd: + return 512; + case 0xe: + return 1024; + case 0xf: + return 2048; + case 0x10: + return 4096; + case 0x11: + return 8192; + default: + pr_info("Invalid DRAM density %x\n", val); + return 0; + } +} + +phys_size_t ddr_get_density(void) +{ + phys_size_t cs0_size = ddr_map_size(readl((void *)DDR_BASE + 0x200)); + phys_size_t cs1_size = ddr_map_size(readl((void *)DDR_BASE + 0x208)); + phys_size_t ddr_size = cs0_size + cs1_size; + + return ddr_size; +} + int dram_init(void) { gd->ram_base = CFG_SYS_SDRAM_BASE; - /* TODO get ram size from ddr controller */ - gd->ram_size = SZ_4G; + gd->ram_size = ddr_get_density() * SZ_1M; return 0; } diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index 9271de0ddfc..0405faca574 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -53,6 +53,19 @@ }; }; #endif +#ifdef CONFIG_OPTEE + tee { + description = "OP-TEE"; + type = "tee"; + arch = "riscv"; + compression = "none"; + os = "tee"; + load = /bits/ 64 <CONFIG_SPL_OPTEE_LOAD_ADDR>; + tee_blob: tee-os { + filename = "tee.bin"; + }; + }; +#endif opensbi { description = "OpenSBI fw_dynamic Firmware"; @@ -88,11 +101,20 @@ #endif description = "NAME"; firmware = "opensbi"; -#ifndef CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT - loadables = "uboot"; +#ifdef CONFIG_OPTEE +#ifdef CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT + loadables = "linux", "tee"; #else + loadables = "uboot", "tee"; +#endif +#else /* !CONFIG_OPTEEE */ +#ifdef CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT loadables = "linux"; +#else + loadables = "uboot"; #endif +#endif /* CONFIG_OPTEE */ + #ifndef CONFIG_OF_BOARD fdt = "fdt-SEQ"; #endif diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index ae52b375ccb..b8f3012873e 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -13,6 +13,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/sandbox-gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/sandbox-pinmux.h> #include <dt-bindings/mux/mux.h> @@ -820,7 +821,7 @@ gpio-controller; #gpio-cells = <1>; gpio-bank-name = "a"; - sandbox,gpio-count = <20>; + sandbox,gpio-count = <25>; hog_input_active_low { gpio-hog; input; @@ -1010,6 +1011,40 @@ /* label intentionally omitted */ default-state = "off"; }; + + led-20 { + gpios = <&gpio_a 20 0>; + /* label intentionally omitted */ + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + function-enumerator = <20>; + }; + + led-21 { + gpios = <&gpio_a 21 0>; + /* label intentionally omitted */ + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + }; + + led-22 { + gpios = <&gpio_a 22 0>; + /* label intentionally omitted */ + function = LED_FUNCTION_STATUS; + }; + + led-23 { + gpios = <&gpio_a 23 0>; + /* label intentionally omitted */ + color = <LED_COLOR_ID_GREEN>; + }; + + led-24 { + gpios = <&gpio_a 24 0>; + label = "sandbox:function"; + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + }; }; wdt-gpio-toggle { diff --git a/board/Marvell/openrd/openrd.env b/board/Marvell/openrd/openrd.env new file mode 100644 index 00000000000..70ca704b73e --- /dev/null +++ b/board/Marvell/openrd/openrd.env @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 Tony Dinh <mibodhi@gmail.com> + * + * Environment variables configurations + */ + +kernel_addr_r=0x800000 +fdt_addr_r=0x2c00000 +ramdisk_addr_r=0x01100000 +scriptaddr=0x200000 +fdtfile=CONFIG_DEFAULT_DEVICE_TREE.dtb +mtdparts=CONFIG_MTDPARTS_DEFAULT +console=ttyS0,115200 + +/* Standard Boot */ +bootcmd= + bootflow scan -lb +failed= + echo CONFIG_SYS_BOARD boot failed - please check your image diff --git a/board/beacon/beacon-rzg2m/Makefile b/board/beacon/beacon-rzg2m/Makefile index 332b41f35c0..10b7a7fbfa9 100644 --- a/board/beacon/beacon-rzg2m/Makefile +++ b/board/beacon/beacon-rzg2m/Makefile @@ -6,4 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := beacon-rzg2m.o ../../renesas/rcar-common/gen3-common.o ../../renesas/rcar-common/common.o +obj-y := beacon-rzg2m.o ../../renesas/common/gen3-common.o ../../renesas/common/rcar64-common.o diff --git a/board/hoperun/hihope-rzg2/Makefile b/board/hoperun/hihope-rzg2/Makefile index 700e26daa2b..299769c9cb6 100644 --- a/board/hoperun/hihope-rzg2/Makefile +++ b/board/hoperun/hihope-rzg2/Makefile @@ -6,4 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := hihope-rzg2.o ../../renesas/rcar-common/gen3-common.o ../../renesas/rcar-common/common.o +obj-y := hihope-rzg2.o ../../renesas/common/gen3-common.o ../../renesas/common/rcar64-common.o diff --git a/board/mediatek/mt7987/MAINTAINERS b/board/mediatek/mt7987/MAINTAINERS new file mode 100644 index 00000000000..c257d0b09df --- /dev/null +++ b/board/mediatek/mt7987/MAINTAINERS @@ -0,0 +1,8 @@ +MT7987 +M: Sam Shih <sam.shih@mediatek.com> +S: Maintained +F: board/mediatek/mt7987 +F: include/configs/mt7987.h +F: configs/mt7987_rfb_defconfig +F: configs/mt7987_emmc_rfb_defconfig +F: configs/mt7987_sd_rfb_defconfig diff --git a/board/mediatek/mt7987/Makefile b/board/mediatek/mt7987/Makefile new file mode 100644 index 00000000000..9f3f493f3c9 --- /dev/null +++ b/board/mediatek/mt7987/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += mt7987_rfb.o diff --git a/board/mediatek/mt7987/mt7987_rfb.c b/board/mediatek/mt7987/mt7987_rfb.c new file mode 100644 index 00000000000..fcb844deed8 --- /dev/null +++ b/board/mediatek/mt7987/mt7987_rfb.c @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +int board_init(void) +{ + return 0; +} diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c index ebdd5fb2abe..9d833456810 100644 --- a/board/phytec/common/k3/board.c +++ b/board/phytec/common/k3/board.c @@ -258,9 +258,21 @@ fixup_error: int ft_board_setup(void *blob, struct bd_info *bd) { + struct phytec_eeprom_data data; + int ret; + fdt_apply_som_overlays(blob); fdt_copy_fixed_partitions(blob); + ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + if (ret || !data.valid) + return 0; + + ret = phytec_ft_board_fixup(&data, blob); + if (ret) + pr_err("%s: Failed to add PHYTEC information to fdt.\n", + __func__); + return 0; } #endif diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index 166c3eae565..1f2213902ed 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -271,11 +271,122 @@ err: return ret; } +static int phytec_get_product_name(struct phytec_eeprom_data *data, + char *product) +{ + struct phytec_api2_data *api2; + unsigned int ksp_no, som_type; + int len; + + if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2) + return -EINVAL; + + api2 = &data->payload.data.data_api2; + + if (api2->som_type > 1 && api2->som_type <= 3) { + ksp_no = (api2->ksp_no << 8) | api2->som_no; + len = snprintf(product, PHYTEC_PRODUCT_NAME_MAX_LEN + 1, + "%s-%04u", phytec_som_type_str[api2->som_type], + ksp_no); + if (len != PHYTEC_PRODUCT_NAME_KSP_LEN) + return -EINVAL; + return 0; + } + + switch (api2->som_type) { + case 0: + som_type = api2->som_type; + break; + case 4: + som_type = 0; + break; + case 5: + som_type = 0; + break; + case 6: + som_type = 1; + break; + case 7: + som_type = 1; + break; + default: + pr_err("%s: Invalid SOM type: %i", __func__, api2->som_type); + return -EINVAL; + }; + + len = snprintf(product, PHYTEC_PRODUCT_NAME_MAX_LEN + 1, "%s-%03u", + phytec_som_type_str[som_type], api2->som_no); + if (len != PHYTEC_PRODUCT_NAME_STD_LEN) + return -EINVAL; + return 0; +} + +static int phytec_get_part_number(struct phytec_eeprom_data *data, + char *part) +{ + char product_name[PHYTEC_PRODUCT_NAME_MAX_LEN + 1] = {'\0'}; + struct phytec_api2_data *api2; + unsigned int ksp_type; + int res, len; + + if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2) + return -EINVAL; + + api2 = &data->payload.data.data_api2; + + res = phytec_get_product_name(data, product_name); + if (res) + return res; + + if (api2->som_type <= 1) { + len = snprintf(part, PHYTEC_PART_NUMBER_MAX_LEN + 1, + "%s-%s.%s", product_name, api2->opt, + api2->bom_rev); + if (len < PHYTEC_PART_NUMBER_STD_LEN) + return -EINVAL; + return 0; + } + if (api2->som_type <= 3) { + snprintf(part, PHYTEC_PART_NUMBER_MAX_LEN + 1, "%s.%s", + product_name, api2->bom_rev); + if (len != PHYTEC_PART_NUMBER_KSP_LEN) + return -EINVAL; + return 0; + } + + switch (api2->som_type) { + case 4: + ksp_type = 3; + break; + case 5: + ksp_type = 2; + break; + case 6: + ksp_type = 3; + break; + case 7: + ksp_type = 2; + break; + default: + pr_err("%s: Invalid SOM type: %i", __func__, api2->som_type); + return -EINVAL; + }; + + len = snprintf(part, PHYTEC_PART_NUMBER_MAX_LEN + 1, "%s-%s%02u.%s", + product_name, phytec_som_type_str[ksp_type], + api2->ksp_no, api2->bom_rev); + if (len < PHYTEC_PART_NUMBER_STD_KSP_LEN) + return -EINVAL; + + return 0; +} + void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data) { + char part_number[PHYTEC_PART_NUMBER_MAX_LEN + 1] = {'\0'}; struct phytec_api2_data *api2; char pcb_sub_rev; - unsigned int ksp_no, sub_som_type1, sub_som_type2; + int res; if (!data) data = &eeprom_data; @@ -289,50 +400,14 @@ void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data) pcb_sub_rev = api2->pcb_sub_opt_rev & 0x0f; pcb_sub_rev = pcb_sub_rev ? ((pcb_sub_rev - 1) + 'a') : ' '; - /* print standard product string */ - if (api2->som_type <= 1) { - printf("SoM: %s-%03u-%s.%s PCB rev: %u%c\n", - phytec_som_type_str[api2->som_type], api2->som_no, - api2->opt, api2->bom_rev, api2->pcb_rev, pcb_sub_rev); + res = phytec_get_part_number(data, part_number); + if (res) return; - } - /* print KSP/KSM string */ - if (api2->som_type <= 3) { - ksp_no = (api2->ksp_no << 8) | api2->som_no; - printf("SoM: %s-%u ", - phytec_som_type_str[api2->som_type], ksp_no); - /* print standard product based KSP/KSM strings */ - } else { - switch (api2->som_type) { - case 4: - sub_som_type1 = 0; - sub_som_type2 = 3; - break; - case 5: - sub_som_type1 = 0; - sub_som_type2 = 2; - break; - case 6: - sub_som_type1 = 1; - sub_som_type2 = 3; - break; - case 7: - sub_som_type1 = 1; - sub_som_type2 = 2; - break; - default: - pr_err("%s: Invalid SoM type: %i", __func__, api2->som_type); - return; - }; - - printf("SoM: %s-%03u-%s-%03u ", - phytec_som_type_str[sub_som_type1], - api2->som_no, phytec_som_type_str[sub_som_type2], - api2->ksp_no); - } - printf("Option: %s BOM rev: %s PCB rev: %u%c\n", api2->opt, - api2->bom_rev, api2->pcb_rev, pcb_sub_rev); + printf("SOM: %s\n", part_number); + printf("PCB Rev.: %u%c\n", api2->pcb_rev, pcb_sub_rev); + if (api2->som_type > 1) + printf("Options: %s\n", api2->opt); } char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data) @@ -379,6 +454,37 @@ u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data) return data->payload.data.data_api2.som_type; } +#if IS_ENABLED(CONFIG_OF_LIBFDT) +int phytec_ft_board_fixup(struct phytec_eeprom_data *data, void *blob) +{ + char product_name[PHYTEC_PRODUCT_NAME_MAX_LEN + 1] = {'\0'}; + char part_number[PHYTEC_PART_NUMBER_MAX_LEN + 1] = {'\0'}; + int res; + + if (!data) + data = &eeprom_data; + + if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2) + return -EINVAL; + + res = phytec_get_product_name(data, product_name); + if (res) + return res; + + fdt_setprop(blob, 0, "phytec,som-product-name", product_name, + strlen(product_name) + 1); + + res = phytec_get_part_number(data, part_number); + if (res) + return res; + + fdt_setprop(blob, 0, "phytec,som-part-number", part_number, + strlen(part_number) + 1); + + return 0; +} +#endif /* IS_ENABLED(CONFIG_OF_LIBFDT) */ + #if IS_ENABLED(CONFIG_CMD_EXTENSION) struct extension *phytec_add_extension(const char *name, const char *overlay, const char *other) @@ -458,6 +564,12 @@ inline struct phytec_api3_element * __maybe_unused return NULL; } +#if IS_ENABLED(CONFIG_OF_LIBFDT) +inline int phytec_ft_board_fixup(struct phytec_eeprom_data *data, void *blob) +{ + return 0; +} +#endif /* IS_ENABLED(CONFIG_OF_LIBFDT) */ #if IS_ENABLED(CONFIG_CMD_EXTENSION) inline struct extension *phytec_add_extension(const char *name, const char *overlay, diff --git a/board/phytec/common/phytec_som_detection.h b/board/phytec/common/phytec_som_detection.h index 5e35a13cb21..187424a2b44 100644 --- a/board/phytec/common/phytec_som_detection.h +++ b/board/phytec/common/phytec_som_detection.h @@ -8,6 +8,7 @@ #define _PHYTEC_SOM_DETECTION_H #include "phytec_som_detection_blocks.h" +#include <fdtdec.h> #define PHYTEC_MAX_OPTIONS 17 #define PHYTEC_EEPROM_INVAL 0xff @@ -17,6 +18,14 @@ #define PHYTEC_GET_OPTION(option) \ (((option) > '9') ? (option) - 'A' + 10 : (option) - '0') +#define PHYTEC_PRODUCT_NAME_STD_LEN 7 // PCx-000 +#define PHYTEC_PRODUCT_NAME_KSP_LEN 8 // KSP-0000 +#define PHYTEC_PRODUCT_NAME_MAX_LEN PHYTEC_PRODUCT_NAME_KSP_LEN +#define PHYTEC_PART_NUMBER_STD_LEN 11 // PCx-000-\w{1,17}.Ax +#define PHYTEC_PART_NUMBER_KSP_LEN 11 // KSP-0000.Ax +#define PHYTEC_PART_NUMBER_STD_KSP_LEN 16 // PCx-000-KSx00.Ax +#define PHYTEC_PART_NUMBER_MAX_LEN PHYTEC_PRODUCT_NAME_MAX_LEN + 21 + enum { PHYTEC_API_REV0 = 0, PHYTEC_API_REV1, @@ -86,6 +95,9 @@ void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data); char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data); +#if IS_ENABLED(CONFIG_OF_LIBFDT) +int phytec_ft_board_fixup(struct phytec_eeprom_data *data, void *blob); +#endif /* IS_ENABLED(CONFIG_OF_LIBFDT) */ #if IS_ENABLED(CONFIG_CMD_EXTENSION) struct extension *phytec_add_extension(const char *name, const char *overlay, diff --git a/board/phytec/phycore_am64x/Kconfig b/board/phytec/phycore_am64x/Kconfig index 829526c3295..a709b71ba4d 100644 --- a/board/phytec/phycore_am64x/Kconfig +++ b/board/phytec/phycore_am64x/Kconfig @@ -35,3 +35,28 @@ config SYS_CONFIG_NAME source "board/phytec/common/Kconfig" endif + +config PHYCORE_AM64X_RAM_SIZE_FIX + bool "Set phyCORE-AM64x RAM size fix instead of detecting" + default false + help + RAM size is automatic being detected with the help of + the EEPROM introspection data. Set RAM size to a fix value + instead. + +choice + prompt "phyCORE-AM64x RAM size" + depends on PHYCORE_AM64X_RAM_SIZE_FIX + default PHYCORE_AM64X_RAM_SIZE_2GB + +config PHYCORE_AM64X_RAM_SIZE_1GB + bool "1GB RAM" + help + Set RAM size fix to 1GB for phyCORE-AM64x. + +config PHYCORE_AM64X_RAM_SIZE_2GB + bool "2GB RAM" + help + Set RAM size fix to 2GB for phyCORE-AM64x. + +endchoice diff --git a/board/phytec/phycore_am64x/phycore-am64x.c b/board/phytec/phycore_am64x/phycore-am64x.c index 8f3b22657c7..f14c87f5c72 100644 --- a/board/phytec/phycore_am64x/phycore-am64x.c +++ b/board/phytec/phycore_am64x/phycore-am64x.c @@ -11,9 +11,12 @@ #include <env.h> #include <env_internal.h> #include <spl.h> +#include <asm/arch/k3-ddr.h> #include <fdt_support.h> #include <asm/arch/hardware.h> +#include "../common/am6_som_detection.h" + DECLARE_GLOBAL_DATA_PTR; int board_init(void) @@ -21,15 +24,113 @@ int board_init(void) return 0; } +static u8 phytec_get_am64_ddr_size_default(void) +{ + int ret; + struct phytec_eeprom_data data; + + if (IS_ENABLED(CONFIG_PHYCORE_AM64X_RAM_SIZE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_AM64X_RAM_SIZE_1GB)) + return EEPROM_RAM_SIZE_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_AM64X_RAM_SIZE_2GB)) + return EEPROM_RAM_SIZE_2GB; + } + + ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + if (!ret && data.valid) + return phytec_get_am6_ddr_size(&data); + + /* Default DDR size is 2GB */ + return EEPROM_RAM_SIZE_2GB; +} + int dram_init(void) { - return fdtdec_setup_mem_size_base(); + u8 ram_size; + + if (!IS_ENABLED(CONFIG_CPU_V7R)) + return fdtdec_setup_mem_size_base(); + + ram_size = phytec_get_am64_ddr_size_default(); + + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + gd->ram_size = 0x40000000; + break; + case EEPROM_RAM_SIZE_2GB: + gd->ram_size = 0x80000000; + break; + default: + gd->ram_size = 0x80000000; + } + + return 0; } int dram_init_banksize(void) { - return fdtdec_setup_memory_banksize(); + u8 ram_size; + + memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS); + + if (!IS_ENABLED(CONFIG_CPU_V7R)) + return fdtdec_setup_memory_banksize(); + + ram_size = phytec_get_am64_ddr_size_default(); + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x40000000; + gd->ram_size = 0x40000000; + break; + + case EEPROM_RAM_SIZE_2GB: + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + break; + + default: + /* Continue with default 2GB setup */ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + printf("DDR size %d is not supported\n", ram_size); + } + + return 0; +} + +#if defined(CONFIG_K3_DDRSS) +int do_board_detect(void) +{ + void *fdt = (void *)gd->fdt_blob; + int bank; + + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + dram_init(); + dram_init_banksize(); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = gd->bd->bi_dram[bank].start; + size[bank] = gd->bd->bi_dram[bank].size; + } + + return fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS); +} +#endif + +#if IS_ENABLED(CONFIG_XPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + if (IS_ENABLED(CONFIG_K3_DDRSS) && IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); + else + fixup_memory_node(spl_image); } +#endif #define CTRLMMR_USB0_PHY_CTRL 0x43004008 #define CORE_VOLTAGE 0x80000000 diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile new file mode 100644 index 00000000000..347be5cc93c --- /dev/null +++ b/board/renesas/common/Makefile @@ -0,0 +1,49 @@ +# +# board/renesas/whitehawk/Makefile +# +# Copyright (C) 2024 Marek Vasut <marek.vasut+renesas@mailbox.org> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# R-Car SoCs +ifndef CONFIG_RZG2L + +# 32 bit SoCs +ifdef CONFIG_RCAR_32 +ifdef CONFIG_RCAR_GEN2 +endif +endif + +# 64 bit SoCs +ifdef CONFIG_RCAR_64 +ifdef CONFIG_XPL_BUILD +obj-y += rcar64-spl.o +else +obj-y += rcar64-common.o +endif + +ifdef CONFIG_RCAR_GEN3 +ifdef CONFIG_XPL_BUILD +obj-y += gen3-spl.o +else +obj-y += gen3-common.o +ifdef CONFIG_R8A77970 +obj-y += v3-common.o +endif +ifdef CONFIG_R8A77980 +obj-y += v3-common.o +endif +endif +endif + +ifdef CONFIG_RCAR_GEN4 +ifdef CONFIG_XPL_BUILD +obj-y += gen4-spl.o +else +obj-y += gen4-common.o +endif +endif +endif + +endif diff --git a/board/renesas/rcar-common/gen3-common.c b/board/renesas/common/gen3-common.c index 004feca6180..94da00985d3 100644 --- a/board/renesas/rcar-common/gen3-common.c +++ b/board/renesas/common/gen3-common.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * board/renesas/rcar-common/gen3-common.c + * board/renesas/common/gen3-common.c * * Copyright (C) 2013 Renesas Electronics Corporation * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> @@ -18,8 +18,6 @@ #include <asm/arch/renesas.h> #include <linux/libfdt.h> -#ifdef CONFIG_RCAR_64 - DECLARE_GLOBAL_DATA_PTR; /* If the firmware passed a device tree use it for e.g. U-Boot DRAM setup. */ @@ -178,4 +176,3 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } #endif -#endif diff --git a/board/renesas/common/gen3-spl.c b/board/renesas/common/gen3-spl.c new file mode 100644 index 00000000000..9590b5d6a2e --- /dev/null +++ b/board/renesas/common/gen3-spl.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R-Car Gen3 recovery SPL + * + * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com> + */ + +#include <init.h> +#include <asm/io.h> +#include <spl.h> + +#define RCAR_CNTC_BASE 0xE6080000 +#define CNTCR_EN BIT(0) + +void board_init_f(ulong dummy) +{ + writel(CNTCR_EN, RCAR_CNTC_BASE); + timer_init(); +} + +void spl_board_init(void) +{ + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_UART; +} + +void s_init(void) +{ +} + +void reset_cpu(void) +{ +} diff --git a/board/renesas/rcar-common/gen4-common.c b/board/renesas/common/gen4-common.c index 2abe9660cf8..52a0639073b 100644 --- a/board/renesas/rcar-common/gen4-common.c +++ b/board/renesas/common/gen4-common.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * board/renesas/rcar-common/gen4-common.c + * board/renesas/common/gen4-common.c * * Copyright (C) 2021-2024 Renesas Electronics Corp. */ diff --git a/board/renesas/rcar-common/gen4-spl.c b/board/renesas/common/gen4-spl.c index 2aca8baf3dd..e46ef0a3075 100644 --- a/board/renesas/rcar-common/gen4-spl.c +++ b/board/renesas/common/gen4-spl.c @@ -76,23 +76,6 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) return map_sysmem(CONFIG_SYS_LOAD_ADDR + offset, 0); } -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) -{ - debug("image entry point: 0x%lx\n", spl_image->entry_point); - if (spl_image->os == IH_OS_ARM_TRUSTED_FIRMWARE) { - typedef void (*image_entry_arg_t)(int, int, int, int) - __attribute__ ((noreturn)); - image_entry_arg_t image_entry = - (image_entry_arg_t)(uintptr_t) spl_image->entry_point; - image_entry(IH_MAGIC, CONFIG_SPL_TEXT_BASE, 0, 0); - } else { - typedef void __noreturn (*image_entry_noargs_t)(void); - image_entry_noargs_t image_entry = - (image_entry_noargs_t)spl_image->entry_point; - image_entry(); - } -} - #define APMU_BASE 0xe6170000U #define CL0GRP3_BIT BIT(3) #define CL1GRP3_BIT BIT(7) diff --git a/board/renesas/rcar-common/common.c b/board/renesas/common/rcar64-common.c index 90eb468e4c4..69229ea3cb0 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/common/rcar64-common.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * board/renesas/rcar-common/common.c + * board/renesas/common/common.c * * Copyright (C) 2013 Renesas Electronics Corporation * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> @@ -18,8 +18,6 @@ #include <asm/system.h> #include <linux/libfdt.h> -#ifdef CONFIG_RCAR_64 - DECLARE_GLOBAL_DATA_PTR; int dram_init(void) @@ -68,4 +66,7 @@ int __weak board_init(void) return 0; } -#endif +int __weak board_early_init_f(void) +{ + return 0; +} diff --git a/board/renesas/rcar-common/gen3-spl.c b/board/renesas/common/rcar64-spl.c index 44a20cef2df..76f2bde924e 100644 --- a/board/renesas/rcar-common/gen3-spl.c +++ b/board/renesas/common/rcar64-spl.c @@ -1,37 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ /* - * R-Car Gen3 recovery SPL - * - * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com> + * Copyright (C) 2024 Marek Vasut <marek.vasut+renesas@mailbox.org> */ -#include <cpu_func.h> #include <image.h> -#include <init.h> -#include <log.h> -#include <asm/io.h> #include <spl.h> -#include <linux/bitops.h> - -#define RCAR_CNTC_BASE 0xE6080000 -#define CNTCR_EN BIT(0) - -void board_init_f(ulong dummy) -{ - writel(CNTCR_EN, RCAR_CNTC_BASE); - timer_init(); -} - -void spl_board_init(void) -{ - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_UART; -} void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { @@ -49,11 +22,3 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) image_entry(); } } - -void s_init(void) -{ -} - -void reset_cpu(void) -{ -} diff --git a/board/renesas/rcar-common/v3-common.c b/board/renesas/common/v3-common.c index 5d057edb0a6..5d057edb0a6 100644 --- a/board/renesas/rcar-common/v3-common.c +++ b/board/renesas/common/v3-common.c diff --git a/board/renesas/condor/Makefile b/board/renesas/condor/Makefile deleted file mode 100644 index fe3a2fd3b7a..00000000000 --- a/board/renesas/condor/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# board/renesas/condor/Makefile -# -# Copyright (C) 2019 Renesas Electronics Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := ../rcar-common/gen3-common.o ../rcar-common/common.o -endif diff --git a/board/renesas/draak/Makefile b/board/renesas/draak/Makefile index 3ed7800b0e9..0a6a325d761 100644 --- a/board/renesas/draak/Makefile +++ b/board/renesas/draak/Makefile @@ -6,8 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := draak.o ../rcar-common/gen3-common.o ../rcar-common/common.o +ifndef CONFIG_XPL_BUILD +obj-y += draak.o endif diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c index a51bf65674f..564cf439aa6 100644 --- a/board/renesas/draak/draak.c +++ b/board/renesas/draak/draak.c @@ -6,43 +6,12 @@ * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> */ -#include <cpu_func.h> -#include <hang.h> -#include <init.h> -#include <malloc.h> -#include <netdev.h> -#include <dm.h> -#include <asm/global_data.h> -#include <dm/platform_data/serial_sh.h> -#include <asm/processor.h> -#include <asm/mach-types.h> #include <asm/io.h> -#include <linux/bitops.h> -#include <linux/errno.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/arch/gpio.h> -#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> -#include <i2c.h> -#include <mmc.h> - -DECLARE_GLOBAL_DATA_PTR; +#include <asm/arch/renesas.h> -#define GSX_MSTP112 BIT(12) /* 3DG */ -#define SCIF2_MSTP310 BIT(10) /* SCIF2 */ -#define DVFS_MSTP926 BIT(26) #define HSUSB_MSTP704 BIT(4) /* HSUSB */ -int board_early_init_f(void) -{ -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) - /* DVFS for reset */ - mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); -#endif - return 0; -} - /* HSUSB block registers */ #define HSUSB_REG_LPSTS 0xE6590102 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) diff --git a/board/renesas/eagle/Makefile b/board/renesas/eagle/Makefile deleted file mode 100644 index 3f5fdab1bc2..00000000000 --- a/board/renesas/eagle/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# board/renesas/eagle/Makefile -# -# Copyright (C) 2015 Renesas Electronics Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := ../rcar-common/v3-common.o ../rcar-common/gen3-common.o ../rcar-common/common.o -endif diff --git a/board/renesas/ebisu/Makefile b/board/renesas/ebisu/Makefile deleted file mode 100644 index 8139391029d..00000000000 --- a/board/renesas/ebisu/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# board/renesas/ebisu/Makefile -# -# Copyright (C) 2018 Renesas Electronics Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := ../rcar-common/gen3-common.o ../rcar-common/common.o -endif diff --git a/board/renesas/falcon/Makefile b/board/renesas/falcon/Makefile deleted file mode 100644 index 48fcfac9105..00000000000 --- a/board/renesas/falcon/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# board/renesas/falcon/Makefile -# -# Copyright (C) 2020 Renesas Electronics Corp. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := ../rcar-common/gen4-common.o ../rcar-common/common.o -endif diff --git a/board/renesas/grayhawk/Makefile b/board/renesas/grayhawk/Makefile deleted file mode 100644 index 7414b773326..00000000000 --- a/board/renesas/grayhawk/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# board/renesas/grayhawk/Makefile -# -# Copyright (C) 2023 Renesas Electronics Corp. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := ../rcar-common/gen4-common.o ../rcar-common/common.o diff --git a/board/renesas/s4sk/Kconfig b/board/renesas/s4sk/Kconfig new file mode 100644 index 00000000000..57013d22b8c --- /dev/null +++ b/board/renesas/s4sk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_S4SK + +config SYS_SOC + default "renesas" + +config SYS_BOARD + default "s4sk" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "s4sk" + +endif diff --git a/board/renesas/s4sk/MAINTAINERS b/board/renesas/s4sk/MAINTAINERS new file mode 100644 index 00000000000..e64da079160 --- /dev/null +++ b/board/renesas/s4sk/MAINTAINERS @@ -0,0 +1,7 @@ +S4SK BOARD +M: Marek Vasut <marek.vasut+renesas@mailbox.org> +S: Maintained +F: arch/arm/dts/r8a779f4* +F: board/renesas/s4sk/ +F: configs/r8a779f4_s4sk_defconfig +F: include/configs/s4sk.h diff --git a/board/renesas/s4sk/Makefile b/board/renesas/s4sk/Makefile new file mode 100644 index 00000000000..f03e52386f2 --- /dev/null +++ b/board/renesas/s4sk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2025 Renesas Electronics Corp. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := s4sk.o diff --git a/board/renesas/s4sk/s4sk.c b/board/renesas/s4sk/s4sk.c new file mode 100644 index 00000000000..d2beb71c684 --- /dev/null +++ b/board/renesas/s4sk/s4sk.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org> + */ + +#include <dm.h> +#include <i2c.h> +#include <malloc.h> +#include <net-common.h> + +#define S4SK_FPGA_I2C_BUS "i2c5" +#define S4SK_FPGA_I2C_DEV_ADDR 0x70 +#define S4SK_FPGA_I2C_DEV_WIDTH 2 +#define S4SK_FPGA_I2C_MAC_COUNT 4 +#define S4SK_FPGA_I2C_MAC_OFFSET 0x58 +#define S4SK_FPGA_I2C_MAC_WIDTH 8 + +int board_late_init(void) +{ + /* + * Extract AVB and TSN0,1,2 MAC addresses from FPGA via I2C. + * + * In case a matching ethaddr/ethNaddr environment variable + * is not set, set it, otherwise do not override it. This + * allows users to set their own MAC addresses via ethaddr + * and ethNaddr environment variables. + * + * The ethaddr/ethNaddr mapping follows Linux kernel DT aliases + * ethernetN property assignment: + * - ethaddr ..... TSN0 (IC104 connector) + * - eth1addr .... TSN1 (IC101 connector) + * - eth2addr .... TSN2 (Expansion connector) + * - eth3addr .... AVB (CN1 connector) + */ + ofnode i2c_node = ofnode_path(S4SK_FPGA_I2C_BUS); + struct udevice *bus, *dev; + unsigned char enetaddr[6]; + unsigned char macs[32]; /* Four MAC addresses in FPGA in total. */ + int i, idx, j, ret; + + ret = uclass_get_device_by_ofnode(UCLASS_I2C, i2c_node, &bus); + if (ret < 0) { + printf("s4sk: cannot find i2c bus (%d)\n", ret); + return 0; + } + + ret = i2c_get_chip(bus, S4SK_FPGA_I2C_DEV_ADDR, + S4SK_FPGA_I2C_DEV_WIDTH, &dev); + if (ret < 0) { + printf("s4sk: cannot find i2c chip (%d)\n", ret); + return 0; + } + + ret = dm_i2c_read(dev, S4SK_FPGA_I2C_MAC_OFFSET, macs, sizeof(macs)); + if (ret < 0) { + printf("s4sk: failed to read MAC addresses via i2c (%d)\n", ret); + return 0; + } + + for (i = 0; i < S4SK_FPGA_I2C_MAC_COUNT; i++) { + /* + * Remap TSN0,1,2 to ethaddr,eth1addr,eth2addr and + * AVB to eth3addr to match Linux /aliases ethernetN + * assignment, which starts with ethernet0 for TSN. + */ + idx = (i + 3) % 4; + ret = eth_env_get_enetaddr_by_index("eth", idx, enetaddr); + if (ret) /* ethaddr is already set */ + continue; + + /* Byte-wise reverse the MAC address */ + for (j = 0; j < sizeof(enetaddr); j++) + enetaddr[j] = macs[i * S4SK_FPGA_I2C_MAC_WIDTH + (5 - j)]; + + if (!is_valid_ethaddr(enetaddr)) { + printf("s4sk: MAC address %d in FPGA not valid (%pM)\n", + i, enetaddr); + continue; + } + + eth_env_set_enetaddr_by_index("eth", idx, enetaddr); + } + + return 0; +} diff --git a/board/renesas/salvator-x/Makefile b/board/renesas/salvator-x/Makefile index fe7c78ef2ff..538bbdddf76 100644 --- a/board/renesas/salvator-x/Makefile +++ b/board/renesas/salvator-x/Makefile @@ -6,8 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := salvator-x.o ../rcar-common/gen3-common.o ../rcar-common/common.o +ifndef CONFIG_XPL_BUILD +obj-y += salvator-x.o endif diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index 2c8860bcee4..6d33d005b4c 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -7,41 +7,13 @@ * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> */ -#include <cpu_func.h> -#include <image.h> -#include <init.h> -#include <malloc.h> -#include <netdev.h> -#include <dm.h> -#include <asm/global_data.h> -#include <dm/platform_data/serial_sh.h> -#include <asm/processor.h> -#include <asm/mach-types.h> #include <asm/io.h> -#include <linux/bitops.h> -#include <linux/errno.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/arch/gpio.h> -#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> -#include <i2c.h> -#include <mmc.h> - -DECLARE_GLOBAL_DATA_PTR; +#include <asm/arch/renesas.h> +#include <init.h> -#define DVFS_MSTP926 BIT(26) #define HSUSB_MSTP704 BIT(4) /* HSUSB */ -int board_early_init_f(void) -{ -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) - /* DVFS for reset */ - mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); -#endif - return 0; -} - /* HSUSB block registers */ #define HSUSB_REG_LPSTS 0xE6590102 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) @@ -65,13 +37,6 @@ int board_init(void) return 0; } -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) -void reset_cpu(void) -{ - i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80); -} -#endif - #ifdef CONFIG_MULTI_DTB_FIT int board_fit_config_name_match(const char *name) { diff --git a/board/renesas/spider/Makefile b/board/renesas/spider/Makefile deleted file mode 100644 index 9489917278c..00000000000 --- a/board/renesas/spider/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# board/renesas/spider/Makefile -# -# Copyright (C) 2020 Renesas Electronics Corp. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := ../rcar-common/gen4-common.o ../rcar-common/common.o diff --git a/board/renesas/ulcb/Makefile b/board/renesas/ulcb/Makefile index c3c2f391e55..4f2dd1ca211 100644 --- a/board/renesas/ulcb/Makefile +++ b/board/renesas/ulcb/Makefile @@ -6,8 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := ulcb.o cpld.o ../rcar-common/gen3-common.o ../rcar-common/common.o +ifndef CONFIG_XPL_BUILD +obj-y += ulcb.o cpld.o endif diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index 64f01b123cb..d02e5d0bfc5 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -6,40 +6,13 @@ * Copyright (C) 2017 Renesas Electronics Corporation */ -#include <image.h> -#include <init.h> -#include <malloc.h> -#include <netdev.h> -#include <dm.h> -#include <asm/global_data.h> -#include <dm/platform_data/serial_sh.h> -#include <asm/processor.h> -#include <asm/mach-types.h> #include <asm/io.h> -#include <linux/bitops.h> -#include <linux/errno.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/arch/gpio.h> -#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> -#include <i2c.h> -#include <mmc.h> - -DECLARE_GLOBAL_DATA_PTR; +#include <asm/arch/renesas.h> +#include <init.h> -#define DVFS_MSTP926 BIT(26) #define HSUSB_MSTP704 BIT(4) /* HSUSB */ -int board_early_init_f(void) -{ -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) - /* DVFS for reset */ - mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); -#endif - return 0; -} - /* HSUSB block registers */ #define HSUSB_REG_LPSTS 0xE6590102 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) diff --git a/board/renesas/v3hsk/Makefile b/board/renesas/v3hsk/Makefile index ee04f67d986..e6db77468e6 100644 --- a/board/renesas/v3hsk/Makefile +++ b/board/renesas/v3hsk/Makefile @@ -7,9 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := ../rcar-common/v3-common.o ../rcar-common/gen3-common.o ../rcar-common/common.o +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_SYSRESET) += cpld.o endif diff --git a/board/renesas/v3msk/Makefile b/board/renesas/v3msk/Makefile index 63e06a4b5fd..211b8a32489 100644 --- a/board/renesas/v3msk/Makefile +++ b/board/renesas/v3msk/Makefile @@ -7,9 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := ../rcar-common/v3-common.o ../rcar-common/gen3-common.o ../rcar-common/common.o +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_SYSRESET) += cpld.o endif diff --git a/board/renesas/whitehawk/Makefile b/board/renesas/whitehawk/Makefile deleted file mode 100644 index 80f92e6b041..00000000000 --- a/board/renesas/whitehawk/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# board/renesas/whitehawk/Makefile -# -# Copyright (C) 2021 Renesas Electronics Corp. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-y := ../rcar-common/gen4-spl.o -else -obj-y := ../rcar-common/gen4-common.o ../rcar-common/common.o -endif diff --git a/board/samsung/coreprimevelte/Kconfig b/board/samsung/coreprimevelte/Kconfig new file mode 100644 index 00000000000..78a80379605 --- /dev/null +++ b/board/samsung/coreprimevelte/Kconfig @@ -0,0 +1,12 @@ +if TARGET_COREPRIMEVELTE + +config SYS_BOARD + default "coreprimevelte" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "pxa1908" + +endif diff --git a/board/samsung/coreprimevelte/MAINTAINERS b/board/samsung/coreprimevelte/MAINTAINERS new file mode 100644 index 00000000000..0902117e8b3 --- /dev/null +++ b/board/samsung/coreprimevelte/MAINTAINERS @@ -0,0 +1,6 @@ +Samsung Galaxy Core Prime VE LTE support +M: Duje Mihanović <duje.mihanovic@skole.hr> +S: Maintained +T: git git://git.dujemihanovic.xyz/u-boot.git +F: board/samsung/coreprimevelte/ +F: configs/coreprimevelte_defconfig diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c index c5cef6f19d2..0bef68d2fb2 100644 --- a/board/samsung/e850-96/e850-96.c +++ b/board/samsung/e850-96/e850-96.c @@ -19,6 +19,11 @@ int dram_init_banksize(void) int board_init(void) { - load_ldfw(); + int err; + + err = load_ldfw(); + if (err) + printf("ERROR: LDFW loading failed (%d)\n", err); + return 0; } diff --git a/board/samsung/e850-96/e850-96.env b/board/samsung/e850-96/e850-96.env index f36f90be950..5ac76bcef02 100644 --- a/board/samsung/e850-96/e850-96.env +++ b/board/samsung/e850-96/e850-96.env @@ -1,26 +1,11 @@ -partitions= - uuid_disk=${uuid_gpt_disk}; - name=efs,start=512K,size=20M,uuid=${uuid_gpt_efs}; - name=env,size=16K,uuid=${uuid_gpt_env}; - name=kernel,size=30M,uuid=${uuid_gpt_kernel}; - name=ramdisk,size=26M,uuid=${uuid_gpt_ramdisk}; - name=dtbo,size=1M,uuid=${uuid_gpt_dtbo}; - name=ldfw,size=4016K,uuid=${uuid_gpt_ldfw}; - name=keystorage,size=8K,uuid=${uuid_gpt_keystorage}; - name=tzsw,size=1M,uuid=${uuid_gpt_tzsw}; - name=harx,size=2M,uuid=${uuid_gpt_harx}; - name=harx_rkp,size=2M,uuid=${uuid_gpt_harx_rkp}; - name=logo,size=40M,uuid=${uuid_gpt_logo}; - name=super,size=3600M,uuid=${uuid_gpt_super}; - name=cache,size=300M,uuid=${uuid_gpt_cache}; - name=modem,size=100M,uuid=${uuid_gpt_modem}; - name=boot,size=100M,uuid=${uuid_gpt_boot}; - name=persist,size=30M,uuid=${uuid_gpt_persist}; - name=recovery,size=40M,uuid=${uuid_gpt_recovery}; - name=misc,size=40M,uuid=${uuid_gpt_misc}; - name=mnv,size=20M,uuid=${uuid_gpt_mnv}; - name=frp,size=512K,uuid=${uuid_gpt_frp}; - name=vbmeta,size=64K,uuid=${uuid_gpt_vbmeta}; - name=metadata,size=16M,uuid=${uuid_gpt_metadata}; - name=dtb,size=1M,uuid=${uuid_gpt_dtb}; - name=userdata,size=-,uuid=${uuid_gpt_userdata} +kernel_addr_r=0x80000000 +kernel_comp_addr_r=0x88000000 +kernel_comp_size=0x4000000 +fdt_addr_r=0x8c000000 +scriptaddr=0x8c100000 +pxefile_addr_r=0x8c200000 +ramdisk_addr_r=0x8c300000 +fdtfile=CONFIG_DEFAULT_FDT_FILE + +partitions=name=esp,start=512K,size=128M,bootable,type=system; +partitions+=name=rootfs,size=-,bootable,type=linux diff --git a/board/samsung/e850-96/fw.c b/board/samsung/e850-96/fw.c index 82a0b224c67..8f64e759b43 100644 --- a/board/samsung/e850-96/fw.c +++ b/board/samsung/e850-96/fw.c @@ -7,14 +7,16 @@ */ #include <part.h> +#include <fs.h> #include <linux/arm-smccc.h> #include "fw.h" #define EMMC_IFACE "mmc" #define EMMC_DEV_NUM 0 +#define LDFW_RAW_PART "ldfw" +#define LDFW_FAT_PART "esp" +#define LDFW_FAT_PATH "/EFI/firmware/ldfw.bin" -/* LDFW constants */ -#define LDFW_PART_NAME "ldfw" #define LDFW_NWD_ADDR 0x88000000 #define LDFW_MAGIC 0x10adab1e #define SMC_CMD_LOAD_LDFW -0x500 @@ -36,7 +38,33 @@ struct ldfw_header { char fw_name[16]; }; -static int read_fw(const char *part_name, void *buf) +/* Load LDFW binary as a file from FAT partition */ +static int read_fw_from_fat(const char *part_name, const char *path, void *buf) +{ + char dev_part_str[8]; + loff_t len_read; + int err; + + snprintf(dev_part_str, sizeof(dev_part_str), "%d#%s", EMMC_DEV_NUM, + LDFW_FAT_PART); + + err = fs_set_blk_dev(EMMC_IFACE, dev_part_str, FS_TYPE_FAT); + if (err) { + debug("%s: Can't set block device\n", __func__); + return -ENODEV; + } + + err = fs_read(path, (ulong)buf, 0, 0, &len_read); + if (err) { + debug("%s: Can't read LDFW file\n", __func__); + return -EIO; + } + + return 0; +} + +/* Load LDFW binary from raw partition on block device into RAM buffer */ +static int read_fw_from_raw(const char *part_name, void *buf) { struct blk_desc *blk_desc; struct disk_partition part; @@ -73,10 +101,13 @@ int load_ldfw(void) u64 size = 0; int err, i; - /* Load LDFW from the block device partition into RAM buffer */ - err = read_fw(LDFW_PART_NAME, buf); - if (err) - return err; + /* First try to read LDFW from EFI partition, then from the raw one */ + err = read_fw_from_fat(LDFW_FAT_PART, LDFW_FAT_PATH, buf); + if (err) { + err = read_fw_from_raw(LDFW_RAW_PART, buf); + if (err) + return err; + } /* Validate LDFW by magic number in its header */ hdr = buf; diff --git a/board/silinux/ek874/Makefile b/board/silinux/ek874/Makefile index 879da9edacf..0beda63d115 100644 --- a/board/silinux/ek874/Makefile +++ b/board/silinux/ek874/Makefile @@ -7,7 +7,7 @@ # ifdef CONFIG_XPL_BUILD -obj-y := ../../renesas/rcar-common/gen3-spl.o +obj-y := ../../renesas/common/gen3-spl.o else -obj-y := ek874.o ../../renesas/rcar-common/gen3-common.o ../../renesas/rcar-common/common.o +obj-y := ek874.o ../../renesas/common/gen3-common.o ../../renesas/common/rcar64-common.o endif diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 2dbd071abd9..67b60d2e7b4 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -161,7 +161,7 @@ static struct mv_ddr_topology_map board_topology_map = { {0}, /* timing parameters */ { {0} }, /* electrical configuration */ {0,}, /* electrical parameters */ - 0, /* ODT configuration */ + 0x30000, /* ODT configuration */ 0x3, /* clock enable mask */ }; diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index d5e5e776d2a..15fb9e4b062 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -751,8 +751,6 @@ enum env_location env_get_location(enum env_operation op, int prio) case BOOT_FLASH_EMMC: if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) return ENVL_MMC; - else if (CONFIG_IS_ENABLED(ENV_IS_IN_EXT4)) - return ENVL_EXT4; else return ENVL_NOWHERE; diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 3855e15b83b..b2149438b88 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -312,7 +312,7 @@ static int tdx_cfg_block_mmc_storage(u8 *config_block, int write) out: /* Switch back to regular eMMC user partition */ - blk_select_hwpart_devnum(UCLASS_MMC, 0, 0); + blk_select_hwpart_devnum(UCLASS_MMC, dev, 0); return ret; } diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 8cdd9d86009..820fb252a3f 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -488,7 +488,7 @@ static int boot_targets_setup(void) if (bootseq >= 0) { bootseq_len = snprintf(NULL, 0, "%i", bootseq); debug("Bootseq len: %x\n", bootseq_len); - env_set_hex("bootseq", bootseq); + env_set_ulong("bootseq", (unsigned long)bootseq); } /* diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env index b0c2ac6f2e8..75b604a1f76 100644 --- a/board/xilinx/zynqmp/zynqmp_kria.env +++ b/board/xilinx/zynqmp/zynqmp_kria.env @@ -43,6 +43,7 @@ script_size_f=0x80000 scriptaddr=0x20000000 usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boot_part; fi preboot=setenv boot_targets; setenv modeboot; run board_setup +usb_pgood_delay=1000 # SOM specific boot methods usb_boot_devices='usb0 usb1 usb2 usb3 usb4' diff --git a/boot/Kconfig b/boot/Kconfig index 20935a269c6..c09a98c3233 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -711,6 +711,20 @@ config BOOTMETH_VBE_SIMPLE firmware image in boot media such as MMC. It does not support any sort of rollback, recovery or A/B boot. +config BOOTMETH_VBE_ABREC + bool "Bootdev support for VBE 'a/b/recovery' method" + imply SPL_CRC8 + imply VPL_CRC8 + help + Enables support for VBE 'abrec' boot. This allows updating one of an + A or B firmware image in boot media such as MMC. The new firmware is + tried and if it boots, it is copied to the other image, so that both + A and B have the same version. If neither firmware image passes the + verification step, a recovery image is booted. This method will + eventually provide rollback protection as well. + +if BOOTMETH_VBE_SIMPLE + config BOOTMETH_VBE_SIMPLE_OS bool "Bootdev support for VBE 'simple' method OS phase" default y @@ -769,6 +783,65 @@ config TPL_BOOTMETH_VBE_SIMPLE_FW endif # BOOTMETH_VBE_SIMPLE +if BOOTMETH_VBE_ABREC + +config SPL_BOOTMETH_VBE_ABREC + bool "Bootdev support for VBE 'abrec' method (SPL)" + depends on SPL + default y if VPL + help + Enables support for VBE 'abrec' boot. The SPL part of this + implementation simply loads U-Boot from the image selected by the + VPL phase. + +config TPL_BOOTMETH_VBE_ABREC + bool "Bootdev support for VBE 'abrec' method (TPL)" + depends on TPL + select TPL_FIT + default y + help + Enables support for VBE 'abrec' boot. The TPL part of this + implementation simply jumps to VPL after device init is completed. + +config VPL_BOOTMETH_VBE_ABREC + bool "Bootdev support for VBE 'abrec' method (VPL)" + depends on VPL + default y + help + Enables support for VBE 'abrec' boot. The VPL part of this + implementation selects which SPL to use (A, B or recovery) and then + boots into SPL. + +config SPL_BOOTMETH_VBE_ABREC_FW + bool "Bootdev support for VBE 'abrec' method firmware phase (SPL)" + depends on SPL + default y if VPL + help + Enables support for VBE 'abrec' boot. The SPL part of this + implementation simply loads U-Boot from the image selected by the + VPL phase. + +config TPL_BOOTMETH_VBE_ABREC_FW + bool "Bootdev support for VBE 'abrec' method firmware phase (TPL)" + depends on TPL + default y if VPL + help + Enables support for VBE 'abrec' boot. The TPL part of this + implementation simply jumps to VPL after device init is completed. + +config VPL_BOOTMETH_VBE_ABREC_FW + bool "Bootdev support for VBE 'abrec' method firmware phase (VPL)" + depends on VPL + default y + help + Enables support for VBE 'abrec' boot. The VPL part of this + implementation selects which SPL to use (A, B or recovery) and then + boots into SPL. + +endif # BOOTMETH_VBE_ABREC + +endif # BOOTMETH_VBE + config EXPO bool "Support for expos - groups of scenes displaying a UI" depends on VIDEO diff --git a/boot/Makefile b/boot/Makefile index c2753de8163..34bac26c4e2 100644 --- a/boot/Makefile +++ b/boot/Makefile @@ -70,3 +70,7 @@ obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE_SIMPLE_FW) += vbe_simple_fw.o obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE_SIMPLE_OS) += vbe_simple_os.o obj-$(CONFIG_$(PHASE_)BOOTMETH_ANDROID) += bootmeth_android.o + +obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE_ABREC) += vbe_abrec.o vbe_common.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE_ABREC_FW) += vbe_abrec_fw.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE_ABREC_OS) += vbe_abrec_os.o diff --git a/boot/image-fit.c b/boot/image-fit.c index 70080d1a6c0..aa139da628c 100644 --- a/boot/image-fit.c +++ b/boot/image-fit.c @@ -1907,24 +1907,30 @@ int fit_conf_get_prop_node(const void *fit, int noffset, const char *prop_name, count = fit_conf_get_prop_node_count(fit, noffset, prop_name); if (count < 0) return count; + log_debug("looking for %s (%s, image-count %d):\n", prop_name, + genimg_get_phase_name(image_ph_phase(sel_phase)), count); /* check each image in the list */ for (i = 0; i < count; i++) { - enum image_phase_t phase; + enum image_phase_t phase = IH_PHASE_NONE; int ret, node; node = fit_conf_get_prop_node_index(fit, noffset, prop_name, i); ret = fit_image_get_phase(fit, node, &phase); + log_debug("- %s (%s): ", fdt_get_name(fit, node, NULL), + genimg_get_phase_name(phase)); /* if the image is for any phase, let's use it */ - if (ret == -ENOENT) + if (ret == -ENOENT || phase == sel_phase) { + log_debug("found\n"); return node; - else if (ret < 0) + } else if (ret < 0) { + log_debug("err=%d\n", ret); return ret; - - if (phase == sel_phase) - return node; + } + log_debug("no match\n"); } + log_debug("- not found\n"); return -ENOENT; } @@ -2012,13 +2018,15 @@ int fit_get_node_from_config(struct bootm_headers *images, } /** - * fit_get_image_type_property() - get property name for IH_TYPE_... + * fit_get_image_type_property() - get property name for sel_phase * * Return: the properly name where we expect to find the image in the * config node */ -static const char *fit_get_image_type_property(int type) +static const char *fit_get_image_type_property(int ph_type) { + int type = image_ph_type(ph_type); + /* * This is sort-of available in the uimage_type[] table in image.c * but we don't have access to the short name, and "fdt" is different @@ -2070,8 +2078,9 @@ int fit_image_load(struct bootm_headers *images, ulong addr, fit_uname = fit_unamep ? *fit_unamep : NULL; fit_uname_config = fit_uname_configp ? *fit_uname_configp : NULL; fit_base_uname_config = NULL; - prop_name = fit_get_image_type_property(image_type); - printf("## Loading %s from FIT Image at %08lx ...\n", prop_name, addr); + prop_name = fit_get_image_type_property(ph_type); + printf("## Loading %s (%s) from FIT Image at %08lx ...\n", + prop_name, genimg_get_phase_name(image_ph_phase(ph_type)), addr); bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT); ret = fit_check_format(fit, IMAGE_SIZE_INVAL); @@ -2346,10 +2355,17 @@ int boot_get_fdt_fit(struct bootm_headers *images, ulong addr, char *next_config = NULL; ulong load, len; #ifdef CONFIG_OF_LIBFDT_OVERLAY - ulong image_start, image_end; ulong ovload, ovlen, ovcopylen; const char *uconfig; const char *uname; + /* + * of_flat_tree is storing the void * returned by map_sysmem, then its + * address is passed to boot_relocate_fdt which expects a char ** and it + * is then cast into a ulong. Setting its type to void * would require + * to cast its address to char ** when passing it to boot_relocate_fdt. + * Instead, let's be lazy and use void *. + */ + char *of_flat_tree; void *base, *ov, *ovcopy = NULL; int i, err, noffset, ov_noffset; #endif @@ -2393,17 +2409,18 @@ int boot_get_fdt_fit(struct bootm_headers *images, ulong addr, /* we need to apply overlays */ #ifdef CONFIG_OF_LIBFDT_OVERLAY - image_start = addr; - image_end = addr + fit_get_size(fit); - /* verify that relocation took place by load address not being in fit */ - if (load >= image_start && load < image_end) { - /* check is simplified; fit load checks for overlaps */ - printf("Overlayed FDT requires relocation\n"); + /* Relocate FDT so resizing does not overwrite other data in FIT. */ + of_flat_tree = map_sysmem(load, len); + len = ALIGN(fdt_totalsize(load), SZ_4K); + err = boot_relocate_fdt(&of_flat_tree, &len); + if (err) { + printf("Required FDT relocation for applying DTOs failed: %d\n", + err); fdt_noffset = -EBADF; goto out; } - base = map_sysmem(load, len); + load = (ulong)of_flat_tree; /* apply extra configs in FIT first, followed by args */ for (i = 1; ; i++) { diff --git a/boot/vbe_abrec.c b/boot/vbe_abrec.c new file mode 100644 index 00000000000..6d0f622262d --- /dev/null +++ b/boot/vbe_abrec.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Verified Boot for Embedded (VBE) 'simple' method + * + * Copyright 2024 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#define LOG_CATEGORY LOGC_BOOT + +#include <dm.h> +#include <memalign.h> +#include <mmc.h> +#include <dm/ofnode.h> +#include "vbe_abrec.h" + +int abrec_read_priv(ofnode node, struct abrec_priv *priv) +{ + memset(priv, '\0', sizeof(*priv)); + if (ofnode_read_u32(node, "area-start", &priv->area_start) || + ofnode_read_u32(node, "area-size", &priv->area_size) || + ofnode_read_u32(node, "version-offset", &priv->version_offset) || + ofnode_read_u32(node, "version-size", &priv->version_size) || + ofnode_read_u32(node, "state-offset", &priv->state_offset) || + ofnode_read_u32(node, "state-size", &priv->state_size)) + return log_msg_ret("read", -EINVAL); + ofnode_read_u32(node, "skip-offset", &priv->skip_offset); + priv->storage = strdup(ofnode_read_string(node, "storage")); + if (!priv->storage) + return log_msg_ret("str", -EINVAL); + + return 0; +} + +int abrec_read_nvdata(struct abrec_priv *priv, struct udevice *blk, + struct abrec_state *state) +{ + ALLOC_CACHE_ALIGN_BUFFER(u8, buf, MMC_MAX_BLOCK_LEN); + const struct vbe_nvdata *nvd = (struct vbe_nvdata *)buf; + uint flags; + int ret; + + ret = vbe_read_nvdata(blk, priv->area_start + priv->state_offset, + priv->state_size, buf); + if (ret == -EPERM) { + memset(buf, '\0', MMC_MAX_BLOCK_LEN); + log_warning("Starting with empty state\n"); + } else if (ret) { + return log_msg_ret("nv", ret); + } + + state->fw_vernum = nvd->fw_vernum; + flags = nvd->flags; + state->try_count = flags & VBEF_TRY_COUNT_MASK; + state->try_b = flags & VBEF_TRY_B; + state->recovery = flags & VBEF_RECOVERY; + state->pick = (flags & VBEF_PICK_MASK) >> VBEF_PICK_SHIFT; + + return 0; +} + +int abrec_read_state(struct udevice *dev, struct abrec_state *state) +{ + struct abrec_priv *priv = dev_get_priv(dev); + struct udevice *blk; + int ret; + + ret = vbe_get_blk(priv->storage, &blk); + if (ret) + return log_msg_ret("blk", ret); + + ret = vbe_read_version(blk, priv->area_start + priv->version_offset, + state->fw_version, MAX_VERSION_LEN); + if (ret) + return log_msg_ret("ver", ret); + log_debug("version=%s\n", state->fw_version); + + ret = abrec_read_nvdata(priv, blk, state); + if (ret) + return log_msg_ret("nvd", ret); + + return 0; +} diff --git a/boot/vbe_abrec.h b/boot/vbe_abrec.h new file mode 100644 index 00000000000..63c73297351 --- /dev/null +++ b/boot/vbe_abrec.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Verified Boot for Embedded (VBE) vbe-abrec common file + * + * Copyright 2024 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#ifndef __VBE_ABREC_H +#define __VBE_ABREC_H + +#include <vbe.h> +#include <dm/ofnode_decl.h> + +#include "vbe_common.h" + +struct bootflow; +struct udevice; + +/** + * struct abrec_priv - information read from the device tree + * + * @area_start: Start offset of the VBE area in the device, in bytes + * @area_size: Total size of the VBE area + * @skip_offset: Size of an initial part of the device to skip, when using + * area_start. This is effectively added to area_start to calculate the + * actual start position on the device + * @state_offset: Offset from area_start of the VBE state, in bytes + * @state_size: Size of the state information + * @version_offset: Offset from from area_start of the VBE version info + * @version_size: Size of the version info + * @storage: Storage device to use, in the form <uclass><devnum>, e.g. "mmc1" + */ +struct abrec_priv { + u32 area_start; + u32 area_size; + u32 skip_offset; + u32 state_offset; + u32 state_size; + u32 version_offset; + u32 version_size; + const char *storage; +}; + +/** struct abrec_state - state information read from media + * + * The state on the media is converted into this more code-friendly structure. + * + * @fw_version: Firmware version string + * @fw_vernum: Firmware version number + * @try_count: Number of times the B firmware has been tried + * @try_b: true to try B firmware on the next boot + * @recovery: true to enter recovery firmware on the next boot + * @try_result: Result of trying to boot with the last firmware + * @pick: Firmware which was chosen in this boot + */ +struct abrec_state { + char fw_version[MAX_VERSION_LEN]; + u32 fw_vernum; + u8 try_count; + bool try_b; + bool recovery; + enum vbe_try_result try_result; + enum vbe_pick_t pick; +}; + +/** + * abrec_read_fw_bootflow() - Read a bootflow for firmware + * + * Locates and loads the firmware image (FIT) needed for the next phase. The FIT + * should ideally use external data, to reduce the amount of it that needs to be + * read. + * + * @bdev: bootdev device containing the firmwre + * @bflow: Place to put the created bootflow, on success + * @return 0 if OK, -ve on error + */ +int abrec_read_bootflow_fw(struct udevice *dev, struct bootflow *bflow); + +/** + * vbe_simple_read_state() - Read the VBE simple state information + * + * @dev: VBE bootmeth + * @state: Place to put the state + * @return 0 if OK, -ve on error + */ +int abrec_read_state(struct udevice *dev, struct abrec_state *state); + +/** + * abrec_read_nvdata() - Read non-volatile data from a block device + * + * Reads the ABrec VBE nvdata from a device. This function reads a single block + * from the device, so the nvdata cannot be larger than that. + * + * @blk: Device to read from + * @offset: Offset to read, in bytes + * @size: Number of bytes to read + * @buf: Buffer to hold the data + * Return: 0 if OK, -E2BIG if @size > block size, -EBADF if the offset is not + * block-aligned, -EIO if an I/O error occurred, -EPERM if the header version is + * incorrect, the header size is invalid or the data fails its CRC check + */ +int abrec_read_nvdata(struct abrec_priv *priv, struct udevice *blk, + struct abrec_state *state); + +/** + * abrec_read_priv() - Read info from the devicetree + * + * @node: Node to read from + * @priv: Information to fill in + * Return 0 if OK, -EINVAL if something is wrong with the devicetree node + */ +int abrec_read_priv(ofnode node, struct abrec_priv *priv); + +#endif /* __VBE_ABREC_H */ diff --git a/boot/vbe_abrec_fw.c b/boot/vbe_abrec_fw.c new file mode 100644 index 00000000000..d52bd9ddff0 --- /dev/null +++ b/boot/vbe_abrec_fw.c @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Verified Boot for Embedded (VBE) loading firmware phases + * + * Copyright 2022 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#define LOG_CATEGORY LOGC_BOOT + +#include <binman_sym.h> +#include <bloblist.h> +#include <bootdev.h> +#include <bootflow.h> +#include <bootmeth.h> +#include <bootstage.h> +#include <display_options.h> +#include <dm.h> +#include <image.h> +#include <log.h> +#include <mapmem.h> +#include <memalign.h> +#include <mmc.h> +#include <spl.h> +#include <vbe.h> +#include <dm/device-internal.h> +#include "vbe_abrec.h" +#include "vbe_common.h" + +binman_sym_declare(ulong, spl_a, image_pos); +binman_sym_declare(ulong, spl_b, image_pos); +binman_sym_declare(ulong, spl_recovery, image_pos); + +binman_sym_declare(ulong, spl_a, size); +binman_sym_declare(ulong, spl_b, size); +binman_sym_declare(ulong, spl_recovery, size); + +binman_sym_declare(ulong, u_boot_a, image_pos); +binman_sym_declare(ulong, u_boot_b, image_pos); +binman_sym_declare(ulong, u_boot_recovery, image_pos); + +binman_sym_declare(ulong, u_boot_a, size); +binman_sym_declare(ulong, u_boot_b, size); +binman_sym_declare(ulong, u_boot_recovery, size); + +binman_sym_declare(ulong, vpl, image_pos); +binman_sym_declare(ulong, vpl, size); + +static const char *const pick_names[] = {"A", "B", "Recovery"}; + +/** + * abrec_read_bootflow_fw() - Create a bootflow for firmware + * + * Locates and loads the firmware image (FIT) needed for the next phase. The FIT + * should ideally use external data, to reduce the amount of it that needs to be + * read. + * + * @bdev: bootdev device containing the firmwre + * @meth: VBE abrec bootmeth + * @blow: Place to put the created bootflow, on success + * @return 0 if OK, -ve on error + */ +int abrec_read_bootflow_fw(struct udevice *dev, struct bootflow *bflow) +{ + struct udevice *media = dev_get_parent(bflow->dev); + struct udevice *meth = bflow->method; + struct abrec_priv *priv = dev_get_priv(meth); + ulong len, load_addr; + struct udevice *blk; + int ret; + + log_debug("media=%s\n", media->name); + ret = blk_get_from_parent(media, &blk); + if (ret) + return log_msg_ret("med", ret); + + ret = vbe_read_fit(blk, priv->area_start + priv->skip_offset, + priv->area_size, NULL, &load_addr, &len, &bflow->name); + if (ret) + return log_msg_ret("vbe", ret); + + /* set up the bootflow with the info we obtained */ + bflow->blk = blk; + bflow->buf = map_sysmem(load_addr, len); + bflow->size = len; + + return 0; +} + +static int abrec_run_vpl(struct udevice *blk, struct spl_image_info *image, + struct vbe_handoff *handoff) +{ + uint flags, tries, prev_result; + struct abrec_priv priv; + struct abrec_state state; + enum vbe_pick_t pick; + uint try_count; + ulong offset, size; + ulong ub_offset, ub_size; + ofnode node; + int ret; + + node = vbe_get_node(); + if (!ofnode_valid(node)) + return log_msg_ret("nod", -EINVAL); + + ret = abrec_read_priv(node, &priv); + if (ret) + return log_msg_ret("pri", ret); + + ret = abrec_read_nvdata(&priv, blk, &state); + if (ret) + return log_msg_ret("sta", ret); + + prev_result = state.try_result; + try_count = state.try_count; + + if (state.recovery) { + pick = VBEP_RECOVERY; + + /* if we are trying B but ran out of tries, use A */ + } else if ((prev_result == VBETR_TRYING) && !tries) { + pick = VBEP_A; + state.try_result = VBETR_BAD; + + /* if requested, try B */ + } else if (flags & VBEF_TRY_B) { + pick = VBEP_B; + + /* decrement the try count if not already zero */ + if (try_count) + try_count--; + state.try_result = VBETR_TRYING; + } else { + pick = VBEP_A; + } + state.try_count = try_count; + + switch (pick) { + case VBEP_A: + offset = binman_sym(ulong, spl_a, image_pos); + size = binman_sym(ulong, spl_a, size); + ub_offset = binman_sym(ulong, u_boot_a, image_pos); + ub_size = binman_sym(ulong, u_boot_a, size); + break; + case VBEP_B: + offset = binman_sym(ulong, spl_b, image_pos); + size = binman_sym(ulong, spl_b, size); + ub_offset = binman_sym(ulong, u_boot_b, image_pos); + ub_size = binman_sym(ulong, u_boot_b, size); + break; + case VBEP_RECOVERY: + offset = binman_sym(ulong, spl_recovery, image_pos); + size = binman_sym(ulong, spl_recovery, size); + ub_offset = binman_sym(ulong, u_boot_recovery, image_pos); + ub_size = binman_sym(ulong, u_boot_recovery, size); + break; + } + log_debug("pick=%d, offset=%lx size=%lx\n", pick, offset, size); + log_info("VBE: Firmware pick %s at %lx\n", pick_names[pick], offset); + + ret = vbe_read_fit(blk, offset, size, image, NULL, NULL, NULL); + if (ret) + return log_msg_ret("vbe", ret); + handoff->offset = ub_offset; + handoff->size = ub_size; + handoff->pick = pick; + image->load_addr = spl_get_image_text_base(); + image->entry_point = image->load_addr; + + return 0; +} + +static int abrec_run_spl(struct udevice *blk, struct spl_image_info *image, + struct vbe_handoff *handoff) +{ + int ret; + + log_info("VBE: Firmware pick %s at %lx\n", pick_names[handoff->pick], + handoff->offset); + ret = vbe_read_fit(blk, handoff->offset, handoff->size, image, NULL, + NULL, NULL); + if (ret) + return log_msg_ret("vbe", ret); + image->load_addr = spl_get_image_text_base(); + image->entry_point = image->load_addr; + + return 0; +} + +static int abrec_load_from_image(struct spl_image_info *image, + struct spl_boot_device *bootdev) +{ + struct vbe_handoff *handoff; + int ret; + + printf("load: %s\n", ofnode_read_string(ofnode_root(), "model")); + if (xpl_phase() != PHASE_VPL && xpl_phase() != PHASE_SPL && + xpl_phase() != PHASE_TPL) + return -ENOENT; + + ret = bloblist_ensure_size(BLOBLISTT_VBE, sizeof(struct vbe_handoff), + 0, (void **)&handoff); + if (ret) + return log_msg_ret("ro", ret); + + if (USE_BOOTMETH) { + struct udevice *meth, *bdev; + struct abrec_priv *priv; + struct bootflow bflow; + + vbe_find_first_device(&meth); + if (!meth) + return log_msg_ret("vd", -ENODEV); + log_debug("vbe dev %s\n", meth->name); + ret = device_probe(meth); + if (ret) + return log_msg_ret("probe", ret); + + priv = dev_get_priv(meth); + log_debug("abrec %s\n", priv->storage); + ret = bootdev_find_by_label(priv->storage, &bdev, NULL); + if (ret) + return log_msg_ret("bd", ret); + log_debug("bootdev %s\n", bdev->name); + + bootflow_init(&bflow, bdev, meth); + ret = bootmeth_read_bootflow(meth, &bflow); + log_debug("\nfw ret=%d\n", ret); + if (ret) + return log_msg_ret("rd", ret); + + /* jump to the image */ + image->flags = SPL_SANDBOXF_ARG_IS_BUF; + image->arg = bflow.buf; + image->size = bflow.size; + log_debug("Image: %s at %p size %x\n", bflow.name, bflow.buf, + bflow.size); + + /* this is not used from now on, so free it */ + bootflow_free(&bflow); + } else { + struct udevice *media; + struct udevice *blk; + + ret = uclass_get_device_by_seq(UCLASS_MMC, 1, &media); + if (ret) + return log_msg_ret("vdv", ret); + ret = blk_get_from_parent(media, &blk); + if (ret) + return log_msg_ret("med", ret); + + if (xpl_phase() == PHASE_TPL) { + ulong offset, size; + + offset = binman_sym(ulong, vpl, image_pos); + size = binman_sym(ulong, vpl, size); + log_debug("VPL at offset %lx size %lx\n", offset, size); + ret = vbe_read_fit(blk, offset, size, image, NULL, + NULL, NULL); + if (ret) + return log_msg_ret("vbe", ret); + } else if (xpl_phase() == PHASE_VPL) { + ret = abrec_run_vpl(blk, image, handoff); + } else { + ret = abrec_run_spl(blk, image, handoff); + } + } + + /* Record that VBE was used in this phase */ + handoff->phases |= 1 << xpl_phase(); + + return 0; +} +SPL_LOAD_IMAGE_METHOD("vbe_abrec", 5, BOOT_DEVICE_VBE, + abrec_load_from_image); diff --git a/boot/vbe_common.c b/boot/vbe_common.c index 0d51fe762c3..a86986d86e9 100644 --- a/boot/vbe_common.c +++ b/boot/vbe_common.c @@ -202,29 +202,30 @@ int vbe_read_fit(struct udevice *blk, ulong area_offset, ulong area_size, phase = IS_ENABLED(CONFIG_TPL_BUILD) ? IH_PHASE_NONE : IS_ENABLED(CONFIG_VPL_BUILD) ? IH_PHASE_SPL : IH_PHASE_U_BOOT; - /* - * Load the image from the FIT. We ignore any load-address information - * so in practice this simply locates the image in the external-data - * region and returns its address and size. Since we only loaded the FIT - * itself, only a part of the image will be present, at best. - */ - fit_uname = NULL; - fit_uname_config = NULL; log_debug("loading FIT\n"); if (xpl_phase() == PHASE_SPL && !IS_ENABLED(CONFIG_SANDBOX)) { struct spl_load_info info; spl_load_init(&info, h_vbe_load_read, desc, desc->blksz); + xpl_set_fdt_update(&info, false); xpl_set_phase(&info, IH_PHASE_U_BOOT); log_debug("doing SPL from %s blksz %lx log2blksz %x area_offset %lx + fdt_size %lx\n", blk->name, desc->blksz, desc->log2blksz, area_offset, ALIGN(size, 4)); ret = spl_load_simple_fit(image, &info, area_offset, buf); - log_debug("spl_load_abrec_fit() ret=%d\n", ret); + log_debug("spl_load_simple_fit() ret=%d\n", ret); return ret; } + /* + * Load the image from the FIT. We ignore any load-address information + * so in practice this simply locates the image in the external-data + * region and returns its address and size. Since we only loaded the FIT + * itself, only a part of the image will be present, at best. + */ + fit_uname = NULL; + fit_uname_config = NULL; ret = fit_image_load(&images, addr, &fit_uname, &fit_uname_config, IH_ARCH_DEFAULT, image_ph(phase, IH_TYPE_FIRMWARE), BOOTSTAGE_ID_FIT_SPL_START, FIT_LOAD_IGNORED, @@ -373,3 +374,8 @@ int vbe_read_fit(struct udevice *blk, ulong area_offset, ulong area_size, return 0; } + +ofnode vbe_get_node(void) +{ + return ofnode_path("/bootstd/firmware0"); +} diff --git a/boot/vbe_common.h b/boot/vbe_common.h index 84117815a19..493cbdc3694 100644 --- a/boot/vbe_common.h +++ b/boot/vbe_common.h @@ -9,6 +9,8 @@ #ifndef __VBE_COMMON_H #define __VBE_COMMON_H +#include <dm/ofnode_decl.h> +#include <linux/bitops.h> #include <linux/types.h> struct spl_image_info; @@ -39,6 +41,40 @@ enum { }; /** + * enum vbe_try_result - result of trying a firmware pick + * + * @VBETR_UNKNOWN: Unknown / invalid result + * @VBETR_TRYING: Firmware pick is being tried + * @VBETR_OK: Firmware pick is OK and can be used from now on + * @VBETR_BAD: Firmware pick is bad and should be removed + */ +enum vbe_try_result { + VBETR_UNKNOWN, + VBETR_TRYING, + VBETR_OK, + VBETR_BAD, +}; + +/** + * enum vbe_flags - flags controlling operation + * + * @VBEF_TRY_COUNT_MASK: mask for the 'try count' value + * @VBEF_TRY_B: Try the B slot + * @VBEF_RECOVERY: Use recovery slot + */ +enum vbe_flags { + VBEF_TRY_COUNT_MASK = 0x3, + VBEF_TRY_B = BIT(2), + VBEF_RECOVERY = BIT(3), + + VBEF_RESULT_SHIFT = 4, + VBEF_RESULT_MASK = 3 << VBEF_RESULT_SHIFT, + + VBEF_PICK_SHIFT = 6, + VBEF_PICK_MASK = 3 << VBEF_PICK_SHIFT, +}; + +/** * struct vbe_nvdata - basic storage format for non-volatile data * * This is used for all VBE methods @@ -134,4 +170,11 @@ int vbe_read_fit(struct udevice *blk, ulong area_offset, ulong area_size, struct spl_image_info *image, ulong *load_addrp, ulong *lenp, char **namep); +/** + * vbe_get_node() - Get the node containing the VBE settings + * + * Return: VBE node (typically "/bootstd/firmware0") + */ +ofnode vbe_get_node(void); + #endif /* __VBE_ABREC_H */ diff --git a/cmd/Kconfig b/cmd/Kconfig index d00e743db36..1f9b26928c4 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -280,13 +280,13 @@ config CMD_BOOTM Boot an application image from the memory. config CMD_BOOTM_PRE_LOAD - bool "enable pre-load on bootm" - depends on CMD_BOOTM - depends on IMAGE_PRE_LOAD - help - Enable support of stage pre-load for the bootm command. - This stage allow to check or modify the image provided - to the bootm command. + bool "enable pre-load on bootm" + depends on CMD_BOOTM + depends on IMAGE_PRE_LOAD + help + Enable support of stage pre-load for the bootm command. + This stage allow to check or modify the image provided + to the bootm command. config CMD_BOOTDEV bool "bootdev" @@ -1178,16 +1178,30 @@ config CMD_FPGA help FPGA support. -config CMD_FPGA_LOADBP - bool "fpga loadbp - load partial bitstream (Xilinx only)" +config CMD_FPGA_LOADB + bool "fpga loadb - load bitstream file" + default y + depends on CMD_FPGA && FPGA_XILINX + help + Supports loading an FPGA device from a bitstream file (.BIT) + +config CMD_FPGA_LOADP + bool "fpga loadp - load partial bitstream" depends on CMD_FPGA help - Supports loading an FPGA device from a bitstream buffer containing - a partial bitstream. + Supports loading an FPGA device from a bitstream buffer (.BIN) + containing a partial bitstream. + +config CMD_FPGA_LOADBP + bool "fpga loadbp - load partial bitstream file" + depends on CMD_FPGA && FPGA_XILINX + help + Supports loading an FPGA device from a bitstream file (.BIT) + containing a partial bitstream. config CMD_FPGA_LOADFS - bool "fpga loadfs - load bitstream from FAT filesystem (Xilinx only)" - depends on CMD_FPGA + bool "fpga loadfs - load bitstream from FAT filesystem" + depends on CMD_FPGA && FPGA_XILINX help Supports loading an FPGA device from a FAT filesystem. @@ -1197,16 +1211,9 @@ config CMD_FPGA_LOADMK help Supports loading an FPGA device from a image generated by mkimage. -config CMD_FPGA_LOADP - bool "fpga loadp - load partial bitstream" - depends on CMD_FPGA - help - Supports loading an FPGA device from a bitstream buffer containing - a partial bitstream. - config CMD_FPGA_LOAD_SECURE bool "fpga loads - loads secure bitstreams" - depends on CMD_FPGA + depends on CMD_FPGA && FPGA_XILINX select FPGA_LOAD_SECURE help Enables the fpga loads command which is used to load secure @@ -1811,7 +1818,7 @@ config CMD_SETEXPR_FMT depends on CMD_SETEXPR help Evaluate format string expression and store result in an environment - variable. + variable. config CMD_XXD bool "xxd" @@ -2154,12 +2161,12 @@ config WGET_HTTPS depends on CMD_WGET depends on PROT_TCP_LWIP depends on MBEDTLS_LIB - select SHA256 - select RSA - select ASYMMETRIC_KEY_TYPE - select ASYMMETRIC_PUBLIC_KEY_SUBTYPE - select X509_CERTIFICATE_PARSER - select PKCS7_MESSAGE_PARSER + select SHA256 + select RSA + select ASYMMETRIC_KEY_TYPE + select ASYMMETRIC_PUBLIC_KEY_SUBTYPE + select X509_CERTIFICATE_PARSER + select PKCS7_MESSAGE_PARSER select MBEDTLS_LIB_CRYPTO select MBEDTLS_LIB_TLS select RSA_VERIFY_WITH_PKEY @@ -2238,10 +2245,10 @@ config CMD_BLKMAP depends on BLKMAP default y if BLKMAP help - Create virtual block devices that are backed by various sources, - e.g. RAM, or parts of an existing block device. Though much more - rudimentary, it borrows a lot of ideas from Linux's device mapper - subsystem. + Create virtual block devices that are backed by various sources, + e.g. RAM, or parts of an existing block device. Though much more + rudimentary, it borrows a lot of ideas from Linux's device mapper + subsystem. Example use-cases: - Treat a region of RAM as a block device, i.e. a RAM disk. This let's @@ -3027,10 +3034,10 @@ config CMD_UBI partition support. config CMD_UBI_RENAME - bool "Enable rename" - depends on CMD_UBI - help - Enable a "ubi" command to rename ubi volume: + bool "Enable rename" + depends on CMD_UBI + help + Enable a "ubi" command to rename ubi volume: ubi rename <oldname> <newname> config CMD_UBIFS diff --git a/cmd/fpga.c b/cmd/fpga.c index 93f14098ccb..9dc7b63db5d 100644 --- a/cmd/fpga.c +++ b/cmd/fpga.c @@ -67,7 +67,8 @@ static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size, } #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) -int do_fpga_loads(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +static int do_fpga_loads(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) { size_t data_size = 0; long fpga_data, dev; @@ -180,6 +181,7 @@ static int do_fpga_load(struct cmd_tbl *cmdtp, int flag, int argc, return fpga_load(dev, (void *)fpga_data, data_size, BIT_FULL, 0); } +#if defined(CONFIG_CMD_FPGA_LOADB) static int do_fpga_loadb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -194,7 +196,7 @@ static int do_fpga_loadb(struct cmd_tbl *cmdtp, int flag, int argc, return fpga_loadbitstream(dev, (void *)fpga_data, data_size, BIT_FULL); } - +#endif #if defined(CONFIG_CMD_FPGA_LOADP) static int do_fpga_loadp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -356,7 +358,9 @@ static struct cmd_tbl fpga_commands[] = { U_BOOT_CMD_MKENT(info, 1, 1, do_fpga_info, "", ""), U_BOOT_CMD_MKENT(dump, 3, 1, do_fpga_dump, "", ""), U_BOOT_CMD_MKENT(load, 3, 1, do_fpga_load, "", ""), +#if defined(CONFIG_CMD_FPGA_LOADB) U_BOOT_CMD_MKENT(loadb, 3, 1, do_fpga_loadb, "", ""), +#endif #if defined(CONFIG_CMD_FPGA_LOADP) U_BOOT_CMD_MKENT(loadp, 3, 1, do_fpga_loadp, "", ""), #endif @@ -408,49 +412,40 @@ U_BOOT_CMD(fpga, 9, 1, do_fpga_wrapper, #else U_BOOT_CMD(fpga, 6, 1, do_fpga_wrapper, #endif - "loadable FPGA image support", - "[operation type] [device number] [image address] [image size]\n" - "fpga operations:\n" - " dump\t[dev] [address] [size]\tLoad device to memory buffer\n" - " info\t[dev]\t\t\tlist known device information\n" - " load\t[dev] [address] [size]\tLoad device from memory buffer\n" + "loadable FPGA image support", + "info [dev] List known device information\n" + "fpga dump <dev> <address> <size> Load device to memory buffer\n" + "fpga load <dev> <address> <size> Load device from memory buffer\n" +#if defined(CONFIG_CMD_FPGA_LOADP) + "fpga loadb <dev> <address> <size> Load device from bitstream buffer\n" +#endif #if defined(CONFIG_CMD_FPGA_LOADP) - " loadp\t[dev] [address] [size]\t" - "Load device from memory buffer with partial bitstream\n" + "fpga loadp <dev> <address> <size> Load device from memory buffer\n" + " with partial bitstream\n" #endif - " loadb\t[dev] [address] [size]\t" - "Load device from bitstream buffer (Xilinx only)\n" #if defined(CONFIG_CMD_FPGA_LOADBP) - " loadbp\t[dev] [address] [size]\t" - "Load device from bitstream buffer with partial bitstream" - "(Xilinx only)\n" + "fpga loadbp <dev> <address> <size> Load device from bitstream buffer\n" + " with partial bitstream\n" #endif #if defined(CONFIG_CMD_FPGA_LOADFS) - "Load device from filesystem (FAT by default) (Xilinx only)\n" - " loadfs [dev] [address] [image size] [blocksize] <interface>\n" - " [<dev[:part]>] <filename>\n" + "fpga loadfs <dev> <address> <size> <blocksize> <interface> [<dev[:part]>] <filename>\n" + " Load device from filesystem (FAT by default)\n" #endif #if defined(CONFIG_CMD_FPGA_LOADMK) - " loadmk [dev] [address]\tLoad device generated with mkimage" + "fpga loadmk <dev> <address> Load device generated with mkimage\n" #if defined(CONFIG_FIT) - "\n" - "\tFor loadmk operating on FIT format uImage address must include\n" - "\tsubimage unit name in the form of addr:<subimg_uname>" + " NOTE: loadmk operating on FIT must include subimage unit\n" + " name in the form of addr:<subimg_uname>\n" #endif #endif #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) - "Load encrypted bitstream (Xilinx only)\n" - " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n" - " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n" - "Loads the secure bistreams(authenticated/encrypted/both\n" - "authenticated and encrypted) of [size] from [address].\n" - "The auth-OCM/DDR flag specifies to perform authentication\n" - "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n" - "The enc flag specifies which key to be used for decryption\n" - "0-device key, 1-user key, 2-no encryption.\n" - "The optional Userkey address specifies from which address key\n" - "has to be used for decryption if user key is selected.\n" - "NOTE: the secure bitstream has to be created using Xilinx\n" - "bootgen tool only.\n" + "fpga loads <dev> <address> <size> <authflag> <encflag> [Userkey address]\n" + " Load device from memory buffer with secure bistream\n" + " (authenticated/encrypted/both)\n" + " -authflag: 0 for OCM, 1 for DDR, 2 for no authentication\n" + " (specifies where to perform authentication)\n" + " -encflag: 0 for device key, 1 for user key, 2 for no encryption\n" + " -Userkey address: address where user key is stored\n" + " NOTE: secure bitstream has to be created using Xilinx bootgen tool\n" #endif ); diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index 5ecf56781c1..b013c8c8d4e 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -30,6 +30,7 @@ static struct sbi_imp implementations[] = { { 8, "PolarFire Hart Software Services" }, { 9, "coreboot" }, { 10, "oreboot" }, + { 11, "bhyve" }, }; static struct sbi_ext extensions[] = { diff --git a/cmd/setexpr.c b/cmd/setexpr.c index e111b8ba98a..c45fa85c887 100644 --- a/cmd/setexpr.c +++ b/cmd/setexpr.c @@ -35,9 +35,37 @@ struct expr_arg { }; }; +/** + * arg_set_str() - copy string to expression argument + * + * The string is truncated to 64 KiB plus NUL terminator. + * + * @p: pointer to string + * @argp: pointer to expression argument + * Return: 0 on success, -ENOMEM if out of memory + */ +static int arg_set_str(void *p, struct expr_arg *argp) +{ + int len; + char *str; + + /* Maximum string length of 64 KiB plus NUL terminator */ + len = strnlen((char *)p, SZ_64K) + 1; + str = malloc(len); + if (!str) { + printf("Out of memory\n"); + return -ENOMEM; + } + memcpy(str, p, len); + str[len - 1] = '\0'; + argp->sval = str; + return 0; +} + static int get_arg(char *s, int w, struct expr_arg *argp) { struct expr_arg arg; + int ret; /* * If the parameter starts with a '*' then assume it is a pointer to @@ -47,8 +75,6 @@ static int get_arg(char *s, int w, struct expr_arg *argp) ulong *p; ulong addr; ulong val; - int len; - char *str; addr = hextoul(&s[1], NULL); switch (w) { @@ -66,18 +92,10 @@ static int get_arg(char *s, int w, struct expr_arg *argp) break; case CMD_DATA_SIZE_STR: p = map_sysmem(addr, SZ_64K); - - /* Maximum string length of 64KB plus terminator */ - len = strnlen((char *)p, SZ_64K) + 1; - str = malloc(len); - if (!str) { - printf("Out of memory\n"); - return -ENOMEM; - } - memcpy(str, p, len); - str[len - 1] = '\0'; + ret = arg_set_str(p, &arg); unmap_sysmem(p); - arg.sval = str; + if (ret) + return ret; break; case 4: p = map_sysmem(addr, sizeof(u32)); @@ -93,9 +111,13 @@ static int get_arg(char *s, int w, struct expr_arg *argp) break; } } else { - if (w == CMD_DATA_SIZE_STR) - return -EINVAL; - arg.ival = hextoul(s, NULL); + if (w == CMD_DATA_SIZE_STR) { + ret = arg_set_str(s, &arg); + if (ret) + return ret; + } else { + arg.ival = hextoul(s, NULL); + } } *argp = arg; diff --git a/common/autoboot.c b/common/autoboot.c index 898a57bc92b..0a254498d40 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -186,10 +186,15 @@ static int passwd_abort_sha256(uint64_t etime) ret = hash_parse_string(algo_name, sha_env_str, sha_env); if (ret) { printf("Hash %s not supported!\n", algo_name); + free(presskey); return 0; } sha = malloc_cache_aligned(SHA256_SUM_LEN); + if (!sha) { + free(presskey); + return -ENOMEM; + } size = SHA256_SUM_LEN; /* * We don't know how long the stop-string is, so we need to diff --git a/common/bloblist.c b/common/bloblist.c index 1fcd387593c..31ba0311090 100644 --- a/common/bloblist.c +++ b/common/bloblist.c @@ -223,13 +223,26 @@ static int bloblist_ensurerec(uint tag, struct bloblist_rec **recp, int size, void *bloblist_find(uint tag, int size) { + void *blob = NULL; + int blob_size; + + blob = bloblist_get_blob(tag, &blob_size); + + if (size && size != blob_size) + return NULL; + + return blob; +} + +void *bloblist_get_blob(uint tag, int *sizep) +{ struct bloblist_rec *rec; rec = bloblist_findrec(tag); if (!rec) return NULL; - if (size && size != rec->size) - return NULL; + + *sizep = rec->size; return (void *)rec + rec_hdr_size(rec); } diff --git a/common/cli_hush.c b/common/cli_hush.c index a6a8edce1f4..9f437ae5f47 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -3626,7 +3626,13 @@ static char *make_string(char **inp, int *nonnull) noeval = 1; for (n = 0; inp[n]; n++) { p = insert_var_value_sub(inp[n], noeval); - str = xrealloc(str, (len + strlen(p) + (2 * nonnull[n]))); + char *new_str = xrealloc(str, (len + strlen(p) + (2 * nonnull[n]))); + if (!new_str) { + free(str); + if (p != inp[n]) free(p); + return NULL; + } + str = new_str; if (n) { strcat(str, " "); } else { diff --git a/common/hash.c b/common/hash.c index 8dd9da85768..0c45992d5c7 100644 --- a/common/hash.c +++ b/common/hash.c @@ -143,7 +143,8 @@ static int __maybe_unused hash_finish_sha512(struct hash_algo *algo, void *ctx, return 0; } -static int hash_init_crc16_ccitt(struct hash_algo *algo, void **ctxp) +static int __maybe_unused hash_init_crc16_ccitt(struct hash_algo *algo, + void **ctxp) { uint16_t *ctx = malloc(sizeof(uint16_t)); *ctx = 0; @@ -151,16 +152,18 @@ static int hash_init_crc16_ccitt(struct hash_algo *algo, void **ctxp) return 0; } -static int hash_update_crc16_ccitt(struct hash_algo *algo, void *ctx, - const void *buf, unsigned int size, - int is_last) +static int __maybe_unused hash_update_crc16_ccitt(struct hash_algo *algo, + void *ctx, const void *buf, + unsigned int size, + int is_last) { *((uint16_t *)ctx) = crc16_ccitt(*((uint16_t *)ctx), buf, size); return 0; } -static int hash_finish_crc16_ccitt(struct hash_algo *algo, void *ctx, - void *dest_buf, int size) +static int __maybe_unused hash_finish_crc16_ccitt(struct hash_algo *algo, + void *ctx, void *dest_buf, + int size) { if (size < algo->digest_size) return -1; @@ -295,6 +298,7 @@ static struct hash_algo hash_algo[] = { #endif }, #endif +#if CONFIG_IS_ENABLED(CRC16) { .name = "crc16-ccitt", .digest_size = 2, @@ -304,6 +308,7 @@ static struct hash_algo hash_algo[] = { .hash_update = hash_update_crc16_ccitt, .hash_finish = hash_finish_crc16_ccitt, }, +#endif #if CONFIG_IS_ENABLED(CRC8) && IS_ENABLED(CONFIG_HASH_CRC8) { .name = "crc8", diff --git a/common/spl/Kconfig.vpl b/common/spl/Kconfig.vpl index 97dfc630152..cf6b36c8e38 100644 --- a/common/spl/Kconfig.vpl +++ b/common/spl/Kconfig.vpl @@ -9,6 +9,19 @@ config VPL_BANNER_PRINT info. Disabling this option could be useful to reduce VPL boot time (e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud). +config VPL_LDSCRIPT + string "Linker script for the VPL stage" + default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 + default "arch/\$(ARCH)/cpu/u-boot-spl.lds" + help + The TPL stage will usually require a different linker-script + (as it runs from a different memory region) than the regular + U-Boot stage. Set this to the path of the linker-script to + be used for TPL. + + May be left empty to trigger the Makefile infrastructure to + fall back to the linker-script used for the SPL stage. + config VPL_BOARD_INIT bool "Call board-specific initialization in VPL" help diff --git a/common/spl/spl.c b/common/spl/spl.c index 9af0a4954d4..76fd56dfe4b 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -50,8 +50,10 @@ u32 *boot_params_ptr = NULL; #if CONFIG_IS_ENABLED(BINMAN_UBOOT_SYMBOLS) /* See spl.h for information about this */ +#if defined(CONFIG_SPL_BUILD) binman_sym_declare(ulong, u_boot_any, image_pos); binman_sym_declare(ulong, u_boot_any, size); +#endif #ifdef CONFIG_TPL binman_sym_declare(ulong, u_boot_spl_any, image_pos); @@ -179,9 +181,15 @@ ulong spl_get_image_pos(void) if (xpl_next_phase() == PHASE_VPL) return binman_sym(ulong, u_boot_vpl_any, image_pos); #endif - return xpl_next_phase() == PHASE_SPL ? - binman_sym(ulong, u_boot_spl_any, image_pos) : - binman_sym(ulong, u_boot_any, image_pos); +#if defined(CONFIG_TPL) && !defined(CONFIG_VPL) + if (xpl_next_phase() == PHASE_SPL) + return binman_sym(ulong, u_boot_spl_any, image_pos); +#endif +#if defined(CONFIG_SPL_BUILD) + return binman_sym(ulong, u_boot_any, image_pos); +#endif + + return BINMAN_SYM_MISSING; } ulong spl_get_image_size(void) @@ -263,14 +271,20 @@ void spl_set_header_raw_uboot(struct spl_image_info *spl_image) */ if (u_boot_pos && u_boot_pos != BINMAN_SYM_MISSING) { /* Binman does not support separated entry addresses */ - spl_image->entry_point = u_boot_pos; - spl_image->load_addr = u_boot_pos; + spl_image->entry_point = spl_get_image_text_base(); + spl_image->load_addr = spl_get_image_text_base(); + spl_image->size = spl_get_image_size(); + log_debug("Next load addr %lx\n", spl_image->load_addr); } else { spl_image->entry_point = CONFIG_SYS_UBOOT_START; spl_image->load_addr = CONFIG_TEXT_BASE; + log_debug("Default load addr %x (u_boot_pos=%lx)\n", + CONFIG_TEXT_BASE, u_boot_pos); } spl_image->os = IH_OS_U_BOOT; - spl_image->name = "U-Boot"; + spl_image->name = xpl_name(xpl_next_phase()); + log_debug("Next phase: %s at %lx size %lx\n", spl_image->name, + spl_image->load_addr, (ulong)spl_image->size); } __weak int spl_parse_board_header(struct spl_image_info *spl_image, diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 64c4349b138..49b4df60560 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -199,7 +199,9 @@ static int get_aligned_image_size(struct spl_load_info *info, int data_size, * the image gets loaded to the address pointed to by the * load_addr member in this struct, if load_addr is not 0 * - * Return: 0 on success or a negative error number. + * Return: 0 on success, -EPERM if this image is not the correct phase + * (for CONFIG_BOOTMETH_VBE_SIMPLE_FW), or another negative error number on + * other error. */ static int load_simple_fit(struct spl_load_info *info, ulong fit_offset, const struct spl_fit_info *ctx, int node, @@ -218,6 +220,25 @@ static int load_simple_fit(struct spl_load_info *info, ulong fit_offset, const void *fit = ctx->fit; bool external_data = false; + log_debug("starting\n"); + if (CONFIG_IS_ENABLED(BOOTMETH_VBE) && + xpl_get_phase(info) != IH_PHASE_NONE) { + enum image_phase_t phase; + int ret; + + ret = fit_image_get_phase(fit, node, &phase); + /* if the image is for any phase, let's use it */ + if (ret == -ENOENT || phase == xpl_get_phase(info)) { + log_debug("found\n"); + } else if (ret < 0) { + log_debug("err=%d\n", ret); + return ret; + } else { + log_debug("- phase mismatch, skipping this image\n"); + return -EPERM; + } + } + if (IS_ENABLED(CONFIG_SPL_FPGA) || (IS_ENABLED(CONFIG_SPL_OS_BOOT) && spl_decompression_enabled())) { if (fit_image_get_type(fit, node, &type)) @@ -278,10 +299,7 @@ static int load_simple_fit(struct spl_load_info *info, ulong fit_offset, log_debug("reading from offset %x / %lx size %lx to %p: ", offset, read_offset, size, src_ptr); - if (info->read(info, - fit_offset + - get_aligned_image_offset(info, offset), size, - src_ptr) < length) + if (info->read(info, read_offset, size, src_ptr) < length) return -EIO; debug("External data: dst=%p, offset=%x, size=%lx\n", @@ -456,7 +474,9 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image, image_info.load_addr = (ulong)tmpbuffer; ret = load_simple_fit(info, offset, ctx, node, &image_info); - if (ret < 0) + if (ret == -EPERM) + continue; + else if (ret < 0) break; /* Make room in FDT for changes from the overlay */ @@ -495,9 +515,6 @@ static int spl_fit_record_loadable(const struct spl_fit_info *ctx, int index, const char *name; int node; - if (CONFIG_IS_ENABLED(FIT_IMAGE_TINY)) - return 0; - ret = spl_fit_get_image_name(ctx, "loadables", index, &name); if (ret < 0) return ret; @@ -817,7 +834,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, image_info.load_addr = 0; ret = load_simple_fit(info, offset, &ctx, node, &image_info); - if (ret < 0) { + if (ret < 0 && ret != -EPERM) { printf("%s: can't load image loadables index %d (ret = %d)\n", __func__, index, ret); return ret; @@ -843,7 +860,8 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, spl_image->entry_point = image_info.entry_point; /* Record our loadables into the FDT */ - if (spl_image->fdt_addr) + if (!CONFIG_IS_ENABLED(FIT_IMAGE_TINY) && + xpl_get_fdt_update(info) && spl_image->fdt_addr) spl_fit_record_loadable(&ctx, index, spl_image->fdt_addr, &image_info); diff --git a/common/spl/spl_reloc.c b/common/spl/spl_reloc.c index be8349b535b..324b98eaf98 100644 --- a/common/spl/spl_reloc.c +++ b/common/spl/spl_reloc.c @@ -154,7 +154,7 @@ int spl_reloc_jump(struct spl_image_info *image, spl_jump_to_image_t jump) rcode_func loader; int ret; - log_debug("malloc usage %lx bytes (%ld KB of %d KB)\n", gd->malloc_ptr, + log_debug("malloc usage %x bytes (%d KB of %d KB)\n", gd->malloc_ptr, gd->malloc_ptr / 1024, CONFIG_VAL(SYS_MALLOC_F_LEN) / 1024); if (*image->stack_prot != STACK_PROT_VALUE) { diff --git a/config.mk b/config.mk index e294be2a4c4..abed9cb65c6 100644 --- a/config.mk +++ b/config.mk @@ -76,4 +76,3 @@ export PLATFORM_CPPFLAGS export RELFLAGS export LDFLAGS_FINAL export LDFLAGS_STANDALONE -export CONFIG_STANDALONE_LOAD_ADDR diff --git a/configs/alt_defconfig b/configs/alt_defconfig index 488115d9a5c..7b16923e34d 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -38,7 +38,6 @@ CONFIG_SH_MMCIF=y CONFIG_DM_MTD=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_SH_ETHER=y diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig index 1f7750c4c03..58cad17b5d5 100644 --- a/configs/am62ax_evm_r5_defconfig +++ b/configs/am62ax_evm_r5_defconfig @@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-r5-sk" CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7145 CONFIG_SPL_TEXT_BASE=0x43c00000 @@ -82,6 +83,8 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y +CONFIG_SPL_MISC=y +CONFIG_ESM_K3=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index c3adfb8697a..54ea4bfb620 100644 --- a/configs/am62px_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -16,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-r5-sk" CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_TEXT_BASE=0x43c00000 @@ -87,6 +88,8 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y +CONFIG_SPL_MISC=y +CONFIG_ESM_K3=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig index af54f9670a7..a8a73166597 100644 --- a/configs/am62x_beagleplay_a53_defconfig +++ b/configs/am62x_beagleplay_a53_defconfig @@ -30,7 +30,6 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y -CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index c77e09db156..6527200259e 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -33,7 +33,6 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y -CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_BOOTCOMMAND="run findfdt; run envboot; bootflow scan -lb" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 diff --git a/configs/am62x_r5_usbdfu.config b/configs/am62x_r5_usbdfu.config index efaae504c1a..62c9247c582 100644 --- a/configs/am62x_r5_usbdfu.config +++ b/configs/am62x_r5_usbdfu.config @@ -23,6 +23,5 @@ CONFIG_SPL_DFU=y # CONFIG_SPL_SPI is not set # CONFIG_SPL_SYS_MALLOC is not set # CONFIG_CMD_GPT is not set -# CONFIG_CMD_MMC is not set # CONFIG_CMD_FAT is not set -# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC is not set diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 4bd5e8f63ff..289c41c3eb5 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -24,7 +24,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x41c7effc CONFIG_SPL_BSS_MAX_SIZE=0xc00 CONFIG_SPL_STACK_R=y -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SPL_SIZE_LIMIT=0x7ec00 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000 CONFIG_SPL_FS_FAT=y diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig index ae57007d898..0b5eaeb363d 100644 --- a/configs/am65x_evm_r5_usbdfu_defconfig +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -22,7 +22,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x41c7effc CONFIG_SPL_BSS_MAX_SIZE=0xc00 CONFIG_SPL_STACK_R=y -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SPL_SIZE_LIMIT=0x7ec00 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000 CONFIG_SPL_LIBDISK_SUPPORT=y diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig index 3aa17eb77f0..ef2ff411172 100644 --- a/configs/am65x_evm_r5_usbmsc_defconfig +++ b/configs/am65x_evm_r5_usbmsc_defconfig @@ -22,7 +22,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x41c7effc CONFIG_SPL_BSS_MAX_SIZE=0xc00 CONFIG_SPL_STACK_R=y -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SPL_SIZE_LIMIT=0x7ec00 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000 CONFIG_SPL_FS_FAT=y diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index b4aebf3e9fb..8bee002777a 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -17,6 +17,7 @@ CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_REMAKE_ELF=y +CONFIG_EFI_HTTP_BOOT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y @@ -30,6 +31,8 @@ CONFIG_SYS_PROMPT="versal2> " CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y @@ -39,15 +42,13 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_MMC_SPEED_MODE_SET=y +CONFIG_CMD_OPTEE=y CONFIG_CMD_MTD=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_SPI=y CONFIG_CMD_UFS=y CONFIG_CMD_USB=y -CONFIG_BOOTP_MAY_FAIL=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_NFS=y +CONFIG_WGET_HTTPS=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y @@ -67,9 +68,7 @@ CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NETCONSOLE=y -CONFIG_IP_DEFRAG=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SIMPLE_PM_BUS=y @@ -152,5 +151,7 @@ CONFIG_UFS_AMD_VERSAL2=y CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y +CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y # CONFIG_OPTEE_LIB is not set +CONFIG_TOOLS_MKFWUMDATA=y diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index 2d6c83a5d5f..e6242e22509 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -85,7 +85,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_MV=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y diff --git a/configs/coreprimevelte_defconfig b/configs/coreprimevelte_defconfig new file mode 100644 index 00000000000..05116669200 --- /dev/null +++ b/configs/coreprimevelte_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=26000000 +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_MMP=y +CONFIG_TEXT_BASE=0x1000000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEFAULT_DEVICE_TREE="pxa1908-samsung-coreprimevelte" +CONFIG_TARGET_COREPRIMEVELTE=y +CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_ARMV8_PSCI=y +CONFIG_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_DM=y +CONFIG_OF_BOARD=y +CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig index c36196c510c..5facd418260 100644 --- a/configs/e850-96_defconfig +++ b/configs/e850-96_defconfig @@ -8,23 +8,40 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ARCH_EXYNOS9=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="exynos/exynos850-e850-96" CONFIG_SYS_LOAD_ADDR=0x80000000 +CONFIG_ENV_OFFSET_REDUND=0x10000 # CONFIG_PSCI_RESET is not set +CONFIG_EFI_SET_TIME=y CONFIG_ANDROID_BOOT_IMAGE=y -# CONFIG_AUTOBOOT is not set +CONFIG_BOOTSTD_FULL=y +CONFIG_DEFAULT_FDT_FILE="exynos850-e850-96.dtb" # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_ABOOTIMG=y +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_CLK=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y +CONFIG_CMD_EFIDEBUG=y +# CONFIG_CMD_DATE is not set +CONFIG_CMD_RTC=y CONFIG_CMD_TIME=y CONFIG_CMD_RNG=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 CONFIG_NO_NET=y CONFIG_CLK_EXYNOS850=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y CONFIG_SOC_SAMSUNG=y CONFIG_EXYNOS_PMU=y CONFIG_EXYNOS_USI=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig index d212f91bf83..b53f2f37409 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -36,7 +36,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k CONFIG_DM_MTD=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_SH_ETHER=y diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig index a4005438c19..d2cc1cf7981 100644 --- a/configs/grpeach_defconfig +++ b/configs/grpeach_defconfig @@ -52,7 +52,6 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_SMSC=y CONFIG_DM_ETH_PHY=y CONFIG_SH_ETHER=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index e1ef6e86d49..ac5b10ba149 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -144,6 +144,7 @@ CONFIG_SPI_FLASH_S28HX_T=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y CONFIG_MULTIPLEXER=y +CONFIG_MUX_MMIO=y CONFIG_PHY_TI_DP83869=y CONFIG_PHY_FIXED=y CONFIG_TI_AM65_CPSW_NUSS=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 3928430f166..1ddb1965d8b 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -151,7 +151,7 @@ CONFIG_SPI_FLASH_MT35XU=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y CONFIG_MULTIPLEXER=y -CONFIG_SPL_MUX_MMIO=y +CONFIG_MUX_MMIO=y CONFIG_PHY_TI_DP83867=y CONFIG_PHY_FIXED=y CONFIG_TI_AM65_CPSW_NUSS=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 42000cc5dc5..c4e9f2d43b1 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -26,7 +26,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x41cf59f0 CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_STACK_R=y -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SPL_SIZE_LIMIT=0xf59f0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 23ae991e2f6..7ec9af8bc48 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -26,7 +26,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x41c76000 CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_STACK_R=y -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SPL_SIZE_LIMIT=0x80000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index 9bce9e33104..eeb97474b2a 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -36,7 +36,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k CONFIG_DM_MTD=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_SH_ETHER=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig index 0d4eed0ddf7..b5682526c8c 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -38,7 +38,6 @@ CONFIG_SH_MMCIF=y CONFIG_DM_MTD=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_SH_ETHER=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 2e618d81544..87756cb26df 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -42,6 +42,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_SPL=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_GPIO=y CONFIG_CMD_SAVES=y CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/mt7987_emmc_rfb_defconfig b/configs/mt7987_emmc_rfb_defconfig new file mode 100644 index 00000000000..022ca32169b --- /dev/null +++ b/configs/mt7987_emmc_rfb_defconfig @@ -0,0 +1,91 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7987a-emmc-rfb" +CONFIG_TARGET_MT7987=y +CONFIG_SYS_BOOTM_LEN=0x6000000 +CONFIG_SYS_LOAD_ADDR=0x48000000 +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_DEBUG_UART=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +# CONFIG_AUTOBOOT is not set +CONFIG_DEFAULT_FDT_FILE="mt7987a-emmc-rfb" +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 +CONFIG_LOG=y +CONFIG_SYS_PROMPT="MT7987> " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_UNLZ4 is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_PWM=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PING=y +CONFIG_CMD_SMC=y +CONFIG_EFI_PARTITION=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.2" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MTK=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_PUYA=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI=y +CONFIG_PHY_ETHERNET_ID=y +CONFIG_MEDIATEK_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7987=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_DM_PWM=y +CONFIG_PWM_MTK=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y +CONFIG_HEXDUMP=y diff --git a/configs/mt7987_rfb_defconfig b/configs/mt7987_rfb_defconfig new file mode 100644 index 00000000000..00e3cea5264 --- /dev/null +++ b/configs/mt7987_rfb_defconfig @@ -0,0 +1,87 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7987a-rfb" +CONFIG_TARGET_MT7987=y +CONFIG_SYS_BOOTM_LEN=0x6000000 +CONFIG_SYS_LOAD_ADDR=0x48000000 +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_DEBUG_UART=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +# CONFIG_AUTOBOOT is not set +CONFIG_DEFAULT_FDT_FILE="mt7987a-rfb" +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 +CONFIG_LOG=y +CONFIG_SYS_PROMPT="MT7987> " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_UNLZ4 is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_PWM=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PING=y +CONFIG_CMD_SMC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.2" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MTK=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_PUYA=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI=y +CONFIG_PHY_ETHERNET_ID=y +CONFIG_MEDIATEK_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7987=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_DM_PWM=y +CONFIG_PWM_MTK=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y +CONFIG_HEXDUMP=y diff --git a/configs/mt7987_sd_rfb_defconfig b/configs/mt7987_sd_rfb_defconfig new file mode 100644 index 00000000000..ca7714b1242 --- /dev/null +++ b/configs/mt7987_sd_rfb_defconfig @@ -0,0 +1,91 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7987a-sd-rfb" +CONFIG_TARGET_MT7987=y +CONFIG_SYS_BOOTM_LEN=0x6000000 +CONFIG_SYS_LOAD_ADDR=0x48000000 +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_DEBUG_UART=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +# CONFIG_AUTOBOOT is not set +CONFIG_DEFAULT_FDT_FILE="mt7987a-sd-rfb" +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 +CONFIG_LOG=y +CONFIG_SYS_PROMPT="MT7987> " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_UNLZ4 is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_PWM=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PING=y +CONFIG_CMD_SMC=y +CONFIG_EFI_PARTITION=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.2" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MTK=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_PUYA=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI=y +CONFIG_PHY_ETHERNET_ID=y +CONFIG_MEDIATEK_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7987=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_DM_PWM=y +CONFIG_PWM_MTK=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y +CONFIG_HEXDUMP=y diff --git a/configs/mvebu_espressobin_ultra-88f3720_defconfig b/configs/mvebu_espressobin_ultra-88f3720_defconfig index aa9026acc34..6f1a66f5f1d 100644 --- a/configs/mvebu_espressobin_ultra-88f3720_defconfig +++ b/configs/mvebu_espressobin_ultra-88f3720_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_LOAD_ADDR=0x6000000 CONFIG_PCI=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_BOOTSTD_FULL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index 708bf5eefd0..1ca0b45d93f 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -4,22 +4,22 @@ CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_KIRKWOOD=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y CONFIG_SYS_KWD_CONFIG="board/Marvell/openrd/kwbimage.cfg" CONFIG_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_TARGET_OPENRD=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-openrd-base" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_IDENT_STRING="\nOpenRD-Base" -# CONFIG_SYS_MALLOC_F is not set CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=524288 +CONFIG_BOOTSTD_FULL=y CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;" CONFIG_USE_PREBOOT=y CONFIG_LOGLEVEL=2 # CONFIG_DISPLAY_BOARDINFO is not set @@ -30,23 +30,17 @@ CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand_mtd" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)" CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 @@ -59,7 +53,5 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index 82a9c77761c..e0cc2e65db3 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -4,10 +4,12 @@ CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_KIRKWOOD=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y CONFIG_SYS_KWD_CONFIG="board/Marvell/openrd/kwbimage.cfg" CONFIG_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_TARGET_OPENRD=y CONFIG_BOARD_IS_OPENRD_CLIENT=y CONFIG_ENV_SIZE=0x20000 @@ -15,12 +17,10 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-openrd-client" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_IDENT_STRING="\nOpenRD-Client" -# CONFIG_SYS_MALLOC_F is not set CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=524288 +CONFIG_BOOTSTD_FULL=y CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;" CONFIG_USE_PREBOOT=y CONFIG_LOGLEVEL=2 # CONFIG_DISPLAY_BOARDINFO is not set @@ -31,23 +31,17 @@ CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand_mtd" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)" CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 @@ -60,7 +54,5 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index 10b46e2ec18..a115691daad 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -4,10 +4,12 @@ CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_KIRKWOOD=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y CONFIG_SYS_KWD_CONFIG="board/Marvell/openrd/kwbimage.cfg" CONFIG_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_TARGET_OPENRD=y CONFIG_BOARD_IS_OPENRD_ULTIMATE=y CONFIG_ENV_SIZE=0x20000 @@ -15,12 +17,10 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-openrd-ultimate" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_IDENT_STRING="\nOpenRD-Ultimate" -# CONFIG_SYS_MALLOC_F is not set CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=524288 +CONFIG_BOOTSTD_FULL=y CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;" CONFIG_USE_PREBOOT=y CONFIG_LOGLEVEL=2 # CONFIG_DISPLAY_BOARDINFO is not set @@ -31,23 +31,17 @@ CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand_mtd" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)" CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 @@ -60,7 +54,5 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/phycore_am64x_r5_defconfig b/configs/phycore_am64x_r5_defconfig index 6b0fd8d1402..d060a0f1d10 100644 --- a/configs/phycore_am64x_r5_defconfig +++ b/configs/phycore_am64x_r5_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SOC_K3_AM642=y CONFIG_TARGET_PHYCORE_AM64X_R5=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7019b800 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -15,6 +16,7 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-phycore-som-2gb" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y diff --git a/configs/porter_defconfig b/configs/porter_defconfig index 98a67bee3e0..cb18024da12 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -36,7 +36,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k CONFIG_DM_MTD=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_SH_ETHER=y diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig index aae4406bf04..f4f5c57451f 100644 --- a/configs/r8a779a0_falcon_defconfig +++ b/configs/r8a779a0_falcon_defconfig @@ -17,7 +17,6 @@ CONFIG_DEFAULT_FDT_FILE="r8a779a0-falcon.dtb" CONFIG_SYS_PBSIZE=2068 CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_RENESAS_RAVB=y diff --git a/configs/r8a779f0_spider_defconfig b/configs/r8a779f0_spider_defconfig index 7274038a202..6b16ff55480 100644 --- a/configs/r8a779f0_spider_defconfig +++ b/configs/r8a779f0_spider_defconfig @@ -1,32 +1,11 @@ -#include <configs/renesas_rcar4.config> +#include <configs/renesas_rcar4_s4.config> CONFIG_ARM=y CONFIG_ARCH_RENESAS=y CONFIG_RCAR_GEN4=y -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_OFFSET=0xD00000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779f0-spider" CONFIG_TARGET_SPIDER=y -CONFIG_SYS_CLK_FREQ=20000000 -CONFIG_SYS_BOOT_GET_CMDLINE=y -CONFIG_SYS_BARGSIZE=2048 +CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779f0-spider" CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779f0-spider.dtb && booti 0x48080000 - 0x48000000" CONFIG_DEFAULT_FDT_FILE="r8a779f0-spider.dtb" -CONFIG_SYS_CBSIZE=2048 -CONFIG_CMD_PART=y -CONFIG_CMD_UFS=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_LBA48=y -CONFIG_SYS_64BIT_LBA=y -CONFIG_CLK_GPIO=y -CONFIG_DM_PCA953X=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_MARVELL_10G=y -CONFIG_RENESAS_ETHER_SWITCH=y -CONFIG_PHY_R8A779F0_ETHERNET_SERDES=y -CONFIG_SCSI=y CONFIG_BAUDRATE=1843200 -CONFIG_UFS=y -CONFIG_UFS_RENESAS=y -CONFIG_FS_FAT_MAX_CLUSTSIZE=131072 +CONFIG_DM_PCA953X=y diff --git a/configs/r8a779f4_s4sk_defconfig b/configs/r8a779f4_s4sk_defconfig new file mode 100644 index 00000000000..1b353492d04 --- /dev/null +++ b/configs/r8a779f4_s4sk_defconfig @@ -0,0 +1,11 @@ +#include <configs/renesas_rcar4_s4.config> + +CONFIG_ARM=y +CONFIG_ARCH_RENESAS=y +CONFIG_RCAR_GEN4=y +CONFIG_TARGET_S4SK=y +CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779f4-s4sk" +CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779f4-s4sk.dtb && booti 0x48080000 - 0x48000000" +CONFIG_DEFAULT_FDT_FILE="r8a779f4-s4sk.dtb" +CONFIG_BAUDRATE=921600 +CONFIG_BOARD_LATE_INIT=y diff --git a/configs/r8a779g0_whitehawk_defconfig b/configs/r8a779g0_whitehawk_defconfig index c74051d1af9..b49a81dcd49 100644 --- a/configs/r8a779g0_whitehawk_defconfig +++ b/configs/r8a779g0_whitehawk_defconfig @@ -19,7 +19,6 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_MMC_ENV_PART=2 CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_RENESAS_RAVB=y diff --git a/configs/r8a779h0_grayhawk_defconfig b/configs/r8a779h0_grayhawk_defconfig index ef709214f03..5b9ad93a596 100644 --- a/configs/r8a779h0_grayhawk_defconfig +++ b/configs/r8a779h0_grayhawk_defconfig @@ -16,7 +16,6 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_MMC_ENV_PART=2 CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_RENESAS_RAVB=y diff --git a/configs/renesas_rcar3.config b/configs/renesas_rcar3.config index 7f7fab7df1d..9f2413ae928 100644 --- a/configs/renesas_rcar3.config +++ b/configs/renesas_rcar3.config @@ -1,5 +1,4 @@ #include <configs/renesas_rcar64.config> CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_SYS_PBSIZE=2068 diff --git a/configs/renesas_rcar4_s4.config b/configs/renesas_rcar4_s4.config new file mode 100644 index 00000000000..866e5759e63 --- /dev/null +++ b/configs/renesas_rcar4_s4.config @@ -0,0 +1,23 @@ +#include <configs/renesas_rcar4.config> + +CONFIG_CLK_GPIO=y +CONFIG_CMD_PART=y +CONFIG_CMD_UFS=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_OFFSET=0xD00000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_FS_FAT_MAX_CLUSTSIZE=131072 +CONFIG_LBA48=y +CONFIG_PHYLIB_10G=y +CONFIG_PHY_MARVELL_10G=y +CONFIG_PHY_R8A779F0_ETHERNET_SERDES=y +CONFIG_RENESAS_ETHER_SWITCH=y +CONFIG_SCSI=y +CONFIG_SYS_64BIT_LBA=y +CONFIG_SYS_BARGSIZE=2048 +CONFIG_SYS_BOOT_GET_CMDLINE=y +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_CLK_FREQ=20000000 +CONFIG_UFS=y +CONFIG_UFS_RENESAS=y diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig index 46329395ba5..f0315f6ab33 100644 --- a/configs/sandbox_vpl_defconfig +++ b/configs/sandbox_vpl_defconfig @@ -252,6 +252,8 @@ CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_CMD_DHRYSTONE=y +CONFIG_VPL_SHA1_LEGACY=y +CONFIG_VPL_SHA256_LEGACY=y CONFIG_RSA_VERIFY_WITH_PKEY=y CONFIG_TPM=y CONFIG_ZSTD=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 53597e9dd4d..1c70a16bf5b 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -38,7 +38,6 @@ CONFIG_SH_MMCIF=y CONFIG_DM_MTD=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_SH_ETHER=y diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig index 98399416fa5..b0144763d37 100644 --- a/configs/stm32f469-discovery_defconfig +++ b/configs/stm32f469-discovery_defconfig @@ -14,6 +14,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CYCLIC_MAX_CPU_TIME_US=50000 CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_IMLS=y diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig index 1e09c224fc0..5be221afd2f 100644 --- a/configs/stm32f769-disco_defconfig +++ b/configs/stm32f769-disco_defconfig @@ -21,6 +21,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CYCLIC_MAX_CPU_TIME_US=8000 CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig index 787571dba0c..7d4bda44068 100644 --- a/configs/stm32f769-disco_spl_defconfig +++ b/configs/stm32f769-disco_spl_defconfig @@ -30,6 +30,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CYCLIC_MAX_CPU_TIME_US=8000 CONFIG_SPL_PAD_TO=0x9000 CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index 7f705808089..0acd1487c9a 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -52,6 +52,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 CONFIG_ENV_MMC_USE_DT=y +CONFIG_SYS_64BIT_LBA=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y CONFIG_CLK_SCMI=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index dcf44bcc0e7..b0dc944a247 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -98,6 +98,7 @@ CONFIG_TFTP_TSIZE=y CONFIG_USE_SERVERIP=y CONFIG_SERVERIP="192.168.1.1" CONFIG_STM32_ADC=y +CONFIG_SYS_64BIT_LBA=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y CONFIG_SET_DFU_ALT_INFO=y diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index f58a514308b..d31349e3f2b 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -69,6 +69,7 @@ CONFIG_TFTP_TSIZE=y CONFIG_USE_SERVERIP=y CONFIG_SERVERIP="192.168.1.1" CONFIG_STM32_ADC=y +CONFIG_SYS_64BIT_LBA=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y CONFIG_CLK_SCMI=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 2e99b8e6a85..1f807f37c69 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -70,6 +70,7 @@ CONFIG_TFTP_TSIZE=y CONFIG_USE_SERVERIP=y CONFIG_SERVERIP="192.168.1.1" CONFIG_STM32_ADC=y +CONFIG_SYS_64BIT_LBA=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y CONFIG_CLK_SCMI=y diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig index bd25d6a49d2..4538ff0ff7e 100644 --- a/configs/stm32mp25_defconfig +++ b/configs/stm32mp25_defconfig @@ -32,6 +32,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_LOG=y CONFIG_OF_LIVE=y CONFIG_NO_NET=y +CONFIG_SYS_64BIT_LBA=y CONFIG_GPIO_HOG=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y diff --git a/configs/stout_defconfig b/configs/stout_defconfig index a25a5627c2c..59bb7075013 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -36,7 +36,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k CONFIG_DM_MTD=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_SH_ETHER=y diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig index 5e3a46baa41..cecd26175d1 100644 --- a/configs/tools-only_defconfig +++ b/configs/tools-only_defconfig @@ -4,27 +4,27 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="sandbox" CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_PCI=y -# CONFIG_SANDBOX_SDL is not set -# CONFIG_EFI_LOADER is not set +CONFIG_SANDBOX_SDL=n +CONFIG_EFI_LOADER=n CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_TIMESTAMP=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y -# CONFIG_BOOTSTD_FULL is not set -# CONFIG_BOOTMETH_CROS is not set -# CONFIG_BOOTMETH_VBE is not set +CONFIG_BOOTSTD_FULL=n +CONFIG_BOOTMETH_CROS=n +CONFIG_BOOTMETH_VBE=n CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run distro_bootcmd" -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set -# CONFIG_CMD_BOOTI is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_EXTENSION is not set -# CONFIG_CMD_DATE is not set +CONFIG_CMD_BOOTD=n +CONFIG_CMD_BOOTM=n +CONFIG_CMD_BOOTI=n +CONFIG_CMD_ELF=n +CONFIG_CMD_EXTENSION=n +CONFIG_CMD_DATE=n CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y -# CONFIG_ACPIGEN is not set +CONFIG_ACPIGEN=n CONFIG_AXI=y CONFIG_AXI_SANDBOX=y CONFIG_SANDBOX_GPIO=y @@ -33,8 +33,8 @@ CONFIG_DM_RTC=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_TIMER=y -# CONFIG_VIRTIO_MMIO is not set -# CONFIG_VIRTIO_PCI is not set -# CONFIG_VIRTIO_SANDBOX is not set -# CONFIG_GENERATE_ACPI_TABLE is not set +CONFIG_VIRTIO_MMIO=n +CONFIG_VIRTIO_PCI=n +CONFIG_VIRTIO_SANDBOX=n +CONFIG_GENERATE_ACPI_TABLE=n CONFIG_TOOLS_MKEFICAPSULE=y diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig index 9af3817c82f..e1cdc186fb4 100644 --- a/configs/xilinx_versal_mini_ospi_defconfig +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_LEN=0x2000 CONFIG_SYS_MALLOC_F_LEN=0x500 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE0000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFFFE00 CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x80 # CONFIG_DM_GPIO is not set diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 30d79ab8c8c..5ef5fd44fd3 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y @@ -44,10 +46,7 @@ CONFIG_MMC_SPEED_MODE_SET=y CONFIG_CMD_MTD=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y -CONFIG_BOOTP_MAY_FAIL=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_NFS=y +CONFIG_WGET_HTTPS=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y @@ -69,9 +68,7 @@ CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NETCONSOLE=y -CONFIG_IP_DEFRAG=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SIMPLE_PM_BUS=y @@ -102,6 +99,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MT35XU=y CONFIG_SPI_FLASH_SST=y @@ -152,4 +150,5 @@ CONFIG_USB_FUNCTION_THOR=y CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y +CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index fb757c1067d..f228eef7c95 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -38,6 +38,8 @@ CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y @@ -50,10 +52,7 @@ CONFIG_MMC_SPEED_MODE_SET=y CONFIG_CMD_MTD=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y -CONFIG_BOOTP_MAY_FAIL=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_NFS=y +CONFIG_WGET_HTTPS=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y @@ -73,9 +72,7 @@ CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NETCONSOLE=y -CONFIG_IP_DEFRAG=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SIMPLE_PM_BUS=y @@ -112,6 +109,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MT35XU=y CONFIG_SPI_FLASH_SST=y @@ -167,4 +165,6 @@ CONFIG_USB_FUNCTION_THOR=y CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y +CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y +CONFIG_TOOLS_MKFWUMDATA=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index ed3d1019485..fdf8bb36129 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -56,6 +56,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_THOR_RESET_OFF=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DFU=y @@ -71,9 +73,6 @@ CONFIG_CMD_MTD=y CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y -CONFIG_BOOTP_MAY_FAIL=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_NFS=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y @@ -92,8 +91,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SIMPLE_PM_BUS=y @@ -158,4 +156,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +CONFIG_MBEDTLS_LIB=y CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index a68bd522f90..ad46c091c4a 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -63,6 +63,8 @@ CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y @@ -82,11 +84,7 @@ CONFIG_CMD_SDRAM=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_BOOTP_MAY_FAIL=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_NFS=y +CONFIG_WGET_HTTPS=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y @@ -118,8 +116,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_FAT_DEVICE_AND_PART=":auto" CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SIMPLE_PM_BUS=y @@ -129,7 +126,6 @@ CONFIG_SATA_CEVA=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y CONFIG_DFU_MTD=y @@ -138,10 +134,6 @@ CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000 CONFIG_DMA=y CONFIG_XILINX_DPDMA=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ARM_FFA_TRANSPORT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y @@ -229,5 +221,6 @@ CONFIG_VIRTIO_BLK=y # CONFIG_BINMAN_FDT is not set CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-som.dtb" CONFIG_PANIC_HANG=y +CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index b13079cdf70..036268c79f7 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -59,10 +59,10 @@ CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTMENU=y -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_THOR_RESET_OFF=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y @@ -84,11 +84,7 @@ CONFIG_CMD_SDRAM=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_BOOTP_MAY_FAIL=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_NFS=y +CONFIG_WGET_HTTPS=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y @@ -119,8 +115,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_FAT_DEVICE_AND_PART=":auto" CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SIMPLE_PM_BUS=y @@ -130,7 +125,6 @@ CONFIG_SATA_CEVA=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y CONFIG_DFU_MTD=y @@ -138,10 +132,6 @@ CONFIG_DFU_NAND=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000 -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ARM_FFA_TRANSPORT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y @@ -245,5 +235,7 @@ CONFIG_VIRTIO_BLK=y # CONFIG_BINMAN_FDT is not set CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman.dtb" CONFIG_PANIC_HANG=y +CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y CONFIG_SPL_GZIP=y +CONFIG_TOOLS_MKFWUMDATA=y diff --git a/doc/README.bitbangMII b/doc/README.bitbangMII index 0a2fa48a56f..05ab20376f3 100644 --- a/doc/README.bitbangMII +++ b/doc/README.bitbangMII @@ -7,28 +7,11 @@ The driver requires that the following macros should be defined into the board configuration file: CONFIG_BITBANGMII - Enable the miiphybb driver -CONFIG_BITBANGMII_MULTI - Enable the multi bus support -If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs -to define at least the following macros: - -MII_INIT - Generic code to enable the MII bus (optional) -MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional) -MDIO_ACTIVE - Activate the MDIO pin as out pin -MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin -MDIO_READ - Read the MDIO pin -MDIO(v) - Write v on the MDIO pin -MDC_DECLARE - Declaration needed to access to the MDC pin (optional) -MDC(v) - Write v on the MDC pin - -The previous macros make the driver compatible with the previous version -(that didn't support the multi-bus). - -When the CONFIG_BITBANGMII_MULTI is also defined, the board code needs to fill -the bb_miiphy_buses[] array with a record for each required bus and declare -the bb_miiphy_buses_num variable with the number of mii buses. -The record (struct bb_miiphy_bus) has the following fields/callbacks (see -miiphy.h for details): +The board code needs to fill the bb_miiphy_buses[] array with a record for +each required bus and declare the bb_miiphy_buses_num variable with the +number of mii buses. The record (struct bb_miiphy_bus) has the following +fields/callbacks (see miiphy.h for details): char name[] - The symbolic name that must be equal to the MII bus registered name diff --git a/doc/board/renesas/renesas.rst b/doc/board/renesas/renesas.rst index 7d961e862e4..0a38ff42eae 100644 --- a/doc/board/renesas/renesas.rst +++ b/doc/board/renesas/renesas.rst @@ -169,6 +169,12 @@ Renesas is a SoC solutions provider for automotive and industrial applications. - r8a779f0_spider_defconfig * - + - S4SK + - R8A779F4 (S4) + - arm64 + - r8a779f4_s4sk_defconfig + + * - - White Hawk - R8A779G0 (V4H) - arm64 diff --git a/doc/develop/py_testing.rst b/doc/develop/py_testing.rst index 6ff78103409..b50473039be 100644 --- a/doc/develop/py_testing.rst +++ b/doc/develop/py_testing.rst @@ -246,6 +246,39 @@ Command-line options sets the directory used to store persistent test data. This is test data that may be re-used across test runs, such as file-system images. +--timing + shows a histogram of test duration, at the end of the run. The columns are: + + Duration + the duration-bucket that this test was in + + Total + total time of all tests in this bucket + + Number of tests + graph showing the number of tests in this bucket, with the actual number + shown at the end + + Example:: + + Duration : Total | Number of tests + ======== : ======= |======================================== + <20ms : 418ms |## 23 + <30ms : 9.1s |######################################## 347 + <40ms : 10.0s |################################# 294 + <50ms : 3.1s |####### 69 + <75ms : 2.6s |#### 43 + <100ms : 1.7s |## 19 + <200ms : 3.0s |## 22 + <300ms : 1.7s | 7 + <400ms : 675ms | 2 + <500ms : 2.2s | 5 + <750ms : 8.3s |# 13 + <1.0s : 1.6s | 2 + <2.0s : 9.4s | 7 + <3.0s : 2.4s | 1 + <7.5s : 6.1s | 1 + `pytest` also implements a number of its own command-line options. Commonly used options are mentioned below. Please see `pytest` documentation for complete details. Execute `py.test --version` for a brief summary. Note that U-Boot's diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 9ecd6b6ab87..03deea2af1a 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -55,7 +55,7 @@ Current Status * The Merge Window for the next release (v2025.04) is **closed**. -* The next branch is now **closed** until the -rc2 release on Mon 10 February +* The next branch is now **open** with the -rc2 release on Mon 10 February 2025. * Release "v2025.04" is scheduled for 07 April 2025. @@ -70,7 +70,7 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2025.04-rc1 was released on Mon 27 January 2025. -.. * U-Boot v2025.04-rc2 was released on Mon 10 February 2025. +* U-Boot v2025.04-rc2 was released on Mon 10 February 2025. .. * U-Boot v2025.04-rc3 was released on Mon 24 February 2025. diff --git a/doc/device-tree-bindings/leds/common.txt b/doc/device-tree-bindings/leds/common.txt deleted file mode 100644 index 2d88816dd55..00000000000 --- a/doc/device-tree-bindings/leds/common.txt +++ /dev/null @@ -1,23 +0,0 @@ -Common leds properties. - -Optional properties for child nodes: -- label : The label for this LED. If omitted, the label is - taken from the node name (excluding the unit address). - -- linux,default-trigger : This parameter, if present, is a - string defining the trigger assigned to the LED. Current triggers are: - "backlight" - LED will act as a back-light, controlled by the framebuffer - system - "default-on" - LED will turn on (but for leds-gpio see "default-state" - property in Documentation/devicetree/bindings/gpio/led.txt) - "heartbeat" - LED "double" flashes at a load average based rate - "ide-disk" - LED indicates disk activity - "timer" - LED flashes at a fixed, configurable rate - -Examples: - -system-status { - label = "Status"; - linux,default-trigger = "heartbeat"; - ... -}; diff --git a/doc/usage/measured_boot.rst b/doc/usage/measured_boot.rst index 05c439e9ac6..488dd546f13 100644 --- a/doc/usage/measured_boot.rst +++ b/doc/usage/measured_boot.rst @@ -24,7 +24,6 @@ Requirements * A hardware TPM 2.0 supported by an enabled U-Boot driver * CONFIG_EFI_TCG2_PROTOCOL=y -* CONFIG_EFI_TCG2_PROTOCOL_EVENTLOG_SIZE=y * optional CONFIG_EFI_TCG2_PROTOCOL_MEASURE_DTB=y will measure the loaded DTB in PCR 1 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e631f79e4dd..e412c92cafc 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o +obj-$(CONFIG_TARGET_MT7987) += clk-mt7987.o obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c new file mode 100644 index 00000000000..173686a38e8 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7987.c @@ -0,0 +1,848 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek clock driver for MT7987 SoC + * + * Copyright (C) 2024 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <dm.h> +#include <log.h> +#include <asm/arch-mediatek/reset.h> +#include <asm/io.h> +#include <dt-bindings/clock/mediatek,mt7987-clk.h> +#include <linux/bitops.h> + +#include "clk-mtk.h" + +#define MT7987_XTAL_RATE (40 * MHZ) +#define MT7987_CLK_PDN 0x250 +#define MT7987_CLK_PDN_EN_WRITE BIT(31) + +#define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) + +#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) + +#define TOP_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) + +#define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS) + +/* FIXED PLLS */ +static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = { + FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000), + FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000), + FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), + FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000), + FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), + FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000), + FIXED_CLK(CLK_APMIXED_ARM_LL, CLK_XTAL, 2000000000), + FIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 384000000), +}; + +static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = { + .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls), + .fclks = apmixedsys_mtk_plls, + .flags = CLK_APMIXED, + .xtal_rate = 40 * MHZ, +}; + +static const struct udevice_id mt7987_fixed_pll_compat[] = { + { .compatible = "mediatek,mt7987-fixed-plls" }, + { .compatible = "mediatek,mt7987-apmixedsys" }, + {} +}; + +static int mt7987_fixed_pll_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt7987_fixed_pll_clk_tree); +} + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt7987-clock-fixed-pll", + .id = UCLASS_CLK, + .of_match = mt7987_fixed_pll_compat, + .probe = mt7987_fixed_pll_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* TOPCKGEN FIXED DIV */ +static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = { + PLL_FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", CLK_APMIXED_MPLL, 1, 2), + PLL_FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", CLK_APMIXED_MPLL, 1, 3), + PLL_FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", CLK_APMIXED_MPLL, 1, 6), + PLL_FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", CLK_APMIXED_MPLL, 1, 4), + PLL_FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", CLK_APMIXED_MPLL, 1, 8), + PLL_FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", CLK_APMIXED_MPLL, 1, 16), + PLL_FACTOR(CLK_TOP_CB_APLL2_D4, "cb_apll2_d4", CLK_APMIXED_APLL2, 1, 4), + PLL_FACTOR(CLK_TOP_CB_NET1_D3, "cb_net1_d3", CLK_APMIXED_NET1PLL, 1, 3), + PLL_FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", CLK_APMIXED_NET1PLL, 1, 4), + PLL_FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", CLK_APMIXED_NET1PLL, 1, 5), + PLL_FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", CLK_APMIXED_NET1PLL, 1, 10), + PLL_FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", CLK_APMIXED_NET1PLL, 1, 20), + PLL_FACTOR(CLK_TOP_CB_NET1_D7, "cb_net1_d7", CLK_APMIXED_NET1PLL, 1, 7), + PLL_FACTOR(CLK_TOP_NET1_D7_D2, "net1_d7_d2", CLK_APMIXED_NET1PLL, 1, 14), + PLL_FACTOR(CLK_TOP_NET1_D7_D4, "net1_d7_d4", CLK_APMIXED_NET1PLL, 1, 28), + PLL_FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", CLK_APMIXED_NET1PLL, 1, 16), + PLL_FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", CLK_APMIXED_NET1PLL, 1, 32), + PLL_FACTOR(CLK_TOP_NET1_D8_D8, "net1_d8_d8", CLK_APMIXED_NET1PLL, 1, 64), + PLL_FACTOR(CLK_TOP_NET1_D8_D16, "net1_d8_d16", CLK_APMIXED_NET1PLL, 1, 128), + PLL_FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", CLK_APMIXED_NET2PLL, 1, 2), + PLL_FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", CLK_APMIXED_NET2PLL, 1, 4), + PLL_FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", CLK_APMIXED_NET2PLL, 1, 16), + PLL_FACTOR(CLK_TOP_NET2_D4_D8, "net2_d4_d8", CLK_APMIXED_NET2PLL, 1, 32), + PLL_FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", CLK_APMIXED_NET2PLL, 1, 6), + PLL_FACTOR(CLK_TOP_NET2_D7_D2, "net2_d7_d2", CLK_APMIXED_NET2PLL, 1, 14), + PLL_FACTOR(CLK_TOP_CB_NET2_D8, "cb_net2_d8", CLK_APMIXED_NET2PLL, 1, 8), + PLL_FACTOR(CLK_TOP_MSDC_D2, "msdc_d2", CLK_APMIXED_MSDCPLL, 1, 2), + XTAL_FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1), + TOP_FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CLK_TOP_CB_CKSQ_40M, 1, 2), + TOP_FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", CLK_TOP_CB_CKSQ_40M, 1, 1250), + TOP_FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CLK_TOP_CB_CKSQ_40M, 1, 1221), +}; + +/* TOPCKGEN MUX PARENTS */ +#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) +#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) + +/* CLK_TOP_NETSYS_SEL (netsys_sel) in topckgen */ +static const struct mtk_parent netsys_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D2) +}; + +/* CLK_TOP_NETSYS_500M_SEL (netsys_500m_sel) in topckgen */ +static const struct mtk_parent netsys_500m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET1_D5), + TOP_PARENT(CLK_TOP_NET1_D5_D2) +}; + +/* CLK_TOP_NETSYS_2X_SEL (netsys_2x_sel) in topckgen */ +static const struct mtk_parent netsys_2x_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + APMIXED_PARENT(CLK_APMIXED_NET2PLL) +}; + +/* CLK_TOP_ETH_GMII_SEL (eth_gmii_sel) in topckgen */ +static const struct mtk_parent eth_gmii_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4) +}; + +/* CLK_TOP_EIP_SEL (eip_sel) in topckgen */ +static const struct mtk_parent eip_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET1_D3), + APMIXED_PARENT(CLK_APMIXED_NET2PLL), + TOP_PARENT(CLK_TOP_CB_NET1_D4), + TOP_PARENT(CLK_TOP_CB_NET1_D5) +}; + +/* CLK_TOP_AXI_INFRA_SEL (axi_infra_sel) in topckgen */ +static const struct mtk_parent axi_infra_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D2) +}; + +/* CLK_TOP_UART_SEL (uart_sel) in topckgen */ +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D8), + TOP_PARENT(CLK_TOP_M_D8_D2) +}; + +/* CLK_TOP_EMMC_250M_SEL (emmc_250m_sel) in topckgen */ +static const struct mtk_parent emmc_250m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D2), + TOP_PARENT(CLK_TOP_NET1_D7_D2) +}; + +/* CLK_TOP_EMMC_400M_SEL (emmc_400m_sel) in topckgen */ +static const struct mtk_parent emmc_400m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_CB_NET1_D7), + TOP_PARENT(CLK_TOP_CB_M_D2), + TOP_PARENT(CLK_TOP_NET1_D7_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D6) +}; + +/* CLK_TOP_SPI_SEL (spi_sel) in topckgen */ +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D2), + TOP_PARENT(CLK_TOP_NET1_D7_D2), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D6), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D4) +}; + +/* CLK_TOP_NFI_SEL (nfi_sel) in topckgen */ +static const struct mtk_parent nfi_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_CB_M_D3), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_NET1_D7_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D4), + TOP_PARENT(CLK_TOP_M_D3_D2), + TOP_PARENT(CLK_TOP_NET2_D7_D2), + TOP_PARENT(CLK_TOP_CB_M_D8) +}; + +/* CLK_TOP_PWM_SEL (pwm_sel) in topckgen */ +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_M_D8_D2), + TOP_PARENT(CLK_TOP_CB_RTC_32K) +}; + +/* CLK_TOP_I2C_SEL (i2c_sel) in topckgen */ +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D4) +}; + +/* CLK_TOP_PCIE_MBIST_250M_SEL (pcie_mbist_250m_sel) in topckgen */ +static const struct mtk_parent pcie_mbist_250m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D2) +}; + +/* CLK_TOP_PEXTP_TL_SEL (pextp_tl_ck_sel) in topckgen */ +static const struct mtk_parent pextp_tl_ck_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D6), + TOP_PARENT(CLK_TOP_NET1_D7_D4), + TOP_PARENT(CLK_TOP_M_D8_D2), + TOP_PARENT(CLK_TOP_CB_RTC_32K) +}; + +/* CLK_TOP_AUD_SEL (aud_sel) in topckgen */ +static const struct mtk_parent aud_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + APMIXED_PARENT(CLK_APMIXED_APLL2) +}; + +/* CLK_TOP_A1SYS_SEL (a1sys_sel) in topckgen */ +static const struct mtk_parent a1sys_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_APLL2_D4) +}; + +/* CLK_TOP_AUD_L_SEL (aud_l_sel) in topckgen */ +static const struct mtk_parent aud_l_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + APMIXED_PARENT(CLK_APMIXED_APLL2), + TOP_PARENT(CLK_TOP_M_D8_D2) +}; + +/* CLK_TOP_USB_PHY_SEL (usb_phy_sel) in topckgen */ +static const struct mtk_parent usb_phy_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_M_D8_D2) +}; + +/* CLK_TOP_SGM_0_SEL (sgm_0_sel) in topckgen */ +static const struct mtk_parent sgm_0_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + APMIXED_PARENT(CLK_APMIXED_SGMPLL) +}; + +/* CLK_TOP_SGM_SBUS_0_SEL (sgm_sbus_0_sel) in topckgen */ +static const struct mtk_parent sgm_sbus_0_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D4) +}; + +/* CLK_TOP_SYSAPB_SEL (sysapb_sel) in topckgen */ +static const struct mtk_parent sysapb_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_M_D3_D2) +}; + +/* CLK_TOP_ETH_REFCK_50M_SEL (eth_refck_50m_sel) in topckgen */ +static const struct mtk_parent eth_refck_50m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET2_D4_D4) +}; + +/* CLK_TOP_ETH_SYS_200M_SEL (eth_sys_200m_sel) in topckgen */ +static const struct mtk_parent eth_sys_200m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D4) +}; + +/* CLK_TOP_ETH_XGMII_SEL (eth_xgmii_sel) in topckgen */ +static const struct mtk_parent eth_xgmii_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_NET1_D8_D8), + TOP_PARENT(CLK_TOP_NET1_D8_D16) +}; + +/* CLK_TOP_DRAMC_MD32_SEL (dramc_md32_sel) in topckgen */ +static const struct mtk_parent dramc_md32_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D2), + APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL) +}; + +/* CLK_TOP_DA_XTP_GLB_P0_SEL (da_xtp_glb_p0_sel) in topckgen */ +static const struct mtk_parent da_xtp_glb_p0_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D8) +}; + +/* CLK_TOP_DA_CKM_XTAL_SEL (da_ckm_xtal_sel) in topckgen */ +static const struct mtk_parent da_ckm_xtal_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_M_D8_D2) +}; + +/* CLK_TOP_ETH_MII_SEL (eth_mii_sel) in topckgen */ +static const struct mtk_parent eth_mii_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_NET2_D4_D8) +}; + +/* CLK_TOP_EMMC_200M_SEL (emmc_200m_sel) in topckgen */ +static const struct mtk_parent emmc_200m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_MSDC_D2), + TOP_PARENT(CLK_TOP_NET1_D7_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D6), + TOP_PARENT(CLK_TOP_NET1_D7_D4) +}; + +#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _shift, _width, _gate, _upd_ofs, _upd) \ + { \ + .id = (_id), .mux_reg = (_mux_ofs), \ + .mux_set_reg = (_mux_set_ofs), .mux_clr_reg = (_mux_clr_ofs), \ + .upd_reg = (_upd_ofs), .upd_shift = (_upd), \ + .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \ + .gate_reg = (_mux_ofs), .gate_shift = (_gate), \ + .parent_flags = (_parents), \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + } + +/* TOPCKGEN MUX_GATE */ +static const struct mtk_composite topckgen_mtk_muxes[] = { + TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, + 0x000, 0x004, 0x008, 0, 1, 7, 0x1C0, 0), + TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", + netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2, 15, 0x1C0, 1), + TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, + 0x000, 0x004, 0x008, 16, 1, 23, 0x1C0, 2), + TOP_MUX(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, + 0x000, 0x004, 0x008, 24, 1, 31, 0x1C0, 3), + TOP_MUX(CLK_TOP_EIP_SEL, "eip_sel", eip_parents, + 0x010, 0x014, 0x018, 0, 3, 7, 0x1C0, 4), + TOP_MUX(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, + 0x010, 0x014, 0x018, 8, 1, 15, 0x1C0, 5), + TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, + 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6), + TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, + 0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7), + TOP_MUX(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, + 0x020, 0x024, 0x028, 0, 3, 7, 0x1C0, 8), + TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, + 0x020, 0x024, 0x028, 8, 3, 15, 0x1C0, 9), + TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, + 0x020, 0x024, 0x028, 16, 3, 23, 0x1C0, 10), + TOP_MUX(CLK_TOP_NFI_SEL, "nfi_sel", nfi_parents, + 0x020, 0x024, 0x028, 24, 4, 31, 0x1C0, 11), + TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, + 0x030, 0x034, 0x038, 0, 3, 7, 0x1C0, 12), + TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, + 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), + TOP_MUX(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel", + pcie_mbist_250m_parents, 0x030, 0x034, 0x038, 16, 1, 23, 0x1C0, 14), + TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, + 0x030, 0x034, 0x038, 24, 3, 31, 0x1C0, 15), + TOP_MUX(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel", + pextp_tl_ck_parents, 0x040, 0x044, 0x048, 0, 3, 7, 0x1C0, 16), + TOP_MUX(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, + 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), + TOP_MUX(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, + 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), + TOP_MUX(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, + 0x040, 0x044, 0x048, 24, 1, 31, 0x1C0, 19), + TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, + 0x050, 0x054, 0x058, 0, 1, 7, 0x1C0, 20), + TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, + 0x050, 0x054, 0x058, 8, 2, 15, 0x1C0, 21), + TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, + 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), + TOP_MUX(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", usb_phy_parents, + 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), + TOP_MUX(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, + 0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24), + TOP_MUX(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", sgm_sbus_0_parents, + 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25), + TOP_MUX(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, + 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), + TOP_MUX(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", sgm_sbus_0_parents, + 0x060, 0x064, 0x068, 24, 1, 31, 0x1C0, 27), + TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, + 0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28), + TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, + 0x070, 0x074, 0x078, 8, 1, 15, 0x1C0, 29), + TOP_MUX(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", + eth_refck_50m_parents, 0x070, 0x074, 0x078, 16, 1, 23, 0x1C0, 30), + TOP_MUX(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", + eth_sys_200m_parents, 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0), + TOP_MUX(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, + 0x080, 0x084, 0x088, 0, 1, 7, 0x1C4, 1), + TOP_MUX(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, + 0x080, 0x084, 0x088, 8, 2, 15, 0x1C4, 2), + TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", usb_phy_parents, + 0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3), + TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, + 0x080, 0x084, 0x088, 24, 2, 31, 0x1C4, 4), + TOP_MUX(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", + usb_phy_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5), + TOP_MUX(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", usb_phy_parents, + 0x090, 0x094, 0x098, 8, 1, 15, 0x1C4, 6), + TOP_MUX(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", usb_phy_parents, + 0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7), + TOP_MUX(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", + da_xtp_glb_p0_parents, 0x090, 0x094, 0x098, 24, 1, 31, 0x1C4, 8), + TOP_MUX(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", + da_xtp_glb_p0_parents, 0x0A0, 0x0A4, 0x0A8, 0, 1, 7, 0x1C4, 9), + TOP_MUX(CLK_TOP_CKM_SEL, "ckm_sel", usb_phy_parents, + 0x0A0, 0x0A4, 0x0A8, 8, 1, 15, 0x1C4, 10), + TOP_MUX(CLK_TOP_DA_CKM_XTAL_SEL, "da_ckm_xtal_sel", + da_ckm_xtal_parents, 0x0A0, 0x0A4, 0x0A8, 16, 1, 23, 0x1C4, 11), + TOP_MUX(CLK_TOP_PEXTP_SEL, "pextp_sel", usb_phy_parents, + 0x0A0, 0x0A4, 0x0A8, 24, 1, 31, 0x1C4, 12), + TOP_MUX(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, + 0x0B0, 0x0B4, 0x0B8, 0, 1, 7, 0x1C4, 13), + TOP_MUX(CLK_TOP_EMMC_200M_SEL, "emmc_200m_sel", emmc_200m_parents, + 0x0B0, 0x0B4, 0x0B8, 8, 3, 15, 0x1C4, 14), +}; + +static const struct mtk_clk_tree mt7987_topckgen_clk_tree = { + .muxes_offs = CLK_TOP_NETSYS_SEL, + .fdivs = topckgen_mtk_fixed_factors, + .muxes = topckgen_mtk_muxes, + .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN, + .xtal_rate = MT7987_XTAL_RATE, +}; + +static const struct udevice_id mt7987_topckgen_compat[] = { + { .compatible = "mediatek,mt7987-topckgen" }, + {} +}; + +static int mt7987_topckgen_probe(struct udevice *dev) +{ + struct mtk_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOENT; + + writel(MT7987_CLK_PDN_EN_WRITE, priv->base + MT7987_CLK_PDN); + return mtk_common_clk_init(dev, &mt7987_topckgen_clk_tree); +} + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt7987-clock-topckgen", + .id = UCLASS_CLK, + .of_match = mt7987_topckgen_compat, + .probe = mt7987_topckgen_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* INFRASYS MUX PARENTS */ + +/* CLK_INFRA_MUX_UART0_SEL (infra_mux_uart0_sel) in infracfg */ +static const int infra_mux_uart0_parents[] = { + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_UART_SEL +}; + +/* CLK_INFRA_MUX_UART1_SEL (infra_mux_uart1_sel) in infracfg */ +static const int infra_mux_uart1_parents[] = { + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_UART_SEL +}; + +/* CLK_INFRA_MUX_UART2_SEL (infra_mux_uart2_sel) in infracfg */ +static const int infra_mux_uart2_parents[] = { + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_UART_SEL +}; + +/* CLK_INFRA_MUX_SPI0_SEL (infra_mux_spi0_sel) in infracfg */ +static const int infra_mux_spi0_parents[] = { + CLK_TOP_I2C_SEL, + CLK_TOP_SPI_SEL +}; + +/* CLK_INFRA_MUX_SPI1_SEL (infra_mux_spi1_sel) in infracfg */ +static const int infra_mux_spi1_parents[] = { + CLK_TOP_I2C_SEL, + CLK_TOP_SPIM_MST_SEL +}; + +/* CLK_INFRA_MUX_SPI2_BCK_SEL (infra_mux_spi2_bck_sel) in infracfg */ +static const int infra_mux_spi2_bck_parents[] = { + CLK_TOP_I2C_SEL, + CLK_TOP_SPI_SEL +}; + +/* CLK_INFRA_PWM_BCK_SEL (infra_pwm_bck_sel) in infracfg */ +static const int infra_pwm_bck_parents[] = { + CLK_TOP_CB_RTC_32P7K, + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_SYSAXI_SEL, + CLK_TOP_PWM_SEL +}; + +/* CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL (infra_pcie_gfmux_tl_ck_o_p0_sel) in infracfg */ +static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = { + CLK_TOP_CB_RTC_32P7K, + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_PEXTP_TL_SEL +}; + +/* CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL (infra_pcie_gfmux_tl_ck_o_p1_sel) in infracfg */ +static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { + CLK_TOP_CB_RTC_32P7K, + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_PEXTP_TL_P1_SEL +}; + +#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ + { \ + .id = (_id), .mux_reg = (_reg) + 0x8, \ + .mux_clr_reg = (_reg) + 0x4, .mux_set_reg = (_reg) + 0x0, \ + .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \ + .gate_shift = -1, .upd_shift = -1, \ + .parent = (_parents), .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ + } + +/* INFRA MUX */ +static const struct mtk_composite infracfg_mtk_mux[] = { + INFRA_MUX(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", + infra_mux_uart0_parents, 0x0010, 0, 1), + INFRA_MUX(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", + infra_mux_uart1_parents, 0x0010, 1, 1), + INFRA_MUX(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", + infra_mux_uart2_parents, 0x0010, 2, 1), + INFRA_MUX(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", + infra_mux_spi0_parents, 0x0010, 4, 1), + INFRA_MUX(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", + infra_mux_spi1_parents, 0x0010, 5, 1), + INFRA_MUX(CLK_INFRA_MUX_SPI2_BCK_SEL, "infra_mux_spi2_bck_sel", + infra_mux_spi2_bck_parents, 0x0010, 6, 1), + INFRA_MUX(CLK_INFRA_PWM_BCK_SEL, "infra_pwm_bck_sel", + infra_pwm_bck_parents, 0x0010, 14, 2), + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_ck_o_p0_sel", + infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0020, 0, 2), + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_ck_o_p1_sel", + infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0020, 2, 2), +}; + +static const struct mtk_gate_regs infra_0_cg_regs = { + .set_ofs = 0x10, + .clr_ofs = 0x14, + .sta_ofs = 0x18, +}; + +static const struct mtk_gate_regs infra_1_cg_regs = { + .set_ofs = 0x40, + .clr_ofs = 0x44, + .sta_ofs = 0x48, +}; + +static const struct mtk_gate_regs infra_2_cg_regs = { + .set_ofs = 0x50, + .clr_ofs = 0x54, + .sta_ofs = 0x58, +}; + +static const struct mtk_gate_regs infra_3_cg_regs = { + .set_ofs = 0x60, + .clr_ofs = 0x64, + .sta_ofs = 0x68, +}; + +#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \ + { \ + .id = (_id), .parent = (_parent), .regs = &infra_0_cg_regs, \ + .shift = (_shift), \ + .flags = (_flags), \ + } +#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \ + { \ + .id = (_id), .parent = (_parent), .regs = &infra_1_cg_regs, \ + .shift = (_shift), \ + .flags = (_flags), \ + } +#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \ + { \ + .id = (_id), .parent = (_parent), .regs = &infra_2_cg_regs, \ + .shift = (_shift), \ + .flags = (_flags), \ + } +#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_INFRA3(_id, _name, _parent, _shift, _flags) \ + { \ + .id = (_id), .parent = (_parent), .regs = &infra_3_cg_regs, \ + .shift = (_shift), \ + .flags = (_flags), \ + } +#define GATE_INFRA3_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) +#define GATE_INFRA3_XTAL(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) + +/* INFRA GATE */ +static const struct mtk_gate infracfg_mtk_gates[] = { + GATE_INFRA1_TOP(CLK_INFRA_66M_GPT_BCK, + "infra_hf_66m_gpt_bck", CLK_TOP_SYSAXI_SEL, 0), + GATE_INFRA1_TOP(CLK_INFRA_66M_PWM_HCK, + "infra_hf_66m_pwm_hck", CLK_TOP_SYSAXI_SEL, 1), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_BCK, + "infra_hf_66m_pwm_bck", CLK_INFRA_PWM_BCK_SEL, 2), + GATE_INFRA1_TOP(CLK_INFRA_133M_CQDMA_BCK, + "infra_hf_133m_cqdma_bck", CLK_TOP_SYSAXI_SEL, 12), + GATE_INFRA1_TOP(CLK_INFRA_66M_AUD_SLV_BCK, + "infra_66m_aud_slv_bck", CLK_TOP_SYSAXI_SEL, 13), + GATE_INFRA1_TOP(CLK_INFRA_AUD_26M, "infra_f_faud_26m", + CLK_TOP_INFRA_F26M_SEL, 14), + GATE_INFRA1_TOP(CLK_INFRA_AUD_L, "infra_f_faud_l", CLK_TOP_AUD_L_SEL, 15), + GATE_INFRA1_TOP(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", CLK_TOP_A1SYS_SEL, 16), + GATE_INFRA1_TOP(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", + CLK_TOP_A_TUNER_SEL, 18), + GATE_INFRA1_TOP(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", + CLK_TOP_INFRA_F26M_SEL, 19), + GATE_INFRA1_TOP(CLK_INFRA_133M_DBG_ACKM, + "infra_hf_133m_dbg_ackm", CLK_TOP_SYSAXI_SEL, 20), + GATE_INFRA1_TOP(CLK_INFRA_66M_AP_DMA_BCK, + "infra_66m_ap_dma_bck", CLK_TOP_SYSAXI_SEL, 21), + GATE_INFRA1_TOP(CLK_INFRA_MSDC200_SRC, "infra_f_fmsdc200_src", + CLK_TOP_EMMC_200M_SEL, 28), + GATE_INFRA1_TOP(CLK_INFRA_66M_SEJ_BCK, + "infra_hf_66m_sej_bck", CLK_TOP_SYSAXI_SEL, 29), + GATE_INFRA1_TOP(CLK_INFRA_PRE_CK_SEJ_F13M, + "infra_pre_ck_sej_f13m", CLK_TOP_INFRA_F26M_SEL, 30), + GATE_INFRA1_TOP(CLK_INFRA_66M_TRNG, "infra_hf_66m_trng", + CLK_TOP_SYSAXI_SEL, 31), + GATE_INFRA2_TOP(CLK_INFRA_26M_THERM_SYSTEM, + "infra_hf_26m_therm_system", CLK_TOP_INFRA_F26M_SEL, 0), + GATE_INFRA2_TOP(CLK_INFRA_I2C_BCK, "infra_i2c_bck", CLK_TOP_I2C_SEL, 1), + GATE_INFRA2_TOP(CLK_INFRA_66M_UART0_PCK, + "infra_hf_66m_uart0_pck", CLK_TOP_SYSAXI_SEL, 3), + GATE_INFRA2_TOP(CLK_INFRA_66M_UART1_PCK, + "infra_hf_66m_uart1_pck", CLK_TOP_SYSAXI_SEL, 4), + GATE_INFRA2_TOP(CLK_INFRA_66M_UART2_PCK, + "infra_hf_66m_uart2_pck", CLK_TOP_SYSAXI_SEL, 5), + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART0_CK, + "infra_f_52m_uart0", CLK_INFRA_MUX_UART0_SEL, 3), + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART1_CK, + "infra_f_52m_uart1", CLK_INFRA_MUX_UART1_SEL, 4), + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART2_CK, + "infra_f_52m_uart2", CLK_INFRA_MUX_UART2_SEL, 5), + GATE_INFRA2_TOP(CLK_INFRA_NFI, "infra_f_fnfi", CLK_TOP_NFI_SEL, 9), + GATE_INFRA2_TOP(CLK_INFRA_66M_NFI_HCK, + "infra_hf_66m_nfi_hck", CLK_TOP_SYSAXI_SEL, 11), + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", + CLK_INFRA_MUX_SPI0_SEL, 12), + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", + CLK_INFRA_MUX_SPI1_SEL, 13), + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI2_BCK, + "infra_hf_104m_spi2_bck", CLK_INFRA_MUX_SPI2_BCK_SEL, 14), + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI0_HCK, + "infra_hf_66m_spi0_hck", CLK_TOP_SYSAXI_SEL, 15), + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI1_HCK, + "infra_hf_66m_spi1_hck", CLK_TOP_SYSAXI_SEL, 16), + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI2_HCK, + "infra_hf_66m_spi2_hck", CLK_TOP_SYSAXI_SEL, 17), + GATE_INFRA2_TOP(CLK_INFRA_66M_FLASHIF_AXI, + "infra_hf_66m_flashif_axi", CLK_TOP_SYSAXI_SEL, 18), + GATE_INFRA2_TOP(CLK_INFRA_RTC, "infra_f_frtc", CLK_TOP_CB_RTC_32K, 19), + GATE_INFRA2_TOP(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", + CLK_TOP_INFRA_F26M_SEL, 20), + GATE_INFRA2_INFRA(CLK_INFRA_RC_ADC, "infra_f_frc_adc", + CLK_INFRA_26M_ADC_BCK, 21), + GATE_INFRA2_TOP(CLK_INFRA_MSDC400, "infra_f_fmsdc400", + CLK_TOP_EMMC_400M_SEL, 22), + GATE_INFRA2_TOP(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", + CLK_TOP_EMMC_250M_SEL, 23), + GATE_INFRA2_TOP(CLK_INFRA_133M_MSDC_0_HCK, + "infra_hf_133m_msdc_0_hck", CLK_TOP_SYSAXI_SEL, 24), + GATE_INFRA2_TOP(CLK_INFRA_66M_MSDC_0_HCK, + "infra_66m_msdc_0_hck", CLK_TOP_SYSAXI_SEL, 25), + GATE_INFRA2_TOP(CLK_INFRA_133M_CPUM_BCK, + "infra_hf_133m_cpum_bck", CLK_TOP_SYSAXI_SEL, 26), + GATE_INFRA2_TOP(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", + CLK_TOP_NFI_SEL, 27), + GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_MCK_CK_P1, + "infra_hf_i2c_x16w_mck_ck_p1", CLK_TOP_SYSAXI_SEL, 29), + GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_PCK_CK_P1, + "infra_hf_i2c_x16w_pck_ck_p1", CLK_TOP_SYSAXI_SEL, 31), + GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK, + "infra_133m_usb_hck", CLK_TOP_SYSAXI_SEL, 0), + GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK_CK_P1, + "infra_133m_usb_hck_ck_p1", CLK_TOP_SYSAXI_SEL, 1), + GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", + CLK_TOP_SYSAXI_SEL, 2), + GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK_CK_P1, + "infra_66m_usb_hck_ck_p1", CLK_TOP_SYSAXI_SEL, 3), + GATE_INFRA3_TOP(CLK_INFRA_USB_SYS_CK_P1, + "infra_usb_sys_ck_p1", CLK_TOP_USB_SYS_P1_SEL, 5), + GATE_INFRA3_TOP(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", + CLK_TOP_CB_CKSQ_40M, 7), + GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1, + "infra_usb_frmcnt_ck_p1", CLK_TOP_CKSQ_40M_D2, 9), + GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1, + "infra_usb_pipe_ck_p1", CLK_XTAL, 11), + GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1, + "infra_usb_utmi_ck_p1", CLK_XTAL, 13), + GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1, + "infra_usb_xhci_ck_p1", CLK_TOP_USB_XHCI_P1_SEL, 15), + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P0, + "infra_pcie_gfmux_tl_ck_p0", CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20), + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P1, + "infra_pcie_gfmux_tl_ck_p1", CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21), + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0, + "infra_pcie_pipe_ck_p0", CLK_XTAL, 24), + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1, + "infra_pcie_pipe_ck_p1", CLK_XTAL, 25), + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0, + "infra_133m_pcie_ck_p0", CLK_TOP_SYSAXI_SEL, 28), + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1, + "infra_133m_pcie_ck_p1", CLK_TOP_SYSAXI_SEL, 29), + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P0, + "infra_pcie_peri_ck_26m_ck_p0", CLK_TOP_INFRA_F26M_SEL, 7), + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P1, + "infra_pcie_peri_ck_26m_ck_p1", CLK_TOP_INFRA_F26M_SEL, 8), +}; + +static const struct mtk_clk_tree mt7987_infracfg_clk_tree = { + .muxes_offs = CLK_INFRA_MUX_UART0_SEL, + .gates_offs = CLK_INFRA_66M_GPT_BCK, + .muxes = infracfg_mtk_mux, + .gates = infracfg_mtk_gates, + .flags = CLK_BYPASS_XTAL, + .xtal_rate = MT7987_XTAL_RATE, +}; + +static const struct udevice_id mt7987_infracfg_compat[] = { + { .compatible = "mediatek,mt7987-infracfg_ao" }, + { .compatible = "mediatek,mt7987-infracfg" }, + {} +}; + +static int mt7987_infracfg_probe(struct udevice *dev) +{ + return mtk_common_clk_infrasys_init(dev, &mt7987_infracfg_clk_tree); +} + +U_BOOT_DRIVER(mtk_clk_infracfg) = { + .name = "mt7987-clock-infracfg", + .id = UCLASS_CLK, + .of_match = mt7987_infracfg_compat, + .probe = mt7987_infracfg_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_infrasys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* ethsys */ +static const struct mtk_gate_regs eth_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x30, + .sta_ofs = 0x30, +}; + +#define GATE_ETH_TOP(_id, _name, _parent, _shift) \ + { \ + .id = (_id), .parent = (_parent), .regs = ð_cg_regs, \ + .shift = (_shift), \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate eth_cgs[] = { + GATE_ETH_TOP(CLK_ETHDMA_FE_EN, "ethdma_fe_en", CLK_TOP_NETSYS_2X_SEL, 6), + GATE_ETH_TOP(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", CLK_TOP_NETSYS_500M_SEL, 7), + GATE_ETH_TOP(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", CLK_TOP_NETSYS_500M_SEL, 8), + GATE_ETH_TOP(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", CLK_TOP_NETSYS_500M_SEL, 10), +}; + +static int mt7987_ethsys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7987_topckgen_clk_tree, + eth_cgs); +} + +static int mt7987_ethsys_bind(struct udevice *dev) +{ + int ret = 0; + + if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) { + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); + if (ret) + debug("Warning: failed to bind reset controller\n"); + } + + return ret; +} + +static const struct udevice_id mt7987_ethsys_compat[] = { + { + .compatible = "mediatek,mt7987-ethsys", + }, + {} +}; + +U_BOOT_DRIVER(mtk_clk_ethsys) = { + .name = "mt7987-clock-ethsys", + .id = UCLASS_CLK, + .of_match = mt7987_ethsys_compat, + .probe = mt7987_ethsys_probe, + .bind = mt7987_ethsys_bind, + .priv_auto = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; diff --git a/drivers/clk/stm32/clk-stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c index a554eda504d..6acf2ff0a8f 100644 --- a/drivers/clk/stm32/clk-stm32h7.c +++ b/drivers/clk/stm32/clk-stm32h7.c @@ -18,6 +18,9 @@ #include <dt-bindings/clock/stm32h7-clks.h> +/* must be equal to last peripheral clock index */ +#define LAST_PERIF_BANK SYSCFG_CK + /* RCC CR specific definitions */ #define RCC_CR_HSION BIT(0) #define RCC_CR_HSIRDY BIT(2) diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index f11eb66761b..dca7c222f35 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -211,8 +211,8 @@ static int fb_mmc_erase_mmc_hwpart(struct blk_desc *dev_desc) return 1; } - printf("........ erased %lu bytes from mmc hwpart[%u]\n", - dev_desc->lba * dev_desc->blksz, dev_desc->hwpart); + printf("........ erased %llu bytes from mmc hwpart[%u]\n", + (u64)(dev_desc->lba * dev_desc->blksz), dev_desc->hwpart); return 0; } @@ -257,8 +257,8 @@ static void fb_mmc_boot_ops(struct blk_desc *dev_desc, void *buffer, return; } - printf("........ wrote %lu bytes to EMMC_BOOT%d\n", - blkcnt * blksz, hwpart); + printf("........ wrote %llu bytes to EMMC_BOOT%d\n", + (u64)(blkcnt * blksz), hwpart); } else { /* erase */ if (fb_mmc_erase_mmc_hwpart(dev_desc)) { pr_err("Failed to erase EMMC_BOOT%d\n", hwpart); diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 1f6782537de..f88267e01b6 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -33,9 +33,9 @@ static void fpga_no_sup(char *fn, char *msg) /* fpga_get_desc * map a device number to a descriptor */ -const fpga_desc *const fpga_get_desc(int devnum) +const fpga_desc *fpga_get_desc(int devnum) { - fpga_desc *desc = (fpga_desc *)NULL; + const fpga_desc *desc = NULL; if ((devnum >= 0) && (devnum < next_desc)) { desc = &desc_table[devnum]; @@ -50,8 +50,8 @@ const fpga_desc *const fpga_get_desc(int devnum) * fpga_validate * generic parameter checking code */ -const fpga_desc *const fpga_validate(int devnum, const void *buf, - size_t bsize, char *fn) +const fpga_desc *fpga_validate(int devnum, const void *buf, + size_t bsize, char *fn) { const fpga_desc *desc = fpga_get_desc(devnum); @@ -60,7 +60,7 @@ const fpga_desc *const fpga_validate(int devnum, const void *buf, if (!buf) { printf("%s: Null buffer.\n", fn); - return (fpga_desc * const)NULL; + return NULL; } return desc; } @@ -72,7 +72,7 @@ const fpga_desc *const fpga_validate(int devnum, const void *buf, static int fpga_dev_info(int devnum) { int ret_val = FPGA_FAIL; /* assume failure */ - const fpga_desc * const desc = fpga_get_desc(devnum); + const fpga_desc *desc = fpga_get_desc(devnum); if (desc) { debug("%s: Device Descriptor @ 0x%p\n", @@ -374,7 +374,7 @@ int fpga_info(int devnum) #if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE) int fpga_compatible2flag(int devnum, const char *compatible) { - const fpga_desc * const desc = fpga_get_desc(devnum); + const fpga_desc *desc = fpga_get_desc(devnum); if (!desc) return 0; diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c index 760750568c0..27ef890ed0a 100644 --- a/drivers/led/led-uclass.c +++ b/drivers/led/led-uclass.c @@ -13,6 +13,25 @@ #include <dm/lists.h> #include <dm/root.h> #include <dm/uclass-internal.h> +#include <dt-bindings/leds/common.h> + +static const char * const led_colors[LED_COLOR_ID_MAX] = { + [LED_COLOR_ID_WHITE] = "white", + [LED_COLOR_ID_RED] = "red", + [LED_COLOR_ID_GREEN] = "green", + [LED_COLOR_ID_BLUE] = "blue", + [LED_COLOR_ID_AMBER] = "amber", + [LED_COLOR_ID_VIOLET] = "violet", + [LED_COLOR_ID_YELLOW] = "yellow", + [LED_COLOR_ID_IR] = "ir", + [LED_COLOR_ID_MULTI] = "multicolor", + [LED_COLOR_ID_RGB] = "rgb", + [LED_COLOR_ID_PURPLE] = "purple", + [LED_COLOR_ID_ORANGE] = "orange", + [LED_COLOR_ID_PINK] = "pink", + [LED_COLOR_ID_CYAN] = "cyan", + [LED_COLOR_ID_LIME] = "lime", +}; int led_bind_generic(struct udevice *parent, const char *driver_name) { @@ -232,11 +251,54 @@ int led_activity_blink(void) #endif #endif -static const char *led_get_label(ofnode node) +static const char *led_get_function_name(struct udevice *dev) +{ + struct led_uc_plat *uc_plat; + const char *func; + u32 color; + u32 enumerator; + int ret; + int cp; + + if (!dev) + return NULL; + + uc_plat = dev_get_uclass_plat(dev); + if (!uc_plat) + return NULL; + + if (uc_plat->label) + return uc_plat->label; + + /* Now try to detect function label name */ + func = dev_read_string(dev, "function"); + cp = dev_read_u32(dev, "color", &color); + if (cp == 0 || func) { + ret = dev_read_u32(dev, "function-enumerator", &enumerator); + if (!ret) { + snprintf(uc_plat->name, LED_MAX_NAME_SIZE, + "%s:%s-%d", + cp ? "" : led_colors[color], + func ? func : "", enumerator); + } else { + snprintf(uc_plat->name, LED_MAX_NAME_SIZE, + "%s:%s", + cp ? "" : led_colors[color], + func ? func : ""); + } + uc_plat->label = uc_plat->name; + } + + return uc_plat->label; +} + +static const char *led_get_label(struct udevice *dev, ofnode node) { const char *label; label = ofnode_read_string(node, "label"); + if (!label) + label = led_get_function_name(dev); if (!label && !ofnode_read_string(node, "compatible")) label = ofnode_get_name(node); @@ -249,7 +311,7 @@ static int led_post_bind(struct udevice *dev) const char *default_state; if (!uc_plat->label) - uc_plat->label = led_get_label(dev_ofnode(dev)); + uc_plat->label = led_get_label(dev, dev_ofnode(dev)); uc_plat->default_state = LEDST_COUNT; @@ -314,14 +376,14 @@ static int led_init(struct uclass *uc) #ifdef CONFIG_LED_BOOT ret = ofnode_options_get_by_phandle("boot-led", &led_node); if (!ret) - priv->boot_led_label = led_get_label(led_node); + priv->boot_led_label = led_get_label(NULL, led_node); priv->boot_led_period = ofnode_options_read_int("boot-led-period-ms", 250); #endif #ifdef CONFIG_LED_ACTIVITY ret = ofnode_options_get_by_phandle("activity-led", &led_node); if (!ret) - priv->activity_led_label = led_get_label(led_node); + priv->activity_led_label = led_get_label(NULL, led_node); priv->activity_led_period = ofnode_options_read_int("activity-led-period-ms", 250); #endif diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index e1110cace89..a51494380ce 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -724,7 +724,7 @@ static int dwmci_init(struct mmc *mmc) return 0; } -#ifdef CONFIG_DM_MMC +#if CONFIG_IS_ENABLED(DM_MMC) int dwmci_probe(struct udevice *dev) { struct mmc *mmc = mmc_get_mmc_dev(dev); @@ -749,7 +749,7 @@ void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, u32 max_clk, u32 min_clk) { cfg->name = host->name; -#ifndef CONFIG_DM_MMC +#if !CONFIG_IS_ENABLED(DM_MMC) cfg->ops = &dwmci_ops; #endif cfg->f_min = min_clk; diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index d676cf9e314..2bc700b0d05 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -329,6 +329,7 @@ struct msdc_compatible { u8 clk_div_bits; bool pad_tune0; bool async_fifo; + bool async_fifo_crcsts; bool data_tune; bool busy_check; bool stop_clk_fix; @@ -1553,8 +1554,12 @@ static void msdc_init_hw(struct msdc_host *host) /* use async fifo to avoid tune internal delay */ clrbits_le32(&host->base->patch_bit2, MSDC_PB2_CFGRESP); - clrbits_le32(&host->base->patch_bit2, - MSDC_PB2_CFGCRCSTS); + if (host->dev_comp->async_fifo_crcsts) + setbits_le32(&host->base->patch_bit2, + MSDC_PB2_CFGCRCSTS); + else + clrbits_le32(&host->base->patch_bit2, + MSDC_PB2_CFGCRCSTS); } if (host->dev_comp->data_tune) { @@ -1844,6 +1849,17 @@ static const struct msdc_compatible mt7986_compat = { .enhance_rx = true, }; +static const struct msdc_compatible mt7987_compat = { + .clk_div_bits = 12, + .pad_tune0 = true, + .async_fifo = true, + .async_fifo_crcsts = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, + .enhance_rx = true, +}; + static const struct msdc_compatible mt7981_compat = { .clk_div_bits = 12, .pad_tune0 = true, @@ -1886,6 +1902,7 @@ static const struct udevice_id msdc_ids[] = { { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat }, { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat }, { .compatible = "mediatek,mt7986-mmc", .data = (ulong)&mt7986_compat }, + { .compatible = "mediatek,mt7987-mmc", .data = (ulong)&mt7987_compat }, { .compatible = "mediatek,mt7981-mmc", .data = (ulong)&mt7981_compat }, { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat }, { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat }, diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 94d8f1b4c04..0a1fff38727 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -741,6 +741,18 @@ int designware_eth_probe(struct udevice *dev) puts("Error enabling phy supply\n"); return ret; } +#if IS_ENABLED(CONFIG_ARCH_NPCM8XX) + int phy_uv; + + phy_uv = dev_read_u32_default(dev, "phy-supply-microvolt", 0); + if (phy_uv) { + ret = regulator_set_value(phy_supply, phy_uv); + if (ret) { + puts("Error setting phy voltage\n"); + return ret; + } + } +#endif } #endif diff --git a/drivers/net/mtk_eth/an8855.c b/drivers/net/mtk_eth/an8855.c index 4bd7506a58b..25a98e0f935 100644 --- a/drivers/net/mtk_eth/an8855.c +++ b/drivers/net/mtk_eth/an8855.c @@ -22,7 +22,7 @@ #define AN8855_FORCE_MODE_LNK BIT(31) #define AN8855_FORCE_MODE 0xb31593f0 -#define AN8855_PORT_CTRL_BASE (0x10208000) +#define AN8855_PORT_CTRL_BASE 0x10208000 #define AN8855_PORT_CTRL_REG(p, r) (AN8855_PORT_CTRL_BASE + (p) * 0x200 + (r)) #define AN8855_PORTMATRIX_REG(p) AN8855_PORT_CTRL_REG(p, 0x44) @@ -46,7 +46,7 @@ #define AN8855_CKGCR 0x10213e1c -#define AN8855_SCU_BASE 0x10000000 +#define AN8855_SCU_BASE 0x10000000 #define AN8855_RG_RGMII_TXCK_C (AN8855_SCU_BASE + 0x1d0) #define AN8855_RG_GPIO_LED_MODE (AN8855_SCU_BASE + 0x0054) #define AN8855_RG_GPIO_LED_SEL(i) (AN8855_SCU_BASE + (0x0058 + ((i) * 4))) @@ -66,23 +66,23 @@ #define AN8855_RG_HSGMII_PCS_CTROL_1 (AN8855_HSGMII_CSR_PCS_BASE + 0xa00) #define AN8855_RG_AN_SGMII_MODE_FORCE (AN8855_HSGMII_CSR_PCS_BASE + 0xa24) -#define AN8855_MULTI_SGMII_CSR_BASE 0x10224000 -#define AN8855_SGMII_STS_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x018) +#define AN8855_MULTI_SGMII_CSR_BASE 0x10224000 +#define AN8855_SGMII_STS_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x018) #define AN8855_MSG_RX_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x100) -#define AN8855_MSG_RX_LIK_STS_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x514) -#define AN8855_MSG_RX_LIK_STS_2 (AN8855_MULTI_SGMII_CSR_BASE + 0x51c) +#define AN8855_MSG_RX_LIK_STS_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x514) +#define AN8855_MSG_RX_LIK_STS_2 (AN8855_MULTI_SGMII_CSR_BASE + 0x51c) #define AN8855_PHY_RX_FORCE_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x520) -#define AN8855_XFI_CSR_PCS_BASE 0x10225000 +#define AN8855_XFI_CSR_PCS_BASE 0x10225000 #define AN8855_RG_USXGMII_AN_CONTROL_0 (AN8855_XFI_CSR_PCS_BASE + 0xbf8) #define AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000 -#define AN8855_RG_RATE_ADAPT_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x000) +#define AN8855_RG_RATE_ADAPT_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x000) #define AN8855_RATE_ADP_P0_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x100) -#define AN8855_MII_RA_AN_ENABLE (AN8855_MULTI_PHY_RA_CSR_BASE + 0x300) +#define AN8855_MII_RA_AN_ENABLE (AN8855_MULTI_PHY_RA_CSR_BASE + 0x300) #define AN8855_QP_DIG_CSR_BASE 0x1022a000 -#define AN8855_QP_CK_RST_CTRL_4 (AN8855_QP_DIG_CSR_BASE + 0x310) +#define AN8855_QP_CK_RST_CTRL_4 (AN8855_QP_DIG_CSR_BASE + 0x310) #define AN8855_QP_DIG_MODE_CTRL_0 (AN8855_QP_DIG_CSR_BASE + 0x324) #define AN8855_QP_DIG_MODE_CTRL_1 (AN8855_QP_DIG_CSR_BASE + 0x330) @@ -90,7 +90,7 @@ #define AN8855_PON_RXFEDIG_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x100) #define AN8855_PON_RXFEDIG_CTRL_9 (AN8855_QP_PMA_TOP_BASE + 0x124) -#define AN8855_SS_LCPLL_PWCTL_SETTING_2 (AN8855_QP_PMA_TOP_BASE + 0x208) +#define AN8855_SS_LCPLL_PWCTL_SETTING_2 (AN8855_QP_PMA_TOP_BASE + 0x208) #define AN8855_SS_LCPLL_TDC_FLT_2 (AN8855_QP_PMA_TOP_BASE + 0x230) #define AN8855_SS_LCPLL_TDC_FLT_5 (AN8855_QP_PMA_TOP_BASE + 0x23c) #define AN8855_SS_LCPLL_TDC_PCW_1 (AN8855_QP_PMA_TOP_BASE + 0x248) @@ -101,7 +101,7 @@ #define AN8855_PLL_CTRL_3 (AN8855_QP_PMA_TOP_BASE + 0x40c) #define AN8855_PLL_CTRL_4 (AN8855_QP_PMA_TOP_BASE + 0x410) #define AN8855_PLL_CK_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x414) -#define AN8855_RX_DLY_0 (AN8855_QP_PMA_TOP_BASE + 0x614) +#define AN8855_RX_DLY_0 (AN8855_QP_PMA_TOP_BASE + 0x614) #define AN8855_RX_CTRL_2 (AN8855_QP_PMA_TOP_BASE + 0x630) #define AN8855_RX_CTRL_5 (AN8855_QP_PMA_TOP_BASE + 0x63c) #define AN8855_RX_CTRL_6 (AN8855_QP_PMA_TOP_BASE + 0x640) @@ -118,7 +118,7 @@ #define AN8855_RG_QP_CDR_PR_CKREF_DIV1 (AN8855_QP_ANA_CSR_BASE + 0x18) #define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE (AN8855_QP_ANA_CSR_BASE + 0x1c) #define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF (AN8855_QP_ANA_CSR_BASE + 0x20) -#define AN8855_RG_QP_TX_MODE_16B_EN (AN8855_QP_ANA_CSR_BASE + 0x28) +#define AN8855_RG_QP_TX_MODE_16B_EN (AN8855_QP_ANA_CSR_BASE + 0x28) #define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL (AN8855_QP_ANA_CSR_BASE + 0x3c) #define AN8855_RG_QP_PLL_SDM_ORD (AN8855_QP_ANA_CSR_BASE + 0x40) @@ -135,49 +135,49 @@ #define PHY_SINGLE_LED_ON_DUR(i) (0x3e9 + ((i) * 2)) #define PHY_SINGLE_LED_BLK_DUR(i) (0x3ea + ((i) * 2)) -#define PHY_PMA_CTRL (0x340) +#define PHY_PMA_CTRL 0x340 #define PHY_DEV1F 0x1f #define PHY_LED_ON_CTRL(i) (0x24 + ((i) * 2)) -#define LED_ON_EN (1 << 15) -#define LED_ON_POL (1 << 14) -#define LED_ON_EVT_MASK (0x7f) +#define LED_ON_EN BIT(15) +#define LED_ON_POL BIT(14) +#define LED_ON_EVT_MASK 0x7f /* LED ON Event */ -#define LED_ON_EVT_FORCE (1 << 6) -#define LED_ON_EVT_LINK_HD (1 << 5) -#define LED_ON_EVT_LINK_FD (1 << 4) -#define LED_ON_EVT_LINK_DOWN (1 << 3) -#define LED_ON_EVT_LINK_10M (1 << 2) -#define LED_ON_EVT_LINK_100M (1 << 1) -#define LED_ON_EVT_LINK_1000M (1 << 0) +#define LED_ON_EVT_FORCE BIT(6) +#define LED_ON_EVT_LINK_HD BIT(5) +#define LED_ON_EVT_LINK_FD BIT(4) +#define LED_ON_EVT_LINK_DOWN BIT(3) +#define LED_ON_EVT_LINK_10M BIT(2) +#define LED_ON_EVT_LINK_100M BIT(1) +#define LED_ON_EVT_LINK_1000M BIT(0) #define PHY_LED_BLK_CTRL(i) (0x25 + ((i) * 2)) -#define LED_BLK_EVT_MASK (0x3ff) +#define LED_BLK_EVT_MASK 0x3ff /* LED Blinking Event */ -#define LED_BLK_EVT_FORCE (1 << 9) -#define LED_BLK_EVT_10M_RX_ACT (1 << 5) -#define LED_BLK_EVT_10M_TX_ACT (1 << 4) -#define LED_BLK_EVT_100M_RX_ACT (1 << 3) -#define LED_BLK_EVT_100M_TX_ACT (1 << 2) -#define LED_BLK_EVT_1000M_RX_ACT (1 << 1) -#define LED_BLK_EVT_1000M_TX_ACT (1 << 0) +#define LED_BLK_EVT_FORCE BIT(9) +#define LED_BLK_EVT_10M_RX_ACT BIT(5) +#define LED_BLK_EVT_10M_TX_ACT BIT(4) +#define LED_BLK_EVT_100M_RX_ACT BIT(3) +#define LED_BLK_EVT_100M_TX_ACT BIT(2) +#define LED_BLK_EVT_1000M_RX_ACT BIT(1) +#define LED_BLK_EVT_1000M_TX_ACT BIT(0) #define PHY_LED_BCR (0x21) -#define LED_BCR_EXT_CTRL (1 << 15) -#define LED_BCR_CLK_EN (1 << 3) -#define LED_BCR_TIME_TEST (1 << 2) -#define LED_BCR_MODE_MASK (3) -#define LED_BCR_MODE_DISABLE (0) +#define LED_BCR_EXT_CTRL BIT(15) +#define LED_BCR_CLK_EN BIT(3) +#define LED_BCR_TIME_TEST BIT(2) +#define LED_BCR_MODE_MASK 3 +#define LED_BCR_MODE_DISABLE 0 -#define PHY_LED_ON_DUR (0x22) -#define LED_ON_DUR_MASK (0xffff) +#define PHY_LED_ON_DUR 0x22 +#define LED_ON_DUR_MASK 0xffff -#define PHY_LED_BLK_DUR (0x23) -#define LED_BLK_DUR_MASK (0xffff) +#define PHY_LED_BLK_DUR 0x23 +#define LED_BLK_DUR_MASK 0xffff -#define PHY_LED_BLINK_DUR_CTRL (0x720) +#define PHY_LED_BLINK_DUR_CTRL 0x720 /* Definition of LED */ #define LED_ON_EVENT (LED_ON_EVT_LINK_1000M | \ @@ -993,7 +993,7 @@ static int an8855_setup(struct mtk_eth_switch_priv *swpriv) /* Switch soft reset */ an8855_reg_write(priv, AN8855_SYS_CTRL_REG, AN8855_SW_SYS_RST); - udelay(100000); + mdelay(100); an8855_reg_read(priv, AN8855_PKG_SEL, &val); if ((val & 0x7) == PAG_SEL_AN8855H) { @@ -1003,8 +1003,7 @@ static int an8855_setup(struct mtk_eth_switch_priv *swpriv) /* Invert for LED activity change */ an8855_reg_read(priv, AN8855_RG_GPIO_L_INV, &val); for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { - if ((led_cfg[id].pol == LED_HIGH) && - (led_cfg[id].en == 1)) + if (led_cfg[id].pol == LED_HIGH && led_cfg[id].en == 1) val |= 0x1 << id; } an8855_reg_write(priv, AN8855_RG_GPIO_L_INV, (val | 0x1)); diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 13e73810ad6..3132718e4f8 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -2,10 +2,6 @@ config BITBANGMII bool "Bit-banged ethernet MII management channel support" -config BITBANGMII_MULTI - bool "Enable the multi bus support" - depends on BITBANGMII - config MV88E6352_SWITCH bool "Marvell 88E6352 switch support" diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c index b143137893f..9f5f9b12c9f 100644 --- a/drivers/net/phy/miiphybb.c +++ b/drivers/net/phy/miiphybb.c @@ -17,90 +17,6 @@ #include <miiphy.h> #include <asm/global_data.h> -#ifndef CONFIG_BITBANGMII_MULTI - -/* - * If CONFIG_BITBANGMII_MULTI is not defined we use a - * compatibility layer with the previous miiphybb implementation - * based on macros usage. - * - */ -static int bb_mii_init_wrap(struct bb_miiphy_bus *bus) -{ -#ifdef MII_INIT - MII_INIT; -#endif - return 0; -} - -static int bb_mdio_active_wrap(struct bb_miiphy_bus *bus) -{ -#ifdef MDIO_DECLARE - MDIO_DECLARE; -#endif - MDIO_ACTIVE; - return 0; -} - -static int bb_mdio_tristate_wrap(struct bb_miiphy_bus *bus) -{ -#ifdef MDIO_DECLARE - MDIO_DECLARE; -#endif - MDIO_TRISTATE; - return 0; -} - -static int bb_set_mdio_wrap(struct bb_miiphy_bus *bus, int v) -{ -#ifdef MDIO_DECLARE - MDIO_DECLARE; -#endif - MDIO(v); - return 0; -} - -static int bb_get_mdio_wrap(struct bb_miiphy_bus *bus, int *v) -{ -#ifdef MDIO_DECLARE - MDIO_DECLARE; -#endif - *v = MDIO_READ; - return 0; -} - -static int bb_set_mdc_wrap(struct bb_miiphy_bus *bus, int v) -{ -#ifdef MDC_DECLARE - MDC_DECLARE; -#endif - MDC(v); - return 0; -} - -static int bb_delay_wrap(struct bb_miiphy_bus *bus) -{ - MIIDELAY; - return 0; -} - -struct bb_miiphy_bus bb_miiphy_buses[] = { - { - .name = BB_MII_DEVNAME, - .init = bb_mii_init_wrap, - .mdio_active = bb_mdio_active_wrap, - .mdio_tristate = bb_mdio_tristate_wrap, - .set_mdio = bb_set_mdio_wrap, - .get_mdio = bb_get_mdio_wrap, - .set_mdc = bb_set_mdc_wrap, - .delay = bb_delay_wrap, - } -}; - -int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / - sizeof(bb_miiphy_buses[0]); -#endif - int bb_miiphy_init(void) { int i; @@ -114,7 +30,6 @@ int bb_miiphy_init(void) static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname) { -#ifdef CONFIG_BITBANGMII_MULTI int i; /* Search the correct bus */ @@ -124,10 +39,6 @@ static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname) } } return NULL; -#else - /* We have just one bitbanging bus */ - return &bb_miiphy_buses[0]; -#endif } /***************************************************************************** @@ -272,9 +183,7 @@ int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg) bus->set_mdc(bus, 1); bus->delay(bus); -#ifdef DEBUG - printf("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, rdreg); -#endif + debug("%s[%s](0x%x) @ 0x%x = 0x%04x\n", __func__, miidev->name, reg, addr, rdreg); return rdreg; } diff --git a/drivers/net/phy/ti_phy_init.c b/drivers/net/phy/ti_phy_init.c index a0878193ac0..850c0cbec96 100644 --- a/drivers/net/phy/ti_phy_init.c +++ b/drivers/net/phy/ti_phy_init.c @@ -10,12 +10,58 @@ #include <phy.h> #include "ti_phy_init.h" +#define DP83822_DEVADDR 0x1f + +#define MII_DP83822_RCSR 0x17 + +/* RCSR bits */ +#define DP83822_RX_CLK_SHIFT BIT(12) +#define DP83822_TX_CLK_SHIFT BIT(11) + +/* DP83822 specific RGMII RX/TX delay configuration. */ +static int dp83822_config(struct phy_device *phydev) +{ + ofnode node = phy_get_ofnode(phydev); + u32 rgmii_delay = 0; + u32 rx_delay = 0; + u32 tx_delay = 0; + int ret; + + ret = ofnode_read_u32(node, "rx-internal-delay-ps", &rx_delay); + if (ret) { + rx_delay = phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID; + } + + ret = ofnode_read_u32(node, "tx-internal-delay-ps", &tx_delay); + if (ret) { + tx_delay = phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID; + } + + /* Bit set means Receive path internal clock shift is ENABLED */ + if (rx_delay) + rgmii_delay |= DP83822_RX_CLK_SHIFT; + + /* Bit set means Transmit path internal clock shift is DISABLED */ + if (!tx_delay) + rgmii_delay |= DP83822_TX_CLK_SHIFT; + + ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, + DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, + rgmii_delay); + if (ret) + return ret; + + return genphy_config_aneg(phydev); +} + U_BOOT_PHY_DRIVER(dp83822) = { .name = "TI DP83822", .uid = 0x2000a240, .mask = 0xfffffff0, .features = PHY_BASIC_FEATURES, - .config = &genphy_config_aneg, + .config = &dp83822_config, .startup = &genphy_startup, .shutdown = &genphy_shutdown, }; diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index 231764e60b5..7286ad19598 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -560,12 +560,12 @@ static int ravb_remove(struct udevice *dev) return 0; } -int ravb_bb_init(struct bb_miiphy_bus *bus) +static int ravb_bb_init(struct bb_miiphy_bus *bus) { return 0; } -int ravb_bb_mdio_active(struct bb_miiphy_bus *bus) +static int ravb_bb_mdio_active(struct bb_miiphy_bus *bus) { struct ravb_priv *eth = bus->priv; @@ -574,7 +574,7 @@ int ravb_bb_mdio_active(struct bb_miiphy_bus *bus) return 0; } -int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus) +static int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus) { struct ravb_priv *eth = bus->priv; @@ -583,7 +583,7 @@ int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus) return 0; } -int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +static int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v) { struct ravb_priv *eth = bus->priv; @@ -595,7 +595,7 @@ int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v) return 0; } -int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +static int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) { struct ravb_priv *eth = bus->priv; @@ -604,7 +604,7 @@ int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) return 0; } -int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +static int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v) { struct ravb_priv *eth = bus->priv; @@ -616,7 +616,7 @@ int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v) return 0; } -int ravb_bb_delay(struct bb_miiphy_bus *bus) +static int ravb_bb_delay(struct bb_miiphy_bus *bus) { udelay(10); diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 34d23cece51..8b9180bd2aa 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -24,6 +24,10 @@ config PINCTRL_MT7986 bool "MT7986 SoC pinctrl driver" select PINCTRL_MTK +config PINCTRL_MT7987 + bool "MT7987 SoC pinctrl driver" + select PINCTRL_MTK + config PINCTRL_MT7988 bool "MT7988 SoC pinctrl driver" select PINCTRL_MTK diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index de39d1ea436..b25e74e4e00 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o +obj-$(CONFIG_PINCTRL_MT7987) += pinctrl-mt7987.o obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c index 047e37bc9cd..6b9769067b0 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -569,6 +569,11 @@ static const struct mtk_pin_desc mt7981_pins[] = { MT7981_TYPE1_PIN(56, "WF_HB10"), }; +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + /* WA_AICE */ static const int mt7981_wa_aice1_pins[] = { 0, 1, }; static const int mt7981_wa_aice1_funcs[] = { 2, 2, }; @@ -632,6 +637,9 @@ static const int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; static const int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; static const int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; +static const int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, }; +static const int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, }; + /* GBE_LED0 */ static const int mt7981_gbe_led0_pins[] = { 8, }; static const int mt7981_gbe_led0_funcs[] = { 3, }; @@ -718,6 +726,17 @@ static const int mt7981_drv_vbus_pins[] = { 14, }; static const int mt7981_drv_vbus_funcs[] = { 1, }; /* EMMC */ +static const int mt7981_emmc_reset_pins[] = { 15, }; +static const int mt7981_emmc_reset_funcs[] = { 2, }; + +static const int mt7981_emmc_4_pins[] = { 16, 17, 18, 19, 24, 25, }; +static const int mt7981_emmc_4_funcs[] = { 2, 2, 2, 2, 2, 2, }; + +static const int mt7981_emmc_8_pins[] = { + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; +static const int mt7981_emmc_8_funcs[] = { + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + static const int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; static const int mt7981_emmc_45_funcs[] = { @@ -754,6 +773,12 @@ static const int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; static const int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; static const int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; +static const int mt7981_uart1_2_pins[] = { 9, 10, }; +static const int mt7981_uart1_2_funcs[] = { 2, 2, }; + +static const int mt7981_uart1_3_pins[] = { 26, 27, }; +static const int mt7981_uart1_3_funcs[] = { 2, 2, }; + /* UART2 */ static const int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; static const int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; @@ -832,6 +857,8 @@ static const struct mtk_group_desc mt7981_groups[] = { PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), /* @GPIO(4,7) WM_JTAG(3) */ PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), + /* @GPIO(4,5) WM_JTAG(4) */ + PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx), /* @GPIO(8) GBE_LED0(3) */ PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), /* @GPIO(4,6) PTA_EXT(4) */ @@ -844,7 +871,7 @@ static const struct mtk_group_desc mt7981_groups[] = { PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0), /* @GPIO(6,7) I2C(5) */ PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0), - /* @GPIO(8): DFD_NTRST(6) */ + /* @GPIO(0,1,4,5): DFD_NTRST(6) */ PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst), /* @GPIO(9,10): WM_AICE(2) */ PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1), @@ -870,6 +897,12 @@ static const struct mtk_group_desc mt7981_groups[] = { PINCTRL_PIN_GROUP("udi", mt7981_udi), /* @GPIO(14) DRV_VBUS(1) */ PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), + /* @GPIO(15): EMMC_RSTB(2) */ + PINCTRL_PIN_GROUP("emmc_reset", mt7981_emmc_reset), + /* @GPIO(16,17,18,19,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ + PINCTRL_PIN_GROUP("emmc_4", mt7981_emmc_4), + /* @GPIO(16,17,18,19,20,21,22,23,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ + PINCTRL_PIN_GROUP("emmc_8", mt7981_emmc_8), /* @GPIO(15,25): EMMC(2) */ PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), /* @GPIO(16,21): SNFI(3) */ @@ -888,8 +921,12 @@ static const struct mtk_group_desc mt7981_groups[] = { PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), /* @GPIO(26,29): UART1(2) */ PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), + /* @GPIO(9,10): UART1(2) */ + PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2), + /* @GPIO(26,27): UART1(2) */ + PINCTRL_PIN_GROUP("uart1_3", mt7981_uart1_3), /* @GPIO(22,25): UART2(3) */ - PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_1), + PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), /* @GPIO(22,24) PTA_EXT(4) */ PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1), /* @GPIO(20,21): WM_UART(4) */ @@ -964,9 +1001,10 @@ static const struct mtk_io_type_desc mt7981_io_type_desc[] = { */ static const char *const mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", "wa_aice3", "wm_aice1_2", }; -static const char *const mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", - "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", - "uart1_0", "uart1_1", "uart2_0", "wm_aurt_1", "wm_aurt_2", "uart0", }; +static const char *const mt7981_uart_groups[] = { "net_wo0_uart_txd_0", + "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", "uart0", "uart1_0", + "uart1_1", "uart1_2", "uart1_3", "uart2_0", "uart2_0_tx_rx", "uart2_1", + "wm_uart_0", "wm_aurt_1", "wm_aurt_2", }; static const char *const mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; static const char *const mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; static const char *const mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", @@ -986,7 +1024,8 @@ static const char *const mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", static const char *const mt7981_pcm_groups[] = { "pcm", }; static const char *const mt7981_udi_groups[] = { "udi", }; static const char *const mt7981_usb_groups[] = { "drv_vbus", }; -static const char *const mt7981_flash_groups[] = { "emmc_45", "snfi", }; +static const char *const mt7981_flash_groups[] = { "emmc_reset", "emmc_4", + "emmc_8", "emmc_45", "snfi", }; static const char *const mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio", "wf0_mode1", "wf0_mode3", "mt7531_int", }; static const char *const mt7981_ant_groups[] = { "ant_sel", }; @@ -1012,8 +1051,9 @@ static const struct mtk_function_desc mt7981_functions[] = { }; static const char *const mt7981_pinctrl_register_base_names[] = { - "gpio_base", "iocfg_rt_base", "iocfg_rm_base", "iocfg_rb_base", - "iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base", "iocfg_tl_base", + "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", + "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl", + "eint", }; static const struct mtk_pinctrl_soc mt7981_data = { diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7987.c b/drivers/pinctrl/mediatek/pinctrl-mt7987.c new file mode 100644 index 00000000000..db672d26798 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt7987.c @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 MediaTek Inc. + * Author: Tim.Kuo <tim.kuo@mediatek.com> + */ + +#include <dm.h> +#include "pinctrl-mtk-common.h" + +enum MT7987_PINCTRL_REG_PAGE { + GPIO_BASE, + IOCFG_RB_BASE, + IOCFG_LB_BASE, + IOCFG_RT1_BASE, + IOCFG_RT2_BASE, + IOCFG_TL_BASE, +}; + +/* + * IO_TYPE_GRP0 / IO_TYPE_GRP1 + * MT7987 pins can be divided into two groups: + * - PUPD_R0_R1 + * - PU/PD + * Here, we divide pins with PU/PD to be IO_TYPE_GRP0 and those with PUPD_R0_R1 + * to be IO_TYPE_GRP1. + * - PUPD_R0_R1 : IO_TYPE_GRP0 + * - PU/PD : IO_TYPE_GRP1 + * DRV_GRP4 + * For MT7987, thr driving of pins can start from 2mA and increase by 2mA + * increments up to 16mA. + */ +#define MT7987_TYPE0_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0) + +#define MT7987_TYPE1_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1) + +#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs, \ + _s_bit, _x_bits, 32, 0) + +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \ + _s_bit, _x_bits, 32, 0) + +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \ + _s_bit, _x_bits, 32, 1) + +static const struct mtk_pin_field_calc mt7987_pin_mode_range[] = { + PIN_FIELD_GPIO(0, 49, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7987_pin_dir_range[] = { + PIN_FIELD_GPIO(0, 49, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_di_range[] = { + PIN_FIELD_GPIO(0, 49, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_do_range[] = { + PIN_FIELD_GPIO(0, 49, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x20, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x10, 0x10, 2, 1), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x10, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x10, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x10, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x10, 0x10, 4, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x20, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x20, 0x10, 8, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x20, 0x10, 9, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x20, 0x10, 12, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x20, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x20, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x20, 0x10, 13, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x20, 0x10, 14, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x20, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x20, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x20, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x20, 0x10, 9, 1), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x20, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x20, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x90, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x70, 0x10, 4, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0xA0, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0xA0, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0xA0, 0x10, 3, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0xA0, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0xA0, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0xA0, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0xA0, 0x10, 5, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0xA0, 0x10, 8, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0xA0, 0x10, 9, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0xA0, 0x10, 12, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0xA0, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0xA0, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0xA0, 0x10, 13, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0xA0, 0x10, 14, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x90, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x90, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x60, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0xA0, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0xA0, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x90, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x90, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_pu_range[] = { + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x40, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_pd_range[] = { + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x30, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x0, 0x10, 9, 3), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x0, 0x10, 6, 3), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x0, 0x10, 6, 3), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x0, 0x10, 3, 3), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x0, 0x10, 9, 3), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x0, 0x10, 0, 3), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x0, 0x10, 12, 3), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x0, 0x10, 6, 3), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x0, 0x10, 3, 3), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x0, 0x10, 0, 3), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x0, 0x10, 9, 3), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x0, 0x10, 12, 3), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x0, 0x10, 0, 3), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x10, 0x10, 15, 3), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x0, 0x10, 9, 3), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x0, 0x10, 21, 3), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x0, 0x10, 18, 3), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x0, 0x10, 12, 3), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x0, 0x10, 15, 3), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x0, 0x10, 24, 3), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x0, 0x10, 27, 3), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x0, 0x10, 27, 3), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x0, 0x10, 21, 3), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x0, 0x10, 24, 3), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x0, 0x10, 15, 3), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x0, 0x10, 18, 3), + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x0, 0x10, 6, 3), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x0, 0x10, 0, 3), + PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x0, 0x10, 12, 3), + PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x0, 0x10, 9, 3), + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x0, 0x10, 3, 3), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x0, 0x10, 15, 3), + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x0, 0x10, 3, 3), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x0, 0x10, 6, 3), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x0, 0x10, 0, 3), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x0, 0x10, 3, 3), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x0, 0x10, 12, 3), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x0, 0x10, 15, 3), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x0, 0x10, 18, 3), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x0, 0x10, 27, 3), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x0, 0x10, 21, 3), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x0, 0x10, 24, 3), +}; + +static const struct mtk_pin_field_calc mt7987_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x30, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x30, 0x10, 12, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x30, 0x10, 13, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x30, 0x10, 14, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x30, 0x10, 6, 1), + + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x30, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_r0_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x40, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x40, 0x10, 12, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x40, 0x10, 13, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x40, 0x10, 6, 1), + + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x40, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_r1_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x50, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x50, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x50, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x50, 0x10, 13, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x50, 0x10, 14, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x50, 0x10, 6, 1), + + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x50, 0x10, 8, 1), +}; + +static const struct mtk_pin_reg_calc mt7987_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7987_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7987_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7987_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7987_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7987_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7987_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7987_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7987_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7987_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7987_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7987_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7987_pin_r1_range), +}; + +static const struct mtk_pin_desc mt7987_pins[] = { + MT7987_TYPE0_PIN(0, "GPIO_WPS"), + MT7987_TYPE0_PIN(1, "GPIO_RESET"), + MT7987_TYPE0_PIN(2, "SYS_WATCHDOG"), + MT7987_TYPE0_PIN(3, "JTAG_JTDO"), + MT7987_TYPE0_PIN(4, "JTAG_JTDI"), + MT7987_TYPE0_PIN(5, "JTAG_JTMS"), + MT7987_TYPE0_PIN(6, "JTAG_JTCLK"), + MT7987_TYPE0_PIN(7, "JTAG_JTRST_N"), + MT7987_TYPE0_PIN(8, "PCM_DTX_I2S_DOUT"), + MT7987_TYPE0_PIN(9, "PCM_DRX_I2S_DIN"), + MT7987_TYPE0_PIN(10, "PCM_CLK_I2S_BCLK"), + MT7987_TYPE0_PIN(11, "PCM_FS_I2S_LRCK"), + MT7987_TYPE0_PIN(12, "PCM_MCK_I2S_MCLK"), + MT7987_TYPE0_PIN(13, "PWM0"), + MT7987_TYPE0_PIN(14, "USB_VBUS"), + MT7987_TYPE0_PIN(15, "SPI0_CLK"), + MT7987_TYPE0_PIN(16, "SPI0_MOSI"), + MT7987_TYPE0_PIN(17, "SPI0_MISO"), + MT7987_TYPE0_PIN(18, "SPI0_CS"), + MT7987_TYPE0_PIN(19, "SPI0_HOLD"), + MT7987_TYPE0_PIN(20, "SPI0_WP"), + MT7987_TYPE0_PIN(21, "SPI1_CLK"), + MT7987_TYPE0_PIN(22, "SPI1_MOSI"), + MT7987_TYPE0_PIN(23, "SPI1_MISO"), + MT7987_TYPE0_PIN(24, "SPI1_CS"), + MT7987_TYPE0_PIN(25, "SPI2_CLK"), + MT7987_TYPE0_PIN(26, "SPI2_MOSI"), + MT7987_TYPE0_PIN(27, "SPI2_MISO"), + MT7987_TYPE0_PIN(28, "SPI2_CS"), + MT7987_TYPE0_PIN(29, "SPI2_HOLD"), + MT7987_TYPE0_PIN(30, "SPI2_WP"), + MT7987_TYPE0_PIN(31, "UART0_RXD"), + MT7987_TYPE0_PIN(32, "UART0_TXD"), + MT7987_TYPE1_PIN(33, "PCIE_PERESET_N_0"), + MT7987_TYPE1_PIN(34, "PCIE_CLK_REQ_0"), + MT7987_TYPE1_PIN(35, "PCIE_WAKE_N_0"), + MT7987_TYPE1_PIN(36, "PCIE_PERESET_N_1"), + MT7987_TYPE1_PIN(37, "PCIE_CLK_REQ_1"), + MT7987_TYPE1_PIN(38, "PCIE_WAKE_N_1"), + MT7987_TYPE0_PIN(39, "SMI_MDC"), + MT7987_TYPE0_PIN(40, "SMI_MDIO"), + MT7987_TYPE0_PIN(41, "GBE_INT"), + MT7987_TYPE0_PIN(42, "GBE_RESET"), + MT7987_TYPE0_PIN(43, "I2C_SCLK"), + MT7987_TYPE0_PIN(44, "I2C_SDATA"), + MT7987_TYPE0_PIN(45, "2P5G_LED0"), + MT7987_TYPE0_PIN(46, "UART1_RXD"), + MT7987_TYPE0_PIN(47, "UART1_TXD"), + MT7987_TYPE0_PIN(48, "UART1_CTS"), + MT7987_TYPE0_PIN(49, "UART1_RTS"), +}; + +/* watchdog */ +static const int mt7987_watchdog_pins[] = {2}; +static const int mt7987_watchdog_funcs[] = {1}; + +/* jtag */ +static const int mt7987_jtag_pins[] = {3, 4, 5, 6, 7}; +static const int mt7987_jtag_funcs[] = {1, 1, 1, 1, 1}; + +/* pcm */ +static const int mt7987_pcm0_0_pins[] = {3, 4, 5, 6, 7}; +static const int mt7987_pcm0_0_funcs[] = {2, 2, 2, 2, 2}; + +static const int mt7987_pcm0_1_pins[] = {8, 9, 10, 11, 12}; +static const int mt7987_pcm0_1_funcs[] = {1, 1, 1, 1, 1}; + +/* uart */ +static const int mt7987_uart0_pins[] = {31, 32}; +static const int mt7987_uart0_funcs[] = {1, 1}; + +static const int mt7987_uart1_0_pins[] = {3, 4, 5, 6}; +static const int mt7987_uart1_0_funcs[] = {3, 3, 3, 3}; + +static const int mt7987_uart1_1_pins[] = {21, 22, 23, 24}; +static const int mt7987_uart1_1_funcs[] = {3, 3, 3, 3}; + +static const int mt7987_uart1_2_pins[] = {46, 47, 48, 49}; +static const int mt7987_uart1_2_funcs[] = {1, 1, 1, 1}; + +static const int mt7987_uart2_0_pins[] = {8, 9, 10, 11}; +static const int mt7987_uart2_0_funcs[] = {2, 2, 2, 2}; + +static const int mt7987_uart2_1_pins[] = {25, 26, 27, 28}; +static const int mt7987_uart2_1_funcs[] = {2, 2, 2, 2}; + +/* pwm */ +static const int mt7987_pwm0_pins[] = {13}; +static const int mt7987_pwm0_funcs[] = {1}; + +static const int mt7987_pwm1_0_pins[] = {7}; +static const int mt7987_pwm1_0_funcs[] = {3}; + +static const int mt7987_pwm1_1_pins[] = {43}; +static const int mt7987_pwm1_1_funcs[] = {2}; + +static const int mt7987_pwm2_0_pins[] = {12}; +static const int mt7987_pwm2_0_funcs[] = {2}; + +static const int mt7987_pwm2_1_pins[] = {44}; +static const int mt7987_pwm2_1_funcs[] = {2}; + +/* vbus */ +static const int mt7987_drv_vbus_p1_pins[] = {14}; +static const int mt7987_drv_vbus_p1_funcs[] = {1}; + +static const int mt7987_drv_vbus_pins[] = {48}; +static const int mt7987_drv_vbus_funcs[] = {3}; + +/* 2p5gbe_led */ +static const int mt7987_2p5gbe_led0_pins[] = {45}; +static const int mt7987_2p5gbe_led0_funcs[] = {1}; + +static const int mt7987_2p5gbe_led1_0_pins[] = {13}; +static const int mt7987_2p5gbe_led1_0_funcs[] = {2}; + +static const int mt7987_2p5gbe_led1_1_pins[] = {49}; +static const int mt7987_2p5gbe_led1_1_funcs[] = {3}; + +/* mdc, mdio */ +static const int mt7987_2p5g_ext_mdc_mdio_pins[] = {23, 24}; +static const int mt7987_2p5g_ext_mdc_mdio_funcs[] = {4, 4}; + +static const int mt7987_mdc_mdio_pins[] = {39, 40}; +static const int mt7987_mdc_mdio_funcs[] = {1, 1}; + +/* spi */ +static const int mt7987_spi0_pins[] = {15, 16, 17, 18}; +static const int mt7987_spi0_funcs[] = {1, 1, 1, 1}; + +static const int mt7987_spi0_wp_hold_pins[] = {19, 20}; +static const int mt7987_spi0_wp_hold_funcs[] = {1, 1}; + +static const int mt7987_spi1_pins[] = {21, 22, 23, 24}; +static const int mt7987_spi1_funcs[] = {1, 1, 1, 1}; + +static const int mt7987_spi1_1_pins[] = {46, 47, 48, 49}; +static const int mt7987_spi1_1_funcs[] = {2, 2, 2, 2}; + +static const int mt7987_spi2_pins[] = {25, 26, 27, 28}; +static const int mt7987_spi2_funcs[] = {1, 1, 1, 1}; + +static const int mt7987_spi2_wp_hold_pins[] = {29, 30}; +static const int mt7987_spi2_wp_hold_funcs[] = {1, 1}; + +/* emmc */ +static const int mt7987_emmc_45_pins[] = {14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24}; +static const int mt7987_emmc_45_funcs[] = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}; + +/* sd */ +static const int mt7987_sd_pins[] = {15, 16, 17, 18, 23, 24}; +static const int mt7987_sd_funcs[] = {2, 2, 2, 2, 2, 2}; + +/* i2c */ +static const int mt7987_i2c0_0_pins[] = {29, 30}; +static const int mt7987_i2c0_0_funcs[] = {2, 2}; + +static const int mt7987_i2c0_1_pins[] = {39, 40}; +static const int mt7987_i2c0_1_funcs[] = {2, 2}; + +static const int mt7987_i2c0_2_pins[] = {43, 44}; +static const int mt7987_i2c0_2_funcs[] = {1, 1}; + +/* pcie */ +static const int mt7987_pcie0_pereset_pins[] = {33}; +static const int mt7987_pcie0_pereset_funcs[] = {1}; + +static const int mt7987_pcie0_clkreq_pins[] = {34}; +static const int mt7987_pcie0_clkreq_funcs[] = {1}; + +static const int mt7987_pcie0_wake_pins[] = {35}; +static const int mt7987_pcie0_wake_funcs[] = {1}; + +static const int mt7987_pcie1_pereset_pins[] = {36}; +static const int mt7987_pcie1_pereset_funcs[] = {1}; + +static const int mt7987_pcie1_clkreq_pins[] = {37}; +static const int mt7987_pcie1_clkreq_funcs[] = {1}; + +static const int mt7987_pcie1_wake_pins[] = {38}; +static const int mt7987_pcie1_wake_funcs[] = {1}; + +static const int mt7987_pcie_phy_i2c_pins[] = {43, 44}; +static const int mt7987_pcie_phy_i2c_funcs[] = {3, 3}; + +/* snfi */ +static const int mt7987_snfi_pins[] = {25, 26, 27, 28, 29, 30}; +static const int mt7987_snfi_funcs[] = {3, 3, 3, 3, 3, 3}; + +/* + * - int hsgmii : + * For pin41 and pin46, they now can only be used as gpio mode for polling + * event. Hence, there's no need to open their pinctrl setting. + * - dfd, udi : + * Due to dfd & udi functions are only used as detection pins for cpu during + * dvt testing stage, we also remove their pinctrl setting. + */ + +static const struct mtk_group_desc mt7987_groups[] = { + PINCTRL_PIN_GROUP("watchdog", mt7987_watchdog), + PINCTRL_PIN_GROUP("jtag", mt7987_jtag), + PINCTRL_PIN_GROUP("pcm0_0", mt7987_pcm0_0), + PINCTRL_PIN_GROUP("pcm0_1", mt7987_pcm0_1), + PINCTRL_PIN_GROUP("uart0", mt7987_uart0), + PINCTRL_PIN_GROUP("uart1_0", mt7987_uart1_0), + PINCTRL_PIN_GROUP("uart1_1", mt7987_uart1_1), + PINCTRL_PIN_GROUP("uart1_2", mt7987_uart1_2), + PINCTRL_PIN_GROUP("uart2_0", mt7987_uart2_0), + PINCTRL_PIN_GROUP("uart2_1", mt7987_uart2_1), + PINCTRL_PIN_GROUP("pwm0", mt7987_pwm0), + PINCTRL_PIN_GROUP("pwm1_0", mt7987_pwm1_0), + PINCTRL_PIN_GROUP("pwm1_1", mt7987_pwm1_1), + PINCTRL_PIN_GROUP("pwm2_0", mt7987_pwm2_0), + PINCTRL_PIN_GROUP("pwm2_1", mt7987_pwm2_1), + PINCTRL_PIN_GROUP("drv_vbus_p1", mt7987_drv_vbus_p1), + PINCTRL_PIN_GROUP("drv_vbus", mt7987_drv_vbus), + PINCTRL_PIN_GROUP("2p5gbe_led0", mt7987_2p5gbe_led0), + PINCTRL_PIN_GROUP("2p5gbe_led1_0", mt7987_2p5gbe_led1_0), + PINCTRL_PIN_GROUP("2p5gbe_led1_1", mt7987_2p5gbe_led1_1), + PINCTRL_PIN_GROUP("2p5g_ext_mdc_mdio", mt7987_2p5g_ext_mdc_mdio), + PINCTRL_PIN_GROUP("mdc_mdio", mt7987_mdc_mdio), + PINCTRL_PIN_GROUP("spi0", mt7987_spi0), + PINCTRL_PIN_GROUP("spi0_wp_hold", mt7987_spi0_wp_hold), + PINCTRL_PIN_GROUP("spi1", mt7987_spi1), + PINCTRL_PIN_GROUP("spi1_1", mt7987_spi1_1), + PINCTRL_PIN_GROUP("spi2", mt7987_spi2), + PINCTRL_PIN_GROUP("spi2_wp_hold", mt7987_spi2_wp_hold), + PINCTRL_PIN_GROUP("emmc_45", mt7987_emmc_45), + PINCTRL_PIN_GROUP("sd", mt7987_sd), + PINCTRL_PIN_GROUP("i2c0_0", mt7987_i2c0_0), + PINCTRL_PIN_GROUP("i2c0_1", mt7987_i2c0_1), + PINCTRL_PIN_GROUP("i2c0_2", mt7987_i2c0_2), + PINCTRL_PIN_GROUP("pcie_phy_i2c", mt7987_pcie_phy_i2c), + PINCTRL_PIN_GROUP("pcie0_pereset", mt7987_pcie0_pereset), + PINCTRL_PIN_GROUP("pcie0_clkreq", mt7987_pcie0_clkreq), + PINCTRL_PIN_GROUP("pcie0_wake", mt7987_pcie0_wake), + PINCTRL_PIN_GROUP("pcie1_pereset", mt7987_pcie1_pereset), + PINCTRL_PIN_GROUP("pcie1_clkreq", mt7987_pcie1_clkreq), + PINCTRL_PIN_GROUP("pcie1_wake", mt7987_pcie1_wake), + PINCTRL_PIN_GROUP("snfi", mt7987_snfi), +}; + +static const struct mtk_io_type_desc mt7987_io_type_desc[] = { + [IO_TYPE_GRP0] = { + .name = "18OD33", + .bias_set = mtk_pinconf_bias_set_pupd_r1_r0, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, + [IO_TYPE_GRP1] = { + .name = "18A01", + .bias_set = mtk_pinconf_bias_set_pu_pd, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, +}; + +static const char *const mt7987_wdt_groups[] = {"watchdog",}; +static const char *const mt7987_jtag_groups[] = {"jtag",}; +static const char *const mt7987_pcm_groups[] = {"pcm0_0", "pcm0_1"}; +static const char *const mt7987_uart_groups[] = {"uart0", "uart1_0", "uart1_1", + "uart1_2", "uart2_0", "uart2_1",}; +static const char *const mt7987_pwm_groups[] = {"pwm0", "pwm1_0", "pwm1_1", "pwm2_0", + "pwm2_1",}; +static const char *const mt7987_usb_groups[] = {"drv_vbus_p1", "drv_vbus",}; +static const char *const mt7987_led_groups[] = {"2p5gbe_led0", "2p5gbe_led1_0", + "2p5gbe_led1_1",}; +static const char *const mt7987_ethernet_groups[] = {"2p5g_ext_mdc_mdio", "mdc_mdio",}; +static const char *const mt7987_spi_groups[] = {"spi0", "spi0_wp_hold", "spi1", + "spi1_1", "spi2", "spi2_wp_hold",}; +static const char *const mt7987_flash_groups[] = {"emmc_45", "snfi", "sd",}; +static const char *const mt7987_i2c_groups[] = {"i2c0_0", "i2c0_1", "i2c0_2",}; +static const char *const mt7987_pcie_groups[] = {"pcie_phy_i2c", "pcie0_pereset", + "pcie0_clkreq", "pcie0_wake", + "pcie1_pereset", "pcie1_clkreq", + "pcie1_wake",}; + +static const struct mtk_function_desc mt7987_functions[] = { + {"wdt", mt7987_wdt_groups, ARRAY_SIZE(mt7987_wdt_groups)}, + {"jtag", mt7987_jtag_groups, ARRAY_SIZE(mt7987_jtag_groups)}, + {"pcm", mt7987_pcm_groups, ARRAY_SIZE(mt7987_pcm_groups)}, + {"uart", mt7987_uart_groups, ARRAY_SIZE(mt7987_uart_groups)}, + {"pwm", mt7987_pwm_groups, ARRAY_SIZE(mt7987_pwm_groups)}, + {"usb", mt7987_usb_groups, ARRAY_SIZE(mt7987_usb_groups)}, + {"led", mt7987_led_groups, ARRAY_SIZE(mt7987_led_groups)}, + {"eth", mt7987_ethernet_groups, ARRAY_SIZE(mt7987_ethernet_groups)}, + {"spi", mt7987_spi_groups, ARRAY_SIZE(mt7987_spi_groups)}, + {"flash", mt7987_flash_groups, ARRAY_SIZE(mt7987_flash_groups)}, + {"i2c", mt7987_i2c_groups, ARRAY_SIZE(mt7987_i2c_groups)}, + {"pcie", mt7987_pcie_groups, ARRAY_SIZE(mt7987_pcie_groups)}, +}; + +static const char *const mt7987_pinctrl_register_base_names[] = { + "gpio", "iocfg_rb", "iocfg_lb", "iocfg_rt1", "iocfg_rt2", "iocfg_tl", +}; + +static const struct mtk_pinctrl_soc mt7987_data = { + .name = "mt7987_pinctrl", + .reg_cal = mt7987_reg_cals, + .pins = mt7987_pins, + .npins = ARRAY_SIZE(mt7987_pins), + .grps = mt7987_groups, + .ngrps = ARRAY_SIZE(mt7987_groups), + .funcs = mt7987_functions, + .nfuncs = ARRAY_SIZE(mt7987_functions), + .io_type = mt7987_io_type_desc, + .ntype = ARRAY_SIZE(mt7987_io_type_desc), + .gpio_mode = 0, + .base_names = mt7987_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7987_pinctrl_register_base_names), + .base_calc = 1, +}; + +static int mtk_pinctrl_mt7987_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt7987_data); +} + +static const struct udevice_id mt7987_pctrl_match[] = { + {.compatible = "mediatek,mt7987-pinctrl"}, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt7987_pinctrl) = { + .name = "mt7987_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt7987_pctrl_match, + .ops = &mtk_pinctrl_ops, + .bind = mtk_pinctrl_common_bind, + .probe = mtk_pinctrl_mt7987_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/drivers/pinctrl/mediatek/pinctrl-mt7988.c index 1f384e86f4e..639e2415c63 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -1233,8 +1233,7 @@ static const struct mtk_function_desc mt7988_functions[] = { }; static const char *const mt7988_pinctrl_register_base_names[] = { - "gpio_base", "iocfg_tr_base", "iocfg_br_base", "iocfg_rb_base", - "iocfg_lb_base", "iocfg_tl_base", + "gpio", "iocfg_tr", "iocfg_br", "iocfg_rb", "iocfg_lb", "iocfg_tl", }; static const struct mtk_pinctrl_soc mt7988_data = { diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 3760c4611ce..4aecb84504a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -816,7 +816,11 @@ int mtk_pinctrl_common_probe(struct udevice *dev, nbase_names = 1; for (i = 0; i < nbase_names; i++) { - addr = devfdt_get_addr_index(dev, i); + if (soc->base_names) + addr = dev_read_addr_name(dev, soc->base_names[i]); + else + addr = dev_read_addr_index(dev, i); + if (addr == FDT_ADDR_T_NONE) return -EINVAL; priv->base[i] = (void __iomem *)addr; diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive.c index 95b1a752de2..1b942e6f045 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive.c @@ -348,7 +348,7 @@ static const struct dm_gpio_ops starfive_gpio_ops = { .set_value = starfive_gpio_set_value, }; -static struct driver starfive_gpio_driver = { +U_BOOT_DRIVER(starfive_gpio) = { .name = "starfive_gpio", .id = UCLASS_GPIO, .probe = starfive_gpio_probe, @@ -367,7 +367,7 @@ static int starfive_gpiochip_register(struct udevice *parent) return -ENOENT; node = dev_ofnode(parent); - ret = device_bind_with_driver_data(parent, &starfive_gpio_driver, + ret = device_bind_with_driver_data(parent, DM_DRIVER_REF(starfive_gpio), "starfive_gpio", 0, node, &dev); return (ret == 0) ? 0 : ret; diff --git a/drivers/remoteproc/renesas_apmu.c b/drivers/remoteproc/renesas_apmu.c index 32d138e6487..1a50cd3289b 100644 --- a/drivers/remoteproc/renesas_apmu.c +++ b/drivers/remoteproc/renesas_apmu.c @@ -68,6 +68,13 @@ static int renesas_apmu_rproc_load(struct udevice *dev, ulong addr, ulong size) flush_dcache_range(trampolineaddr, trampolineaddr + sizeof(renesas_apmu_rproc_trampoline)); + invalidate_dcache_range(trampolineaddr, + trampolineaddr + + sizeof(renesas_apmu_rproc_trampoline)); + flush_dcache_range(addr, addr + size); + invalidate_dcache_range(addr, addr + size); + asm volatile("dsb sy\n"); + asm volatile("isb sy\n"); /* CR52 boot address set */ writel(trampolineaddr | APMU_CRBARP_CR_VLD_BARP, diff --git a/drivers/rtc/emul_rtc.c b/drivers/rtc/emul_rtc.c index 97a8d9bb7df..6817daad18f 100644 --- a/drivers/rtc/emul_rtc.c +++ b/drivers/rtc/emul_rtc.c @@ -58,7 +58,7 @@ static int emul_rtc_set(struct udevice *dev, const struct rtc_time *time) return 0; } -int emul_rtc_probe(struct udevice *dev) +static int emul_rtc_probe(struct udevice *dev) { struct emul_rtc *priv = dev_get_priv(dev); const char *epoch_str; diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index bcdeda95ed1..cd0b84c0622 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -38,7 +38,7 @@ void scsi_setup_read16(struct scsi_cmd *pccb, lbaint_t start, unsigned long blocks) { pccb->cmd[0] = SCSI_READ16; - pccb->cmd[1] = pccb->lun << 5; + pccb->cmd[1] = 0; pccb->cmd[2] = (unsigned char)(start >> 56) & 0xff; pccb->cmd[3] = (unsigned char)(start >> 48) & 0xff; pccb->cmd[4] = (unsigned char)(start >> 40) & 0xff; @@ -66,7 +66,7 @@ void scsi_setup_read16(struct scsi_cmd *pccb, lbaint_t start, static void scsi_setup_inquiry(struct scsi_cmd *pccb) { pccb->cmd[0] = SCSI_INQUIRY; - pccb->cmd[1] = pccb->lun << 5; + pccb->cmd[1] = 0; pccb->cmd[2] = 0; pccb->cmd[3] = 0; if (pccb->datalen > 255) @@ -82,7 +82,7 @@ static void scsi_setup_read_ext(struct scsi_cmd *pccb, lbaint_t start, unsigned short blocks) { pccb->cmd[0] = SCSI_READ10; - pccb->cmd[1] = pccb->lun << 5; + pccb->cmd[1] = 0; pccb->cmd[2] = (unsigned char)(start >> 24) & 0xff; pccb->cmd[3] = (unsigned char)(start >> 16) & 0xff; pccb->cmd[4] = (unsigned char)(start >> 8) & 0xff; @@ -103,7 +103,7 @@ static void scsi_setup_write_ext(struct scsi_cmd *pccb, lbaint_t start, unsigned short blocks) { pccb->cmd[0] = SCSI_WRITE10; - pccb->cmd[1] = pccb->lun << 5; + pccb->cmd[1] = 0; pccb->cmd[2] = (unsigned char)(start >> 24) & 0xff; pccb->cmd[3] = (unsigned char)(start >> 16) & 0xff; pccb->cmd[4] = (unsigned char)(start >> 8) & 0xff; @@ -289,7 +289,7 @@ static int scsi_read_capacity(struct udevice *dev, struct scsi_cmd *pccb, memset(pccb->cmd, '\0', sizeof(pccb->cmd)); pccb->cmd[0] = SCSI_RD_CAPAC10; - pccb->cmd[1] = pccb->lun << 5; + pccb->cmd[1] = 0; pccb->cmdlen = 10; pccb->dma_dir = DMA_FROM_DEVICE; pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */ @@ -353,7 +353,7 @@ static int scsi_read_capacity(struct udevice *dev, struct scsi_cmd *pccb, static void scsi_setup_test_unit_ready(struct scsi_cmd *pccb) { pccb->cmd[0] = SCSI_TST_U_RDY; - pccb->cmd[1] = pccb->lun << 5; + pccb->cmd[1] = 0; pccb->cmd[2] = 0; pccb->cmd[3] = 0; pccb->cmd[4] = 0; diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 039da835f5f..0e267d097c5 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -605,6 +605,7 @@ static const struct udevice_id ns16550_serial_ids[] = { { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 }, { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 }, { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 }, + { .compatible = "intel,xscale-uart", .data = PORT_NS16550 }, {} }; #endif /* OF_REAL */ diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index dcf28c75596..816916de16d 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -24,6 +24,13 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, u8 opcode, addr_bytes, *rxbuf, dummy_cycles; n_rx = op->data.nbytes; + + if (op->addr.dtr && (op->addr.val % 2)) { + n_rx += 1; + writel(op->addr.val & ~0x1, + priv->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); + } + rxbuf = op->data.buf.in; rx_rem = n_rx % 4; bytes_to_dma = n_rx - rx_rem; @@ -104,6 +111,11 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, memcpy(rxbuf, &data, rx_rem); } + if (op->addr.dtr && (op->addr.val % 2)) { + rxbuf -= bytes_to_dma; + memcpy(rxbuf, rxbuf + 1, n_rx - 1); + } + return 0; } diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 693474a2871..1f9125cd239 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -307,7 +307,7 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, const struct spi_mem_op *op); int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv); int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg); -int cadence_qspi_versal_flash_reset(struct udevice *dev); +int cadence_qspi_flash_reset(struct udevice *dev); ofnode cadence_qspi_get_subnode(struct udevice *dev); void cadence_qspi_apb_enable_linear_mode(bool enable); diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig index d59102d9a6b..01bc686d367 100644 --- a/drivers/tpm/Kconfig +++ b/drivers/tpm/Kconfig @@ -209,6 +209,15 @@ config TPM2_MMIO to the device using the standard TPM Interface Specification (TIS) protocol. +config TPM2_EVENT_LOG_SIZE + int "EventLog size" + depends on TPM_V2 + default 65536 + help + Define the size of the EventLog. Note that this is going to be + allocated twice. One for the eventlog it self and one for the + configuration table that is required from the TCG2 spec + endif # TPM_V2 endmenu diff --git a/env/fat.c b/env/fat.c index b04b1d9c315..1ad301eaaff 100644 --- a/env/fat.c +++ b/env/fat.c @@ -41,14 +41,12 @@ __weak const char *env_fat_get_intf(void) __weak char *env_fat_get_dev_part(void) { #ifdef CONFIG_MMC - static char *part_str; - - if (!part_str) { - part_str = CONFIG_ENV_FAT_DEVICE_AND_PART; - if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "mmc") && part_str[0] == ':') { - part_str = "0" CONFIG_ENV_FAT_DEVICE_AND_PART; - part_str[0] += mmc_get_env_dev(); - } + /* reserve one more char for the manipulation below */ + static char part_str[] = CONFIG_ENV_FAT_DEVICE_AND_PART "\0"; + + if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "mmc") && part_str[0] == ':') { + part_str[0] = '0' + mmc_get_env_dev(); + strcpy(&part_str[1], CONFIG_ENV_FAT_DEVICE_AND_PART); } return part_str; diff --git a/examples/api/Makefile b/examples/api/Makefile index 722c7e45904..be97b8015bd 100644 --- a/examples/api/Makefile +++ b/examples/api/Makefile @@ -5,26 +5,9 @@ # Provide symbol API_BUILD to signal that the API example is being built. KBUILD_CPPFLAGS += -DAPI_BUILD -ifeq ($(ARCH),powerpc) -LOAD_ADDR = 0x40000 -endif -ifeq ($(ARCH),arm) -ifdef CONFIG_64BIT -LOAD_ADDR = 0x40400000 -else -LOAD_ADDR = 0x1000000 -endif -endif -ifeq ($(ARCH),mips) -ifdef CONFIG_64BIT -LOAD_ADDR = 0xffffffff80200000 -else -LOAD_ADDR = 0x80200000 -endif -endif -ifeq ($(ARCH),riscv) -LOAD_ADDR = 0x84000000 -endif +# Environment variable loadaddr is set from CONFIG_SYS_LOAD_ADDR. +# Run the examples 4 MiB above this address. +LOAD_ADDR:=${shell printf 0x%X $$(( $(CONFIG_SYS_LOAD_ADDR) + 0x400000 ))} # Resulting ELF and binary exectuables will be named demo and demo.bin extra-y = demo diff --git a/examples/api/crt0.S b/examples/api/crt0.S index d2a97557817..6899ebf8ac2 100644 --- a/examples/api/crt0.S +++ b/examples/api/crt0.S @@ -29,15 +29,17 @@ syscall: .text .globl _start _start: - ldr ip, =search_hint - str sp, [ip] + ldr r4, =search_hint + mov r5, sp + str r5, [r4] b main .globl syscall syscall: - ldr ip, =syscall_ptr - ldr pc, [ip] + ldr r4, =syscall_ptr + ldr r4, [r4] + bx r4 #elif defined(CONFIG_ARM64) diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 559170dd5c9..9b57f1c0c66 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -7,6 +7,10 @@ extra-y := hello_world extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2 extra-$(CONFIG_PPC) += sched +# Environment variable loadaddr is set from CONFIG_SYS_LOAD_ADDR. +# Run the examples 4 MiB above this address. +LOAD_ADDR:=${shell printf 0x%X $$(( $(CONFIG_SYS_LOAD_ADDR) + 0x400000 ))} + # # Some versions of make do not handle trailing white spaces properly; # leading to build failures. The problem was found with GNU Make 3.80. @@ -46,7 +50,7 @@ endif # source file. ccflags-y += $(call cc-option,-fno-toplevel-reorder) -LDFLAGS_STANDALONE += -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) +LDFLAGS_STANDALONE += -Ttext $(LOAD_ADDR) ######################################################################### diff --git a/fs/ubifs/recovery.c b/fs/ubifs/recovery.c index 6b6884fb209..12c0575cc97 100644 --- a/fs/ubifs/recovery.c +++ b/fs/ubifs/recovery.c @@ -439,7 +439,6 @@ static void clean_buf(const struct ubifs_info *c, void **buf, int lnum, { int empty_offs, pad_len; - lnum = lnum; dbg_rcvry("cleaning corruption at %d:%d", lnum, *offs); ubifs_assert(!(*offs & 7)); diff --git a/fs/ubifs/scan.c b/fs/ubifs/scan.c index 7a6e46df5d9..2335e9e2d25 100644 --- a/fs/ubifs/scan.c +++ b/fs/ubifs/scan.c @@ -169,7 +169,6 @@ struct ubifs_scan_leb *ubifs_start_scan(const struct ubifs_info *c, int lnum, void ubifs_end_scan(const struct ubifs_info *c, struct ubifs_scan_leb *sleb, int lnum, int offs) { - lnum = lnum; dbg_scan("stop scanning LEB %d at offset %d", lnum, offs); ubifs_assert(offs % c->min_io_size == 0); diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index b6bca53db10..3fd5c772a1a 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -67,6 +67,9 @@ extern char __text_start[]; /* This marks the text region which must be relocated */ extern char __image_copy_start[], __image_copy_end[]; +/* This marks the rcode region used for SPL relocation */ +extern char _rcode_start[], _rcode_end[]; + extern char __bss_end[]; extern char __rel_dyn_start[], __rel_dyn_end[]; extern char _image_binary_end[]; @@ -77,4 +80,17 @@ extern char _image_binary_end[]; */ extern void _start(void); +#ifndef USE_HOSTCC +#if CONFIG_IS_ENABLED(RELOC_LOADER) +#define __rcode __section(".text.rcode") +#define __rdata __section(".text.rdata") +#else +#define __rcode +#define __rdata +#endif +#else +#define __rcode +#define __rdata +#endif + #endif /* _ASM_GENERIC_SECTIONS_H_ */ diff --git a/include/bloblist.h b/include/bloblist.h index 03d9862c0f1..98aacf52733 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -250,6 +250,24 @@ static inline void *bloblist_check_magic(ulong addr) return ptr; } +#if CONFIG_IS_ENABLED(BLOBLIST) +/** + * bloblist_get_blob() - Find a blob and get the size of it + * + * Searches the bloblist and returns the blob with the matching tag + * + * @tag: Tag to search for (enum bloblist_tag_t) + * @sizep: Size of the blob found + * Return: pointer to bloblist if found, or NULL if not found + */ +void *bloblist_get_blob(uint tag, int *sizep); +#else +static inline void *bloblist_get_blob(uint tag, int *sizep) +{ + return NULL; +} +#endif + /** * bloblist_find() - Find a blob * diff --git a/include/configs/mt7987.h b/include/configs/mt7987.h new file mode 100644 index 00000000000..18ed3c7a55b --- /dev/null +++ b/include/configs/mt7987.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for MediaTek MT7987 SoC + * + * Copyright (C) 2025 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#ifndef __MT7987_H +#define __MT7987_H + +#define CFG_MAX_MEM_MAPPED 0xC0000000 + +#endif diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 1e6b16b4e70..f91e62a2e47 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -15,22 +15,4 @@ #include "mv-common.h" -/* - * Environment variables configurations - */ -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ - -/* - * Default environment variables - */ - -#define CFG_EXTRA_ENV_SETTINGS "x_bootargs=console=ttyS0,115200 " \ - CONFIG_MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" - #endif /* _CONFIG_OPENRD_BASE_H */ diff --git a/include/configs/pxa1908.h b/include/configs/pxa1908.h new file mode 100644 index 00000000000..b0d6cdfeb76 --- /dev/null +++ b/include/configs/pxa1908.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 + * Duje Mihanović <duje.mihanovic@skole.hr> + */ + +#ifndef __PXA1908_H +#define __PXA1908_H + +#define CFG_SYS_SDRAM_BASE 0x1000000 +#define CFG_SYS_INIT_RAM_ADDR 0x10000000 +#define CFG_SYS_INIT_RAM_SIZE 0x4000 +#define CFG_SYS_NS16550_IER 0x40 +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_EXTRA_ENV_SETTINGS \ + "bootcmd=bootm $prevbl_initrd_start_addr\0" + +#endif diff --git a/include/configs/s4sk.h b/include/configs/s4sk.h new file mode 100644 index 00000000000..a1707359a39 --- /dev/null +++ b/include/configs/s4sk.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This file is S4SK board configuration. + * + * Copyright (C) 2024-2025 Renesas Electronics Corp. + */ + +#ifndef __S4SK_H +#define __S4SK_H + +#include "rcar-gen4-common.h" + +#endif /* __S4SK_H */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index bb0db7c5ca3..13941ba3589 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -179,6 +179,7 @@ #ifndef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ + "usb_pgood_delay=1000\0" \ BOOTENV #endif diff --git a/include/dt-bindings/clock/mediatek,mt7987-clk.h b/include/dt-bindings/clock/mediatek,mt7987-clk.h new file mode 100644 index 00000000000..c7472ef9ebb --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt7987-clk.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 MediaTek Inc. + * Author: Lu Tang <Lu.Tang@mediatek.com> + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#ifndef _DT_BINDINGS_CLK_MT7987_H +#define _DT_BINDINGS_CLK_MT7987_H + +/* INFRACFG */ + +#define CLK_INFRA_MUX_UART0_SEL 0 +#define CLK_INFRA_MUX_UART1_SEL 1 +#define CLK_INFRA_MUX_UART2_SEL 2 +#define CLK_INFRA_MUX_SPI0_SEL 3 +#define CLK_INFRA_MUX_SPI1_SEL 4 +#define CLK_INFRA_MUX_SPI2_BCK_SEL 5 +#define CLK_INFRA_PWM_BCK_SEL 6 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 7 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 8 +#define CLK_INFRA_66M_GPT_BCK 9 +#define CLK_INFRA_66M_PWM_HCK 10 +#define CLK_INFRA_66M_PWM_BCK 11 +#define CLK_INFRA_133M_CQDMA_BCK 12 +#define CLK_INFRA_66M_AUD_SLV_BCK 13 +#define CLK_INFRA_AUD_26M 14 +#define CLK_INFRA_AUD_L 15 +#define CLK_INFRA_AUD_AUD 16 +#define CLK_INFRA_AUD_EG2 17 +#define CLK_INFRA_DRAMC_F26M 18 +#define CLK_INFRA_133M_DBG_ACKM 19 +#define CLK_INFRA_66M_AP_DMA_BCK 20 +#define CLK_INFRA_MSDC200_SRC 21 +#define CLK_INFRA_66M_SEJ_BCK 22 +#define CLK_INFRA_PRE_CK_SEJ_F13M 23 +#define CLK_INFRA_66M_TRNG 24 +#define CLK_INFRA_26M_THERM_SYSTEM 25 +#define CLK_INFRA_I2C_BCK 26 +#define CLK_INFRA_66M_UART0_PCK 27 +#define CLK_INFRA_66M_UART1_PCK 28 +#define CLK_INFRA_66M_UART2_PCK 29 +#define CLK_INFRA_52M_UART0_CK 30 +#define CLK_INFRA_52M_UART1_CK 31 +#define CLK_INFRA_52M_UART2_CK 32 +#define CLK_INFRA_NFI 33 +#define CLK_INFRA_66M_NFI_HCK 34 +#define CLK_INFRA_104M_SPI0 35 +#define CLK_INFRA_104M_SPI1 36 +#define CLK_INFRA_104M_SPI2_BCK 37 +#define CLK_INFRA_66M_SPI0_HCK 38 +#define CLK_INFRA_66M_SPI1_HCK 39 +#define CLK_INFRA_66M_SPI2_HCK 40 +#define CLK_INFRA_66M_FLASHIF_AXI 41 +#define CLK_INFRA_RTC 42 +#define CLK_INFRA_26M_ADC_BCK 43 +#define CLK_INFRA_RC_ADC 44 +#define CLK_INFRA_MSDC400 45 +#define CLK_INFRA_MSDC2_HCK 46 +#define CLK_INFRA_133M_MSDC_0_HCK 47 +#define CLK_INFRA_66M_MSDC_0_HCK 48 +#define CLK_INFRA_133M_CPUM_BCK 49 +#define CLK_INFRA_BIST2FPC 50 +#define CLK_INFRA_I2C_X16W_MCK_CK_P1 51 +#define CLK_INFRA_I2C_X16W_PCK_CK_P1 52 +#define CLK_INFRA_133M_USB_HCK 53 +#define CLK_INFRA_133M_USB_HCK_CK_P1 54 +#define CLK_INFRA_66M_USB_HCK 55 +#define CLK_INFRA_66M_USB_HCK_CK_P1 56 +#define CLK_INFRA_USB_SYS_CK_P1 57 +#define CLK_INFRA_USB_CK_P1 58 +#define CLK_INFRA_USB_FRMCNT_CK_P1 59 +#define CLK_INFRA_USB_PIPE_CK_P1 60 +#define CLK_INFRA_USB_UTMI_CK_P1 61 +#define CLK_INFRA_USB_XHCI_CK_P1 62 +#define CLK_INFRA_PCIE_GFMUX_TL_P0 63 +#define CLK_INFRA_PCIE_GFMUX_TL_P1 64 +#define CLK_INFRA_PCIE_PIPE_P0 65 +#define CLK_INFRA_PCIE_PIPE_P1 66 +#define CLK_INFRA_133M_PCIE_CK_P0 67 +#define CLK_INFRA_133M_PCIE_CK_P1 68 +#define CLK_INFRA_PCIE_PERI_26M_CK_P0 69 +#define CLK_INFRA_PCIE_PERI_26M_CK_P1 70 +#define CLK_INFRA_NR_CLK 71 + +/* TOPCKGEN */ + +#define CLK_TOP_CB_M_D2 0 +#define CLK_TOP_CB_M_D3 1 +#define CLK_TOP_M_D3_D2 2 +#define CLK_TOP_CB_M_D4 3 +#define CLK_TOP_CB_M_D8 4 +#define CLK_TOP_M_D8_D2 5 +#define CLK_TOP_CB_APLL2_D4 6 +#define CLK_TOP_CB_NET1_D3 7 +#define CLK_TOP_CB_NET1_D4 8 +#define CLK_TOP_CB_NET1_D5 9 +#define CLK_TOP_NET1_D5_D2 10 +#define CLK_TOP_NET1_D5_D4 11 +#define CLK_TOP_CB_NET1_D7 12 +#define CLK_TOP_NET1_D7_D2 13 +#define CLK_TOP_NET1_D7_D4 14 +#define CLK_TOP_NET1_D8_D2 15 +#define CLK_TOP_NET1_D8_D4 16 +#define CLK_TOP_NET1_D8_D8 17 +#define CLK_TOP_NET1_D8_D16 18 +#define CLK_TOP_CB_NET2_D2 19 +#define CLK_TOP_CB_NET2_D4 20 +#define CLK_TOP_NET2_D4_D4 21 +#define CLK_TOP_NET2_D4_D8 22 +#define CLK_TOP_CB_NET2_D6 23 +#define CLK_TOP_NET2_D7_D2 24 +#define CLK_TOP_CB_NET2_D8 25 +#define CLK_TOP_MSDC_D2 26 +#define CLK_TOP_CB_CKSQ_40M 27 +#define CLK_TOP_CKSQ_40M_D2 28 +#define CLK_TOP_CB_RTC_32K 29 +#define CLK_TOP_CB_RTC_32P7K 30 +#define CLK_TOP_NETSYS_SEL 31 +#define CLK_TOP_NETSYS_500M_SEL 32 +#define CLK_TOP_NETSYS_2X_SEL 33 +#define CLK_TOP_ETH_GMII_SEL 34 +#define CLK_TOP_EIP_SEL 35 +#define CLK_TOP_AXI_INFRA_SEL 36 +#define CLK_TOP_UART_SEL 37 +#define CLK_TOP_EMMC_250M_SEL 38 +#define CLK_TOP_EMMC_400M_SEL 39 +#define CLK_TOP_SPI_SEL 40 +#define CLK_TOP_SPIM_MST_SEL 41 +#define CLK_TOP_NFI_SEL 42 +#define CLK_TOP_PWM_SEL 43 +#define CLK_TOP_I2C_SEL 44 +#define CLK_TOP_PCIE_MBIST_250M_SEL 45 +#define CLK_TOP_PEXTP_TL_SEL 46 +#define CLK_TOP_PEXTP_TL_P1_SEL 47 +#define CLK_TOP_USB_SYS_P1_SEL 48 +#define CLK_TOP_USB_XHCI_P1_SEL 49 +#define CLK_TOP_AUD_SEL 50 +#define CLK_TOP_A1SYS_SEL 51 +#define CLK_TOP_AUD_L_SEL 52 +#define CLK_TOP_A_TUNER_SEL 53 +#define CLK_TOP_USB_PHY_SEL 54 +#define CLK_TOP_SGM_0_SEL 55 +#define CLK_TOP_SGM_SBUS_0_SEL 56 +#define CLK_TOP_SGM_1_SEL 57 +#define CLK_TOP_SGM_SBUS_1_SEL 58 +#define CLK_TOP_SYSAXI_SEL 59 +#define CLK_TOP_SYSAPB_SEL 60 +#define CLK_TOP_ETH_REFCK_50M_SEL 61 +#define CLK_TOP_ETH_SYS_200M_SEL 62 +#define CLK_TOP_ETH_SYS_SEL 63 +#define CLK_TOP_ETH_XGMII_SEL 64 +#define CLK_TOP_DRAMC_SEL 65 +#define CLK_TOP_DRAMC_MD32_SEL 66 +#define CLK_TOP_INFRA_F26M_SEL 67 +#define CLK_TOP_PEXTP_P0_SEL 68 +#define CLK_TOP_PEXTP_P1_SEL 69 +#define CLK_TOP_DA_XTP_GLB_P0_SEL 70 +#define CLK_TOP_DA_XTP_GLB_P1_SEL 71 +#define CLK_TOP_CKM_SEL 72 +#define CLK_TOP_DA_CKM_XTAL_SEL 73 +#define CLK_TOP_PEXTP_SEL 74 +#define CLK_TOP_ETH_MII_SEL 75 +#define CLK_TOP_EMMC_200M_SEL 76 +#define CLK_TOP_AUD_I2S_M 77 +#define CLK_TOP_NR_CLK 78 + +/* APMIXEDSYS */ + +#define CLK_APMIXED_MPLL 0 +#define CLK_APMIXED_APLL2 1 +#define CLK_APMIXED_NET1PLL 2 +#define CLK_APMIXED_NET2PLL 3 +#define CLK_APMIXED_WEDMCUPLL 4 +#define CLK_APMIXED_SGMPLL 5 +#define CLK_APMIXED_ARM_LL 6 +#define CLK_APMIXED_MSDCPLL 7 +#define CLK_APMIXED_NR_CLK 8 + +/* MCUSYS */ + +#define CLK_MCU_BUS_DIV_SEL 0 +#define CLK_MCU_NR_CLK 1 + +/* SGMIISYS_0 */ + +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 +#define CLK_SGMII0_NR_CLK 2 + +/* SGMIISYS_1 */ + +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 +#define CLK_SGMII1_NR_CLK 2 + +/* ETHDMA */ + +#define CLK_ETHDMA_FE_EN 0 +#define CLK_ETHDMA_GP2_EN 1 +#define CLK_ETHDMA_GP1_EN 2 +#define CLK_ETHDMA_GP3_EN 3 +#define CLK_ETHDMA_NR_CLK 4 + +#endif /* _DT_BINDINGS_CLK_MT7987_H */ + diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h deleted file mode 100644 index e5dad050d51..00000000000 --- a/include/dt-bindings/clock/stm32fx-clock.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * stm32fx-clock.h - * - * Copyright (C) 2016 STMicroelectronics - * Author: Gabriel Fernandez for STMicroelectronics. - */ - -/* - * List of clocks which are not derived from system clock (SYSCLOCK) - * - * The index of these clocks is the secondary index of DT bindings - * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt) - * - * e.g: - <assigned-clocks = <&rcc 1 CLK_LSE>; -*/ - -#ifndef _DT_BINDINGS_CLK_STMFX_H -#define _DT_BINDINGS_CLK_STMFX_H - -#define SYSTICK 0 -#define FCLK 1 -#define CLK_LSI 2 -#define CLK_LSE 3 -#define CLK_HSE_RTC 4 -#define CLK_RTC 5 -#define PLL_VCO_I2S 6 -#define PLL_VCO_SAI 7 -#define CLK_LCD 8 -#define CLK_I2S 9 -#define CLK_SAI1 10 -#define CLK_SAI2 11 -#define CLK_I2SQ_PDIV 12 -#define CLK_SAIQ_PDIV 13 -#define CLK_HSI 14 -#define CLK_SYSCLK 15 -#define CLK_F469_DSI 16 - -#define END_PRIMARY_CLK 17 - -#define CLK_HDMI_CEC 16 -#define CLK_SPDIF 17 -#define CLK_USART1 18 -#define CLK_USART2 19 -#define CLK_USART3 20 -#define CLK_UART4 21 -#define CLK_UART5 22 -#define CLK_USART6 23 -#define CLK_UART7 24 -#define CLK_UART8 25 -#define CLK_I2C1 26 -#define CLK_I2C2 27 -#define CLK_I2C3 28 -#define CLK_I2C4 29 -#define CLK_LPTIMER 30 -#define CLK_PLL_SRC 31 -#define CLK_DFSDM1 32 -#define CLK_ADFSDM1 33 -#define CLK_F769_DSI 34 -#define END_PRIMARY_CLK_F7 35 - -#endif diff --git a/include/dt-bindings/clock/stm32h7-clks.h b/include/dt-bindings/clock/stm32h7-clks.h deleted file mode 100644 index 4d87e7ebc39..00000000000 --- a/include/dt-bindings/clock/stm32h7-clks.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SYS, CORE AND BUS CLOCKS */ -#define SYS_D1CPRE 0 -#define HCLK 1 -#define PCLK1 2 -#define PCLK2 3 -#define PCLK3 4 -#define PCLK4 5 -#define HSI_DIV 6 -#define HSE_1M 7 -#define I2S_CKIN 8 -#define CK_DSI_PHY 9 -#define HSE_CK 10 -#define LSE_CK 11 -#define CSI_KER_DIV122 12 -#define RTC_CK 13 -#define CPU_SYSTICK 14 - -/* OSCILLATOR BANK */ -#define OSC_BANK 18 -#define HSI_CK 18 -#define HSI_KER_CK 19 -#define CSI_CK 20 -#define CSI_KER_CK 21 -#define RC48_CK 22 -#define LSI_CK 23 - -/* MCLOCK BANK */ -#define MCLK_BANK 28 -#define PER_CK 28 -#define PLLSRC 29 -#define SYS_CK 30 -#define TRACEIN_CK 31 - -/* ODF BANK */ -#define ODF_BANK 32 -#define PLL1_P 32 -#define PLL1_Q 33 -#define PLL1_R 34 -#define PLL2_P 35 -#define PLL2_Q 36 -#define PLL2_R 37 -#define PLL3_P 38 -#define PLL3_Q 39 -#define PLL3_R 40 - -/* MCO BANK */ -#define MCO_BANK 41 -#define MCO1 41 -#define MCO2 42 - -/* PERIF BANK */ -#define PERIF_BANK 50 -#define D1SRAM1_CK 50 -#define ITCM_CK 51 -#define DTCM2_CK 52 -#define DTCM1_CK 53 -#define FLITF_CK 54 -#define JPGDEC_CK 55 -#define DMA2D_CK 56 -#define MDMA_CK 57 -#define USB2ULPI_CK 58 -#define USB1ULPI_CK 59 -#define ETH1RX_CK 60 -#define ETH1TX_CK 61 -#define ETH1MAC_CK 62 -#define ART_CK 63 -#define DMA2_CK 64 -#define DMA1_CK 65 -#define D2SRAM3_CK 66 -#define D2SRAM2_CK 67 -#define D2SRAM1_CK 68 -#define HASH_CK 69 -#define CRYPT_CK 70 -#define CAMITF_CK 71 -#define BKPRAM_CK 72 -#define HSEM_CK 73 -#define BDMA_CK 74 -#define CRC_CK 75 -#define GPIOK_CK 76 -#define GPIOJ_CK 77 -#define GPIOI_CK 78 -#define GPIOH_CK 79 -#define GPIOG_CK 80 -#define GPIOF_CK 81 -#define GPIOE_CK 82 -#define GPIOD_CK 83 -#define GPIOC_CK 84 -#define GPIOB_CK 85 -#define GPIOA_CK 86 -#define WWDG1_CK 87 -#define DAC12_CK 88 -#define WWDG2_CK 89 -#define TIM14_CK 90 -#define TIM13_CK 91 -#define TIM12_CK 92 -#define TIM7_CK 93 -#define TIM6_CK 94 -#define TIM5_CK 95 -#define TIM4_CK 96 -#define TIM3_CK 97 -#define TIM2_CK 98 -#define MDIOS_CK 99 -#define OPAMP_CK 100 -#define CRS_CK 101 -#define TIM17_CK 102 -#define TIM16_CK 103 -#define TIM15_CK 104 -#define TIM8_CK 105 -#define TIM1_CK 106 -#define TMPSENS_CK 107 -#define RTCAPB_CK 108 -#define VREF_CK 109 -#define COMP12_CK 110 -#define SYSCFG_CK 111 -/* must be equal to last peripheral clock index */ -#define LAST_PERIF_BANK SYSCFG_CK - -/* KERNEL BANK */ -#define KERN_BANK 120 -#define SDMMC1_CK 120 -#define QUADSPI_CK 121 -#define FMC_CK 122 -#define USB2OTG_CK 123 -#define USB1OTG_CK 124 -#define ADC12_CK 125 -#define SDMMC2_CK 126 -#define RNG_CK 127 -#define ADC3_CK 128 -#define DSI_CK 129 -#define LTDC_CK 130 -#define USART8_CK 131 -#define USART7_CK 132 -#define HDMICEC_CK 133 -#define I2C3_CK 134 -#define I2C2_CK 135 -#define I2C1_CK 136 -#define UART5_CK 137 -#define UART4_CK 138 -#define USART3_CK 139 -#define USART2_CK 140 -#define SPDIFRX_CK 141 -#define SPI3_CK 142 -#define SPI2_CK 143 -#define LPTIM1_CK 144 -#define FDCAN_CK 145 -#define SWP_CK 146 -#define HRTIM_CK 147 -#define DFSDM1_CK 148 -#define SAI3_CK 149 -#define SAI2_CK 150 -#define SAI1_CK 151 -#define SPI5_CK 152 -#define SPI4_CK 153 -#define SPI1_CK 154 -#define USART6_CK 155 -#define USART1_CK 156 -#define SAI4B_CK 157 -#define SAI4A_CK 158 -#define LPTIM5_CK 159 -#define LPTIM4_CK 160 -#define LPTIM3_CK 161 -#define LPTIM2_CK 162 -#define I2C4_CK 163 -#define SPI6_CK 164 -#define LPUART1_CK 165 - -#define STM32H7_MAX_CLKS 166 diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h deleted file mode 100644 index 0a5324bcdbd..00000000000 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ /dev/null @@ -1,274 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_ -#define _DT_BINDINGS_STM32MP1_CLKS_H_ - -/* OSCILLATOR clocks */ -#define CK_HSE 0 -#define CK_CSI 1 -#define CK_LSI 2 -#define CK_LSE 3 -#define CK_HSI 4 -#define CK_HSE_DIV2 5 - -/* Bus clocks */ -#define TIM2 6 -#define TIM3 7 -#define TIM4 8 -#define TIM5 9 -#define TIM6 10 -#define TIM7 11 -#define TIM12 12 -#define TIM13 13 -#define TIM14 14 -#define LPTIM1 15 -#define SPI2 16 -#define SPI3 17 -#define USART2 18 -#define USART3 19 -#define UART4 20 -#define UART5 21 -#define UART7 22 -#define UART8 23 -#define I2C1 24 -#define I2C2 25 -#define I2C3 26 -#define I2C5 27 -#define SPDIF 28 -#define CEC 29 -#define DAC12 30 -#define MDIO 31 -#define TIM1 32 -#define TIM8 33 -#define TIM15 34 -#define TIM16 35 -#define TIM17 36 -#define SPI1 37 -#define SPI4 38 -#define SPI5 39 -#define USART6 40 -#define SAI1 41 -#define SAI2 42 -#define SAI3 43 -#define DFSDM 44 -#define FDCAN 45 -#define LPTIM2 46 -#define LPTIM3 47 -#define LPTIM4 48 -#define LPTIM5 49 -#define SAI4 50 -#define SYSCFG 51 -#define VREF 52 -#define TMPSENS 53 -#define PMBCTRL 54 -#define HDP 55 -#define LTDC 56 -#define DSI 57 -#define IWDG2 58 -#define USBPHY 59 -#define STGENRO 60 -#define SPI6 61 -#define I2C4 62 -#define I2C6 63 -#define USART1 64 -#define RTCAPB 65 -#define TZC1 66 -#define TZPC 67 -#define IWDG1 68 -#define BSEC 69 -#define STGEN 70 -#define DMA1 71 -#define DMA2 72 -#define DMAMUX 73 -#define ADC12 74 -#define USBO 75 -#define SDMMC3 76 -#define DCMI 77 -#define CRYP2 78 -#define HASH2 79 -#define RNG2 80 -#define CRC2 81 -#define HSEM 82 -#define IPCC 83 -#define GPIOA 84 -#define GPIOB 85 -#define GPIOC 86 -#define GPIOD 87 -#define GPIOE 88 -#define GPIOF 89 -#define GPIOG 90 -#define GPIOH 91 -#define GPIOI 92 -#define GPIOJ 93 -#define GPIOK 94 -#define GPIOZ 95 -#define CRYP1 96 -#define HASH1 97 -#define RNG1 98 -#define BKPSRAM 99 -#define MDMA 100 -#define GPU 101 -#define ETHCK 102 -#define ETHTX 103 -#define ETHRX 104 -#define ETHMAC 105 -#define FMC 106 -#define QSPI 107 -#define SDMMC1 108 -#define SDMMC2 109 -#define CRC1 110 -#define USBH 111 -#define ETHSTP 112 -#define TZC2 113 - -/* Kernel clocks */ -#define SDMMC1_K 118 -#define SDMMC2_K 119 -#define SDMMC3_K 120 -#define FMC_K 121 -#define QSPI_K 122 -#define ETHCK_K 123 -#define RNG1_K 124 -#define RNG2_K 125 -#define GPU_K 126 -#define USBPHY_K 127 -#define STGEN_K 128 -#define SPDIF_K 129 -#define SPI1_K 130 -#define SPI2_K 131 -#define SPI3_K 132 -#define SPI4_K 133 -#define SPI5_K 134 -#define SPI6_K 135 -#define CEC_K 136 -#define I2C1_K 137 -#define I2C2_K 138 -#define I2C3_K 139 -#define I2C4_K 140 -#define I2C5_K 141 -#define I2C6_K 142 -#define LPTIM1_K 143 -#define LPTIM2_K 144 -#define LPTIM3_K 145 -#define LPTIM4_K 146 -#define LPTIM5_K 147 -#define USART1_K 148 -#define USART2_K 149 -#define USART3_K 150 -#define UART4_K 151 -#define UART5_K 152 -#define USART6_K 153 -#define UART7_K 154 -#define UART8_K 155 -#define DFSDM_K 156 -#define FDCAN_K 157 -#define SAI1_K 158 -#define SAI2_K 159 -#define SAI3_K 160 -#define SAI4_K 161 -#define ADC12_K 162 -#define DSI_K 163 -#define DSI_PX 164 -#define ADFSDM_K 165 -#define USBO_K 166 -#define LTDC_PX 167 -#define DAC12_K 168 -#define ETHPTP_K 169 - -/* PLL */ -#define PLL1 176 -#define PLL2 177 -#define PLL3 178 -#define PLL4 179 - -/* ODF */ -#define PLL1_P 180 -#define PLL1_Q 181 -#define PLL1_R 182 -#define PLL2_P 183 -#define PLL2_Q 184 -#define PLL2_R 185 -#define PLL3_P 186 -#define PLL3_Q 187 -#define PLL3_R 188 -#define PLL4_P 189 -#define PLL4_Q 190 -#define PLL4_R 191 - -/* AUX */ -#define RTC 192 - -/* MCLK */ -#define CK_PER 193 -#define CK_MPU 194 -#define CK_AXI 195 -#define CK_MCU 196 - -/* Time base */ -#define TIM2_K 197 -#define TIM3_K 198 -#define TIM4_K 199 -#define TIM5_K 200 -#define TIM6_K 201 -#define TIM7_K 202 -#define TIM12_K 203 -#define TIM13_K 204 -#define TIM14_K 205 -#define TIM1_K 206 -#define TIM8_K 207 -#define TIM15_K 208 -#define TIM16_K 209 -#define TIM17_K 210 - -/* MCO clocks */ -#define CK_MCO1 211 -#define CK_MCO2 212 - -/* TRACE & DEBUG clocks */ -#define CK_DBG 214 -#define CK_TRACE 215 - -/* DDR */ -#define DDRC1 220 -#define DDRC1LP 221 -#define DDRC2 222 -#define DDRC2LP 223 -#define DDRPHYC 224 -#define DDRPHYCLP 225 -#define DDRCAPB 226 -#define DDRCAPBLP 227 -#define AXIDCG 228 -#define DDRPHYCAPB 229 -#define DDRPHYCAPBLP 230 -#define DDRPERFM 231 - -#define STM32MP1_LAST_CLK 232 - -/* SCMI clock identifiers */ -#define CK_SCMI_HSE 0 -#define CK_SCMI_HSI 1 -#define CK_SCMI_CSI 2 -#define CK_SCMI_LSE 3 -#define CK_SCMI_LSI 4 -#define CK_SCMI_PLL2_Q 5 -#define CK_SCMI_PLL2_R 6 -#define CK_SCMI_MPU 7 -#define CK_SCMI_AXI 8 -#define CK_SCMI_BSEC 9 -#define CK_SCMI_CRYP1 10 -#define CK_SCMI_GPIOZ 11 -#define CK_SCMI_HASH1 12 -#define CK_SCMI_I2C4 13 -#define CK_SCMI_I2C6 14 -#define CK_SCMI_IWDG1 15 -#define CK_SCMI_RNG1 16 -#define CK_SCMI_RTC 17 -#define CK_SCMI_RTCAPB 18 -#define CK_SCMI_SPI6 19 -#define CK_SCMI_USART1 20 - -#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ diff --git a/include/dt-bindings/clock/stm32mp13-clks.h b/include/dt-bindings/clock/stm32mp13-clks.h deleted file mode 100644 index 0bd7b54c65f..00000000000 --- a/include/dt-bindings/clock/stm32mp13-clks.h +++ /dev/null @@ -1,229 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ -/* - * Copyright (C) STMicroelectronics 2020 - All Rights Reserved - * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_ -#define _DT_BINDINGS_STM32MP13_CLKS_H_ - -/* OSCILLATOR clocks */ -#define CK_HSE 0 -#define CK_CSI 1 -#define CK_LSI 2 -#define CK_LSE 3 -#define CK_HSI 4 -#define CK_HSE_DIV2 5 - -/* PLL */ -#define PLL1 6 -#define PLL2 7 -#define PLL3 8 -#define PLL4 9 - -/* ODF */ -#define PLL1_P 10 -#define PLL1_Q 11 -#define PLL1_R 12 -#define PLL2_P 13 -#define PLL2_Q 14 -#define PLL2_R 15 -#define PLL3_P 16 -#define PLL3_Q 17 -#define PLL3_R 18 -#define PLL4_P 19 -#define PLL4_Q 20 -#define PLL4_R 21 - -#define PCLK1 22 -#define PCLK2 23 -#define PCLK3 24 -#define PCLK4 25 -#define PCLK5 26 -#define PCLK6 27 - -/* SYSTEM CLOCK */ -#define CK_PER 28 -#define CK_MPU 29 -#define CK_AXI 30 -#define CK_MLAHB 31 - -/* BASE TIMER */ -#define CK_TIMG1 32 -#define CK_TIMG2 33 -#define CK_TIMG3 34 - -/* AUX */ -#define RTC 35 - -/* TRACE & DEBUG clocks */ -#define CK_DBG 36 -#define CK_TRACE 37 - -/* MCO clocks */ -#define CK_MCO1 38 -#define CK_MCO2 39 - -/* IP clocks */ -#define SYSCFG 40 -#define VREF 41 -#define DTS 42 -#define PMBCTRL 43 -#define HDP 44 -#define IWDG2 45 -#define STGENRO 46 -#define USART1 47 -#define RTCAPB 48 -#define TZC 49 -#define TZPC 50 -#define IWDG1 51 -#define BSEC 52 -#define DMA1 53 -#define DMA2 54 -#define DMAMUX1 55 -#define DMAMUX2 56 -#define GPIOA 57 -#define GPIOB 58 -#define GPIOC 59 -#define GPIOD 60 -#define GPIOE 61 -#define GPIOF 62 -#define GPIOG 63 -#define GPIOH 64 -#define GPIOI 65 -#define CRYP1 66 -#define HASH1 67 -#define BKPSRAM 68 -#define MDMA 69 -#define CRC1 70 -#define USBH 71 -#define DMA3 72 -#define TSC 73 -#define PKA 74 -#define AXIMC 75 -#define MCE 76 -#define ETH1TX 77 -#define ETH2TX 78 -#define ETH1RX 79 -#define ETH2RX 80 -#define ETH1MAC 81 -#define ETH2MAC 82 -#define ETH1STP 83 -#define ETH2STP 84 - -/* IP clocks with parents */ -#define SDMMC1_K 85 -#define SDMMC2_K 86 -#define ADC1_K 87 -#define ADC2_K 88 -#define FMC_K 89 -#define QSPI_K 90 -#define RNG1_K 91 -#define USBPHY_K 92 -#define STGEN_K 93 -#define SPDIF_K 94 -#define SPI1_K 95 -#define SPI2_K 96 -#define SPI3_K 97 -#define SPI4_K 98 -#define SPI5_K 99 -#define I2C1_K 100 -#define I2C2_K 101 -#define I2C3_K 102 -#define I2C4_K 103 -#define I2C5_K 104 -#define TIM2_K 105 -#define TIM3_K 106 -#define TIM4_K 107 -#define TIM5_K 108 -#define TIM6_K 109 -#define TIM7_K 110 -#define TIM12_K 111 -#define TIM13_K 112 -#define TIM14_K 113 -#define TIM1_K 114 -#define TIM8_K 115 -#define TIM15_K 116 -#define TIM16_K 117 -#define TIM17_K 118 -#define LPTIM1_K 119 -#define LPTIM2_K 120 -#define LPTIM3_K 121 -#define LPTIM4_K 122 -#define LPTIM5_K 123 -#define USART1_K 124 -#define USART2_K 125 -#define USART3_K 126 -#define UART4_K 127 -#define UART5_K 128 -#define USART6_K 129 -#define UART7_K 130 -#define UART8_K 131 -#define DFSDM_K 132 -#define FDCAN_K 133 -#define SAI1_K 134 -#define SAI2_K 135 -#define ADFSDM_K 136 -#define USBO_K 137 -#define LTDC_PX 138 -#define ETH1CK_K 139 -#define ETH1PTP_K 140 -#define ETH2CK_K 141 -#define ETH2PTP_K 142 -#define DCMIPP_K 143 -#define SAES_K 144 -#define DTS_K 145 - -/* DDR */ -#define DDRC1 146 -#define DDRC1LP 147 -#define DDRC2 148 -#define DDRC2LP 149 -#define DDRPHYC 150 -#define DDRPHYCLP 151 -#define DDRCAPB 152 -#define DDRCAPBLP 153 -#define AXIDCG 154 -#define DDRPHYCAPB 155 -#define DDRPHYCAPBLP 156 -#define DDRPERFM 157 - -#define ADC1 158 -#define ADC2 159 -#define SAI1 160 -#define SAI2 161 - -#define STM32MP1_LAST_CLK 162 - -/* SCMI clock identifiers */ -#define CK_SCMI_HSE 0 -#define CK_SCMI_HSI 1 -#define CK_SCMI_CSI 2 -#define CK_SCMI_LSE 3 -#define CK_SCMI_LSI 4 -#define CK_SCMI_HSE_DIV2 5 -#define CK_SCMI_PLL2_Q 6 -#define CK_SCMI_PLL2_R 7 -#define CK_SCMI_PLL3_P 8 -#define CK_SCMI_PLL3_Q 9 -#define CK_SCMI_PLL3_R 10 -#define CK_SCMI_PLL4_P 11 -#define CK_SCMI_PLL4_Q 12 -#define CK_SCMI_PLL4_R 13 -#define CK_SCMI_MPU 14 -#define CK_SCMI_AXI 15 -#define CK_SCMI_MLAHB 16 -#define CK_SCMI_CKPER 17 -#define CK_SCMI_PCLK1 18 -#define CK_SCMI_PCLK2 19 -#define CK_SCMI_PCLK3 20 -#define CK_SCMI_PCLK4 21 -#define CK_SCMI_PCLK5 22 -#define CK_SCMI_PCLK6 23 -#define CK_SCMI_CKTIMG1 24 -#define CK_SCMI_CKTIMG2 25 -#define CK_SCMI_CKTIMG3 26 -#define CK_SCMI_RTC 27 -#define CK_SCMI_RTCAPB 28 - -#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */ diff --git a/include/dt-bindings/mfd/stm32f4-rcc.h b/include/dt-bindings/mfd/stm32f4-rcc.h deleted file mode 100644 index 36448a5619a..00000000000 --- a/include/dt-bindings/mfd/stm32f4-rcc.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the STM32F4 RCC IP - */ - -#ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H -#define _DT_BINDINGS_MFD_STM32F4_RCC_H - -/* AHB1 */ -#define STM32F4_RCC_AHB1_GPIOA 0 -#define STM32F4_RCC_AHB1_GPIOB 1 -#define STM32F4_RCC_AHB1_GPIOC 2 -#define STM32F4_RCC_AHB1_GPIOD 3 -#define STM32F4_RCC_AHB1_GPIOE 4 -#define STM32F4_RCC_AHB1_GPIOF 5 -#define STM32F4_RCC_AHB1_GPIOG 6 -#define STM32F4_RCC_AHB1_GPIOH 7 -#define STM32F4_RCC_AHB1_GPIOI 8 -#define STM32F4_RCC_AHB1_GPIOJ 9 -#define STM32F4_RCC_AHB1_GPIOK 10 -#define STM32F4_RCC_AHB1_CRC 12 -#define STM32F4_RCC_AHB1_BKPSRAM 18 -#define STM32F4_RCC_AHB1_CCMDATARAM 20 -#define STM32F4_RCC_AHB1_DMA1 21 -#define STM32F4_RCC_AHB1_DMA2 22 -#define STM32F4_RCC_AHB1_DMA2D 23 -#define STM32F4_RCC_AHB1_ETHMAC 25 -#define STM32F4_RCC_AHB1_ETHMACTX 26 -#define STM32F4_RCC_AHB1_ETHMACRX 27 -#define STM32F4_RCC_AHB1_ETHMACPTP 28 -#define STM32F4_RCC_AHB1_OTGHS 29 -#define STM32F4_RCC_AHB1_OTGHSULPI 30 - -#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) -#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) - -/* AHB2 */ -#define STM32F4_RCC_AHB2_DCMI 0 -#define STM32F4_RCC_AHB2_CRYP 4 -#define STM32F4_RCC_AHB2_HASH 5 -#define STM32F4_RCC_AHB2_RNG 6 -#define STM32F4_RCC_AHB2_OTGFS 7 - -#define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) -#define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) - -/* AHB3 */ -#define STM32F4_RCC_AHB3_FMC 0 -#define STM32F4_RCC_AHB3_QSPI 1 - -#define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) -#define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) - -/* APB1 */ -#define STM32F4_RCC_APB1_TIM2 0 -#define STM32F4_RCC_APB1_TIM3 1 -#define STM32F4_RCC_APB1_TIM4 2 -#define STM32F4_RCC_APB1_TIM5 3 -#define STM32F4_RCC_APB1_TIM6 4 -#define STM32F4_RCC_APB1_TIM7 5 -#define STM32F4_RCC_APB1_TIM12 6 -#define STM32F4_RCC_APB1_TIM13 7 -#define STM32F4_RCC_APB1_TIM14 8 -#define STM32F4_RCC_APB1_WWDG 11 -#define STM32F4_RCC_APB1_SPI2 14 -#define STM32F4_RCC_APB1_SPI3 15 -#define STM32F4_RCC_APB1_UART2 17 -#define STM32F4_RCC_APB1_UART3 18 -#define STM32F4_RCC_APB1_UART4 19 -#define STM32F4_RCC_APB1_UART5 20 -#define STM32F4_RCC_APB1_I2C1 21 -#define STM32F4_RCC_APB1_I2C2 22 -#define STM32F4_RCC_APB1_I2C3 23 -#define STM32F4_RCC_APB1_CAN1 25 -#define STM32F4_RCC_APB1_CAN2 26 -#define STM32F4_RCC_APB1_PWR 28 -#define STM32F4_RCC_APB1_DAC 29 -#define STM32F4_RCC_APB1_UART7 30 -#define STM32F4_RCC_APB1_UART8 31 - -#define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) -#define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) - -/* APB2 */ -#define STM32F4_RCC_APB2_TIM1 0 -#define STM32F4_RCC_APB2_TIM8 1 -#define STM32F4_RCC_APB2_USART1 4 -#define STM32F4_RCC_APB2_USART6 5 -#define STM32F4_RCC_APB2_ADC1 8 -#define STM32F4_RCC_APB2_ADC2 9 -#define STM32F4_RCC_APB2_ADC3 10 -#define STM32F4_RCC_APB2_SDIO 11 -#define STM32F4_RCC_APB2_SPI1 12 -#define STM32F4_RCC_APB2_SPI4 13 -#define STM32F4_RCC_APB2_SYSCFG 14 -#define STM32F4_RCC_APB2_TIM9 16 -#define STM32F4_RCC_APB2_TIM10 17 -#define STM32F4_RCC_APB2_TIM11 18 -#define STM32F4_RCC_APB2_SPI5 20 -#define STM32F4_RCC_APB2_SPI6 21 -#define STM32F4_RCC_APB2_SAI1 22 -#define STM32F4_RCC_APB2_LTDC 26 -#define STM32F4_RCC_APB2_DSI 27 - -#define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) -#define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) - -#endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */ diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h deleted file mode 100644 index 1aa267e76a5..00000000000 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ /dev/null @@ -1,115 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the STM32F7 RCC IP - */ - -#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H -#define _DT_BINDINGS_MFD_STM32F7_RCC_H - -/* AHB1 */ -#define STM32F7_RCC_AHB1_GPIOA 0 -#define STM32F7_RCC_AHB1_GPIOB 1 -#define STM32F7_RCC_AHB1_GPIOC 2 -#define STM32F7_RCC_AHB1_GPIOD 3 -#define STM32F7_RCC_AHB1_GPIOE 4 -#define STM32F7_RCC_AHB1_GPIOF 5 -#define STM32F7_RCC_AHB1_GPIOG 6 -#define STM32F7_RCC_AHB1_GPIOH 7 -#define STM32F7_RCC_AHB1_GPIOI 8 -#define STM32F7_RCC_AHB1_GPIOJ 9 -#define STM32F7_RCC_AHB1_GPIOK 10 -#define STM32F7_RCC_AHB1_CRC 12 -#define STM32F7_RCC_AHB1_BKPSRAM 18 -#define STM32F7_RCC_AHB1_DTCMRAM 20 -#define STM32F7_RCC_AHB1_DMA1 21 -#define STM32F7_RCC_AHB1_DMA2 22 -#define STM32F7_RCC_AHB1_DMA2D 23 -#define STM32F7_RCC_AHB1_ETHMAC 25 -#define STM32F7_RCC_AHB1_ETHMACTX 26 -#define STM32F7_RCC_AHB1_ETHMACRX 27 -#define STM32FF_RCC_AHB1_ETHMACPTP 28 -#define STM32F7_RCC_AHB1_OTGHS 29 -#define STM32F7_RCC_AHB1_OTGHSULPI 30 - -#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) -#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) - -/* AHB2 */ -#define STM32F7_RCC_AHB2_DCMI 0 -#define STM32F7_RCC_AHB2_CRYP 4 -#define STM32F7_RCC_AHB2_HASH 5 -#define STM32F7_RCC_AHB2_RNG 6 -#define STM32F7_RCC_AHB2_OTGFS 7 - -#define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) -#define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) - -/* AHB3 */ -#define STM32F7_RCC_AHB3_FMC 0 -#define STM32F7_RCC_AHB3_QSPI 1 - -#define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) -#define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) - -/* APB1 */ -#define STM32F7_RCC_APB1_TIM2 0 -#define STM32F7_RCC_APB1_TIM3 1 -#define STM32F7_RCC_APB1_TIM4 2 -#define STM32F7_RCC_APB1_TIM5 3 -#define STM32F7_RCC_APB1_TIM6 4 -#define STM32F7_RCC_APB1_TIM7 5 -#define STM32F7_RCC_APB1_TIM12 6 -#define STM32F7_RCC_APB1_TIM13 7 -#define STM32F7_RCC_APB1_TIM14 8 -#define STM32F7_RCC_APB1_LPTIM1 9 -#define STM32F7_RCC_APB1_WWDG 11 -#define STM32F7_RCC_APB1_CAN3 13 -#define STM32F7_RCC_APB1_SPI2 14 -#define STM32F7_RCC_APB1_SPI3 15 -#define STM32F7_RCC_APB1_SPDIFRX 16 -#define STM32F7_RCC_APB1_UART2 17 -#define STM32F7_RCC_APB1_UART3 18 -#define STM32F7_RCC_APB1_UART4 19 -#define STM32F7_RCC_APB1_UART5 20 -#define STM32F7_RCC_APB1_I2C1 21 -#define STM32F7_RCC_APB1_I2C2 22 -#define STM32F7_RCC_APB1_I2C3 23 -#define STM32F7_RCC_APB1_I2C4 24 -#define STM32F7_RCC_APB1_CAN1 25 -#define STM32F7_RCC_APB1_CAN2 26 -#define STM32F7_RCC_APB1_CEC 27 -#define STM32F7_RCC_APB1_PWR 28 -#define STM32F7_RCC_APB1_DAC 29 -#define STM32F7_RCC_APB1_UART7 30 -#define STM32F7_RCC_APB1_UART8 31 - -#define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) -#define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80) - -/* APB2 */ -#define STM32F7_RCC_APB2_TIM1 0 -#define STM32F7_RCC_APB2_TIM8 1 -#define STM32F7_RCC_APB2_USART1 4 -#define STM32F7_RCC_APB2_USART6 5 -#define STM32F7_RCC_APB2_SDMMC2 7 -#define STM32F7_RCC_APB2_ADC1 8 -#define STM32F7_RCC_APB2_ADC2 9 -#define STM32F7_RCC_APB2_ADC3 10 -#define STM32F7_RCC_APB2_SDMMC1 11 -#define STM32F7_RCC_APB2_SPI1 12 -#define STM32F7_RCC_APB2_SPI4 13 -#define STM32F7_RCC_APB2_SYSCFG 14 -#define STM32F7_RCC_APB2_TIM9 16 -#define STM32F7_RCC_APB2_TIM10 17 -#define STM32F7_RCC_APB2_TIM11 18 -#define STM32F7_RCC_APB2_SPI5 20 -#define STM32F7_RCC_APB2_SPI6 21 -#define STM32F7_RCC_APB2_SAI1 22 -#define STM32F7_RCC_APB2_SAI2 23 -#define STM32F7_RCC_APB2_LTDC 26 -#define STM32F7_RCC_APB2_DSI 27 - -#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) -#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) - -#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */ diff --git a/include/dt-bindings/mfd/stm32h7-rcc.h b/include/dt-bindings/mfd/stm32h7-rcc.h deleted file mode 100644 index 06e8476bf08..00000000000 --- a/include/dt-bindings/mfd/stm32h7-rcc.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This header provides constants for the STM32H7 RCC IP - */ - -#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H -#define _DT_BINDINGS_MFD_STM32H7_RCC_H - -/* AHB3 */ -#define STM32H7_RCC_AHB3_MDMA 0 -#define STM32H7_RCC_AHB3_DMA2D 4 -#define STM32H7_RCC_AHB3_JPGDEC 5 -#define STM32H7_RCC_AHB3_FMC 12 -#define STM32H7_RCC_AHB3_QUADSPI 14 -#define STM32H7_RCC_AHB3_SDMMC1 16 -#define STM32H7_RCC_AHB3_CPU 31 -#define STM32H7_RCC_AHB3_CPU1 31 - -#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) - -/* AHB1 */ -#define STM32H7_RCC_AHB1_DMA1 0 -#define STM32H7_RCC_AHB1_DMA2 1 -#define STM32H7_RCC_AHB1_ADC12 5 -#define STM32H7_RCC_AHB1_ART 14 -#define STM32H7_RCC_AHB1_ETH1MAC 15 -#define STM32H7_RCC_AHB1_USB1OTG 25 -#define STM32H7_RCC_AHB1_USB2OTG 27 -#define STM32H7_RCC_AHB1_CPU2 31 - -#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8)) - -/* AHB2 */ -#define STM32H7_RCC_AHB2_CAMITF 0 -#define STM32H7_RCC_AHB2_CRYPT 4 -#define STM32H7_RCC_AHB2_HASH 5 -#define STM32H7_RCC_AHB2_RNG 6 -#define STM32H7_RCC_AHB2_SDMMC2 9 - -#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8)) - -/* AHB4 */ -#define STM32H7_RCC_AHB4_GPIOA 0 -#define STM32H7_RCC_AHB4_GPIOB 1 -#define STM32H7_RCC_AHB4_GPIOC 2 -#define STM32H7_RCC_AHB4_GPIOD 3 -#define STM32H7_RCC_AHB4_GPIOE 4 -#define STM32H7_RCC_AHB4_GPIOF 5 -#define STM32H7_RCC_AHB4_GPIOG 6 -#define STM32H7_RCC_AHB4_GPIOH 7 -#define STM32H7_RCC_AHB4_GPIOI 8 -#define STM32H7_RCC_AHB4_GPIOJ 9 -#define STM32H7_RCC_AHB4_GPIOK 10 -#define STM32H7_RCC_AHB4_CRC 19 -#define STM32H7_RCC_AHB4_BDMA 21 -#define STM32H7_RCC_AHB4_ADC3 24 -#define STM32H7_RCC_AHB4_HSEM 25 - -#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) - -/* APB3 */ -#define STM32H7_RCC_APB3_LTDC 3 -#define STM32H7_RCC_APB3_DSI 4 - -#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8)) - -/* APB1L */ -#define STM32H7_RCC_APB1L_TIM2 0 -#define STM32H7_RCC_APB1L_TIM3 1 -#define STM32H7_RCC_APB1L_TIM4 2 -#define STM32H7_RCC_APB1L_TIM5 3 -#define STM32H7_RCC_APB1L_TIM6 4 -#define STM32H7_RCC_APB1L_TIM7 5 -#define STM32H7_RCC_APB1L_TIM12 6 -#define STM32H7_RCC_APB1L_TIM13 7 -#define STM32H7_RCC_APB1L_TIM14 8 -#define STM32H7_RCC_APB1L_LPTIM1 9 -#define STM32H7_RCC_APB1L_SPI2 14 -#define STM32H7_RCC_APB1L_SPI3 15 -#define STM32H7_RCC_APB1L_SPDIF_RX 16 -#define STM32H7_RCC_APB1L_USART2 17 -#define STM32H7_RCC_APB1L_USART3 18 -#define STM32H7_RCC_APB1L_UART4 19 -#define STM32H7_RCC_APB1L_UART5 20 -#define STM32H7_RCC_APB1L_I2C1 21 -#define STM32H7_RCC_APB1L_I2C2 22 -#define STM32H7_RCC_APB1L_I2C3 23 -#define STM32H7_RCC_APB1L_HDMICEC 27 -#define STM32H7_RCC_APB1L_DAC12 29 -#define STM32H7_RCC_APB1L_USART7 30 -#define STM32H7_RCC_APB1L_USART8 31 - -#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8)) - -/* APB1H */ -#define STM32H7_RCC_APB1H_CRS 1 -#define STM32H7_RCC_APB1H_SWP 2 -#define STM32H7_RCC_APB1H_OPAMP 4 -#define STM32H7_RCC_APB1H_MDIOS 5 -#define STM32H7_RCC_APB1H_FDCAN 8 - -#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8)) - -/* APB2 */ -#define STM32H7_RCC_APB2_TIM1 0 -#define STM32H7_RCC_APB2_TIM8 1 -#define STM32H7_RCC_APB2_USART1 4 -#define STM32H7_RCC_APB2_USART6 5 -#define STM32H7_RCC_APB2_SPI1 12 -#define STM32H7_RCC_APB2_SPI4 13 -#define STM32H7_RCC_APB2_TIM15 16 -#define STM32H7_RCC_APB2_TIM16 17 -#define STM32H7_RCC_APB2_TIM17 18 -#define STM32H7_RCC_APB2_SPI5 20 -#define STM32H7_RCC_APB2_SAI1 22 -#define STM32H7_RCC_APB2_SAI2 23 -#define STM32H7_RCC_APB2_SAI3 24 -#define STM32H7_RCC_APB2_DFSDM1 28 -#define STM32H7_RCC_APB2_HRTIM 29 - -#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8)) - -/* APB4 */ -#define STM32H7_RCC_APB4_SYSCFG 1 -#define STM32H7_RCC_APB4_LPUART1 3 -#define STM32H7_RCC_APB4_SPI6 5 -#define STM32H7_RCC_APB4_I2C4 7 -#define STM32H7_RCC_APB4_LPTIM2 9 -#define STM32H7_RCC_APB4_LPTIM3 10 -#define STM32H7_RCC_APB4_LPTIM4 11 -#define STM32H7_RCC_APB4_LPTIM5 12 -#define STM32H7_RCC_APB4_COMP12 14 -#define STM32H7_RCC_APB4_VREF 15 -#define STM32H7_RCC_APB4_SAI4 21 -#define STM32H7_RCC_APB4_TMPSENS 26 - -#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8)) - -#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */ diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h deleted file mode 100644 index 28ad0235086..00000000000 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (C) STMicroelectronics 2017 - All Rights Reserved - * Author: Torgue Alexandre <alexandre.torgue@st.com> for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32_PINFUNC_H -#define _DT_BINDINGS_STM32_PINFUNC_H - -/* define PIN modes */ -#define GPIO 0x0 -#define AF0 0x1 -#define AF1 0x2 -#define AF2 0x3 -#define AF3 0x4 -#define AF4 0x5 -#define AF5 0x6 -#define AF6 0x7 -#define AF7 0x8 -#define AF8 0x9 -#define AF9 0xa -#define AF10 0xb -#define AF11 0xc -#define AF12 0xd -#define AF13 0xe -#define AF14 0xf -#define AF15 0x10 -#define ANALOG 0x11 - -/* define Pins number*/ -#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line)) - -#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode)) - -/* package information */ -#define STM32MP_PKG_AA 0x1 -#define STM32MP_PKG_AB 0x2 -#define STM32MP_PKG_AC 0x4 -#define STM32MP_PKG_AD 0x8 -#define STM32MP_PKG_AI 0x100 -#define STM32MP_PKG_AK 0x400 -#define STM32MP_PKG_AL 0x800 - -#endif /* _DT_BINDINGS_STM32_PINFUNC_H */ - diff --git a/include/dt-bindings/regulator/st,stm32mp13-regulator.h b/include/dt-bindings/regulator/st,stm32mp13-regulator.h deleted file mode 100644 index b3a974dfc58..00000000000 --- a/include/dt-bindings/regulator/st,stm32mp13-regulator.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ -/* - * Copyright (C) 2022, STMicroelectronics - All Rights Reserved - */ - -#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H -#define __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H - -/* SCMI voltage domains identifiers */ - -/* SOC Internal regulators */ -#define VOLTD_SCMI_REG11 0 -#define VOLTD_SCMI_REG18 1 -#define VOLTD_SCMI_USB33 2 -#define VOLTD_SCMI_SDMMC1_IO 3 -#define VOLTD_SCMI_SDMMC2_IO 4 -#define VOLTD_SCMI_VREFBUF 5 - -/* STPMIC1 regulators */ -#define VOLTD_SCMI_STPMIC1_BUCK1 6 -#define VOLTD_SCMI_STPMIC1_BUCK2 7 -#define VOLTD_SCMI_STPMIC1_BUCK3 8 -#define VOLTD_SCMI_STPMIC1_BUCK4 9 -#define VOLTD_SCMI_STPMIC1_LDO1 10 -#define VOLTD_SCMI_STPMIC1_LDO2 11 -#define VOLTD_SCMI_STPMIC1_LDO3 12 -#define VOLTD_SCMI_STPMIC1_LDO4 13 -#define VOLTD_SCMI_STPMIC1_LDO5 14 -#define VOLTD_SCMI_STPMIC1_LDO6 15 -#define VOLTD_SCMI_STPMIC1_VREFDDR 16 -#define VOLTD_SCMI_STPMIC1_BOOST 17 -#define VOLTD_SCMI_STPMIC1_PWR_SW1 18 -#define VOLTD_SCMI_STPMIC1_PWR_SW2 19 - -/* External regulators */ -#define VOLTD_SCMI_REGU0 20 -#define VOLTD_SCMI_REGU1 21 -#define VOLTD_SCMI_REGU2 22 -#define VOLTD_SCMI_REGU3 23 -#define VOLTD_SCMI_REGU4 24 - -#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H */ diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h deleted file mode 100644 index 9071f139649..00000000000 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32MP1_RESET_H_ -#define _DT_BINDINGS_STM32MP1_RESET_H_ - -#define MCU_HOLD_BOOT_R 2144 -#define LTDC_R 3072 -#define DSI_R 3076 -#define DDRPERFM_R 3080 -#define USBPHY_R 3088 -#define SPI6_R 3136 -#define I2C4_R 3138 -#define I2C6_R 3139 -#define USART1_R 3140 -#define STGEN_R 3156 -#define GPIOZ_R 3200 -#define CRYP1_R 3204 -#define HASH1_R 3205 -#define RNG1_R 3206 -#define AXIM_R 3216 -#define GPU_R 3269 -#define ETHMAC_R 3274 -#define FMC_R 3276 -#define QSPI_R 3278 -#define SDMMC1_R 3280 -#define SDMMC2_R 3281 -#define CRC1_R 3284 -#define USBH_R 3288 -#define MDMA_R 3328 -#define MCU_R 8225 -#define TIM2_R 19456 -#define TIM3_R 19457 -#define TIM4_R 19458 -#define TIM5_R 19459 -#define TIM6_R 19460 -#define TIM7_R 19461 -#define TIM12_R 16462 -#define TIM13_R 16463 -#define TIM14_R 16464 -#define LPTIM1_R 19465 -#define SPI2_R 19467 -#define SPI3_R 19468 -#define USART2_R 19470 -#define USART3_R 19471 -#define UART4_R 19472 -#define UART5_R 19473 -#define UART7_R 19474 -#define UART8_R 19475 -#define I2C1_R 19477 -#define I2C2_R 19478 -#define I2C3_R 19479 -#define I2C5_R 19480 -#define SPDIF_R 19482 -#define CEC_R 19483 -#define DAC12_R 19485 -#define MDIO_R 19847 -#define TIM1_R 19520 -#define TIM8_R 19521 -#define TIM15_R 19522 -#define TIM16_R 19523 -#define TIM17_R 19524 -#define SPI1_R 19528 -#define SPI4_R 19529 -#define SPI5_R 19530 -#define USART6_R 19533 -#define SAI1_R 19536 -#define SAI2_R 19537 -#define SAI3_R 19538 -#define DFSDM_R 19540 -#define FDCAN_R 19544 -#define LPTIM2_R 19584 -#define LPTIM3_R 19585 -#define LPTIM4_R 19586 -#define LPTIM5_R 19587 -#define SAI4_R 19592 -#define SYSCFG_R 19595 -#define VREF_R 19597 -#define TMPSENS_R 19600 -#define PMBCTRL_R 19601 -#define DMA1_R 19648 -#define DMA2_R 19649 -#define DMAMUX_R 19650 -#define ADC12_R 19653 -#define USBO_R 19656 -#define SDMMC3_R 19664 -#define CAMITF_R 19712 -#define CRYP2_R 19716 -#define HASH2_R 19717 -#define RNG2_R 19718 -#define CRC2_R 19719 -#define HSEM_R 19723 -#define MBOX_R 19724 -#define GPIOA_R 19776 -#define GPIOB_R 19777 -#define GPIOC_R 19778 -#define GPIOD_R 19779 -#define GPIOE_R 19780 -#define GPIOF_R 19781 -#define GPIOG_R 19782 -#define GPIOH_R 19783 -#define GPIOI_R 19784 -#define GPIOJ_R 19785 -#define GPIOK_R 19786 - -/* SCMI reset domain identifiers */ -#define RST_SCMI_SPI6 0 -#define RST_SCMI_I2C4 1 -#define RST_SCMI_I2C6 2 -#define RST_SCMI_USART1 3 -#define RST_SCMI_STGEN 4 -#define RST_SCMI_GPIOZ 5 -#define RST_SCMI_CRYP1 6 -#define RST_SCMI_HASH1 7 -#define RST_SCMI_RNG1 8 -#define RST_SCMI_MDMA 9 -#define RST_SCMI_MCU 10 -#define RST_SCMI_MCU_HOLD_BOOT 11 - -#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ diff --git a/include/dt-bindings/reset/stm32mp13-resets.h b/include/dt-bindings/reset/stm32mp13-resets.h deleted file mode 100644 index ecb37c7ddde..00000000000 --- a/include/dt-bindings/reset/stm32mp13-resets.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32MP13_RESET_H_ -#define _DT_BINDINGS_STM32MP13_RESET_H_ - -#define TIM2_R 13568 -#define TIM3_R 13569 -#define TIM4_R 13570 -#define TIM5_R 13571 -#define TIM6_R 13572 -#define TIM7_R 13573 -#define LPTIM1_R 13577 -#define SPI2_R 13579 -#define SPI3_R 13580 -#define USART3_R 13583 -#define UART4_R 13584 -#define UART5_R 13585 -#define UART7_R 13586 -#define UART8_R 13587 -#define I2C1_R 13589 -#define I2C2_R 13590 -#define SPDIF_R 13594 -#define TIM1_R 13632 -#define TIM8_R 13633 -#define SPI1_R 13640 -#define USART6_R 13645 -#define SAI1_R 13648 -#define SAI2_R 13649 -#define DFSDM_R 13652 -#define FDCAN_R 13656 -#define LPTIM2_R 13696 -#define LPTIM3_R 13697 -#define LPTIM4_R 13698 -#define LPTIM5_R 13699 -#define SYSCFG_R 13707 -#define VREF_R 13709 -#define DTS_R 13712 -#define PMBCTRL_R 13713 -#define LTDC_R 13760 -#define DCMIPP_R 13761 -#define DDRPERFM_R 13768 -#define USBPHY_R 13776 -#define STGEN_R 13844 -#define USART1_R 13888 -#define USART2_R 13889 -#define SPI4_R 13890 -#define SPI5_R 13891 -#define I2C3_R 13892 -#define I2C4_R 13893 -#define I2C5_R 13894 -#define TIM12_R 13895 -#define TIM13_R 13896 -#define TIM14_R 13897 -#define TIM15_R 13898 -#define TIM16_R 13899 -#define TIM17_R 13900 -#define DMA1_R 13952 -#define DMA2_R 13953 -#define DMAMUX1_R 13954 -#define DMA3_R 13955 -#define DMAMUX2_R 13956 -#define ADC1_R 13957 -#define ADC2_R 13958 -#define USBO_R 13960 -#define GPIOA_R 14080 -#define GPIOB_R 14081 -#define GPIOC_R 14082 -#define GPIOD_R 14083 -#define GPIOE_R 14084 -#define GPIOF_R 14085 -#define GPIOG_R 14086 -#define GPIOH_R 14087 -#define GPIOI_R 14088 -#define TSC_R 14095 -#define PKA_R 14146 -#define SAES_R 14147 -#define CRYP1_R 14148 -#define HASH1_R 14149 -#define RNG1_R 14150 -#define AXIMC_R 14160 -#define MDMA_R 14208 -#define MCE_R 14209 -#define ETH1MAC_R 14218 -#define FMC_R 14220 -#define QSPI_R 14222 -#define SDMMC1_R 14224 -#define SDMMC2_R 14225 -#define CRC1_R 14228 -#define USBH_R 14232 -#define ETH2MAC_R 14238 - -/* SCMI reset domain identifiers */ -#define RST_SCMI_LTDC 0 -#define RST_SCMI_MDMA 1 - -#endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */ diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h index 8dfb1bc9527..7ed88809913 100644 --- a/include/efi_tcg2.h +++ b/include/efi_tcg2.h @@ -28,8 +28,6 @@ #define EFI_TCG2_MAX_PCR_INDEX 23 #define EFI_TCG2_FINAL_EVENTS_TABLE_VERSION 1 -#define TPM2_EVENT_LOG_SIZE CONFIG_EFI_TCG2_PROTOCOL_EVENTLOG_SIZE - typedef u32 efi_tcg_event_log_bitmap; typedef u32 efi_tcg_event_log_format; typedef u32 efi_tcg_event_algorithm_bitmap; diff --git a/include/env/phytec/k3_mmc.env b/include/env/phytec/k3_mmc.env index ad8d3a8b764..3f67e312f65 100644 --- a/include/env/phytec/k3_mmc.env +++ b/include/env/phytec/k3_mmc.env @@ -11,6 +11,7 @@ mmcargs=setenv bootargs console=${console} earlycon=${earlycon} root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw + ${optargs} mmcloadimage=load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} Image mmcloadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} mmcboot=if test ${doraucboot} = 1; then run raucinit; fi; diff --git a/include/env/phytec/k3_net.env b/include/env/phytec/k3_net.env index 377e406688d..8ad1cb7b0c2 100644 --- a/include/env/phytec/k3_net.env +++ b/include/env/phytec/k3_net.env @@ -9,7 +9,7 @@ #include <env/phytec/overlays.env> netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp rw - nfsroot=${serverip}:${nfsroot},vers=4,tcp + nfsroot=${serverip}:${nfsroot},vers=4,tcp ${optargs} netloadimage=${net_fetch_cmd} ${kernel_addr_r} ${serverip}:/Image netloadfdt=${net_fetch_cmd} ${fdt_addr_r} ${serverip}:/${fdtfile} netboot=run netargs; diff --git a/include/env/phytec/k3_spi.env b/include/env/phytec/k3_spi.env index 97d3a157058..8e9cfce3b4c 100644 --- a/include/env/phytec/k3_spi.env +++ b/include/env/phytec/k3_spi.env @@ -6,7 +6,7 @@ /* Logic for TI K3 based SoCs to boot from an OSPI/QSPI NOR flash. */ -spiargs=setenv bootargs console=${console} earlycon=${earlycon} +spiargs=setenv bootargs console=${console} earlycon=${earlycon} ${optargs} spiloadimage=sf read ${kernel_addr_r} ${spi_image_addr} ${size_kern} spiloadfdt=sf read ${fdt_addr_r} ${spi_fdt_addr} ${size_fdt} spiloadramdisk=sf read ${ramdisk_addr_r} ${spi_ramdisk_addr} ${size_fs} diff --git a/include/fpga.h b/include/fpga.h index 44f2755a3f1..4cc44164b2f 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -58,7 +58,7 @@ typedef enum { void fpga_init(void); int fpga_add(fpga_type devtype, void *desc); int fpga_count(void); -const fpga_desc *const fpga_get_desc(int devnum); +const fpga_desc *fpga_get_desc(int devnum); int fpga_is_partial_data(int devnum, size_t img_len); #if CONFIG_IS_ENABLED(FPGA) int fpga_load(int devnum, const void *buf, size_t bsize, @@ -78,8 +78,8 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, bitstream_type bstype); int fpga_dump(int devnum, const void *buf, size_t bsize); int fpga_info(int devnum); -const fpga_desc *const fpga_validate(int devnum, const void *buf, - size_t bsize, char *fn); +const fpga_desc *fpga_validate(int devnum, const void *buf, + size_t bsize, char *fn); int fpga_compatible2flag(int devnum, const char *compatible); #endif /* _FPGA_H_ */ diff --git a/include/led.h b/include/led.h index 64247cd3a70..2a7f38bf84b 100644 --- a/include/led.h +++ b/include/led.h @@ -53,6 +53,11 @@ struct udevice; +/* + * value imported from linux:include/linux/uapi/linux/uleds.h + */ +#define LED_MAX_NAME_SIZE 64 + enum led_state_t { LEDST_OFF = 0, LEDST_ON = 1, @@ -81,11 +86,14 @@ struct led_sw_blink { * * @label: LED label * @default_state: LED default state + * @name: LED name, derived from function, color or function-enumerator + * property. * @sw_blink: LED software blink struct */ struct led_uc_plat { const char *label; enum led_state_t default_state; + char name[LED_MAX_NAME_SIZE]; #ifdef CONFIG_LED_SW_BLINK struct led_sw_blink *sw_blink; #endif diff --git a/include/miiphy.h b/include/miiphy.h index 5abffd8fb6b..1e6c7041fdc 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -64,7 +64,7 @@ void mdio_list_devices(void); #define BB_MII_DEVNAME "bb_miiphy" struct bb_miiphy_bus { - char name[16]; + char name[MDIO_NAME_LEN]; int (*init)(struct bb_miiphy_bus *bus); int (*mdio_active)(struct bb_miiphy_bus *bus); int (*mdio_tristate)(struct bb_miiphy_bus *bus); @@ -72,9 +72,7 @@ struct bb_miiphy_bus { int (*get_mdio)(struct bb_miiphy_bus *bus, int *v); int (*set_mdc)(struct bb_miiphy_bus *bus, int v); int (*delay)(struct bb_miiphy_bus *bus); -#ifdef CONFIG_BITBANGMII_MULTI void *priv; -#endif }; extern struct bb_miiphy_bus bb_miiphy_buses[]; diff --git a/include/spl.h b/include/spl.h index 7155e9c67aa..850c64d4b19 100644 --- a/include/spl.h +++ b/include/spl.h @@ -345,7 +345,7 @@ typedef ulong (*spl_load_reader)(struct spl_load_info *load, ulong sector, * @priv: Private data for the device * @bl_len: Block length for reading in bytes * @phase: Image phase to load - * @fit_loaded: true if the FIT has been loaded, except for external data + * @no_fdt_update: true to update the FDT with any loadables that are loaded */ struct spl_load_info { spl_load_reader read; @@ -355,7 +355,7 @@ struct spl_load_info { #endif #if CONFIG_IS_ENABLED(BOOTMETH_VBE) u8 phase; - u8 fit_loaded; + u8 fdt_update; #endif }; @@ -395,12 +395,20 @@ static inline enum image_phase_t xpl_get_phase(struct spl_load_info *info) #endif } -static inline bool xpl_get_fit_loaded(struct spl_load_info *info) +static inline void xpl_set_fdt_update(struct spl_load_info *info, + bool fdt_update) { #if CONFIG_IS_ENABLED(BOOTMETH_VBE) - return info->fit_loaded; + info->fdt_update = fdt_update; +#endif +} + +static inline enum image_phase_t xpl_get_fdt_update(struct spl_load_info *info) +{ +#if CONFIG_IS_ENABLED(BOOTMETH_VBE) + return info->fdt_update; #else - return false; + return true; #endif } @@ -415,6 +423,7 @@ static inline void spl_load_init(struct spl_load_info *load, load->priv = priv; spl_set_bl_len(load, bl_len); xpl_set_phase(load, IH_PHASE_NONE); + xpl_set_fdt_update(load, true); } /* diff --git a/include/spl_load.h b/include/spl_load.h index 935f7d336f2..525e0c9e86c 100644 --- a/include/spl_load.h +++ b/include/spl_load.h @@ -20,13 +20,15 @@ static inline int _spl_load(struct spl_image_info *spl_image, ulong base_offset, image_offset, overhead; int read, ret; + log_debug("\nloading hdr from %lx to %p\n", (ulong)offset, header); read = info->read(info, offset, ALIGN(sizeof(*header), spl_get_bl_len(info)), header); if (read < (int)sizeof(*header)) return -EIO; if (image_get_magic(header) == FDT_MAGIC) { - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)) { + log_debug("Found FIT\n"); + if (CONFIG_IS_ENABLED(LOAD_FIT_FULL)) { void *buf; /* @@ -48,9 +50,12 @@ static inline int _spl_load(struct spl_image_info *spl_image, return spl_parse_image_header(spl_image, bootdev, buf); } - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) + if (CONFIG_IS_ENABLED(LOAD_FIT)) { + log_debug("Simple loading\n"); return spl_load_simple_fit(spl_image, info, offset, header); + } + log_debug("No FIT support\n"); } if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && diff --git a/include/vbe.h b/include/vbe.h index 56bff63362f..61bfa0e557d 100644 --- a/include/vbe.h +++ b/include/vbe.h @@ -10,6 +10,8 @@ #ifndef __VBE_H #define __VBE_H +#include <linux/types.h> + /** * enum vbe_phase_t - current phase of VBE * @@ -26,12 +28,31 @@ enum vbe_phase_t { }; /** + * enum vbe_pick_t - indicates which firmware is picked + * + * @VBEFT_A: Firmware A + * @VBEFT_B: Firmware B + * @VBEFT_RECOVERY: Recovery firmware + */ +enum vbe_pick_t { + VBEP_A, + VBEP_B, + VBEP_RECOVERY, +}; + +/** * struct vbe_handoff - information about VBE progress * + * @offset: Offset of the FIT to use for SPL onwards + * @size: Size of the area containing the FIT * @phases: Indicates which phases used the VBE bootmeth (1 << PHASE_...) + * @pick: Indicates which firmware pick was used (enum vbe_pick_t) */ struct vbe_handoff { + ulong offset; + ulong size; u8 phases; + u8 pick; }; /** diff --git a/lib/Kconfig b/lib/Kconfig index b27965fc480..1a683dea670 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -758,6 +758,16 @@ config VPL_CRC8 checksum with feedback to produce an 8-bit result. The code is small and it does not require a lookup table (unlike CRC32). +config CRC16 + bool "Support CRC16" + default y + help + Enables CRC16 support. This is normally required. Two algorithms are + provided: + + - CCITT, with a polynomical x^16 + x^12 + x^5 + 1 + - standard, with polynomial x^16 + x^15 + x^2 + 1 (0x8005) + config SPL_CRC16 bool "Support CRC16 in SPL" depends on SPL diff --git a/lib/Makefile b/lib/Makefile index fc6e68c901a..a7bc2f3134a 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -35,8 +35,6 @@ obj-$(CONFIG_CIRCBUF) += circbuf.o endif obj-y += crc8.o -obj-y += crc16.o -obj-y += crc16-ccitt.o obj-$(CONFIG_ERRNO_STR) += errno_str.o obj-$(CONFIG_FIT) += fdtdec_common.o obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o @@ -71,6 +69,7 @@ endif obj-$(CONFIG_$(PHASE_)CRC8) += crc8.o obj-$(CONFIG_$(PHASE_)CRC16) += crc16.o +obj-$(CONFIG_$(PHASE_)CRC16) += crc16-ccitt.o obj-y += crypto/ @@ -80,11 +79,11 @@ obj-$(CONFIG_$(XPL_)RSA) += rsa/ obj-$(CONFIG_HASH) += hash-checksum.o obj-$(CONFIG_BLAKE2) += blake2/blake2b.o -obj-$(CONFIG_$(XPL_)MD5_LEGACY) += md5.o -obj-$(CONFIG_$(XPL_)SHA1_LEGACY) += sha1.o -obj-$(CONFIG_$(XPL_)SHA256) += sha256_common.o -obj-$(CONFIG_$(XPL_)SHA256_LEGACY) += sha256.o -obj-$(CONFIG_$(XPL_)SHA512_LEGACY) += sha512.o +obj-$(CONFIG_$(PHASE_)MD5_LEGACY) += md5.o +obj-$(CONFIG_$(PHASE_)SHA1_LEGACY) += sha1.o +obj-$(CONFIG_$(PHASE_)SHA256) += sha256_common.o +obj-$(CONFIG_$(PHASE_)SHA256_LEGACY) += sha256.o +obj-$(CONFIG_$(PHASE_)SHA512_LEGACY) += sha512.o obj-$(CONFIG_CRYPT_PW) += crypt/ obj-$(CONFIG_$(XPL_)ASN1_DECODER_LEGACY) += asn1_decoder.o diff --git a/lib/crc8.c b/lib/crc8.c index 811e19917b4..bbb229c3892 100644 --- a/lib/crc8.c +++ b/lib/crc8.c @@ -6,11 +6,12 @@ #ifdef USE_HOSTCC #include <arpa/inet.h> #endif +#include <asm/sections.h> #include <u-boot/crc.h> #define POLY (0x1070U << 3) -static unsigned char _crc8(unsigned short data) +__rcode static unsigned char _crc8(unsigned short data) { int i; @@ -23,7 +24,7 @@ static unsigned char _crc8(unsigned short data) return (unsigned char)(data >> 8); } -unsigned int crc8(unsigned int crc, const unsigned char *vptr, int len) +__rcode unsigned int crc8(unsigned int crc, const unsigned char *vptr, int len) { int i; diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index ad0bbdd8a77..d4f6b56afaa 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -438,15 +438,6 @@ config EFI_TCG2_PROTOCOL Provide a EFI_TCG2_PROTOCOL implementation using the TPM hardware of the platform. -config EFI_TCG2_PROTOCOL_EVENTLOG_SIZE - int "EFI_TCG2_PROTOCOL EventLog size" - depends on EFI_TCG2_PROTOCOL - default 65536 - help - Define the size of the EventLog for EFI_TCG2_PROTOCOL. Note that - this is going to be allocated twice. One for the eventlog it self - and one for the configuration table that is required from the spec - config EFI_TCG2_PROTOCOL_MEASURE_DTB bool "Measure DTB with EFI_TCG2_PROTOCOL" depends on EFI_TCG2_PROTOCOL diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c index c697b53441a..210a846ebc8 100644 --- a/lib/efi_loader/efi_tcg2.c +++ b/lib/efi_loader/efi_tcg2.c @@ -112,7 +112,7 @@ static efi_status_t tcg2_agile_log_append(u32 pcr_index, u32 event_type, /* if ExitBootServices hasn't been called update the normal log */ if (!event_log.ebs_called) { if (event_log.truncated || - event_log.pos + event_size > TPM2_EVENT_LOG_SIZE) { + event_log.pos + event_size > CONFIG_TPM2_EVENT_LOG_SIZE) { event_log.truncated = true; return EFI_VOLUME_FULL; } @@ -125,7 +125,7 @@ static efi_status_t tcg2_agile_log_append(u32 pcr_index, u32 event_type, return ret; /* if GetEventLog has been called update FinalEventLog as well */ - if (event_log.final_pos + event_size > TPM2_EVENT_LOG_SIZE) + if (event_log.final_pos + event_size > CONFIG_TPM2_EVENT_LOG_SIZE) return EFI_VOLUME_FULL; log = (void *)((uintptr_t)event_log.final_buffer + event_log.final_pos); @@ -823,12 +823,12 @@ static efi_status_t create_final_event(void) * EFI_TCG2_GET_EVENT_LOGS need to be stored in an instance of an * EFI_CONFIGURATION_TABLE */ - ret = efi_allocate_pool(EFI_ACPI_MEMORY_NVS, TPM2_EVENT_LOG_SIZE, + ret = efi_allocate_pool(EFI_ACPI_MEMORY_NVS, CONFIG_TPM2_EVENT_LOG_SIZE, &event_log.final_buffer); if (ret != EFI_SUCCESS) goto out; - memset(event_log.final_buffer, 0xff, TPM2_EVENT_LOG_SIZE); + memset(event_log.final_buffer, 0xff, CONFIG_TPM2_EVENT_LOG_SIZE); final_event = event_log.final_buffer; final_event->number_of_events = 0; final_event->version = EFI_TCG2_FINAL_EVENTS_TABLE_VERSION; @@ -914,7 +914,8 @@ static efi_status_t efi_init_event_log(void) if (tcg2_platform_get_tpm2(&dev)) return EFI_DEVICE_ERROR; - ret = efi_allocate_pool(EFI_BOOT_SERVICES_DATA, TPM2_EVENT_LOG_SIZE, + ret = efi_allocate_pool(EFI_BOOT_SERVICES_DATA, + CONFIG_TPM2_EVENT_LOG_SIZE, (void **)&event_log.buffer); if (ret != EFI_SUCCESS) return ret; @@ -923,7 +924,7 @@ static efi_status_t efi_init_event_log(void) * initialize log area as 0xff so the OS can easily figure out the * last log entry */ - memset(event_log.buffer, 0xff, TPM2_EVENT_LOG_SIZE); + memset(event_log.buffer, 0xff, CONFIG_TPM2_EVENT_LOG_SIZE); /* * The log header is defined to be in SHA1 event log entry format. @@ -940,7 +941,7 @@ static efi_status_t efi_init_event_log(void) * platforms can use different ways to do so. */ elog.log = event_log.buffer; - elog.log_size = TPM2_EVENT_LOG_SIZE; + elog.log_size = CONFIG_TPM2_EVENT_LOG_SIZE; rc = tcg2_log_prepare_buffer(dev, &elog, false); if (rc) { ret = (rc == -ENOBUFS) ? EFI_BUFFER_TOO_SMALL : EFI_DEVICE_ERROR; diff --git a/lib/gunzip.c b/lib/gunzip.c index e71d8d00ccb..52007715bda 100644 --- a/lib/gunzip.c +++ b/lib/gunzip.c @@ -15,6 +15,7 @@ #include <u-boot/crc.h> #include <watchdog.h> #include <u-boot/zlib.h> +#include <asm/sections.h> #define HEADER0 '\x1f' #define HEADER1 '\x8b' @@ -43,7 +44,7 @@ void gzfree(void *x, void *addr, unsigned nb) free (addr); } -int gzip_parse_header(const unsigned char *src, unsigned long len) +__rcode int gzip_parse_header(const unsigned char *src, unsigned long len) { int i, flags; @@ -71,7 +72,7 @@ int gzip_parse_header(const unsigned char *src, unsigned long len) return i; } -int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp) +__rcode int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp) { int offset = gzip_parse_header(src, *lenp); @@ -274,8 +275,8 @@ out: /* * Uncompress blocks compressed with zlib without headers */ -int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp, - int stoponerr, int offset) +__rcode int zunzip(void *dst, int dstlen, unsigned char *src, + unsigned long *lenp, int stoponerr, int offset) { z_stream s; int err = 0; diff --git a/lib/lz4.c b/lib/lz4.c index 63955a0b178..c718659c590 100644 --- a/lib/lz4.c +++ b/lib/lz4.c @@ -33,15 +33,16 @@ #include <linux/bug.h> #include <asm/unaligned.h> #include <u-boot/lz4.h> +#include <asm/sections.h> #define FORCE_INLINE inline __attribute__((always_inline)) -static FORCE_INLINE u16 LZ4_readLE16(const void *src) +__rcode static FORCE_INLINE u16 LZ4_readLE16(const void *src) { return get_unaligned_le16(src); } -static FORCE_INLINE void LZ4_copy8(void *dst, const void *src) +__rcode static FORCE_INLINE void LZ4_copy8(void *dst, const void *src) { put_unaligned(get_unaligned((const u64 *)src), (u64 *)dst); } @@ -53,7 +54,7 @@ typedef int32_t S32; typedef uint64_t U64; typedef uintptr_t uptrval; -static FORCE_INLINE void LZ4_write32(void *memPtr, U32 value) +__rcode static FORCE_INLINE void LZ4_write32(void *memPtr, U32 value) { put_unaligned(value, (U32 *)memPtr); } @@ -63,7 +64,7 @@ static FORCE_INLINE void LZ4_write32(void *memPtr, U32 value) **************************************/ /* customized version of memcpy, which may overwrite up to 7 bytes beyond dstEnd */ -static void LZ4_wildCopy(void* dstPtr, const void* srcPtr, void* dstEnd) +__rcode static void LZ4_wildCopy(void *dstPtr, const void *srcPtr, void *dstEnd) { BYTE* d = (BYTE*)dstPtr; const BYTE* s = (const BYTE*)srcPtr; @@ -112,13 +113,24 @@ typedef enum { decode_full_block = 0, partial_decode = 1 } earlyEnd_directive; #endif /* + * spl_reloc needs all necessary data to be set up within its code, since the + * code is relocated at runtime. Unfortunately this increase code-size slightly + * so only do it if spl_reloc is enabled + */ +#if CONFIG_IS_ENABLED(RELOC_LOADER) +#define STATIC +#else +#define STATIC static +#endif + +/* * LZ4_decompress_generic() : * This generic decompression function covers all use cases. * It shall be instantiated several times, using different sets of directives. * Note that it is important for performance that this function really get inlined, * in order to remove useless branches during compilation optimization. */ -static FORCE_INLINE int LZ4_decompress_generic( +__rcode static FORCE_INLINE int LZ4_decompress_generic( const char * const src, char * const dst, int srcSize, @@ -141,6 +153,8 @@ static FORCE_INLINE int LZ4_decompress_generic( const size_t dictSize ) { + STATIC const unsigned int inc32table[8] = {0, 1, 2, 1, 0, 4, 4, 4}; + STATIC const int dec64table[8] = {0, 0, 0, -1, -4, 1, 2, 3}; const BYTE *ip = (const BYTE *) src; const BYTE * const iend = ip + srcSize; @@ -149,8 +163,6 @@ static FORCE_INLINE int LZ4_decompress_generic( BYTE *cpy; const BYTE * const dictEnd = (const BYTE *)dictStart + dictSize; - static const unsigned int inc32table[8] = {0, 1, 2, 1, 0, 4, 4, 4}; - static const int dec64table[8] = {0, 0, 0, -1, -4, 1, 2, 3}; const int safeDecode = (endOnInput == endOnInputSize); const int checkOffset = ((safeDecode) && (dictSize < (int)(64 * KB))); @@ -514,8 +526,9 @@ _output_error: return (int) (-(((const char *)ip) - src)) - 1; } -int LZ4_decompress_safe(const char *source, char *dest, - int compressedSize, int maxDecompressedSize) +#ifndef CONFIG_SPL_BUILD +__rcode int LZ4_decompress_safe(const char *source, char *dest, + int compressedSize, int maxDecompressedSize) { return LZ4_decompress_generic(source, dest, compressedSize, maxDecompressedSize, @@ -523,11 +536,13 @@ int LZ4_decompress_safe(const char *source, char *dest, noDict, (BYTE *)dest, NULL, 0); } -int LZ4_decompress_safe_partial(const char *src, char *dst, - int compressedSize, int targetOutputSize, int dstCapacity) +__rcode int LZ4_decompress_safe_partial(const char *src, char *dst, + int compressedSize, + int targetOutputSize, int dstCapacity) { dstCapacity = min(targetOutputSize, dstCapacity); return LZ4_decompress_generic(src, dst, compressedSize, dstCapacity, endOnInputSize, partial_decode, noDict, (BYTE *)dst, NULL, 0); } +#endif diff --git a/lib/lz4_wrapper.c b/lib/lz4_wrapper.c index 4d48e7b0e8b..b1204511170 100644 --- a/lib/lz4_wrapper.c +++ b/lib/lz4_wrapper.c @@ -15,7 +15,7 @@ #define LZ4F_BLOCKUNCOMPRESSED_FLAG 0x80000000U -int ulz4fn(const void *src, size_t srcn, void *dst, size_t *dstn) +__rcode int ulz4fn(const void *src, size_t srcn, void *dst, size_t *dstn) { const void *end = dst + *dstn; const void *in = src; diff --git a/lib/mbedtls/Kconfig b/lib/mbedtls/Kconfig index aa82336ef14..35d8c507a89 100644 --- a/lib/mbedtls/Kconfig +++ b/lib/mbedtls/Kconfig @@ -112,6 +112,46 @@ config SPL_MD5_LEGACY endif # SPL +if VPL + +config VPL_SHA1_LEGACY + bool "Enable SHA1 support in VPL with legacy crypto library" + depends on LEGACY_CRYPTO_BASIC && VPL_SHA1 + help + This option enables support of hashing using SHA1 algorithm + with legacy crypto library. + +config VPL_SHA256_LEGACY + bool "Enable SHA256 support in VPL with legacy crypto library" + depends on LEGACY_CRYPTO_BASIC && VPL_SHA256 + help + This option enables support of hashing using SHA256 algorithm + with legacy crypto library. + +config VPL_SHA512_LEGACY + bool "Enable SHA512 support in VPL with legacy crypto library" + depends on LEGACY_CRYPTO_BASIC && VPL_SHA512 + help + This option enables support of hashing using SHA512 algorithm + with legacy crypto library. + +config VPL_SHA384_LEGACY + bool "Enable SHA384 support in VPL with legacy crypto library" + depends on LEGACY_CRYPTO_BASIC && VPL_SHA384 + select VPL_SHA512_LEGACY + help + This option enables support of hashing using SHA384 algorithm + with legacy crypto library. + +config VPL_MD5_LEGACY + bool "Enable MD5 support in VPL with legacy crypto library" + depends on LEGACY_CRYPTO_BASIC && VPL_MD5 + help + This option enables support of hashing using MD5 algorithm + with legacy crypto library. + +endif # VPL + endif # LEGACY_CRYPTO_BASIC config LEGACY_CRYPTO_CERT diff --git a/lib/string.c b/lib/string.c index feae9519f2f..0e0900de8bf 100644 --- a/lib/string.c +++ b/lib/string.c @@ -21,6 +21,7 @@ #include <linux/string.h> #include <linux/ctype.h> #include <malloc.h> +#include <asm/sections.h> /** * strncasecmp - Case insensitive, length-limited string comparison @@ -559,7 +560,7 @@ __used void * memset(void * s,int c,size_t count) * You should not use this function to access IO space, use memcpy_toio() * or memcpy_fromio() instead. */ -__used void * memcpy(void *dest, const void *src, size_t count) +__rcode __used void *memcpy(void *dest, const void *src, size_t count) { unsigned long *dl = (unsigned long *)dest, *sl = (unsigned long *)src; char *d8, *s8; @@ -593,7 +594,7 @@ __used void * memcpy(void *dest, const void *src, size_t count) * * Unlike memcpy(), memmove() copes with overlapping areas. */ -__used void * memmove(void * dest,const void *src,size_t count) +__rcode __used void *memmove(void *dest, const void *src, size_t count) { char *tmp, *s; diff --git a/lib/tpm_tcg2.c b/lib/tpm_tcg2.c index 1175d08abc5..c314b401d0b 100644 --- a/lib/tpm_tcg2.c +++ b/lib/tpm_tcg2.c @@ -19,6 +19,7 @@ #include <linux/unaligned/generic.h> #include <linux/unaligned/le_byteshift.h> #include "tpm-utils.h" +#include <bloblist.h> int tcg2_get_pcr_info(struct udevice *dev, u32 *supported_bank, u32 *active_bank, u32 *bank_num) @@ -654,21 +655,42 @@ void tcg2_measurement_term(struct udevice *dev, struct tcg2_event_log *elog, __weak int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size) { - const __be32 *addr_prop; - const __be32 *size_prop; + const __be32 *addr_prop = NULL; + const __be32 *size_prop = NULL; int asize; int ssize; + struct ofnode_phandle_args args; + phys_addr_t a; + fdt_size_t s; *addr = NULL; *size = 0; - addr_prop = dev_read_prop(dev, "tpm_event_log_addr", &asize); - if (!addr_prop) - addr_prop = dev_read_prop(dev, "linux,sml-base", &asize); + *addr = bloblist_get_blob(BLOBLISTT_TPM_EVLOG, size); + if (*addr && *size) { + *addr = map_physmem((uintptr_t)(*addr), *size, MAP_NOCACHE); + return 0; + } - size_prop = dev_read_prop(dev, "tpm_event_log_size", &ssize); - if (!size_prop) + /* + * TODO: + * Replace BLOBLIST with a new kconfig for handoff all components + * (fdt, tpm event log, etc...) from previous boot stage via bloblist + * mandatorily following Firmware Handoff spec. + */ + if (!CONFIG_IS_ENABLED(BLOBLIST)) { + addr_prop = dev_read_prop(dev, "tpm_event_log_addr", &asize); + size_prop = dev_read_prop(dev, "tpm_event_log_size", &ssize); + } + + /* + * If no eventlog was observed, a sml buffer is required for the kernel + * to discover the eventlog. + */ + if (!addr_prop || !size_prop) { + addr_prop = dev_read_prop(dev, "linux,sml-base", &asize); size_prop = dev_read_prop(dev, "linux,sml-size", &ssize); + } if (addr_prop && size_prop) { u64 a = of_read_number(addr_prop, asize / sizeof(__be32)); @@ -676,22 +698,19 @@ __weak int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size) *addr = map_physmem(a, s, MAP_NOCACHE); *size = (u32)s; - } else { - struct ofnode_phandle_args args; - phys_addr_t a; - fdt_size_t s; - if (dev_read_phandle_with_args(dev, "memory-region", NULL, 0, - 0, &args)) - return -ENODEV; + return 0; + } - a = ofnode_get_addr_size(args.node, "reg", &s); - if (a == FDT_ADDR_T_NONE) - return -ENOMEM; + if (dev_read_phandle_with_args(dev, "memory-region", NULL, 0, 0, &args)) + return -ENODEV; - *addr = map_physmem(a, s, MAP_NOCACHE); - *size = (u32)s; - } + a = ofnode_get_addr_size(args.node, "reg", &s); + if (a == FDT_ADDR_T_NONE) + return -ENOMEM; + + *addr = map_physmem(a, s, MAP_NOCACHE); + *size = (u32)s; return 0; } diff --git a/lib/zlib/inflate.c b/lib/zlib/inflate.c index f7e81fc8b2a..b4c72cc2c5c 100644 --- a/lib/zlib/inflate.c +++ b/lib/zlib/inflate.c @@ -2,10 +2,12 @@ * Copyright (C) 1995-2005 Mark Adler * For conditions of distribution and use, see copyright notice in zlib.h */ +#include <asm/sections.h> + local void fixedtables OF((struct inflate_state FAR *state)); local int updatewindow OF((z_streamp strm, unsigned out)); -int ZEXPORT inflateReset(z_streamp strm) +__rcode int ZEXPORT inflateReset(z_streamp strm) { struct inflate_state FAR *state; @@ -30,8 +32,8 @@ int ZEXPORT inflateReset(z_streamp strm) return Z_OK; } -int ZEXPORT inflateInit2_(z_streamp strm, int windowBits, - int stream_size) +__rcode int ZEXPORT inflateInit2_(z_streamp strm, int windowBits, + int stream_size) { struct inflate_state FAR *state; @@ -67,12 +69,12 @@ int ZEXPORT inflateInit2_(z_streamp strm, int windowBits, return inflateReset(strm); } -int ZEXPORT inflateInit_(z_streamp strm, int stream_size) +__rcode int ZEXPORT inflateInit_(z_streamp strm, int stream_size) { return inflateInit2_(strm, DEF_WBITS, stream_size); } -local void fixedtables(struct inflate_state FAR *state) +__rcode local void fixedtables(struct inflate_state FAR *state) { state->lencode = lenfix; state->lenbits = 9; @@ -94,7 +96,7 @@ local void fixedtables(struct inflate_state FAR *state) output will fall in the output data, making match copies simpler and faster. The advantage may be dependent on the size of the processor's data caches. */ -local int updatewindow(z_streamp strm, unsigned out) +__rcode local int updatewindow(z_streamp strm, unsigned int out) { struct inflate_state FAR *state; unsigned copy, dist; @@ -322,7 +324,7 @@ local int updatewindow(z_streamp strm, unsigned out) when flush is set to Z_FINISH, inflate() cannot return Z_OK. Instead it will return Z_BUF_ERROR if it has not reached the end of the stream. */ -int ZEXPORT inflate(z_streamp strm, int flush) +__rcode int ZEXPORT inflate(z_streamp strm, int flush) { struct inflate_state FAR *state; unsigned char FAR *next; /* next input */ @@ -924,7 +926,7 @@ int ZEXPORT inflate(z_streamp strm, int flush) return ret; } -int ZEXPORT inflateEnd(z_streamp strm) +__rcode int ZEXPORT inflateEnd(z_streamp strm) { struct inflate_state FAR *state; if (strm == Z_NULL || strm->state == Z_NULL || strm->zfree == (free_func)0) diff --git a/test/cmd/setexpr.c b/test/cmd/setexpr.c index 7f318a42ead..5e9b577fe36 100644 --- a/test/cmd/setexpr.c +++ b/test/cmd/setexpr.c @@ -297,31 +297,19 @@ SETEXPR_TEST(setexpr_test_backref, UTF_CONSOLE); /* Test 'setexpr' command with setting strings */ static int setexpr_test_str(struct unit_test_state *uts) { - ulong start_mem; char *buf; buf = map_sysmem(0, BUF_SIZE); memset(buf, '\xff', BUF_SIZE); - /* - * Set 'fred' to the same length as we expect to get below, to avoid a - * new allocation in 'setexpr'. That way we can check for memory leaks. - */ ut_assertok(env_set("fred", "x")); - start_mem = ut_check_free(); - strcpy(buf, "hello"); - ut_asserteq(1, run_command("setexpr.s fred 0", 0)); - ut_assertok(ut_check_delta(start_mem)); + ut_asserteq(0, run_command("setexpr.s fred 0", 0)); + ut_asserteq_str("0", env_get("fred")); + strcpy(buf, "hello"); ut_assertok(env_set("fred", "12345")); - start_mem = ut_check_free(); ut_assertok(run_command("setexpr.s fred *0", 0)); ut_asserteq_str("hello", env_get("fred")); - /* - * This fails in CI at present. - * - * ut_assertok(ut_check_delta(start_mem)); - */ unmap_sysmem(buf); @@ -332,45 +320,25 @@ SETEXPR_TEST(setexpr_test_str, UTF_CONSOLE); /* Test 'setexpr' command with concatenating strings */ static int setexpr_test_str_oper(struct unit_test_state *uts) { - ulong start_mem; char *buf; + /* Test concatenation of strings */ + ut_assertok(run_command("setexpr.s fred '1' + '3'", 0)); + ut_asserteq_str("13", env_get("fred")); + buf = map_sysmem(0, BUF_SIZE); memset(buf, '\xff', BUF_SIZE); strcpy(buf, "hello"); strcpy(buf + 0x10, " there"); - start_mem = ut_check_free(); ut_asserteq(1, run_command("setexpr.s fred *0 * *10", 0)); - ut_assertok(ut_check_delta(start_mem)); ut_assert_nextline("invalid op"); ut_assert_console_end(); - /* - * Set 'fred' to the same length as we expect to get below, to avoid a - * new allocation in 'setexpr'. That way we can check for memory leaks. - */ ut_assertok(env_set("fred", "12345012345")); - start_mem = ut_check_free(); ut_assertok(run_command("setexpr.s fred *0 + *10", 0)); ut_asserteq_str("hello there", env_get("fred")); - /* - * This check does not work with sandbox_flattree, apparently due to - * memory allocations in env_set(). - * - * The truetype console produces lots of memory allocations even though - * the LCD display is not visible. But even without these, it does not - * work. - * - * A better test would be for dlmalloc to record the allocs and frees - * for a particular caller, but that is not supported. - * - * For now, drop this test. - * - * ut_assertok(ut_check_delta(start_mem)); - */ - unmap_sysmem(buf); return 0; diff --git a/test/common/bloblist.c b/test/common/bloblist.c index 9467abfa8e1..ab8f41c6808 100644 --- a/test/common/bloblist.c +++ b/test/common/bloblist.c @@ -98,10 +98,12 @@ static int bloblist_test_blob(struct unit_test_state *uts) struct bloblist_hdr *hdr; struct bloblist_rec *rec, *rec2; char *data; + int size = 0; /* At the start there should be no records */ hdr = clear_bloblist(); ut_assertnull(bloblist_find(TEST_TAG, TEST_BLOBLIST_SIZE)); + ut_assertnull(bloblist_get_blob(TEST_TAG, &size)); ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0)); ut_asserteq(sizeof(struct bloblist_hdr), bloblist_get_size()); ut_asserteq(TEST_BLOBLIST_SIZE, bloblist_get_total_size()); @@ -114,6 +116,8 @@ static int bloblist_test_blob(struct unit_test_state *uts) ut_asserteq_addr(rec + 1, data); data = bloblist_find(TEST_TAG, TEST_SIZE); ut_asserteq_addr(rec + 1, data); + ut_asserteq_addr(bloblist_get_blob(TEST_TAG, &size), data); + ut_asserteq(size, TEST_SIZE); /* Check the data is zeroed */ ut_assertok(check_zero(data, TEST_SIZE)); diff --git a/test/dm/led.c b/test/dm/led.c index e5b86326c3a..36652c2833a 100644 --- a/test/dm/led.c +++ b/test/dm/led.c @@ -20,7 +20,12 @@ static int dm_test_led_base(struct unit_test_state *uts) ut_assertok(uclass_get_device(UCLASS_LED, 1, &dev)); ut_assertok(uclass_get_device(UCLASS_LED, 2, &dev)); ut_assertok(uclass_get_device(UCLASS_LED, 3, &dev)); - ut_asserteq(-ENODEV, uclass_get_device(UCLASS_LED, 4, &dev)); + ut_assertok(uclass_get_device(UCLASS_LED, 4, &dev)); + ut_assertok(uclass_get_device(UCLASS_LED, 5, &dev)); + ut_assertok(uclass_get_device(UCLASS_LED, 6, &dev)); + ut_assertok(uclass_get_device(UCLASS_LED, 7, &dev)); + ut_assertok(uclass_get_device(UCLASS_LED, 8, &dev)); + ut_asserteq(-ENODEV, uclass_get_device(UCLASS_LED, 9, &dev)); return 0; } @@ -110,6 +115,21 @@ static int dm_test_led_label(struct unit_test_state *uts) ut_asserteq(-ENODEV, led_get_by_label("sandbox:blue", &dev)); + /* Test if function, color and function-enumerator naming works */ + ut_assertok(led_get_by_label("red:status-20", &dev)); + + /* Test if function, color naming works */ + ut_assertok(led_get_by_label("green:status", &dev)); + + /* Test if function, without color naming works */ + ut_assertok(led_get_by_label(":status", &dev)); + + /* Test if color without function naming works */ + ut_assertok(led_get_by_label("green:", &dev)); + + /* Test if function, color naming is ignored if label is found */ + ut_assertok(led_get_by_label("sandbox:function", &dev)); + return 0; } DM_TEST(dm_test_led_label, UTF_SCAN_PDATA | UTF_SCAN_FDT); diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c index 4a23a3ca38c..cc8b444ff9a 100644 --- a/test/dm/ofnode.c +++ b/test/dm/ofnode.c @@ -1599,7 +1599,7 @@ static int dm_test_ofnode_delete(struct unit_test_state *uts) ut_assert(!ofnode_valid(node)); ut_assert(!ofnode_valid(ofnode_path("/leds/default_on"))); - ut_asserteq(2, ofnode_get_child_count(ofnode_path("/leds"))); + ut_asserteq(7, ofnode_get_child_count(ofnode_path("/leds"))); return 0; } diff --git a/test/py/conftest.py b/test/py/conftest.py index 3bd333bfd24..31043a697e2 100644 --- a/test/py/conftest.py +++ b/test/py/conftest.py @@ -25,6 +25,7 @@ import re from _pytest.runner import runtestprotocol import subprocess import sys +import time from u_boot_spawn import BootFail, Timeout, Unexpected, handle_exception # Globals: The HTML log file, and the connection to the U-Boot console. @@ -91,6 +92,9 @@ def pytest_addoption(parser): parser.addoption('--role', help='U-Boot board role (for Labgrid-sjg)') parser.addoption('--use-running-system', default=False, action='store_true', help="Assume that U-Boot is ready and don't wait for a prompt") + parser.addoption('--timing', default=False, action='store_true', + help='Show info on test timing') + def run_build(config, source_dir, build_dir, board_type, log): """run_build: Build U-Boot @@ -322,6 +326,7 @@ def pytest_configure(config): ubconfig.use_running_system = config.getoption('use_running_system') ubconfig.dtb = build_dir + '/arch/sandbox/dts/test.dtb' ubconfig.connection_ok = True + ubconfig.timing = config.getoption('timing') env_vars = ( 'board_type', @@ -516,6 +521,12 @@ tests_skipped = [] tests_warning = [] tests_passed = [] +# Duration of each test: +# key (string): test name +# value (float): duration in ms +test_durations = {} + + def pytest_itemcollected(item): """pytest hook: Called once for each test found during collection. @@ -531,6 +542,73 @@ def pytest_itemcollected(item): tests_not_run.append(item.name) + +def show_timings(): + """Write timings for each test, along with a histogram""" + + def get_time_delta(msecs): + """Convert milliseconds into a user-friendly string""" + if msecs >= 1000: + return f'{msecs / 1000:.1f}s' + else: + return f'{msecs:.0f}ms' + + def show_bar(key, msecs, value): + """Show a single bar (line) of the histogram + + Args: + key (str): Key to write on the left + value (int): Value to display, i.e. the relative length of the bar + """ + if value: + bar_length = int((value / max_count) * max_bar_length) + print(f"{key:>8} : {get_time_delta(msecs):>7} |{'#' * bar_length} {value}", file=buf) + + # Create the buckets we will use, each has a count and a total time + bucket = {} + for power in range(5): + for i in [1, 2, 3, 4, 5, 7.5]: + bucket[i * 10 ** power] = {'count': 0, 'msecs': 0.0} + max_dur = max(bucket.keys()) + + # Collect counts for each bucket; if outside the range, add to too_long + # Also show a sorted list of test timings from longest to shortest + too_long = 0 + too_long_msecs = 0.0 + max_count = 0 + with log.section('Timing Report', 'timing_report'): + for name, dur in sorted(test_durations.items(), key=lambda kv: kv[1], + reverse=True): + log.info(f'{get_time_delta(dur):>8} {name}') + greater = [k for k in bucket.keys() if dur <= k] + if greater: + buck = bucket[min(greater)] + buck['count'] += 1 + max_count = max(max_count, buck['count']) + buck['msecs'] += dur + else: + too_long += 1 + too_long_msecs += dur + + # Set the maximum length of a histogram bar, in characters + max_bar_length = 40 + + # Show a a summary with histogram + buf = io.StringIO() + with log.section('Timing Summary', 'timing_summary'): + print('Duration : Total | Number of tests', file=buf) + print(f'{"=" * 8} : {"=" * 7} |{"=" * max_bar_length}', file=buf) + for dur, buck in bucket.items(): + if buck['count']: + label = get_time_delta(dur) + show_bar(f'<{label}', buck['msecs'], buck['count']) + if too_long: + show_bar(f'>{get_time_delta(max_dur)}', too_long_msecs, too_long) + log.info(buf.getvalue()) + if ubconfig.timing: + print(buf.getvalue(), end='') + + def cleanup(): """Clean up all global state. @@ -580,6 +658,7 @@ def cleanup(): for test in tests_not_run: anchor = anchors.get(test, None) log.status_fail('... ' + test, anchor) + show_timings() log.close() atexit.register(cleanup) @@ -713,7 +792,9 @@ def pytest_runtest_protocol(item, nextitem): log.get_and_reset_warning() ihook = item.ihook ihook.pytest_runtest_logstart(nodeid=item.nodeid, location=item.location) + start = time.monotonic() reports = runtestprotocol(item, nextitem=nextitem) + duration = round((time.monotonic() - start) * 1000, 1) ihook.pytest_runtest_logfinish(nodeid=item.nodeid, location=item.location) was_warning = log.get_and_reset_warning() @@ -726,6 +807,7 @@ def pytest_runtest_protocol(item, nextitem): start_test_section(item) failure_cleanup = False + record_duration = True if not was_warning: test_list = tests_passed msg = 'OK' @@ -756,6 +838,11 @@ def pytest_runtest_protocol(item, nextitem): test_list = tests_skipped msg = 'SKIPPED:\n' + str(report.longrepr) msg_log = log.status_skipped + record_duration = False + + msg += f' {duration} ms' + if record_duration: + test_durations[item.name] = duration if failure_cleanup: console.drain_console() diff --git a/test/py/tests/test_usb.py b/test/py/tests/test_usb.py index e1f203b5cbc..566d73b7c64 100644 --- a/test/py/tests/test_usb.py +++ b/test/py/tests/test_usb.py @@ -242,7 +242,7 @@ def test_usb_part(u_boot_console): elif part_type == '83': print('ext(2/4) detected') output = u_boot_console.run_command( - 'fstype usb %d:%d' % i, part_id + 'fstype usb %d:%d' % (i, part_id) ) if 'ext2' in output: part_ext2.append(part_id) diff --git a/tools/Kconfig b/tools/Kconfig index 5c75af48fe3..01ff0fcf748 100644 --- a/tools/Kconfig +++ b/tools/Kconfig @@ -9,6 +9,11 @@ config MKIMAGE_DTC_PATH some cases the system dtc may not support all required features and the path to a different version should be given here. +config TOOLS_CRC16 + def_bool y + help + Enable CRC32 support in the tools builds + config TOOLS_CRC32 def_bool y help diff --git a/tools/image-host.c b/tools/image-host.c index 84095d760c1..05d8c898209 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -716,11 +716,20 @@ static int strlist_add(struct strlist *list, const char *str) { char *dup; + if (!list || !str) + return -1; + dup = strdup(str); + if(!dup) + return -1; + list->strings = realloc(list->strings, (list->count + 1) * sizeof(char *)); - if (!list || !str) + if (!list->strings) { + free(dup); return -1; + } + list->strings[list->count++] = dup; return 0; diff --git a/tools/mkenvimage.c b/tools/mkenvimage.c index a8eebab6c33..885cdb1390e 100644 --- a/tools/mkenvimage.c +++ b/tools/mkenvimage.c @@ -28,7 +28,7 @@ static void usage(const char *exec_name) { - fprintf(stderr, "%s [-h] [-r] [-b] [-p <byte>] -s <environment partition size> -o <output> <input file>\n" + fprintf(stderr, "%s [-h] [-V] [-r] [-b] [-p <byte>] -s <environment partition size> -o <output> <input file>\n" "\n" "This tool takes a key=value input file (same as would a `printenv' show) and generates the corresponding environment image, ready to be flashed.\n" "\n" diff --git a/tools/proftool.c b/tools/proftool.c index af2cdb6d584..c7b427f3078 100644 --- a/tools/proftool.c +++ b/tools/proftool.c @@ -676,6 +676,7 @@ static int read_trace_config(FILE *fin) if (!tok) { error("Invalid trace config data on line %d\n", linenum); + free(line); return -1; } if (0 == strcmp(tok, "include-func")) { @@ -685,6 +686,7 @@ static int read_trace_config(FILE *fin) } else { error("Unknown command in trace config data line %d\n", linenum); + free(line); return -1; } @@ -692,6 +694,7 @@ static int read_trace_config(FILE *fin) if (!tok) { error("Missing pattern in trace config data line %d\n", linenum); + free(line); return -1; } diff --git a/tools/ublimage.c b/tools/ublimage.c index 8f9b58c7983..a1bd807bfa0 100644 --- a/tools/ublimage.c +++ b/tools/ublimage.c @@ -178,6 +178,7 @@ static uint32_t parse_cfg_file(struct ubl_header *ublhdr, char *name) lineno, fld, &dcd_len); } } + free(line); fclose(fd); return dcd_len; |