diff options
427 files changed, 14312 insertions, 3603 deletions
diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt new file mode 100644 index 00000000000..fbe6cb21f4c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt @@ -0,0 +1,114 @@ +* ARM L2 Cache Controller + +ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/ +PL310 and variants) based level 2 cache controller. All these various implementations +of the L2 cache controller have compatible programming models (Note 1). +Some of the properties that are just prefixed "cache-*" are taken from section +3.7.3 of the Devicetree Specification which can be found at: +https://www.devicetree.org/specifications/ + +The ARM L2 cache representation in the device tree should be done as follows: + +Required properties: + +- compatible : should be one of: + "arm,pl310-cache" + "arm,l220-cache" + "arm,l210-cache" + "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache" + "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an + offset needs to be added to the address before passing down to the L2 + cache controller + "marvell,aurora-system-cache": Marvell Controller designed to be + compatible with the ARM one, with system cache mode (meaning + maintenance operations on L1 are broadcasted to the L2 and L2 + performs the same operation). + "marvell,aurora-outer-cache": Marvell Controller designed to be + compatible with the ARM one with outer cache mode. + "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible + with arm,pl310-cache controller. +- cache-unified : Specifies the cache is a unified cache. +- cache-level : Should be set to 2 for a level 2 cache. +- reg : Physical base address and size of cache controller's memory mapped + registers. + +Optional properties: + +- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of + read, write and setup latencies. Minimum valid values are 1. Controllers + without setup latency control should use a value of 0. +- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of + read, write and setup latencies. Controllers without setup latency control + should use 0. Controllers without separate read and write Tag RAM latency + values should only use the first cell. +- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell. +- arm,filter-ranges : <start length> Starting address and length of window to + filter. Addresses in the filter window are directed to the M1 port. Other + addresses will go to the M0 port. +- arm,io-coherent : indicates that the system is operating in an hardware + I/O coherent mode. Valid only when the arm,pl310-cache compatible + string is used. +- interrupts : 1 combined interrupt. +- cache-size : specifies the size in bytes of the cache +- cache-sets : specifies the number of associativity sets of the cache +- cache-block-size : specifies the size in bytes of a cache block +- cache-line-size : specifies the size in bytes of a line in the cache, + if this is not specified, the line size is assumed to be equal to the + cache block size +- cache-id-part: cache id part number to be used if it is not present + on hardware +- wt-override: If present then L2 is forced to Write through mode +- arm,double-linefill : Override double linefill enable setting. Enable if + non-zero, disable if zero. +- arm,double-linefill-incr : Override double linefill on INCR read. Enable + if non-zero, disable if zero. +- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable + if non-zero, disable if zero. +- arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero, + disable if zero. +- arm,prefetch-offset : Override prefetch offset value. Valid values are + 0-7, 15, 23, and 31. +- arm,shared-override : The default behavior of the L220 or PL310 cache + controllers with respect to the shareable attribute is to transform "normal + memory non-cacheable transactions" into "cacheable no allocate" (for reads) + or "write through no write allocate" (for writes). + On systems where this may cause DMA buffer corruption, this property must be + specified to indicate that such transforms are precluded. +- arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310). +- arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310). +- arm,outer-sync-disable : disable the outer sync operation on the L2 cache. + Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that + will randomly hang unless outer sync operations are disabled. +- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1> + (forcibly enable), property absent (retain settings set by firmware) +- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable), + <1> (forcibly enable), property absent (retain settings set by + firmware) +- arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly + disable), <1> (forcibly enable), property absent (OS specific behavior, + preferably retain firmware settings) +- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable), + <1> (forcibly enable), property absent (OS specific behavior, + preferably retain firmware settings) +- arm,early-bresp-disable : Disable the CA9 optimization Early BRESP (PL310) +- arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero + write (PL310) + +Example: + +L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xfff12000 0x1000>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <2 2 2>; + arm,filter-ranges = <0x80000000 0x8000000>; + cache-unified; + cache-level = <2>; + interrupts = <45>; +}; + +Note 1: The description in this document doesn't apply to integrated L2 + cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These + integrated L2 controllers are assumed to be all preconfigured by + early secure boot code. Thus no need to deal with their configuration + in the kernel at all. diff --git a/MAINTAINERS b/MAINTAINERS index 09f31cd483b..33fd4652a42 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -239,6 +239,7 @@ F: arch/arm/mach-rmobile/ ARM ROCKCHIP M: Simon Glass <sjg@chromium.org> M: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> +M: Kever Yang <kever.yang@rock-chips.com> S: Maintained T: git git://git.denx.de/u-boot-rockchip.git F: arch/arm/include/asm/arch-rockchip/ @@ -577,6 +578,7 @@ F: configs/mscc* F: drivers/gpio/mscc_sgpio.c F: drivers/spi/mscc_bb_spi.c F: include/configs/vcoreiii.h +F: include/dt-bindings/mscc/ F: drivers/pinctrl/mscc/ F: drivers/net/mscc_eswitch/ @@ -586,7 +588,7 @@ S: Maintained F: arch/mips/mach-jz47xx/ MMC -M: Jaehoon Chung <jh80.chung@samsung.com> +M: Peng Fan <peng.fan@nxp.com> S: Maintained T: git git://git.denx.de/u-boot-mmc.git F: drivers/mmc/ @@ -1120,9 +1120,6 @@ The following options need to be configured: CONFIG_SH_MMCIF_CLK Define the clock frequency for MMCIF - CONFIG_SUPPORT_EMMC_BOOT - Enable some additional features of the eMMC boot partitions. - - USB Device Firmware Update (DFU) class support: CONFIG_DFU_OVER_USB This enables the USB portion of the DFU USB class diff --git a/arch/Kconfig b/arch/Kconfig index 2f3d07c13a1..760023b19a8 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -227,6 +227,15 @@ config SYS_CONFIG_NAME The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h should be included from include/config.h. +config SYS_DISABLE_DCACHE_OPS + bool + help + This option disables dcache flush and dcache invalidation + operations. For example, on coherent systems where cache + operatios are not required, enable this option to avoid them. + Note that, its up to the individual architectures to implement + this functionality. + source "arch/arc/Kconfig" source "arch/arm/Kconfig" source "arch/m68k/Kconfig" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e84f3d7debf..5be959bf8b8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -847,6 +847,7 @@ config ARCH_SOCFPGA imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE imply SPL_SPI_FLASH_SUPPORT imply SPL_SPI_SUPPORT + imply L2X0_CACHE config ARCH_SUNXI bool "Support sunxi (Allwinner) SoCs" @@ -1439,6 +1440,7 @@ config ARCH_ROCKCHIP select SYS_THUMB_BUILD if !ARM64 imply ADC imply CMD_DM + imply DEBUG_UART_BOARD_INIT imply DISTRO_DEFAULTS imply FAT_WRITE imply SARADC_ROCKCHIP diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 038405173eb..9ca397e73c9 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -443,6 +443,7 @@ inline void flush_dcache_all(void) debug("flushing dcache successfully.\n"); } +#ifndef CONFIG_SYS_DISABLE_DCACHE_OPS /* * Invalidates range in all levels of D-cache/unified cache */ @@ -458,6 +459,15 @@ void flush_dcache_range(unsigned long start, unsigned long stop) { __asm_flush_dcache_range(start, stop); } +#else +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ +} +#endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */ void dcache_enable(void) { diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index fe52166e28f..ecee9e37a50 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -26,7 +26,11 @@ _start: * order to boot, allow them to set that in their boot0.h file and then * use it here. */ +#ifdef CONFIG_ARCH_ROCKCHIP +#include <asm/arch-rockchip/boot0.h> +#else #include <asm/arch/boot0.h> +#endif #else b reset #endif diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index a2aa93a7357..97899a567ff 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -79,16 +79,16 @@ SECTIONS } #if defined(IMAGE_MAX_SIZE) -ASSERT(__image_copy_end - __image_copy_start < (IMAGE_MAX_SIZE), \ +ASSERT(__image_copy_end - __image_copy_start <= (IMAGE_MAX_SIZE), \ "SPL image too big"); #endif #if defined(CONFIG_SPL_BSS_MAX_SIZE) -ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \ +ASSERT(__bss_end - __bss_start <= (CONFIG_SPL_BSS_MAX_SIZE), \ "SPL image BSS too big"); #endif #if defined(CONFIG_SPL_MAX_FOOTPRINT) -ASSERT(__bss_end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \ +ASSERT(__bss_end - _start <= (CONFIG_SPL_MAX_FOOTPRINT), \ "SPL image plus BSS too big"); #endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dfa5b029587..8e082f28403 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -74,6 +74,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-fennec.dtb \ rk3288-firefly.dtb \ rk3288-miqi.dtb \ + rk3399-orangepi.dtb \ rk3288-phycore-rdk.dtb \ rk3288-popmetal.dtb \ rk3288-rock2-square.dtb \ @@ -255,6 +256,7 @@ dtb-$(CONFIG_AM33XX) += \ am335x-evmsk.dtb \ am335x-bonegreen.dtb \ am335x-icev2.dtb \ + am335x-pocketbeagle.dtb \ am335x-pxm50.dtb \ am335x-rut.dtb \ am335x-shc.dtb \ diff --git a/arch/arm/dts/am335x-osd335x-common.dtsi b/arch/arm/dts/am335x-osd335x-common.dtsi new file mode 100644 index 00000000000..f8ff473f94f --- /dev/null +++ b/arch/arm/dts/am335x-osd335x-common.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * Author: Robert Nelson <robertcnelson@gmail.com> + */ + +/ { + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; +}; + +&cpu0_opp_table { + /* + * Octavo Systems: + * The EFUSE_SMA register is not programmed for any of the AM335x wafers + * we get and we are not programming them during our production test. + * Therefore, from a DEVICE_ID revision point of view, the silicon looks + * like it is Revision 2.1. However, from an EFUSE_SMA point of view for + * the HW OPP table, the silicon looks like it is Revision 1.0 (ie the + * EFUSE_SMA register reads as all zeros). + */ + oppnitro-1000000000 { + opp-supported-hw = <0x06 0x0100>; + }; +}; + +&am33xx_pinmux { + i2c0_pins: pinmux-i2c0-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; +}; + +/include/ "tps65217.dtsi" + +&tps { + interrupts = <7>; /* NMI */ + interrupt-parent = <&intc>; + + ti,pmic-shutdown-controller; + + pwrbutton { + interrupts = <2>; + status = "okay"; + }; + + regulators { + dcdc1_reg: regulator@0 { + regulator-name = "vdds_dpr"; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1351500>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-name = "vio,vrtc,vdds"; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-name = "vdd_3v3aux"; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-name = "vdd_3v3a"; + regulator-always-on; + }; + }; +}; + +&aes { + status = "okay"; +}; + +&sham { + status = "okay"; +}; diff --git a/arch/arm/dts/am335x-pocketbeagle.dts b/arch/arm/dts/am335x-pocketbeagle.dts new file mode 100644 index 00000000000..62fe5cab9fa --- /dev/null +++ b/arch/arm/dts/am335x-pocketbeagle.dts @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * Author: Robert Nelson <robertcnelson@gmail.com> + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-osd335x-common.dtsi" + +/ { + model = "TI AM335x PocketBeagle"; + compatible = "ti,am335x-pocketbeagle", "ti,am335x-bone", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&usr_leds_pins>; + + compatible = "gpio-leds"; + + usr0 { + label = "beaglebone:green:usr0"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + usr1 { + label = "beaglebone:green:usr1"; + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + usr2 { + label = "beaglebone:green:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + usr3 { + label = "beaglebone:green:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&am33xx_pinmux { + i2c2_pins: pinmux-i2c2-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ + AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ + >; + }; + + ehrpwm0_pins: pinmux-ehrpwm0-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */ + >; + }; + + ehrpwm1_pins: pinmux-ehrpwm1-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* (U14) gpmc_a2.ehrpwm1A */ + >; + }; + + mmc0_pins: pinmux-mmc0-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */ + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */ + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */ + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */ + AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4) /* (B12) mcasp0_aclkr.mmc0_sdwp */ + >; + }; + + spi0_pins: pinmux-spi0-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */ + AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */ + AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */ + AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */ + >; + }; + + spi1_pins: pinmux-spi1-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE4) /* (C18) eCAP0_in_PWM0_out.spi1_sclk */ + AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE4) /* (E18) uart0_ctsn.spi1_d0 */ + AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE4) /* (E17) uart0_rtsn.spi1_d1 */ + AM33XX_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE4) /* (A15) xdma_event_intr0.spi1_cs1 */ + >; + }; + + usr_leds_pins: pinmux-usr-leds-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ + AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ + AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ + AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ + >; + }; + + uart0_pins: pinmux-uart0-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (E16) uart0_txd.uart0_txd */ + >; + }; + + uart4_pins: pinmux-uart4-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ + AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */ + >; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&ehrpwm0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ehrpwm0_pins>; +}; + +&epwmss1 { + status = "okay"; +}; + +&ehrpwm1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ehrpwm1_pins>; +}; + +&i2c0 { + eeprom: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + status = "okay"; + clock-frequency = <400000>; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&rtc { + system-power-controller; +}; + +&tscadc { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + ti,chan-step-avg = <16 16 16 16 16 16 16 16>; + ti,chan-step-opendelay = <0x98 0x98 0x98 0x98 0x98 0x98 0x98 0x98>; + ti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; diff --git a/arch/arm/dts/at91sam9g20-taurus.dts b/arch/arm/dts/at91sam9g20-taurus.dts index cee228bb8cf..c00c5a8b8dd 100644 --- a/arch/arm/dts/at91sam9g20-taurus.dts +++ b/arch/arm/dts/at91sam9g20-taurus.dts @@ -15,7 +15,7 @@ / { model = "Siemens taurus"; - compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9"; + compatible = "atmel,at91sam9g20", "atmel,at91sam9"; chosen { u-boot,dm-pre-reloc; @@ -35,88 +35,86 @@ clock-frequency = <18432000>; }; }; +}; - ahb { - apb { - pinctrl@fffff400 { - board { - pinctrl_pck0_as_mck: pck0_as_mck { - atmel,pins = - <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC1 periph B */ - }; - - }; - }; - - dbgu: serial@fffff200 { - u-boot,dm-pre-reloc; - status = "okay"; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = - <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts - &pinctrl_usart0_dtr_dsr - &pinctrl_usart0_dcd - &pinctrl_usart0_ri>; - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - ssc0: ssc@fffbc000 { - status = "okay"; - pinctrl-0 = <&pinctrl_ssc0_tx>; - }; - - spi0: spi@fffc8000 { - cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; - mtd_dataflash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <50000000>; - reg = <1>; - }; - }; - - rtc@fffffd20 { - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; - status = "okay"; - }; - - watchdog@fffffd40 { - timeout-sec = <15>; - status = "okay"; - }; - - gpbr: syscon@fffffd50 { - status = "okay"; - }; - }; +&dbgu { + status = "okay"; +}; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - }; +&gpbr { + status = "okay"; +}; + +&macb0 { + phy-mode = "rmii"; + status = "okay"; +}; - usb0: ohci@00500000 { - num-ports = <2>; - status = "okay"; +&nand0 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; +}; + +&pinctrl { + u-boot,dm-pre-reloc; + board { + pinctrl_pck0_as_mck: pck0_as_mck { + atmel,pins = + /* PC1 periph B */ + <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; + }; }; + +&rtc { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; +}; + +&spi0 { + cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <50000000>; + reg = <1>; + }; +}; + +&ssc0 { + status = "okay"; + pinctrl-0 = <&pinctrl_ssc0_tx>; +}; + +&usart0 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + &pinctrl_usart0_dtr_dsr + &pinctrl_usart0_dcd + &pinctrl_usart0_ri>; + status = "okay"; +}; + +&usart1 { + status = "okay"; +}; + +&usb0 { + num-ports = <2>; + status = "okay"; +}; + +&usb1 { + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&watchdog { + u-boot,dm-pre-reloc; + timeout-sec = <15>; + status = "okay"; +}; diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index c5d23d0203a..f5c8253831a 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -3,7 +3,7 @@ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ */ -#include <dt-bindings/pinctrl/k3-am65.h> +#include <dt-bindings/pinctrl/k3.h> #include <dt-bindings/dma/k3-udma.h> / { @@ -144,41 +144,41 @@ u-boot,dm-spl; main_uart0_pins_default: main_uart0_pins_default { pinctrl-single,pins = < - AM65X_IOPAD(0x01e4, PIN_INPUT | MUX_MODE0) /* (AF11) UART0_RXD */ - AM65X_IOPAD(0x01e8, PIN_OUTPUT | MUX_MODE0) /* (AE11) UART0_TXD */ - AM65X_IOPAD(0x01ec, PIN_INPUT | MUX_MODE0) /* (AG11) UART0_CTSn */ - AM65X_IOPAD(0x01f0, PIN_OUTPUT | MUX_MODE0) /* (AD11) UART0_RTSn */ + AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ + AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ + AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */ + AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ >; u-boot,dm-spl; }; main_mmc0_pins_default: main_mmc0_pins_default { pinctrl-single,pins = < - AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (B25) MMC0_CLK */ - AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP | MUX_MODE0) /* (B27) MMC0_CMD */ - AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* (A26) MMC0_DAT0 */ - AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP | MUX_MODE0) /* (E25) MMC0_DAT1 */ - AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C26) MMC0_DAT2 */ - AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP | MUX_MODE0) /* (A25) MMC0_DAT3 */ - AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP | MUX_MODE0) /* (E24) MMC0_DAT4 */ - AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP | MUX_MODE0) /* (A24) MMC0_DAT5 */ - AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP | MUX_MODE0) /* (B26) MMC0_DAT6 */ - AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP | MUX_MODE0) /* (D25) MMC0_DAT7 */ - AM65X_IOPAD(0x01b0, PIN_INPUT | MUX_MODE0) /* (C25) MMC0_DS */ + AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ + AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ + AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ + AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ + AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ + AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ + AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ + AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ + AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ + AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ + AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ >; u-boot,dm-spl; }; main_mmc1_pins_default: main_mmc1_pins_default { pinctrl-single,pins = < - AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (C27) MMC1_CLK */ - AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP | MUX_MODE0) /* (C28) MMC1_CMD */ - AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP | MUX_MODE0) /* (D28) MMC1_DAT0 */ - AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP | MUX_MODE0) /* (E27) MMC1_DAT1 */ - AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP | MUX_MODE0) /* (D26) MMC1_DAT2 */ - AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP | MUX_MODE0) /* (D27) MMC1_DAT3 */ - AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP | MUX_MODE0) /* (B24) MMC1_SDCD */ - AM65X_IOPAD(0x02e0, PIN_INPUT | MUX_MODE0) /* (C24) MMC1_SDWP */ + AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ + AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ + AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */ + AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */ + AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */ + AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */ + AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */ + AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */ >; u-boot,dm-spl; }; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index 081a2eceb29..a07038be709 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -99,7 +99,7 @@ }; &dmsc { - mboxes= <&mcu_secproxy 7>, <&mcu_secproxy 6>, <&mcu_secproxy 5>; + mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>; mbox-names = "tx", "rx", "notify"; ti,host-id = <4>; ti,secure-host; @@ -116,17 +116,17 @@ u-boot,dm-spl; wkup_uart0_pins_default: wkup_uart0_pins_default { pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT | MUX_MODE0) /* (AB1) WKUP_UART0_RXD */ - AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT | MUX_MODE0) /* (AB5) WKUP_UART0_TXD */ - AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT | MUX_MODE1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT | MUX_MODE1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */ + AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */ + AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */ >; u-boot,dm-spl; }; wkup_vtt_pins_default: wkup_vtt_pins_default { pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP | MUX_MODE7) /* WKUP_GPIO0_28 */ + AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */ >; u-boot,dm-spl; }; diff --git a/arch/arm/dts/logicpd-som-lv-baseboard.dtsi b/arch/arm/dts/logicpd-som-lv-baseboard.dtsi index 4990ed90dce..3524766515b 100644 --- a/arch/arm/dts/logicpd-som-lv-baseboard.dtsi +++ b/arch/arm/dts/logicpd-som-lv-baseboard.dtsi @@ -152,8 +152,8 @@ interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; - wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ - cd-gpios = <&gpio4 14 IRQ_TYPE_LEVEL_LOW>; /* gpio_110 */ + wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ + cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */ vmmc-supply = <&vmmc1>; bus-width = <4>; cap-power-off-card; diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index ce004d0d18d..9162f3dd508 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -155,7 +155,6 @@ }; &sdmmc { - u-boot,dm-pre-reloc; bus-width = <4>; status = "okay"; }; diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index f90e7e88db1..46f2ffaf8dd 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -592,7 +592,6 @@ }; &sdmmc { - u-boot,dm-pre-reloc; bus-width = <4>; status = "okay"; }; diff --git a/arch/arm/dts/rk3399-opp.dtsi b/arch/arm/dts/rk3399-opp.dtsi new file mode 100644 index 00000000000..d6f1095abb0 --- /dev/null +++ b/arch/arm/dts/rk3399-opp.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/ { + cluster0_opp: opp-table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <800000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <850000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <925000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1125000>; + }; + }; + + cluster1_opp: opp-table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <800000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <825000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <875000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <950000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1025000>; + }; + opp06 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1100000>; + }; + opp07 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1200000>; + }; + }; + + gpu_opp_table: opp-table2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <800000>; + }; + opp01 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <825000>; + }; + opp03 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <875000>; + }; + opp04 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <925000>; + }; + opp05 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1100000>; + }; + }; +}; + +&cpu_l0 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l1 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l2 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l3 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_b0 { + operating-points-v2 = <&cluster1_opp>; +}; + +&cpu_b1 { + operating-points-v2 = <&cluster1_opp>; +}; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +}; diff --git a/arch/arm/dts/rk3399-orangepi-u-boot.dtsi b/arch/arm/dts/rk3399-orangepi-u-boot.dtsi new file mode 100644 index 00000000000..236b61d78dc --- /dev/null +++ b/arch/arm/dts/rk3399-orangepi-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com> + */ + +#include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-ddr3-1333.dtsi" diff --git a/arch/arm/dts/rk3399-orangepi.dts b/arch/arm/dts/rk3399-orangepi.dts new file mode 100644 index 00000000000..cf37b96a6b7 --- /dev/null +++ b/arch/arm/dts/rk3399-orangepi.dts @@ -0,0 +1,771 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "dt-bindings/pwm/pwm.h" +#include "dt-bindings/input/input.h" +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Orange Pi RK3399 Board"; + compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <100000>; + }; + + button-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <300000>; + }; + + back { + label = "Back"; + linux,code = <KEY_BACK>; + press-threshold-microvolt = <985000>; + }; + + menu { + label = "Menu"; + linux,code = <KEY_MENU>; + press-threshold-microvolt = <1314000>; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = <KEY_POWER>; + linux,input-type = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_btn>; + wakeup-source; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc3v0_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_typec0: vcc5v0-typec0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec0_en>; + regulator-name = "vcc5v0_typec0"; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc3v3_s3>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "rtc_clko_soc", "rtc_clko_wifi"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-name = "vcc3v0_tp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmupll: LDO_REG3 { + regulator-name = "vcc1v8_pmupll"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2500000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; + + ak09911@c { + compatible = "asahi-kasei,ak09911"; + reg = <0x0c>; + vdd-supply = <&vcc3v3_s3>; + }; + + mpu6500@68 { + compatible = "invensense,mpu6500"; + reg = <0x68>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&gsensor_int_l>; + vddio-supply = <&vcc3v3_s3>; + }; + + lsm6ds3@6a { + compatible = "st,lsm6ds3"; + reg = <0x6a>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PD0 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&gyr_int_l>; + vdd-supply = <&vcc3v3_s3>; + vddio-supply = <&vcc3v3_s3>; + }; + + cm32181@10 { + compatible = "capella,cm32181"; + reg = <0x10>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PD0 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&light_int_l>; + vdd-supply = <&vcc3v3_s3>; + }; +}; + +&io_domains { + status = "okay"; + bt656-supply = <&vcc_3v0>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_3v0>; +}; + +&pinctrl { + buttons { + pwr_btn: pwr-btn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = + <RK_GPIO0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_typec0_en: vcc5v0-typec0-en { + rockchip,pins = + <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + bluetooth { + bt_reg_on_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mpu6500 { + gsensor_int_l: gsensor-int-l { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lsm6ds3 { + gyr_int_l: gyr-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cm32181 { + light_int_l: light-int-l { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + clock-frequency = <50000000>; + disable-wp; + keep-power-in-suspend; + max-frequency = <50000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + clock-frequency = <150000000>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + phy-supply = <&vcc5v0_typec0>; + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index aec13a28f1a..319a610022c 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -492,7 +492,6 @@ }; &sdmmc { - u-boot,dm-pre-reloc; clock-frequency = <150000000>; max-frequency = <40000000>; supports-sd; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi new file mode 100644 index 00000000000..f533ed95eb7 --- /dev/null +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com> + */ + +&sdmmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts index b620dd8dda5..4be4083941d 100644 --- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts @@ -77,6 +77,7 @@ }; &uart0 { + clock-frequency = <100000000>; u-boot,dm-pre-reloc; }; diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h index a6d66d102ba..db83d0e7d3b 100644 --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h @@ -6,7 +6,7 @@ #ifndef _ASM_ARCH_DDR_RK3188_H #define _ASM_ARCH_DDR_RK3188_H -#include <asm/arch/ddr_rk3288.h> +#include <asm/arch-rockchip/ddr_rk3288.h> /* * RK3188 Memory scheduler register map. diff --git a/arch/arm/include/asm/arch-rockchip/hardware.h b/arch/arm/include/asm/arch-rockchip/hardware.h index cd94bdd1ba3..62e8bed8f31 100644 --- a/arch/arm/include/asm/arch-rockchip/hardware.h +++ b/arch/arm/include/asm/arch-rockchip/hardware.h @@ -10,8 +10,6 @@ #define RK_SETBITS(set) RK_CLRSETBITS(0, set) #define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) -#define TIMER7_BASE 0xff810020 - #define rk_clrsetreg(addr, clr, set) \ writel(((clr) | (set)) << 16 | (set), addr) #define rk_clrreg(addr, clr) writel((clr) << 16, addr) diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 992a84152cf..370031f2acc 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,6 +1,6 @@ #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \ !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \ - !defined(CONFIG_ARCH_BCM63158) + !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) #include <asm/arch/gpio.h> #endif #include <asm-generic/gpio.h> diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index b83978b1cc6..f69e9e45f86 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -18,6 +18,9 @@ #define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) #define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) #define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29) +#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0) +#define L310_LATENCY_CTRL_RD(n) ((n) << 4) +#define L310_LATENCY_CTRL_WR(n) ((n) << 8) #define L2X0_CACHE_ID_PART_MASK (0xf << 6) #define L2X0_CACHE_ID_PART_L310 (3 << 6) diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 2ca6e2494a7..20f485142ef 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -67,8 +67,11 @@ * (1) defines '_start:' as appropriate * (2) inserts the vector table using ARM_VECTORS as appropriate */ +#ifdef CONFIG_ARCH_ROCKCHIP +#include <asm/arch-rockchip/boot0.h> +#else #include <asm/arch/boot0.h> - +#endif #else /* diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds index 3955bea23a1..74f63552297 100644 --- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds +++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds @@ -52,11 +52,11 @@ SECTIONS } #if defined(IMAGE_MAX_SIZE) -ASSERT(__image_copy_end - __start < (IMAGE_MAX_SIZE), \ +ASSERT(__image_copy_end - __start <= (IMAGE_MAX_SIZE), \ "SPL image too big"); #endif #if defined(CONFIG_SPL_BSS_MAX_SIZE) -ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \ +ASSERT(__bss_end - __bss_start <= (CONFIG_SPL_BSS_MAX_SIZE), \ "SPL image BSS too big"); #endif diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index df43b1d7e05..6887fe05dd8 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -12,7 +12,6 @@ obj-$(CONFIG_SOC_DM365) += dm365.o obj-$(CONFIG_SOC_DM644X) += dm644x.o obj-$(CONFIG_SOC_DM646X) += dm646x.o obj-$(CONFIG_SOC_DA850) += da850_pinmux.o -obj-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_FRAMEWORK) += spl.o diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c index aca2f2961d3..f97ad3fc740 100644 --- a/arch/arm/mach-davinci/cpu.c +++ b/arch/arm/mach-davinci/cpu.c @@ -27,25 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PLLC_PLLDIV8 0x170 #define PLLC_PLLDIV9 0x174 -/* SOC-specific pll info */ -#ifdef CONFIG_SOC_DM355 -#define ARM_PLLDIV PLLC_PLLDIV1 -#define DDR_PLLDIV PLLC_PLLDIV1 -#endif - -#ifdef CONFIG_SOC_DM644X -#define ARM_PLLDIV PLLC_PLLDIV2 -#define DSP_PLLDIV PLLC_PLLDIV1 -#define DDR_PLLDIV PLLC_PLLDIV2 -#endif - -#ifdef CONFIG_SOC_DM646X -#define DSP_PLLDIV PLLC_PLLDIV1 -#define ARM_PLLDIV PLLC_PLLDIV2 -#define DDR_PLLDIV PLLC_PLLDIV1 -#endif - -#ifdef CONFIG_SOC_DA8XX unsigned int sysdiv[9] = { PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5, PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9 @@ -110,103 +91,6 @@ int set_cpu_clk_info(void) return 0; } -#else /* CONFIG_SOC_DA8XX */ - -static unsigned pll_div(volatile void *pllbase, unsigned offset) -{ - u32 div; - - div = REG(pllbase + offset); - return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1; -} - -static inline unsigned pll_prediv(volatile void *pllbase) -{ -#ifdef CONFIG_SOC_DM355 - /* this register read seems to fail on pll0 */ - if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE) - return 8; - else - return pll_div(pllbase, PLLC_PREDIV); -#elif defined(CONFIG_SOC_DM365) - return pll_div(pllbase, PLLC_PREDIV); -#endif - return 1; -} - -static inline unsigned pll_postdiv(volatile void *pllbase) -{ -#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365) - return pll_div(pllbase, PLLC_POSTDIV); -#elif defined(CONFIG_SOC_DM6446) - if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE) - return pll_div(pllbase, PLLC_POSTDIV); -#endif - return 1; -} - -static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div) -{ - volatile void *pllbase = (volatile void *) pll_addr; -#ifdef CONFIG_SOC_DM646X - unsigned base = CONFIG_REFCLK_FREQ / 1000; -#else - unsigned base = CONFIG_SYS_HZ_CLOCK / 1000; -#endif - - /* the PLL might be bypassed */ - if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) { - base /= pll_prediv(pllbase); -#if defined(CONFIG_SOC_DM365) - base *= 2 * (readl(pllbase + PLLC_PLLM) & 0x0ff); -#else - base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff); -#endif - base /= pll_postdiv(pllbase); - } - return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div)); -} - -#ifdef DAVINCI_DM6467EVM -unsigned int davinci_arm_clk_get() -{ - return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000; -} -#endif - -#if defined(CONFIG_SOC_DM365) -unsigned int davinci_clk_get(unsigned int div) -{ - return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000; -} -#endif - -int set_cpu_clk_info(void) -{ - unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE; -#if defined(CONFIG_SOC_DM365) - pllbase = DAVINCI_PLL_CNTRL1_BASE; -#endif - gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV); - -#ifdef DSP_PLLDIV - gd->bd->bi_dsp_freq = - pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV); -#else - gd->bd->bi_dsp_freq = 0; -#endif - - pllbase = DAVINCI_PLL_CNTRL1_BASE; -#if defined(CONFIG_SOC_DM365) - pllbase = DAVINCI_PLL_CNTRL0_BASE; -#endif - gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2; - - return 0; -} - -#endif /* !CONFIG_SOC_DA8XX */ - /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c deleted file mode 100644 index bc158d96752..00000000000 --- a/arch/arm/mach-davinci/dm355.c +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SoC-specific code for tms320dm355 and similar chips - * - * Copyright (C) 2009 David Brownell - */ - -#include <common.h> -#include <asm/arch/hardware.h> - - -void davinci_enable_uart0(void) -{ - lpsc_on(DAVINCI_LPSC_UART0); - - /* Bringup UART0 out of reset */ - REG(UART0_PWREMU_MGMT) = 0x00006001; -} - - -#ifdef CONFIG_SYS_I2C_DAVINCI -void davinci_enable_i2c(void) -{ - lpsc_on(DAVINCI_LPSC_I2C); - - /* Enable I2C pin Mux */ - REG(PINMUX3) |= (1 << 20) | (1 << 19); -} -#endif diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c deleted file mode 100644 index 486b9007f24..00000000000 --- a/arch/arm/mach-davinci/dm365.c +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SoC-specific code for tms320dm365 and similar chips - */ - -#include <common.h> -#include <asm/arch/hardware.h> - -void davinci_enable_uart0(void) -{ - lpsc_on(DAVINCI_LPSC_UART0); -} - -#ifdef CONFIG_SYS_I2C_DAVINCI -void davinci_enable_i2c(void) -{ - lpsc_on(DAVINCI_LPSC_I2C); -} -#endif diff --git a/arch/arm/mach-davinci/dm365_lowlevel.c b/arch/arm/mach-davinci/dm365_lowlevel.c deleted file mode 100644 index ad83917402d..00000000000 --- a/arch/arm/mach-davinci/dm365_lowlevel.c +++ /dev/null @@ -1,459 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SoC-specific lowlevel code for tms320dm365 and similar chips - * Actually used for booting from NAND with nand_spl. - * - * Copyright (C) 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ -#include <common.h> -#include <nand.h> -#include <ns16550.h> -#include <post.h> -#include <asm/ti-common/davinci_nand.h> -#include <asm/arch/dm365_lowlevel.h> -#include <asm/arch/hardware.h> - -void dm365_waitloop(unsigned long loopcnt) -{ - unsigned long i; - - for (i = 0; i < loopcnt; i++) - asm(" NOP"); -} - -int dm365_pll1_init(unsigned long pllmult, unsigned long prediv) -{ - unsigned int clksrc = 0x0; - - /* Power up the PLL */ - clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN); - - clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9); - setbits_le32(&dv_pll0_regs->pllctl, - clksrc << PLLCTL_CLOCK_MODE_SHIFT); - - /* - * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled - * through MMR - */ - clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC); - - /* Set PLLEN=0 => PLL BYPASS MODE */ - clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); - - dm365_waitloop(150); - - /* PLLRST=1(reset assert) */ - setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); - - dm365_waitloop(300); - - /*Bring PLL out of Reset*/ - clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); - - /* Program the Multiper and Pre-Divider for PLL1 */ - writel(pllmult, &dv_pll0_regs->pllm); - writel(prediv, &dv_pll0_regs->prediv); - - /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */ - writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE | - PLLSECCTL_TINITZ, &dv_pll0_regs->secctl); - /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */ - writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE, - &dv_pll0_regs->secctl); - /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */ - writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl); - /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */ - writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl); - - /* Program the PostDiv for PLL1 */ - writel(PLL_POSTDEN, &dv_pll0_regs->postdiv); - - /* Post divider setting for PLL1 */ - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1); - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2); - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3); - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4); - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5); - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6); - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7); - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8); - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9); - - dm365_waitloop(300); - - /* Set the GOSET bit */ - writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */ - - dm365_waitloop(300); - - /* Wait for PLL to LOCK */ - while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK) - == PLL0_LOCK)) - ; - - /* Enable the PLL Bit of PLLCTL*/ - setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); - - return 0; -} - -int dm365_pll2_init(unsigned long pllm, unsigned long prediv) -{ - unsigned int clksrc = 0x0; - - /* Power up the PLL*/ - clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN); - - /* - * Select the Clock Mode as Onchip Oscilator or External Clock on - * MXI pin - * VDB has input on MXI pin - */ - clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9); - setbits_le32(&dv_pll1_regs->pllctl, - clksrc << PLLCTL_CLOCK_MODE_SHIFT); - - /* - * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled - * through MMR - */ - clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC); - - /* Set PLLEN=0 => PLL BYPASS MODE */ - clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN); - - dm365_waitloop(50); - - /* PLLRST=1(reset assert) */ - setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST); - - dm365_waitloop(300); - - /* Bring PLL out of Reset */ - clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST); - - /* Program the Multiper and Pre-Divider for PLL2 */ - writel(pllm, &dv_pll1_regs->pllm); - writel(prediv, &dv_pll1_regs->prediv); - - writel(PLL_POSTDEN, &dv_pll1_regs->postdiv); - - /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */ - writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE | - PLLSECCTL_TINITZ, &dv_pll1_regs->secctl); - /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */ - writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE, - &dv_pll1_regs->secctl); - /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */ - writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl); - /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */ - writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl); - - /* Post divider setting for PLL2 */ - writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1); - writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2); - writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3); - writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4); - writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5); - - /* GoCmd for PostDivider to take effect */ - writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd); - - dm365_waitloop(150); - - /* Wait for PLL to LOCK */ - while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK) - == PLL1_LOCK)) - ; - - dm365_waitloop(4100); - - /* Enable the PLL2 */ - setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN); - - /* do this after PLL's have been set up */ - writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL, - &dv_sys_module_regs->peri_clkctl); - - return 0; -} - -int dm365_ddr_setup(void) -{ - lpsc_on(DAVINCI_LPSC_DDR_EMIF); - clrbits_le32(&dv_sys_module_regs->vtpiocr, - VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN); - - /* Set bit CLRZ (bit 13) */ - setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ); - - /* Check VTP READY Status */ - while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY)) - ; - - /* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */ - setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN); - - /* Set bit LOCK(bit7) */ - setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK); - - /* - * Powerdown VTP as it is locked (bit 6) - * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) - */ - setbits_le32(&dv_sys_module_regs->vtpiocr, - VPTIO_IOPWRDN | VPTIO_PWRDN); - - /* Wait for calibration to complete */ - dm365_waitloop(150); - - /* Set the DDR2 to synreset, then enable it again */ - lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF); - lpsc_on(DAVINCI_LPSC_DDR_EMIF); - - writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); - - /* Program SDRAM Bank Config Register */ - writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK), - &dv_ddr2_regs_ctrl->sdbcr); - writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK), - &dv_ddr2_regs_ctrl->sdbcr); - - /* Program SDRAM Timing Control Register1 */ - writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); - /* Program SDRAM Timing Control Register2 */ - writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); - - writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); - - writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr); - - /* Program SDRAM Refresh Control Register */ - writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr); - - lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF); - lpsc_on(DAVINCI_LPSC_DDR_EMIF); - - return 0; -} - -static void dm365_vpss_sync_reset(void) -{ - unsigned int PdNum = 0; - - /* VPSS_CLKMD 1:1 */ - setbits_le32(&dv_sys_module_regs->vpss_clkctl, - VPSS_CLK_CTL_VPSS_CLKMD); - - /* LPSC SyncReset DDR Clock Enable */ - writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) & - ~PSC_MD_STATE_MSK) | PSC_SYNCRESET), - &dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]); - - writel((1 << PdNum), &dv_psc_regs->ptcmd); - - while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0)) - ; - while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) & - PSC_MD_STATE_MSK) == PSC_SYNCRESET)) - ; -} - -static void dm365_por_reset(void) -{ - struct davinci_timer *wdog = - (struct davinci_timer *)DAVINCI_WDOG_BASE; - - if (readl(&dv_pll0_regs->rstype) & - (PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) { - dm365_vpss_sync_reset(); - - writel(DV_TMPBUF_VAL, TMPBUF); - setbits_le32(TMPSTATUS, FLAG_PORRST); - writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1); - writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2); - - while (1); - } -} - -static void dm365_wdt_reset(void) -{ - struct davinci_timer *wdog = - (struct davinci_timer *)DAVINCI_WDOG_BASE; - - if (readl(TMPBUF) != DV_TMPBUF_VAL) { - writel(DV_TMPBUF_VAL, TMPBUF); - setbits_le32(TMPSTATUS, FLAG_PORRST); - setbits_le32(TMPSTATUS, FLAG_FLGOFF); - - dm365_waitloop(100); - - dm365_vpss_sync_reset(); - - writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1); - writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2); - - while (1); - } -} - -static void dm365_wdt_flag_on(void) -{ - /* VPSS_CLKMD 1:2 */ - clrbits_le32(&dv_sys_module_regs->vpss_clkctl, - VPSS_CLK_CTL_VPSS_CLKMD); - writel(0, TMPBUF); - setbits_le32(TMPSTATUS, FLAG_FLGON); -} - -void dm365_psc_init(void) -{ - unsigned char i = 0; - unsigned char lpsc_start; - unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax; - unsigned int PdNum = 0; - - lpscmin = 0; - lpscmax = 2; - - for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) { - if (lpscgroup == 0) { - /* Enabling LPSC 3 to 28 SCR first */ - lpsc_start = DAVINCI_LPSC_VPSSMSTR; - lpsc_end = DAVINCI_LPSC_TIMER1; - } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */ - lpsc_start = DAVINCI_LPSC_CFG5; - lpsc_end = DAVINCI_LPSC_VPSSMASTER; - } else { - lpsc_start = DAVINCI_LPSC_MJCP; - lpsc_end = DAVINCI_LPSC_HDVICP; - } - - /* NEXT=0x3, Enable LPSC's */ - for (i = lpsc_start; i <= lpsc_end; i++) - setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE); - - /* - * Program goctl to start transition sequence for LPSCs - * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power - * Domain 0 Modules - */ - writel((1 << PdNum), &dv_psc_regs->ptcmd); - - /* - * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0 - */ - while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) - == 0)) - ; - - /* Wait for MODSTAT = ENABLE from LPSC's */ - for (i = lpsc_start; i <= lpsc_end; i++) - while (!((readl(&dv_psc_regs->mdstat[i]) & - PSC_MD_STATE_MSK) == PSC_ENABLE)) - ; - } -} - -static void dm365_emif_init(void) -{ - writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr); - writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr); - - setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND); - - writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr); - - return; -} - -void dm365_pinmux_ctl(unsigned long offset, unsigned long mask, - unsigned long value) -{ - clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask); - setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value)); -} - -__attribute__((weak)) -void board_gpio_init(void) -{ - return; -} - -#if defined(CONFIG_POST) -int post_log(char *format, ...) -{ - return 0; -} -#endif - -void dm36x_lowlevel_init(ulong bootflag) -{ - struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs = - (struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 + - DAVINCI_UART_CTRL_BASE); - - /* Mask all interrupts */ - writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl); - writel(0x0, &dv_aintc_regs->eabase); - writel(0x0, &dv_aintc_regs->eint0); - writel(0x0, &dv_aintc_regs->eint1); - - /* Clear all interrupts */ - writel(0xffffffff, &dv_aintc_regs->fiq0); - writel(0xffffffff, &dv_aintc_regs->fiq1); - writel(0xffffffff, &dv_aintc_regs->irq0); - writel(0xffffffff, &dv_aintc_regs->irq1); - - dm365_por_reset(); - dm365_wdt_reset(); - - /* System PSC setup - enable all */ - dm365_psc_init(); - - /* Setup Pinmux */ - dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0); - dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1); - dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2); - dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3); - dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4); - - /* PLL setup */ - dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM, - CONFIG_SYS_DM36x_PLL1_PREDIV); - dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM, - CONFIG_SYS_DM36x_PLL2_PREDIV); - - /* GPIO setup */ - board_gpio_init(); - - NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); - - /* - * Fix Power and Emulation Management Register - * see sprufh2.pdf page 38 Table 22 - */ - writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | - DAVINCI_UART_PWREMU_MGMT_UTRST), - &davinci_uart_ctrl_regs->pwremu_mgmt); - - puts("ddr init\n"); - dm365_ddr_setup(); - - puts("emif init\n"); - dm365_emif_init(); - - dm365_wdt_flag_on(); - -#if defined(CONFIG_POST) - /* - * Do memory tests, calls arch_memory_failure_handle() - * if error detected. - */ - memory_post_test(0); -#endif -} diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c deleted file mode 100644 index 2be6a23711d..00000000000 --- a/arch/arm/mach-davinci/dm644x.c +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SoC-specific code for tms320dm644x chips - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * Copyright (C) 2008 Lyrtech <www.lyrtech.com> - * Copyright (C) 2004 Texas Instruments. - */ - -#include <common.h> -#include <asm/arch/hardware.h> - - -#define PINMUX0_EMACEN (1 << 31) -#define PINMUX0_AECS5 (1 << 11) -#define PINMUX0_AECS4 (1 << 10) - -#define PINMUX1_I2C (1 << 7) -#define PINMUX1_UART1 (1 << 1) -#define PINMUX1_UART0 (1 << 0) - - -void davinci_enable_uart0(void) -{ - lpsc_on(DAVINCI_LPSC_UART0); - - /* Bringup UART0 out of reset */ - REG(UART0_PWREMU_MGMT) = 0x00006001; - - /* Enable UART0 MUX lines */ - REG(PINMUX1) |= PINMUX1_UART0; -} - -#ifdef CONFIG_DRIVER_TI_EMAC -void davinci_enable_emac(void) -{ - lpsc_on(DAVINCI_LPSC_EMAC); - lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); - lpsc_on(DAVINCI_LPSC_MDIO); - - /* Enable GIO3.3V cells used for EMAC */ - REG(VDD3P3V_PWDN) = 0; - - /* Enable EMAC. */ - REG(PINMUX0) |= PINMUX0_EMACEN; -} -#endif - -#ifdef CONFIG_SYS_I2C_DAVINCI -void davinci_enable_i2c(void) -{ - lpsc_on(DAVINCI_LPSC_I2C); - - /* Enable I2C pin Mux */ - REG(PINMUX1) |= PINMUX1_I2C; -} -#endif - -void davinci_errata_workarounds(void) -{ - /* - * Workaround for TMS320DM6446 errata 1.3.22: - * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset - * Revision(s) Affected: 1.3 and earlier - */ - REG(PSC_SILVER_BULLET) = 0; - - /* - * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR) - * as suggested in TMS320DM6446 errata 2.1.2: - * - * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions - * low priority modules can occupy the bus and prevent high priority - * modules like the VPSS from getting the required DDR2 throughput. - * A hex value of 0x20 should provide a good ARM (cache enabled) - * performance and still allow good utilization by the VPSS or other - * modules. - */ - REG(VBPR) = 0x20; -} diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c deleted file mode 100644 index 199c40378d0..00000000000 --- a/arch/arm/mach-davinci/dm646x.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SoC-specific code for TMS320DM646x chips - */ - -#include <asm/arch/hardware.h> - -void davinci_enable_uart0(void) -{ - lpsc_on(DAVINCI_DM646X_LPSC_UART0); -} - -#ifdef CONFIG_DRIVER_TI_EMAC -void davinci_enable_emac(void) -{ - lpsc_on(DAVINCI_DM646X_LPSC_EMAC); -} -#endif - -#ifdef CONFIG_SYS_I2C_DAVINCI -void davinci_enable_i2c(void) -{ - lpsc_on(DAVINCI_DM646X_LPSC_I2C); -} -#endif diff --git a/arch/arm/mach-davinci/dp83848.c b/arch/arm/mach-davinci/dp83848.c deleted file mode 100644 index 7115d7bad24..00000000000 --- a/arch/arm/mach-davinci/dp83848.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * National Semiconductor DP83848 PHY Driver for TI DaVinci - * (TMS320DM644x) based boards. - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * -------------------------------------------------------- - */ - -#include <common.h> -#include <net.h> -#include <dp83848.h> -#include <asm/arch/emac_defs.h> -#include "../../../drivers/net/ti/davinci_emac.h" - -#ifdef CONFIG_DRIVER_TI_EMAC - -#ifdef CONFIG_CMD_NET - -int dp83848_is_phy_connected(int phy_addr) -{ - u_int16_t id1, id2; - - if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1)) - return(0); - if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2)) - return(0); - - if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI)) - return(1); - - return(0); -} - -int dp83848_get_link_speed(int phy_addr) -{ - u_int16_t tmp; - volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR; - - if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp)) - return(0); - - if (!(tmp & DP83848_LINK_STATUS)) /* link up? */ - return(0); - - if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp)) - return(0); - - /* Speed doesn't matter, there is no setting for it in EMAC... */ - if (tmp & DP83848_DUPLEX) { - /* set DM644x EMAC for Full Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | - EMAC_MACCONTROL_FULLDUPLEX_ENABLE; - } else { - /*set DM644x EMAC for Half Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; - } - - return(1); -} - - -int dp83848_init_phy(int phy_addr) -{ - int ret = 1; - - if (!dp83848_get_link_speed(phy_addr)) { - /* Try another time */ - udelay(100000); - ret = dp83848_get_link_speed(phy_addr); - } - - /* Disable PHY Interrupts */ - davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0); - - return(ret); -} - - -int dp83848_auto_negotiate(int phy_addr) -{ - u_int16_t tmp; - - - if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp)) - return(0); - - /* Restart Auto_negotiation */ - tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */ - tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */ - davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); - - /* Set the Auto_negotiation Advertisement Register - * MII advertising for Next page, 100BaseTxFD and HD, - * 10BaseTFD and HD, IEEE 802.3 - */ - tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX | - DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3; - davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp); - - - /* Read Control Register */ - if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp)) - return(0); - - tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE; - davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); - - /* Restart Auto_negotiation */ - tmp |= DP83848_RESTART_AUTONEG; - davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); - - /*check AutoNegotiate complete */ - udelay(10000); - if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp)) - return(0); - - if (!(tmp & DP83848_AUTONEG_COMP)) - return(0); - - return (dp83848_get_link_speed(phy_addr)); -} - -#endif /* CONFIG_CMD_NET */ - -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/arch/arm/mach-davinci/et1011c.c b/arch/arm/mach-davinci/et1011c.c deleted file mode 100644 index bfb7ff26894..00000000000 --- a/arch/arm/mach-davinci/et1011c.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board. - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include <common.h> -#include <net.h> -#include <miiphy.h> -#include <asm/arch/emac_defs.h> -#include "../../../drivers/net/ti/davinci_emac.h" - -#ifdef CONFIG_DRIVER_TI_EMAC - -#ifdef CONFIG_CMD_NET - -/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */ - -#define MII_PHY_CONFIG_REG 22 - -/* PHY Config bits */ -#define PHY_SYS_CLK_EN (1 << 4) - -int et1011c_get_link_speed(int phy_addr) -{ - u_int16_t data; - - if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) { - davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data); - /* Enable 125MHz clock sourced from PHY */ - davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG, - data | PHY_SYS_CLK_EN); - return (1); - } - return (0); -} - -#endif /* CONFIG_CMD_NET */ - -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/arch/arm/mach-davinci/include/mach/da8xx-usb.h b/arch/arm/mach-davinci/include/mach/da8xx-usb.h index 42e1258225b..215706e1729 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx-usb.h +++ b/arch/arm/mach-davinci/include/mach/da8xx-usb.h @@ -86,7 +86,4 @@ struct da8xx_usb_regs { #define DA8XX_USB_VBUS_GPIO (1 << 15) -int usb_phy_on(void); -void usb_phy_off(void); - #endif /* __DA8XX_MUSB_H__ */ diff --git a/arch/arm/mach-davinci/include/mach/davinci_misc.h b/arch/arm/mach-davinci/include/mach/davinci_misc.h index 842be589fa2..48b11f7a5c8 100644 --- a/arch/arm/mach-davinci/include/mach/davinci_misc.h +++ b/arch/arm/mach-davinci/include/mach/davinci_misc.h @@ -40,13 +40,11 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr); int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins); int davinci_configure_pin_mux_items(const struct pinmux_resource *item, int n_items); -#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_SOC_DA8XX) +#if defined(CONFIG_DRIVER_TI_EMAC) void davinci_emac_mii_mode_sel(int mode_sel); #endif -#if defined(CONFIG_SOC_DA8XX) void irq_init(void); int da8xx_configure_lpsc_items(const struct lpsc_resource *item, const int n_items); -#endif #endif /* __MISC_H */ diff --git a/arch/arm/mach-davinci/include/mach/emac_defs.h b/arch/arm/mach-davinci/include/mach/emac_defs.h index b08d06dd247..7c6c19ba0fa 100644 --- a/arch/arm/mach-davinci/include/mach/emac_defs.h +++ b/arch/arm/mach-davinci/include/mach/emac_defs.h @@ -23,71 +23,15 @@ #include <asm/arch/hardware.h> -#ifdef CONFIG_SOC_DM365 -#define EMAC_BASE_ADDR (0x01d07000) -#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000) -#define EMAC_WRAPPER_RAM_ADDR (0x01d08000) -#define EMAC_MDIO_BASE_ADDR (0x01d0b000) -#define DAVINCI_EMAC_VERSION2 -#elif defined(CONFIG_SOC_DA8XX) #define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE #define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE #define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE #define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE #define DAVINCI_EMAC_VERSION2 -#else -#define EMAC_BASE_ADDR (0x01c80000) -#define EMAC_WRAPPER_BASE_ADDR (0x01c81000) -#define EMAC_WRAPPER_RAM_ADDR (0x01c82000) -#define EMAC_MDIO_BASE_ADDR (0x01c84000) -#endif - -#ifdef CONFIG_SOC_DM646X -#define DAVINCI_EMAC_VERSION2 -#define DAVINCI_EMAC_GIG_ENABLE -#endif -#ifdef CONFIG_SOC_DM646X -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ 76500000 -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ -#elif defined(CONFIG_SOC_DM365) -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ 121500000 -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */ -#elif defined(CONFIG_SOC_DA8XX) /* MDIO module input frequency */ #define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID) /* MDIO clock output frequency */ #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ -#else -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */ -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ -#endif - -#define PHY_KSZ8873 (0x00221450) -int ksz8873_is_phy_connected(int phy_addr); -int ksz8873_get_link_speed(int phy_addr); -int ksz8873_init_phy(int phy_addr); -int ksz8873_auto_negotiate(int phy_addr); - -#define PHY_LXT972 (0x001378e2) -int lxt972_is_phy_connected(int phy_addr); -int lxt972_get_link_speed(int phy_addr); -int lxt972_init_phy(int phy_addr); -int lxt972_auto_negotiate(int phy_addr); - -#define PHY_DP83848 (0x20005c90) -int dp83848_is_phy_connected(int phy_addr); -int dp83848_get_link_speed(int phy_addr); -int dp83848_init_phy(int phy_addr); -int dp83848_auto_negotiate(int phy_addr); - -#define PHY_ET1011C (0x282f013) -int et1011c_get_link_speed(int phy_addr); #endif /* _DM644X_EMAC_H_ */ diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index 39819788a1f..3dca50f776b 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -5,21 +5,12 @@ #ifndef _GPIO_DEFS_H_ #define _GPIO_DEFS_H_ -#ifndef CONFIG_SOC_DA8XX -#define DAVINCI_GPIO_BINTEN 0x01C67008 -#define DAVINCI_GPIO_BANK01 0x01C67010 -#define DAVINCI_GPIO_BANK23 0x01C67038 -#define DAVINCI_GPIO_BANK45 0x01C67060 -#define DAVINCI_GPIO_BANK67 0x01C67088 - -#else /* CONFIG_SOC_DA8XX */ #define DAVINCI_GPIO_BINTEN 0x01E26008 #define DAVINCI_GPIO_BANK01 0x01E26010 #define DAVINCI_GPIO_BANK23 0x01E26038 #define DAVINCI_GPIO_BANK45 0x01E26060 #define DAVINCI_GPIO_BANK67 0x01E26088 #define DAVINCI_GPIO_BANK8 0x01E260B0 -#endif /* CONFIG_SOC_DA8XX */ #define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01) #define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23) @@ -31,10 +22,7 @@ #define gpio_status() gpio_info() #endif #define GPIO_NAME_SIZE 20 -#if defined(CONFIG_SOC_DM644X) -/* GPIO0 to GPIO53, omit the V3.3 volts one */ -#define MAX_NUM_GPIOS 70 -#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850) +#if !defined(CONFIG_SOC_DA850) #define MAX_NUM_GPIOS 128 #else #define MAX_NUM_GPIOS 144 diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h index ca5f85a8bbf..4466c6c1d52 100644 --- a/arch/arm/mach-davinci/include/mach/hardware.h +++ b/arch/arm/mach-davinci/include/mach/hardware.h @@ -23,89 +23,6 @@ typedef volatile unsigned int dv_reg; typedef volatile unsigned int * dv_reg_p; #endif -/* - * Base register addresses - * - * NOTE: some of these DM6446-specific addresses DO NOT WORK - * on other DaVinci chips. Double check them before you try - * using the addresses ... or PSC module identifiers, etc. - */ -#ifndef CONFIG_SOC_DA8XX - -#define DAVINCI_DMA_3PCC_BASE (0x01c00000) -#define DAVINCI_DMA_3PTC0_BASE (0x01c10000) -#define DAVINCI_DMA_3PTC1_BASE (0x01c10400) -#define DAVINCI_UART0_BASE (0x01c20000) -#define DAVINCI_UART1_BASE (0x01c20400) -#define DAVINCI_TIMER3_BASE (0x01c20800) -#define DAVINCI_I2C_BASE (0x01c21000) -#define DAVINCI_TIMER0_BASE (0x01c21400) -#define DAVINCI_TIMER1_BASE (0x01c21800) -#define DAVINCI_WDOG_BASE (0x01c21c00) -#define DAVINCI_PWM0_BASE (0x01c22000) -#define DAVINCI_PWM1_BASE (0x01c22400) -#define DAVINCI_PWM2_BASE (0x01c22800) -#define DAVINCI_TIMER4_BASE (0x01c23800) -#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000) -#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800) -#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) -#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000) -#define DAVINCI_ARM_INTC_BASE (0x01c48000) -#define DAVINCI_USB_OTG_BASE (0x01c64000) -#define DAVINCI_CFC_ATA_BASE (0x01c66000) -#define DAVINCI_SPI_BASE (0x01c66800) -#define DAVINCI_GPIO_BASE (0x01c67000) -#define DAVINCI_VPSS_REGS_BASE (0x01c70000) -#if !defined(CONFIG_SOC_DM646X) -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) -#endif -#define DAVINCI_DDR_BASE (0x80000000) - -#ifdef CONFIG_SOC_DM644X -#define DAVINCI_UART2_BASE 0x01c20800 -#define DAVINCI_UHPI_BASE 0x01c67800 -#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000 -#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000 -#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000 -#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000 -#define DAVINCI_IMCOP_BASE 0x01cc0000 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000 -#define DAVINCI_VLYNQ_BASE 0x01e01000 -#define DAVINCI_ASP_BASE 0x01e02000 -#define DAVINCI_MMC_SD_BASE 0x01e10000 -#define DAVINCI_MS_BASE 0x01e20000 -#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000 - -#elif defined(CONFIG_SOC_DM355) -#define DAVINCI_MMC_SD1_BASE 0x01e00000 -#define DAVINCI_ASP0_BASE 0x01e02000 -#define DAVINCI_ASP1_BASE 0x01e04000 -#define DAVINCI_UART2_BASE 0x01e06000 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000 -#define DAVINCI_MMC_SD0_BASE 0x01e11000 - -#elif defined(CONFIG_SOC_DM365) -#define DAVINCI_MMC_SD1_BASE 0x01d00000 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000 -#define DAVINCI_MMC_SD0_BASE 0x01d11000 -#define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000 -#define DAVINCI_SPI0_BASE 0x01c66000 -#define DAVINCI_SPI1_BASE 0x01c66800 - -#elif defined(CONFIG_SOC_DM646X) -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000 -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000 - -#endif - -#else /* CONFIG_SOC_DA8XX */ - #define DAVINCI_UART0_BASE 0x01c42000 #define DAVINCI_UART1_BASE 0x01d0c000 #define DAVINCI_UART2_BASE 0x01d0d000 @@ -162,66 +79,11 @@ typedef volatile unsigned int * dv_reg_p; #define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c) #define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90) #define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94) -#endif /* CONFIG_SOC_DA8XX */ /* Power and Sleep Controller (PSC) Domains */ #define DAVINCI_GPSC_ARMDOMAIN 0 #define DAVINCI_GPSC_DSPDOMAIN 1 -#ifndef CONFIG_SOC_DA8XX - -#define DAVINCI_LPSC_VPSSMSTR 0 -#define DAVINCI_LPSC_VPSSSLV 1 -#define DAVINCI_LPSC_TPCC 2 -#define DAVINCI_LPSC_TPTC0 3 -#define DAVINCI_LPSC_TPTC1 4 -#define DAVINCI_LPSC_EMAC 5 -#define DAVINCI_LPSC_EMAC_WRAPPER 6 -#define DAVINCI_LPSC_MDIO 7 -#define DAVINCI_LPSC_IEEE1394 8 -#define DAVINCI_LPSC_USB 9 -#define DAVINCI_LPSC_ATA 10 -#define DAVINCI_LPSC_VLYNQ 11 -#define DAVINCI_LPSC_UHPI 12 -#define DAVINCI_LPSC_DDR_EMIF 13 -#define DAVINCI_LPSC_AEMIF 14 -#define DAVINCI_LPSC_MMC_SD 15 -#define DAVINCI_LPSC_MEMSTICK 16 -#define DAVINCI_LPSC_McBSP 17 -#define DAVINCI_LPSC_I2C 18 -#define DAVINCI_LPSC_UART0 19 -#define DAVINCI_LPSC_UART1 20 -#define DAVINCI_LPSC_UART2 21 -#define DAVINCI_LPSC_SPI 22 -#define DAVINCI_LPSC_PWM0 23 -#define DAVINCI_LPSC_PWM1 24 -#define DAVINCI_LPSC_PWM2 25 -#define DAVINCI_LPSC_GPIO 26 -#define DAVINCI_LPSC_TIMER0 27 -#define DAVINCI_LPSC_TIMER1 28 -#define DAVINCI_LPSC_TIMER2 29 -#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 -#define DAVINCI_LPSC_ARM 31 -#define DAVINCI_LPSC_SCR2 32 -#define DAVINCI_LPSC_SCR3 33 -#define DAVINCI_LPSC_SCR4 34 -#define DAVINCI_LPSC_CROSSBAR 35 -#define DAVINCI_LPSC_CFG27 36 -#define DAVINCI_LPSC_CFG3 37 -#define DAVINCI_LPSC_CFG5 38 -#define DAVINCI_LPSC_GEM 39 -#define DAVINCI_LPSC_IMCOP 40 -#define DAVINCI_LPSC_VPSSMASTER 47 -#define DAVINCI_LPSC_MJCP 50 -#define DAVINCI_LPSC_HDVICP 51 - -#define DAVINCI_DM646X_LPSC_EMAC 14 -#define DAVINCI_DM646X_LPSC_UART0 26 -#define DAVINCI_DM646X_LPSC_I2C 31 -#define DAVINCI_DM646X_LPSC_TIMER0 34 - -#else /* CONFIG_SOC_DA8XX */ - #define DAVINCI_LPSC_TPCC 0 #define DAVINCI_LPSC_TPTC0 1 #define DAVINCI_LPSC_TPTC1 2 @@ -283,8 +145,6 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29) #define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30) -#endif /* CONFIG_SOC_DA8XX */ - #ifndef __ASSEMBLY__ void lpsc_on(unsigned int id); void lpsc_syncreset(unsigned int id); @@ -296,30 +156,6 @@ void davinci_enable_emac(void); void davinci_enable_i2c(void); void davinci_errata_workarounds(void); -#ifndef CONFIG_SOC_DA8XX - -/* Some PSC defines */ -#define PSC_CHP_SHRTSW (0x01c40038) -#define PSC_GBLCTL (0x01c41010) -#define PSC_EPCPR (0x01c41070) -#define PSC_EPCCR (0x01c41078) -#define PSC_PTCMD (0x01c41120) -#define PSC_PTSTAT (0x01c41128) -#define PSC_PDSTAT (0x01c41200) -#define PSC_PDSTAT1 (0x01c41204) -#define PSC_PDCTL (0x01c41300) -#define PSC_PDCTL1 (0x01c41304) - -#define PSC_MDCTL_BASE (0x01c41a00) -#define PSC_MDSTAT_BASE (0x01c41800) - -#define VDD3P3V_PWDN (0x01c40048) -#define UART0_PWREMU_MGMT (0x01c20030) - -#define PSC_SILVER_BULLET (0x01c41a20) - -#else /* CONFIG_SOC_DA8XX */ - #define PSC_ENABLE 0x3 #define PSC_DISABLE 0x2 #define PSC_SYNCRESET 0x1 @@ -354,41 +190,9 @@ struct davinci_psc_regs { #define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE) #define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE) -#endif /* CONFIG_SOC_DA8XX */ - #define PSC_MDSTAT_STATE 0x3f #define PSC_MDCTL_NEXT 0x07 -#ifndef CONFIG_SOC_DA8XX - -/* Miscellania... */ -#define VBPR (0x20000020) - -/* NOTE: system control modules are *highly* chip-specific, both - * as to register content (e.g. for muxing) and which registers exist. - */ -#define PINMUX0 0x01c40000 -#define PINMUX1 0x01c40004 -#define PINMUX2 0x01c40008 -#define PINMUX3 0x01c4000c -#define PINMUX4 0x01c40010 - -struct davinci_uart_ctrl_regs { - dv_reg revid1; - dv_reg res; - dv_reg pwremu_mgmt; - dv_reg mdr; -}; - -#define DAVINCI_UART_CTRL_BASE 0x28 - -/* UART PWREMU_MGMT definitions */ -#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0) -#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13) -#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14) - -#else /* CONFIG_SOC_DA8XX */ - struct davinci_pllc_regs { dv_reg revid; dv_reg rsvd1[56]; @@ -606,26 +410,6 @@ static inline enum davinci_clk_ids get_async3_src(void) DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2; } -#endif /* CONFIG_SOC_DA8XX */ - -#if defined(CONFIG_SOC_DM365) -#include <asm/arch/aintc_defs.h> -#include <asm/arch/ddr2_defs.h> -#include <asm/arch/gpio.h> -#include <asm/arch/pll_defs.h> -#include <asm/arch/psc_defs.h> -#include <asm/arch/syscfg_defs.h> -#include <asm/arch/timer_defs.h> - -#define TMPBUF 0x00017ff8 -#define TMPSTATUS 0x00017ff0 -#define DV_TMPBUF_VAL 0x591b3ed7 -#define FLAG_PORRST 0x00000001 -#define FLAG_WDTRST 0x00000002 -#define FLAG_FLGON 0x00000004 -#define FLAG_FLGOFF 0x00000010 - -#endif #endif /* !__ASSEMBLY__ */ #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-davinci/include/mach/i2c_defs.h b/arch/arm/mach-davinci/include/mach/i2c_defs.h index 50e31ca3b9a..f12460dd5fd 100644 --- a/arch/arm/mach-davinci/include/mach/i2c_defs.h +++ b/arch/arm/mach-davinci/include/mach/i2c_defs.h @@ -8,10 +8,6 @@ #ifndef _I2C_DEFS_H_ #define _I2C_DEFS_H_ -#ifndef CONFIG_SOC_DA8XX -#define I2C_BASE 0x01c21000 -#else #define I2C_BASE 0x01c22000 -#endif #endif diff --git a/arch/arm/mach-davinci/include/mach/syscfg_defs.h b/arch/arm/mach-davinci/include/mach/syscfg_defs.h deleted file mode 100644 index 41deeda6441..00000000000 --- a/arch/arm/mach-davinci/include/mach/syscfg_defs.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ -#ifndef _DV_SYSCFG_DEFS_H_ -#define _DV_SYSCFG_DEFS_H_ - -#ifndef CONFIG_SOC_DA8XX -/* System Control Module register structure for DM365 */ -struct dv_sys_module_regs { - unsigned int pinmux[5]; /* 0x00 */ - unsigned int bootcfg; /* 0x14 */ - unsigned int arm_intmux; /* 0x18 */ - unsigned int edma_evtmux; /* 0x1C */ - unsigned int ddr_slew; /* 0x20 */ - unsigned int clkout; /* 0x24 */ - unsigned int device_id; /* 0x28 */ - unsigned int vdac_config; /* 0x2C */ - unsigned int timer64_ctl; /* 0x30 */ - unsigned int usbbphy_ctl; /* 0x34 */ - unsigned int misc; /* 0x38 */ - unsigned int mstpri[2]; /* 0x3C */ - unsigned int vpss_clkctl; /* 0x44 */ - unsigned int peri_clkctl; /* 0x48 */ - unsigned int deepsleep; /* 0x4C */ - unsigned int dft_enable; /* 0x50 */ - unsigned int debounce[8]; /* 0x54 */ - unsigned int vtpiocr; /* 0x74 */ - unsigned int pupdctl0; /* 0x78 */ - unsigned int pupdctl1; /* 0x7C */ - unsigned int hdimcopbt; /* 0x80 */ - unsigned int pll0_config; /* 0x84 */ - unsigned int pll1_config; /* 0x88 */ -}; - -#define VPTIO_RDY (1 << 15) -#define VPTIO_IOPWRDN (1 << 14) -#define VPTIO_CLRZ (1 << 13) -#define VPTIO_LOCK (1 << 7) -#define VPTIO_PWRDN (1 << 6) - -#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7) - -#define dv_sys_module_regs \ - ((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE) - -#endif /* !CONFIG_SOC_DA8XX */ -#endif /* _DV_SYSCFG_DEFS_H_ */ diff --git a/arch/arm/mach-davinci/ksz8873.c b/arch/arm/mach-davinci/ksz8873.c deleted file mode 100644 index 85b0c2620c9..00000000000 --- a/arch/arm/mach-davinci/ksz8873.c +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Micrel KSZ8873 PHY Driver for TI DaVinci - * (TMS320DM644x) based boards. - * - * Copyright (C) 2011 Heiko Schocher <hsdenx.de> - * - * based on: - * National Semiconductor DP83848 PHY Driver for TI DaVinci - * (TMS320DM644x) based boards. - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * -------------------------------------------------------- - */ - -#include <common.h> -#include <miiphy.h> -#include <net.h> -#include <asm/arch/emac_defs.h> -#include <asm/io.h> -#include "../../../drivers/net/ti/davinci_emac.h" - -int ksz8873_is_phy_connected(int phy_addr) -{ - u_int16_t dummy; - - return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy); -} - -int ksz8873_get_link_speed(int phy_addr) -{ - emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR; - - /* we always have a link to the switch, 100 FD */ - writel((EMAC_MACCONTROL_MIIEN_ENABLE | - EMAC_MACCONTROL_FULLDUPLEX_ENABLE), - &emac->MACCONTROL); - return 1; -} - - -int ksz8873_init_phy(int phy_addr) -{ - return 1; -} - - -int ksz8873_auto_negotiate(int phy_addr) -{ - return dp83848_get_link_speed(phy_addr); -} diff --git a/arch/arm/mach-davinci/lxt972.c b/arch/arm/mach-davinci/lxt972.c deleted file mode 100644 index b54f67dbfed..00000000000 --- a/arch/arm/mach-davinci/lxt972.c +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Intel LXT971/LXT972 PHY Driver for TI DaVinci - * (TMS320DM644x) based boards. - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * -------------------------------------------------------- - */ - -#include <common.h> -#include <net.h> -#include <miiphy.h> -#include <lxt971a.h> -#include <asm/arch/emac_defs.h> -#include "../../../drivers/net/ti/davinci_emac.h" - -#ifdef CONFIG_DRIVER_TI_EMAC - -#ifdef CONFIG_CMD_NET - -int lxt972_is_phy_connected(int phy_addr) -{ - u_int16_t id1, id2; - - if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1)) - return(0); - if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2)) - return(0); - - if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0)) - return(1); - - return(0); -} - -int lxt972_get_link_speed(int phy_addr) -{ - u_int16_t stat1, tmp; - volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR; - - if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1)) - return(0); - - if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link up? */ - return(0); - - if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) - return(0); - - tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE; - - davinci_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp); - /* Read back */ - if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) - return(0); - - /* Speed doesn't matter, there is no setting for it in EMAC... */ - if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { - /* set DM644x EMAC for Full Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | - EMAC_MACCONTROL_FULLDUPLEX_ENABLE; - } else { - /*set DM644x EMAC for Half Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; - } - - return(1); -} - - -int lxt972_init_phy(int phy_addr) -{ - int ret = 1; - - if (!lxt972_get_link_speed(phy_addr)) { - /* Try another time */ - ret = lxt972_get_link_speed(phy_addr); - } - - /* Disable PHY Interrupts */ - davinci_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0); - - return(ret); -} - - -int lxt972_auto_negotiate(int phy_addr) -{ - u_int16_t tmp; - - if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) - return(0); - - /* Restart Auto_negotiation */ - tmp |= BMCR_ANRESTART; - davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); - - /*check AutoNegotiate complete */ - udelay (10000); - if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) - return(0); - - if (!(tmp & BMSR_ANEGCOMPLETE)) - return(0); - - return (lxt972_get_link_speed(phy_addr)); -} - -#endif /* CONFIG_CMD_NET */ - -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 919041521b9..df500c8f35b 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -68,7 +68,6 @@ err: /* * Set the mii mode as MII or RMII */ -#if defined(CONFIG_SOC_DA8XX) void davinci_emac_mii_mode_sel(int mode_sel) { int val; @@ -80,7 +79,7 @@ void davinci_emac_mii_mode_sel(int mode_sel) val |= (1 << 8); writel(val, &davinci_syscfg_regs->cfgchip3); } -#endif + /* * If there is no MAC address in the environment, then it will be initialized * (silently) from the value in the EEPROM. @@ -106,7 +105,6 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) } #endif /* CONFIG_DRIVER_TI_EMAC */ -#if defined(CONFIG_SOC_DA8XX) void irq_init(void) { /* @@ -135,4 +133,3 @@ int da8xx_configure_lpsc_items(const struct lpsc_resource *item, return 0; } -#endif diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index 9c3ff917bbf..dae10aa03bb 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c @@ -33,19 +33,8 @@ static void lpsc_transition(unsigned int id, unsigned int state) { dv_reg_p mdstat, mdctl, ptstat, ptcmd; -#ifdef CONFIG_SOC_DA8XX struct davinci_psc_regs *psc_regs; -#endif -#ifndef CONFIG_SOC_DA8XX - if (id >= DAVINCI_LPSC_GEM) - return; /* Don't work on DSP Power Domain */ - - mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); - mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); - ptstat = REG_P(PSC_PTSTAT); - ptcmd = REG_P(PSC_PTCMD); -#else if (id < DAVINCI_LPSC_PSC1_BASE) { if (id >= PSC_PSC0_MODULE_ID_CNT) return; @@ -62,7 +51,6 @@ static void lpsc_transition(unsigned int id, unsigned int state) } ptstat = &psc_regs->ptstat; ptcmd = &psc_regs->ptcmd; -#endif while (readl(ptstat) & 0x01) continue; @@ -71,29 +59,6 @@ static void lpsc_transition(unsigned int id, unsigned int state) return; /* Already in that state */ writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl); - - switch (id) { -#ifdef CONFIG_SOC_DM644X - /* Special treatment for some modules as for sprue14 p.7.4.2 */ - case DAVINCI_LPSC_VPSSSLV: - case DAVINCI_LPSC_EMAC: - case DAVINCI_LPSC_EMAC_WRAPPER: - case DAVINCI_LPSC_MDIO: - case DAVINCI_LPSC_USB: - case DAVINCI_LPSC_ATA: - case DAVINCI_LPSC_VLYNQ: - case DAVINCI_LPSC_UHPI: - case DAVINCI_LPSC_DDR_EMIF: - case DAVINCI_LPSC_AEMIF: - case DAVINCI_LPSC_MMC_SD: - case DAVINCI_LPSC_MEMSTICK: - case DAVINCI_LPSC_McBSP: - case DAVINCI_LPSC_GPIO: - writel(readl(mdctl) | 0x200, mdctl); - break; -#endif - } - writel(0x01, ptcmd); while (readl(ptstat) & 0x01) @@ -116,44 +81,3 @@ void lpsc_disable(unsigned int id) { lpsc_transition(id, 0x0); } - -/* Not all DaVinci chips have a DSP power domain. */ -#ifdef CONFIG_SOC_DM644X - -/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */ -#if !defined(CONFIG_SYS_USE_DSPLINK) -void dsp_on(void) -{ - int i; - - if (REG(PSC_PDSTAT1) & 0x1f) - return; /* Already on */ - - REG(PSC_GBLCTL) |= 0x01; - REG(PSC_PDCTL1) |= 0x01; - REG(PSC_PDCTL1) &= ~0x100; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; - REG(PSC_PTCMD) = 0x02; - - for (i = 0; i < 100; i++) { - if (REG(PSC_EPCPR) & 0x02) - break; - } - - REG(PSC_CHP_SHRTSW) = 0x01; - REG(PSC_PDCTL1) |= 0x100; - REG(PSC_EPCCR) = 0x02; - - for (i = 0; i < 100; i++) { - if (!(REG(PSC_PTSTAT) & 0x02)) - break; - } - - REG(PSC_GBLCTL) &= ~0x1f; -} -#endif /* CONFIG_SYS_USE_DSPLINK */ - -#endif /* have a DSP */ diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c index c9aaa4841b1..103639e3475 100644 --- a/arch/arm/mach-davinci/spl.c +++ b/arch/arm/mach-davinci/spl.c @@ -33,12 +33,7 @@ void putc(char c) void spl_board_init(void) { -#ifdef CONFIG_SOC_DM365 - dm36x_lowlevel_init(0); -#endif -#ifdef CONFIG_SOC_DA8XX arch_cpu_init(); -#endif preloader_console_init(); } diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 38077703621..14347e7c7d9 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -116,7 +116,6 @@ config TARGET_SNOW config TARGET_SPRING bool "Spring board" select OF_CONTROL - select SPL_DISABLE_OF_CONTROL select SUPPORT_SPL config TARGET_SMDK5420 @@ -150,7 +149,6 @@ config TARGET_ESPRESSO7420 select OF_CONTROL select PINCTRL select PINCTRL_EXYNOS7420 - select SPL_DISABLE_OF_CONTROL select SUPPORT_SPL endchoice diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index f99bd3bf656..a832e1dc8c9 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -116,6 +116,13 @@ config TARGET_DB_88F6820_AMC config TARGET_TURRIS_OMNIA bool "Support Turris Omnia" select 88F6820 + select BOARD_LATE_INIT + select DM_I2C + select I2C_MUX + select I2C_MUX_PCA954x + select SPL_I2C_MUX + select SYS_I2C_MVTWSI + select ATSHA204A config TARGET_TURRIS_MOX bool "Support Turris Mox" diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 62158a95925..5507348981b 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -38,6 +38,14 @@ #include <asm/omap_musb.h> #include <asm/davinci_rtc.h> +#define AM43XX_EMIF_BASE 0x4C000000 +#define AM43XX_SDRAM_CONFIG_OFFSET 0x8 +#define AM43XX_SDRAM_TYPE_MASK 0xE0000000 +#define AM43XX_SDRAM_TYPE_SHIFT 29 +#define AM43XX_SDRAM_TYPE_DDR3 3 +#define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC +#define AM43XX_RDWRLVLFULL_START 0x80000000 + DECLARE_GLOBAL_DATA_PTR; int dram_init(void) @@ -435,7 +443,7 @@ static void rtc_only(void) struct prm_device_inst *prm_device = (struct prm_device_inst *)PRM_DEVICE_INST; - u32 scratch1; + u32 scratch1, sdrc; void (*resume_func)(void); scratch1 = readl(&rtc->scratch1); @@ -473,8 +481,25 @@ static void rtc_only(void) rtc_only_prcm_init(); sdram_init(); - /* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */ - writel(0, &prm_device->emif_ctrl); + /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */ + /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */ + sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET); + + sdrc &= AM43XX_SDRAM_TYPE_MASK; + sdrc >>= AM43XX_SDRAM_TYPE_SHIFT; + + if (sdrc == AM43XX_SDRAM_TYPE_DDR3) { + writel(AM43XX_RDWRLVLFULL_START, + AM43XX_EMIF_BASE + + AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET); + mdelay(1); + +am43xx_wait: + sdrc = readl(AM43XX_EMIF_BASE + + AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET); + if (sdrc == AM43XX_RDWRLVLFULL_START) + goto am43xx_wait; + } resume_func = (void *)readl(&rtc->scratch0); if (resume_func) diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index be6f4d72ccd..3fd1d086ff1 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -80,6 +80,11 @@ static void configure_mr(int nr, u32 cs) */ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) { +#ifdef CONFIG_AM43XX + struct prm_device_inst *prm_device = + (struct prm_device_inst *)PRM_DEVICE_INST; +#endif + writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl); writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw); writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); @@ -126,6 +131,15 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); +#ifdef CONFIG_AM43XX + /* + * Disable EMIF_DEVOFF + * -> Cold Boot: This is just rewriting the default register value. + * -> RTC Resume: Must disable DEVOFF before leveling. + */ + writel(0, &prm_device->emif_ctrl); +#endif + /* Perform hardware leveling for DDR3 */ if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) { writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) | @@ -138,6 +152,9 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) /* Enable read leveling */ writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl); + /* Wait 1ms because of L3 timeout error */ + udelay(1000); + /* * Enable full read and write leveling. Wait for read and write * leveling bit to clear RDWRLVLFULL_START bit 31 @@ -256,8 +273,16 @@ static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr) * Enable hardware leveling on the EMIF. For details about these * magic values please see the EMIF registers section of the TRM. */ - writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); - writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw); + if (regs->emif_ddr_phy_ctlr_1 & 0x00040000) { + /* PHY_INVERT_CLKOUT = 1 */ + writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); + writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw); + } else { + /* PHY_INVERT_CLKOUT = 0 */ + writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); + writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw); + } + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22); writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw); writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23); @@ -286,8 +311,8 @@ static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr) writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw); writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35); writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw); - writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); - writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); + writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); + writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); /* * Sequence to ensure that the PHY is again in a known state after diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index b9a026abb5c..282d728b82d 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -34,7 +34,6 @@ config ROCKCHIP_RK3188 select SPL_RAM select SPL_DRIVERS_MISC_SUPPORT select SPL_ROCKCHIP_EARLYRETURN_TO_BROM - select DEBUG_UART_BOARD_INIT select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER help @@ -50,7 +49,6 @@ config ROCKCHIP_RK322X select SUPPORT_SPL select SPL select ROCKCHIP_BROM_HELPER - select DEBUG_UART_BOARD_INIT help The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7 including NEON and GPU, Mali-400 graphics, several DDR3 options @@ -102,7 +100,6 @@ config ROCKCHIP_RK3368 imply SPL_SEPARATE_BSS imply SPL_SERIAL_SUPPORT imply TPL_SERIAL_SUPPORT - select DEBUG_UART_BOARD_INIT help The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised into a big and little cluster with 4 cores each) Cortex-A53 including @@ -135,7 +132,6 @@ config ROCKCHIP_RK3399 select SPL_SEPARATE_BSS select SPL_SERIAL_SUPPORT select SPL_DRIVERS_MISC_SUPPORT - select DEBUG_UART_BOARD_INIT select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER help @@ -192,7 +188,7 @@ config ROCKCHIP_BOOT_MODE_REG default 0x10300580 if ROCKCHIP_RV1108 default 0 help - The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h) + The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h) according to the value from this register. config ROCKCHIP_SPL_RESERVE_IRAM diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c index f32b3c4ce56..08f80bd91aa 100644 --- a/arch/arm/mach-rockchip/boot_mode.c +++ b/arch/arm/mach-rockchip/boot_mode.c @@ -6,7 +6,7 @@ #include <common.h> #include <adc.h> #include <asm/io.h> -#include <asm/arch/boot_mode.h> +#include <asm/arch-rockchip/boot_mode.h> #if (CONFIG_ROCKCHIP_BOOT_MODE_REG == 0) diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c index 2f2f73aeddf..9ccb45e6acd 100644 --- a/arch/arm/mach-rockchip/bootrom.c +++ b/arch/arm/mach-rockchip/bootrom.c @@ -4,8 +4,8 @@ */ #include <common.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/boot_mode.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/boot_mode.h> #include <asm/io.h> #include <asm/setjmp.h> #include <asm/system.h> diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 5ec69f13116..110d06dba5e 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -6,31 +6,13 @@ #include <common.h> #include <debug_uart.h> #include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/grf_rk3036.h> -#include <asm/arch/hardware.h> -#include <asm/arch/sdram_rk3036.h> -#include <asm/arch/timer.h> -#include <asm/arch/uart.h> - -#define GRF_BASE 0x20008000 - -#define DEBUG_UART_BASE 0x20068000 +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/sdram_rk3036.h> +#include <asm/arch-rockchip/timer.h> void board_init_f(ulong dummy) { -#ifdef EARLY_DEBUG - struct rk3036_grf * const grf = (void *)GRF_BASE; - /* - * NOTE: sd card and debug uart use same iomux in rk3036, - * so if you enable uart, - * you can not boot from sdcard - */ - rk_clrsetreg(&grf->gpio1c_iomux, - GPIO1C3_MASK << GPIO1C3_SHIFT | - GPIO1C2_MASK << GPIO1C2_SHIFT, - GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | - GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); +#ifdef CONFIG_DEBUG_UART debug_uart_init(); #endif rockchip_timer_init(); diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c index 872bed9606b..2094a4336d0 100644 --- a/arch/arm/mach-rockchip/rk3036-board.c +++ b/arch/arm/mach-rockchip/rk3036-board.c @@ -9,11 +9,11 @@ #include <ram.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/periph.h> -#include <asm/arch/grf_rk3036.h> -#include <asm/arch/boot_mode.h> -#include <asm/arch/sdram_rk3036.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/grf_rk3036.h> +#include <asm/arch-rockchip/boot_mode.h> +#include <asm/arch-rockchip/sdram_rk3036.h> #include <dm/pinctrl.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index c63db343e26..5e04d204482 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -9,7 +9,7 @@ config TARGET_KYLIN_RK3036 select BOARD_LATE_INIT config SYS_SOC - default "rockchip" + default "rk3036" config SYS_MALLOC_F_LEN default 0x400 diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile index 20d28f7c21c..299fc50635d 100644 --- a/arch/arm/mach-rockchip/rk3036/Makefile +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -10,4 +10,5 @@ ifndef CONFIG_SPL_BUILD obj-y += syscon_rk3036.o endif +obj-y += rk3036.o obj-y += sdram_rk3036.o diff --git a/arch/arm/mach-rockchip/rk3036/clk_rk3036.c b/arch/arm/mach-rockchip/rk3036/clk_rk3036.c index 2145c59fcde..20e2ed68132 100644 --- a/arch/arm/mach-rockchip/rk3036/clk_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/clk_rk3036.c @@ -7,8 +7,8 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3036.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3036.h> int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3036/rk3036.c b/arch/arm/mach-rockchip/rk3036/rk3036.c new file mode 100644 index 00000000000..481af8a9344 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/rk3036.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ +#include <asm/io.h> +#include <asm/arch-rockchip/grf_rk3036.h> +#include <asm/arch-rockchip/hardware.h> + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ +#define GRF_BASE 0x20008000 + struct rk3036_grf * const grf = (void *)GRF_BASE; + enum { + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, + GPIO1C3_GPIO = 0, + GPIO1C3_MMC0_D1, + GPIO1C3_UART2_SOUT, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT, + GPIO1C2_GPIO = 0, + GPIO1C2_MMC0_D0, + GPIO1C2_UART2_SIN, + }; + /* + * NOTE: sd card and debug uart use same iomux in rk3036, + * so if you enable uart, + * you can not boot from sdcard + */ + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C3_MASK << GPIO1C3_SHIFT | + GPIO1C2_MASK << GPIO1C2_SHIFT, + GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | + GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); +} +#endif diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index 2012d9fe04d..1d940a0d77c 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -5,12 +5,12 @@ #include <common.h> #include <asm/io.h> #include <asm/types.h> -#include <asm/arch/cru_rk3036.h> -#include <asm/arch/grf_rk3036.h> -#include <asm/arch/hardware.h> -#include <asm/arch/sdram_rk3036.h> -#include <asm/arch/timer.h> -#include <asm/arch/uart.h> +#include <asm/arch-rockchip/cru_rk3036.h> +#include <asm/arch-rockchip/grf_rk3036.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/sdram_rk3036.h> +#include <asm/arch-rockchip/timer.h> +#include <asm/arch-rockchip/uart.h> /* * we can not fit the code to access the device tree in SPL diff --git a/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c b/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c index d3f4cc77f1f..c2fd1607990 100644 --- a/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c @@ -6,7 +6,7 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> static const struct udevice_id rk3036_syscon_ids[] = { { .compatible = "rockchip,rk3036-grf", .data = ROCKCHIP_SYSCON_GRF }, diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c index 7fd667a0b8e..b1c66382e35 100644 --- a/arch/arm/mach-rockchip/rk3128-board.c +++ b/arch/arm/mach-rockchip/rk3128-board.c @@ -8,11 +8,11 @@ #include <ram.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/periph.h> -#include <asm/arch/grf_rk3128.h> -#include <asm/arch/boot_mode.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/grf_rk3128.h> +#include <asm/arch-rockchip/boot_mode.h> +#include <asm/arch-rockchip/timer.h> #include <power/regulator.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig index 40655a22b59..a82b7dc063f 100644 --- a/arch/arm/mach-rockchip/rk3128/Kconfig +++ b/arch/arm/mach-rockchip/rk3128/Kconfig @@ -14,7 +14,7 @@ config TARGET_EVB_RK3128 endchoice config SYS_SOC - default "rockchip" + default "rk3128" config SYS_MALLOC_F_LEN default 0x0800 diff --git a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c index b9b02975792..827750bf98b 100644 --- a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c +++ b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c @@ -6,8 +6,8 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3128.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3128.h> int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c index 8117895434c..1406d5d0d32 100644 --- a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c +++ b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c @@ -6,7 +6,7 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> static const struct udevice_id rk3128_syscon_ids[] = { { .compatible = "rockchip,rk3128-grf", .data = ROCKCHIP_SYSCON_GRF }, diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index 5c09b0e4ae0..77b9b36d357 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -15,14 +15,14 @@ #include <syscon.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3188.h> -#include <asm/arch/hardware.h> -#include <asm/arch/periph.h> -#include <asm/arch/pmu_rk3188.h> -#include <asm/arch/sdram.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3188.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/pmu_rk3188.h> +#include <asm/arch-rockchip/sdram.h> +#include <asm/arch-rockchip/timer.h> #include <dm/pinctrl.h> #include <dm/root.h> #include <dm/test.h> @@ -93,38 +93,12 @@ static int setup_arm_clock(void) return ret; } -void board_debug_uart_init(void) -{ - /* Enable early UART on the RK3188 */ -#define GRF_BASE 0x20008000 - struct rk3188_grf * const grf = (void *)GRF_BASE; - enum { - GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 3, - GPIO1B1_GPIO = 0, - GPIO1B1_UART2_SOUT, - - GPIO1B0_SHIFT = 0, - GPIO1B0_MASK = 3, - GPIO1B0_GPIO = 0, - GPIO1B0_UART2_SIN, - }; - - /* Enable early UART on the RK3188 */ - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B1_MASK << GPIO1B1_SHIFT | - GPIO1B0_MASK << GPIO1B0_SHIFT, - GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | - GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); -} - void board_init_f(ulong dummy) { struct udevice *dev; int ret; -#define EARLY_UART -#ifdef EARLY_UART +#ifdef CONFIG_DEBUG_UART /* * Debug UART can be used from here if required: * diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index 3802395bc07..e03759f7892 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -10,11 +10,11 @@ #include <syscon.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3188.h> -#include <asm/arch/periph.h> -#include <asm/arch/pmu_rk3288.h> -#include <asm/arch/boot_mode.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3188.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/pmu_rk3288.h> +#include <asm/arch-rockchip/boot_mode.h> #include <dm/pinctrl.h> __weak int rk_board_late_init(void) diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig b/arch/arm/mach-rockchip/rk3188/Kconfig index 2bb35662d19..a6fc691fb6c 100644 --- a/arch/arm/mach-rockchip/rk3188/Kconfig +++ b/arch/arm/mach-rockchip/rk3188/Kconfig @@ -10,7 +10,7 @@ config TARGET_ROCK UART and GPIOs. config SYS_SOC - default "rockchip" + default "rk3188" config SYS_MALLOC_F_LEN default 0x0800 diff --git a/arch/arm/mach-rockchip/rk3188/Makefile b/arch/arm/mach-rockchip/rk3188/Makefile index 7fa010405b1..7dc123a3d23 100644 --- a/arch/arm/mach-rockchip/rk3188/Makefile +++ b/arch/arm/mach-rockchip/rk3188/Makefile @@ -6,5 +6,6 @@ ifndef CONFIG_TPL_BUILD obj-y += clk_rk3188.o +obj-y += rk3188.o obj-y += syscon_rk3188.o endif diff --git a/arch/arm/mach-rockchip/rk3188/clk_rk3188.c b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c index e8fcec70cd4..9d4fc37eda9 100644 --- a/arch/arm/mach-rockchip/rk3188/clk_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c @@ -7,8 +7,8 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3188.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3188.h> int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c new file mode 100644 index 00000000000..933484e0df9 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch-rockchip/grf_rk3188.h> +#include <asm/arch-rockchip/hardware.h> + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + /* Enable early UART on the RK3188 */ +#define GRF_BASE 0x20008000 + struct rk3188_grf * const grf = (void *)GRF_BASE; + enum { + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3, + GPIO1B1_GPIO = 0, + GPIO1B1_UART2_SOUT, + GPIO1B1_JTAG_TDO, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 3, + GPIO1B0_GPIO = 0, + GPIO1B0_UART2_SIN, + GPIO1B0_JTAG_TDI, + }; + + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK << GPIO1B1_SHIFT | + GPIO1B0_MASK << GPIO1B0_SHIFT, + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); +} +#endif diff --git a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c index 6572bfa6a2b..94f4ec7227d 100644 --- a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c @@ -7,7 +7,7 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> static const struct udevice_id rk3188_syscon_ids[] = { { .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC }, diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c index 1e718f26942..888310efbe1 100644 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c @@ -9,55 +9,14 @@ #include <ram.h> #include <spl.h> #include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/cru_rk322x.h> -#include <asm/arch/grf_rk322x.h> -#include <asm/arch/hardware.h> -#include <asm/arch/timer.h> -#include <asm/arch/uart.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/timer.h> u32 spl_boot_device(void) { return BOOT_DEVICE_MMC1; } -#define GRF_BASE 0x11000000 -#define SGRF_BASE 0x10140000 - -#define DEBUG_UART_BASE 0x11030000 - -void board_debug_uart_init(void) -{ - static struct rk322x_grf * const grf = (void *)GRF_BASE; - enum { - GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, - GPIO1B2_GPIO = 0, - GPIO1B2_UART1_SIN, - GPIO1B2_UART21_SIN, - - GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, - GPIO1B1_GPIO = 0, - GPIO1B1_UART1_SOUT, - GPIO1B1_UART21_SOUT, - }; - enum { - CON_IOMUX_UART2SEL_SHIFT= 8, - CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT, - CON_IOMUX_UART2SEL_2 = 0, - CON_IOMUX_UART2SEL_21, - }; - - /* Enable early UART2 channel 1 on the RK322x */ - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B1_MASK | GPIO1B2_MASK, - GPIO1B2_UART21_SIN << GPIO1B2_SHIFT | - GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT); - /* Set channel C as UART2 input */ - rk_clrsetreg(&grf->con_iomux, - CON_IOMUX_UART2SEL_MASK, - CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); -} #define SGRF_DDR_CON0 0x10150000 void board_init_f(ulong dummy) @@ -65,6 +24,7 @@ void board_init_f(ulong dummy) struct udevice *dev; int ret; +#ifdef CONFIG_DEBUG_UART /* * Debug UART can be used from here if required: * @@ -75,7 +35,7 @@ void board_init_f(ulong dummy) */ debug_uart_init(); printascii("SPL Init"); - +#endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c index 5659248178a..6170c76f8b9 100644 --- a/arch/arm/mach-rockchip/rk322x-board.c +++ b/arch/arm/mach-rockchip/rk322x-board.c @@ -8,10 +8,10 @@ #include <ram.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/boot_mode.h> -#include <asm/arch/clock.h> -#include <asm/arch/periph.h> -#include <asm/arch/grf_rk322x.h> +#include <asm/arch-rockchip/boot_mode.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk322x.h> +#include <asm/arch-rockchip/periph.h> DECLARE_GLOBAL_DATA_PTR; @@ -29,37 +29,10 @@ int board_late_init(void) int board_init(void) { -#include <asm/arch/grf_rk322x.h> +#include <asm/arch-rockchip/grf_rk322x.h> /* Enable early UART2 channel 1 on the RK322x */ #define GRF_BASE 0x11000000 - struct rk322x_grf * const grf = (void *)GRF_BASE; - enum { - GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, - GPIO1B2_GPIO = 0, - GPIO1B2_UART21_SIN, - - GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, - GPIO1B1_GPIO = 0, - GPIO1B1_UART1_SOUT, - GPIO1B1_UART21_SOUT, - }; - enum { - CON_IOMUX_UART2SEL_SHIFT= 8, - CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT, - CON_IOMUX_UART2SEL_2 = 0, - CON_IOMUX_UART2SEL_21, - }; - - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B1_MASK | GPIO1B2_MASK, - GPIO1B2_UART21_SIN << GPIO1B2_SHIFT | - GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT); - /* Set channel C as UART2 input */ - rk_clrsetreg(&grf->con_iomux, - CON_IOMUX_UART2SEL_MASK, - CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); + static struct rk322x_grf * const grf = (void *)GRF_BASE; /* * The integrated macphy is enabled by default, disable it diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index dc8071e4f3b..8a1f95f7859 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -5,7 +5,7 @@ config TARGET_EVB_RK3229 select BOARD_LATE_INIT config SYS_SOC - default "rockchip" + default "rk322x" config SYS_MALLOC_F_LEN default 0x400 diff --git a/arch/arm/mach-rockchip/rk322x/Makefile b/arch/arm/mach-rockchip/rk322x/Makefile index ecb3e8dfda1..89b0fed6926 100644 --- a/arch/arm/mach-rockchip/rk322x/Makefile +++ b/arch/arm/mach-rockchip/rk322x/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # - obj-y += clk_rk322x.o +obj-y += rk322x.o obj-y += syscon_rk322x.o diff --git a/arch/arm/mach-rockchip/rk322x/clk_rk322x.c b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c index accf9443b00..958c7b82b92 100644 --- a/arch/arm/mach-rockchip/rk322x/clk_rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c @@ -6,8 +6,8 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk322x.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk322x.h> int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c new file mode 100644 index 00000000000..e5250bc7848 --- /dev/null +++ b/arch/arm/mach-rockchip/rk322x/rk322x.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ +#include <asm/io.h> +#include <asm/arch-rockchip/grf_rk322x.h> +#include <asm/arch-rockchip/hardware.h> + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ +#define GRF_BASE 0x11000000 + static struct rk322x_grf * const grf = (void *)GRF_BASE; + enum { + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, + GPIO1B2_GPIO = 0, + GPIO1B2_UART1_SIN, + GPIO1B2_UART21_SIN, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, + GPIO1B1_GPIO = 0, + GPIO1B1_UART1_SOUT, + GPIO1B1_UART21_SOUT, + }; + enum { + CON_IOMUX_UART2SEL_SHIFT = 8, + CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT, + CON_IOMUX_UART2SEL_2 = 0, + CON_IOMUX_UART2SEL_21, + }; + + /* Enable early UART2 channel 1 on the RK322x */ + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK | GPIO1B2_MASK, + GPIO1B2_UART21_SIN << GPIO1B2_SHIFT | + GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT); + /* Set channel C as UART2 input */ + rk_clrsetreg(&grf->con_iomux, + CON_IOMUX_UART2SEL_MASK, + CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); +} +#endif diff --git a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c index 9aa64f8f1f2..0d9dca8173c 100644 --- a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c @@ -6,7 +6,7 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> static const struct udevice_id rk322x_syscon_ids[] = { { .compatible = "rockchip,rk3228-grf", .data = ROCKCHIP_SYSCON_GRF }, diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 93c772184d3..d8d215db8a0 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -14,15 +14,15 @@ #include <spl.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> -#include <asm/arch/periph.h> -#include <asm/arch/pmu_rk3288.h> -#include <asm/arch/sdram.h> -#include <asm/arch/sdram_common.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/pmu_rk3288.h> +#include <asm/arch-rockchip/sdram.h> +#include <asm/arch-rockchip/sdram_common.h> +#include <asm/arch-rockchip/sys_proto.h> +#include <asm/arch-rockchip/timer.h> #include <dm/pinctrl.h> #include <dm/root.h> #include <dm/test.h> @@ -109,16 +109,7 @@ void board_init_f(ulong dummy) struct udevice *dev; int ret; - /* Example code showing how to enable the debug UART on RK3288 */ -#include <asm/arch/grf_rk3288.h> - /* Enable early UART on the RK3288 */ -#define GRF_BASE 0xff770000 - struct rk3288_grf * const grf = (void *)GRF_BASE; - - rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | - GPIO7C6_MASK << GPIO7C6_SHIFT, - GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | - GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); +#ifdef CONFIG_DEBUG_UART /* * Debug UART can be used from here if required: * @@ -129,6 +120,7 @@ void board_init_f(ulong dummy) */ debug_uart_init(); debug("\nspl:debug uart enabled in %s\n", __func__); +#endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); diff --git a/arch/arm/mach-rockchip/rk3288-board-tpl.c b/arch/arm/mach-rockchip/rk3288-board-tpl.c index 2aa63f515a7..787129bbaea 100644 --- a/arch/arm/mach-rockchip/rk3288-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3288-board-tpl.c @@ -10,28 +10,17 @@ #include <spl.h> #include <version.h> #include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3288.h> -#include <asm/arch/periph.h> -#include <asm/arch/pmu_rk3288.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/sys_proto.h> +#include <asm/arch-rockchip/timer.h> -#define GRF_BASE 0xff770000 void board_init_f(ulong dummy) { struct udevice *dev; int ret; - /* Example code showing how to enable the debug UART on RK3288 */ - /* Enable early UART on the RK3288 */ - struct rk3288_grf * const grf = (void *)GRF_BASE; - - rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | - GPIO7C6_MASK << GPIO7C6_SHIFT, - GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | - GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); +#ifdef CONFIG_DEBUG_UART /* * Debug UART can be used from here if required: * @@ -41,7 +30,7 @@ void board_init_f(ulong dummy) * printascii("string"); */ debug_uart_init(); - +#endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 9c4f7f219f1..41e9786d46f 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -9,12 +9,12 @@ #include <ram.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3288.h> -#include <asm/arch/periph.h> -#include <asm/arch/pmu_rk3288.h> -#include <asm/arch/qos_rk3288.h> -#include <asm/arch/boot_mode.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3288.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/pmu_rk3288.h> +#include <asm/arch-rockchip/qos_rk3288.h> +#include <asm/arch-rockchip/boot_mode.h> #include <asm/gpio.h> #include <dm/pinctrl.h> #include <dt-bindings/clock/rk3288-cru.h> @@ -321,7 +321,6 @@ int board_early_init_f(void) { const uintptr_t GRF_SOC_CON0 = 0xff770244; const uintptr_t GRF_SOC_CON2 = 0xff77024c; - struct udevice *pinctrl; struct udevice *dev; int ret; @@ -335,18 +334,7 @@ int board_early_init_f(void) debug("CLK init failed: %d\n", ret); return ret; } - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - return ret; - } - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - return ret; - } rk_setreg(GRF_SOC_CON2, 1 << 0); /* diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index bce80238813..50680ce606b 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -148,7 +148,7 @@ config ROCKCHIP_FAST_SPL and have the required PMIC code. config SYS_SOC - default "rockchip" + default "rk3288" config SYS_MALLOC_F_LEN default 0x0800 diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c index 6ca2271869a..e64ee86f081 100644 --- a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c @@ -7,8 +7,8 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3288.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3288.h> int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index a725abc5a56..7941ca68a64 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -3,16 +3,31 @@ * Copyright (c) 2016 Rockchip Electronics Co., Ltd */ #include <asm/io.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rk3288.h> -#define GRF_SOC_CON2 0xff77024c +#define GRF_BASE 0xff770000 int arch_cpu_init(void) { /* We do some SoC one time setting here. */ + struct rk3288_grf * const grf = (void *)GRF_BASE; /* Use rkpwm by default */ - rk_setreg(GRF_SOC_CON2, 1 << 0); + rk_setreg(&grf->soc_con2, 1 << 0); return 0; } + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + /* Enable early UART on the RK3288 */ + struct rk3288_grf * const grf = (void *)GRF_BASE; + + rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | + GPIO7C6_MASK << GPIO7C6_SHIFT, + GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | + GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); +} +#endif diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c index 3bc80281c73..dff2caa5981 100644 --- a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c @@ -7,7 +7,7 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> static const struct udevice_id rk3288_syscon_ids[] = { { .compatible = "rockchip,rk3288-noc", .data = ROCKCHIP_SYSCON_NOC }, diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index 43afba24304..6c5c4303a35 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -13,7 +13,7 @@ config TARGET_EVB_RK3328 endchoice config SYS_SOC - default "rockchip" + default "rk3328" config SYS_MALLOC_F_LEN default 0x0800 diff --git a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c index e5c2ce5766f..f64f0cbbe56 100644 --- a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c @@ -5,8 +5,8 @@ #include <common.h> #include <dm.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3328.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3328.h> int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index a519f5fb846..1cf829dc343 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -4,7 +4,7 @@ */ #include <common.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include <asm/armv8/mmu.h> #include <asm/io.h> diff --git a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c index 28dd8cb20a5..8a0eceb1787 100644 --- a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c @@ -4,7 +4,7 @@ */ #include <common.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> #include <dm.h> #include <syscon.h> diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c index 230850ad6c5..b055ed4aee0 100644 --- a/arch/arm/mach-rockchip/rk3368-board-spl.c +++ b/arch/arm/mach-rockchip/rk3368-board-spl.c @@ -9,17 +9,9 @@ #include <ram.h> #include <spl.h> #include <asm/io.h> -#include <asm/arch/cru_rk3368.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/hardware.h> -#include <asm/arch/periph.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/periph.h> #include <dm/pinctrl.h> -void board_debug_uart_init(void) -{ -} - void board_init_f(ulong dummy) { struct udevice *pinctrl; diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c index f90a1fdca72..dc65a021c81 100644 --- a/arch/arm/mach-rockchip/rk3368-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3368-board-tpl.c @@ -10,12 +10,11 @@ #include <spl.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3368.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/hardware.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3368.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/timer.h> /* * The SPL (and also the full U-Boot stage on the RK3368) will run in @@ -79,42 +78,12 @@ static void sgrf_init(void) rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ); } -void board_debug_uart_init(void) -{ - /* - * N.B.: This is called before the device-model has been - * initialised. For this reason, we can not access - * the GRF address range using the syscon API. - */ - struct rk3368_grf * const grf = - (struct rk3368_grf * const)0xff770000; - - enum { - GPIO2D1_MASK = GENMASK(3, 2), - GPIO2D1_GPIO = 0, - GPIO2D1_UART0_SOUT = (1 << 2), - - GPIO2D0_MASK = GENMASK(1, 0), - GPIO2D0_GPIO = 0, - GPIO2D0_UART0_SIN = (1 << 0), - }; - -#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) - /* Enable early UART0 on the RK3368 */ - rk_clrsetreg(&grf->gpio2d_iomux, - GPIO2D0_MASK, GPIO2D0_UART0_SIN); - rk_clrsetreg(&grf->gpio2d_iomux, - GPIO2D1_MASK, GPIO2D1_UART0_SOUT); -#endif -} - void board_init_f(ulong dummy) { struct udevice *dev; int ret; -#define EARLY_UART -#ifdef EARLY_UART +#ifdef CONFIG_DEBUG_UART /* * Debug UART can be used from here if required: * diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 7c9b722b002..325572a7e40 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -43,7 +43,7 @@ config TARGET_EVB_PX5 endchoice config SYS_SOC - default "rockchip" + default "rk3368" source "board/theobroma-systems/lion_rk3368/Kconfig" source "board/rockchip/sheep_rk3368/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c index 722160dfdc5..55e5dd768a9 100644 --- a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c @@ -7,8 +7,8 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3368.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3368.h> int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index 6d5d4cc760a..1ed06c5352a 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -7,9 +7,9 @@ #include <common.h> #include <asm/armv8/mmu.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3368.h> -#include <asm/arch/grf_rk3368.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3368.h> +#include <asm/arch-rockchip/grf_rk3368.h> #include <syscon.h> DECLARE_GLOBAL_DATA_PTR; @@ -96,3 +96,34 @@ int arch_early_init_r(void) return mcu_init(); } #endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + /* + * N.B.: This is called before the device-model has been + * initialised. For this reason, we can not access + * the GRF address range using the syscon API. + */ +#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) + struct rk3368_grf * const grf = + (struct rk3368_grf * const)0xff770000; + + enum { + GPIO2D1_MASK = GENMASK(3, 2), + GPIO2D1_GPIO = 0, + GPIO2D1_UART0_SOUT = (1 << 2), + + GPIO2D0_MASK = GENMASK(1, 0), + GPIO2D0_GPIO = 0, + GPIO2D0_UART0_SIN = (1 << 0), + }; + + /* Enable early UART0 on the RK3368 */ + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D0_MASK, GPIO2D0_UART0_SIN); + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D1_MASK, GPIO2D1_UART0_SOUT); +#endif +} +#endif diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c index c08ce437ea4..4ba94f2e805 100644 --- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c @@ -8,7 +8,7 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> static const struct udevice_id rk3368_syscon_ids[] = { { .compatible = "rockchip,rk3368-grf", diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index ccc136f3881..800ca800223 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -12,12 +12,12 @@ #include <spl_gpio.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3399.h> -#include <asm/arch/hardware.h> -#include <asm/arch/periph.h> -#include <asm/arch/sys_proto.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/sys_proto.h> #include <dm/pinctrl.h> void board_return_to_bootrom(void) @@ -127,53 +127,6 @@ void secure_timer_init(void) writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); } -void board_debug_uart_init(void) -{ -#define GRF_BASE 0xff770000 -#define GPIO0_BASE 0xff720000 -#define PMUGRF_BASE 0xff320000 - struct rk3399_grf_regs * const grf = (void *)GRF_BASE; -#ifdef CONFIG_TARGET_CHROMEBOOK_BOB - struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; - struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; -#endif - -#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) - /* Enable early UART0 on the RK3399 */ - rk_clrsetreg(&grf->gpio2c_iomux, - GRF_GPIO2C0_SEL_MASK, - GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT); - rk_clrsetreg(&grf->gpio2c_iomux, - GRF_GPIO2C1_SEL_MASK, - GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT); -#else -# ifdef CONFIG_TARGET_CHROMEBOOK_BOB - rk_setreg(&grf->io_vsel, 1 << 0); - - /* - * Let's enable these power rails here, we are already running the SPI - * Flash based code. - */ - spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */ - spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL); - - spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */ - spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL); -#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ - - /* Enable early UART2 channel C on the RK3399 */ - rk_clrsetreg(&grf->gpio4c_iomux, - GRF_GPIO4C3_SEL_MASK, - GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); - rk_clrsetreg(&grf->gpio4c_iomux, - GRF_GPIO4C4_SEL_MASK, - GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); - /* Set channel C as UART2 input */ - rk_clrsetreg(&grf->soc_con7, - GRF_UART_DBG_SEL_MASK, - GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT); -#endif -} void board_init_f(ulong dummy) { @@ -183,8 +136,7 @@ void board_init_f(ulong dummy) struct rk3399_grf_regs *grf; int ret; -#define EARLY_UART -#ifdef EARLY_UART +#ifdef CONFIG_DEBUG_UART debug_uart_init(); # ifdef CONFIG_TARGET_CHROMEBOOK_BOB diff --git a/arch/arm/mach-rockchip/rk3399-board.c b/arch/arm/mach-rockchip/rk3399-board.c index 137ec714c2e..443c87cccce 100644 --- a/arch/arm/mach-rockchip/rk3399-board.c +++ b/arch/arm/mach-rockchip/rk3399-board.c @@ -4,7 +4,7 @@ */ #include <common.h> -#include <asm/arch/boot_mode.h> +#include <asm/arch-rockchip/boot_mode.h> int board_late_init(void) { diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 2408adb4206..2c5c93c0b85 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -65,7 +65,7 @@ config TARGET_CHROMEBOOK_BOB endchoice config SYS_SOC - default "rockchip" + default "rk3399" config SYS_MALLOC_F_LEN default 0x0800 diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c index 98f7482f79f..f0411c0a21e 100644 --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c @@ -7,8 +7,8 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3399.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3399.h> static int rockchip_get_cruclk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index d8467d73335..a7ccd4f3ed2 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -4,13 +4,17 @@ */ #include <common.h> +#include <spl_gpio.h> #include <asm/armv8/mmu.h> #include <asm/io.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/gpio.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> DECLARE_GLOBAL_DATA_PTR; #define GRF_EMMCCORE_CON11 0xff77f02c +#define GRF_BASE 0xff770000 static struct mm_region rk3399_mem_map[] = { { @@ -48,9 +52,60 @@ int dram_init_banksize(void) int arch_cpu_init(void) { /* We do some SoC one time setting here. */ + struct rk3399_grf_regs * const grf = (void *)GRF_BASE; /* Emmc clock generator: disable the clock multipilier */ - rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff); + rk_clrreg(&grf->emmccore_con[11], 0x0ff); return 0; } + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ +#define GRF_BASE 0xff770000 +#define GPIO0_BASE 0xff720000 +#define PMUGRF_BASE 0xff320000 + struct rk3399_grf_regs * const grf = (void *)GRF_BASE; +#ifdef CONFIG_TARGET_CHROMEBOOK_BOB + struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; + struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; +#endif + +#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) + /* Enable early UART0 on the RK3399 */ + rk_clrsetreg(&grf->gpio2c_iomux, + GRF_GPIO2C0_SEL_MASK, + GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2c_iomux, + GRF_GPIO2C1_SEL_MASK, + GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT); +#else +# ifdef CONFIG_TARGET_CHROMEBOOK_BOB + rk_setreg(&grf->io_vsel, 1 << 0); + + /* + * Let's enable these power rails here, we are already running the SPI + * Flash based code. + */ + spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */ + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL); + + spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */ + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL); +#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ + + /* Enable early UART2 channel C on the RK3399 */ + rk_clrsetreg(&grf->gpio4c_iomux, + GRF_GPIO4C3_SEL_MASK, + GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); + rk_clrsetreg(&grf->gpio4c_iomux, + GRF_GPIO4C4_SEL_MASK, + GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); + /* Set channel C as UART2 input */ + rk_clrsetreg(&grf->soc_con7, + GRF_UART_DBG_SEL_MASK, + GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT); +#endif +} +#endif diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c index 98f4be970f8..a8bb5b11e56 100644 --- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c @@ -6,7 +6,7 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> static const struct udevice_id rk3399_syscon_ids[] = { { .compatible = "rockchip,rk3399-grf", .data = ROCKCHIP_SYSCON_GRF }, diff --git a/arch/arm/mach-rockchip/rk_timer.c b/arch/arm/mach-rockchip/rk_timer.c index e751f29d0f6..f20e64f48ec 100644 --- a/arch/arm/mach-rockchip/rk_timer.c +++ b/arch/arm/mach-rockchip/rk_timer.c @@ -4,7 +4,7 @@ */ #include <common.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/timer.h> #include <asm/io.h> #include <linux/types.h> diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig b/arch/arm/mach-rockchip/rv1108/Kconfig index 8883aeae7a4..e3a63b80e13 100644 --- a/arch/arm/mach-rockchip/rv1108/Kconfig +++ b/arch/arm/mach-rockchip/rv1108/Kconfig @@ -23,7 +23,7 @@ config TARGET_ELGIN_RV1108 RV1108 ELGIN is a board based on the Rockchip RV1108. config SYS_SOC - default "rockchip" + default "rv1108" config SYS_MALLOC_F_LEN default 0x400 diff --git a/arch/arm/mach-rockchip/rv1108/clk_rv1108.c b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c index 5f3705cc390..58a7e889cc3 100644 --- a/arch/arm/mach-rockchip/rv1108/clk_rv1108.c +++ b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c @@ -7,8 +7,8 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rv1108.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rv1108.h> int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c b/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c index 5a0f0a56114..babdf5720b2 100644 --- a/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c +++ b/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c @@ -6,7 +6,7 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> static const struct udevice_id rv1108_syscon_ids[] = { { .compatible = "rockchip,rv1108-grf", .data = ROCKCHIP_SYSCON_GRF }, diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c index a27138083ab..8684dbd4fa6 100644 --- a/arch/arm/mach-rockchip/sdram_common.c +++ b/arch/arm/mach-rockchip/sdram_common.c @@ -7,7 +7,7 @@ #include <dm.h> #include <ram.h> #include <asm/io.h> -#include <asm/arch/sdram_common.h> +#include <asm/arch-rockchip/sdram_common.h> #include <dm/uclass-internal.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 86d5d2b62b0..c3ca8cdf3ba 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -39,6 +39,6 @@ void socfpga_init_security_policies(void); void socfpga_sdram_remap_zero(void); #endif -void do_bridge_reset(int enable); +void do_bridge_reset(int enable, unsigned int mask); #endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h index dd58922cecc..5e490d182e3 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h @@ -9,6 +9,7 @@ #include <dt-bindings/reset/altr,rst-mgr.h> void reset_deassert_peripherals_handoff(void); +void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h); void socfpga_bridges_reset(int enable); struct socfpga_reset_manager { diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index ec8339e0457..d887f0201f7 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -59,20 +59,10 @@ void enable_caches(void) #ifdef CONFIG_SYS_L2_PL310 void v7_outer_cache_enable(void) { - /* Disable the L2 cache */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - - writel(0x0, &pl310->pl310_tag_latency_ctrl); - writel(0x10, &pl310->pl310_data_latency_ctrl); + struct udevice *dev; - /* enable BRESP, instruction and data prefetch, full line of zeroes */ - setbits_le32(&pl310->pl310_aux_ctrl, - L310_AUX_CTRL_DATA_PREFETCH_MASK | - L310_AUX_CTRL_INST_PREFETCH_MASK | - L310_SHARED_ATT_OVERRIDE_ENABLE); - - /* Enable the L2 cache */ - setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + if (uclass_get_device(UCLASS_CACHE, 0, &dev)) + pr_err("cache controller driver NOT found!\n"); } void v7_outer_cache_disable(void) @@ -126,17 +116,22 @@ int arch_cpu_init(void) #ifndef CONFIG_SPL_BUILD static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - if (argc != 2) + unsigned int mask = ~0; + + if (argc < 2 || argc > 3) return CMD_RET_USAGE; argv++; + if (argc == 3) + mask = simple_strtoul(argv[1], NULL, 16); + switch (*argv[0]) { case 'e': /* Enable */ - do_bridge_reset(1); + do_bridge_reset(1, mask); break; case 'd': /* Disable */ - do_bridge_reset(0); + do_bridge_reset(0, mask); break; default: return CMD_RET_USAGE; @@ -145,10 +140,10 @@ static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -U_BOOT_CMD(bridge, 2, 1, do_bridge, +U_BOOT_CMD(bridge, 3, 1, do_bridge, "SoCFPGA HPS FPGA bridge control", - "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" "" ); diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 63b8c75d31d..2e2a40b65dc 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -115,7 +115,7 @@ int print_cpuinfo(void) } #endif -void do_bridge_reset(int enable) +void do_bridge_reset(int enable, unsigned int mask) { if (enable) socfpga_reset_deassert_bridges_handoff(); diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 9865f5b5b12..71547d81ab6 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -210,47 +210,26 @@ static struct socfpga_reset_manager *reset_manager_base = static struct socfpga_sdr_ctrl *sdr_ctrl = (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; -static void socfpga_sdram_apply_static_cfg(void) +void do_bridge_reset(int enable, unsigned int mask) { - const u32 applymask = 0x8; - u32 val = readl(&sdr_ctrl->static_cfg) | applymask; - - /* - * SDRAM staticcfg register specific: - * When applying the register setting, the CPU must not access - * SDRAM. Luckily for us, we can abuse i-cache here to help us - * circumvent the SDRAM access issue. The idea is to make sure - * that the code is in one full i-cache line by branching past - * it and back. Once it is in the i-cache, we execute the core - * of the code and apply the register settings. - * - * The code below uses 7 instructions, while the Cortex-A9 has - * 32-byte cachelines, thus the limit is 8 instructions total. - */ - asm volatile( - ".align 5 \n" - " b 2f \n" - "1: str %0, [%1] \n" - " dsb \n" - " isb \n" - " b 3f \n" - "2: b 1b \n" - "3: nop \n" - : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc"); -} + int i; -void do_bridge_reset(int enable) -{ if (enable) { + socfpga_bridges_set_handoff_regs(!(mask & BIT(0)), + !(mask & BIT(1)), + !(mask & BIT(2))); + for (i = 0; i < 2; i++) { /* Reload SW setting cache */ + iswgrp_handoff[i] = + readl(&sysmgr_regs->iswgrp_handoff[i]); + } + writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); - socfpga_sdram_apply_static_cfg(); writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); writel(iswgrp_handoff[1], &nic301_regs->remap); } else { writel(0, &sysmgr_regs->fpgaintfgrp_module); writel(0, &sdr_ctrl->fpgaport_rst); - socfpga_sdram_apply_static_cfg(); writel(0, &reset_manager_base->brg_mod_reset); writel(1, &nic301_regs->remap); } diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index 113eace650e..60c96090ce1 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -150,7 +150,7 @@ int arch_early_init_r(void) return 0; } -void do_bridge_reset(int enable) +void do_bridge_reset(int enable, unsigned int mask) { socfpga_bridges_reset(enable); } diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c index 25baef79bc2..89a384b59c8 100644 --- a/arch/arm/mach-socfpga/reset_manager_gen5.c +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -73,6 +73,28 @@ void reset_deassert_peripherals_handoff(void) #define L3REGS_REMAP_HPS2FPGA_MASK 0x08 #define L3REGS_REMAP_OCRAM_MASK 0x01 +void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h) +{ + u32 brgmask = 0x0; + u32 l3rmask = L3REGS_REMAP_OCRAM_MASK; + + if (h2f) + brgmask |= BIT(0); + else + l3rmask |= L3REGS_REMAP_HPS2FPGA_MASK; + + if (lwh2f) + brgmask |= BIT(1); + else + l3rmask |= L3REGS_REMAP_LWHPS2FPGA_MASK; + + if (f2h) + brgmask |= BIT(2); + + writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]); + writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]); +} + void socfpga_bridges_reset(int enable) { const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK | @@ -81,10 +103,10 @@ void socfpga_bridges_reset(int enable) if (enable) { /* brdmodrst */ - writel(0xffffffff, &reset_manager_base->brg_mod_reset); + writel(0x7, &reset_manager_base->brg_mod_reset); + writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS); } else { - writel(0, &sysmgr_regs->iswgrp_handoff[0]); - writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]); + socfpga_bridges_set_handoff_regs(false, false, false); /* Check signal from FPGA. */ if (!fpgamgr_test_fpga_ready()) { diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 9dd0afb4bca..bd2a9fe5aed 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -175,8 +175,9 @@ void board_init_f(ulong dummy) sysmgr_pinmux_init(); sysmgr_config_warmrstcfgio(0); - /* De-assert reset for bridges based on handoff */ - socfpga_bridges_reset(0); + /* De-assert reset for peripherals and bridges based on handoff */ + reset_deassert_peripherals_handoff(); + socfpga_bridges_set_handoff_regs(true, true, true); debug("Unfreezing/Thaw all I/O banks\n"); /* unfreeze / thaw all IO banks */ @@ -205,7 +206,4 @@ void board_init_f(ulong dummy) debug("DRAM init failed: %d\n", ret); hang(); } - - if (!socfpga_is_booting_from_fpga()) - socfpga_bridges_reset(1); } diff --git a/arch/microblaze/cpu/u-boot-spl.lds b/arch/microblaze/cpu/u-boot-spl.lds index 99c62b51a1a..3387eb7189d 100644 --- a/arch/microblaze/cpu/u-boot-spl.lds +++ b/arch/microblaze/cpu/u-boot-spl.lds @@ -57,6 +57,6 @@ SECTIONS } #if defined(CONFIG_SPL_MAX_FOOTPRINT) -ASSERT(__end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \ +ASSERT(__end - _start <= (CONFIG_SPL_MAX_FOOTPRINT), \ "SPL image plus BSS too big"); #endif diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 194f4f349ed..9cf8e9800d8 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -74,8 +74,8 @@ config ARCH_BMIPS select SYSRESET imply CMD_DM -config ARCH_MT7620 - bool "Support MT7620/7688 SoCs" +config ARCH_MTMIPS + bool "Support MediaTek MIPS platforms" imply CMD_DM select DISPLAY_CPUINFO select DM @@ -153,7 +153,7 @@ source "arch/mips/mach-mscc/Kconfig" source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-jz47xx/Kconfig" source "arch/mips/mach-pic32/Kconfig" -source "arch/mips/mach-mt7620/Kconfig" +source "arch/mips/mach-mtmips/Kconfig" if MIPS diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 029d290f1e0..af3f227436e 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -15,7 +15,7 @@ machine-$(CONFIG_ARCH_ATH79) += ath79 machine-$(CONFIG_ARCH_BMIPS) += bmips machine-$(CONFIG_ARCH_JZ47XX) += jz47xx machine-$(CONFIG_MACH_PIC32) += pic32 -machine-$(CONFIG_ARCH_MT7620) += mt7620 +machine-$(CONFIG_ARCH_MTMIPS) += mtmips machine-$(CONFIG_ARCH_MSCC) += mscc machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 3522e6cdc82..e2de1da147e 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_ARCH_MT7620) += \ +dtb-$(CONFIG_ARCH_MTMIPS) += \ gardena-smart-gateway-mt7688.dtb \ linkit-smart-7688.dtb dtb-$(CONFIG_TARGET_AP121) += ap121.dtb diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts index fe457bae9d5..ea3e3b7fbd8 100644 --- a/arch/mips/dts/luton_pcb090.dts +++ b/arch/mips/dts/luton_pcb090.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mscc,luton.dtsi" +#include <dt-bindings/mscc/luton_data.h> / { model = "Luton26 PCB090 Reference Board"; @@ -57,52 +58,195 @@ &mdio0 { status = "okay"; -}; - -&port0 { - phy-handle = <&phy0>; -}; - -&port1 { - phy-handle = <&phy1>; -}; - -&port2 { - phy-handle = <&phy2>; -}; - -&port3 { - phy-handle = <&phy3>; -}; - -&port4 { - phy-handle = <&phy4>; -}; - -&port5 { - phy-handle = <&phy5>; -}; - -&port6 { - phy-handle = <&phy6>; -}; - -&port7 { - phy-handle = <&phy7>; -}; -&port8 { - phy-handle = <&phy8>; + phy0: ethernet-phy@0 { + reg = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + }; + phy2: ethernet-phy@2 { + reg = <2>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + }; + phy4: ethernet-phy@4 { + reg = <4>; + }; + phy5: ethernet-phy@5 { + reg = <5>; + }; + phy6: ethernet-phy@6 { + reg = <6>; + }; + phy7: ethernet-phy@7 { + reg = <7>; + }; + phy8: ethernet-phy@8 { + reg = <8>; + }; + phy9: ethernet-phy@9 { + reg = <9>; + }; + phy10: ethernet-phy@10 { + reg = <10>; + }; + phy11: ethernet-phy@11 { + reg = <11>; + }; }; -&port9 { - phy-handle = <&phy9>; -}; +&mdio1 { + status = "okay"; -&port10 { - phy-handle = <&phy10>; + phy12: ethernet-phy@12 { + reg = <0>; + }; + phy13: ethernet-phy@13 { + reg = <1>; + }; + phy14: ethernet-phy@14 { + reg = <2>; + }; + phy15: ethernet-phy@15 { + reg = <3>; + }; + phy16: ethernet-phy@16 { + reg = <4>; + }; + phy17: ethernet-phy@17 { + reg = <5>; + }; + phy18: ethernet-phy@18 { + reg = <6>; + }; + phy19: ethernet-phy@19 { + reg = <7>; + }; + phy20: ethernet-phy@20 { + reg = <8>; + }; + phy21: ethernet-phy@21 { + reg = <9>; + }; + phy22: ethernet-phy@22 { + reg = <10>; + }; + phy23: ethernet-phy@23 { + reg = <11>; + }; }; -&port11 { - phy-handle = <&phy11>; +&switch { + ethernet-ports { + port0: port@0 { + reg = <0>; + phy-handle = <&phy0>; + }; + port1: port@1 { + reg = <1>; + phy-handle = <&phy1>; + }; + port2: port@2 { + reg = <2>; + phy-handle = <&phy2>; + }; + port3: port@3 { + reg = <3>; + phy-handle = <&phy3>; + }; + port4: port@4 { + reg = <4>; + phy-handle = <&phy4>; + }; + port5: port@5 { + reg = <5>; + phy-handle = <&phy5>; + }; + port6: port@6 { + reg = <6>; + phy-handle = <&phy6>; + }; + port7: port@7 { + reg = <7>; + phy-handle = <&phy7>; + }; + port8: port@8 { + reg = <8>; + phy-handle = <&phy8>; + }; + port9: port@9 { + reg = <9>; + phy-handle = <&phy9>; + }; + port10: port@10 { + reg = <10>; + phy-handle = <&phy10>; + }; + port11: port@11 { + reg = <11>; + phy-handle = <&phy11>; + }; + port12: port@12 { + reg = <12>; + phy-handle = <&phy12>; + phys = <&serdes_hsio 12 SERDES6G(1) PHY_MODE_QSGMII>; + }; + port13: port@13 { + reg = <13>; + phy-handle = <&phy13>; + phys = <&serdes_hsio 13 0xff PHY_MODE_QSGMII>; + }; + port14: port@14 { + reg = <14>; + phy-handle = <&phy14>; + phys = <&serdes_hsio 14 0xff PHY_MODE_QSGMII>; + }; + port15: port@15 { + reg = <15>; + phy-handle = <&phy15>; + phys = <&serdes_hsio 15 0xff PHY_MODE_QSGMII>; + }; + port16: port@16 { + reg = <16>; + phy-handle = <&phy16>; + phys = <&serdes_hsio 16 SERDES6G(2) PHY_MODE_QSGMII>; + }; + port17: port@17 { + reg = <17>; + phy-handle = <&phy17>; + phys = <&serdes_hsio 17 0xff PHY_MODE_QSGMII>; + }; + port18: port@18 { + reg = <18>; + phy-handle = <&phy18>; + phys = <&serdes_hsio 18 0xff PHY_MODE_QSGMII>; + }; + port19: port@19 { + reg = <19>; + phy-handle = <&phy19>; + phys = <&serdes_hsio 19 0xff PHY_MODE_QSGMII>; + }; + port20: port@20 { + reg = <20>; + phy-handle = <&phy20>; + phys = <&serdes_hsio 20 SERDES6G(3) PHY_MODE_QSGMII>; + }; + port21: port@21 { + reg = <21>; + phy-handle = <&phy21>; + phys = <&serdes_hsio 21 0xff PHY_MODE_QSGMII>; + }; + port22: port@22 { + reg = <22>; + phy-handle = <&phy22>; + phys = <&serdes_hsio 22 0xff PHY_MODE_QSGMII>; + }; + port23: port@23 { + reg = <23>; + phy-handle = <&phy23>; + phys = <&serdes_hsio 23 0xff PHY_MODE_QSGMII>; + }; + }; }; diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts index f684cc8dd63..cb78c5751bb 100644 --- a/arch/mips/dts/luton_pcb091.dts +++ b/arch/mips/dts/luton_pcb091.dts @@ -63,52 +63,94 @@ &mdio0 { status = "okay"; -}; - -&port0 { - phy-handle = <&phy0>; -}; - -&port1 { - phy-handle = <&phy1>; -}; - -&port2 { - phy-handle = <&phy2>; -}; - -&port3 { - phy-handle = <&phy3>; -}; -&port4 { - phy-handle = <&phy4>; -}; - -&port5 { - phy-handle = <&phy5>; -}; - -&port6 { - phy-handle = <&phy6>; -}; - -&port7 { - phy-handle = <&phy7>; -}; - -&port8 { - phy-handle = <&phy8>; -}; - -&port9 { - phy-handle = <&phy9>; -}; - -&port10 { - phy-handle = <&phy10>; + phy0: ethernet-phy@0 { + reg = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + }; + phy2: ethernet-phy@2 { + reg = <2>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + }; + phy4: ethernet-phy@4 { + reg = <4>; + }; + phy5: ethernet-phy@5 { + reg = <5>; + }; + phy6: ethernet-phy@6 { + reg = <6>; + }; + phy7: ethernet-phy@7 { + reg = <7>; + }; + phy8: ethernet-phy@8 { + reg = <8>; + }; + phy9: ethernet-phy@9 { + reg = <9>; + }; + phy10: ethernet-phy@10 { + reg = <10>; + }; + phy11: ethernet-phy@11 { + reg = <11>; + }; }; -&port11 { - phy-handle = <&phy11>; +&switch { + ethernet-ports { + port0: port@0 { + reg = <0>; + phy-handle = <&phy0>; + }; + port1: port@1 { + reg = <1>; + phy-handle = <&phy1>; + }; + port2: port@2 { + reg = <2>; + phy-handle = <&phy2>; + }; + port3: port@3 { + reg = <3>; + phy-handle = <&phy3>; + }; + port4: port@4 { + reg = <4>; + phy-handle = <&phy4>; + }; + port5: port@5 { + reg = <5>; + phy-handle = <&phy5>; + }; + port6: port@6 { + reg = <6>; + phy-handle = <&phy6>; + }; + port7: port@7 { + reg = <7>; + phy-handle = <&phy7>; + }; + port8: port@8 { + reg = <8>; + phy-handle = <&phy8>; + }; + port9: port@9 { + reg = <9>; + phy-handle = <&phy9>; + }; + port10: port@10 { + reg = <10>; + phy-handle = <&phy10>; + }; + port11: port@11 { + reg = <11>; + phy-handle = <&phy11>; + }; + }; }; diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi index de354fe2ce2..c8231018f10 100644 --- a/arch/mips/dts/mscc,luton.dtsi +++ b/arch/mips/dts/mscc,luton.dtsi @@ -124,7 +124,7 @@ <0x030000 0x1000>, // VTSS_TO_REW <0x070000 0x1000>, // VTSS_TO_DEVCPU_GCB <0x080000 0x0100>, // VTSS_TO_DEVCPU_QS - <0x0a0000 0x0100>; // VTSS_TO_HSIO + <0x0a0000 0x10000>; // VTSS_TO_HSIO reg-names = "port0", "port1", "port2", "port3", "port4", "port5", "port6", "port7", "port8", "port9", "port10", "port11", @@ -137,79 +137,6 @@ ethernet-ports { #address-cells = <1>; #size-cells = <0>; - - port0: port@0 { - reg = <0>; - }; - port1: port@1 { - reg = <1>; - }; - port2: port@2 { - reg = <2>; - }; - port3: port@3 { - reg = <3>; - }; - port4: port@4 { - reg = <4>; - }; - port5: port@5 { - reg = <5>; - }; - port6: port@6 { - reg = <6>; - }; - port7: port@7 { - reg = <7>; - }; - port8: port@8 { - reg = <8>; - }; - port9: port@9 { - reg = <9>; - }; - port10: port@10 { - reg = <10>; - }; - port11: port@11 { - reg = <11>; - }; - port12: port@12 { - reg = <12>; - }; - port13: port@13 { - reg = <13>; - }; - port14: port@14 { - reg = <14>; - }; - port15: port@15 { - reg = <15>; - }; - port16: port@16 { - reg = <16>; - }; - port17: port@17 { - reg = <17>; - }; - port18: port@18 { - reg = <18>; - }; - port19: port@19 { - reg = <19>; - }; - port20: port@20 { - reg = <20>; - }; - port21: port@21 { - reg = <21>; - }; - port22: port@22 { - reg = <22>; - }; - port23: port@23 { - reg = <23>; - }; }; }; @@ -219,42 +146,23 @@ compatible = "mscc,luton-miim"; reg = <0x700a0 0x24>; status = "disabled"; + }; - phy0: ethernet-phy@0 { - reg = <0>; - }; - phy1: ethernet-phy@1 { - reg = <1>; - }; - phy2: ethernet-phy@2 { - reg = <2>; - }; - phy3: ethernet-phy@3 { - reg = <3>; - }; - phy4: ethernet-phy@4 { - reg = <4>; - }; - phy5: ethernet-phy@5 { - reg = <5>; - }; - phy6: ethernet-phy@6 { - reg = <6>; - }; - phy7: ethernet-phy@7 { - reg = <7>; - }; - phy8: ethernet-phy@8 { - reg = <8>; - }; - phy9: ethernet-phy@9 { - reg = <9>; - }; - phy10: ethernet-phy@10 { - reg = <10>; - }; - phy11: ethernet-phy@11 { - reg = <11>; + mdio1: mdio@700c4 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,luton-miim"; + reg = <0x700c4 0x24>; + status = "disabled"; + }; + + hsio: syscon@10d0000 { + compatible = "mscc,luton-hsio", "syscon", "simple-mfd"; + reg = <0xa0000 0x10000>; + + serdes_hsio: serdes_hsio { + compatible = "mscc,vsc7527-serdes"; + #phy-cells = <3>; }; }; }; diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi index 4f3fe356c45..9a187b6e588 100644 --- a/arch/mips/dts/mscc,ocelot.dtsi +++ b/arch/mips/dts/mscc,ocelot.dtsi @@ -112,32 +112,33 @@ status = "disabled"; }; - switch@1010000 { + switch: switch@1010000 { pinctrl-0 = <&miim1_pins>; pinctrl-names = "default"; compatible = "mscc,vsc7514-switch"; - reg = <0x1010000 0x10000>, /* VTSS_TO_SYS */ - <0x1030000 0x10000>, /* VTSS_TO_REW */ - <0x1080000 0x100>, /* VTSS_TO_DEVCPU_QS */ - <0x10d0000 0x10000>, /* VTSS_TO_HSIO */ - <0x11e0000 0x100>, /* VTSS_TO_DEV_0 */ - <0x11f0000 0x100>, /* VTSS_TO_DEV_1 */ - <0x1200000 0x100>, /* VTSS_TO_DEV_2 */ - <0x1210000 0x100>, /* VTSS_TO_DEV_3 */ - <0x1220000 0x100>, /* VTSS_TO_DEV_4 */ - <0x1230000 0x100>, /* VTSS_TO_DEV_5 */ - <0x1240000 0x100>, /* VTSS_TO_DEV_6 */ - <0x1250000 0x100>, /* VTSS_TO_DEV_7 */ - <0x1260000 0x100>, /* VTSS_TO_DEV_8 */ - <0x1270000 0x100>, /* NA */ - <0x1280000 0x100>, /* NA */ - <0x1800000 0x80000>, /* VTSS_TO_QSYS */ - <0x1880000 0x10000>; /* VTSS_TO_ANA */ - reg-names = "sys", "rew", "qs", "hsio", "port0", - "port1", "port2", "port3", "port4", "port5", - "port6", "port7", "port8", "port9", - "port10", "qsys", "ana"; + + reg = <0x11e0000 0x100>, // VTSS_TO_DEV_0 + <0x11f0000 0x100>, // VTSS_TO_DEV_1 + <0x1200000 0x100>, // VTSS_TO_DEV_2 + <0x1210000 0x100>, // VTSS_TO_DEV_3 + <0x1220000 0x100>, // VTSS_TO_DEV_4 + <0x1230000 0x100>, // VTSS_TO_DEV_5 + <0x1240000 0x100>, // VTSS_TO_DEV_6 + <0x1250000 0x100>, // VTSS_TO_DEV_7 + <0x1260000 0x100>, // VTSS_TO_DEV_8 + <0x1270000 0x100>, // VTSS_TO_DEV_9 + <0x1280000 0x100>, // VTSS_TO_DEV_10 + <0x1010000 0x10000>, // VTSS_TO_SYS + <0x1030000 0x10000>, // VTSS_TO_REW + <0x1080000 0x100>, // VTSS_TO_DEVCPU_QS + <0x10d0000 0x10000>, // VTSS_TO_HSIO + <0x1800000 0x80000>,// VTSS_TO_QSYS + <0x1880000 0x10000>;// VTSS_TO_ANA + reg-names = "port0", "port1", "port2", "port3", "port4", + "port5", "port6", "port7", "port8", "port9", + "port10", + "sys", "rew", "qs", "hsio", "qsys", "ana"; interrupts = <21 22>; interrupt-names = "xtr", "inj"; status = "okay"; @@ -145,40 +146,6 @@ ethernet-ports { #address-cells = <1>; #size-cells = <0>; - - port0: port@0 { - reg = <0>; - }; - port1: port@1 { - reg = <1>; - }; - port2: port@2 { - reg = <2>; - }; - port3: port@3 { - reg = <3>; - }; - port4: port@4 { - reg = <4>; - }; - port5: port@5 { - reg = <5>; - }; - port6: port@6 { - reg = <6>; - }; - port7: port@7 { - reg = <7>; - }; - port8: port@8 { - reg = <8>; - }; - port9: port@9 { - reg = <9>; - }; - port10: port@10 { - reg = <10>; - }; }; }; @@ -186,21 +153,27 @@ #address-cells = <1>; #size-cells = <0>; compatible = "mscc,ocelot-miim"; - reg = <0x107009c 0x24>, <0x10700f0 0x8>; + reg = <0x107009c 0x24>; interrupts = <14>; status = "disabled"; + }; - phy0: ethernet-phy@0 { - reg = <0>; - }; - phy1: ethernet-phy@1 { - reg = <1>; - }; - phy2: ethernet-phy@2 { - reg = <2>; - }; - phy3: ethernet-phy@3 { - reg = <3>; + mdio1: mdio@10700f0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,ocelot-miim"; + reg = <0x10700c0 0x24>; + interrupts = <14>; + status = "disabled"; + }; + + hsio: syscon@10d0000 { + compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd"; + reg = <0x10d0000 0x10000>; + + serdes_hsio: serdes_hsio { + compatible = "mscc,vsc7514-serdes"; + #phy-cells = <3>; }; }; diff --git a/arch/mips/dts/mscc,serval.dtsi b/arch/mips/dts/mscc,serval.dtsi index bd60051719b..90eeebd3a4e 100644 --- a/arch/mips/dts/mscc,serval.dtsi +++ b/arch/mips/dts/mscc,serval.dtsi @@ -145,5 +145,63 @@ #gpio-cells = <2>; gpio-ranges = <&sgpio 0 0 64>; }; + + switch: switch@011e0000 { + compatible = "mscc,vsc7418-switch"; + reg = <0x011e0000 0x0100>, // VTSS_TO_DEV0 + <0x011f0000 0x0100>, // VTSS_TO_DEV1 + <0x01200000 0x0100>, // VTSS_TO_DEV2 + <0x01210000 0x0100>, // VTSS_TO_DEV3 + <0x01220000 0x0100>, // VTSS_TO_DEV4 + <0x01230000 0x0100>, // VTSS_TO_DEV5 + <0x01240000 0x0100>, // VTSS_TO_DEV6 + <0x01250000 0x0100>, // VTSS_TO_DEV7 + <0x01260000 0x0100>, // VTSS_TO_DEV8 + <0x01270000 0x0100>, // VTSS_TO_DEV9 + <0x01280000 0x0100>, // VTSS_TO_DEV10 + <0x01900000 0x100000>, // ANA + <0x01080000 0x20000>, // QS + <0x01800000 0x100000>, // QSYS + <0x01030000 0x10000>, // REW + <0x01010000 0x20000>, // SYS + <0x010a0000 0x10000>; // HSIO + reg-names = "port0", "port1", "port2", "port3", + "port4", "port5", "port6", "port7", + "port8", "port9", "port10", + "ana", "qs", "qsys", "rew", "sys", + "hsio"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio0: mdio@0107005c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,serval-miim"; + reg = <0x0107005c 0x24>; + status = "disabled"; + }; + + mdio1: mdio@01070080 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,serval-miim"; + reg = <0x01070080 0x24>; + status = "disabled"; + }; + + hsio: syscon@10d0000 { + compatible = "mscc,serval-hsio", "syscon", "simple-mfd"; + reg = <0x10a0000 0x10000>; + + serdes_hsio: serdes_hsio { + compatible = "mscc,vsc7418-serdes"; + #phy-cells = <3>; + }; + }; }; }; diff --git a/arch/mips/dts/ocelot_pcb120.dts b/arch/mips/dts/ocelot_pcb120.dts index 658719e684f..e608029a3f8 100644 --- a/arch/mips/dts/ocelot_pcb120.dts +++ b/arch/mips/dts/ocelot_pcb120.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mscc,ocelot_pcb.dtsi" +#include <dt-bindings/mscc/ocelot_data.h> / { model = "Ocelot PCB120 Reference Board"; @@ -86,3 +87,77 @@ mscc,sgpio-ports = <0x000FFFFF>; }; +&mdio0 { + status = "okay"; + + phy4: ethernet-phy@4 { + reg = <3>; + }; + phy5: ethernet-phy@5 { + reg = <2>; + }; + phy6: ethernet-phy@6 { + reg = <1>; + }; + phy7: ethernet-phy@7 { + reg = <0>; + }; +}; + +&mdio1 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <3>; + }; + phy1: ethernet-phy@1 { + reg = <2>; + }; + phy2: ethernet-phy@2 { + reg = <1>; + }; + phy3: ethernet-phy@3 { + reg = <0>; + }; +}; + +&switch { + ethernet-ports { + port0: port@0 { + reg = <5>; + phy-handle = <&phy0>; + phys = <&serdes_hsio 5 SERDES1G(2) PHY_MODE_SGMII>; + }; + port1: port@1 { + reg = <9>; + phy-handle = <&phy1>; + phys = <&serdes_hsio 9 SERDES1G(3) PHY_MODE_SGMII>; + }; + port2: port@2 { + reg = <6>; + phy-handle = <&phy2>; + phys = <&serdes_hsio 6 SERDES1G(4) PHY_MODE_SGMII>; + }; + port3: port@3 { + reg = <4>; + phy-handle = <&phy3>; + phys = <&serdes_hsio 4 SERDES1G(5) PHY_MODE_SGMII>; + }; + port4: port@4 { + reg = <3>; + phy-handle = <&phy4>; + }; + port5: port@5 { + reg = <2>; + phy-handle = <&phy5>; + }; + port6: port@6 { + reg = <1>; + phy-handle = <&phy6>; + }; + port7: port@7 { + reg = <0>; + phy-handle = <&phy7>; + }; + }; +}; diff --git a/arch/mips/dts/ocelot_pcb123.dts b/arch/mips/dts/ocelot_pcb123.dts index a4fa37001f2..1b0156e503c 100644 --- a/arch/mips/dts/ocelot_pcb123.dts +++ b/arch/mips/dts/ocelot_pcb123.dts @@ -38,20 +38,38 @@ &mdio0 { status = "okay"; -}; - -&port0 { - phy-handle = <&phy0>; -}; -&port1 { - phy-handle = <&phy1>; -}; - -&port2 { - phy-handle = <&phy2>; + phy0: ethernet-phy@0 { + reg = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + }; + phy2: ethernet-phy@2 { + reg = <2>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + }; }; -&port3 { - phy-handle = <&phy3>; +&switch { + ethernet-ports { + port0: port@0 { + reg = <2>; + phy-handle = <&phy2>; + }; + port1: port@1 { + reg = <3>; + phy-handle = <&phy3>; + }; + port2: port@2 { + reg = <0>; + phy-handle = <&phy0>; + }; + port3: port@3 { + reg = <1>; + phy-handle = <&phy1>; + }; + }; }; diff --git a/arch/mips/dts/serval_pcb105.dts b/arch/mips/dts/serval_pcb105.dts index 1598669447f..667277080f2 100644 --- a/arch/mips/dts/serval_pcb105.dts +++ b/arch/mips/dts/serval_pcb105.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mscc,serval.dtsi" +#include <dt-bindings/mscc/serval_data.h> / { model = "Serval PCB105 Reference Board"; @@ -54,3 +55,46 @@ status = "okay"; sgpio-ports = <0x00FFFFFF>; }; + +&mdio1 { + status = "okay"; + + phy16: ethernet-phy@16 { + reg = <16>; + }; + phy17: ethernet-phy@17 { + reg = <17>; + }; + phy18: ethernet-phy@18 { + reg = <18>; + }; + phy19: ethernet-phy@19 { + reg = <19>; + }; +}; + +&switch { + ethernet-ports { + + port0: port@0 { + reg = <7>; + phy-handle = <&phy16>; + phys = <&serdes_hsio 7 SERDES1G(7) PHY_MODE_SGMII>; + }; + port1: port@1 { + reg = <6>; + phy-handle = <&phy17>; + phys = <&serdes_hsio 6 SERDES1G(6) PHY_MODE_SGMII>; + }; + port2: port@2 { + reg = <5>; + phy-handle = <&phy18>; + phys = <&serdes_hsio 5 SERDES1G(5) PHY_MODE_SGMII>; + }; + port3: port@3 { + reg = <4>; + phy-handle = <&phy19>; + phys = <&serdes_hsio 4 SERDES1G(4) PHY_MODE_SGMII>; + }; + }; +}; diff --git a/arch/mips/dts/serval_pcb106.dts b/arch/mips/dts/serval_pcb106.dts index fb3524bb31e..e77c357868b 100644 --- a/arch/mips/dts/serval_pcb106.dts +++ b/arch/mips/dts/serval_pcb106.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mscc,serval.dtsi" +#include <dt-bindings/mscc/serval_data.h> / { model = "Serval PCB106 Reference Board"; @@ -54,3 +55,46 @@ status = "okay"; sgpio-ports = <0x00FFFFFF>; }; + +&mdio1 { + status = "okay"; + + phy16: ethernet-phy@16 { + reg = <16>; + }; + phy17: ethernet-phy@17 { + reg = <17>; + }; + phy18: ethernet-phy@18 { + reg = <18>; + }; + phy19: ethernet-phy@19 { + reg = <19>; + }; +}; + +&switch { + ethernet-ports { + + port0: port@0 { + reg = <7>; + phy-handle = <&phy16>; + phys = <&serdes_hsio 7 SERDES1G(7) PHY_MODE_SGMII>; + }; + port1: port@1 { + reg = <6>; + phy-handle = <&phy17>; + phys = <&serdes_hsio 6 SERDES1G(6) PHY_MODE_SGMII>; + }; + port2: port@2 { + reg = <5>; + phy-handle = <&phy18>; + phys = <&serdes_hsio 5 SERDES1G(5) PHY_MODE_SGMII>; + }; + port3: port@3 { + reg = <4>; + phy-handle = <&phy19>; + phys = <&serdes_hsio 4 SERDES1G(4) PHY_MODE_SGMII>; + }; + }; +}; diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index 35152cb3f64..6a462f3e5a5 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -247,6 +247,8 @@ int arch_fixup_fdt(void *blob) static int boot_setup_fdt(bootm_headers_t *images) { + images->initrd_start = virt_to_phys((void *)images->initrd_start); + images->initrd_end = virt_to_phys((void *)images->initrd_end); return image_setup_libfdt(images, images->ft_addr, images->ft_len, &images->lmb); } diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig index 34584a19099..affc4721f82 100644 --- a/arch/mips/mach-mscc/Kconfig +++ b/arch/mips/mach-mscc/Kconfig @@ -29,7 +29,6 @@ config SOC_OCELOT config SOC_LUTON bool "Luton SOC Family" select SOC_VCOREIII - select MSCC_BITBANG_SPI_GPIO help This supports MSCC Luton family of SOCs. diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index 84ecfbdd920..d1f4287f654 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -401,23 +401,7 @@ static inline void sleep_100ns(u32 val) ; } -#if defined(CONFIG_SOC_OCELOT) -static inline void hal_vcoreiii_ddr_reset_assert(void) -{ - /* DDR has reset pin on GPIO 19 toggle Low-High to release */ - setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); - writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR); - sleep_100ns(10000); -} - -static inline void hal_vcoreiii_ddr_reset_release(void) -{ - /* DDR has reset pin on GPIO 19 toggle Low-High to release */ - setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); - writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET); - sleep_100ns(10000); -} - +#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL) /* * DDR memory sanity checking failed, tally and do hard reset * @@ -427,9 +411,11 @@ static inline void hal_vcoreiii_ddr_failed(void) { register u32 reset; +#if defined(CONFIG_SOC_OCELOT) writel(readl(BASE_CFG + ICPU_GPR(6)) + 1, BASE_CFG + ICPU_GPR(6)); clrbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); +#endif /* We have to execute the reset function from cache. Indeed, * the reboot workaround in _machine_restart() will change the @@ -452,6 +438,33 @@ static inline void hal_vcoreiii_ddr_failed(void) panic("DDR init failed\n"); } +#else /* JR2 || ServalT */ +static inline void hal_vcoreiii_ddr_failed(void) +{ + writel(0, BASE_CFG + ICPU_RESET); + writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST); + + panic("DDR init failed\n"); +} +#endif + +#if defined(CONFIG_SOC_OCELOT) +static inline void hal_vcoreiii_ddr_reset_assert(void) +{ + /* DDR has reset pin on GPIO 19 toggle Low-High to release */ + setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); + writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR); + sleep_100ns(10000); +} + +static inline void hal_vcoreiii_ddr_reset_release(void) +{ + /* DDR has reset pin on GPIO 19 toggle Low-High to release */ + setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); + writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET); + sleep_100ns(10000); +} + #else /* JR2 || ServalT || Serval */ static inline void hal_vcoreiii_ddr_reset_assert(void) { @@ -463,14 +476,6 @@ static inline void hal_vcoreiii_ddr_reset_assert(void) writel(readl(BASE_CFG + ICPU_RESET) | ICPU_RESET_MEM_RST_FORCE, BASE_CFG + ICPU_RESET); } - -static inline void hal_vcoreiii_ddr_failed(void) -{ - writel(0, BASE_CFG + ICPU_RESET); - writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST); - - panic("DDR init failed\n"); -} #endif /* JR2 || ServalT || Serval */ /* diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h index d3a76412e2e..b2a4203644a 100644 --- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h @@ -20,4 +20,5 @@ #define GPIO_ALT(x) (0x54 + 4 * (x)) +#define PERF_PHY_CFG 0xf0 #endif diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c index a555fc9d9a9..a1214573b51 100644 --- a/arch/mips/mach-mscc/reset.c +++ b/arch/mips/mach-mscc/reset.c @@ -36,7 +36,7 @@ void _machine_restart(void) /* Do global reset */ writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); - for (i = 0; i < 1000; i++) + for (i = 0; i < 2000; i++) ; /* Power down DDR for clean DDR re-training */ diff --git a/arch/mips/mach-mt7620/Kconfig b/arch/mips/mach-mtmips/Kconfig index a9834439993..4af2d545288 100644 --- a/arch/mips/mach-mt7620/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -1,20 +1,20 @@ menu "MediaTek MIPS platforms" - depends on ARCH_MT7620 + depends on ARCH_MTMIPS config SYS_MALLOC_F_LEN default 0x1000 config SYS_SOC - default "mt7620" if SOC_MT7620 + default "mt7628" if SOC_MT7628 choice prompt "MediaTek MIPS SoC select" -config SOC_MT7620 - bool "MT7620/8" +config SOC_MT7628 + bool "MT7628" select MIPS_L1_CACHE_SHIFT_5 help - This supports MediaTek MIPS MT7620 family. + This supports MediaTek MT7628/MT7688. endchoice @@ -23,7 +23,7 @@ choice config BOARD_GARDENA_SMART_GATEWAY_MT7688 bool "GARDENA smart Gateway" - depends on SOC_MT7620 + depends on SOC_MT7628 select BOARD_LATE_INIT select SUPPORTS_BOOT_RAM help @@ -32,7 +32,7 @@ config BOARD_GARDENA_SMART_GATEWAY_MT7688 config BOARD_LINKIT_SMART_7688 bool "LinkIt Smart 7688" - depends on SOC_MT7620 + depends on SOC_MT7628 select SUPPORTS_BOOT_RAM help Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM diff --git a/arch/mips/mach-mt7620/Makefile b/arch/mips/mach-mtmips/Makefile index 1f3e65e8a55..1f3e65e8a55 100644 --- a/arch/mips/mach-mt7620/Makefile +++ b/arch/mips/mach-mtmips/Makefile diff --git a/arch/mips/mach-mt7620/cpu.c b/arch/mips/mach-mtmips/cpu.c index fcd0484a6d8..fcd0484a6d8 100644 --- a/arch/mips/mach-mt7620/cpu.c +++ b/arch/mips/mach-mtmips/cpu.c diff --git a/arch/mips/mach-mt7620/ddr_calibrate.c b/arch/mips/mach-mtmips/ddr_calibrate.c index 75763c45286..75763c45286 100644 --- a/arch/mips/mach-mt7620/ddr_calibrate.c +++ b/arch/mips/mach-mtmips/ddr_calibrate.c diff --git a/arch/mips/mach-mt7620/lowlevel_init.S b/arch/mips/mach-mtmips/lowlevel_init.S index aa707e0de6c..aa707e0de6c 100644 --- a/arch/mips/mach-mt7620/lowlevel_init.S +++ b/arch/mips/mach-mtmips/lowlevel_init.S diff --git a/arch/mips/mach-mt7620/mt76xx.h b/arch/mips/mach-mtmips/mt76xx.h index 17473ea8f18..17473ea8f18 100644 --- a/arch/mips/mach-mt7620/mt76xx.h +++ b/arch/mips/mach-mtmips/mt76xx.h diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 8a4872343b6..3818e3752a0 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -16,10 +16,6 @@ #include <fdt_support.h> #include <environment.h> -#ifdef CONFIG_WDT_ARMADA_37XX -#include <wdt.h> -#endif - #include "mox_sp.h" #define MAX_MOX_MODULES 10 diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 4c08f810a24..ad6e29021e8 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -18,40 +18,38 @@ #include <dm/uclass.h> #include <fdt_support.h> #include <time.h> - -#ifdef CONFIG_ATSHA204A # include <atsha204a-i2c.h> -#endif - -#ifdef CONFIG_WDT_ORION -# include <wdt.h> -#endif #include "../drivers/ddr/marvell/a38x/ddr3_init.h" #include <../serdes/a38x/high_speed_env_spec.h> DECLARE_GLOBAL_DATA_PTR; -#define OMNIA_I2C_EEPROM_DM_NAME "i2c@11000->i2cmux@70->i2c@0" -#define OMNIA_I2C_EEPROM 0x54 -#define OMNIA_I2C_EEPROM_CONFIG_ADDR 0x0 -#define OMNIA_I2C_EEPROM_ADDRLEN 2 +#define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0" + +#define OMNIA_I2C_MCU_CHIP_ADDR 0x2a +#define OMNIA_I2C_MCU_CHIP_LEN 1 + +#define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54 +#define OMNIA_I2C_EEPROM_CHIP_LEN 2 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034 -#define OMNIA_I2C_MCU_DM_NAME "i2c@11000->i2cmux@70->i2c@0" -#define OMNIA_I2C_MCU_ADDR_STATUS 0x1 -#define OMNIA_I2C_MCU_SATA 0x20 -#define OMNIA_I2C_MCU_CARDDET 0x10 -#define OMNIA_I2C_MCU 0x2a -#define OMNIA_I2C_MCU_WDT_ADDR 0x0b +enum mcu_commands { + CMD_GET_STATUS_WORD = 0x01, + CMD_GET_RESET = 0x09, + CMD_WATCHDOG_STATE = 0x0b, +}; + +enum status_word_bits { + CARD_DET_STSBIT = 0x0010, + MSATA_IND_STSBIT = 0x0020, +}; #define OMNIA_ATSHA204_OTP_VERSION 0 #define OMNIA_ATSHA204_OTP_SERIAL 1 #define OMNIA_ATSHA204_OTP_MAC0 3 #define OMNIA_ATSHA204_OTP_MAC1 4 -#define MVTWSI_ARMADA_DEBUG_REG 0x8c - /* * Those values and defines are taken from the Marvell U-Boot version * "u-boot-2013.01-2014_T3.0" @@ -87,48 +85,97 @@ static struct serdes_map board_serdes_map_sata[] = { {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} }; -static bool omnia_detect_sata(void) +static struct udevice *omnia_get_i2c_chip(const char *name, uint addr, + uint offset_len) { struct udevice *bus, *dev; - int ret, retry = 3; - u16 mode; - - puts("SERDES0 card detect: "); + int ret; - if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { - puts("Cannot find MCU bus!\n"); - return false; + ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus); + if (ret) { + printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n", + OMNIA_I2C_BUS_NAME, ret); + return NULL; } - ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); + ret = i2c_get_chip(bus, addr, offset_len, &dev); if (ret) { - puts("Cannot get MCU chip!\n"); - return false; + printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n", + name, ret); + return NULL; } - for (; retry > 0; --retry) { - ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2); - if (!ret) - break; - } + return dev; +} + +static int omnia_mcu_read(u8 cmd, void *buf, int len) +{ + struct udevice *chip; + + chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR, + OMNIA_I2C_MCU_CHIP_LEN); + if (!chip) + return -ENODEV; + + return dm_i2c_read(chip, cmd, buf, len); +} - if (!retry) { - puts("I2C read failed! Default PEX\n"); +#ifndef CONFIG_SPL_BUILD +static int omnia_mcu_write(u8 cmd, const void *buf, int len) +{ + struct udevice *chip; + + chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR, + OMNIA_I2C_MCU_CHIP_LEN); + if (!chip) + return -ENODEV; + + return dm_i2c_write(chip, cmd, buf, len); +} + +static bool disable_mcu_watchdog(void) +{ + int ret; + + puts("Disabling MCU watchdog... "); + + ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1); + if (ret) { + printf("omnia_mcu_write failed: %i\n", ret); return false; } - if (!(mode & OMNIA_I2C_MCU_CARDDET)) { - puts("NONE\n"); + puts("disabled\n"); + + return true; +} +#endif + +static bool omnia_detect_sata(void) +{ + int ret; + u16 stsword; + + puts("MiniPCIe/mSATA card detection... "); + + ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword)); + if (ret) { + printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n", + ret); return false; } - if (mode & OMNIA_I2C_MCU_SATA) { - puts("SATA\n"); - return true; - } else { - puts("PEX\n"); + if (!(stsword & CARD_DET_STSBIT)) { + puts("none\n"); return false; } + + if (stsword & MSATA_IND_STSBIT) + puts("mSATA\n"); + else + puts("MiniPCIe\n"); + + return stsword & MSATA_IND_STSBIT ? true : false; } int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) @@ -153,48 +200,63 @@ struct omnia_eeprom { static bool omnia_read_eeprom(struct omnia_eeprom *oep) { - struct udevice *bus, *dev; - int ret, crc, retry = 3; + struct udevice *chip; + u32 crc; + int ret; + + chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR, + OMNIA_I2C_EEPROM_CHIP_LEN); - if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_EEPROM_DM_NAME, &bus)) { - puts("Cannot find EEPROM bus\n"); + if (!chip) return false; - } - ret = i2c_get_chip(bus, OMNIA_I2C_EEPROM, OMNIA_I2C_EEPROM_ADDRLEN, &dev); + ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep)); if (ret) { - puts("Cannot get EEPROM chip\n"); + printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret); return false; } - for (; retry > 0; --retry) { - ret = dm_i2c_read(dev, OMNIA_I2C_EEPROM_CONFIG_ADDR, (uchar *) oep, sizeof(struct omnia_eeprom)); - if (ret) - continue; - - if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) { - puts("I2C EEPROM missing magic number!\n"); - continue; - } - - crc = crc32(0, (unsigned char *) oep, - sizeof(struct omnia_eeprom) - 4); - if (crc == oep->crc) { - break; - } else { - printf("CRC of EEPROM memory config failed! " - "calc=0x%04x saved=0x%04x\n", crc, oep->crc); - } + if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) { + printf("bad EEPROM magic number (%08x, should be %08x)\n", + oep->magic, OMNIA_I2C_EEPROM_MAGIC); + return false; } - if (!retry) { - puts("I2C EEPROM read failed!\n"); + crc = crc32(0, (void *)oep, sizeof(*oep) - 4); + if (crc != oep->crc) { + printf("bad EEPROM CRC (stored %08x, computed %08x)\n", + oep->crc, crc); return false; } return true; } +static int omnia_get_ram_size_gb(void) +{ + static int ram_size; + struct omnia_eeprom oep; + + if (!ram_size) { + /* Get the board config from EEPROM */ + if (omnia_read_eeprom(&oep)) { + debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize); + + if (oep.ramsize == 0x2) + ram_size = 2; + else + ram_size = 1; + } else { + /* Hardcoded fallback */ + puts("Memory config from EEPROM read failed!\n"); + puts("Falling back to default 1 GiB!\n"); + ram_size = 1; + } + } + + return ram_size; +} + /* * Define the DDR layout / topology here in the board file. This will * be used by the DDR3 init code in the SPL U-Boot version to configure @@ -246,37 +308,10 @@ static struct mv_ddr_topology_map board_topology_map_2g = { struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) { - static int mem = 0; - struct omnia_eeprom oep; - - /* Get the board config from EEPROM */ - if (mem == 0) { - if(!omnia_read_eeprom(&oep)) - goto out; - - printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize); - - if (oep.ramsize == 0x2) - mem = 2; - else - mem = 1; - } - -out: - /* Hardcoded fallback */ - if (mem == 0) { - puts("WARNING: Memory config from EEPROM read failed.\n"); - puts("Falling back to default 1GiB map.\n"); - mem = 1; - } - - /* Return the board topology as defined in the board code */ - if (mem == 1) - return &board_topology_map_1g; - if (mem == 2) + if (omnia_get_ram_size_gb() == 2) return &board_topology_map_2g; - - return &board_topology_map_1g; + else + return &board_topology_map_1g; } #ifndef CONFIG_SPL_BUILD @@ -293,12 +328,47 @@ static int set_regdomain(void) printf("Regdomain set to %s\n", rd); return env_set("regdomain", rd); } + +/* + * default factory reset bootcommand on Omnia first sets all the front LEDs + * to green and then tries to load the rescue image from SPI flash memory and + * boot it + */ +#define OMNIA_FACTORY_RESET_BOOTCMD \ + "i2c dev 2; " \ + "i2c mw 0x2a.1 0x3 0x1c 1; " \ + "i2c mw 0x2a.1 0x4 0x1c 1; " \ + "mw.l 0x01000000 0x00ff000c; " \ + "i2c write 0x01000000 0x2a.1 0x5 4 -s; " \ + "setenv bootargs \"$bootargs omniarescue=$omnia_reset\"; " \ + "sf probe; " \ + "sf read 0x1000000 0x100000 0x700000; " \ + "bootm 0x1000000; " \ + "bootz 0x1000000" + +static void handle_reset_button(void) +{ + int ret; + u8 reset_status; + + ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1); + if (ret) { + printf("omnia_mcu_read failed: %i, reset status unknown!\n", + ret); + return; + } + + env_set_ulong("omnia_reset", reset_status); + + if (reset_status) { + printf("RESET button was pressed, overwriting bootcmd!\n"); + env_set("bootcmd", OMNIA_FACTORY_RESET_BOOTCMD); + } +} #endif int board_early_init_f(void) { - u32 i2c_debug_reg; - /* Configure MPP */ writel(0x11111111, MVEBU_MPP_BASE + 0x00); writel(0x11111111, MVEBU_MPP_BASE + 0x04); @@ -321,59 +391,16 @@ int board_early_init_f(void) writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); - /* - * Disable I2C debug mode blocking 0x64 I2C address. - * Note: that would be redundant once Turris Omnia migrates to DM_I2C, - * because the mvtwsi driver includes equivalent code. - */ - i2c_debug_reg = readl(MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); - i2c_debug_reg &= ~(1<<18); - writel(i2c_debug_reg, MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); - return 0; } -#ifndef CONFIG_SPL_BUILD -static bool disable_mcu_watchdog(void) -{ - struct udevice *bus, *dev; - int ret, retry = 3; - uchar buf[1] = {0x0}; - - if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { - puts("Cannot find MCU bus! Can not disable MCU WDT.\n"); - return false; - } - - ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); - if (ret) { - puts("Cannot get MCU chip! Can not disable MCU WDT.\n"); - return false; - } - - for (; retry > 0; --retry) - if (!dm_i2c_write(dev, OMNIA_I2C_MCU_WDT_ADDR, (uchar *) buf, 1)) - break; - - if (retry <= 0) { - puts("I2C MCU watchdog failed to disable!\n"); - return false; - } - - return true; -} -#endif - int board_init(void) { - /* adress of boot parameters */ + /* address of boot parameters */ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; #ifndef CONFIG_SPL_BUILD - if (disable_mcu_watchdog()) - puts("Disabled MCU startup watchdog.\n"); - - set_regdomain(); + disable_mcu_watchdog(); #endif return 0; @@ -383,17 +410,17 @@ int board_late_init(void) { #ifndef CONFIG_SPL_BUILD set_regdomain(); + handle_reset_button(); #endif return 0; } -#ifdef CONFIG_ATSHA204A static struct udevice *get_atsha204a_dev(void) { - static struct udevice *dev = NULL; + static struct udevice *dev; - if (dev != NULL) + if (dev) return dev; if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) { @@ -403,14 +430,12 @@ static struct udevice *get_atsha204a_dev(void) return dev; } -#endif int checkboard(void) { u32 version_num, serial_num; int err = 1; -#ifdef CONFIG_ATSHA204A struct udevice *dev = get_atsha204a_dev(); if (dev) { @@ -420,13 +445,13 @@ int checkboard(void) err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, OMNIA_ATSHA204_OTP_VERSION, - (u8 *) &version_num); + (u8 *)&version_num); if (err) goto out; err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, OMNIA_ATSHA204_OTP_SERIAL, - (u8 *) &serial_num); + (u8 *)&serial_num); if (err) goto out; @@ -434,13 +459,13 @@ int checkboard(void) } out: -#endif - + printf("Turris Omnia:\n"); + printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024); if (err) - printf("Board: Turris Omnia (ver N/A). SN: N/A\n"); + printf(" Serial Number: unknown\n"); else - printf("Board: Turris Omnia SNL %08X%08X\n", - be32_to_cpu(version_num), be32_to_cpu(serial_num)); + printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num), + be32_to_cpu(serial_num)); return 0; } @@ -458,7 +483,6 @@ static void increment_mac(u8 *mac) int misc_init_r(void) { -#ifdef CONFIG_ATSHA204A int err; struct udevice *dev = get_atsha204a_dev(); u8 mac0[4], mac1[4], mac[6]; @@ -503,8 +527,6 @@ int misc_init_r(void) eth_env_set_enetaddr("eth2addr", mac); out: -#endif - return 0; } diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c index 3abc5144129..0de1f4243eb 100644 --- a/board/elgin/elgin_rv1108/elgin_rv1108.c +++ b/board/elgin/elgin_rv1108/elgin_rv1108.c @@ -7,8 +7,8 @@ #include <common.h> #include <asm/io.h> #include <fdtdec.h> -#include <asm/arch/grf_rv1108.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/grf_rv1108.h> +#include <asm/arch-rockchip/hardware.h> #include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c index 807c717e33a..114f7fd9d9b 100644 --- a/board/mscc/luton/luton.c +++ b/board/mscc/luton/luton.c @@ -6,8 +6,7 @@ #include <common.h> #include <asm/io.h> #include <led.h> - -DECLARE_GLOBAL_DATA_PTR; +#include <miiphy.h> enum { BOARD_TYPE_PCB090 = 0xAABBCD00, @@ -36,6 +35,16 @@ int board_early_init_r(void) return 0; } +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, 0, 31, 0x10); + phy_write(phydev, 0, 18, 0x80A0); + while (phy_read(phydev, 0, 18) & 0x8000) + ; + phy_write(phydev, 0, 31, 0); + return 0; +} + static void do_board_detect(void) { u32 chipid = (readl(BASE_DEVCPU_GCB + CHIP_ID) >> 12) & 0xFFFF; diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c index 532d06f0003..bcae8fa50ca 100644 --- a/board/mscc/ocelot/ocelot.c +++ b/board/mscc/ocelot/ocelot.c @@ -11,6 +11,7 @@ #include <spi.h> #include <led.h> #include <wait_bit.h> +#include <miiphy.h> DECLARE_GLOBAL_DATA_PTR; @@ -42,6 +43,20 @@ void mscc_switch_reset(bool enter) mscc_gpio_set_alternate(19, 0); } +int board_phy_config(struct phy_device *phydev) +{ + if (gd->board_type == BOARD_TYPE_PCB123) + return 0; + + phy_write(phydev, 0, 31, 0x10); + phy_write(phydev, 0, 18, 0x80F0); + while (phy_read(phydev, 0, 18) & 0x8000) + ; + phy_write(phydev, 0, 31, 0); + + return 0; +} + void board_debug_uart_init(void) { /* too early for the pinctrl driver, so configure the UART pins here */ diff --git a/board/mscc/serval/serval.c b/board/mscc/serval/serval.c index 24ee5e528d9..da7f55620de 100644 --- a/board/mscc/serval/serval.c +++ b/board/mscc/serval/serval.c @@ -6,6 +6,7 @@ #include <common.h> #include <asm/io.h> #include <led.h> +#include <miiphy.h> enum { BOARD_TYPE_PCB106 = 0xAABBCD00, @@ -27,6 +28,17 @@ int board_early_init_r(void) return 0; } +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, 0, 31, 0x10); + phy_write(phydev, 0, 18, 0x80F0); + while (phy_read(phydev, 0, 18) & 0x8000) + ; + phy_write(phydev, 0, 14, 0x800); + phy_write(phydev, 0, 31, 0); + return 0; +} + static void do_board_detect(void) { u16 gpio_in_reg; @@ -42,10 +54,10 @@ static void do_board_detect(void) gd->board_type = BOARD_TYPE_PCB106; else gd->board_type = BOARD_TYPE_PCB105; - mscc_phy_wr(1, 16, 15, 0); } else { gd->board_type = BOARD_TYPE_PCB105; } + mscc_phy_wr(1, 16, 31, 0x0); } #if defined(CONFIG_MULTI_DTB_FIT) diff --git a/board/rockchip/evb_rk3036/evb_rk3036.c b/board/rockchip/evb_rk3036/evb_rk3036.c index d5acc4fe27f..8c606463e45 100644 --- a/board/rockchip/evb_rk3036/evb_rk3036.c +++ b/board/rockchip/evb_rk3036/evb_rk3036.c @@ -6,8 +6,8 @@ #include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/uart.h> -#include <asm/arch/sdram_rk3036.h> +#include <asm/arch-rockchip/uart.h> +#include <asm/arch-rockchip/sdram_rk3036.h> void get_ddr_config(struct rk3036_ddr_config *config) { diff --git a/board/rockchip/evb_rk3229/evb_rk3229.c b/board/rockchip/evb_rk3229/evb_rk3229.c index 63c84fccfe8..c64c62f7b0f 100644 --- a/board/rockchip/evb_rk3229/evb_rk3229.c +++ b/board/rockchip/evb_rk3229/evb_rk3229.c @@ -6,5 +6,5 @@ #include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/uart.h> +#include <asm/arch-rockchip/uart.h> diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index caad30641ec..07ee8ce92c9 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -5,3 +5,10 @@ F: board/rockchip/evb_rk3399 F: include/configs/evb_rk3399.h F: configs/evb-rk3399_defconfig F: configs/firefly-rk3399_defconfig + +ORANGEPI-RK3399 +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/orangepi-rk3399_defconfig +F: arch/arm/dts/rk3399-u-boot.dtsi +F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index 3e9e83f3ad0..bf2ad98c473 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -7,7 +7,7 @@ #include <dm.h> #include <dm/pinctrl.h> #include <dm/uclass-internal.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/periph.h> #include <power/regulator.h> #include <spl.h> diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c index 107929ee8a8..457b110cd52 100644 --- a/board/rockchip/evb_rv1108/evb_rv1108.c +++ b/board/rockchip/evb_rv1108/evb_rv1108.c @@ -7,8 +7,8 @@ #include <common.h> #include <asm/io.h> #include <fdtdec.h> -#include <asm/arch/grf_rv1108.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/grf_rv1108.h> +#include <asm/arch-rockchip/hardware.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/rockchip/kylin_rk3036/kylin_rk3036.c b/board/rockchip/kylin_rk3036/kylin_rk3036.c index 3a2f08354f5..2faeab9baf5 100644 --- a/board/rockchip/kylin_rk3036/kylin_rk3036.c +++ b/board/rockchip/kylin_rk3036/kylin_rk3036.c @@ -6,8 +6,8 @@ #include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/uart.h> -#include <asm/arch/sdram_rk3036.h> +#include <asm/arch-rockchip/uart.h> +#include <asm/arch-rockchip/sdram_rk3036.h> #include <asm/gpio.h> void get_ddr_config(struct rk3036_ddr_config *config) diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c index ea22cb985fe..9bb93c7d166 100644 --- a/board/rockchip/sheep_rk3368/sheep_rk3368.c +++ b/board/rockchip/sheep_rk3368/sheep_rk3368.c @@ -4,8 +4,8 @@ */ #include <common.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3368.h> #include <syscon.h> int mach_cpu_init(void) diff --git a/board/siemens/taurus/Kconfig b/board/siemens/taurus/Kconfig index cf71e4ce561..28816bc1a0c 100644 --- a/board/siemens/taurus/Kconfig +++ b/board/siemens/taurus/Kconfig @@ -9,4 +9,20 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "taurus" +choice + prompt "Board Type AXM/TAURUS" + default BOARD_AXM + +config BOARD_AXM + bool "AXM board type" + help + Select this, if you want to build for AXM board. + +config BOARD_TAURUS + bool "TAURUS board type" + help + Select this, if you want to build for TAURUS board. + +endchoice + endif diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 8396ce502b0..6ea97eb4e87 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -197,11 +197,11 @@ void mem_init(void) /* Mirrors at A15 on ATMEL G20 SDRAM Controller with 64MB*/ if (ram_size == 0x800) { - printf("\n\r 64MB"); + printf("\n\r 64MB\n"); sdramc_configure(AT91_SDRAMC_NC_9); } else { /* Size already initialized */ - printf("\n\r 128MB"); + printf("\n\r 128MB\n"); } } #endif @@ -282,24 +282,6 @@ int board_early_init_f(void) return 0; } -/* FIXME gpio code here need to handle through DM_GPIO */ -#ifndef CONFIG_DM_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - at91_set_gpio_value(TAURUS_SPI_CS_PIN, 0); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1); -} -#endif - #ifdef CONFIG_USB_GADGET_AT91 #include <linux/usb/at91_udc.h> @@ -347,17 +329,6 @@ int dram_init(void) return 0; } -#ifndef CONFIG_DM_ETH -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); -#endif - return rc; -} -#endif - #if !defined(CONFIG_SPL_BUILD) #if defined(CONFIG_BOARD_AXM) /* diff --git a/board/theobroma-systems/lion_rk3368/lion_rk3368.c b/board/theobroma-systems/lion_rk3368/lion_rk3368.c index e207535df05..6cd5a5f18ef 100644 --- a/board/theobroma-systems/lion_rk3368/lion_rk3368.c +++ b/board/theobroma-systems/lion_rk3368/lion_rk3368.c @@ -6,9 +6,9 @@ #include <dm.h> #include <ram.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3368.h> +#include <asm/arch-rockchip/timer.h> #include <syscon.h> int mach_cpu_init(void) diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 573e691457f..c6b509c109c 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -15,11 +15,11 @@ #include <asm/io.h> #include <asm/gpio.h> #include <asm/setup.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3399.h> -#include <asm/arch/hardware.h> -#include <asm/arch/grf_rk3399.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/periph.h> #include <power/regulator.h> #include <u-boot/sha256.h> diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 04f4b8e6934..37a599768b1 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -399,7 +399,6 @@ void enable_board_pin_mux(void) configure_module_pin_mux(mii1_pin_mux); } /* Beaglebone LT pinmux */ - configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); #if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT) configure_module_pin_mux(nand_pin_mux); diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 536c5b88ed5..d29a22cf05f 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -244,7 +244,7 @@ const struct emif_regs ddr3_emif_regs_400Mhz_production = { .read_idle_ctrl = 0x00050000, .zq_config = 0x50074BE4, .temp_alert_config = 0x0, - .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_phy_ctlr_1 = 0x00048008, .emif_ddr_ext_phy_ctrl_1 = 0x08020080, .emif_ddr_ext_phy_ctrl_2 = 0x00000066, .emif_ddr_ext_phy_ctrl_3 = 0x00000091, diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig index d4b36dbb42f..98172c28f5d 100644 --- a/board/ti/am65x/Kconfig +++ b/board/ti/am65x/Kconfig @@ -11,6 +11,7 @@ config TARGET_AM654_A53_EVM bool "TI K3 based AM654 EVM running on A53" select ARM64 select SOC_K3_AM6 + select SYS_DISABLE_DCACHE_OPS config TARGET_AM654_R5_EVM bool "TI K3 based AM654 EVM running on R5" diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS index 7cda5559842..626c1f94f9d 100644 --- a/board/toradex/colibri-imx6ull/MAINTAINERS +++ b/board/toradex/colibri-imx6ull/MAINTAINERS @@ -1,6 +1,5 @@ Colibri iMX6ULL M: Stefan Agner <stefan.agner@toradex.com> -M: Toradex ARM Support <support.arm@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS index f55f8045f45..cd0f9c9b2d2 100644 --- a/board/toradex/colibri_imx7/MAINTAINERS +++ b/board/toradex/colibri_imx7/MAINTAINERS @@ -1,6 +1,5 @@ Colibri iMX7 M: Stefan Agner <stefan.agner@toradex.com> -M: Toradex ARM Support <support.arm@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c index d3775b22191..0f5ef3a09a4 100644 --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -7,7 +7,7 @@ #include <dm.h> #include <dm/pinctrl.h> #include <dm/uclass-internal.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/periph.h> #include <power/regulator.h> #include <spl.h> diff --git a/cmd/bootefi.c b/cmd/bootefi.c index efaa548be4d..f1d7d8bc663 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -297,18 +297,21 @@ static efi_status_t efi_install_fdt(const char *fdt_opt) static efi_status_t do_bootefi_exec(efi_handle_t handle) { efi_status_t ret; + efi_uintn_t exit_data_size = 0; + u16 *exit_data = NULL; /* Transfer environment variable as load options */ ret = set_load_options(handle, "bootargs"); if (ret != EFI_SUCCESS) return ret; - /* we don't support much: */ - env_set("efi_8be4df61-93ca-11d2-aa0d-00e098032b8c_OsIndicationsSupported", - "{ro,boot}(blob)0000000000000000"); - /* Call our payload! */ - ret = EFI_CALL(efi_start_image(handle, NULL, NULL)); + ret = EFI_CALL(efi_start_image(handle, &exit_data_size, &exit_data)); + printf("## Application terminated, r = %lu\n", ret & ~EFI_ERROR_MASK); + if (ret && exit_data) { + printf("## %ls\n", exit_data); + efi_free_pool(exit_data); + } efi_restore_gd(); @@ -361,7 +364,6 @@ static int do_efibootmgr(const char *fdt_opt) } ret = do_bootefi_exec(handle); - printf("## Application terminated, r = %lu\n", ret & ~EFI_ERROR_MASK); if (ret != EFI_SUCCESS) return CMD_RET_FAILURE; @@ -476,7 +478,6 @@ static int do_bootefi_image(const char *image_opt, const char *fdt_opt) goto out; ret = do_bootefi_exec(handle); - printf("## Application terminated, r = %lu\n", ret & ~EFI_ERROR_MASK); out: if (mem_handle) diff --git a/cmd/efidebug.c b/cmd/efidebug.c index a40c4f4be28..c4ac9dd634e 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -11,6 +11,7 @@ #include <efi_loader.h> #include <environment.h> #include <exports.h> +#include <hexdump.h> #include <malloc.h> #include <search.h> #include <linux/ctype.h> @@ -545,7 +546,10 @@ static int do_efi_boot_add(cmd_tbl_t *cmdtp, int flag, + sizeof(struct efi_device_path); /* for END */ /* optional data */ - lo.optional_data = (u8 *)(argc == 6 ? "" : argv[6]); + if (argc < 6) + lo.optional_data = NULL; + else + lo.optional_data = (const u8 *)argv[6]; size = efi_serialize_load_option(&lo, (u8 **)&data); if (!size) { @@ -615,12 +619,13 @@ static int do_efi_boot_rm(cmd_tbl_t *cmdtp, int flag, /** * show_efi_boot_opt_data() - dump UEFI load option * - * @id: Load option number - * @data: Value of UEFI load option variable + * @id: load option number + * @data: value of UEFI load option variable + * @size: size of the boot option * * Decode the value of UEFI load option variable and print information. */ -static void show_efi_boot_opt_data(int id, void *data) +static void show_efi_boot_opt_data(int id, void *data, size_t size) { struct efi_load_option lo; char *label, *p; @@ -638,7 +643,7 @@ static void show_efi_boot_opt_data(int id, void *data) utf16_utf8_strncpy(&p, lo.label, label_len16); printf("Boot%04X:\n", id); - printf("\tattributes: %c%c%c (0x%08x)\n", + printf(" attributes: %c%c%c (0x%08x)\n", /* ACTIVE */ lo.attributes & LOAD_OPTION_ACTIVE ? 'A' : '-', /* FORCE RECONNECT */ @@ -646,14 +651,16 @@ static void show_efi_boot_opt_data(int id, void *data) /* HIDDEN */ lo.attributes & LOAD_OPTION_HIDDEN ? 'H' : '-', lo.attributes); - printf("\tlabel: %s\n", label); + printf(" label: %s\n", label); dp_str = efi_dp_str(lo.file_path); - printf("\tfile_path: %ls\n", dp_str); + printf(" file_path: %ls\n", dp_str); efi_free_pool(dp_str); - printf("\tdata: %s\n", lo.optional_data); - + printf(" data:\n"); + print_hex_dump(" ", DUMP_PREFIX_OFFSET, 16, 1, + lo.optional_data, size + (u8 *)data - + (u8 *)lo.optional_data, true); free(label); } @@ -686,13 +693,24 @@ static void show_efi_boot_opt(int id) data)); } if (ret == EFI_SUCCESS) - show_efi_boot_opt_data(id, data); + show_efi_boot_opt_data(id, data, size); else if (ret == EFI_NOT_FOUND) printf("Boot%04X: not found\n", id); free(data); } +static int u16_tohex(u16 c) +{ + if (c >= '0' && c <= '9') + return c - '0'; + if (c >= 'A' && c <= 'F') + return c - 'A' + 10; + + /* not hexadecimal */ + return -1; +} + /** * show_efi_boot_dump() - dump all UEFI load options * @@ -709,38 +727,58 @@ static void show_efi_boot_opt(int id) static int do_efi_boot_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - char regex[256]; - char * const regexlist[] = {regex}; - char *variables = NULL, *boot, *value; - int len; - int id; + u16 *var_name16, *p; + efi_uintn_t buf_size, size; + efi_guid_t guid; + int id, i, digit; + efi_status_t ret; if (argc > 1) return CMD_RET_USAGE; - snprintf(regex, 256, "efi_.*-.*-.*-.*-.*_Boot[0-9A-F]+"); - - /* TODO: use GetNextVariableName? */ - len = hexport_r(&env_htab, '\n', H_MATCH_REGEX | H_MATCH_KEY, - &variables, 0, 1, regexlist); - - if (!len) - return CMD_RET_SUCCESS; - - if (len < 0) + buf_size = 128; + var_name16 = malloc(buf_size); + if (!var_name16) return CMD_RET_FAILURE; - boot = variables; - while (*boot) { - value = strstr(boot, "Boot") + 4; - id = (int)simple_strtoul(value, NULL, 16); - show_efi_boot_opt(id); - boot = strchr(boot, '\n'); - if (!*boot) + var_name16[0] = 0; + for (;;) { + size = buf_size; + ret = EFI_CALL(efi_get_next_variable_name(&size, var_name16, + &guid)); + if (ret == EFI_NOT_FOUND) break; - boot++; + if (ret == EFI_BUFFER_TOO_SMALL) { + buf_size = size; + p = realloc(var_name16, buf_size); + if (!p) { + free(var_name16); + return CMD_RET_FAILURE; + } + var_name16 = p; + ret = EFI_CALL(efi_get_next_variable_name(&size, + var_name16, + &guid)); + } + if (ret != EFI_SUCCESS) { + free(var_name16); + return CMD_RET_FAILURE; + } + + if (memcmp(var_name16, L"Boot", 8)) + continue; + + for (id = 0, i = 0; i < 4; i++) { + digit = u16_tohex(var_name16[4 + i]); + if (digit < 0) + break; + id = (id << 4) + digit; + } + if (i == 4 && !var_name16[8]) + show_efi_boot_opt(id); } - free(variables); + + free(var_name16); return CMD_RET_SUCCESS; } diff --git a/cmd/gpt.c b/cmd/gpt.c index 638870352f4..33cda513969 100644 --- a/cmd/gpt.c +++ b/cmd/gpt.c @@ -876,21 +876,21 @@ U_BOOT_CMD(gpt, CONFIG_SYS_MAXARGS, 1, do_gpt, " Example usage:\n" " gpt write mmc 0 $partitions\n" " gpt verify mmc 0 $partitions\n" - " read <interface> <dev>\n" - " - read GPT into a data structure for manipulation\n" - " guid <interface> <dev>\n" + " gpt guid <interface> <dev>\n" " - print disk GUID\n" - " guid <interface> <dev> <varname>\n" + " gpt guid <interface> <dev> <varname>\n" " - set environment variable to disk GUID\n" " Example usage:\n" " gpt guid mmc 0\n" " gpt guid mmc 0 varname\n" #ifdef CONFIG_CMD_GPT_RENAME "gpt partition renaming commands:\n" - "gpt swap <interface> <dev> <name1> <name2>\n" + " gpt read <interface> <dev>\n" + " - read GPT into a data structure for manipulation\n" + " gpt swap <interface> <dev> <name1> <name2>\n" " - change all partitions named name1 to name2\n" " and vice-versa\n" - "gpt rename <interface> <dev> <part> <name>\n" + " gpt rename <interface> <dev> <part> <name>\n" " - rename the specified partition\n" " Example usage:\n" " gpt swap mmc 0 foo bar\n" diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c index e65b38dbf39..2805e8182b4 100644 --- a/cmd/nvedit_efi.c +++ b/cmd/nvedit_efi.c @@ -291,8 +291,11 @@ static int append_value(char **bufp, size_t *sizep, char *data) if (!tmp_buf) return -1; - if (hex2bin((u8 *)tmp_buf, data, len) < 0) + if (hex2bin((u8 *)tmp_buf, data, len) < 0) { + printf("Error: illegal hexadecimal string\n"); + free(tmp_buf); return -1; + } value = tmp_buf; } else { /* string */ diff --git a/cmd/pxe.c b/cmd/pxe.c index e77770237cb..1dd0a74ea39 100644 --- a/cmd/pxe.c +++ b/cmd/pxe.c @@ -24,6 +24,9 @@ const char *pxe_default_paths[] = { #ifdef CONFIG_SYS_SOC +#ifdef CONFIG_SYS_BOARD + "default-" CONFIG_SYS_ARCH "-" CONFIG_SYS_SOC "-" CONFIG_SYS_BOARD, +#endif "default-" CONFIG_SYS_ARCH "-" CONFIG_SYS_SOC, #endif "default-" CONFIG_SYS_ARCH, diff --git a/cmd/rockusb.c b/cmd/rockusb.c index e0c1480d6d4..9b70c6a6aff 100644 --- a/cmd/rockusb.c +++ b/cmd/rockusb.c @@ -8,7 +8,7 @@ #include <console.h> #include <g_dnl.h> #include <usb.h> -#include <asm/arch/f_rockusb.h> +#include <asm/arch-rockchip/f_rockusb.h> static int do_rockusb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index c9bfe0cc8ae..87ecf0bb9e5 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -333,7 +333,7 @@ static int spl_fit_record_loadable(const void *fit, int images, int index, static int spl_fit_image_get_os(const void *fit, int noffset, uint8_t *os) { -#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY) +#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY) && !defined(CONFIG_SPL_OS_BOOT) return -ENOTSUPP; #else return fit_image_get_os(fit, noffset, os); diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 105ff01d14d..ff96f192e02 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -11,6 +11,7 @@ CONFIG_LOGLEVEL=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_ETH_SUPPORT=y # CONFIG_SPL_FS_EXT4 is not set CONFIG_SPL_MTD_SUPPORT=y @@ -31,7 +32,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),1 # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="am335x-evm" -CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2" +CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle" CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_ENV_IS_NOWHERE=y CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 5d901d13a3b..a3de7a4ec48 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -59,6 +59,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index c27916cbc97..d2548ff6606 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -57,6 +57,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index 23310c38c73..b52d321a69a 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -63,6 +63,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index b69702b677c..be9d55e7d47 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_DM=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_SYS_I2C_TEGRA=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y CONFIG_E1000=y CONFIG_PCI=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index 234416e7f65..3292d644aa3 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -58,6 +58,7 @@ CONFIG_DFU_MMC=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig index 3a1a749f3f3..9727d28c124 100644 --- a/configs/arndale_defconfig +++ b/configs/arndale_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale" CONFIG_ENV_IS_IN_MMC=y CONFIG_DM_I2C_COMPAT=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig index fc4429ba202..b504332ff00 100644 --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@ -56,6 +56,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig index 59ea252f5bc..bcc5a0aa4aa 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -1,46 +1,74 @@ CONFIG_ARM=y -CONFIG_SPL_SYS_THUMB_BUILD=y +CONFIG_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_AT91=y +CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds" CONFIG_SYS_TEXT_BASE=0x21000000 CONFIG_TARGET_TAURUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=18432000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM" +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068" CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="\0addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}::off\0addtest=setenv bootargs ${bootargs} loglevel=4 test\0baudrate=115200\0boot_file=setenv bootfile /${project_dir}/kernel/uImage\0boot_retries=0\0bootcmd=run flash_self\0bootdelay=3\0ethact=macb0\0flash_nfs=run nand_kernel;run nfsargs;run addip;upgrade_available;bootm ${kernel_ram};reset\0flash_self=run nand_kernel;run setbootargs;upgrade_available;bootm ${kernel_ram};reset\0flash_self_test=run nand_kernel;run setbootargs addtest; upgrade_available;bootm ${kernel_ram};reset\0hostname=systemone\0kernel_Off=0x00200000\0kernel_Off_fallback=0x03800000\0kernel_ram=0x21500000\0kernel_size=0x00400000\0kernel_size_fallback=0x00400000\0loads_echo=1\0nand_kernel=nand read.e ${kernel_ram} ${kernel_Off} ${kernel_size}\0net_nfs=run boot_file;tftp ${kernel_ram} ${bootfile};run nfsargs;run addip;upgrade_available;bootm ${kernel_ram};reset\0netdev=eth0\0nfsargs=run root_path;setenv bootargs ${bootargs} root=/dev/nfs rw nfsroot=${serverip}:${rootpath} at91sam9_wdt.wdt_timeout=16\0partitionset_active=A\0preboot=echo;echo Type 'run flash_self' to use kernel and root filesystem on memory;echo Type 'run flash_nfs' to use kernel from memory and root filesystem over NFS;echo Type 'run net_nfs' to get Kernel over TFTP and mount root filesystem over NFS;echo\0project_dir=systemone\0root_path=setenv rootpath /home/projects/${project_dir}/rootfs\0rootfs=/dev/mtdblock5\0rootfs_fallback=/dev/mtdblock7\0setbootargs=setenv bootargs ${bootargs} console=ttyMTD,mtdoops root=${rootfs} rootfstype=jffs2 panic=7 at91sam9_wdt.wdt_timeout=16\0stderr=serial\0stdin=serial\0stdout=serial\0upgrade_available=0\0" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run flash_self" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_SPL_CRC32_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_NAND=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_SF=y CONFIG_CMD_SPI=y # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_MTDPARTS=y CONFIG_OF_CONTROL=y -CONFIG_OF_EMBED=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" +CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_SPL_DM=y +CONFIG_BLK=y +CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y # CONFIG_MMC is not set CONFIG_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_ATMEL_USART=y +CONFIG_WDT=y +CONFIG_WDT_AT91=y CONFIG_USE_TINY_PRINTF=y +CONFIG_HEXDUMP=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index c613962cbd3..73c78e23c65 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -50,6 +50,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" # CONFIG_ENV_IS_IN_MMC is not set CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index 05b19b31c01..ee3fb149e46 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -45,6 +45,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig index fa9972b47fb..dedc8b573ac 100644 --- a/configs/cm_t54_defconfig +++ b/configs/cm_t54_defconfig @@ -32,6 +32,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SCSI_AHCI=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_SCSI=y CONFIG_CONS_INDEX=4 diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 449f4f9de25..ba17ec00306 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -57,6 +57,7 @@ CONFIG_DFU_MMC=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 5e2a204a881..0617b120a05 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -45,6 +45,7 @@ CONFIG_DFU_MMC=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 221c204af0d..09c6147e2d1 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -68,5 +68,10 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_DA8XX=y # CONFIG_FAT_WRITE is not set CONFIG_USE_TINY_PRINTF=y diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 5c0695481b1..e2f69eb64e8 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -63,6 +63,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_MTD_DEVICE=y CONFIG_SPI_FLASH=y diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 8e2667101e5..0d9eed3a3e8 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -64,6 +64,7 @@ CONFIG_PARTITION_TYPE_GUID=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DFU_MMC=y CONFIG_DFU_SF=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_MTD_DEVICE=y CONFIG_SPI_FLASH=y diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig index eed0b67a127..980f7b4abb6 100644 --- a/configs/dms-ba16-1g_defconfig +++ b/configs/dms-ba16-1g_defconfig @@ -32,6 +32,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DWC_AHSATA=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig index d9f6d59874b..bea75b5d23c 100644 --- a/configs/dms-ba16_defconfig +++ b/configs/dms-ba16_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DWC_AHSATA=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index ec6b5667e52..682e3018222 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -65,6 +65,7 @@ CONFIG_PCF8575_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 3f64669814a..7b50d2cbc6b 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -68,6 +68,7 @@ CONFIG_PCF8575_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 47d4ad02b69..6d6bfbc4937 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -70,6 +70,7 @@ CONFIG_PCF8575_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y diff --git a/configs/edison_defconfig b/configs/edison_defconfig index 22fc84a41e3..b99906a4d14 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -30,6 +30,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_CPU=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_DM_PCI_COMPAT=y CONFIG_RTC_MC146818=y CONFIG_USB_DWC3_GADGET=y diff --git a/configs/gardena-smart-gateway-mt7688-ram_defconfig b/configs/gardena-smart-gateway-mt7688-ram_defconfig index 7c8ae0f6474..e09950637ff 100644 --- a/configs/gardena-smart-gateway-mt7688-ram_defconfig +++ b/configs/gardena-smart-gateway-mt7688-ram_defconfig @@ -1,7 +1,7 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_ARCH_MT7620=y +CONFIG_ARCH_MTMIPS=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y CONFIG_ENV_VARS_UBOOT_CONFIG=y diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig index 8fd676025aa..ad0db2e7235 100644 --- a/configs/gardena-smart-gateway-mt7688_defconfig +++ b/configs/gardena-smart-gateway-mt7688_defconfig @@ -1,7 +1,7 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x9c000000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_ARCH_MT7620=y +CONFIG_ARCH_MTMIPS=y CONFIG_BOOT_ROM=y CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index eba37939f91..3111451162c 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -42,6 +42,7 @@ CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5" CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000 CONFIG_DM_GPIO=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index ff88c3e77cc..f9857d13caf 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -62,6 +62,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_MTD_DEVICE=y CONFIG_PHYLIB=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index b5251abab8e..27ef264d821 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -62,6 +62,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_MTD_DEVICE=y CONFIG_PHYLIB=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index e90b3db3ff6..25af0878208 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -64,6 +64,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig index 6e668c5a04b..09f33755f9a 100644 --- a/configs/imx6dl_mamoj_defconfig +++ b/configs/imx6dl_mamoj_defconfig @@ -32,6 +32,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=2 CONFIG_SYS_I2C_MXC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 989dc445d03..6811a62bd11 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -29,6 +29,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_DM_ETH=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX8M=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index 2fb2fdf7fff..59675e56b92 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -53,6 +53,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ATHEROS=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 393046edc8b..f6a18748a93 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -7,8 +7,11 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK3036=y CONFIG_TARGET_KYLIN_RK3036=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x0 -CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0x20068000 +CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb" # CONFIG_DISPLAY_CPUINFO is not set @@ -46,6 +49,7 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_PINCTRL=y CONFIG_DM_REGULATOR_FIXED=y # CONFIG_SPL_DM_SERIAL is not set +CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/linkit-smart-7688-ram_defconfig b/configs/linkit-smart-7688-ram_defconfig index 6e9aa7adefc..c2502b27139 100644 --- a/configs/linkit-smart-7688-ram_defconfig +++ b/configs/linkit-smart-7688-ram_defconfig @@ -1,7 +1,7 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x80010000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_ARCH_MT7620=y +CONFIG_ARCH_MTMIPS=y CONFIG_BOARD_LINKIT_SMART_7688=y # CONFIG_MIPS_BOOT_ENV_LEGACY is not set CONFIG_MIPS_BOOT_FDT=y diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig index 5660f41e8e3..fba1bfd653c 100644 --- a/configs/linkit-smart-7688_defconfig +++ b/configs/linkit-smart-7688_defconfig @@ -1,7 +1,7 @@ CONFIG_MIPS=y CONFIG_SYS_TEXT_BASE=0x9c000000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_ARCH_MT7620=y +CONFIG_ARCH_MTMIPS=y CONFIG_BOARD_LINKIT_SMART_7688=y CONFIG_BOOT_ROM=y CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig index 173ceedcc9c..a439631e91c 100644 --- a/configs/liteboard_defconfig +++ b/configs/liteboard_defconfig @@ -38,6 +38,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_DM_ETH=y diff --git a/configs/mscc_serval_defconfig b/configs/mscc_serval_defconfig index 146188bb0c9..753a11aa122 100644 --- a/configs/mscc_serval_defconfig +++ b/configs/mscc_serval_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y -# CONFIG_CMD_NFS is not set CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk)" @@ -58,3 +57,8 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_LZMA=y +CONFIG_CMD_DHCP=y +# CONFIG_NET_TFTP_VARS is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_MSCC_SERVAL_SWITCH=y diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig index 5c411fe1d16..ae8209831b4 100644 --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig @@ -35,6 +35,7 @@ CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_DM_MMC=y # CONFIG_MMC_QUIRKS is not set +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_MTK=y CONFIG_PHY_FIXED=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index d232fbc76a9..d3ed3c45430 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -73,6 +73,7 @@ CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=2 CONFIG_DM_GPIO=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 88d363a27e6..b2ca4f96ccd 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -44,6 +44,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index 3d74967432d..27a838787a7 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -44,6 +44,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index 6bbacaa6861..d125ccc1af0 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -21,6 +21,7 @@ CONFIG_IMX_RGPIO2P=y # CONFIG_MXC_GPIO is not set CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7ULP=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index 549ca2e9643..fcead94f57b 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -20,6 +20,7 @@ CONFIG_IMX_RGPIO2P=y # CONFIG_MXC_GPIO is not set CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7ULP=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index 4ec4e5871c5..b8ebd56bf9d 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -34,6 +34,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_ADC=y CONFIG_ADC_EXYNOS=y CONFIG_DFU_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_SMC911X=y CONFIG_SMC911X_BASE=0x5000000 diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index 9a7fccd93e1..719ab8dde8e 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -30,6 +30,7 @@ CONFIG_SCSI_AHCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_CMD_TCA642X=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_SCSI=y CONFIG_CONS_INDEX=3 diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index 6a5e8cc8535..409bea88eb5 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -68,6 +68,7 @@ CONFIG_SYSCON=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_PWRSEQ=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig new file mode 100644 index 00000000000..cdccf221b52 --- /dev/null +++ b/configs/orangepi-rk3399_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index cf55764ae5f..c1904f102bc 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -38,6 +38,7 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index cecb4ee619a..da4155b286f 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -37,6 +37,7 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig index fdebb55ecb9..5481fffa0c1 100644 --- a/configs/pico-hobbit-imx6ul_defconfig +++ b/configs/pico-hobbit-imx6ul_defconfig @@ -45,6 +45,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 33f2a0ad71c..17043d5b22b 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -53,6 +53,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_MII=y diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index 0c587161dca..af8267777a6 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -47,6 +47,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 41374a33bff..81eda9dc6f4 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -53,6 +53,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_MII=y diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index d8d26611426..295c822aa9c 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -45,6 +45,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 81d19df04c0..0aa14878e2e 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -53,6 +53,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_MII=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index f9f98c95905..964464ac0fe 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -69,6 +69,7 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index da08bb89186..6b0d7e58532 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -21,6 +21,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig index a485ceb42c2..1b61232d5c4 100644 --- a/configs/riotboard_spl_defconfig +++ b/configs/riotboard_spl_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig index 69b58f5860d..1bdcc4797b8 100644 --- a/configs/smdk5250_defconfig +++ b/configs/smdk5250_defconfig @@ -33,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_BUS=y CONFIG_ENV_SPI_BUS=1 +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig index 989cd6305ae..7510f80c2ef 100644 --- a/configs/smdk5420_defconfig +++ b/configs/smdk5420_defconfig @@ -28,6 +28,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_BUS=y CONFIG_ENV_SPI_BUS=1 +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index e87f5d59849..f4744095164 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -43,6 +43,7 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y diff --git a/configs/spring_defconfig b/configs/spring_defconfig index b4a8d5e55cd..bfc7495a734 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -43,6 +43,7 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index bd75df8eac9..0ea9dff43de 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_PHY=y CONFIG_PHY_STM32_USBPHYC=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index f82b770bc87..3c2bb75564d 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -45,6 +45,7 @@ CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_PHY=y CONFIG_PHY_STM32_USBPHYC=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 0da77d8c94a..02a89592d74 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -1,36 +1,48 @@ CONFIG_ARM=y -CONFIG_SPL_SYS_THUMB_BUILD=y +CONFIG_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_AT91=y CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds" CONFIG_SYS_TEXT_BASE=0x21000000 CONFIG_TARGET_TAURUS=y +CONFIG_BOARD_TAURUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x1000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=18432000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS" +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_SPL_CRC32_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_XTRACE="n" # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_NAND=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -41,19 +53,30 @@ CONFIG_CMD_PING=y CONFIG_CMD_MTDPARTS=y # CONFIG_DOS_PARTITION is not set CONFIG_OF_CONTROL=y -CONFIG_OF_EMBED=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" +CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_SPL_DM=y +CONFIG_BLK=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_DFU_NAND=y # CONFIG_MMC is not set CONFIG_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y +CONFIG_DM_USB=y +# CONFIG_SPL_DM_USB is not set CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Siemens AG" @@ -63,3 +86,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_WDT=y CONFIG_WDT_AT91=y CONFIG_USE_TINY_PRINTF=y +CONFIG_HEXDUMP=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index 999425e460d..e04156311f4 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SPL_SYS_THUMB_BUILD=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 +CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 @@ -14,7 +15,10 @@ CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_MISC_INIT_R=y @@ -23,16 +27,22 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_LZMADEC=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_SATA=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_AES=y +CONFIG_CMD_HASH=y CONFIG_CMD_BTRFS=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia" @@ -40,8 +50,11 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_MAX_HZ=y CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_SPL_OF_TRANSLATE=y -CONFIG_SCSI_AHCI=y -CONFIG_ATSHA204A=y +CONFIG_AHCI_PCI=y +CONFIG_AHCI_MVEBU=y +CONFIG_DM_GPIO=y +# CONFIG_MVEBU_GPIO is not set +CONFIG_DM_PCA953X=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_MV=y @@ -53,11 +66,13 @@ CONFIG_MVNETA=y CONFIG_MII=y CONFIG_PCI=y CONFIG_PCI_MVEBU=y +CONFIG_SCSI=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_WDT=y CONFIG_WDT_ORION=y diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index 25303e67898..2cc30e0fd2b 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -40,6 +40,7 @@ CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_UNIPHIER=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index 296424ec6e5..61007a67706 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -39,6 +39,7 @@ CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_UNIPHIER=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index b0c673c98e5..83f78776b7d 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -34,6 +34,7 @@ CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_UNIPHIER=y CONFIG_MMC_SDHCI=y diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig index 5d929437bf3..745aa85f3b6 100644 --- a/configs/vinco_defconfig +++ b/configs/vinco_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="at91-vinco" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index 5347ac8fe85..073ff483296 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -33,6 +33,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_EFI_PARTITION=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_MII=y diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index 300dc3805af..a79f670ea01 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -29,6 +29,7 @@ CONFIG_DFU_MMC=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 1b5356c02ef..5b351133a82 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -38,6 +38,7 @@ CONFIG_DFU_MMC=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y diff --git a/configs/warp_defconfig b/configs/warp_defconfig index df43a798697..a37d7692969 100644 --- a/configs/warp_defconfig +++ b/configs/warp_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y # CONFIG_NET is not set CONFIG_DFU_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index 91d7c6993f8..c8d68864930 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -53,6 +53,7 @@ CONFIG_SPL_DM=y # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index 4515b2047db..29e472842a4 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -53,6 +53,7 @@ CONFIG_SPL_DM=y # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index a57c71eeac9..7b1f5e9d0ae 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -58,6 +58,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig index f0706f31ef3..559a61e8d02 100644 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@ -50,6 +50,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_MTD_DEVICE=y diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig index 2cbeeb39008..709a7ef9084 100644 --- a/configs/xpress_defconfig +++ b/configs/xpress_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_MII=y diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig index fb2bf0a64a3..e79a038816d 100644 --- a/configs/xpress_spl_defconfig +++ b/configs/xpress_spl_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_MII=y diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig index 9ba661cebe4..ae3a6b32bf2 100644 --- a/configs/zc5202_defconfig +++ b/configs/zc5202_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=3 diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig index ba07f615bb4..65a19151a82 100644 --- a/configs/zc5601_defconfig +++ b/configs/zc5601_defconfig @@ -33,6 +33,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=3 diff --git a/disk/part_efi.c b/disk/part_efi.c index 239455b8161..c0fa753339c 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -209,6 +209,8 @@ int get_disk_guid(struct blk_desc * dev_desc, char *guid) guid_bin = gpt_head->disk_guid.b; uuid_bin_to_str(guid_bin, guid, UUID_STR_FORMAT_GUID); + /* Remember to free pte */ + free(gpt_pte); return 0; } @@ -696,6 +698,10 @@ int gpt_verify_headers(struct blk_desc *dev_desc, gpt_header *gpt_head, __func__); return -1; } + + /* Free pte before allocating again */ + free(*gpt_pte); + if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), gpt_head, gpt_pte) != 1) { printf("%s: *** ERROR: Invalid Backup GPT ***\n", diff --git a/doc/README.davinci b/doc/README.davinci index aa7c85011a3..6522c24eea1 100644 --- a/doc/README.davinci +++ b/doc/README.davinci @@ -1,108 +1,47 @@ Summary ======= -This README is about U-Boot support for TI's ARM 926EJS based family of SoCs. -These SOCs are used for cameras, video security and surveillance, DVR's, etc. -DaVinci SOC's comprise of DM644x, DM646x, DM35x and DM36x series of SOC's -Additionally there are some SOCs meant for the audio market which though have -an OMAP part number are very similar to the DaVinci series of SOC's -Additionally, some family members contain a TI DSP and/or graphics -co processors along with a host of other peripherals. +Note: this document used to be about the entire family of DaVinci SOCs but the +support for the DM* family and DA830 has since been dropped. -Currently the following boards are supported: - -* TI DaVinci DM644x EVM - -* TI DaVinci DM646x EVM - -* TI DaVinci DM355 EVM - -* TI DaVinci DM365 EVM +This README is about U-Boot support for TI's DA850 SoC. This SOC has an OMAP +part number but is very similar to the DaVinci series. -* TI DA830 EVM +Currently the following boards are supported: * TI DA850 EVM -* DM355 based Leopard board - -* DM644x based schmoogie board - -* DM644x based sffsdr board +* TI OMAP-L138 LCDK -* DM644x based sonata board +* Lego EV3 Build ===== -* TI DaVinci DM644x EVM: - -make davinci_dvevm_config -make - -* TI DaVinci DM646x EVM: - -make davinci_dm6467evm_config -make - -* TI DaVinci DM355 EVM: - -make davinci_dm355evm_config -make - -* TI DaVinci DM365 EVM: - -make davinci_dm365evm_config -make - -* TI DA830 EVM: - -make da830evm_config -make - * TI DA850 EVM: make da850evm_config make -* DM355 based Leopard board: - -make davinci_dm355leopard_config -make - -* DM644x based schmoogie board: +* TI OMAP-L138 LCDK -make davinci_schmoogie_config +make omapl138_lcdk_defconfig make -* DM644x based sffsdr board: +* Lego EV3 -make davinci_sffsdr_config -make - -* DM644x based sonata board: - -make davinci_sonata_config +make legoev3_defconfig make Bootloaders =============== -The DaVinci SOC's use 2 bootloaders. The low level initialization -is done by a UBL(user boot loader). The UBL is written to a NAND/NOR/SPI flash -by a programmer. During initial bootup, the ROM Bootloader reads the UBL -from a storage device and loads it into the IRAM. The UBL then loads the U-Boot -into the RAM. -The programmers and UBL are always released as part of any standard TI -software release associated with an SOC. - -Alternative boot method (DA850 EVM only): -For the DA850 EVM an SPL (secondary program loader, see doc/README.SPL) -is provided to load U-Boot directly from SPI flash. In this case, the -SPL does the low level initialization that is otherwise done by the SPL. -To build U-Boot with this SPL, do -make da850evm_config -make u-boot.ais -and program the resulting u-boot.ais file to the SPI flash of the DA850 EVM. +For DA850 an SPL (secondary program loader, see doc/README.SPL) is provided +to load U-Boot directly from SPI flash. The SPL takes care of the low level +initialization. + +The SPL is built as u-boot.ais for all DA850 defconfigs. The resulting +image file can be programmed to the SPI flash of the DA850 EVM/LCDK. Environment Variables ===================== @@ -121,34 +60,14 @@ is used to obtain this information. Links ===== -1) TI DaVinci DM355 EVM: -http://focus.ti.com/docs/prod/folders/print/tms320dm355.html -http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=203&osCsid=c499af6087317f11b3da19b4e8f1af32 - -2) TI DaVinci DM365 EVM: -http://focus.ti.com/docs/prod/folders/print/tms320dm365.html?247SEM= -http://support.spectrumdigital.com/boards/evmdm365/revc/ - -3) DaVinci DM355 based leopard board -http://designsomething.org/leopardboard/default.aspx -http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=192&osCsid=67c20335668ffc57cb35727106eb24b1 - -4) TI DaVinci DM6467 EVM: -http://focus.ti.com/docs/prod/folders/print/tms320dm6467.html -http://support.spectrumdigital.com/boards/evmdm6467/revf/ - -5) TI DaVinci DM6446 EVM: -http://focus.ti.com/docs/prod/folders/print/tms320dm6446.html -http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=222 - -6) TI DA830 EVM -http://focus.ti.com/apps/docs/gencontent.tsp?appId=1&contentId=52385 -http://www.spectrumdigital.com/product_info.php?cPath=37&products_id=214 - -7) TI DA850 EVM +1) TI DA850 EVM http://focus.ti.com/docs/prod/folders/print/omap-l138.html http://www.logicpd.com/products/development-kits/zoom-omap-l138-evm-development-kit +2) TI OMAP-L138 LCDK +http://focus.ti.com/docs/prod/folders/print/omap-l138.html +http://www.ti.com/tool/TMDXLCDK138 + Davinci special defines ======================= diff --git a/doc/git-mailrc b/doc/git-mailrc index 13137017fe4..a63b76befc5 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -22,10 +22,12 @@ alias bmeng Bin Meng <bmeng.cn@gmail.com> alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com> alias dinh Dinh Nguyen <dinguyen@kernel.org> alias hs Heiko Schocher <hs@denx.de> +alias freenix Peng Fan <peng.fan@nxp.com> alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org> alias jaehoon Jaehoon Chung <jh80.chung@samsung.com> alias jagan Jagan Teki <jagan@amarulasolutions.com> alias jhersh Joe Hershberger <joe.hershberger@ni.com> +alias kevery Kever Yang <kever.yang@rock-chips.com> alias lukma Lukasz Majewski <lukma@denx.de> alias macpaul Macpaul Lin <macpaul@andestech.com> alias marex Marek Vasut <marex@denx.de> @@ -70,7 +72,7 @@ alias tegra2 tegra alias ti uboot, trini alias uniphier uboot, masahiro alias zynq uboot, monstr -alias rockchip uboot, sjg, Kever Yang <kever.yang@rock-chips.com>, ptomsich +alias rockchip uboot, sjg, kevery, ptomsich alias m68k uboot, alisonwang, angelo_ts alias coldfire m68k @@ -110,7 +112,7 @@ alias kerneldoc uboot, marex alias fdt uboot, sjg alias i2c uboot, hs alias kconfig uboot, masahiro -alias mmc uboot, jaehoon +alias mmc uboot, freenix alias nand uboot alias net uboot, jhersh alias phy uboot, jhersh diff --git a/drivers/Kconfig b/drivers/Kconfig index e6702eced46..96ff4f566ab 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -14,6 +14,8 @@ source "drivers/block/Kconfig" source "drivers/bootcount/Kconfig" +source "drivers/cache/Kconfig" + source "drivers/clk/Kconfig" source "drivers/cpu/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index a7bba3ed564..0a00096332b 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -77,6 +77,7 @@ obj-$(CONFIG_BIOSEMU) += bios_emulator/ obj-y += block/ obj-y += board/ obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/ +obj-y += cache/ obj-$(CONFIG_CPU) += cpu/ obj-y += crypto/ obj-$(CONFIG_FASTBOOT) += fastboot/ diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig new file mode 100644 index 00000000000..24def7ac0fe --- /dev/null +++ b/drivers/cache/Kconfig @@ -0,0 +1,25 @@ +# +# Cache controllers +# + +menu "Cache Controller drivers" + +config CACHE + bool "Enable Driver Model for Cache controllers" + depends on DM + help + Enable driver model for cache controllers that are found on + most CPU's. Cache is memory that the CPU can access directly and + is usually located on the same chip. This uclass can be used for + configuring settings that be found from a device tree file. + +config L2X0_CACHE + tristate "PL310 cache driver" + select CACHE + depends on ARM + help + This driver is for the PL310 cache controller commonly found on + ARMv7(32-bit) devices. The driver configures the cache settings + found in the device tree. + +endmenu diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile new file mode 100644 index 00000000000..9deb961d91f --- /dev/null +++ b/drivers/cache/Makefile @@ -0,0 +1,4 @@ + +obj-$(CONFIG_CACHE) += cache-uclass.o +obj-$(CONFIG_SANDBOX) += sandbox_cache.o +obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c new file mode 100644 index 00000000000..67c752d076f --- /dev/null +++ b/drivers/cache/cache-l2x0.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ +#include <common.h> +#include <command.h> +#include <dm.h> + +#include <asm/io.h> +#include <asm/pl310.h> + +static void l2c310_of_parse_and_init(struct udevice *dev) +{ + u32 tag[3] = { 0, 0, 0 }; + u32 saved_reg, prefetch; + struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev); + + /* Disable the L2 Cache */ + clrbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN); + + saved_reg = readl(®s->pl310_aux_ctrl); + if (!dev_read_u32(dev, "prefetch-data", &prefetch)) { + if (prefetch) + saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK; + else + saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK; + } + + if (!dev_read_u32(dev, "prefetch-instr", &prefetch)) { + if (prefetch) + saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK; + else + saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK; + } + + saved_reg |= dev_read_bool(dev, "arm,shared-override"); + writel(saved_reg, ®s->pl310_aux_ctrl); + + saved_reg = readl(®s->pl310_tag_latency_ctrl); + if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3)) + saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) | + L310_LATENCY_CTRL_WR(tag[1] - 1) | + L310_LATENCY_CTRL_SETUP(tag[2] - 1); + writel(saved_reg, ®s->pl310_tag_latency_ctrl); + + saved_reg = readl(®s->pl310_data_latency_ctrl); + if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3)) + saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) | + L310_LATENCY_CTRL_WR(tag[1] - 1) | + L310_LATENCY_CTRL_SETUP(tag[2] - 1); + writel(saved_reg, ®s->pl310_data_latency_ctrl); + + /* Enable the L2 cache */ + setbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN); +} + +static int l2x0_probe(struct udevice *dev) +{ + l2c310_of_parse_and_init(dev); + + return 0; +} + + +static const struct udevice_id l2x0_ids[] = { + { .compatible = "arm,pl310-cache" }, + {} +}; + +U_BOOT_DRIVER(pl310_cache) = { + .name = "pl310_cache", + .id = UCLASS_CACHE, + .of_match = l2x0_ids, + .probe = l2x0_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c new file mode 100644 index 00000000000..97ce0249a4a --- /dev/null +++ b/drivers/cache/cache-uclass.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#include <common.h> +#include <cache.h> +#include <dm.h> + +int cache_get_info(struct udevice *dev, struct cache_info *info) +{ + struct cache_ops *ops = cache_get_ops(dev); + + if (!ops->get_info) + return -ENOSYS; + + return ops->get_info(dev, info); +} + +UCLASS_DRIVER(cache) = { + .id = UCLASS_CACHE, + .name = "cache", + .post_bind = dm_scan_fdt_dev, +}; diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c new file mode 100644 index 00000000000..14cc6b0c0ac --- /dev/null +++ b/drivers/cache/sandbox_cache.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#include <common.h> +#include <cache.h> +#include <dm.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int sandbox_get_info(struct udevice *dev, struct cache_info *info) +{ + info->base = 0x11223344; + + return 0; +} + +static const struct cache_ops sandbox_cache_ops = { + .get_info = sandbox_get_info, +}; + +static const struct udevice_id sandbox_cache_ids[] = { + { .compatible = "sandbox,cache" }, + { } +}; + +U_BOOT_DRIVER(cache_sandbox) = { + .name = "cache_sandbox", + .id = UCLASS_CACHE, + .of_match = sandbox_cache_ids, + .ops = &sandbox_cache_ops, +}; diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 9c4e8901e80..9bf9cedaf8c 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -9,9 +9,9 @@ #include <errno.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3036.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3036.h> +#include <asm/arch-rockchip/hardware.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3036-cru.h> #include <linux/log2.h> diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c index 7da785abc67..efda8c830b0 100644 --- a/drivers/clk/rockchip/clk_rk3128.c +++ b/drivers/clk/rockchip/clk_rk3128.c @@ -9,9 +9,9 @@ #include <errno.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3128.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3128.h> +#include <asm/arch-rockchip/hardware.h> #include <bitfield.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3128-cru.h> diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index db7479a2375..9bb9959c9d3 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -12,10 +12,10 @@ #include <mapmem.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3188.h> -#include <asm/arch/grf_rk3188.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3188.h> +#include <asm/arch-rockchip/grf_rk3188.h> +#include <asm/arch-rockchip/hardware.h> #include <dt-bindings/clock/rk3188-cru.h> #include <dm/device-internal.h> #include <dm/lists.h> diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 46a569c9ecd..48ed14b2aff 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -9,9 +9,9 @@ #include <errno.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk322x.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk322x.h> +#include <asm/arch-rockchip/hardware.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3228-cru.h> #include <linux/log2.h> diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 930c99f4d9f..375d7f8acbb 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -13,10 +13,10 @@ #include <mapmem.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3288.h> -#include <asm/arch/grf_rk3288.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3288.h> +#include <asm/arch-rockchip/grf_rk3288.h> +#include <asm/arch-rockchip/hardware.h> #include <dt-bindings/clock/rk3288-cru.h> #include <dm/device-internal.h> #include <dm/lists.h> diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 106621fe7cf..a89e2ecc4ad 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -9,10 +9,10 @@ #include <dm.h> #include <errno.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3328.h> -#include <asm/arch/hardware.h> -#include <asm/arch/grf_rk3328.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3328.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rk3328.h> #include <asm/io.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3328-cru.h> diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 9492cc2a36e..89cbae59c5e 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -13,9 +13,9 @@ #include <mapmem.h> #include <syscon.h> #include <bitfield.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3368.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3368.h> +#include <asm/arch-rockchip/hardware.h> #include <asm/io.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3368-cru.h> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index cab2bd99433..93a652e5ff4 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -13,9 +13,9 @@ #include <syscon.h> #include <bitfield.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3399.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/hardware.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3399-cru.h> diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index 914e2f4b214..3ebb007fab3 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -11,9 +11,9 @@ #include <errno.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rv1108.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rv1108.h> +#include <asm/arch-rockchip/hardware.h> #include <dm/lists.h> #include <dt-bindings/clock/rv1108-cru.h> diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index f78a01aa8f8..a5fc7809bc4 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -575,14 +575,6 @@ static int udma_get_tchan(struct udma_chan *uc) pr_debug("chan%d: got tchan%d\n", uc->id, uc->tchan->id); - if (udma_is_chan_running(uc)) { - dev_warn(ud->dev, "chan%d: tchan%d is running!\n", uc->id, - uc->tchan->id); - udma_stop(uc); - if (udma_is_chan_running(uc)) - dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); - } - return 0; } @@ -602,14 +594,6 @@ static int udma_get_rchan(struct udma_chan *uc) pr_debug("chan%d: got rchan%d\n", uc->id, uc->rchan->id); - if (udma_is_chan_running(uc)) { - dev_warn(ud->dev, "chan%d: rchan%d is running!\n", uc->id, - uc->rchan->id); - udma_stop(uc); - if (udma_is_chan_running(uc)) - dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); - } - return 0; } @@ -652,14 +636,6 @@ static int udma_get_chan_pair(struct udma_chan *uc) pr_debug("chan%d: got t/rchan%d pair\n", uc->id, chan_id); - if (udma_is_chan_running(uc)) { - dev_warn(ud->dev, "chan%d: t/rchan%d pair is running!\n", - uc->id, chan_id); - udma_stop(uc); - if (udma_is_chan_running(uc)) - dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); - } - return 0; } @@ -1071,6 +1047,15 @@ static int udma_alloc_chan_resources(struct udma_chan *uc) } } + if (udma_is_chan_running(uc)) { + dev_warn(ud->dev, "chan%d: is running!\n", uc->id); + udma_stop(uc); + if (udma_is_chan_running(uc)) { + dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); + goto err_free_res; + } + } + /* PSI-L pairing */ ret = udma_navss_psil_pair(ud, uc->src_thread, uc->dst_thread); if (ret) { @@ -1492,7 +1477,7 @@ static int udma_send(struct dma *dma, void *src, size_t len, void *metadata) u32 tc_ring_id; int ret; - if (!metadata) + if (metadata) packet_data = *((struct ti_udma_drv_packet_data *)metadata); if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) { diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 1196ce07123..303aa6a6311 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -158,7 +158,7 @@ static inline int ti_sci_get_response(struct ti_sci_info *info, int ret; /* Receive the response */ - ret = mbox_recv(chan, msg, info->desc->max_rx_timeout_ms); + ret = mbox_recv(chan, msg, info->desc->max_rx_timeout_ms * 1000); if (ret) { dev_err(info->dev, "%s: Message receive failed. ret = %d\n", __func__, ret); @@ -257,7 +257,8 @@ static int ti_sci_cmd_get_revision(struct ti_sci_handle *handle) info = handle_to_ti_sci_info(handle); - xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_VERSION, 0x0, + xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_VERSION, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, (u32 *)&hdr, sizeof(struct ti_sci_msg_hdr), sizeof(*rev_info)); if (IS_ERR(xfer)) { @@ -499,8 +500,8 @@ static int ti_sci_get_device_state(const struct ti_sci_handle *handle, info = handle_to_ti_sci_info(handle); - /* Response is expected, so need of any flags */ - xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_GET_DEVICE_STATE, 0, + xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_GET_DEVICE_STATE, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, (u32 *)&req, sizeof(req), sizeof(*resp)); if (IS_ERR(xfer)) { ret = PTR_ERR(xfer); @@ -2574,8 +2575,8 @@ static int ti_sci_cmd_change_fwl_owner(const struct ti_sci_handle *handle, info = handle_to_ti_sci_info(handle); - xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_FWL_GET, - TISCI_MSG_FWL_CHANGE_OWNER, + xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_FWL_CHANGE_OWNER, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, (u32 *)&req, sizeof(req), sizeof(*resp)); if (IS_ERR(xfer)) { ret = PTR_ERR(xfer); diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b3e4ecc50e1..684ca9d868f 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -351,7 +351,7 @@ config MPC8XXX_GPIO config MT7621_GPIO bool "MediaTek MT7621 GPIO driver" - depends on DM_GPIO && ARCH_MT7620 + depends on DM_GPIO && SOC_MT7628 default y help Say yes here to support MediaTek MT7621 compatible GPIOs. diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index 21df2277176..3d96678a45a 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -12,7 +12,8 @@ #include <linux/errno.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/gpio.h> #include <dm/pinctrl.h> #include <dt-bindings/clock/rk3288-cru.h> diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index 74ac0a4aa78..0a2dafcec6c 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -271,6 +271,17 @@ static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status, do { control = readl(&twsi->control); if (control & MVTWSI_CONTROL_IFLG) { + /* + * On Armada 38x it seems that the controller works as + * if it first set the MVTWSI_CONTROL_IFLAG in the + * control register and only after that it changed the + * status register. + * This sometimes caused weird bugs which only appeared + * on selected I2C speeds and even then only sometimes. + * We therefore add here a simple ndealy(100), which + * seems to fix this weird bug. + */ + ndelay(100); status = readl(&twsi->status); if (status == expected_status) return 0; diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c index f9a5796b96b..cdd94bb05a9 100644 --- a/drivers/i2c/rk_i2c.c +++ b/drivers/i2c/rk_i2c.c @@ -12,9 +12,9 @@ #include <errno.h> #include <i2c.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/i2c.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/i2c.h> +#include <asm/arch-rockchip/periph.h> #include <dm/pinctrl.h> #include <linux/sizes.h> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index c34dd5d1879..c23299ea962 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -78,6 +78,12 @@ config SUPPORT_EMMC_RPMB Enable support for reading, writing and programming the key for the Replay Protection Memory Block partition in eMMC. +config SUPPORT_EMMC_BOOT + bool "Support some additional features of the eMMC boot partitions" + help + Enable support for eMMC boot partitions. This also enables + extensions within the mmc command. + config MMC_IO_VOLTAGE bool "Support IO voltage configuration" help @@ -385,6 +391,20 @@ config MMC_SDHCI_SDMA This enables support for the SDMA (Single Operation DMA) defined in the SD Host Controller Standard Specification Version 1.00 . +config MMC_SDHCI_ADMA + bool "Support SDHCI ADMA2" + depends on MMC_SDHCI + help + This enables support for the ADMA (Advanced DMA) defined + in the SD Host Controller Standard Specification Version 3.00 + +config SPL_MMC_SDHCI_ADMA + bool "Support SDHCI ADMA2 in SPL" + depends on MMC_SDHCI + help + This enables support for the ADMA (Advanced DMA) defined + in the SD Host Controller Standard Specification Version 3.00 in SPL. + config MMC_SDHCI_ATMEL bool "Atmel SDHCI controller support" depends on ARCH_AT91 diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 93a836eac36..1992d611821 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -74,15 +74,15 @@ static void dwmci_prepare_data(struct dwmci_host *host, dwmci_set_idma_desc(cur_idmac, flags, cnt, (ulong)bounce_buffer + (i * PAGE_SIZE)); + cur_idmac++; if (blk_cnt <= 8) break; blk_cnt -= 8; - cur_idmac++; i++; } while(1); data_end = (ulong)cur_idmac; - flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN); + flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN)); ctrl = dwmci_readl(host, DWMCI_CTRL); ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; @@ -114,22 +114,40 @@ static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len) return 0; } +static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size) +{ + unsigned int timeout; + + timeout = size * 8 * 1000; /* counting in bits and msec */ + timeout *= 2; /* wait twice as long */ + timeout /= mmc->clock; + timeout /= mmc->bus_width; + timeout /= mmc->ddr_mode ? 2 : 1; + timeout = (timeout < 1000) ? 1000 : timeout; + + return timeout; +} + static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) { + struct mmc *mmc = host->mmc; int ret = 0; - u32 timeout = 240000; - u32 mask, size, i, len = 0; + u32 timeout, mask, size, i, len = 0; u32 *buf = NULL; ulong start = get_timer(0); u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1) * 2; - size = data->blocksize * data->blocks / 4; + size = data->blocksize * data->blocks; if (data->flags == MMC_DATA_READ) buf = (unsigned int *)data->dest; else buf = (unsigned int *)data->src; + timeout = dwmci_get_timeout(mmc, size); + + size /= 4; + for (;;) { mask = dwmci_readl(host, DWMCI_RINTSTS); /* Error during data transfer. */ @@ -252,14 +270,20 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); } else { if (data->flags == MMC_DATA_READ) { - bounce_buffer_start(&bbstate, (void*)data->dest, + ret = bounce_buffer_start(&bbstate, + (void*)data->dest, data->blocksize * data->blocks, GEN_BB_WRITE); } else { - bounce_buffer_start(&bbstate, (void*)data->src, + ret = bounce_buffer_start(&bbstate, + (void*)data->src, data->blocksize * data->blocks, GEN_BB_READ); } + + if (ret) + return ret; + dwmci_prepare_data(host, data, cur_idmac, bbstate.bounce_buffer); } diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 9e34557d165..1b7de74a72d 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -297,6 +297,13 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); return -ETIMEDOUT; } + } else { +#ifdef CONFIG_DM_GPIO + if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) { + printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); + return -ETIMEDOUT; + } +#endif } esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, @@ -614,18 +621,31 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) #else int pre_div = 2; #endif - int ddr_pre_div = mmc->ddr_mode ? 2 : 1; int sdhc_clk = priv->sdhc_clk; uint clk; + /* + * For ddr mode, usdhc need to enable DDR mode first, after select + * this DDR mode, usdhc will automatically divide the usdhc clock + */ + if (mmc->ddr_mode) { + writel(readl(®s->mixctrl) | MIX_CTRL_DDREN, ®s->mixctrl); + sdhc_clk >>= 1; + } + if (clock < mmc->cfg->f_min) clock = mmc->cfg->f_min; - while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) - pre_div *= 2; + if (sdhc_clk / 16 > clock) { + for (; pre_div < 256; pre_div *= 2) + if ((sdhc_clk / pre_div) <= (clock * 16)) + break; + } else + pre_div = 1; - while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) - div++; + for (div = 1; div <= 16; div++) + if ((sdhc_clk / (div * pre_div)) <= clock) + break; pre_div >>= 1; div -= 1; @@ -1489,14 +1509,15 @@ static int fsl_esdhc_probe(struct udevice *dev) #endif } - priv->wp_enable = 1; - + if (dev_read_prop(dev, "fsl,wp-controller", NULL)) { + priv->wp_enable = 1; + } else { + priv->wp_enable = 0; #ifdef CONFIG_DM_GPIO - ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, + gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); - if (ret) - priv->wp_enable = 0; #endif + } priv->vs18_enable = 0; diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index bf2d83a52c5..b2a1201631a 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -13,8 +13,8 @@ #include <pwrseq.h> #include <syscon.h> #include <asm/gpio.h> -#include <asm/arch/clock.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/periph.h> #include <linux/err.h> struct rockchip_mmc_plat { diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index cdeba914f95..e2bb90abbdf 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -67,17 +67,123 @@ static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) } } -static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, - unsigned int start_addr) +#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA) +static void sdhci_adma_desc(struct sdhci_host *host, char *buf, u16 len, + bool end) +{ + struct sdhci_adma_desc *desc; + u8 attr; + + desc = &host->adma_desc_table[host->desc_slot]; + + attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA; + if (!end) + host->desc_slot++; + else + attr |= ADMA_DESC_ATTR_END; + + desc->attr = attr; + desc->len = len; + desc->reserved = 0; + desc->addr_lo = (dma_addr_t)buf; +#ifdef CONFIG_DMA_ADDR_T_64BIT + desc->addr_hi = (u64)buf >> 32; +#endif +} + +static void sdhci_prepare_adma_table(struct sdhci_host *host, + struct mmc_data *data) +{ + uint trans_bytes = data->blocksize * data->blocks; + uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN); + int i = desc_count; + char *buf; + + host->desc_slot = 0; + + if (data->flags & MMC_DATA_READ) + buf = data->dest; + else + buf = (char *)data->src; + + while (--i) { + sdhci_adma_desc(host, buf, ADMA_MAX_LEN, false); + buf += ADMA_MAX_LEN; + trans_bytes -= ADMA_MAX_LEN; + } + + sdhci_adma_desc(host, buf, trans_bytes, true); + + flush_cache((dma_addr_t)host->adma_desc_table, + ROUND(desc_count * sizeof(struct sdhci_adma_desc), + ARCH_DMA_MINALIGN)); +} +#elif defined(CONFIG_MMC_SDHCI_SDMA) +static void sdhci_prepare_adma_table(struct sdhci_host *host, + struct mmc_data *data) +{} +#endif +#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)) +static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data, + int *is_aligned, int trans_bytes) { - unsigned int stat, rdy, mask, timeout, block = 0; - bool transfer_done = false; -#ifdef CONFIG_MMC_SDHCI_SDMA unsigned char ctrl; + + if (data->flags == MMC_DATA_READ) + host->start_addr = (dma_addr_t)data->dest; + else + host->start_addr = (dma_addr_t)data->src; + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); ctrl &= ~SDHCI_CTRL_DMA_MASK; + if (host->flags & USE_ADMA64) + ctrl |= SDHCI_CTRL_ADMA64; + else if (host->flags & USE_ADMA) + ctrl |= SDHCI_CTRL_ADMA32; sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); + + if (host->flags & USE_SDMA) { + if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && + (host->start_addr & 0x7) != 0x0) { + *is_aligned = 0; + host->start_addr = (unsigned long)aligned_buffer; + if (data->flags != MMC_DATA_READ) + memcpy(aligned_buffer, data->src, trans_bytes); + } + +#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) + /* + * Always use this bounce-buffer when + * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined + */ + *is_aligned = 0; + host->start_addr = (unsigned long)aligned_buffer; + if (data->flags != MMC_DATA_READ) + memcpy(aligned_buffer, data->src, trans_bytes); +#endif + sdhci_writel(host, host->start_addr, SDHCI_DMA_ADDRESS); + + } else if (host->flags & (USE_ADMA | USE_ADMA64)) { + sdhci_prepare_adma_table(host, data); + + sdhci_writel(host, (u32)host->adma_addr, SDHCI_ADMA_ADDRESS); + if (host->flags & USE_ADMA64) + sdhci_writel(host, (u64)host->adma_addr >> 32, + SDHCI_ADMA_ADDRESS_HI); + } + + flush_cache(host->start_addr, ROUND(trans_bytes, ARCH_DMA_MINALIGN)); +} +#else +static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data, + int *is_aligned, int trans_bytes) +{} #endif +static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data) +{ + dma_addr_t start_addr = host->start_addr; + unsigned int stat, rdy, mask, timeout, block = 0; + bool transfer_done = false; timeout = 1000000; rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; @@ -104,14 +210,17 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, continue; } } -#ifdef CONFIG_MMC_SDHCI_SDMA - if (!transfer_done && (stat & SDHCI_INT_DMA_END)) { + if ((host->flags & USE_DMA) && !transfer_done && + (stat & SDHCI_INT_DMA_END)) { sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); - start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); - start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; - sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); + if (host->flags & USE_SDMA) { + start_addr &= + ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); + start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; + sdhci_writel(host, start_addr, + SDHCI_DMA_ADDRESS); + } } -#endif if (timeout-- > 0) udelay(10); else { @@ -149,10 +258,11 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, int ret = 0; int trans_bytes = 0, is_aligned = 1; u32 mask, flags, mode; - unsigned int time = 0, start_addr = 0; + unsigned int time = 0; int mmc_dev = mmc_get_blk_desc(mmc)->devnum; ulong start = get_timer(0); + host->start_addr = 0; /* Timeout unit - ms */ static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT; @@ -218,33 +328,11 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, if (data->flags == MMC_DATA_READ) mode |= SDHCI_TRNS_READ; -#ifdef CONFIG_MMC_SDHCI_SDMA - if (data->flags == MMC_DATA_READ) - start_addr = (unsigned long)data->dest; - else - start_addr = (unsigned long)data->src; - if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && - (start_addr & 0x7) != 0x0) { - is_aligned = 0; - start_addr = (unsigned long)aligned_buffer; - if (data->flags != MMC_DATA_READ) - memcpy(aligned_buffer, data->src, trans_bytes); + if (host->flags & USE_DMA) { + mode |= SDHCI_TRNS_DMA; + sdhci_prepare_dma(host, data, &is_aligned, trans_bytes); } -#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) - /* - * Always use this bounce-buffer when - * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined - */ - is_aligned = 0; - start_addr = (unsigned long)aligned_buffer; - if (data->flags != MMC_DATA_READ) - memcpy(aligned_buffer, data->src, trans_bytes); -#endif - - sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); - mode |= SDHCI_TRNS_DMA; -#endif sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, data->blocksize), SDHCI_BLOCK_SIZE); @@ -255,12 +343,6 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, } sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); -#ifdef CONFIG_MMC_SDHCI_SDMA - if (data) { - trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE); - flush_cache(start_addr, trans_bytes); - } -#endif sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); start = get_timer(0); do { @@ -286,7 +368,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, ret = -1; if (!ret && data) - ret = sdhci_transfer_data(host, data, start_addr); + ret = sdhci_transfer_data(host, data); if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) udelay(1000); @@ -570,6 +652,24 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, __func__); return -EINVAL; } + + host->flags |= USE_SDMA; +#endif +#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA) + if (!(caps & SDHCI_CAN_DO_ADMA2)) { + printf("%s: Your controller doesn't support SDMA!!\n", + __func__); + return -EINVAL; + } + host->adma_desc_table = (struct sdhci_adma_desc *) + memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ); + + host->adma_addr = (dma_addr_t)host->adma_desc_table; +#ifdef CONFIG_DMA_ADDR_T_64BIT + host->flags |= USE_ADMA64; +#else + host->flags |= USE_ADMA; +#endif #endif if (host->quirks & SDHCI_QUIRK_REG32_RW) host->version = diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index e6a84a52b42..cfa9b535c8a 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -730,43 +730,6 @@ static int nand_davinci_dev_ready(struct mtd_info *mtd) return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1; } -static void nand_flash_init(void) -{ - /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS! - * Instead, have your board_init() set EMIF timings, based on its - * knowledge of the clocks and what devices are hooked up ... and - * don't even do that unless no UBL handled it. - */ -#ifdef CONFIG_SOC_DM644X - u_int32_t acfg1 = 0x3ffffffc; - - /*------------------------------------------------------------------* - * NAND FLASH CHIP TIMEOUT @ 459 MHz * - * * - * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz * - * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns * - * * - *------------------------------------------------------------------*/ - acfg1 = 0 - | (0 << 31) /* selectStrobe */ - | (0 << 30) /* extWait */ - | (1 << 26) /* writeSetup 10 ns */ - | (3 << 20) /* writeStrobe 40 ns */ - | (1 << 17) /* writeHold 10 ns */ - | (1 << 13) /* readSetup 10 ns */ - | (5 << 7) /* readStrobe 60 ns */ - | (1 << 4) /* readHold 10 ns */ - | (3 << 2) /* turnAround ?? ns */ - | (0 << 0) /* asyncSize 8-bit bus */ - ; - - __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */ - - /* NAND flash on CS2 */ - __raw_writel(0x00000101, &davinci_emif_regs->nandfcr); -#endif -} - void davinci_nand_init(struct nand_chip *nand) { #if defined CONFIG_KEYSTONE_RBL_NAND @@ -820,8 +783,6 @@ void davinci_nand_init(struct nand_chip *nand) nand->write_buf = nand_davinci_write_buf; nand->dev_ready = nand_davinci_dev_ready; - - nand_flash_init(); } int board_nand_init(struct nand_chip *chip) __attribute__((weak)); diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 6e436b56abf..64cdc58f92c 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -269,7 +269,7 @@ config MACB_ZYNQ config MT7628_ETH bool "MediaTek MT7628 Ethernet Interface" - depends on ARCH_MT7620 + depends on SOC_MT7628 help The MediaTek MT7628 ethernet interface is used on MT7628 and MT7688 based boards. diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index c01ae758c76..26a61211750 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -11,15 +11,15 @@ #include <phy.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/periph.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> -#include <asm/arch/grf_rk322x.h> -#include <asm/arch/grf_rk3288.h> -#include <asm/arch/grf_rk3328.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/grf_rk3399.h> -#include <asm/arch/grf_rv1108.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rk322x.h> +#include <asm/arch-rockchip/grf_rk3288.h> +#include <asm/arch-rockchip/grf_rk3328.h> +#include <asm/arch-rockchip/grf_rk3368.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/grf_rv1108.h> #include <dm/pinctrl.h> #include <dt-bindings/clock/rk3288-cru.h> #include "designware.h" diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig index 6359d0b6101..80dd22f98b7 100644 --- a/drivers/net/mscc_eswitch/Kconfig +++ b/drivers/net/mscc_eswitch/Kconfig @@ -29,3 +29,10 @@ config MSCC_SERVALT_SWITCH select PHYLIB help This driver supports the Servalt network switch device. + +config MSCC_SERVAL_SWITCH + bool "Serval switch driver" + depends on DM_ETH && ARCH_MSCC + select PHYLIB + help + This driver supports the Serval network switch device. diff --git a/drivers/net/mscc_eswitch/Makefile b/drivers/net/mscc_eswitch/Makefile index bffd8ec77b0..02f39a76bb0 100644 --- a/drivers/net/mscc_eswitch/Makefile +++ b/drivers/net/mscc_eswitch/Makefile @@ -1,5 +1,6 @@ -obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o -obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o +obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_xfer.o mscc_mac_table.o +obj-$(CONFIG_MSCC_LUTON_SWITCH) += luton_switch.o mscc_xfer.o mscc_mac_table.o obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o +obj-$(CONFIG_MSCC_SERVAL_SWITCH) += serval_switch.o mscc_xfer.o mscc_mac_table.o diff --git a/drivers/net/mscc_eswitch/luton_switch.c b/drivers/net/mscc_eswitch/luton_switch.c index 6667614966d..94852b06e74 100644 --- a/drivers/net/mscc_eswitch/luton_switch.c +++ b/drivers/net/mscc_eswitch/luton_switch.c @@ -15,10 +15,21 @@ #include <net.h> #include <wait_bit.h> -#include "mscc_miim.h" #include "mscc_xfer.h" #include "mscc_mac_table.h" +#define GCB_MIIM_MII_STATUS 0x0 +#define GCB_MIIM_STAT_BUSY BIT(3) +#define GCB_MIIM_MII_CMD 0x8 +#define GCB_MIIM_MII_CMD_OPR_WRITE BIT(1) +#define GCB_MIIM_MII_CMD_OPR_READ BIT(2) +#define GCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4) +#define GCB_MIIM_MII_CMD_REGAD(x) ((x) << 20) +#define GCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25) +#define GCB_MIIM_MII_CMD_VLD BIT(31) +#define GCB_MIIM_DATA 0xC +#define GCB_MIIM_DATA_ERROR (0x2 << 16) + #define ANA_PORT_VLAN_CFG(x) (0x00 + 0x80 * (x)) #define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20) #define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18) @@ -136,61 +147,53 @@ #define PGID_UNICAST 29 #define PGID_SRC 80 -enum luton_target { - PORT0, - PORT1, - PORT2, - PORT3, - PORT4, - PORT5, - PORT6, - PORT7, - PORT8, - PORT9, - PORT10, - PORT11, - PORT12, - PORT13, - PORT14, - PORT15, - PORT16, - PORT17, - PORT18, - PORT19, - PORT20, - PORT21, - PORT22, - PORT23, - SYS, +static const char * const regs_names[] = { + "port0", "port1", "port2", "port3", "port4", "port5", "port6", "port7", + "port8", "port9", "port10", "port11", "port12", "port13", "port14", + "port15", "port16", "port17", "port18", "port19", "port20", "port21", + "port22", "port23", + "sys", "ana", "rew", "gcb", "qs", "hsio", +}; + +#define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1 +#define MAX_PORT 24 + +enum luton_ctrl_regs { + SYS = MAX_PORT, ANA, REW, GCB, QS, - HSIO, - TARGET_MAX, + HSIO }; -#define MAX_PORT (PORT23 - PORT0 + 1) +#define MIN_INT_PORT 0 +#define PORT10 10 +#define PORT11 11 +#define MAX_INT_PORT 12 +#define MIN_EXT_PORT MAX_INT_PORT +#define MAX_EXT_PORT MAX_PORT -#define MIN_INT_PORT PORT0 -#define MAX_INT_PORT (PORT11 - PORT0 + 1) -#define MIN_EXT_PORT PORT12 -#define MAX_EXT_PORT MAX_PORT +#define LUTON_MIIM_BUS_COUNT 2 -enum luton_mdio_target { - MIIM, - TARGET_MDIO_MAX, +struct luton_phy_port_t { + size_t phy_addr; + struct mii_dev *bus; + u8 serdes_index; + u8 phy_mode; }; -enum luton_phy_id { - INTERNAL, - EXTERNAL, - NUM_PHY, +struct luton_private { + void __iomem *regs[REGS_NAMES_COUNT]; + struct mii_dev *bus[LUTON_MIIM_BUS_COUNT]; + struct luton_phy_port_t ports[MAX_PORT]; }; -struct luton_private { - void __iomem *regs[TARGET_MAX]; - struct mii_dev *bus[NUM_PHY]; +struct mscc_miim_dev { + void __iomem *regs; + phys_addr_t miim_base; + unsigned long miim_size; + struct mii_dev *bus; }; static const unsigned long luton_regs_qs[] = { @@ -207,53 +210,85 @@ static const unsigned long luton_regs_ana_table[] = { [MSCC_ANA_TABLES_MACACCESS] = 0x11b8, }; -static struct mscc_miim_dev miim[NUM_PHY]; +static struct mscc_miim_dev miim[LUTON_MIIM_BUS_COUNT]; +static int miim_count = -1; -static struct mii_dev *luton_mdiobus_init(struct udevice *dev, - int mdiobus_id) +static int mscc_miim_wait_ready(struct mscc_miim_dev *miim) +{ + return wait_for_bit_le32(miim->regs + GCB_MIIM_MII_STATUS, + GCB_MIIM_STAT_BUSY, false, 250, false); +} + +static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv; + u32 val; + int ret; + + ret = mscc_miim_wait_ready(miim); + if (ret) + goto out; + + writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) | + GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ, + miim->regs + GCB_MIIM_MII_CMD); + + ret = mscc_miim_wait_ready(miim); + if (ret) + goto out; + + val = readl(miim->regs + GCB_MIIM_DATA); + if (val & GCB_MIIM_DATA_ERROR) { + ret = -EIO; + goto out; + } + + ret = val & 0xFFFF; + out: + return ret; +} + +static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv; + int ret; + + ret = mscc_miim_wait_ready(miim); + if (ret < 0) + goto out; + + writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) | + GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_WRDATA(val) | + GCB_MIIM_MII_CMD_OPR_WRITE, miim->regs + GCB_MIIM_MII_CMD); + out: + return ret; +} + +static struct mii_dev *serval_mdiobus_init(phys_addr_t miim_base, + unsigned long miim_size) { - unsigned long phy_size[NUM_PHY]; - phys_addr_t phy_base[NUM_PHY]; - struct ofnode_phandle_args phandle; - ofnode eth_node, node, mdio_node; - struct resource res; struct mii_dev *bus; - fdt32_t faddr; - int i; bus = mdio_alloc(); if (!bus) return NULL; - /* gather only the first mdio bus */ - eth_node = dev_read_first_subnode(dev); - node = ofnode_first_subnode(eth_node); - ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0, - &phandle); - mdio_node = ofnode_get_parent(phandle.node); - - for (i = 0; i < TARGET_MDIO_MAX; i++) { - if (ofnode_read_resource(mdio_node, i, &res)) { - pr_err("%s: get OF resource failed\n", __func__); - return NULL; - } - - faddr = cpu_to_fdt32(res.start); - phy_base[i] = ofnode_translate_address(mdio_node, &faddr); - phy_size[i] = res.end - res.start; - } + ++miim_count; + sprintf(bus->name, "miim-bus%d", miim_count); - strcpy(bus->name, "miim-internal"); - miim[mdiobus_id].regs = ioremap(phy_base[mdiobus_id], - phy_size[mdiobus_id]); - bus->priv = &miim[mdiobus_id]; + miim[miim_count].regs = ioremap(miim_base, miim_size); + miim[miim_count].miim_base = miim_base; + miim[miim_count].miim_size = miim_size; + bus->priv = &miim[miim_count]; bus->read = mscc_miim_read; bus->write = mscc_miim_write; if (mdio_register(bus)) return NULL; - else - return bus; + + miim[miim_count].bus = bus; + return bus; } static void luton_stop(struct udevice *dev) @@ -324,10 +359,10 @@ static void luton_gmii_port_init(struct luton_private *priv, int port) writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) | MAC_VID, - priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0)); + priv->regs[ANA] + ANA_PORT_VLAN_CFG(port)); /* Enable switching to/from port */ - setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port - PORT0), + setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port), SYS_SWITCH_PORT_MODE_PORT_ENA); } @@ -346,10 +381,10 @@ static void luton_port_init(struct luton_private *priv, int port) writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) | MAC_VID, - priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0)); + priv->regs[ANA] + ANA_PORT_VLAN_CFG(port)); /* Enable switching to/from port */ - setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port - PORT0), + setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port), SYS_SWITCH_PORT_MODE_PORT_ENA); } @@ -393,35 +428,34 @@ static void luton_ext_port_init(struct luton_private *priv, int port) writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) | MAC_VID, - priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0)); + priv->regs[ANA] + ANA_PORT_VLAN_CFG(port)); /* Enable switching to/from port */ - setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port - PORT0), + setbits_le32(priv->regs[SYS] + SYS_SWITCH_PORT_MODE(port), SYS_SWITCH_PORT_MODE_PORT_ENA); } -static void serdes6g_write(struct luton_private *priv, u32 addr) +static void serdes6g_write(void __iomem *base, u32 addr) { u32 data; writel(HSIO_MCB_SERDES6G_CFG_WR_ONE_SHOT | HSIO_MCB_SERDES6G_CFG_ADDR(addr), - priv->regs[HSIO] + HSIO_MCB_SERDES6G_CFG); + base + HSIO_MCB_SERDES6G_CFG); do { - data = readl(priv->regs[HSIO] + HSIO_MCB_SERDES6G_CFG); + data = readl(base + HSIO_MCB_SERDES6G_CFG); } while (data & HSIO_MCB_SERDES6G_CFG_WR_ONE_SHOT); - - mdelay(100); } -static void serdes6g_cfg(struct luton_private *priv) +static void serdes6g_setup(void __iomem *base, uint32_t addr, + phy_interface_t interface) { writel(HSIO_RCOMP_CFG_CFG0_MODE_SEL(0x3) | HSIO_RCOMP_CFG_CFG0_RUN_CAL, - priv->regs[HSIO] + HSIO_RCOMP_CFG_CFG0); + base + HSIO_RCOMP_CFG_CFG0); - while (readl(priv->regs[HSIO] + HSIO_RCOMP_STATUS) & + while (readl(base + HSIO_RCOMP_STATUS) & HSIO_RCOMP_STATUS_BUSY) ; @@ -430,50 +464,64 @@ static void serdes6g_cfg(struct luton_private *priv) HSIO_SERDES6G_ANA_CFG_OB_CFG_POST0(0x10) | HSIO_SERDES6G_ANA_CFG_OB_CFG_POL | HSIO_SERDES6G_ANA_CFG_OB_CFG_ENA1V_MODE, - priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_OB_CFG); + base + HSIO_SERDES6G_ANA_CFG_OB_CFG); writel(HSIO_SERDES6G_ANA_CFG_OB_CFG1_LEV(0x18) | HSIO_SERDES6G_ANA_CFG_OB_CFG1_ENA_CAS(0x1), - priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_OB_CFG1); + base + HSIO_SERDES6G_ANA_CFG_OB_CFG1); writel(HSIO_SERDES6G_ANA_CFG_IB_CFG_RESISTOR_CTRL(0xc) | HSIO_SERDES6G_ANA_CFG_IB_CFG_VBCOM(0x4) | HSIO_SERDES6G_ANA_CFG_IB_CFG_VBAC(0x5) | HSIO_SERDES6G_ANA_CFG_IB_CFG_RT(0xf) | HSIO_SERDES6G_ANA_CFG_IB_CFG_RF(0x4), - priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_IB_CFG); + base + HSIO_SERDES6G_ANA_CFG_IB_CFG); writel(HSIO_SERDES6G_ANA_CFG_IB_CFG1_RST | HSIO_SERDES6G_ANA_CFG_IB_CFG1_ENA_OFFSDC | HSIO_SERDES6G_ANA_CFG_IB_CFG1_ENA_OFFSAC | HSIO_SERDES6G_ANA_CFG_IB_CFG1_ANEG_MODE | HSIO_SERDES6G_ANA_CFG_IB_CFG1_CHF | HSIO_SERDES6G_ANA_CFG_IB_CFG1_C(0x4), - priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_IB_CFG1); + base + HSIO_SERDES6G_ANA_CFG_IB_CFG1); writel(HSIO_SERDES6G_ANA_CFG_DES_CFG_BW_ANA(0x5) | HSIO_SERDES6G_ANA_CFG_DES_CFG_BW_HYST(0x5) | HSIO_SERDES6G_ANA_CFG_DES_CFG_MBTR_CTRL(0x2) | HSIO_SERDES6G_ANA_CFG_DES_CFG_PHS_CTRL(0x6), - priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_DES_CFG); + base + HSIO_SERDES6G_ANA_CFG_DES_CFG); writel(HSIO_SERDES6G_ANA_CFG_PLL_CFG_FSM_ENA | HSIO_SERDES6G_ANA_CFG_PLL_CFG_FSM_CTRL_DATA(0x78), - priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_PLL_CFG); + base + HSIO_SERDES6G_ANA_CFG_PLL_CFG); writel(HSIO_SERDES6G_ANA_CFG_COMMON_CFG_IF_MODE(0x30) | HSIO_SERDES6G_ANA_CFG_COMMON_CFG_ENA_LANE, - priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_COMMON_CFG); + base + HSIO_SERDES6G_ANA_CFG_COMMON_CFG); /* * There are 4 serdes6g, configure all except serdes6g0, therefore * the address is b1110 */ - serdes6g_write(priv, 0xe); + serdes6g_write(base, addr); - writel(readl(priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_COMMON_CFG) | + writel(readl(base + HSIO_SERDES6G_ANA_CFG_COMMON_CFG) | HSIO_SERDES6G_ANA_CFG_COMMON_CFG_SYS_RST, - priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_COMMON_CFG); - serdes6g_write(priv, 0xe); + base + HSIO_SERDES6G_ANA_CFG_COMMON_CFG); + serdes6g_write(base, addr); - clrbits_le32(priv->regs[HSIO] + HSIO_SERDES6G_ANA_CFG_IB_CFG1, + clrbits_le32(base + HSIO_SERDES6G_ANA_CFG_IB_CFG1, HSIO_SERDES6G_ANA_CFG_IB_CFG1_RST); writel(HSIO_SERDES6G_DIG_CFG_MISC_CFG_LANE_RST, - priv->regs[HSIO] + HSIO_SERDES6G_DIG_CFG_MISC_CFG); - serdes6g_write(priv, 0xe); + base + HSIO_SERDES6G_DIG_CFG_MISC_CFG); + serdes6g_write(base, addr); +} + +static void serdes_setup(struct luton_private *priv) +{ + size_t mask; + int i = 0; + + for (i = 0; i < MAX_PORT; ++i) { + if (!priv->ports[i].bus || priv->ports[i].serdes_index == 0xff) + continue; + + mask = BIT(priv->ports[i].serdes_index); + serdes6g_setup(priv->regs[HSIO], mask, priv->ports[i].phy_mode); + } } static int luton_switch_init(struct luton_private *priv) @@ -495,8 +543,8 @@ static int luton_switch_init(struct luton_private *priv) setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG, SYS_SYSTEM_RST_CORE_ENA); - /* Setup the Serdes6g macros */ - serdes6g_cfg(priv); + /* Setup the Serdes macros */ + serdes_setup(priv); return 0; } @@ -525,7 +573,7 @@ static int luton_initialize(struct luton_private *priv) writel(2000000000 / 4, priv->regs[SYS] + SYS_FRM_AGING); - for (i = PORT0; i < MAX_PORT; i++) { + for (i = 0; i < MAX_PORT; i++) { if (i < PORT10) luton_gmii_port_init(priv, i); else @@ -608,56 +656,51 @@ static int luton_recv(struct udevice *dev, int flags, uchar **packetp) return byte_cnt; } +static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size) +{ + int i = 0; + + for (i = 0; i < LUTON_MIIM_BUS_COUNT; ++i) + if (miim[i].miim_base == base && miim[i].miim_size == size) + return miim[i].bus; + + return NULL; +} + +static void add_port_entry(struct luton_private *priv, size_t index, + size_t phy_addr, struct mii_dev *bus, + u8 serdes_index, u8 phy_mode) +{ + priv->ports[index].phy_addr = phy_addr; + priv->ports[index].bus = bus; + priv->ports[index].serdes_index = serdes_index; + priv->ports[index].phy_mode = phy_mode; +} + static int luton_probe(struct udevice *dev) { struct luton_private *priv = dev_get_priv(dev); - int i; - - struct { - enum luton_target id; - char *name; - } reg[] = { - { PORT0, "port0" }, - { PORT1, "port1" }, - { PORT2, "port2" }, - { PORT3, "port3" }, - { PORT4, "port4" }, - { PORT5, "port5" }, - { PORT6, "port6" }, - { PORT7, "port7" }, - { PORT8, "port8" }, - { PORT9, "port9" }, - { PORT10, "port10" }, - { PORT11, "port11" }, - { PORT12, "port12" }, - { PORT13, "port13" }, - { PORT14, "port14" }, - { PORT15, "port15" }, - { PORT16, "port16" }, - { PORT17, "port17" }, - { PORT18, "port18" }, - { PORT19, "port19" }, - { PORT20, "port20" }, - { PORT21, "port21" }, - { PORT22, "port22" }, - { PORT23, "port23" }, - { SYS, "sys" }, - { ANA, "ana" }, - { REW, "rew" }, - { GCB, "gcb" }, - { QS, "qs" }, - { HSIO, "hsio" }, - }; + int i, ret; + struct resource res; + fdt32_t faddr; + phys_addr_t addr_base; + unsigned long addr_size; + ofnode eth_node, node, mdio_node; + size_t phy_addr; + struct mii_dev *bus; + struct ofnode_phandle_args phandle; + struct phy_device *phy; if (!priv) return -EINVAL; - for (i = 0; i < ARRAY_SIZE(reg); i++) { - priv->regs[reg[i].id] = dev_remap_addr_name(dev, reg[i].name); - if (!priv->regs[reg[i].id]) { + /* Get registers and map them to the private structure */ + for (i = 0; i < ARRAY_SIZE(regs_names); i++) { + priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]); + if (!priv->regs[i]) { debug ("Error can't get regs base addresses for %s\n", - reg[i].name); + regs_names[i]); return -ENOMEM; } } @@ -666,7 +709,7 @@ static int luton_probe(struct udevice *dev) writel(0, priv->regs[GCB] + GCB_DEVCPU_RST_SOFT_CHIP_RST); /* Ports with ext phy don't need to reset clk */ - for (i = PORT0; i < MAX_INT_PORT; i++) { + for (i = 0; i < MAX_INT_PORT; i++) { if (i < PORT10) clrbits_le32(priv->regs[i] + DEV_GMII_PORT_MODE_CLK, DEV_GMII_PORT_MODE_CLK_PHY_RST); @@ -680,20 +723,76 @@ static int luton_probe(struct udevice *dev) GCB_MISC_STAT_PHY_READY, true, 500, false)) return -EACCES; - priv->bus[INTERNAL] = luton_mdiobus_init(dev, INTERNAL); - for (i = 0; i < MAX_INT_PORT; i++) { - phy_connect(priv->bus[INTERNAL], i, dev, - PHY_INTERFACE_MODE_NONE); + /* Initialize miim buses */ + memset(&miim, 0x0, sizeof(miim) * LUTON_MIIM_BUS_COUNT); + + /* iterate all the ports and find out on which bus they are */ + i = 0; + eth_node = dev_read_first_subnode(dev); + for (node = ofnode_first_subnode(eth_node); + ofnode_valid(node); + node = ofnode_next_subnode(node)) { + if (ofnode_read_resource(node, 0, &res)) + return -ENOMEM; + i = res.start; + + ret = ofnode_parse_phandle_with_args(node, "phy-handle", NULL, + 0, 0, &phandle); + if (ret) + continue; + + /* Get phy address on mdio bus */ + if (ofnode_read_resource(phandle.node, 0, &res)) + return -ENOMEM; + phy_addr = res.start; + + /* Get mdio node */ + mdio_node = ofnode_get_parent(phandle.node); + + if (ofnode_read_resource(mdio_node, 0, &res)) + return -ENOMEM; + faddr = cpu_to_fdt32(res.start); + + addr_base = ofnode_translate_address(mdio_node, &faddr); + addr_size = res.end - res.start; + + /* If the bus is new then create a new bus */ + if (!get_mdiobus(addr_base, addr_size)) + priv->bus[miim_count] = + serval_mdiobus_init(addr_base, addr_size); + + /* Connect mdio bus with the port */ + bus = get_mdiobus(addr_base, addr_size); + + /* Get serdes info */ + ret = ofnode_parse_phandle_with_args(node, "phys", NULL, + 3, 0, &phandle); + if (ret) + add_port_entry(priv, i, phy_addr, bus, 0xff, 0xff); + else + add_port_entry(priv, i, phy_addr, bus, phandle.args[1], + phandle.args[2]); + } + + for (i = 0; i < MAX_PORT; i++) { + if (!priv->ports[i].bus) + continue; + + phy = phy_connect(priv->ports[i].bus, + priv->ports[i].phy_addr, dev, + PHY_INTERFACE_MODE_NONE); + if (phy && i >= MAX_INT_PORT) + board_phy_config(phy); } /* * coma_mode is need on only one phy, because all the other phys * will be affected. */ - mscc_miim_write(priv->bus[INTERNAL], 0, 0, 31, 0x10); - mscc_miim_write(priv->bus[INTERNAL], 0, 0, 14, 0x800); - mscc_miim_write(priv->bus[INTERNAL], 0, 0, 31, 0); + mscc_miim_write(priv->ports[0].bus, 0, 0, 31, 0x10); + mscc_miim_write(priv->ports[0].bus, 0, 0, 14, 0x800); + mscc_miim_write(priv->ports[0].bus, 0, 0, 31, 0); return 0; } @@ -703,7 +802,7 @@ static int luton_remove(struct udevice *dev) struct luton_private *priv = dev_get_priv(dev); int i; - for (i = 0; i < NUM_PHY; i++) { + for (i = 0; i < LUTON_MIIM_BUS_COUNT; i++) { mdio_unregister(priv->bus[i]); mdio_free(priv->bus[i]); } diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c b/drivers/net/mscc_eswitch/ocelot_switch.c index 815c2da2646..5c7e6961be4 100644 --- a/drivers/net/mscc_eswitch/ocelot_switch.c +++ b/drivers/net/mscc_eswitch/ocelot_switch.c @@ -15,7 +15,6 @@ #include <net.h> #include <wait_bit.h> -#include "mscc_miim.h" #include "mscc_xfer.h" #include "mscc_mac_table.h" @@ -26,6 +25,20 @@ #define PHY_STAT 0x4 #define PHY_STAT_SUPERVISOR_COMPLETE BIT(0) +#define GCB_MIIM_MII_STATUS 0x0 +#define GCB_MIIM_STAT_BUSY BIT(3) +#define GCB_MIIM_MII_CMD 0x8 +#define GCB_MIIM_MII_CMD_SCAN BIT(0) +#define GCB_MIIM_MII_CMD_OPR_WRITE BIT(1) +#define GCB_MIIM_MII_CMD_OPR_READ BIT(2) +#define GCB_MIIM_MII_CMD_SINGLE_SCAN BIT(3) +#define GCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4) +#define GCB_MIIM_MII_CMD_REGAD(x) ((x) << 20) +#define GCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25) +#define GCB_MIIM_MII_CMD_VLD BIT(31) +#define GCB_MIIM_DATA 0xC +#define GCB_MIIM_DATA_ERROR (0x3 << 16) + #define ANA_PORT_VLAN_CFG(x) (0x7000 + 0x100 * (x)) #define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20) #define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18) @@ -33,6 +46,41 @@ #define ANA_PORT_PORT_CFG_RECV_ENA BIT(6) #define ANA_PGID(x) (0x8c00 + 4 * (x)) +#define HSIO_ANA_SERDES1G_DES_CFG 0x4c +#define HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x) ((x) << 1) +#define HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5) +#define HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8) +#define HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << 13) +#define HSIO_ANA_SERDES1G_IB_CFG 0x50 +#define HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x) +#define HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << 6) +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP BIT(9) +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11) +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13) +#define HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << 24) +#define HSIO_ANA_SERDES1G_OB_CFG 0x54 +#define HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x) +#define HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x) ((x) << 4) +#define HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << 10) +#define HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x) ((x) << 13) +#define HSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << 17) +#define HSIO_ANA_SERDES1G_SER_CFG 0x58 +#define HSIO_ANA_SERDES1G_COMMON_CFG 0x5c +#define HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE BIT(0) +#define HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18) +#define HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST BIT(31) +#define HSIO_ANA_SERDES1G_PLL_CFG 0x60 +#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7) +#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8) +#define HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21) +#define HSIO_DIG_SERDES1G_DFT_CFG0 0x68 +#define HSIO_DIG_SERDES1G_MISC_CFG 0x7c +#define HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0) +#define HSIO_MCB_SERDES1G_CFG 0x88 +#define HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31) +#define HSIO_MCB_SERDES1G_CFG_ADDR(x) (x) +#define HSIO_HW_CFGSTAT_HW_CFG 0x10c + #define SYS_FRM_AGING 0x574 #define SYS_FRM_AGING_ENA BIT(20) @@ -83,49 +131,58 @@ #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) #define IFH_INJ_BYPASS BIT(31) -#define IFH_TAG_TYPE_C 0 -#define MAC_VID 1 +#define IFH_TAG_TYPE_C 0 +#define MAC_VID 1 #define CPU_PORT 11 -#define INTERNAL_PORT_MSK 0xF +#define INTERNAL_PORT_MSK 0x2FF #define IFH_LEN 4 #define ETH_ALEN 6 -#define PGID_BROADCAST 13 -#define PGID_UNICAST 14 -#define PGID_SRC 80 +#define PGID_BROADCAST 13 +#define PGID_UNICAST 14 +#define PGID_SRC 80 -enum ocelot_target { - ANA, - QS, - QSYS, +static const char * const regs_names[] = { + "port0", "port1", "port2", "port3", "port4", "port5", "port6", "port7", + "port8", "port9", "port10", "sys", "rew", "qs", "hsio", "qsys", "ana", +}; + +#define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1 +#define MAX_PORT 11 + +enum ocelot_ctrl_regs { + SYS = MAX_PORT, REW, - SYS, + QS, HSIO, - PORT0, - PORT1, - PORT2, - PORT3, - TARGET_MAX, + QSYS, + ANA, }; -#define MAX_PORT (PORT3 - PORT0) +#define OCELOT_MIIM_BUS_COUNT 2 -enum ocelot_mdio_target { - MIIM, - PHY, - TARGET_MDIO_MAX, +struct ocelot_phy_port_t { + size_t phy_addr; + struct mii_dev *bus; + u8 serdes_index; + u8 phy_mode; }; -enum ocelot_phy_id { - INTERNAL, - EXTERNAL, - NUM_PHY, +struct ocelot_private { + void __iomem *regs[REGS_NAMES_COUNT]; + struct mii_dev *bus[OCELOT_MIIM_BUS_COUNT]; + struct ocelot_phy_port_t ports[MAX_PORT]; }; -struct ocelot_private { - void __iomem *regs[TARGET_MAX]; - struct mii_dev *bus[NUM_PHY]; +struct mscc_miim_dev { + void __iomem *regs; + phys_addr_t miim_base; + unsigned long miim_size; + struct mii_dev *bus; }; +static struct mscc_miim_dev miim[OCELOT_MIIM_BUS_COUNT]; +static int miim_count = -1; + static const unsigned long ocelot_regs_qs[] = { [MSCC_QS_XTR_RD] = 0x8, [MSCC_QS_XTR_FLUSH] = 0x18, @@ -140,65 +197,95 @@ static const unsigned long ocelot_regs_ana_table[] = { [MSCC_ANA_TABLES_MACACCESS] = 0x8b3c, }; -static struct mscc_miim_dev miim[NUM_PHY]; - static void mscc_phy_reset(void) { - writel(0, miim[INTERNAL].phy_regs + PHY_CFG); + writel(0, BASE_DEVCPU_GCB + PERF_PHY_CFG + PHY_CFG); writel(PHY_CFG_RST | PHY_CFG_COMMON_RST - | PHY_CFG_ENA, miim[INTERNAL].phy_regs + PHY_CFG); - if (wait_for_bit_le32(miim[INTERNAL].phy_regs + PHY_STAT, - PHY_STAT_SUPERVISOR_COMPLETE, + | PHY_CFG_ENA, BASE_DEVCPU_GCB + PERF_PHY_CFG + PHY_CFG); + if (wait_for_bit_le32((const void *)(BASE_DEVCPU_GCB + PERF_PHY_CFG) + + PHY_STAT, PHY_STAT_SUPERVISOR_COMPLETE, true, 2000, false)) { pr_err("Timeout in phy reset\n"); } } -/* For now only setup the internal mdio bus */ -static struct mii_dev *ocelot_mdiobus_init(struct udevice *dev) +static int mscc_miim_wait_ready(struct mscc_miim_dev *miim) +{ + return wait_for_bit_le32(miim->regs + GCB_MIIM_MII_STATUS, + GCB_MIIM_STAT_BUSY, false, 250, false); +} + +static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv; + u32 val; + int ret; + + ret = mscc_miim_wait_ready(miim); + if (ret) + goto out; + + writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) | + GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ, + miim->regs + GCB_MIIM_MII_CMD); + + ret = mscc_miim_wait_ready(miim); + if (ret) + goto out; + + val = readl(miim->regs + GCB_MIIM_DATA); + if (val & GCB_MIIM_DATA_ERROR) { + ret = -EIO; + goto out; + } + + ret = val & 0xFFFF; + out: + return ret; +} + +static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv; + int ret; + + ret = mscc_miim_wait_ready(miim); + if (ret < 0) + goto out; + + writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) | + GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_WRDATA(val) | + GCB_MIIM_MII_CMD_OPR_WRITE, miim->regs + GCB_MIIM_MII_CMD); + out: + return ret; +} + +static struct mii_dev *ocelot_mdiobus_init(phys_addr_t miim_base, + unsigned long miim_size) { - unsigned long phy_size[TARGET_MAX]; - phys_addr_t phy_base[TARGET_MAX]; - struct ofnode_phandle_args phandle; - ofnode eth_node, node, mdio_node; - struct resource res; struct mii_dev *bus; - fdt32_t faddr; - int i; bus = mdio_alloc(); if (!bus) return NULL; - /* gathered only the first mdio bus */ - eth_node = dev_read_first_subnode(dev); - node = ofnode_first_subnode(eth_node); - ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0, - &phandle); - mdio_node = ofnode_get_parent(phandle.node); - - for (i = 0; i < TARGET_MDIO_MAX; i++) { - if (ofnode_read_resource(mdio_node, i, &res)) { - pr_err("%s: get OF resource failed\n", __func__); - return NULL; - } - faddr = cpu_to_fdt32(res.start); - phy_base[i] = ofnode_translate_address(mdio_node, &faddr); - phy_size[i] = res.end - res.start; - } + ++miim_count; + sprintf(bus->name, "miim-bus%d", miim_count); - strcpy(bus->name, "miim-internal"); - miim[INTERNAL].phy_regs = ioremap(phy_base[PHY], phy_size[PHY]); - miim[INTERNAL].regs = ioremap(phy_base[MIIM], phy_size[MIIM]); - bus->priv = &miim[INTERNAL]; + miim[miim_count].regs = ioremap(miim_base, miim_size); + miim[miim_count].miim_base = miim_base; + miim[miim_count].miim_size = miim_size; + bus->priv = &miim[miim_count]; bus->read = mscc_miim_read; bus->write = mscc_miim_write; if (mdio_register(bus)) return NULL; - else - return bus; + + miim[miim_count].bus = bus; + return bus; } __weak void mscc_switch_reset(void) @@ -291,13 +378,87 @@ static void ocelot_port_init(struct ocelot_private *priv, int port) /* Make VLAN aware for CPU traffic */ writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) | - MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0)); + MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port)); /* Enable the port in the core */ - setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port - PORT0), + setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port), QSYS_SWITCH_PORT_MODE_PORT_ENA); } +static void serdes1g_write(void __iomem *base, u32 addr) +{ + u32 data; + + writel(HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT | + HSIO_MCB_SERDES1G_CFG_ADDR(addr), + base + HSIO_MCB_SERDES1G_CFG); + + do { + data = readl(base + HSIO_MCB_SERDES1G_CFG); + } while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT); +} + +static void serdes1g_setup(void __iomem *base, uint32_t addr, + phy_interface_t interface) +{ + writel(0x34, base + HSIO_HW_CFGSTAT_HW_CFG); + + writel(0x0, base + HSIO_ANA_SERDES1G_SER_CFG); + writel(0x0, base + HSIO_DIG_SERDES1G_DFT_CFG0); + writel(HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(11) | + HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(0) | + HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP | + HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM | + HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(1), + base + HSIO_ANA_SERDES1G_IB_CFG); + writel(HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(7) | + HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(6) | + HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(2) | + HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(6), + base + HSIO_ANA_SERDES1G_DES_CFG); + writel(HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(1) | + HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(4) | + HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(2) | + HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(12) | + HSIO_ANA_SERDES1G_OB_CFG_SLP(3), + base + HSIO_ANA_SERDES1G_OB_CFG); + writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE | + HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE, + base + HSIO_ANA_SERDES1G_COMMON_CFG); + writel(HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA | + HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(200) | + HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2, + base + HSIO_ANA_SERDES1G_PLL_CFG); + writel(HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST, + base + HSIO_DIG_SERDES1G_MISC_CFG); + + serdes1g_write(base, addr); + + writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE | + HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE | + HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST, + base + HSIO_ANA_SERDES1G_COMMON_CFG); + serdes1g_write(base, addr); + + writel(0x0, base + HSIO_DIG_SERDES1G_MISC_CFG); + serdes1g_write(base, addr); +} + +static void serdes_setup(struct ocelot_private *priv) +{ + size_t mask; + int i = 0; + + for (i = 0; i < MAX_PORT; ++i) { + if (!priv->ports[i].bus || priv->ports[i].serdes_index == 0xff) + continue; + + mask = BIT(priv->ports[i].serdes_index); + serdes1g_setup(priv->regs[HSIO], mask, + priv->ports[i].phy_mode); + } +} + static int ocelot_switch_init(struct ocelot_private *priv) { /* Reset switch & memories */ @@ -315,6 +476,7 @@ static int ocelot_switch_init(struct ocelot_private *priv) setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG, SYS_SYSTEM_RST_CORE_ENA); + serdes_setup(priv); return 0; } @@ -331,7 +493,7 @@ static int ocelot_initialize(struct ocelot_private *priv) * Put fron ports in "port isolation modes" - i.e. they cant send * to other ports - via the PGID sorce masks. */ - for (i = 0; i <= MAX_PORT; i++) + for (i = 0; i < MAX_PORT; i++) writel(0, priv->regs[ANA] + ANA_PGID(PGID_SRC + i)); /* Flush queues */ @@ -341,7 +503,7 @@ static int ocelot_initialize(struct ocelot_private *priv) writel(SYS_FRM_AGING_ENA | (20000000 / 65), priv->regs[SYS] + SYS_FRM_AGING); - for (i = PORT0; i <= PORT3; i++) + for (i = 0; i < MAX_PORT; i++) ocelot_port_init(priv, i); ocelot_cpu_capture_setup(priv); @@ -433,43 +595,119 @@ static int ocelot_recv(struct udevice *dev, int flags, uchar **packetp) return byte_cnt; } +static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size) +{ + int i = 0; + + for (i = 0; i < OCELOT_MIIM_BUS_COUNT; ++i) + if (miim[i].miim_base == base && miim[i].miim_size == size) + return miim[i].bus; + + return NULL; +} + +static void add_port_entry(struct ocelot_private *priv, size_t index, + size_t phy_addr, struct mii_dev *bus, + u8 serdes_index, u8 phy_mode) +{ + priv->ports[index].phy_addr = phy_addr; + priv->ports[index].bus = bus; + priv->ports[index].serdes_index = serdes_index; + priv->ports[index].phy_mode = phy_mode; +} + +static int external_bus(struct ocelot_private *priv, size_t port_index) +{ + return priv->ports[port_index].serdes_index != 0xff; +} + static int ocelot_probe(struct udevice *dev) { struct ocelot_private *priv = dev_get_priv(dev); - int ret, i; + int i, ret; + struct resource res; + fdt32_t faddr; + phys_addr_t addr_base; + unsigned long addr_size; + ofnode eth_node, node, mdio_node; + size_t phy_addr; + struct mii_dev *bus; + struct ofnode_phandle_args phandle; + struct phy_device *phy; + + if (!priv) + return -EINVAL; - struct { - enum ocelot_target id; - char *name; - } reg[] = { - { SYS, "sys" }, - { REW, "rew" }, - { QSYS, "qsys" }, - { ANA, "ana" }, - { QS, "qs" }, - { HSIO, "hsio" }, - { PORT0, "port0" }, - { PORT1, "port1" }, - { PORT2, "port2" }, - { PORT3, "port3" }, - }; - - for (i = 0; i < ARRAY_SIZE(reg); i++) { - priv->regs[reg[i].id] = dev_remap_addr_name(dev, reg[i].name); - if (!priv->regs[reg[i].id]) { - pr_err - ("Error %d: can't get regs base addresses for %s\n", - ret, reg[i].name); + for (i = 0; i < ARRAY_SIZE(regs_names); i++) { + priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]); + if (!priv->regs[i]) { + debug + ("Error can't get regs base addresses for %s\n", + regs_names[i]); return -ENOMEM; } } - priv->bus[INTERNAL] = ocelot_mdiobus_init(dev); + /* Initialize miim buses */ + memset(&miim, 0x0, sizeof(struct mscc_miim_dev) * + OCELOT_MIIM_BUS_COUNT); + + /* iterate all the ports and find out on which bus they are */ + i = 0; + eth_node = dev_read_first_subnode(dev); + for (node = ofnode_first_subnode(eth_node); ofnode_valid(node); + node = ofnode_next_subnode(node)) { + if (ofnode_read_resource(node, 0, &res)) + return -ENOMEM; + i = res.start; + + ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0, + &phandle); + + /* Get phy address on mdio bus */ + if (ofnode_read_resource(phandle.node, 0, &res)) + return -ENOMEM; + phy_addr = res.start; + + /* Get mdio node */ + mdio_node = ofnode_get_parent(phandle.node); + + if (ofnode_read_resource(mdio_node, 0, &res)) + return -ENOMEM; + faddr = cpu_to_fdt32(res.start); + + addr_base = ofnode_translate_address(mdio_node, &faddr); + addr_size = res.end - res.start; + + /* If the bus is new then create a new bus */ + if (!get_mdiobus(addr_base, addr_size)) + priv->bus[miim_count] = + ocelot_mdiobus_init(addr_base, addr_size); + + /* Connect mdio bus with the port */ + bus = get_mdiobus(addr_base, addr_size); + + /* Get serdes info */ + ret = ofnode_parse_phandle_with_args(node, "phys", NULL, + 3, 0, &phandle); + if (ret) + add_port_entry(priv, i, phy_addr, bus, 0xff, 0xff); + else + add_port_entry(priv, i, phy_addr, bus, phandle.args[1], + phandle.args[2]); + } + mscc_phy_reset(); - for (i = 0; i < 4; i++) { - phy_connect(priv->bus[INTERNAL], i, dev, - PHY_INTERFACE_MODE_NONE); + for (i = 0; i < MAX_PORT; i++) { + if (!priv->ports[i].bus) + continue; + + phy = phy_connect(priv->ports[i].bus, + priv->ports[i].phy_addr, dev, + PHY_INTERFACE_MODE_NONE); + if (phy && external_bus(priv, i)) + board_phy_config(phy); } return 0; @@ -480,7 +718,7 @@ static int ocelot_remove(struct udevice *dev) struct ocelot_private *priv = dev_get_priv(dev); int i; - for (i = 0; i < NUM_PHY; i++) { + for (i = 0; i < OCELOT_MIIM_BUS_COUNT; i++) { mdio_unregister(priv->bus[i]); mdio_free(priv->bus[i]); } diff --git a/drivers/net/mscc_eswitch/serval_switch.c b/drivers/net/mscc_eswitch/serval_switch.c new file mode 100644 index 00000000000..2559f5d0cd1 --- /dev/null +++ b/drivers/net/mscc_eswitch/serval_switch.c @@ -0,0 +1,703 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Microsemi Corporation + */ + +#include <common.h> +#include <config.h> +#include <dm.h> +#include <dm/of_access.h> +#include <dm/of_addr.h> +#include <fdt_support.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <miiphy.h> +#include <net.h> +#include <wait_bit.h> + +#include "mscc_xfer.h" +#include "mscc_mac_table.h" + +#define GCB_MIIM_MII_STATUS 0x0 +#define GCB_MIIM_STAT_BUSY BIT(3) +#define GCB_MIIM_MII_CMD 0x8 +#define GCB_MIIM_MII_CMD_OPR_WRITE BIT(1) +#define GCB_MIIM_MII_CMD_OPR_READ BIT(2) +#define GCB_MIIM_MII_CMD_WRDATA(x) ((x) << 4) +#define GCB_MIIM_MII_CMD_REGAD(x) ((x) << 20) +#define GCB_MIIM_MII_CMD_PHYAD(x) ((x) << 25) +#define GCB_MIIM_MII_CMD_VLD BIT(31) +#define GCB_MIIM_DATA 0xC +#define GCB_MIIM_DATA_ERROR (0x2 << 16) + +#define ANA_PORT_VLAN_CFG(x) (0xc000 + 0x100 * (x)) +#define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20) +#define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18) +#define ANA_PORT_PORT_CFG(x) (0xc070 + 0x100 * (x)) +#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6) +#define ANA_PGID(x) (0x9c00 + 4 * (x)) + +#define HSIO_ANA_SERDES1G_DES_CFG 0x3c +#define HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x) ((x) << 1) +#define HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5) +#define HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8) +#define HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << 13) +#define HSIO_ANA_SERDES1G_IB_CFG 0x40 +#define HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x) +#define HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << 6) +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP BIT(9) +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11) +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13) +#define HSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x) ((x) << 19) +#define HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << 24) +#define HSIO_ANA_SERDES1G_OB_CFG 0x44 +#define HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x) +#define HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x) ((x) << 4) +#define HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << 10) +#define HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x) ((x) << 13) +#define HSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << 17) +#define HSIO_ANA_SERDES1G_SER_CFG 0x48 +#define HSIO_ANA_SERDES1G_COMMON_CFG 0x4c +#define HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE BIT(0) +#define HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18) +#define HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST BIT(31) +#define HSIO_ANA_SERDES1G_PLL_CFG 0x50 +#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7) +#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8) +#define HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21) +#define HSIO_DIG_SERDES1G_DFT_CFG0 0x58 +#define HSIO_DIG_SERDES1G_MISC_CFG 0x6c +#define HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0) +#define HSIO_MCB_SERDES1G_CFG 0x74 +#define HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31) +#define HSIO_MCB_SERDES1G_CFG_ADDR(x) (x) + +#define SYS_FRM_AGING 0x584 +#define SYS_FRM_AGING_ENA BIT(20) +#define SYS_SYSTEM_RST_CFG 0x518 +#define SYS_SYSTEM_RST_MEM_INIT BIT(5) +#define SYS_SYSTEM_RST_MEM_ENA BIT(6) +#define SYS_SYSTEM_RST_CORE_ENA BIT(7) +#define SYS_PORT_MODE(x) (0x524 + 0x4 * (x)) +#define SYS_PORT_MODE_INCL_INJ_HDR(x) ((x) << 4) +#define SYS_PORT_MODE_INCL_XTR_HDR(x) ((x) << 2) +#define SYS_PAUSE_CFG(x) (0x65c + 0x4 * (x)) +#define SYS_PAUSE_CFG_PAUSE_ENA BIT(0) + +#define QSYS_SWITCH_PORT_MODE(x) (0x15a34 + 0x4 * (x)) +#define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(13) +#define QSYS_EGR_NO_SHARING 0x15a9c +#define QSYS_QMAP 0x15adc + +/* Port registers */ +#define DEV_CLOCK_CFG 0x0 +#define DEV_CLOCK_CFG_LINK_SPEED_1000 1 +#define DEV_MAC_ENA_CFG 0x10 +#define DEV_MAC_ENA_CFG_RX_ENA BIT(4) +#define DEV_MAC_ENA_CFG_TX_ENA BIT(0) +#define DEV_MAC_IFG_CFG 0x24 +#define DEV_MAC_IFG_CFG_TX_IFG(x) ((x) << 8) +#define DEV_MAC_IFG_CFG_RX_IFG2(x) ((x) << 4) +#define DEV_MAC_IFG_CFG_RX_IFG1(x) (x) +#define PCS1G_CFG 0x3c +#define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) +#define PCS1G_MODE_CFG 0x40 +#define PCS1G_SD_CFG 0x44 +#define PCS1G_ANEG_CFG 0x48 +#define PCS1G_ANEG_CFG_ADV_ABILITY(x) ((x) << 16) + +#define QS_XTR_GRP_CFG(x) (4 * (x)) +#define QS_XTR_GRP_CFG_MODE(x) ((x) << 2) +#define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) +#define QS_INJ_GRP_CFG(x) (0x24 + (x) * 4) +#define QS_INJ_GRP_CFG_MODE(x) ((x) << 2) +#define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) + +#define IFH_INJ_BYPASS BIT(31) +#define IFH_TAG_TYPE_C 0 +#define MAC_VID 1 +#define CPU_PORT 11 +#define INTERNAL_PORT_MSK 0xFF +#define IFH_LEN 4 +#define ETH_ALEN 6 +#define PGID_BROADCAST 13 +#define PGID_UNICAST 14 + +static const char *const regs_names[] = { + "port0", "port1", "port2", "port3", "port4", "port5", "port6", + "port7", "port8", "port9", "port10", + "ana", "qs", "qsys", "rew", "sys", "hsio", +}; + +#define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1 +#define MAX_PORT 11 + +enum serval_ctrl_regs { + ANA = MAX_PORT, + QS, + QSYS, + REW, + SYS, + HSIO, +}; + +#define SERVAL_MIIM_BUS_COUNT 2 + +struct serval_phy_port_t { + size_t phy_addr; + struct mii_dev *bus; + u8 serdes_index; + u8 phy_mode; +}; + +struct serval_private { + void __iomem *regs[REGS_NAMES_COUNT]; + struct mii_dev *bus[SERVAL_MIIM_BUS_COUNT]; + struct serval_phy_port_t ports[MAX_PORT]; +}; + +struct mscc_miim_dev { + void __iomem *regs; + phys_addr_t miim_base; + unsigned long miim_size; + struct mii_dev *bus; +}; + +static const unsigned long serval_regs_qs[] = { + [MSCC_QS_XTR_RD] = 0x8, + [MSCC_QS_XTR_FLUSH] = 0x18, + [MSCC_QS_XTR_DATA_PRESENT] = 0x1c, + [MSCC_QS_INJ_WR] = 0x2c, + [MSCC_QS_INJ_CTRL] = 0x34, +}; + +static const unsigned long serval_regs_ana_table[] = { + [MSCC_ANA_TABLES_MACHDATA] = 0x9b34, + [MSCC_ANA_TABLES_MACLDATA] = 0x9b38, + [MSCC_ANA_TABLES_MACACCESS] = 0x9b3c, +}; + +static struct mscc_miim_dev miim[SERVAL_MIIM_BUS_COUNT]; +static int miim_count = -1; + +static int mscc_miim_wait_ready(struct mscc_miim_dev *miim) +{ + return wait_for_bit_le32(miim->regs + GCB_MIIM_MII_STATUS, + GCB_MIIM_STAT_BUSY, false, 250, false); +} + +static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv; + u32 val; + int ret; + + ret = mscc_miim_wait_ready(miim); + if (ret) + goto out; + + writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) | + GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_OPR_READ, + miim->regs + GCB_MIIM_MII_CMD); + + ret = mscc_miim_wait_ready(miim); + if (ret) + goto out; + + val = readl(miim->regs + GCB_MIIM_DATA); + if (val & GCB_MIIM_DATA_ERROR) { + ret = -EIO; + goto out; + } + + ret = val & 0xFFFF; + out: + return ret; +} + +static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv; + int ret; + + ret = mscc_miim_wait_ready(miim); + if (ret < 0) + goto out; + + writel(GCB_MIIM_MII_CMD_VLD | GCB_MIIM_MII_CMD_PHYAD(addr) | + GCB_MIIM_MII_CMD_REGAD(reg) | GCB_MIIM_MII_CMD_WRDATA(val) | + GCB_MIIM_MII_CMD_OPR_WRITE, miim->regs + GCB_MIIM_MII_CMD); + out: + return ret; +} + +static struct mii_dev *serval_mdiobus_init(phys_addr_t miim_base, + unsigned long miim_size) +{ + struct mii_dev *bus; + + bus = mdio_alloc(); + if (!bus) + return NULL; + + ++miim_count; + sprintf(bus->name, "miim-bus%d", miim_count); + + miim[miim_count].regs = ioremap(miim_base, miim_size); + miim[miim_count].miim_base = miim_base; + miim[miim_count].miim_size = miim_size; + bus->priv = &miim[miim_count]; + bus->read = mscc_miim_read; + bus->write = mscc_miim_write; + + if (mdio_register(bus)) + return NULL; + + miim[miim_count].bus = bus; + return bus; +} + +static void serval_cpu_capture_setup(struct serval_private *priv) +{ + int i; + + /* map the 8 CPU extraction queues to CPU port 11 */ + writel(0, priv->regs[QSYS] + QSYS_QMAP); + + for (i = 0; i <= 1; i++) { + /* + * Do byte-swap and expect status after last data word + * Extraction: Mode: manual extraction) | Byte_swap + */ + writel(QS_XTR_GRP_CFG_MODE(1) | QS_XTR_GRP_CFG_BYTE_SWAP, + priv->regs[QS] + QS_XTR_GRP_CFG(i)); + /* + * Injection: Mode: manual extraction | Byte_swap + */ + writel(QS_INJ_GRP_CFG_MODE(1) | QS_INJ_GRP_CFG_BYTE_SWAP, + priv->regs[QS] + QS_INJ_GRP_CFG(i)); + } + + for (i = 0; i <= 1; i++) + /* Enable IFH insertion/parsing on CPU ports */ + writel(SYS_PORT_MODE_INCL_INJ_HDR(1) | + SYS_PORT_MODE_INCL_XTR_HDR(1), + priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i)); + /* + * Setup the CPU port as VLAN aware to support switching frames + * based on tags + */ + writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) | + MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT)); + + /* Disable learning (only RECV_ENA must be set) */ + writel(ANA_PORT_PORT_CFG_RECV_ENA, + priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT)); + + /* Enable switching to/from cpu port */ + setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT), + QSYS_SWITCH_PORT_MODE_PORT_ENA); + + /* No pause on CPU port - not needed (off by default) */ + clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT), + SYS_PAUSE_CFG_PAUSE_ENA); + + setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT)); +} + +static void serval_port_init(struct serval_private *priv, int port) +{ + void __iomem *regs = priv->regs[port]; + + /* Enable PCS */ + writel(PCS1G_MODE_CFG_SGMII_MODE_ENA, regs + PCS1G_CFG); + + /* Disable Signal Detect */ + writel(0, regs + PCS1G_SD_CFG); + + /* Enable MAC RX and TX */ + writel(DEV_MAC_ENA_CFG_RX_ENA | DEV_MAC_ENA_CFG_TX_ENA, + regs + DEV_MAC_ENA_CFG); + + /* Clear sgmii_mode_ena */ + writel(0, regs + PCS1G_MODE_CFG); + + /* + * Clear sw_resolve_ena(bit 0) and set adv_ability to + * something meaningful just in case + */ + writel(PCS1G_ANEG_CFG_ADV_ABILITY(0x20), regs + PCS1G_ANEG_CFG); + + /* Set MAC IFG Gaps */ + writel(DEV_MAC_IFG_CFG_TX_IFG(5) | DEV_MAC_IFG_CFG_RX_IFG1(5) | + DEV_MAC_IFG_CFG_RX_IFG2(1), regs + DEV_MAC_IFG_CFG); + + /* Set link speed and release all resets */ + writel(DEV_CLOCK_CFG_LINK_SPEED_1000, regs + DEV_CLOCK_CFG); + + /* Make VLAN aware for CPU traffic */ + writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) | + MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port)); + + /* Enable the port in the core */ + setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port), + QSYS_SWITCH_PORT_MODE_PORT_ENA); +} + +static void serdes_write(void __iomem *base, u32 addr) +{ + u32 data; + + writel(HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT | + HSIO_MCB_SERDES1G_CFG_ADDR(addr), + base + HSIO_MCB_SERDES1G_CFG); + + do { + data = readl(base + HSIO_MCB_SERDES1G_CFG); + } while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT); + + mdelay(100); +} + +static void serdes1g_setup(void __iomem *base, uint32_t addr, + phy_interface_t interface) +{ + writel(0x0, base + HSIO_ANA_SERDES1G_SER_CFG); + writel(0x0, base + HSIO_DIG_SERDES1G_DFT_CFG0); + writel(HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(11) | + HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(0) | + HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP | + HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM | + HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(1), + base + HSIO_ANA_SERDES1G_IB_CFG); + writel(HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(7) | + HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(6) | + HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(2) | + HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(6), + base + HSIO_ANA_SERDES1G_DES_CFG); + writel(HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(1) | + HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(4) | + HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(2) | + HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(12) | + HSIO_ANA_SERDES1G_OB_CFG_SLP(3), + base + HSIO_ANA_SERDES1G_OB_CFG); + writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE | + HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE, + base + HSIO_ANA_SERDES1G_COMMON_CFG); + writel(HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA | + HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(200) | + HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2, + base + HSIO_ANA_SERDES1G_PLL_CFG); + writel(HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST, + base + HSIO_DIG_SERDES1G_MISC_CFG); + serdes_write(base, addr); + + writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE | + HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE | + HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST, + base + HSIO_ANA_SERDES1G_COMMON_CFG); + serdes_write(base, addr); + + writel(0x0, base + HSIO_DIG_SERDES1G_MISC_CFG); + serdes_write(base, addr); +} + +static void serdes_setup(struct serval_private *priv) +{ + size_t mask; + int i = 0; + + for (i = 0; i < MAX_PORT; ++i) { + if (!priv->ports[i].bus) + continue; + + mask = BIT(priv->ports[i].serdes_index); + serdes1g_setup(priv->regs[HSIO], mask, + priv->ports[i].phy_mode); + } +} + +static int serval_switch_init(struct serval_private *priv) +{ + /* Reset switch & memories */ + writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT, + priv->regs[SYS] + SYS_SYSTEM_RST_CFG); + + if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG, + SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) { + pr_err("Timeout in memory reset\n"); + return -EIO; + } + + /* Enable switch core */ + setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG, + SYS_SYSTEM_RST_CORE_ENA); + + serdes_setup(priv); + + return 0; +} + +static int serval_initialize(struct serval_private *priv) +{ + int ret, i; + + /* Initialize switch memories, enable core */ + ret = serval_switch_init(priv); + if (ret) + return ret; + + /* Flush queues */ + mscc_flush(priv->regs[QS], serval_regs_qs); + + /* Setup frame ageing - "2 sec" - The unit is 6.5us on serval */ + writel(SYS_FRM_AGING_ENA | (20000000 / 65), + priv->regs[SYS] + SYS_FRM_AGING); + + for (i = 0; i < MAX_PORT; i++) + serval_port_init(priv, i); + + serval_cpu_capture_setup(priv); + + debug("Ports enabled\n"); + + return 0; +} + +static int serval_write_hwaddr(struct udevice *dev) +{ + struct serval_private *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + + mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table, + pdata->enetaddr, PGID_UNICAST); + + writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST)); + + return 0; +} + +static int serval_start(struct udevice *dev) +{ + struct serval_private *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff }; + int ret; + + ret = serval_initialize(priv); + if (ret) + return ret; + + /* Set MAC address tables entries for CPU redirection */ + mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table, mac, + PGID_BROADCAST); + + writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK, + priv->regs[ANA] + ANA_PGID(PGID_BROADCAST)); + + /* It should be setup latter in serval_write_hwaddr */ + mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table, + pdata->enetaddr, PGID_UNICAST); + + writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST)); + return 0; +} + +static void serval_stop(struct udevice *dev) +{ + writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET); + writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); +} + +static int serval_send(struct udevice *dev, void *packet, int length) +{ + struct serval_private *priv = dev_get_priv(dev); + u32 ifh[IFH_LEN]; + u32 *buf = packet; + + /* + * Generate the IFH for frame injection + * + * The IFH is a 128bit-value + * bit 127: bypass the analyzer processing + * bit 57-67: destination mask + * bit 28-29: pop_cnt: 3 disables all rewriting of the frame + * bit 20-27: cpu extraction queue mask + * bit 16: tag type 0: C-tag, 1: S-tag + * bit 0-11: VID + */ + ifh[0] = IFH_INJ_BYPASS; + ifh[1] = (0x07); + ifh[2] = (0x7f) << 25; + ifh[3] = (IFH_TAG_TYPE_C << 16); + + return mscc_send(priv->regs[QS], serval_regs_qs, + ifh, IFH_LEN, buf, length); +} + +static int serval_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct serval_private *priv = dev_get_priv(dev); + u32 *rxbuf = (u32 *)net_rx_packets[0]; + int byte_cnt = 0; + + byte_cnt = mscc_recv(priv->regs[QS], serval_regs_qs, rxbuf, IFH_LEN, + false); + + *packetp = net_rx_packets[0]; + + return byte_cnt; +} + +static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size) +{ + int i = 0; + + for (i = 0; i < SERVAL_MIIM_BUS_COUNT; ++i) + if (miim[i].miim_base == base && miim[i].miim_size == size) + return miim[i].bus; + + return NULL; +} + +static void add_port_entry(struct serval_private *priv, size_t index, + size_t phy_addr, struct mii_dev *bus, + u8 serdes_index, u8 phy_mode) +{ + priv->ports[index].phy_addr = phy_addr; + priv->ports[index].bus = bus; + priv->ports[index].serdes_index = serdes_index; + priv->ports[index].phy_mode = phy_mode; +} + +static int serval_probe(struct udevice *dev) +{ + struct serval_private *priv = dev_get_priv(dev); + int i, ret; + struct resource res; + fdt32_t faddr; + phys_addr_t addr_base; + unsigned long addr_size; + ofnode eth_node, node, mdio_node; + size_t phy_addr; + struct mii_dev *bus; + struct ofnode_phandle_args phandle; + struct phy_device *phy; + + if (!priv) + return -EINVAL; + + /* Get registers and map them to the private structure */ + for (i = 0; i < ARRAY_SIZE(regs_names); i++) { + priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]); + if (!priv->regs[i]) { + debug + ("Error can't get regs base addresses for %s\n", + regs_names[i]); + return -ENOMEM; + } + } + + /* Initialize miim buses */ + memset(&miim, 0x0, sizeof(miim) * SERVAL_MIIM_BUS_COUNT); + + /* iterate all the ports and find out on which bus they are */ + i = 0; + eth_node = dev_read_first_subnode(dev); + for (node = ofnode_first_subnode(eth_node); + ofnode_valid(node); + node = ofnode_next_subnode(node)) { + if (ofnode_read_resource(node, 0, &res)) + return -ENOMEM; + i = res.start; + + ret = ofnode_parse_phandle_with_args(node, "phy-handle", NULL, + 0, 0, &phandle); + if (ret) + continue; + + /* Get phy address on mdio bus */ + if (ofnode_read_resource(phandle.node, 0, &res)) + return -ENOMEM; + phy_addr = res.start; + + /* Get mdio node */ + mdio_node = ofnode_get_parent(phandle.node); + + if (ofnode_read_resource(mdio_node, 0, &res)) + return -ENOMEM; + faddr = cpu_to_fdt32(res.start); + + addr_base = ofnode_translate_address(mdio_node, &faddr); + addr_size = res.end - res.start; + + /* If the bus is new then create a new bus */ + if (!get_mdiobus(addr_base, addr_size)) + priv->bus[miim_count] = + serval_mdiobus_init(addr_base, addr_size); + + /* Connect mdio bus with the port */ + bus = get_mdiobus(addr_base, addr_size); + + /* Get serdes info */ + ret = ofnode_parse_phandle_with_args(node, "phys", NULL, + 3, 0, &phandle); + if (ret) + return -ENOMEM; + + add_port_entry(priv, i, phy_addr, bus, phandle.args[1], + phandle.args[2]); + } + + for (i = 0; i < MAX_PORT; i++) { + if (!priv->ports[i].bus) + continue; + + phy = phy_connect(priv->ports[i].bus, + priv->ports[i].phy_addr, dev, + PHY_INTERFACE_MODE_NONE); + if (phy) + board_phy_config(phy); + } + + return 0; +} + +static int serval_remove(struct udevice *dev) +{ + struct serval_private *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < SERVAL_MIIM_BUS_COUNT; i++) { + mdio_unregister(priv->bus[i]); + mdio_free(priv->bus[i]); + } + + return 0; +} + +static const struct eth_ops serval_ops = { + .start = serval_start, + .stop = serval_stop, + .send = serval_send, + .recv = serval_recv, + .write_hwaddr = serval_write_hwaddr, +}; + +static const struct udevice_id mscc_serval_ids[] = { + {.compatible = "mscc,vsc7418-switch"}, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(serval) = { + .name = "serval-switch", + .id = UCLASS_ETH, + .of_match = mscc_serval_ids, + .probe = serval_probe, + .remove = serval_remove, + .ops = &serval_ops, + .priv_auto_alloc_size = sizeof(struct serval_private), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c index bb879d8d4fe..9d539849739 100644 --- a/drivers/net/ti/davinci_emac.c +++ b/drivers/net/ti/davinci_emac.c @@ -816,55 +816,12 @@ int davinci_emac_initialize(void) phy_id |= tmp & 0x0000ffff; - switch (phy_id) { -#ifdef PHY_KSZ8873 - case PHY_KSZ8873: - sprintf(phy[i].name, "KSZ8873 @ 0x%02x", - active_phy_addr[i]); - phy[i].init = ksz8873_init_phy; - phy[i].is_phy_connected = ksz8873_is_phy_connected; - phy[i].get_link_speed = ksz8873_get_link_speed; - phy[i].auto_negotiate = ksz8873_auto_negotiate; - break; -#endif -#ifdef PHY_LXT972 - case PHY_LXT972: - sprintf(phy[i].name, "LXT972 @ 0x%02x", - active_phy_addr[i]); - phy[i].init = lxt972_init_phy; - phy[i].is_phy_connected = lxt972_is_phy_connected; - phy[i].get_link_speed = lxt972_get_link_speed; - phy[i].auto_negotiate = lxt972_auto_negotiate; - break; -#endif -#ifdef PHY_DP83848 - case PHY_DP83848: - sprintf(phy[i].name, "DP83848 @ 0x%02x", - active_phy_addr[i]); - phy[i].init = dp83848_init_phy; - phy[i].is_phy_connected = dp83848_is_phy_connected; - phy[i].get_link_speed = dp83848_get_link_speed; - phy[i].auto_negotiate = dp83848_auto_negotiate; - break; -#endif -#ifdef PHY_ET1011C - case PHY_ET1011C: - sprintf(phy[i].name, "ET1011C @ 0x%02x", - active_phy_addr[i]); - phy[i].init = gen_init_phy; - phy[i].is_phy_connected = gen_is_phy_connected; - phy[i].get_link_speed = et1011c_get_link_speed; - phy[i].auto_negotiate = gen_auto_negotiate; - break; -#endif - default: - sprintf(phy[i].name, "GENERIC @ 0x%02x", - active_phy_addr[i]); - phy[i].init = gen_init_phy; - phy[i].is_phy_connected = gen_is_phy_connected; - phy[i].get_link_speed = gen_get_link_speed; - phy[i].auto_negotiate = gen_auto_negotiate; - } + sprintf(phy[i].name, "GENERIC @ 0x%02x", + active_phy_addr[i]); + phy[i].init = gen_init_phy; + phy[i].is_phy_connected = gen_is_phy_connected; + phy[i].get_link_speed = gen_get_link_speed; + phy[i].auto_negotiate = gen_auto_negotiate; debug("Ethernet PHY: %s\n", phy[i].name); diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index 0e6c559d5ef..f01bc77a576 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -116,6 +116,9 @@ static int pinconfig_post_bind(struct udevice *dev) ofnode node; int ret; + if (!dev_of_valid(dev)) + return 0; + dev_for_each_subnode(node, dev) { if (pre_reloc_only && !ofnode_pre_reloc(node)) diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c index 9994cbafbff..88db294cf14 100644 --- a/drivers/pwm/rk_pwm.c +++ b/drivers/pwm/rk_pwm.c @@ -12,7 +12,7 @@ #include <regmap.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/pwm.h> +#include <asm/arch-rockchip/pwm.h> #include <power/regulator.h> struct rk_pwm_priv { diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c index 8d1b9faacc0..92f584fadcb 100644 --- a/drivers/ram/rockchip/dmc-rk3368.c +++ b/drivers/ram/rockchip/dmc-rk3368.c @@ -12,12 +12,12 @@ #include <regmap.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3368.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/ddr_rk3368.h> -#include <asm/arch/sdram.h> -#include <asm/arch/sdram_common.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3368.h> +#include <asm/arch-rockchip/grf_rk3368.h> +#include <asm/arch-rockchip/ddr_rk3368.h> +#include <asm/arch-rockchip/sdram.h> +#include <asm/arch-rockchip/sdram_common.h> struct dram_info { struct ram_info info; diff --git a/drivers/ram/rockchip/sdram_rk3128.c b/drivers/ram/rockchip/sdram_rk3128.c index df7b9887033..bfabc22a7d8 100644 --- a/drivers/ram/rockchip/sdram_rk3128.c +++ b/drivers/ram/rockchip/sdram_rk3128.c @@ -7,9 +7,9 @@ #include <dm.h> #include <ram.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3128.h> -#include <asm/arch/sdram_common.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3128.h> +#include <asm/arch-rockchip/sdram_common.h> struct dram_info { struct ram_info info; diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index fdd500aa472..00e52ec949e 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -15,13 +15,13 @@ #include <regmap.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3188.h> -#include <asm/arch/ddr_rk3188.h> -#include <asm/arch/grf_rk3188.h> -#include <asm/arch/pmu_rk3188.h> -#include <asm/arch/sdram.h> -#include <asm/arch/sdram_common.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3188.h> +#include <asm/arch-rockchip/ddr_rk3188.h> +#include <asm/arch-rockchip/grf_rk3188.h> +#include <asm/arch-rockchip/pmu_rk3188.h> +#include <asm/arch-rockchip/sdram.h> +#include <asm/arch-rockchip/sdram_common.h> #include <linux/err.h> struct chan_info { diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index 53835a9cd08..c596523d4ff 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -11,14 +11,14 @@ #include <regmap.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk322x.h> -#include <asm/arch/grf_rk322x.h> -#include <asm/arch/hardware.h> -#include <asm/arch/sdram_rk322x.h> -#include <asm/arch/timer.h> -#include <asm/arch/uart.h> -#include <asm/arch/sdram_common.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk322x.h> +#include <asm/arch-rockchip/grf_rk322x.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/sdram_rk322x.h> +#include <asm/arch-rockchip/timer.h> +#include <asm/arch-rockchip/uart.h> +#include <asm/arch-rockchip/sdram_common.h> #include <asm/types.h> #include <linux/err.h> diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index d1e52d84e7a..6bb025a851a 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -15,13 +15,13 @@ #include <regmap.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3288.h> -#include <asm/arch/ddr_rk3288.h> -#include <asm/arch/grf_rk3288.h> -#include <asm/arch/pmu_rk3288.h> -#include <asm/arch/sdram.h> -#include <asm/arch/sdram_common.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3288.h> +#include <asm/arch-rockchip/ddr_rk3288.h> +#include <asm/arch-rockchip/grf_rk3288.h> +#include <asm/arch-rockchip/pmu_rk3288.h> +#include <asm/arch-rockchip/sdram.h> +#include <asm/arch-rockchip/sdram_common.h> #include <linux/err.h> #include <power/regulator.h> #include <power/rk8xx_pmic.h> diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index e8b234d8665..f4e0b184470 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -7,9 +7,9 @@ #include <dm.h> #include <ram.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3328.h> -#include <asm/arch/sdram_common.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3328.h> +#include <asm/arch-rockchip/sdram_common.h> struct dram_info { struct ram_info info; diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 94dd01156a7..05ec5fc28d7 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -13,12 +13,12 @@ #include <regmap.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/sdram_common.h> -#include <asm/arch/sdram_rk3399.h> -#include <asm/arch/cru_rk3399.h> -#include <asm/arch/grf_rk3399.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/sdram_common.h> +#include <asm/arch-rockchip/sdram_rk3399.h> +#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> #include <linux/err.h> #include <time.h> diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c index af071340495..3871fc00d07 100644 --- a/drivers/reset/reset-rockchip.c +++ b/drivers/reset/reset-rockchip.c @@ -7,7 +7,7 @@ #include <dm.h> #include <reset-uclass.h> #include <linux/io.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include <dm/lists.h> /* * Each reg has 16 bits reset signal for devices diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c index 35fefd74c69..b1718f72d1b 100644 --- a/drivers/serial/serial_rockchip.c +++ b/drivers/serial/serial_rockchip.c @@ -9,7 +9,7 @@ #include <dt-structs.h> #include <ns16550.h> #include <serial.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> #if defined(CONFIG_ROCKCHIP_RK3188) struct rockchip_uart_platdata { diff --git a/drivers/sound/rockchip_sound.c b/drivers/sound/rockchip_sound.c index e7fb9fb1646..a092dbc4458 100644 --- a/drivers/sound/rockchip_sound.c +++ b/drivers/sound/rockchip_sound.c @@ -13,7 +13,7 @@ #include <i2s.h> #include <misc.h> #include <sound.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/periph.h> #include <dm/pinctrl.h> static int rockchip_sound_setup(struct udevice *dev) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index fb794adae72..2830f765877 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -133,7 +133,7 @@ config MPC8XX_SPI config MT7621_SPI bool "MediaTek MT7621 SPI driver" - depends on ARCH_MT7620 + depends on SOC_MT7628 help Enable the MT7621 SPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Ralink / MediaTek diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index 14437c0a9af..a68553b75bf 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -2,6 +2,8 @@ /* * spi driver for rockchip * + * (C) 2019 Theobroma Systems Design und Consulting GmbH + * * (C) Copyright 2015 Google, Inc * * (C) Copyright 2008-2013 Rockchip Electronics @@ -16,14 +18,19 @@ #include <spi.h> #include <linux/errno.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/periph.h> #include <dm/pinctrl.h> #include "rk_spi.h" /* Change to 1 to output registers at the start of each transaction */ #define DEBUG_RK_SPI 0 +struct rockchip_spi_params { + /* RXFIFO overruns and TXFIFO underruns stop the master clock */ + bool master_manages_fifo; +}; + struct rockchip_spi_platdata { #if CONFIG_IS_ENABLED(OF_PLATDATA) struct dtd_rockchip_rk3288_spi of_plat; @@ -40,11 +47,8 @@ struct rockchip_spi_priv { unsigned int max_freq; unsigned int mode; ulong last_transaction_us; /* Time of last transaction end */ - u8 bits_per_word; /* max 16 bits per word */ - u8 n_bytes; unsigned int speed_hz; unsigned int last_speed_hz; - unsigned int tmode; uint input_rate; }; @@ -130,8 +134,13 @@ static void spi_cs_activate(struct udevice *dev, uint cs) if (plat->deactivate_delay_us && priv->last_transaction_us) { ulong delay_us; /* The delay completed so far */ delay_us = timer_get_us() - priv->last_transaction_us; - if (delay_us < plat->deactivate_delay_us) - udelay(plat->deactivate_delay_us - delay_us); + if (delay_us < plat->deactivate_delay_us) { + ulong additional_delay_us = + plat->deactivate_delay_us - delay_us; + debug("%s: delaying by %ld us\n", + __func__, additional_delay_us); + udelay(additional_delay_us); + } } debug("activate cs%u\n", cs); @@ -263,8 +272,6 @@ static int rockchip_spi_probe(struct udevice *bus) } priv->input_rate = ret; debug("%s: rate = %u\n", __func__, priv->input_rate); - priv->bits_per_word = 8; - priv->tmode = TMOD_TR; /* Tx & Rx */ return 0; } @@ -274,28 +281,10 @@ static int rockchip_spi_claim_bus(struct udevice *dev) struct udevice *bus = dev->parent; struct rockchip_spi_priv *priv = dev_get_priv(bus); struct rockchip_spi *regs = priv->regs; - u8 spi_dfs, spi_tf; uint ctrlr0; /* Disable the SPI hardware */ - rkspi_enable_chip(regs, 0); - - switch (priv->bits_per_word) { - case 8: - priv->n_bytes = 1; - spi_dfs = DFS_8BIT; - spi_tf = HALF_WORD_OFF; - break; - case 16: - priv->n_bytes = 2; - spi_dfs = DFS_16BIT; - spi_tf = HALF_WORD_ON; - break; - default: - debug("%s: unsupported bits: %dbits\n", __func__, - priv->bits_per_word); - return -EPROTONOSUPPORT; - } + rkspi_enable_chip(regs, false); if (priv->speed_hz != priv->last_speed_hz) rkspi_set_clk(priv, priv->speed_hz); @@ -304,7 +293,7 @@ static int rockchip_spi_claim_bus(struct udevice *dev) ctrlr0 = OMOD_MASTER << OMOD_SHIFT; /* Data Frame Size */ - ctrlr0 |= spi_dfs << DFS_SHIFT; + ctrlr0 |= DFS_8BIT << DFS_SHIFT; /* set SPI mode 0..3 */ if (priv->mode & SPI_CPOL) @@ -325,7 +314,7 @@ static int rockchip_spi_claim_bus(struct udevice *dev) ctrlr0 |= FBM_MSB << FBM_SHIFT; /* Byte and Halfword Transform */ - ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT; + ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT; /* Rxd Sample Delay */ ctrlr0 |= 0 << RXDSD_SHIFT; @@ -334,7 +323,7 @@ static int rockchip_spi_claim_bus(struct udevice *dev) ctrlr0 |= FRF_SPI << FRF_SHIFT; /* Tx and Rx mode */ - ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT; + ctrlr0 |= TMOD_TR << TMOD_SHIFT; writel(ctrlr0, ®s->ctrlr0); @@ -351,6 +340,83 @@ static int rockchip_spi_release_bus(struct udevice *dev) return 0; } +static inline int rockchip_spi_16bit_reader(struct udevice *dev, + u8 **din, int *len) +{ + struct udevice *bus = dev->parent; + const struct rockchip_spi_params * const data = + (void *)dev_get_driver_data(bus); + struct rockchip_spi_priv *priv = dev_get_priv(bus); + struct rockchip_spi *regs = priv->regs; + const u32 saved_ctrlr0 = readl(®s->ctrlr0); +#if defined(DEBUG) + u32 statistics_rxlevels[33] = { }; +#endif + u32 frames = *len / 2; + u8 *in = (u8 *)(*din); + u32 max_chunk_size = SPI_FIFO_DEPTH; + + if (!frames) + return 0; + + /* + * If we know that the hardware will manage RXFIFO overruns + * (i.e. stop the SPI clock until there's space in the FIFO), + * we the allow largest possible chunk size that can be + * represented in CTRLR1. + */ + if (data && data->master_manages_fifo) + max_chunk_size = 0x10000; + + // rockchip_spi_configure(dev, mode, size) + rkspi_enable_chip(regs, false); + clrsetbits_le32(®s->ctrlr0, + TMOD_MASK << TMOD_SHIFT, + TMOD_RO << TMOD_SHIFT); + /* 16bit data frame size */ + clrsetbits_le32(®s->ctrlr0, DFS_MASK, DFS_16BIT); + + /* Update caller's context */ + const u32 bytes_to_process = 2 * frames; + *din += bytes_to_process; + *len -= bytes_to_process; + + /* Process our frames */ + while (frames) { + u32 chunk_size = min(frames, max_chunk_size); + + frames -= chunk_size; + + writew(chunk_size - 1, ®s->ctrlr1); + rkspi_enable_chip(regs, true); + + do { + u32 rx_level = readw(®s->rxflr); +#if defined(DEBUG) + statistics_rxlevels[rx_level]++; +#endif + chunk_size -= rx_level; + while (rx_level--) { + u16 val = readw(regs->rxdr); + *in++ = val & 0xff; + *in++ = val >> 8; + } + } while (chunk_size); + + rkspi_enable_chip(regs, false); + } + +#if defined(DEBUG) + debug("%s: observed rx_level during processing:\n", __func__); + for (int i = 0; i <= 32; ++i) + if (statistics_rxlevels[i]) + debug("\t%2d: %d\n", i, statistics_rxlevels[i]); +#endif + /* Restore the original transfer setup and return error-free. */ + writel(saved_ctrlr0, ®s->ctrlr0); + return 0; +} + static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { @@ -362,7 +428,7 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, const u8 *out = dout; u8 *in = din; int toread, towrite; - int ret; + int ret = 0; debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din, len, flags); @@ -373,8 +439,18 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, if (flags & SPI_XFER_BEGIN) spi_cs_activate(dev, slave_plat->cs); + /* + * To ensure fast loading of firmware images (e.g. full U-Boot + * stage, ATF, Linux kernel) from SPI flash, we optimise the + * case of read-only transfers by using the full 16bits of each + * FIFO element. + */ + if (!out) + ret = rockchip_spi_16bit_reader(dev, &in, &len); + + /* This is the original 8bit reader/writer code */ while (len > 0) { - int todo = min(len, 0xffff); + int todo = min(len, 0x10000); rkspi_enable_chip(regs, false); writel(todo - 1, ®s->ctrlr1); @@ -397,9 +473,18 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, toread--; } } - ret = rkspi_wait_till_not_busy(regs); - if (ret) - break; + + /* + * In case that there's a transmit-component, we need to wait + * until the control goes idle before we can disable the SPI + * control logic (as this will implictly flush the FIFOs). + */ + if (out) { + ret = rkspi_wait_till_not_busy(regs); + if (ret) + break; + } + len -= todo; } @@ -446,10 +531,16 @@ static const struct dm_spi_ops rockchip_spi_ops = { */ }; +const struct rockchip_spi_params rk3399_spi_params = { + .master_manages_fifo = true, +}; + static const struct udevice_id rockchip_spi_ids[] = { { .compatible = "rockchip,rk3288-spi" }, - { .compatible = "rockchip,rk3368-spi" }, - { .compatible = "rockchip,rk3399-spi" }, + { .compatible = "rockchip,rk3368-spi", + .data = (ulong)&rk3399_spi_params }, + { .compatible = "rockchip,rk3399-spi", + .data = (ulong)&rk3399_spi_params }, { } }; diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c index 93d7cfe463a..0fc6b683f2b 100644 --- a/drivers/sysreset/sysreset_rockchip.c +++ b/drivers/sysreset/sysreset_rockchip.c @@ -8,9 +8,9 @@ #include <errno.h> #include <sysreset.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3328.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3328.h> +#include <asm/arch-rockchip/hardware.h> #include <linux/err.h> int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type) diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c index 69019740b0d..54956e557a1 100644 --- a/drivers/timer/rockchip_timer.c +++ b/drivers/timer/rockchip_timer.c @@ -7,7 +7,7 @@ #include <dm.h> #include <dm/ofnode.h> #include <mapmem.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/timer.h> #include <dt-structs.h> #include <timer.h> #include <asm/io.h> diff --git a/drivers/usb/gadget/f_rockusb.c b/drivers/usb/gadget/f_rockusb.c index e81eb164b0d..f3d24772cde 100644 --- a/drivers/usb/gadget/f_rockusb.c +++ b/drivers/usb/gadget/f_rockusb.c @@ -15,7 +15,7 @@ #include <linux/compiler.h> #include <version.h> #include <g_dnl.h> -#include <asm/arch/f_rockusb.h> +#include <asm/arch-rockchip/f_rockusb.h> static inline struct f_rockusb *func_to_rockusb(struct usb_function *f) { diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 1c2212f547b..b1188bcbf52 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -246,6 +246,11 @@ config USB_OHCI_GENERIC ---help--- Enables support for generic OHCI controller. +config USB_OHCI_DA8XX + bool "Support for da850 OHCI USB controller" + help + Enable support for the da850 USB controller. + endif # USB_OHCI_HCD config USB_UHCI_HCD diff --git a/drivers/usb/host/ohci-da8xx.c b/drivers/usb/host/ohci-da8xx.c index 47ad3f34d5a..e8a495fde59 100644 --- a/drivers/usb/host/ohci-da8xx.c +++ b/drivers/usb/host/ohci-da8xx.c @@ -4,9 +4,54 @@ */ #include <common.h> - +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/ofnode.h> +#include <generic-phy.h> +#include <reset.h> +#include "ohci.h" #include <asm/arch/da8xx-usb.h> +struct da8xx_ohci { + ohci_t ohci; + struct clk *clocks; /* clock list */ + struct phy phy; + int clock_count; /* number of clock in clock list */ +}; + +static int usb_phy_on(void) +{ + unsigned long timeout; + + clrsetbits_le32(&davinci_syscfg_regs->cfgchip2, + (CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | + CFGCHIP2_OTGPWRDN | CFGCHIP2_OTGMODE | + CFGCHIP2_REFFREQ | CFGCHIP2_USB1PHYCLKMUX), + (CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | + CFGCHIP2_PHY_PLLON | CFGCHIP2_REFFREQ_24MHZ | + CFGCHIP2_USB2PHYCLKMUX | CFGCHIP2_USB1SUSPENDM)); + + /* wait until the usb phy pll locks */ + timeout = get_timer(0); + while (get_timer(timeout) < 10) { + if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD) + return 1; + } + + /* USB phy was not turned on */ + return 0; +} + +static void usb_phy_off(void) +{ + /* Power down the on-chip PHY. */ + clrsetbits_le32(&davinci_syscfg_regs->cfgchip2, + CFGCHIP2_PHY_PLLON | CFGCHIP2_USB1SUSPENDM, + CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | + CFGCHIP2_RESET); +} + int usb_cpu_init(void) { /* enable psc for usb2.0 */ @@ -37,3 +82,94 @@ int usb_cpu_init_fail(void) { return usb_cpu_stop(); } + +#if CONFIG_IS_ENABLED(DM_USB) +static int ohci_da8xx_probe(struct udevice *dev) +{ + struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev); + struct da8xx_ohci *priv = dev_get_priv(dev); + int i, err, ret, clock_nb; + + err = 0; + priv->clock_count = 0; + clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells"); + if (clock_nb > 0) { + priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk), + GFP_KERNEL); + if (!priv->clocks) + return -ENOMEM; + + for (i = 0; i < clock_nb; i++) { + err = clk_get_by_index(dev, i, &priv->clocks[i]); + if (err < 0) + break; + + err = clk_enable(&priv->clocks[i]); + if (err) { + dev_err(dev, "failed to enable clock %d\n", i); + clk_free(&priv->clocks[i]); + goto clk_err; + } + priv->clock_count++; + } + } else if (clock_nb != -ENOENT) { + dev_err(dev, "failed to get clock phandle(%d)\n", clock_nb); + return clock_nb; + } + + err = usb_cpu_init(); + + if (err) + goto clk_err; + + err = ohci_register(dev, regs); + if (err) + goto phy_err; + + return 0; + +phy_err: + ret = usb_cpu_stop(); + if (ret) + dev_err(dev, "failed to shutdown usb phy\n"); + +clk_err: + ret = clk_release_all(priv->clocks, priv->clock_count); + if (ret) + dev_err(dev, "failed to disable all clocks\n"); + + return err; +} + +static int ohci_da8xx_remove(struct udevice *dev) +{ + struct da8xx_ohci *priv = dev_get_priv(dev); + int ret; + + ret = ohci_deregister(dev); + if (ret) + return ret; + + ret = usb_cpu_stop(); + if (ret) + return ret; + + return clk_release_all(priv->clocks, priv->clock_count); +} + +static const struct udevice_id da8xx_ohci_ids[] = { + { .compatible = "ti,da830-ohci" }, + { } +}; + +U_BOOT_DRIVER(ohci_generic) = { + .name = "ohci-da8xx", + .id = UCLASS_USB, + .of_match = da8xx_ohci_ids, + .probe = ohci_da8xx_probe, + .remove = ohci_da8xx_remove, + .ops = &ohci_usb_ops, + .priv_auto_alloc_size = sizeof(struct da8xx_ohci), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; +#endif diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 3b6f889f7b7..2b0df88f49e 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1545,10 +1545,8 @@ static int submit_common_msg(ohci_t *ohci, struct usb_device *dev, return -1; } -#if 0 mdelay(10); /* ohci_dump_status(ohci); */ -#endif timeout = USB_TIMEOUT_MS(pipe); diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c index 2ee0f23b7ed..1f2805270aa 100644 --- a/drivers/usb/musb/musb_hcd.c +++ b/drivers/usb/musb/musb_hcd.c @@ -327,9 +327,7 @@ static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer) csr = readw(&musbr->txcsr); csr |= MUSB_CSR0_TXPKTRDY; -#if !defined(CONFIG_SOC_DM365) csr |= MUSB_CSR0_H_DIS_PING; -#endif writew(csr, &musbr->txcsr); result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); if (result < 0) @@ -352,9 +350,7 @@ static int ctrlreq_out_status_phase(struct usb_device *dev) /* Set the StatusPkt bit */ csr = readw(&musbr->txcsr); csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT); -#if !defined(CONFIG_SOC_DM365) csr |= MUSB_CSR0_H_DIS_PING; -#endif writew(csr, &musbr->txcsr); /* Wait until TXPKTRDY bit is cleared */ @@ -372,9 +368,7 @@ static int ctrlreq_in_status_phase(struct usb_device *dev) /* Set the StatusPkt bit and ReqPkt bit */ csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT; -#if !defined(CONFIG_SOC_DM365) csr |= MUSB_CSR0_H_DIS_PING; -#endif writew(csr, &musbr->txcsr); result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT); diff --git a/drivers/video/rockchip/rk3288_hdmi.c b/drivers/video/rockchip/rk3288_hdmi.c index eb3692c3871..315d3adf275 100644 --- a/drivers/video/rockchip/rk3288_hdmi.c +++ b/drivers/video/rockchip/rk3288_hdmi.c @@ -13,9 +13,9 @@ #include <syscon.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> -#include <asm/arch/grf_rk3288.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rk3288.h> #include <power/regulator.h> #include "rk_hdmi.h" diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c index d268b465148..7c4a4cc53b0 100644 --- a/drivers/video/rockchip/rk3288_mipi.c +++ b/drivers/video/rockchip/rk3288_mipi.c @@ -14,14 +14,14 @@ #include "rk_mipi.h" #include <syscon.h> #include <asm/gpio.h> -#include <asm/hardware.h> #include <asm/io.h> #include <dm/uclass-internal.h> #include <linux/kernel.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3288.h> -#include <asm/arch/grf_rk3288.h> -#include <asm/arch/rockchip_mipi_dsi.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3288.h> +#include <asm/arch-rockchip/grf_rk3288.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/rockchip_mipi_dsi.h> #define MHz 1000000 diff --git a/drivers/video/rockchip/rk3288_vop.c b/drivers/video/rockchip/rk3288_vop.c index 7e953a628c1..0f91dab1f25 100644 --- a/drivers/video/rockchip/rk3288_vop.c +++ b/drivers/video/rockchip/rk3288_vop.c @@ -11,10 +11,10 @@ #include <regmap.h> #include <syscon.h> #include <video.h> -#include <asm/hardware.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3288.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3288.h> +#include <asm/arch-rockchip/hardware.h> #include "rk_vop.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/video/rockchip/rk3399_hdmi.c b/drivers/video/rockchip/rk3399_hdmi.c index b75efe6fc32..a62be983275 100644 --- a/drivers/video/rockchip/rk3399_hdmi.c +++ b/drivers/video/rockchip/rk3399_hdmi.c @@ -13,9 +13,9 @@ #include <syscon.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> -#include <asm/arch/grf_rk3399.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rk3399.h> #include <power/regulator.h> #include "rk_hdmi.h" diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c index bb9007bf363..a93b73400be 100644 --- a/drivers/video/rockchip/rk3399_mipi.c +++ b/drivers/video/rockchip/rk3399_mipi.c @@ -14,14 +14,14 @@ #include "rk_mipi.h" #include <syscon.h> #include <asm/gpio.h> -#include <asm/hardware.h> #include <asm/io.h> #include <dm/uclass-internal.h> #include <linux/kernel.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3399.h> -#include <asm/arch/grf_rk3399.h> -#include <asm/arch/rockchip_mipi_dsi.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/rockchip_mipi_dsi.h> /* Select mipi dsi source, big or little vop */ static int rk_mipi_dsi_source_select(struct udevice *dev) diff --git a/drivers/video/rockchip/rk3399_vop.c b/drivers/video/rockchip/rk3399_vop.c index 7a02221ae0b..81c122d7a9e 100644 --- a/drivers/video/rockchip/rk3399_vop.c +++ b/drivers/video/rockchip/rk3399_vop.c @@ -10,7 +10,7 @@ #include <dm.h> #include <regmap.h> #include <video.h> -#include <asm/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include <asm/io.h> #include "rk_vop.h" diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index e0741076324..4330725a251 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -14,9 +14,9 @@ #include <syscon.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/edp_rk3288.h> -#include <asm/arch/grf_rk3288.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/edp_rk3288.h> +#include <asm/arch-rockchip/grf_rk3288.h> #include <dt-bindings/clock/rk3288-cru.h> #define MAX_CR_LOOP 5 diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index 13d07ee3048..51931ceefae 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -14,10 +14,9 @@ #include <regmap.h> #include <syscon.h> #include <asm/gpio.h> -#include <asm/hardware.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> #include "rk_hdmi.h" #include "rk_vop.h" /* for rk_vop_probe_regulators */ diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c index f0a528c0d6d..cf5c0439b1a 100644 --- a/drivers/video/rockchip/rk_lvds.c +++ b/drivers/video/rockchip/rk_lvds.c @@ -12,9 +12,9 @@ #include <syscon.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/lvds_rk3288.h> -#include <asm/arch/grf_rk3288.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/lvds_rk3288.h> +#include <asm/arch-rockchip/grf_rk3288.h> #include <dt-bindings/clock/rk3288-cru.h> #include <dt-bindings/video/rk3288.h> diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index 4f1a0f3a5f7..bcd039b7bc6 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -14,14 +14,13 @@ #include "rk_mipi.h" #include <syscon.h> #include <asm/gpio.h> -#include <asm/hardware.h> #include <asm/io.h> #include <dm/uclass-internal.h> #include <linux/kernel.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3399.h> -#include <asm/arch/grf_rk3399.h> -#include <asm/arch/rockchip_mipi_dsi.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/rockchip_mipi_dsi.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index faf4f24db04..b56c3f336c9 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -13,11 +13,10 @@ #include <syscon.h> #include <video.h> #include <asm/gpio.h> -#include <asm/hardware.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/edp_rk3288.h> -#include <asm/arch/vop_rk3288.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/edp_rk3288.h> +#include <asm/arch-rockchip/vop_rk3288.h> #include <dm/device-internal.h> #include <dm/uclass-internal.h> #include <power/regulator.h> diff --git a/drivers/video/rockchip/rk_vop.h b/drivers/video/rockchip/rk_vop.h index 828974d394f..8fa2f389390 100644 --- a/drivers/video/rockchip/rk_vop.h +++ b/drivers/video/rockchip/rk_vop.h @@ -6,7 +6,7 @@ #ifndef __RK_VOP_H__ #define __RK_VOP_H__ -#include <asm/arch/vop_rk3288.h> +#include <asm/arch-rockchip/vop_rk3288.h> struct rk_vop_priv { void *grf; diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 3bce0aa0b87..f909d40f455 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -55,7 +55,7 @@ config WDT help Enable driver model for watchdog timer. At the moment the API is very simple and only supports four operations: - start, restart, stop and reset (expire immediately). + start, stop, reset and expire_now (expire immediately). What exactly happens when the timer expires is up to a particular device/driver. @@ -143,7 +143,7 @@ config WDT_AT91 config WDT_MT7621 bool "MediaTek MT7621 watchdog timer support" - depends on WDT && ARCH_MT7620 + depends on WDT && SOC_MT7628 help Select this to enable Ralink / Mediatek watchdog timer, which can be found on some MediaTek chips. diff --git a/fs/btrfs/Kconfig b/fs/btrfs/Kconfig index 22909d9fccc..f302b1fbef5 100644 --- a/fs/btrfs/Kconfig +++ b/fs/btrfs/Kconfig @@ -2,6 +2,7 @@ config FS_BTRFS bool "Enable BTRFS filesystem support" select CRC32C select LZO + select ZSTD select RBTREE help This provides a single-device read-only BTRFS support. BTRFS is a diff --git a/fs/btrfs/btrfs.c b/fs/btrfs/btrfs.c index 6f35854823e..cb7e1827422 100644 --- a/fs/btrfs/btrfs.c +++ b/fs/btrfs/btrfs.c @@ -119,17 +119,17 @@ int btrfs_ls(const char *path) if (inr == -1ULL) { printf("Cannot lookup path %s\n", path); - return 1; + return -1; } if (type != BTRFS_FT_DIR) { printf("Not a directory: %s\n", path); - return 1; + return -1; } if (btrfs_readdir(&root, inr, readdir_callback)) { printf("An error occured while listing directory %s\n", path); - return 1; + return -1; } return 0; @@ -158,12 +158,12 @@ int btrfs_size(const char *file, loff_t *size) if (inr == -1ULL) { printf("Cannot lookup file %s\n", file); - return 1; + return -1; } if (type != BTRFS_FT_REG_FILE) { printf("Not a regular file: %s\n", file); - return 1; + return -1; } *size = inode.size; @@ -183,12 +183,12 @@ int btrfs_read(const char *file, void *buf, loff_t offset, loff_t len, if (inr == -1ULL) { printf("Cannot lookup file %s\n", file); - return 1; + return -1; } if (type != BTRFS_FT_REG_FILE) { printf("Not a regular file: %s\n", file); - return 1; + return -1; } if (!len) @@ -200,7 +200,7 @@ int btrfs_read(const char *file, void *buf, loff_t offset, loff_t len, rd = btrfs_file_read(&root, inr, offset, len, buf); if (rd == -1ULL) { printf("An error occured while reading file %s\n", file); - return 1; + return -1; } *actread = rd; diff --git a/fs/btrfs/btrfs_tree.h b/fs/btrfs/btrfs_tree.h index f90fbb29514..aa0f3d6c86d 100644 --- a/fs/btrfs/btrfs_tree.h +++ b/fs/btrfs/btrfs_tree.h @@ -647,8 +647,9 @@ enum btrfs_compression_type { BTRFS_COMPRESS_NONE = 0, BTRFS_COMPRESS_ZLIB = 1, BTRFS_COMPRESS_LZO = 2, - BTRFS_COMPRESS_TYPES = 2, - BTRFS_COMPRESS_LAST = 3, + BTRFS_COMPRESS_ZSTD = 3, + BTRFS_COMPRESS_TYPES = 3, + BTRFS_COMPRESS_LAST = 4, }; struct btrfs_file_extent_item { diff --git a/fs/btrfs/compression.c b/fs/btrfs/compression.c index e5601b8f2bf..346875d45a1 100644 --- a/fs/btrfs/compression.c +++ b/fs/btrfs/compression.c @@ -6,7 +6,9 @@ */ #include "btrfs.h" +#include <malloc.h> #include <linux/lzo.h> +#include <linux/zstd.h> #include <u-boot/zlib.h> #include <asm/unaligned.h> @@ -108,6 +110,61 @@ static u32 decompress_zlib(const u8 *_cbuf, u32 clen, u8 *dbuf, u32 dlen) return res; } +#define ZSTD_BTRFS_MAX_WINDOWLOG 17 +#define ZSTD_BTRFS_MAX_INPUT (1 << ZSTD_BTRFS_MAX_WINDOWLOG) + +static u32 decompress_zstd(const u8 *cbuf, u32 clen, u8 *dbuf, u32 dlen) +{ + ZSTD_DStream *dstream; + ZSTD_inBuffer in_buf; + ZSTD_outBuffer out_buf; + void *workspace; + size_t wsize; + u32 res = -1; + + wsize = ZSTD_DStreamWorkspaceBound(ZSTD_BTRFS_MAX_INPUT); + workspace = malloc(wsize); + if (!workspace) { + debug("%s: cannot allocate workspace of size %zu\n", __func__, + wsize); + return -1; + } + + dstream = ZSTD_initDStream(ZSTD_BTRFS_MAX_INPUT, workspace, wsize); + if (!dstream) { + printf("%s: ZSTD_initDStream failed\n", __func__); + goto err_free; + } + + in_buf.src = cbuf; + in_buf.pos = 0; + in_buf.size = clen; + + out_buf.dst = dbuf; + out_buf.pos = 0; + out_buf.size = dlen; + + while (1) { + size_t ret; + + ret = ZSTD_decompressStream(dstream, &out_buf, &in_buf); + if (ZSTD_isError(ret)) { + printf("%s: ZSTD_decompressStream error %d\n", __func__, + ZSTD_getErrorCode(ret)); + goto err_free; + } + + if (in_buf.pos >= clen || !ret) + break; + } + + res = out_buf.pos; + +err_free: + free(workspace); + return res; +} + u32 btrfs_decompress(u8 type, const char *c, u32 clen, char *d, u32 dlen) { u32 res; @@ -126,6 +183,8 @@ u32 btrfs_decompress(u8 type, const char *c, u32 clen, char *d, u32 dlen) return decompress_zlib(cbuf, clen, dbuf, dlen); case BTRFS_COMPRESS_LZO: return decompress_lzo(cbuf, clen, dbuf, dlen); + case BTRFS_COMPRESS_ZSTD: + return decompress_zstd(cbuf, clen, dbuf, dlen); default: printf("%s: Unsupported compression in extent: %i\n", __func__, type); diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c index 7aaf8f9b0d8..2dc4a6fcd7a 100644 --- a/fs/btrfs/super.c +++ b/fs/btrfs/super.c @@ -198,17 +198,16 @@ int btrfs_read_superblock(void) break; if (btrfs_check_super_csum(raw_sb)) { - printf("%s: invalid checksum at superblock mirror %i\n", - __func__, i); + debug("%s: invalid checksum at superblock mirror %i\n", + __func__, i); continue; } btrfs_super_block_to_cpu(sb); if (sb->magic != BTRFS_MAGIC) { - printf("%s: invalid BTRFS magic 0x%016llX at " - "superblock mirror %i\n", __func__, sb->magic, - i); + debug("%s: invalid BTRFS magic 0x%016llX at " + "superblock mirror %i\n", __func__, sb->magic, i); } else if (sb->bytenr != superblock_offsets[i]) { printf("%s: invalid bytenr 0x%016llX (expected " "0x%016llX) at superblock mirror %i\n", @@ -224,7 +223,7 @@ int btrfs_read_superblock(void) } if (!btrfs_info.sb.generation) { - printf("%s: No valid BTRFS superblock found!\n", __func__); + debug("%s: No valid BTRFS superblock found!\n", __func__); return -1; } diff --git a/include/cache.h b/include/cache.h new file mode 100644 index 00000000000..c6334ca27fb --- /dev/null +++ b/include/cache.h @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#ifndef __CACHE_H +#define __CACHE_H + +/* + * Structure for the cache controller + */ +struct cache_info { + phys_addr_t base; /* Base physical address of cache device. */ +}; + +struct cache_ops { + /** + * get_info() - Get basic cache info + * + * @dev: Device to check (UCLASS_CACHE) + * @info: Place to put info + * @return 0 if OK, -ve on error + */ + int (*get_info)(struct udevice *dev, struct cache_info *info); +}; + +#define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops) + +/** + * cache_get_info() - Get information about a cache controller + * + * @dev: Device to check (UCLASS_CACHE) + * @info: Returns cache info + * @return 0 if OK, -ve on error + */ +int cache_get_info(struct udevice *dev, struct cache_info *info); + +#endif diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index 57edeee941e..22d1e41bc8d 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -21,8 +21,6 @@ #define CONFIG_LOADCMD "fatload" #define CONFIG_RFSPART "2" -#define CONFIG_SUPPORT_EMMC_BOOT - #include "mx6_common.h" #include <linux/sizes.h> diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index c14b010550f..2c651aab178 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -63,8 +63,6 @@ #define CONFIG_NET_RETRY_COUNT 10 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ -#define CONFIG_SUPPORT_EMMC_BOOT - /* USB xHCI HOST */ #define CONFIG_USB_XHCI_OMAP diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 1d296ba51a0..9c8c8979f04 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -18,9 +18,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -/* SD/MMC support */ -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - /* Environment in eMMC, before config block at the end of 1st "boot sector" */ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ CONFIG_TDX_CFG_BLOCK_OFFSET) diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 91054d8c05b..9d9e16e5d96 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -46,8 +46,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - /* * SATA Configs */ diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 06b02ce90a9..dd321c4748d 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -14,9 +14,6 @@ #include "exynos5250-common.h" #include <configs/exynos5-common.h> -/* SD/MMC configuration */ -#define CONFIG_SUPPORT_EMMC_BOOT - /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index 84c801d10a9..51af93a32f8 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -31,11 +31,6 @@ /*#define CONFIG_MACH_TYPE 3589*/ #define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/ -/* MMC/SD IP block */ -#if defined(CONFIG_EMMC_BOOT) - #define CONFIG_SUPPORT_EMMC_BOOT -#endif /* CONFIG_EMMC_BOOT */ - /* * When we have NAND flash we expect to be making use of mtdparts, * both for ease of use in U-Boot and for passing information on to diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 26d1a97891d..4c93fc6cbea 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -153,7 +153,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #endif /* USB Configs */ diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index a00329db299..4198ff05117 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -26,10 +26,6 @@ */ #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE -#ifdef CONFIG_CMD_MMC -#define CONFIG_SUPPORT_EMMC_BOOT -#endif - /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h index cda1b5528ff..2387f864e32 100644 --- a/include/configs/cm_t54.h +++ b/include/configs/cm_t54.h @@ -41,7 +41,6 @@ /* Enhance our eMMC support / experience. */ #define CONFIG_HSMMC2_8BIT -#define CONFIG_SUPPORT_EMMC_BOOT /* SATA Boot related defines */ #define CONFIG_SPL_SATA_BOOT_DEVICE 0 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 129a42466d4..b540b3e0749 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -44,8 +44,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - /* Network */ #define CONFIG_FEC_MXC #define IMX_FEC_BASE ENET_BASE_ADDR diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 5a4b9801cb7..7dfc92c085b 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -35,8 +35,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 1 #elif CONFIG_TARGET_COLIBRI_IMX7_EMMC #define CONFIG_SYS_FSL_USDHC_NUM 2 - -#define CONFIG_SUPPORT_EMMC_BOOT #endif #undef CONFIG_BOOTM_PLAN9 diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 41ff6676e06..ccdac0abece 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -267,6 +267,14 @@ #define CONFIG_ENV_SIZE (16 << 10) #endif +/* USB Configs */ +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x01E25000 +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "da850evm" + #ifndef CONFIG_DIRECT_NOR_BOOT /* defines for SPL */ #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ diff --git a/include/configs/display5.h b/include/configs/display5.h index 8ab47abfa85..8829cbad913 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -83,7 +83,6 @@ #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SUPPORT_EMMC_BOOT /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index f6be6595fe3..aec70ee7182 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -96,8 +96,6 @@ /* SPI SPL */ #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 -#define CONFIG_SUPPORT_EMMC_BOOT - /* USB xHCI HOST */ #define CONFIG_USB_XHCI_OMAP diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index cf021083ae2..7155ebac5c2 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -31,13 +31,6 @@ * it has to be done after each HCD reset */ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET -/* Support all possible USB ethernet dongles */ - -/* Extra Commands */ -/* Enable that for switching of boot partitions */ -/* Disabled by default as some sub-commands can brick eMMC */ -/*#define CONFIG_SUPPORT_EMMC_BOOT */ - /* BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE diff --git a/include/configs/edison.h b/include/configs/edison.h index a6155ba5a8b..218b50a1d9b 100644 --- a/include/configs/edison.h +++ b/include/configs/edison.h @@ -34,7 +34,6 @@ #define CONFIG_ENV_SIZE (64 * 1024) #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) #define CONFIG_ENV_OFFSET_REDUND (6 * 1024 * 1024) -#define CONFIG_SUPPORT_EMMC_BOOT /* RTC */ #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 858bed012c6..8bc7a3ad2e1 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -76,7 +76,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 #define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */ #define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) /* MarSBoard */ #define CONFIG_FDTFILE "imx6q-marsboard.dtb" diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index db1fc934bbb..397bbf6d9d3 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -44,7 +44,6 @@ /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 -#define CONFIG_SUPPORT_EMMC_BOOT /* specific .lds file */ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 196f114c60e..0481ed06a91 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -19,9 +19,6 @@ #define CONFIG_MXC_UART_BASE UART3_BASE #define CONSOLE_DEV "ttymxc2" -#define CONFIG_SUPPORT_EMMC_BOOT - - #include "mx6_common.h" #include <linux/sizes.h> diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 93608e5aec4..02ceb4c8fc8 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -81,9 +81,6 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -/* eMMC Configs */ -#define CONFIG_SUPPORT_EMMC_BOOT - /* * SATA Configs */ diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index 030dbedce81..7605e145c2f 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -51,7 +51,6 @@ /* MMC */ #define CONFIG_SYS_MMC_ENV_DEV 2 -#define CONFIG_SUPPORT_EMMC_BOOT /* Ethernet */ #define CONFIG_FEC_MXC_PHYADDR 1 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index aaecf6f0535..7759bbf2645 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -224,7 +224,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_MXC_GPIO diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 18ea5a8fb6d..40163c8d504 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -53,7 +53,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index a97ccb50b2f..975f32474c4 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -24,7 +24,6 @@ /* MMC Configs */ #ifdef CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT #endif #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index e449364ad48..5f67893f312 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -42,7 +42,6 @@ /* MMC */ #define MMC_SUPPORTS_TUNING -#define CONFIG_SUPPORT_EMMC_BOOT /* DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 555942a2c2a..ec1537541ae 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -16,8 +16,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - #include "mx6sabre_common.h" /* Falcon Mode */ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 39d29de7446..77856a8f3a4 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -38,7 +38,6 @@ #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #ifdef CONFIG_IMX_BOOTAUX diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index b8dcaa10361..5bd63929735 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -28,7 +28,6 @@ #define IOMUXC_BASE_ADDR IOMUXC1_RBASE #define CONFIG_FSL_USDHC -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #define CONFIG_SYS_FSL_USDHC_NUM 1 diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 66bd288040c..0d8f945349d 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -39,7 +39,6 @@ /* Enhance our eMMC support / experience. */ #define CONFIG_HSMMC2_8BIT -#define CONFIG_SUPPORT_EMMC_BOOT /* Required support for the TCA642X GPIO we have on the uEVM */ #define CONFIG_TCA642X diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 70cf4665df3..e0c76ff43da 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -33,9 +33,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* MMC */ -#define CONFIG_SUPPORT_EMMC_BOOT - /* USB */ #ifdef CONFIG_USB_EHCI_MX6 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 050f69801b4..cd051bf263f 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -41,7 +41,6 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT /* USB Configs */ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 04d316f1132..365a5984e4d 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -58,7 +58,6 @@ "bootmenu_1=Boot using PICO-Pi baseboard=" \ "setenv fdtfile imx7d-pico-pi.dtb\0" \ -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 6c02446a65a..f5d09d18e5e 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_RK3036_COMMON_H #define __CONFIG_RK3036_COMMON_H -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CONFIG_SYS_MALLOC_LEN (32 << 20) diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 4f6f4af957d..1d417028467 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -8,7 +8,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 22eb064fadc..3a96748f6b7 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_RK322X_COMMON_H #define __CONFIG_RK322X_COMMON_H -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 3a1cbf28af8..7c79ed61382 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_RK3288_COMMON_H #define __CONFIG_RK3288_COMMON_H -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index cf51f25bf34..bb2e96ba05d 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -10,7 +10,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include <linux/sizes.h> #define CONFIG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 952ea9fdca4..6f61f015387 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_RV1108_COMMON_H #define __CONFIG_RV1108_COMMON_H -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CONFIG_SYS_MALLOC_LEN (32 << 20) diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index 3069373236b..fd6c97a0c61 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -77,7 +77,6 @@ /*MMC SD*/ #define CONFIG_SYS_MMC_MAX_DEVICE 3 -#define CONFIG_SUPPORT_EMMC_BOOT /*****************************************************************************/ #ifdef CONFIG_DISTRO_DEFAULTS diff --git a/include/configs/taurus.h b/include/configs/taurus.h index c3353d74a9e..45a4a800c58 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -41,6 +41,7 @@ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG + #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* general purpose I/O */ @@ -48,12 +49,9 @@ #define CONFIG_AT91_GPIO #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ -/* serial console */ -#define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS - /* * SDRAM: 1 bank, min 32, max 128 MB * Initialized before u-boot gets started. @@ -106,7 +104,6 @@ /* SPI EEPROM */ #define TAURUS_SPI_MASK (1 << 4) -#define TAURUS_SPI_CS_PIN AT91_PIN_PA3 #if defined(CONFIG_SPL_BUILD) /* SPL related */ @@ -120,8 +117,57 @@ #define CONFIG_ENV_OFFSET 0x100000 #define CONFIG_ENV_OFFSET_REDUND 0x180000 #define CONFIG_ENV_SIZE (SZ_128K) /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" +#ifndef CONFIG_SPL_BUILD +#if defined(CONFIG_BOARD_AXM) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ + "${gatewayip}:${netmask}:${hostname}:${netdev}::off\0" \ + "addtest=setenv bootargs ${bootargs} loglevel=4 test\0" \ + "boot_file=setenv bootfile /${project_dir}/kernel/uImage\0" \ + "boot_retries=0\0" \ + "ethact=macb0\0" \ + "flash_nfs=run nand_kernel;run nfsargs;run addip;" \ + "upgrade_available;bootm ${kernel_ram};reset\0" \ + "flash_self=run nand_kernel;run setbootargs;upgrade_available;" \ + "bootm ${kernel_ram};reset\0" \ + "flash_self_test=run nand_kernel;run setbootargs addtest;" \ + "upgrade_available;bootm ${kernel_ram};reset\0" \ + "hostname=systemone\0" \ + "kernel_Off=0x00200000\0" \ + "kernel_Off_fallback=0x03800000\0" \ + "kernel_ram=0x21500000\0" \ + "kernel_size=0x00400000\0" \ + "kernel_size_fallback=0x00400000\0" \ + "loads_echo=1\0" \ + "nand_kernel=nand read.e ${kernel_ram} ${kernel_Off} " \ + "${kernel_size}\0" \ + "net_nfs=run boot_file;tftp ${kernel_ram} ${bootfile};" \ + "run nfsargs;run addip;upgrade_available;" \ + "bootm ${kernel_ram};reset\0" \ + "netdev=eth0\0" \ + "nfsargs=run root_path;setenv bootargs ${bootargs} root=/dev/nfs " \ + "rw nfsroot=${serverip}:${rootpath} " \ + "at91sam9_wdt.wdt_timeout=16\0" \ + "partitionset_active=A\0" \ + "preboot=echo;echo Type 'run flash_self' to use kernel and root " \ + "filesystem on memory;echo Type 'run flash_nfs' to use " \ + "kernel from memory and root filesystem over NFS;echo Type " \ + "'run net_nfs' to get Kernel over TFTP and mount root " \ + "filesystem over NFS;echo\0" \ + "project_dir=systemone\0" \ + "root_path=setenv rootpath /home/projects/${project_dir}/rootfs\0" \ + "rootfs=/dev/mtdblock5\0" \ + "rootfs_fallback=/dev/mtdblock7\0" \ + "setbootargs=setenv bootargs ${bootargs} console=ttyMTD,mtdoops " \ + "root=${rootfs} rootfstype=jffs2 panic=7 " \ + "at91sam9_wdt.wdt_timeout=16\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "upgrade_available=0\0" +#endif +#endif /* #ifndef CONFIG_SPL_BUILD */ /* * Size of malloc() pool */ diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 5a148873c78..018f54428bc 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -18,31 +18,6 @@ */ #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ -/* - * Commands configuration - */ - -/* I2C support */ -#define CONFIG_DM_I2C -#define CONFIG_I2C_MUX -#define CONFIG_I2C_MUX_PCA954x -#define CONFIG_SPL_I2C_MUX -#define CONFIG_SYS_I2C_MVTWSI - -/* - * SDIO/MMC Card Configuration - */ -#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE - -/* - * SATA/SCSI/AHCI configuration - */ -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) - /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI @@ -114,9 +89,16 @@ #define BOOT_TARGET_DEVICES_USB(func) #endif +#ifdef CONFIG_SCSI +#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) +#else +#define BOOT_TARGET_DEVICES_SCSI(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_USB(func) \ + BOOT_TARGET_DEVICES_SCSI(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 31a9c59ed5b..bec7b68794c 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -94,9 +94,6 @@ #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -/* SD/MMC */ -#define CONFIG_SUPPORT_EMMC_BOOT - /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) diff --git a/include/configs/vinco.h b/include/configs/vinco.h index ec22a30cda1..eebb3f7ca78 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -43,7 +43,6 @@ /* MMC */ #ifdef CONFIG_CMD_MMC -#define CONFIG_SUPPORT_EMMC_BOOT #define CONFIG_GENERIC_ATMEL_MCI #define ATMEL_BASE_MMCI 0xfc000000 #define CONFIG_SYS_MMC_CLK_OD 500000 diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index d3cbdc6f2e4..fd98c1417e7 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -95,7 +95,6 @@ #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #ifdef CONFIG_ENV_IS_IN_MMC -#define CONFIG_SUPPORT_EMMC_BOOT #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC4 eMMC */ /* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */ #define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */ diff --git a/include/configs/warp.h b/include/configs/warp.h index 9aa8a48d3d8..5345f5314d6 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -23,7 +23,6 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE -#define CONFIG_SUPPORT_EMMC_BOOT /* Watchdog */ #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 /* 30s */ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 37649cf2c5f..0ef8e359480 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -29,7 +29,6 @@ /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 37a9ae90e5c..684faaee2e8 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -47,10 +47,6 @@ #define CONFIG_BOOTP_BOOTFILESIZE #define CONFIG_BOOTP_MAY_FAIL -#if defined(CONFIG_MMC_SDHCI_ZYNQ) -# define CONFIG_SUPPORT_EMMC_BOOT -#endif - #ifdef CONFIG_NAND_ARASAN # define CONFIG_SYS_MAX_NAND_DEVICE 1 # define CONFIG_SYS_NAND_ONFI_DETECTION diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 08e0ca0c8f1..4cbf8aa5261 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -21,7 +21,6 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ /* I2C configs */ #define CONFIG_SYS_I2C diff --git a/include/configs/zc5202.h b/include/configs/zc5202.h index 40d33f7830a..77ff04754bc 100644 --- a/include/configs/zc5202.h +++ b/include/configs/zc5202.h @@ -12,8 +12,6 @@ #define CONSOLE_DEV "ttymxc1" #define CONFIG_MMCROOT "/dev/mmcblk0p2" -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - #include "el6x_common.h" /* Ethernet */ diff --git a/include/configs/zc5601.h b/include/configs/zc5601.h index b9673e2c065..e4fe7a462d2 100644 --- a/include/configs/zc5601.h +++ b/include/configs/zc5601.h @@ -13,8 +13,6 @@ #define CONSOLE_DEV "ttymxc1" #define CONFIG_MMCROOT "/dev/mmcblk0p1" -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - #include "el6x_common.h" /* Ethernet */ diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 86e59781b05..09e0ad5391b 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -34,6 +34,7 @@ enum uclass_id { UCLASS_BLK, /* Block device */ UCLASS_BOARD, /* Device information from hardware */ UCLASS_BOOTCOUNT, /* Bootcount backing store */ + UCLASS_CACHE, /* Cache controller */ UCLASS_CLK, /* Clock source, e.g. used by peripherals */ UCLASS_CPU, /* CPU, typically part of an SoC */ UCLASS_CROS_EC, /* Chrome OS EC */ diff --git a/include/dt-bindings/mscc/luton_data.h b/include/dt-bindings/mscc/luton_data.h new file mode 100644 index 00000000000..e488567729d --- /dev/null +++ b/include/dt-bindings/mscc/luton_data.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Microsemi Corporation + */ + +#ifndef _LUTON_DATA_H_ +#define _LUTON_DATA_H_ + +#define SERDES6G(x) (x) +#define SERDES6G_MAX SERDES6G(5) +#define SERDES_MAX (SERDES6G_MAX) + +/* similar with phy_interface_t */ +#define PHY_MODE_SGMII 2 +#define PHY_MODE_QSGMII 4 + +#endif diff --git a/include/dt-bindings/mscc/ocelot_data.h b/include/dt-bindings/mscc/ocelot_data.h new file mode 100644 index 00000000000..7a5a1bf36e8 --- /dev/null +++ b/include/dt-bindings/mscc/ocelot_data.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Microsemi Corporation + */ + +#ifndef _OCELOT_DATA_H_ +#define _OCELOT_DATA_H_ + +#define SERDES1G(x) (x) +#define SERDES1G_MAX SERDES1G(7) +#define SERDES6G(x) (SERDES1G_MAX + 1 + (x)) +#define SERDES6G_MAX SERDES6G(11) +#define SERDES_MAX (SERDES6G_MAX + 1) + +/* similar with phy_interface_t */ +#define PHY_MODE_SGMII 2 +#define PHY_MODE_QSGMII 4 + +#endif diff --git a/include/dt-bindings/mscc/serval_data.h b/include/dt-bindings/mscc/serval_data.h new file mode 100644 index 00000000000..b374fda05e7 --- /dev/null +++ b/include/dt-bindings/mscc/serval_data.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef _SERVAL_DATA_H_ +#define _SERVAL_DATA_H_ + +#define SERDES1G(x) (x) +#define SERDES1G_MAX SERDES1G(9) +#define SERDES6G(x) (SERDES1G_MAX + 1 + (x)) +#define SERDES6G_MAX SERDES6G(11) +#define SERDES_MAX (SERDES6G_MAX + 1) + +/* similar with phy_interface_t */ +#define PHY_MODE_SGMII 2 +#define PHY_MODE_QSGMII 4 + +#endif diff --git a/include/dt-bindings/pinctrl/k3-am65.h b/include/dt-bindings/pinctrl/k3.h index c86c9fd4ce2..a67521cdc4a 100644 --- a/include/dt-bindings/pinctrl/k3-am65.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -7,17 +7,6 @@ #ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H #define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H -/* K3 mux mode options for each pin. See TRM for options */ -#define MUX_MODE0 0 -#define MUX_MODE1 1 -#define MUX_MODE2 2 -#define MUX_MODE3 3 -#define MUX_MODE4 4 -#define MUX_MODE5 5 -#define MUX_MODE6 6 -#define MUX_MODE7 7 -#define MUX_MODE15 15 - #define PULL_DISABLE (1 << 16) #define PULL_UP (1 << 17) #define INPUT_EN (1 << 18) @@ -43,7 +32,7 @@ #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) #define PIN_INPUT_PULLDOWN (INPUT_EN) -#define AM65X_IOPAD(pa, val) (((pa) & 0x1fff)) (val) -#define AM65X_WKUP_IOPAD(pa, val) (((pa) & 0x1fff)) (val) +#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #endif diff --git a/include/efi_loader.h b/include/efi_loader.h index 39ed8a6fa59..7af3f16ef84 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -207,12 +207,17 @@ struct efi_object { * struct efi_loaded_image_obj - handle of a loaded image * * @header: EFI object header + * @exit_status: exit status passed to Exit() + * @exit_data_size: exit data size passed to Exit() + * @exit_data: exit data passed to Exit() * @exit_jmp: long jump buffer for returning form started image * @entry: entry address of the relocated image */ struct efi_loaded_image_obj { struct efi_object header; efi_status_t exit_status; + efi_uintn_t *exit_data_size; + u16 **exit_data; struct jmp_buf_data exit_jmp; EFIAPI efi_status_t (*entry)(efi_handle_t image_handle, struct efi_system_table *st); @@ -560,7 +565,7 @@ struct efi_load_option { u16 file_path_length; u16 *label; struct efi_device_path *file_path; - u8 *optional_data; + const u8 *optional_data; }; void efi_deserialize_load_option(struct efi_load_option *lo, u8 *data); diff --git a/include/efi_selftest.h b/include/efi_selftest.h index 49d3d6d0b47..dd42e49023c 100644 --- a/include/efi_selftest.h +++ b/include/efi_selftest.h @@ -16,7 +16,7 @@ #define EFI_ST_SUCCESS 0 #define EFI_ST_FAILURE 1 - +#define EFI_ST_SUCCESS_STR L"SUCCESS" /* * Prints a message. */ diff --git a/include/fs.h b/include/fs.h index 6854597700f..7601b0343bc 100644 --- a/include/fs.h +++ b/include/fs.h @@ -71,30 +71,33 @@ int fs_exists(const char *filename); */ int fs_size(const char *filename, loff_t *size); -/* - * fs_read - Read file from the partition previously set by fs_set_blk_dev() - * Note that not all filesystem types support either/both offset!=0 or len!=0. +/** + * fs_read() - read file from the partition previously set by fs_set_blk_dev() + * + * Note that not all filesystem drivers support either or both of offset != 0 + * and len != 0. * - * @filename: Name of file to read from - * @addr: The address to read into - * @offset: The offset in file to read from - * @len: The number of bytes to read. Maybe 0 to read entire file - * @actread: Returns the actual number of bytes read - * @return 0 if ok with valid *actread, -1 on error conditions + * @filename: full path of the file to read from + * @addr: address of the buffer to write to + * @offset: offset in the file from where to start reading + * @len: the number of bytes to read. Use 0 to read entire file. + * @actread: returns the actual number of bytes read + * Return: 0 if OK with valid *actread, -1 on error conditions */ int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len, loff_t *actread); -/* - * fs_write - Write file to the partition previously set by fs_set_blk_dev() - * Note that not all filesystem types support offset!=0. +/** + * fs_write() - write file to the partition previously set by fs_set_blk_dev() + * + * Note that not all filesystem drivers support offset != 0. * - * @filename: Name of file to read from - * @addr: The address to read into - * @offset: The offset in file to read from. Maybe 0 to write to start of file - * @len: The number of bytes to write - * @actwrite: Returns the actual number of bytes written - * @return 0 if ok with valid *actwrite, -1 on error conditions + * @filename: full path of the file to write to + * @addr: address of the buffer to read from + * @offset: offset in the file from where to start writing + * @len: the number of bytes to write + * @actwrite: returns the actual number of bytes written + * Return: 0 if OK with valid *actwrite, -1 on error conditions */ int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len, loff_t *actwrite); diff --git a/include/image.h b/include/image.h index 889305cbefd..54f2b58ac52 100644 --- a/include/image.h +++ b/include/image.h @@ -1072,18 +1072,18 @@ int calculate_hash(const void *data, int data_len, const char *algo, * At present we only support signing on the host, and verification on the * device */ -#if defined(CONFIG_FIT_SIGNATURE) -# ifdef USE_HOSTCC +#if defined(USE_HOSTCC) +# if defined(CONFIG_FIT_SIGNATURE) # define IMAGE_ENABLE_SIGN 1 # define IMAGE_ENABLE_VERIFY 1 -# include <openssl/evp.h> -#else +# include <openssl/evp.h> +# else # define IMAGE_ENABLE_SIGN 0 -# define IMAGE_ENABLE_VERIFY 1 +# define IMAGE_ENABLE_VERIFY 0 # endif #else # define IMAGE_ENABLE_SIGN 0 -# define IMAGE_ENABLE_VERIFY 0 +# define IMAGE_ENABLE_VERIFY CONFIG_IS_ENABLED(FIT_SIGNATURE) #endif #ifdef USE_HOSTCC diff --git a/include/linux/xxhash.h b/include/linux/xxhash.h new file mode 100644 index 00000000000..85feb67fbdf --- /dev/null +++ b/include/linux/xxhash.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause) */ +/* + * xxHash - Extremely Fast Hash algorithm + * Copyright (C) 2012-2016, Yann Collet. + * + * You can contact the author at: + * - xxHash homepage: http://cyan4973.github.io/xxHash/ + * - xxHash source repository: https://github.com/Cyan4973/xxHash + */ + +/* + * Notice extracted from xxHash homepage: + * + * xxHash is an extremely fast Hash algorithm, running at RAM speed limits. + * It also successfully passes all tests from the SMHasher suite. + * + * Comparison (single thread, Windows Seven 32 bits, using SMHasher on a Core 2 + * Duo @3GHz) + * + * Name Speed Q.Score Author + * xxHash 5.4 GB/s 10 + * CrapWow 3.2 GB/s 2 Andrew + * MumurHash 3a 2.7 GB/s 10 Austin Appleby + * SpookyHash 2.0 GB/s 10 Bob Jenkins + * SBox 1.4 GB/s 9 Bret Mulvey + * Lookup3 1.2 GB/s 9 Bob Jenkins + * SuperFastHash 1.2 GB/s 1 Paul Hsieh + * CityHash64 1.05 GB/s 10 Pike & Alakuijala + * FNV 0.55 GB/s 5 Fowler, Noll, Vo + * CRC32 0.43 GB/s 9 + * MD5-32 0.33 GB/s 10 Ronald L. Rivest + * SHA1-32 0.28 GB/s 10 + * + * Q.Score is a measure of quality of the hash function. + * It depends on successfully passing SMHasher test set. + * 10 is a perfect score. + * + * A 64-bits version, named xxh64 offers much better speed, + * but for 64-bits applications only. + * Name Speed on 64 bits Speed on 32 bits + * xxh64 13.8 GB/s 1.9 GB/s + * xxh32 6.8 GB/s 6.0 GB/s + */ + +#ifndef XXHASH_H +#define XXHASH_H + +#include <linux/types.h> + +/*-**************************** + * Simple Hash Functions + *****************************/ + +/** + * xxh32() - calculate the 32-bit hash of the input with a given seed. + * + * @input: The data to hash. + * @length: The length of the data to hash. + * @seed: The seed can be used to alter the result predictably. + * + * Speed on Core 2 Duo @ 3 GHz (single thread, SMHasher benchmark) : 5.4 GB/s + * + * Return: The 32-bit hash of the data. + */ +uint32_t xxh32(const void *input, size_t length, uint32_t seed); + +/** + * xxh64() - calculate the 64-bit hash of the input with a given seed. + * + * @input: The data to hash. + * @length: The length of the data to hash. + * @seed: The seed can be used to alter the result predictably. + * + * This function runs 2x faster on 64-bit systems, but slower on 32-bit systems. + * + * Return: The 64-bit hash of the data. + */ +uint64_t xxh64(const void *input, size_t length, uint64_t seed); + +/** + * xxhash() - calculate wordsize hash of the input with a given seed + * @input: The data to hash. + * @length: The length of the data to hash. + * @seed: The seed can be used to alter the result predictably. + * + * If the hash does not need to be comparable between machines with + * different word sizes, this function will call whichever of xxh32() + * or xxh64() is faster. + * + * Return: wordsize hash of the data. + */ + +static inline unsigned long xxhash(const void *input, size_t length, + uint64_t seed) +{ +#if BITS_PER_LONG == 64 + return xxh64(input, length, seed); +#else + return xxh32(input, length, seed); +#endif +} + +/*-**************************** + * Streaming Hash Functions + *****************************/ + +/* + * These definitions are only meant to allow allocation of XXH state + * statically, on stack, or in a struct for example. + * Do not use members directly. + */ + +/** + * struct xxh32_state - private xxh32 state, do not use members directly + */ +struct xxh32_state { + uint32_t total_len_32; + uint32_t large_len; + uint32_t v1; + uint32_t v2; + uint32_t v3; + uint32_t v4; + uint32_t mem32[4]; + uint32_t memsize; +}; + +/** + * struct xxh32_state - private xxh64 state, do not use members directly + */ +struct xxh64_state { + uint64_t total_len; + uint64_t v1; + uint64_t v2; + uint64_t v3; + uint64_t v4; + uint64_t mem64[4]; + uint32_t memsize; +}; + +/** + * xxh32_reset() - reset the xxh32 state to start a new hashing operation + * + * @state: The xxh32 state to reset. + * @seed: Initialize the hash state with this seed. + * + * Call this function on any xxh32_state to prepare for a new hashing operation. + */ +void xxh32_reset(struct xxh32_state *state, uint32_t seed); + +/** + * xxh32_update() - hash the data given and update the xxh32 state + * + * @state: The xxh32 state to update. + * @input: The data to hash. + * @length: The length of the data to hash. + * + * After calling xxh32_reset() call xxh32_update() as many times as necessary. + * + * Return: Zero on success, otherwise an error code. + */ +int xxh32_update(struct xxh32_state *state, const void *input, size_t length); + +/** + * xxh32_digest() - produce the current xxh32 hash + * + * @state: Produce the current xxh32 hash of this state. + * + * A hash value can be produced at any time. It is still possible to continue + * inserting input into the hash state after a call to xxh32_digest(), and + * generate new hashes later on, by calling xxh32_digest() again. + * + * Return: The xxh32 hash stored in the state. + */ +uint32_t xxh32_digest(const struct xxh32_state *state); + +/** + * xxh64_reset() - reset the xxh64 state to start a new hashing operation + * + * @state: The xxh64 state to reset. + * @seed: Initialize the hash state with this seed. + */ +void xxh64_reset(struct xxh64_state *state, uint64_t seed); + +/** + * xxh64_update() - hash the data given and update the xxh64 state + * @state: The xxh64 state to update. + * @input: The data to hash. + * @length: The length of the data to hash. + * + * After calling xxh64_reset() call xxh64_update() as many times as necessary. + * + * Return: Zero on success, otherwise an error code. + */ +int xxh64_update(struct xxh64_state *state, const void *input, size_t length); + +/** + * xxh64_digest() - produce the current xxh64 hash + * + * @state: Produce the current xxh64 hash of this state. + * + * A hash value can be produced at any time. It is still possible to continue + * inserting input into the hash state after a call to xxh64_digest(), and + * generate new hashes later on, by calling xxh64_digest() again. + * + * Return: The xxh64 hash stored in the state. + */ +uint64_t xxh64_digest(const struct xxh64_state *state); + +/*-************************** + * Utils + ***************************/ + +/** + * xxh32_copy_state() - copy the source state into the destination state + * + * @src: The source xxh32 state. + * @dst: The destination xxh32 state. + */ +void xxh32_copy_state(struct xxh32_state *dst, const struct xxh32_state *src); + +/** + * xxh64_copy_state() - copy the source state into the destination state + * + * @src: The source xxh64 state. + * @dst: The destination xxh64 state. + */ +void xxh64_copy_state(struct xxh64_state *dst, const struct xxh64_state *src); + +#endif /* XXHASH_H */ diff --git a/include/linux/zstd.h b/include/linux/zstd.h new file mode 100644 index 00000000000..724f69350e0 --- /dev/null +++ b/include/linux/zstd.h @@ -0,0 +1,1147 @@ +/* SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause-Clear) */ +/* + * Copyright (c) 2016-present, Yann Collet, Facebook, Inc. + * All rights reserved. + */ + +#ifndef ZSTD_H +#define ZSTD_H + +/* ====== Dependency ======*/ +#include <linux/types.h> /* size_t */ + + +/*-***************************************************************************** + * Introduction + * + * zstd, short for Zstandard, is a fast lossless compression algorithm, + * targeting real-time compression scenarios at zlib-level and better + * compression ratios. The zstd compression library provides in-memory + * compression and decompression functions. The library supports compression + * levels from 1 up to ZSTD_maxCLevel() which is 22. Levels >= 20, labeled + * ultra, should be used with caution, as they require more memory. + * Compression can be done in: + * - a single step, reusing a context (described as Explicit memory management) + * - unbounded multiple steps (described as Streaming compression) + * The compression ratio achievable on small data can be highly improved using + * compression with a dictionary in: + * - a single step (described as Simple dictionary API) + * - a single step, reusing a dictionary (described as Fast dictionary API) + ******************************************************************************/ + +/*====== Helper functions ======*/ + +/** + * enum ZSTD_ErrorCode - zstd error codes + * + * Functions that return size_t can be checked for errors using ZSTD_isError() + * and the ZSTD_ErrorCode can be extracted using ZSTD_getErrorCode(). + */ +typedef enum { + ZSTD_error_no_error, + ZSTD_error_GENERIC, + ZSTD_error_prefix_unknown, + ZSTD_error_version_unsupported, + ZSTD_error_parameter_unknown, + ZSTD_error_frameParameter_unsupported, + ZSTD_error_frameParameter_unsupportedBy32bits, + ZSTD_error_frameParameter_windowTooLarge, + ZSTD_error_compressionParameter_unsupported, + ZSTD_error_init_missing, + ZSTD_error_memory_allocation, + ZSTD_error_stage_wrong, + ZSTD_error_dstSize_tooSmall, + ZSTD_error_srcSize_wrong, + ZSTD_error_corruption_detected, + ZSTD_error_checksum_wrong, + ZSTD_error_tableLog_tooLarge, + ZSTD_error_maxSymbolValue_tooLarge, + ZSTD_error_maxSymbolValue_tooSmall, + ZSTD_error_dictionary_corrupted, + ZSTD_error_dictionary_wrong, + ZSTD_error_dictionaryCreation_failed, + ZSTD_error_maxCode +} ZSTD_ErrorCode; + +/** + * ZSTD_maxCLevel() - maximum compression level available + * + * Return: Maximum compression level available. + */ +int ZSTD_maxCLevel(void); +/** + * ZSTD_compressBound() - maximum compressed size in worst case scenario + * @srcSize: The size of the data to compress. + * + * Return: The maximum compressed size in the worst case scenario. + */ +size_t ZSTD_compressBound(size_t srcSize); +/** + * ZSTD_isError() - tells if a size_t function result is an error code + * @code: The function result to check for error. + * + * Return: Non-zero iff the code is an error. + */ +static __attribute__((unused)) unsigned int ZSTD_isError(size_t code) +{ + return code > (size_t)-ZSTD_error_maxCode; +} +/** + * ZSTD_getErrorCode() - translates an error function result to a ZSTD_ErrorCode + * @functionResult: The result of a function for which ZSTD_isError() is true. + * + * Return: The ZSTD_ErrorCode corresponding to the functionResult or 0 + * if the functionResult isn't an error. + */ +static __attribute__((unused)) ZSTD_ErrorCode ZSTD_getErrorCode( + size_t functionResult) +{ + if (!ZSTD_isError(functionResult)) + return (ZSTD_ErrorCode)0; + return (ZSTD_ErrorCode)(0 - functionResult); +} + +/** + * enum ZSTD_strategy - zstd compression search strategy + * + * From faster to stronger. + */ +typedef enum { + ZSTD_fast, + ZSTD_dfast, + ZSTD_greedy, + ZSTD_lazy, + ZSTD_lazy2, + ZSTD_btlazy2, + ZSTD_btopt, + ZSTD_btopt2 +} ZSTD_strategy; + +/** + * struct ZSTD_compressionParameters - zstd compression parameters + * @windowLog: Log of the largest match distance. Larger means more + * compression, and more memory needed during decompression. + * @chainLog: Fully searched segment. Larger means more compression, slower, + * and more memory (useless for fast). + * @hashLog: Dispatch table. Larger means more compression, + * slower, and more memory. + * @searchLog: Number of searches. Larger means more compression and slower. + * @searchLength: Match length searched. Larger means faster decompression, + * sometimes less compression. + * @targetLength: Acceptable match size for optimal parser (only). Larger means + * more compression, and slower. + * @strategy: The zstd compression strategy. + */ +typedef struct { + unsigned int windowLog; + unsigned int chainLog; + unsigned int hashLog; + unsigned int searchLog; + unsigned int searchLength; + unsigned int targetLength; + ZSTD_strategy strategy; +} ZSTD_compressionParameters; + +/** + * struct ZSTD_frameParameters - zstd frame parameters + * @contentSizeFlag: Controls whether content size will be present in the frame + * header (when known). + * @checksumFlag: Controls whether a 32-bit checksum is generated at the end + * of the frame for error detection. + * @noDictIDFlag: Controls whether dictID will be saved into the frame header + * when using dictionary compression. + * + * The default value is all fields set to 0. + */ +typedef struct { + unsigned int contentSizeFlag; + unsigned int checksumFlag; + unsigned int noDictIDFlag; +} ZSTD_frameParameters; + +/** + * struct ZSTD_parameters - zstd parameters + * @cParams: The compression parameters. + * @fParams: The frame parameters. + */ +typedef struct { + ZSTD_compressionParameters cParams; + ZSTD_frameParameters fParams; +} ZSTD_parameters; + +/** + * ZSTD_getCParams() - returns ZSTD_compressionParameters for selected level + * @compressionLevel: The compression level from 1 to ZSTD_maxCLevel(). + * @estimatedSrcSize: The estimated source size to compress or 0 if unknown. + * @dictSize: The dictionary size or 0 if a dictionary isn't being used. + * + * Return: The selected ZSTD_compressionParameters. + */ +ZSTD_compressionParameters ZSTD_getCParams(int compressionLevel, + unsigned long long estimatedSrcSize, size_t dictSize); + +/** + * ZSTD_getParams() - returns ZSTD_parameters for selected level + * @compressionLevel: The compression level from 1 to ZSTD_maxCLevel(). + * @estimatedSrcSize: The estimated source size to compress or 0 if unknown. + * @dictSize: The dictionary size or 0 if a dictionary isn't being used. + * + * The same as ZSTD_getCParams() except also selects the default frame + * parameters (all zero). + * + * Return: The selected ZSTD_parameters. + */ +ZSTD_parameters ZSTD_getParams(int compressionLevel, + unsigned long long estimatedSrcSize, size_t dictSize); + +/*-************************************* + * Explicit memory management + **************************************/ + +/** + * ZSTD_CCtxWorkspaceBound() - amount of memory needed to initialize a ZSTD_CCtx + * @cParams: The compression parameters to be used for compression. + * + * If multiple compression parameters might be used, the caller must call + * ZSTD_CCtxWorkspaceBound() for each set of parameters and use the maximum + * size. + * + * Return: A lower bound on the size of the workspace that is passed to + * ZSTD_initCCtx(). + */ +size_t ZSTD_CCtxWorkspaceBound(ZSTD_compressionParameters cParams); + +/** + * struct ZSTD_CCtx - the zstd compression context + * + * When compressing many times it is recommended to allocate a context just once + * and reuse it for each successive compression operation. + */ +typedef struct ZSTD_CCtx_s ZSTD_CCtx; +/** + * ZSTD_initCCtx() - initialize a zstd compression context + * @workspace: The workspace to emplace the context into. It must outlive + * the returned context. + * @workspaceSize: The size of workspace. Use ZSTD_CCtxWorkspaceBound() to + * determine how large the workspace must be. + * + * Return: A compression context emplaced into workspace. + */ +ZSTD_CCtx *ZSTD_initCCtx(void *workspace, size_t workspaceSize); + +/** + * ZSTD_compressCCtx() - compress src into dst + * @ctx: The context. Must have been initialized with a workspace at + * least as large as ZSTD_CCtxWorkspaceBound(params.cParams). + * @dst: The buffer to compress src into. + * @dstCapacity: The size of the destination buffer. May be any size, but + * ZSTD_compressBound(srcSize) is guaranteed to be large enough. + * @src: The data to compress. + * @srcSize: The size of the data to compress. + * @params: The parameters to use for compression. See ZSTD_getParams(). + * + * Return: The compressed size or an error, which can be checked using + * ZSTD_isError(). + */ +size_t ZSTD_compressCCtx(ZSTD_CCtx *ctx, void *dst, size_t dstCapacity, + const void *src, size_t srcSize, ZSTD_parameters params); + +/** + * ZSTD_DCtxWorkspaceBound() - amount of memory needed to initialize a ZSTD_DCtx + * + * Return: A lower bound on the size of the workspace that is passed to + * ZSTD_initDCtx(). + */ +size_t ZSTD_DCtxWorkspaceBound(void); + +/** + * struct ZSTD_DCtx - the zstd decompression context + * + * When decompressing many times it is recommended to allocate a context just + * once and reuse it for each successive decompression operation. + */ +typedef struct ZSTD_DCtx_s ZSTD_DCtx; +/** + * ZSTD_initDCtx() - initialize a zstd decompression context + * @workspace: The workspace to emplace the context into. It must outlive + * the returned context. + * @workspaceSize: The size of workspace. Use ZSTD_DCtxWorkspaceBound() to + * determine how large the workspace must be. + * + * Return: A decompression context emplaced into workspace. + */ +ZSTD_DCtx *ZSTD_initDCtx(void *workspace, size_t workspaceSize); + +/** + * ZSTD_decompressDCtx() - decompress zstd compressed src into dst + * @ctx: The decompression context. + * @dst: The buffer to decompress src into. + * @dstCapacity: The size of the destination buffer. Must be at least as large + * as the decompressed size. If the caller cannot upper bound the + * decompressed size, then it's better to use the streaming API. + * @src: The zstd compressed data to decompress. Multiple concatenated + * frames and skippable frames are allowed. + * @srcSize: The exact size of the data to decompress. + * + * Return: The decompressed size or an error, which can be checked using + * ZSTD_isError(). + */ +size_t ZSTD_decompressDCtx(ZSTD_DCtx *ctx, void *dst, size_t dstCapacity, + const void *src, size_t srcSize); + +/*-************************ + * Simple dictionary API + **************************/ + +/** + * ZSTD_compress_usingDict() - compress src into dst using a dictionary + * @ctx: The context. Must have been initialized with a workspace at + * least as large as ZSTD_CCtxWorkspaceBound(params.cParams). + * @dst: The buffer to compress src into. + * @dstCapacity: The size of the destination buffer. May be any size, but + * ZSTD_compressBound(srcSize) is guaranteed to be large enough. + * @src: The data to compress. + * @srcSize: The size of the data to compress. + * @dict: The dictionary to use for compression. + * @dictSize: The size of the dictionary. + * @params: The parameters to use for compression. See ZSTD_getParams(). + * + * Compression using a predefined dictionary. The same dictionary must be used + * during decompression. + * + * Return: The compressed size or an error, which can be checked using + * ZSTD_isError(). + */ +size_t ZSTD_compress_usingDict(ZSTD_CCtx *ctx, void *dst, size_t dstCapacity, + const void *src, size_t srcSize, const void *dict, size_t dictSize, + ZSTD_parameters params); + +/** + * ZSTD_decompress_usingDict() - decompress src into dst using a dictionary + * @ctx: The decompression context. + * @dst: The buffer to decompress src into. + * @dstCapacity: The size of the destination buffer. Must be at least as large + * as the decompressed size. If the caller cannot upper bound the + * decompressed size, then it's better to use the streaming API. + * @src: The zstd compressed data to decompress. Multiple concatenated + * frames and skippable frames are allowed. + * @srcSize: The exact size of the data to decompress. + * @dict: The dictionary to use for decompression. The same dictionary + * must've been used to compress the data. + * @dictSize: The size of the dictionary. + * + * Return: The decompressed size or an error, which can be checked using + * ZSTD_isError(). + */ +size_t ZSTD_decompress_usingDict(ZSTD_DCtx *ctx, void *dst, size_t dstCapacity, + const void *src, size_t srcSize, const void *dict, size_t dictSize); + +/*-************************** + * Fast dictionary API + ***************************/ + +/** + * ZSTD_CDictWorkspaceBound() - memory needed to initialize a ZSTD_CDict + * @cParams: The compression parameters to be used for compression. + * + * Return: A lower bound on the size of the workspace that is passed to + * ZSTD_initCDict(). + */ +size_t ZSTD_CDictWorkspaceBound(ZSTD_compressionParameters cParams); + +/** + * struct ZSTD_CDict - a digested dictionary to be used for compression + */ +typedef struct ZSTD_CDict_s ZSTD_CDict; + +/** + * ZSTD_initCDict() - initialize a digested dictionary for compression + * @dictBuffer: The dictionary to digest. The buffer is referenced by the + * ZSTD_CDict so it must outlive the returned ZSTD_CDict. + * @dictSize: The size of the dictionary. + * @params: The parameters to use for compression. See ZSTD_getParams(). + * @workspace: The workspace. It must outlive the returned ZSTD_CDict. + * @workspaceSize: The workspace size. Must be at least + * ZSTD_CDictWorkspaceBound(params.cParams). + * + * When compressing multiple messages / blocks with the same dictionary it is + * recommended to load it just once. The ZSTD_CDict merely references the + * dictBuffer, so it must outlive the returned ZSTD_CDict. + * + * Return: The digested dictionary emplaced into workspace. + */ +ZSTD_CDict *ZSTD_initCDict(const void *dictBuffer, size_t dictSize, + ZSTD_parameters params, void *workspace, size_t workspaceSize); + +/** + * ZSTD_compress_usingCDict() - compress src into dst using a ZSTD_CDict + * @ctx: The context. Must have been initialized with a workspace at + * least as large as ZSTD_CCtxWorkspaceBound(cParams) where + * cParams are the compression parameters used to initialize the + * cdict. + * @dst: The buffer to compress src into. + * @dstCapacity: The size of the destination buffer. May be any size, but + * ZSTD_compressBound(srcSize) is guaranteed to be large enough. + * @src: The data to compress. + * @srcSize: The size of the data to compress. + * @cdict: The digested dictionary to use for compression. + * @params: The parameters to use for compression. See ZSTD_getParams(). + * + * Compression using a digested dictionary. The same dictionary must be used + * during decompression. + * + * Return: The compressed size or an error, which can be checked using + * ZSTD_isError(). + */ +size_t ZSTD_compress_usingCDict(ZSTD_CCtx *cctx, void *dst, size_t dstCapacity, + const void *src, size_t srcSize, const ZSTD_CDict *cdict); + + +/** + * ZSTD_DDictWorkspaceBound() - memory needed to initialize a ZSTD_DDict + * + * Return: A lower bound on the size of the workspace that is passed to + * ZSTD_initDDict(). + */ +size_t ZSTD_DDictWorkspaceBound(void); + +/** + * struct ZSTD_DDict - a digested dictionary to be used for decompression + */ +typedef struct ZSTD_DDict_s ZSTD_DDict; + +/** + * ZSTD_initDDict() - initialize a digested dictionary for decompression + * @dictBuffer: The dictionary to digest. The buffer is referenced by the + * ZSTD_DDict so it must outlive the returned ZSTD_DDict. + * @dictSize: The size of the dictionary. + * @workspace: The workspace. It must outlive the returned ZSTD_DDict. + * @workspaceSize: The workspace size. Must be at least + * ZSTD_DDictWorkspaceBound(). + * + * When decompressing multiple messages / blocks with the same dictionary it is + * recommended to load it just once. The ZSTD_DDict merely references the + * dictBuffer, so it must outlive the returned ZSTD_DDict. + * + * Return: The digested dictionary emplaced into workspace. + */ +ZSTD_DDict *ZSTD_initDDict(const void *dictBuffer, size_t dictSize, + void *workspace, size_t workspaceSize); + +/** + * ZSTD_decompress_usingDDict() - decompress src into dst using a ZSTD_DDict + * @ctx: The decompression context. + * @dst: The buffer to decompress src into. + * @dstCapacity: The size of the destination buffer. Must be at least as large + * as the decompressed size. If the caller cannot upper bound the + * decompressed size, then it's better to use the streaming API. + * @src: The zstd compressed data to decompress. Multiple concatenated + * frames and skippable frames are allowed. + * @srcSize: The exact size of the data to decompress. + * @ddict: The digested dictionary to use for decompression. The same + * dictionary must've been used to compress the data. + * + * Return: The decompressed size or an error, which can be checked using + * ZSTD_isError(). + */ +size_t ZSTD_decompress_usingDDict(ZSTD_DCtx *dctx, void *dst, + size_t dstCapacity, const void *src, size_t srcSize, + const ZSTD_DDict *ddict); + + +/*-************************** + * Streaming + ***************************/ + +/** + * struct ZSTD_inBuffer - input buffer for streaming + * @src: Start of the input buffer. + * @size: Size of the input buffer. + * @pos: Position where reading stopped. Will be updated. + * Necessarily 0 <= pos <= size. + */ +typedef struct ZSTD_inBuffer_s { + const void *src; + size_t size; + size_t pos; +} ZSTD_inBuffer; + +/** + * struct ZSTD_outBuffer - output buffer for streaming + * @dst: Start of the output buffer. + * @size: Size of the output buffer. + * @pos: Position where writing stopped. Will be updated. + * Necessarily 0 <= pos <= size. + */ +typedef struct ZSTD_outBuffer_s { + void *dst; + size_t size; + size_t pos; +} ZSTD_outBuffer; + + + +/*-***************************************************************************** + * Streaming compression - HowTo + * + * A ZSTD_CStream object is required to track streaming operation. + * Use ZSTD_initCStream() to initialize a ZSTD_CStream object. + * ZSTD_CStream objects can be reused multiple times on consecutive compression + * operations. It is recommended to re-use ZSTD_CStream in situations where many + * streaming operations will be achieved consecutively. Use one separate + * ZSTD_CStream per thread for parallel execution. + * + * Use ZSTD_compressStream() repetitively to consume input stream. + * The function will automatically update both `pos` fields. + * Note that it may not consume the entire input, in which case `pos < size`, + * and it's up to the caller to present again remaining data. + * It returns a hint for the preferred number of bytes to use as an input for + * the next function call. + * + * At any moment, it's possible to flush whatever data remains within internal + * buffer, using ZSTD_flushStream(). `output->pos` will be updated. There might + * still be some content left within the internal buffer if `output->size` is + * too small. It returns the number of bytes left in the internal buffer and + * must be called until it returns 0. + * + * ZSTD_endStream() instructs to finish a frame. It will perform a flush and + * write frame epilogue. The epilogue is required for decoders to consider a + * frame completed. Similar to ZSTD_flushStream(), it may not be able to flush + * the full content if `output->size` is too small. In which case, call again + * ZSTD_endStream() to complete the flush. It returns the number of bytes left + * in the internal buffer and must be called until it returns 0. + ******************************************************************************/ + +/** + * ZSTD_CStreamWorkspaceBound() - memory needed to initialize a ZSTD_CStream + * @cParams: The compression parameters to be used for compression. + * + * Return: A lower bound on the size of the workspace that is passed to + * ZSTD_initCStream() and ZSTD_initCStream_usingCDict(). + */ +size_t ZSTD_CStreamWorkspaceBound(ZSTD_compressionParameters cParams); + +/** + * struct ZSTD_CStream - the zstd streaming compression context + */ +typedef struct ZSTD_CStream_s ZSTD_CStream; + +/*===== ZSTD_CStream management functions =====*/ +/** + * ZSTD_initCStream() - initialize a zstd streaming compression context + * @params: The zstd compression parameters. + * @pledgedSrcSize: If params.fParams.contentSizeFlag == 1 then the caller must + * pass the source size (zero means empty source). Otherwise, + * the caller may optionally pass the source size, or zero if + * unknown. + * @workspace: The workspace to emplace the context into. It must outlive + * the returned context. + * @workspaceSize: The size of workspace. + * Use ZSTD_CStreamWorkspaceBound(params.cParams) to determine + * how large the workspace must be. + * + * Return: The zstd streaming compression context. + */ +ZSTD_CStream *ZSTD_initCStream(ZSTD_parameters params, + unsigned long long pledgedSrcSize, void *workspace, + size_t workspaceSize); + +/** + * ZSTD_initCStream_usingCDict() - initialize a streaming compression context + * @cdict: The digested dictionary to use for compression. + * @pledgedSrcSize: Optionally the source size, or zero if unknown. + * @workspace: The workspace to emplace the context into. It must outlive + * the returned context. + * @workspaceSize: The size of workspace. Call ZSTD_CStreamWorkspaceBound() + * with the cParams used to initialize the cdict to determine + * how large the workspace must be. + * + * Return: The zstd streaming compression context. + */ +ZSTD_CStream *ZSTD_initCStream_usingCDict(const ZSTD_CDict *cdict, + unsigned long long pledgedSrcSize, void *workspace, + size_t workspaceSize); + +/*===== Streaming compression functions =====*/ +/** + * ZSTD_resetCStream() - reset the context using parameters from creation + * @zcs: The zstd streaming compression context to reset. + * @pledgedSrcSize: Optionally the source size, or zero if unknown. + * + * Resets the context using the parameters from creation. Skips dictionary + * loading, since it can be reused. If `pledgedSrcSize` is non-zero the frame + * content size is always written into the frame header. + * + * Return: Zero or an error, which can be checked using ZSTD_isError(). + */ +size_t ZSTD_resetCStream(ZSTD_CStream *zcs, unsigned long long pledgedSrcSize); +/** + * ZSTD_compressStream() - streaming compress some of input into output + * @zcs: The zstd streaming compression context. + * @output: Destination buffer. `output->pos` is updated to indicate how much + * compressed data was written. + * @input: Source buffer. `input->pos` is updated to indicate how much data was + * read. Note that it may not consume the entire input, in which case + * `input->pos < input->size`, and it's up to the caller to present + * remaining data again. + * + * The `input` and `output` buffers may be any size. Guaranteed to make some + * forward progress if `input` and `output` are not empty. + * + * Return: A hint for the number of bytes to use as the input for the next + * function call or an error, which can be checked using + * ZSTD_isError(). + */ +size_t ZSTD_compressStream(ZSTD_CStream *zcs, ZSTD_outBuffer *output, + ZSTD_inBuffer *input); +/** + * ZSTD_flushStream() - flush internal buffers into output + * @zcs: The zstd streaming compression context. + * @output: Destination buffer. `output->pos` is updated to indicate how much + * compressed data was written. + * + * ZSTD_flushStream() must be called until it returns 0, meaning all the data + * has been flushed. Since ZSTD_flushStream() causes a block to be ended, + * calling it too often will degrade the compression ratio. + * + * Return: The number of bytes still present within internal buffers or an + * error, which can be checked using ZSTD_isError(). + */ +size_t ZSTD_flushStream(ZSTD_CStream *zcs, ZSTD_outBuffer *output); +/** + * ZSTD_endStream() - flush internal buffers into output and end the frame + * @zcs: The zstd streaming compression context. + * @output: Destination buffer. `output->pos` is updated to indicate how much + * compressed data was written. + * + * ZSTD_endStream() must be called until it returns 0, meaning all the data has + * been flushed and the frame epilogue has been written. + * + * Return: The number of bytes still present within internal buffers or an + * error, which can be checked using ZSTD_isError(). + */ +size_t ZSTD_endStream(ZSTD_CStream *zcs, ZSTD_outBuffer *output); + +/** + * ZSTD_CStreamInSize() - recommended size for the input buffer + * + * Return: The recommended size for the input buffer. + */ +size_t ZSTD_CStreamInSize(void); +/** + * ZSTD_CStreamOutSize() - recommended size for the output buffer + * + * When the output buffer is at least this large, it is guaranteed to be large + * enough to flush at least one complete compressed block. + * + * Return: The recommended size for the output buffer. + */ +size_t ZSTD_CStreamOutSize(void); + + + +/*-***************************************************************************** + * Streaming decompression - HowTo + * + * A ZSTD_DStream object is required to track streaming operations. + * Use ZSTD_initDStream() to initialize a ZSTD_DStream object. + * ZSTD_DStream objects can be re-used multiple times. + * + * Use ZSTD_decompressStream() repetitively to consume your input. + * The function will update both `pos` fields. + * If `input->pos < input->size`, some input has not been consumed. + * It's up to the caller to present again remaining data. + * If `output->pos < output->size`, decoder has flushed everything it could. + * Returns 0 iff a frame is completely decoded and fully flushed. + * Otherwise it returns a suggested next input size that will never load more + * than the current frame. + ******************************************************************************/ + +/** + * ZSTD_DStreamWorkspaceBound() - memory needed to initialize a ZSTD_DStream + * @maxWindowSize: The maximum window size allowed for compressed frames. + * + * Return: A lower bound on the size of the workspace that is passed to + * ZSTD_initDStream() and ZSTD_initDStream_usingDDict(). + */ +size_t ZSTD_DStreamWorkspaceBound(size_t maxWindowSize); + +/** + * struct ZSTD_DStream - the zstd streaming decompression context + */ +typedef struct ZSTD_DStream_s ZSTD_DStream; +/*===== ZSTD_DStream management functions =====*/ +/** + * ZSTD_initDStream() - initialize a zstd streaming decompression context + * @maxWindowSize: The maximum window size allowed for compressed frames. + * @workspace: The workspace to emplace the context into. It must outlive + * the returned context. + * @workspaceSize: The size of workspace. + * Use ZSTD_DStreamWorkspaceBound(maxWindowSize) to determine + * how large the workspace must be. + * + * Return: The zstd streaming decompression context. + */ +ZSTD_DStream *ZSTD_initDStream(size_t maxWindowSize, void *workspace, + size_t workspaceSize); +/** + * ZSTD_initDStream_usingDDict() - initialize streaming decompression context + * @maxWindowSize: The maximum window size allowed for compressed frames. + * @ddict: The digested dictionary to use for decompression. + * @workspace: The workspace to emplace the context into. It must outlive + * the returned context. + * @workspaceSize: The size of workspace. + * Use ZSTD_DStreamWorkspaceBound(maxWindowSize) to determine + * how large the workspace must be. + * + * Return: The zstd streaming decompression context. + */ +ZSTD_DStream *ZSTD_initDStream_usingDDict(size_t maxWindowSize, + const ZSTD_DDict *ddict, void *workspace, size_t workspaceSize); + +/*===== Streaming decompression functions =====*/ +/** + * ZSTD_resetDStream() - reset the context using parameters from creation + * @zds: The zstd streaming decompression context to reset. + * + * Resets the context using the parameters from creation. Skips dictionary + * loading, since it can be reused. + * + * Return: Zero or an error, which can be checked using ZSTD_isError(). + */ +size_t ZSTD_resetDStream(ZSTD_DStream *zds); +/** + * ZSTD_decompressStream() - streaming decompress some of input into output + * @zds: The zstd streaming decompression context. + * @output: Destination buffer. `output.pos` is updated to indicate how much + * decompressed data was written. + * @input: Source buffer. `input.pos` is updated to indicate how much data was + * read. Note that it may not consume the entire input, in which case + * `input.pos < input.size`, and it's up to the caller to present + * remaining data again. + * + * The `input` and `output` buffers may be any size. Guaranteed to make some + * forward progress if `input` and `output` are not empty. + * ZSTD_decompressStream() will not consume the last byte of the frame until + * the entire frame is flushed. + * + * Return: Returns 0 iff a frame is completely decoded and fully flushed. + * Otherwise returns a hint for the number of bytes to use as the input + * for the next function call or an error, which can be checked using + * ZSTD_isError(). The size hint will never load more than the frame. + */ +size_t ZSTD_decompressStream(ZSTD_DStream *zds, ZSTD_outBuffer *output, + ZSTD_inBuffer *input); + +/** + * ZSTD_DStreamInSize() - recommended size for the input buffer + * + * Return: The recommended size for the input buffer. + */ +size_t ZSTD_DStreamInSize(void); +/** + * ZSTD_DStreamOutSize() - recommended size for the output buffer + * + * When the output buffer is at least this large, it is guaranteed to be large + * enough to flush at least one complete decompressed block. + * + * Return: The recommended size for the output buffer. + */ +size_t ZSTD_DStreamOutSize(void); + + +/* --- Constants ---*/ +#define ZSTD_MAGICNUMBER 0xFD2FB528 /* >= v0.8.0 */ +#define ZSTD_MAGIC_SKIPPABLE_START 0x184D2A50U + +#define ZSTD_CONTENTSIZE_UNKNOWN (0ULL - 1) +#define ZSTD_CONTENTSIZE_ERROR (0ULL - 2) + +#define ZSTD_WINDOWLOG_MAX_32 27 +#define ZSTD_WINDOWLOG_MAX_64 27 +#define ZSTD_WINDOWLOG_MAX \ + ((unsigned int)(sizeof(size_t) == 4 \ + ? ZSTD_WINDOWLOG_MAX_32 \ + : ZSTD_WINDOWLOG_MAX_64)) +#define ZSTD_WINDOWLOG_MIN 10 +#define ZSTD_HASHLOG_MAX ZSTD_WINDOWLOG_MAX +#define ZSTD_HASHLOG_MIN 6 +#define ZSTD_CHAINLOG_MAX (ZSTD_WINDOWLOG_MAX+1) +#define ZSTD_CHAINLOG_MIN ZSTD_HASHLOG_MIN +#define ZSTD_HASHLOG3_MAX 17 +#define ZSTD_SEARCHLOG_MAX (ZSTD_WINDOWLOG_MAX-1) +#define ZSTD_SEARCHLOG_MIN 1 +/* only for ZSTD_fast, other strategies are limited to 6 */ +#define ZSTD_SEARCHLENGTH_MAX 7 +/* only for ZSTD_btopt, other strategies are limited to 4 */ +#define ZSTD_SEARCHLENGTH_MIN 3 +#define ZSTD_TARGETLENGTH_MIN 4 +#define ZSTD_TARGETLENGTH_MAX 999 + +/* for static allocation */ +#define ZSTD_FRAMEHEADERSIZE_MAX 18 +#define ZSTD_FRAMEHEADERSIZE_MIN 6 +static const size_t ZSTD_frameHeaderSize_prefix = 5; +static const size_t ZSTD_frameHeaderSize_min = ZSTD_FRAMEHEADERSIZE_MIN; +static const size_t ZSTD_frameHeaderSize_max = ZSTD_FRAMEHEADERSIZE_MAX; +/* magic number + skippable frame length */ +static const size_t ZSTD_skippableHeaderSize = 8; + + +/*-************************************* + * Compressed size functions + **************************************/ + +/** + * ZSTD_findFrameCompressedSize() - returns the size of a compressed frame + * @src: Source buffer. It should point to the start of a zstd encoded frame + * or a skippable frame. + * @srcSize: The size of the source buffer. It must be at least as large as the + * size of the frame. + * + * Return: The compressed size of the frame pointed to by `src` or an error, + * which can be check with ZSTD_isError(). + * Suitable to pass to ZSTD_decompress() or similar functions. + */ +size_t ZSTD_findFrameCompressedSize(const void *src, size_t srcSize); + +/*-************************************* + * Decompressed size functions + **************************************/ +/** + * ZSTD_getFrameContentSize() - returns the content size in a zstd frame header + * @src: It should point to the start of a zstd encoded frame. + * @srcSize: The size of the source buffer. It must be at least as large as the + * frame header. `ZSTD_frameHeaderSize_max` is always large enough. + * + * Return: The frame content size stored in the frame header if known. + * `ZSTD_CONTENTSIZE_UNKNOWN` if the content size isn't stored in the + * frame header. `ZSTD_CONTENTSIZE_ERROR` on invalid input. + */ +unsigned long long ZSTD_getFrameContentSize(const void *src, size_t srcSize); + +/** + * ZSTD_findDecompressedSize() - returns decompressed size of a series of frames + * @src: It should point to the start of a series of zstd encoded and/or + * skippable frames. + * @srcSize: The exact size of the series of frames. + * + * If any zstd encoded frame in the series doesn't have the frame content size + * set, `ZSTD_CONTENTSIZE_UNKNOWN` is returned. But frame content size is always + * set when using ZSTD_compress(). The decompressed size can be very large. + * If the source is untrusted, the decompressed size could be wrong or + * intentionally modified. Always ensure the result fits within the + * application's authorized limits. ZSTD_findDecompressedSize() handles multiple + * frames, and so it must traverse the input to read each frame header. This is + * efficient as most of the data is skipped, however it does mean that all frame + * data must be present and valid. + * + * Return: Decompressed size of all the data contained in the frames if known. + * `ZSTD_CONTENTSIZE_UNKNOWN` if the decompressed size is unknown. + * `ZSTD_CONTENTSIZE_ERROR` if an error occurred. + */ +unsigned long long ZSTD_findDecompressedSize(const void *src, size_t srcSize); + +/*-************************************* + * Advanced compression functions + **************************************/ +/** + * ZSTD_checkCParams() - ensure parameter values remain within authorized range + * @cParams: The zstd compression parameters. + * + * Return: Zero or an error, which can be checked using ZSTD_isError(). + */ +size_t ZSTD_checkCParams(ZSTD_compressionParameters cParams); + +/** + * ZSTD_adjustCParams() - optimize parameters for a given srcSize and dictSize + * @srcSize: Optionally the estimated source size, or zero if unknown. + * @dictSize: Optionally the estimated dictionary size, or zero if unknown. + * + * Return: The optimized parameters. + */ +ZSTD_compressionParameters ZSTD_adjustCParams( + ZSTD_compressionParameters cParams, unsigned long long srcSize, + size_t dictSize); + +/*--- Advanced decompression functions ---*/ + +/** + * ZSTD_isFrame() - returns true iff the buffer starts with a valid frame + * @buffer: The source buffer to check. + * @size: The size of the source buffer, must be at least 4 bytes. + * + * Return: True iff the buffer starts with a zstd or skippable frame identifier. + */ +unsigned int ZSTD_isFrame(const void *buffer, size_t size); + +/** + * ZSTD_getDictID_fromDict() - returns the dictionary id stored in a dictionary + * @dict: The dictionary buffer. + * @dictSize: The size of the dictionary buffer. + * + * Return: The dictionary id stored within the dictionary or 0 if the + * dictionary is not a zstd dictionary. If it returns 0 the + * dictionary can still be loaded as a content-only dictionary. + */ +unsigned int ZSTD_getDictID_fromDict(const void *dict, size_t dictSize); + +/** + * ZSTD_getDictID_fromDDict() - returns the dictionary id stored in a ZSTD_DDict + * @ddict: The ddict to find the id of. + * + * Return: The dictionary id stored within `ddict` or 0 if the dictionary is not + * a zstd dictionary. If it returns 0 `ddict` will be loaded as a + * content-only dictionary. + */ +unsigned int ZSTD_getDictID_fromDDict(const ZSTD_DDict *ddict); + +/** + * ZSTD_getDictID_fromFrame() - returns the dictionary id stored in a zstd frame + * @src: Source buffer. It must be a zstd encoded frame. + * @srcSize: The size of the source buffer. It must be at least as large as the + * frame header. `ZSTD_frameHeaderSize_max` is always large enough. + * + * Return: The dictionary id required to decompress the frame stored within + * `src` or 0 if the dictionary id could not be decoded. It can return + * 0 if the frame does not require a dictionary, the dictionary id + * wasn't stored in the frame, `src` is not a zstd frame, or `srcSize` + * is too small. + */ +unsigned int ZSTD_getDictID_fromFrame(const void *src, size_t srcSize); + +/** + * struct ZSTD_frameParams - zstd frame parameters stored in the frame header + * @frameContentSize: The frame content size, or 0 if not present. + * @windowSize: The window size, or 0 if the frame is a skippable frame. + * @dictID: The dictionary id, or 0 if not present. + * @checksumFlag: Whether a checksum was used. + */ +typedef struct { + unsigned long long frameContentSize; + unsigned int windowSize; + unsigned int dictID; + unsigned int checksumFlag; +} ZSTD_frameParams; + +/** + * ZSTD_getFrameParams() - extracts parameters from a zstd or skippable frame + * @fparamsPtr: On success the frame parameters are written here. + * @src: The source buffer. It must point to a zstd or skippable frame. + * @srcSize: The size of the source buffer. `ZSTD_frameHeaderSize_max` is + * always large enough to succeed. + * + * Return: 0 on success. If more data is required it returns how many bytes + * must be provided to make forward progress. Otherwise it returns + * an error, which can be checked using ZSTD_isError(). + */ +size_t ZSTD_getFrameParams(ZSTD_frameParams *fparamsPtr, const void *src, + size_t srcSize); + +/*-***************************************************************************** + * Buffer-less and synchronous inner streaming functions + * + * This is an advanced API, giving full control over buffer management, for + * users which need direct control over memory. + * But it's also a complex one, with many restrictions (documented below). + * Prefer using normal streaming API for an easier experience + ******************************************************************************/ + +/*-***************************************************************************** + * Buffer-less streaming compression (synchronous mode) + * + * A ZSTD_CCtx object is required to track streaming operations. + * Use ZSTD_initCCtx() to initialize a context. + * ZSTD_CCtx object can be re-used multiple times within successive compression + * operations. + * + * Start by initializing a context. + * Use ZSTD_compressBegin(), or ZSTD_compressBegin_usingDict() for dictionary + * compression, + * or ZSTD_compressBegin_advanced(), for finer parameter control. + * It's also possible to duplicate a reference context which has already been + * initialized, using ZSTD_copyCCtx() + * + * Then, consume your input using ZSTD_compressContinue(). + * There are some important considerations to keep in mind when using this + * advanced function : + * - ZSTD_compressContinue() has no internal buffer. It uses externally provided + * buffer only. + * - Interface is synchronous : input is consumed entirely and produce 1+ + * (or more) compressed blocks. + * - Caller must ensure there is enough space in `dst` to store compressed data + * under worst case scenario. Worst case evaluation is provided by + * ZSTD_compressBound(). + * ZSTD_compressContinue() doesn't guarantee recover after a failed + * compression. + * - ZSTD_compressContinue() presumes prior input ***is still accessible and + * unmodified*** (up to maximum distance size, see WindowLog). + * It remembers all previous contiguous blocks, plus one separated memory + * segment (which can itself consists of multiple contiguous blocks) + * - ZSTD_compressContinue() detects that prior input has been overwritten when + * `src` buffer overlaps. In which case, it will "discard" the relevant memory + * section from its history. + * + * Finish a frame with ZSTD_compressEnd(), which will write the last block(s) + * and optional checksum. It's possible to use srcSize==0, in which case, it + * will write a final empty block to end the frame. Without last block mark, + * frames will be considered unfinished (corrupted) by decoders. + * + * `ZSTD_CCtx` object can be re-used (ZSTD_compressBegin()) to compress some new + * frame. + ******************************************************************************/ + +/*===== Buffer-less streaming compression functions =====*/ +size_t ZSTD_compressBegin(ZSTD_CCtx *cctx, int compressionLevel); +size_t ZSTD_compressBegin_usingDict(ZSTD_CCtx *cctx, const void *dict, + size_t dictSize, int compressionLevel); +size_t ZSTD_compressBegin_advanced(ZSTD_CCtx *cctx, const void *dict, + size_t dictSize, ZSTD_parameters params, + unsigned long long pledgedSrcSize); +size_t ZSTD_copyCCtx(ZSTD_CCtx *cctx, const ZSTD_CCtx *preparedCCtx, + unsigned long long pledgedSrcSize); +size_t ZSTD_compressBegin_usingCDict(ZSTD_CCtx *cctx, const ZSTD_CDict *cdict, + unsigned long long pledgedSrcSize); +size_t ZSTD_compressContinue(ZSTD_CCtx *cctx, void *dst, size_t dstCapacity, + const void *src, size_t srcSize); +size_t ZSTD_compressEnd(ZSTD_CCtx *cctx, void *dst, size_t dstCapacity, + const void *src, size_t srcSize); + + + +/*-***************************************************************************** + * Buffer-less streaming decompression (synchronous mode) + * + * A ZSTD_DCtx object is required to track streaming operations. + * Use ZSTD_initDCtx() to initialize a context. + * A ZSTD_DCtx object can be re-used multiple times. + * + * First typical operation is to retrieve frame parameters, using + * ZSTD_getFrameParams(). It fills a ZSTD_frameParams structure which provide + * important information to correctly decode the frame, such as the minimum + * rolling buffer size to allocate to decompress data (`windowSize`), and the + * dictionary ID used. + * Note: content size is optional, it may not be present. 0 means unknown. + * Note that these values could be wrong, either because of data malformation, + * or because an attacker is spoofing deliberate false information. As a + * consequence, check that values remain within valid application range, + * especially `windowSize`, before allocation. Each application can set its own + * limit, depending on local restrictions. For extended interoperability, it is + * recommended to support at least 8 MB. + * Frame parameters are extracted from the beginning of the compressed frame. + * Data fragment must be large enough to ensure successful decoding, typically + * `ZSTD_frameHeaderSize_max` bytes. + * Result: 0: successful decoding, the `ZSTD_frameParams` structure is filled. + * >0: `srcSize` is too small, provide at least this many bytes. + * errorCode, which can be tested using ZSTD_isError(). + * + * Start decompression, with ZSTD_decompressBegin() or + * ZSTD_decompressBegin_usingDict(). Alternatively, you can copy a prepared + * context, using ZSTD_copyDCtx(). + * + * Then use ZSTD_nextSrcSizeToDecompress() and ZSTD_decompressContinue() + * alternatively. + * ZSTD_nextSrcSizeToDecompress() tells how many bytes to provide as 'srcSize' + * to ZSTD_decompressContinue(). + * ZSTD_decompressContinue() requires this _exact_ amount of bytes, or it will + * fail. + * + * The result of ZSTD_decompressContinue() is the number of bytes regenerated + * within 'dst' (necessarily <= dstCapacity). It can be zero, which is not an + * error; it just means ZSTD_decompressContinue() has decoded some metadata + * item. It can also be an error code, which can be tested with ZSTD_isError(). + * + * ZSTD_decompressContinue() needs previous data blocks during decompression, up + * to `windowSize`. They should preferably be located contiguously, prior to + * current block. Alternatively, a round buffer of sufficient size is also + * possible. Sufficient size is determined by frame parameters. + * ZSTD_decompressContinue() is very sensitive to contiguity, if 2 blocks don't + * follow each other, make sure that either the compressor breaks contiguity at + * the same place, or that previous contiguous segment is large enough to + * properly handle maximum back-reference. + * + * A frame is fully decoded when ZSTD_nextSrcSizeToDecompress() returns zero. + * Context can then be reset to start a new decompression. + * + * Note: it's possible to know if next input to present is a header or a block, + * using ZSTD_nextInputType(). This information is not required to properly + * decode a frame. + * + * == Special case: skippable frames == + * + * Skippable frames allow integration of user-defined data into a flow of + * concatenated frames. Skippable frames will be ignored (skipped) by a + * decompressor. The format of skippable frames is as follows: + * a) Skippable frame ID - 4 Bytes, Little endian format, any value from + * 0x184D2A50 to 0x184D2A5F + * b) Frame Size - 4 Bytes, Little endian format, unsigned 32-bits + * c) Frame Content - any content (User Data) of length equal to Frame Size + * For skippable frames ZSTD_decompressContinue() always returns 0. + * For skippable frames ZSTD_getFrameParams() returns fparamsPtr->windowLog==0 + * what means that a frame is skippable. + * Note: If fparamsPtr->frameContentSize==0, it is ambiguous: the frame might + * actually be a zstd encoded frame with no content. For purposes of + * decompression, it is valid in both cases to skip the frame using + * ZSTD_findFrameCompressedSize() to find its size in bytes. + * It also returns frame size as fparamsPtr->frameContentSize. + ******************************************************************************/ + +/*===== Buffer-less streaming decompression functions =====*/ +size_t ZSTD_decompressBegin(ZSTD_DCtx *dctx); +size_t ZSTD_decompressBegin_usingDict(ZSTD_DCtx *dctx, const void *dict, + size_t dictSize); +void ZSTD_copyDCtx(ZSTD_DCtx *dctx, const ZSTD_DCtx *preparedDCtx); +size_t ZSTD_nextSrcSizeToDecompress(ZSTD_DCtx *dctx); +size_t ZSTD_decompressContinue(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, + const void *src, size_t srcSize); +typedef enum { + ZSTDnit_frameHeader, + ZSTDnit_blockHeader, + ZSTDnit_block, + ZSTDnit_lastBlock, + ZSTDnit_checksum, + ZSTDnit_skippableFrame +} ZSTD_nextInputType_e; +ZSTD_nextInputType_e ZSTD_nextInputType(ZSTD_DCtx *dctx); + +/*-***************************************************************************** + * Block functions + * + * Block functions produce and decode raw zstd blocks, without frame metadata. + * Frame metadata cost is typically ~18 bytes, which can be non-negligible for + * very small blocks (< 100 bytes). User will have to take in charge required + * information to regenerate data, such as compressed and content sizes. + * + * A few rules to respect: + * - Compressing and decompressing require a context structure + * + Use ZSTD_initCCtx() and ZSTD_initDCtx() + * - It is necessary to init context before starting + * + compression : ZSTD_compressBegin() + * + decompression : ZSTD_decompressBegin() + * + variants _usingDict() are also allowed + * + copyCCtx() and copyDCtx() work too + * - Block size is limited, it must be <= ZSTD_getBlockSizeMax() + * + If you need to compress more, cut data into multiple blocks + * + Consider using the regular ZSTD_compress() instead, as frame metadata + * costs become negligible when source size is large. + * - When a block is considered not compressible enough, ZSTD_compressBlock() + * result will be zero. In which case, nothing is produced into `dst`. + * + User must test for such outcome and deal directly with uncompressed data + * + ZSTD_decompressBlock() doesn't accept uncompressed data as input!!! + * + In case of multiple successive blocks, decoder must be informed of + * uncompressed block existence to follow proper history. Use + * ZSTD_insertBlock() in such a case. + ******************************************************************************/ + +/* Define for static allocation */ +#define ZSTD_BLOCKSIZE_ABSOLUTEMAX (128 * 1024) +/*===== Raw zstd block functions =====*/ +size_t ZSTD_getBlockSizeMax(ZSTD_CCtx *cctx); +size_t ZSTD_compressBlock(ZSTD_CCtx *cctx, void *dst, size_t dstCapacity, + const void *src, size_t srcSize); +size_t ZSTD_decompressBlock(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, + const void *src, size_t srcSize); +size_t ZSTD_insertBlock(ZSTD_DCtx *dctx, const void *blockStart, + size_t blockSize); + +#endif /* ZSTD_H */ diff --git a/include/sdhci.h b/include/sdhci.h index bef37df982e..eee493ab5f5 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -186,6 +186,7 @@ /* 55-57 reserved */ #define SDHCI_ADMA_ADDRESS 0x58 +#define SDHCI_ADMA_ADDRESS_HI 0x5c /* 60-FB reserved */ @@ -252,6 +253,38 @@ struct sdhci_ops { void (*set_delay)(struct sdhci_host *host); }; +#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA) +#define ADMA_MAX_LEN 65532 +#ifdef CONFIG_DMA_ADDR_T_64BIT +#define ADMA_DESC_LEN 16 +#else +#define ADMA_DESC_LEN 8 +#endif +#define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \ + MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN + +#define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN) + +/* Decriptor table defines */ +#define ADMA_DESC_ATTR_VALID BIT(0) +#define ADMA_DESC_ATTR_END BIT(1) +#define ADMA_DESC_ATTR_INT BIT(2) +#define ADMA_DESC_ATTR_ACT1 BIT(4) +#define ADMA_DESC_ATTR_ACT2 BIT(5) + +#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 +#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2) + +struct sdhci_adma_desc { + u8 attr; + u8 reserved; + u16 len; + u32 addr_lo; +#ifdef CONFIG_DMA_ADDR_T_64BIT + u32 addr_hi; +#endif +} __packed; +#endif struct sdhci_host { const char *name; void *ioaddr; @@ -272,6 +305,17 @@ struct sdhci_host { uint voltages; struct mmc_config cfg; + dma_addr_t start_addr; + int flags; +#define USE_SDMA (0x1 << 0) +#define USE_ADMA (0x1 << 1) +#define USE_ADMA64 (0x1 << 2) +#define USE_DMA (USE_SDMA | USE_ADMA | USE_ADMA64) + dma_addr_t adma_addr; +#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA) + struct sdhci_adma_desc *adma_desc_table; + uint desc_slot; +#endif }; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS diff --git a/lib/Kconfig b/lib/Kconfig index 05f82d4a502..416e63c1c73 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -327,6 +327,9 @@ config MD5 config CRC32C bool +config XXHASH + bool + endmenu menu "Compression Support" @@ -359,7 +362,7 @@ config LZO This enables support for LZO compression algorithm.r config GZIP - bool "Enable gzip decompression support for SPL build" + bool "Enable gzip decompression support" select ZLIB default y help @@ -371,6 +374,12 @@ config ZLIB help This enables ZLIB compression lib. +config ZSTD + bool "Enable Zstandard decompression support" + select XXHASH + help + This enables Zstandard decompression library. + config SPL_LZ4 bool "Enable LZ4 decompression support in SPL" help @@ -395,6 +404,12 @@ config SPL_ZLIB help This enables compression lib for SPL boot. +config SPL_ZSTD + bool "Enable Zstandard decompression support in SPL" + select XXHASH + help + This enables Zstandard decompression library in the SPL. + endmenu config ERRNO_STR diff --git a/lib/Makefile b/lib/Makefile index 47829bfed52..09c45b81229 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o obj-$(CONFIG_IMAGE_SPARSE) += image-sparse.o obj-y += ldiv.o obj-$(CONFIG_MD5) += md5.o +obj-$(CONFIG_XXHASH) += xxhash.o obj-y += net_utils.o obj-$(CONFIG_PHYSMEM) += physmem.o obj-y += rc4.o @@ -58,6 +59,7 @@ obj-$(CONFIG_SHA1) += sha1.o obj-$(CONFIG_SHA256) += sha256.o obj-$(CONFIG_$(SPL_)ZLIB) += zlib/ +obj-$(CONFIG_$(SPL_)ZSTD) += zstd/ obj-$(CONFIG_$(SPL_)GZIP) += gunzip.o obj-$(CONFIG_$(SPL_)LZO) += lzo/ obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o diff --git a/lib/display_options.c b/lib/display_options.c index af1802ef992..cff20f37552 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -23,7 +23,9 @@ char *display_options_get_banner_priv(bool newlines, const char *build_tag, build_tag); if (len > size - 3) len = size - 3; - strcpy(buf + len, "\n\n"); + if (len < 0) + len = 0; + snprintf(buf + len, size - len, "\n\n"); return buf; } diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c index 4ccba228757..7bf51874c1c 100644 --- a/lib/efi_loader/efi_bootmgr.c +++ b/lib/efi_loader/efi_bootmgr.c @@ -53,19 +53,20 @@ void efi_deserialize_load_option(struct efi_load_option *lo, u8 *data) */ unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8 **data) { - unsigned long label_len, option_len; + unsigned long label_len; unsigned long size; u8 *p; label_len = (u16_strlen(lo->label) + 1) * sizeof(u16); - option_len = strlen((char *)lo->optional_data); /* total size */ size = sizeof(lo->attributes); size += sizeof(lo->file_path_length); size += label_len; size += lo->file_path_length; - size += option_len + 1; + if (lo->optional_data) + size += (utf8_utf16_strlen((const char *)lo->optional_data) + + 1) * sizeof(u16); p = malloc(size); if (!p) return 0; @@ -84,10 +85,10 @@ unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8 **data) memcpy(p, lo->file_path, lo->file_path_length); p += lo->file_path_length; - memcpy(p, lo->optional_data, option_len); - p += option_len; - *(char *)p = '\0'; - + if (lo->optional_data) { + utf8_utf16_strcpy((u16 **)&p, (const char *)lo->optional_data); + p += sizeof(u16); /* size of trailing \0 */ + } return size; } diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 601b0a2cb88..e5c46e9f081 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -423,10 +423,12 @@ static efi_status_t EFIAPI efi_free_pool_ext(void *buffer) } /** - * efi_add_handle() - add a new object to the object list - * @obj: object to be added + * efi_add_handle() - add a new handle to the object list * - * The protocols list is initialized. The object handle is set. + * @handle: handle to be added + * + * The protocols list is initialized. The handle is added to the list of known + * UEFI objects. */ void efi_add_handle(efi_handle_t handle) { @@ -618,7 +620,7 @@ efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl, } if ((type & (EVT_NOTIFY_WAIT | EVT_NOTIFY_SIGNAL)) && - (is_valid_tpl(notify_tpl) != EFI_SUCCESS)) + (!notify_function || is_valid_tpl(notify_tpl) != EFI_SUCCESS)) return EFI_INVALID_PARAMETER; evt = calloc(1, sizeof(struct efi_event)); @@ -2626,6 +2628,9 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle, efi_is_direct_boot = false; + image_obj->exit_data_size = exit_data_size; + image_obj->exit_data = exit_data; + /* call the image! */ if (setjmp(&image_obj->exit_jmp)) { /* @@ -2670,6 +2675,41 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle, } /** + * efi_update_exit_data() - fill exit data parameters of StartImage() + * + * @image_obj image handle + * @exit_data_size size of the exit data buffer + * @exit_data buffer with data returned by UEFI payload + * Return: status code + */ +static efi_status_t efi_update_exit_data(struct efi_loaded_image_obj *image_obj, + efi_uintn_t exit_data_size, + u16 *exit_data) +{ + efi_status_t ret; + + /* + * If exit_data is not provided to StartImage(), exit_data_size must be + * ignored. + */ + if (!image_obj->exit_data) + return EFI_SUCCESS; + if (image_obj->exit_data_size) + *image_obj->exit_data_size = exit_data_size; + if (exit_data_size && exit_data) { + ret = efi_allocate_pool(EFI_BOOT_SERVICES_DATA, + exit_data_size, + (void **)image_obj->exit_data); + if (ret != EFI_SUCCESS) + return ret; + memcpy(*image_obj->exit_data, exit_data, exit_data_size); + } else { + image_obj->exit_data = NULL; + } + return EFI_SUCCESS; +} + +/** * efi_exit() - leave an EFI application or driver * @image_handle: handle of the application or driver that is exiting * @exit_status: status code @@ -2709,6 +2749,15 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle, if (ret != EFI_SUCCESS) goto out; + /* Exit data is only foreseen in case of failure. */ + if (exit_status != EFI_SUCCESS) { + ret = efi_update_exit_data(image_obj, exit_data_size, + exit_data); + /* Exiting has priority. Don't return error to caller. */ + if (ret != EFI_SUCCESS) + EFI_PRINT("%s: out of memory\n", __func__); + } + /* Make sure entry/exit counts for EFI world cross-overs match */ EFI_EXIT(exit_status); diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 987cc6dc5f6..776077cc35a 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -452,7 +452,7 @@ efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages) uint64_t r = 0; /* Sanity check */ - if (!memory || (memory & EFI_PAGE_MASK)) { + if (!memory || (memory & EFI_PAGE_MASK) || !pages) { printf("%s: illegal free 0x%llx, 0x%zx\n", __func__, memory, pages); return EFI_INVALID_PARAMETER; diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index b32a7b3f934..87db51cbb74 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -79,6 +79,7 @@ out: */ efi_status_t efi_init_obj_list(void) { + u64 os_indications_supported = 0; /* None */ efi_status_t ret = EFI_SUCCESS; /* Initialize once only */ @@ -90,6 +91,16 @@ efi_status_t efi_init_obj_list(void) if (ret != EFI_SUCCESS) goto out; + /* Indicate supported features */ + ret = EFI_CALL(efi_set_variable(L"OsIndicationsSupported", + &efi_global_variable_guid, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS, + sizeof(os_indications_supported), + &os_indications_supported)); + if (ret != EFI_SUCCESS) + goto out; + /* Initialize system table */ ret = efi_initialize_system_table(); if (ret != EFI_SUCCESS) diff --git a/lib/efi_selftest/efi_selftest_miniapp_exit.c b/lib/efi_selftest/efi_selftest_miniapp_exit.c index b3ca109d811..6b5cfb01cf7 100644 --- a/lib/efi_selftest/efi_selftest_miniapp_exit.c +++ b/lib/efi_selftest/efi_selftest_miniapp_exit.c @@ -9,7 +9,7 @@ */ #include <common.h> -#include <efi_api.h> +#include <efi_selftest.h> static efi_guid_t loaded_image_protocol_guid = EFI_LOADED_IMAGE_PROTOCOL_GUID; @@ -66,15 +66,22 @@ efi_status_t EFIAPI efi_main(efi_handle_t handle, struct efi_system_table *systable) { struct efi_simple_text_output_protocol *con_out = systable->con_out; - efi_status_t ret = EFI_UNSUPPORTED; + efi_status_t ret; + u16 text[] = EFI_ST_SUCCESS_STR; con_out->output_string(con_out, L"EFI application calling Exit\n"); - if (check_loaded_image_protocol(handle, systable) != EFI_SUCCESS) + if (check_loaded_image_protocol(handle, systable) != EFI_SUCCESS) { + con_out->output_string(con_out, + L"Loaded image protocol missing\n"); ret = EFI_NOT_FOUND; + goto out; + } - /* The return value is checked by the calling test */ - systable->boottime->exit(handle, ret, 0, NULL); + /* This return value is expected by the calling test */ + ret = EFI_UNSUPPORTED; +out: + systable->boottime->exit(handle, ret, sizeof(text), text); /* * This statement should not be reached. diff --git a/lib/efi_selftest/efi_selftest_startimage_exit.c b/lib/efi_selftest/efi_selftest_startimage_exit.c index fa4b7d4a9b6..96049dea868 100644 --- a/lib/efi_selftest/efi_selftest_startimage_exit.c +++ b/lib/efi_selftest/efi_selftest_startimage_exit.c @@ -123,6 +123,9 @@ static int execute(void) { efi_status_t ret; efi_handle_t handle; + efi_uintn_t exit_data_size = 0; + u16 *exit_data = NULL; + u16 expected_text[] = EFI_ST_SUCCESS_STR; ret = boottime->load_image(false, image_handle, NULL, image, img.length, &handle); @@ -130,11 +133,21 @@ static int execute(void) efi_st_error("Failed to load image\n"); return EFI_ST_FAILURE; } - ret = boottime->start_image(handle, NULL, NULL); + ret = boottime->start_image(handle, &exit_data_size, &exit_data); if (ret != EFI_UNSUPPORTED) { efi_st_error("Wrong return value from application\n"); return EFI_ST_FAILURE; } + if (!exit_data || exit_data_size != sizeof(expected_text) || + efi_st_memcmp(exit_data, expected_text, sizeof(expected_text))) { + efi_st_error("Incorrect exit data\n"); + return EFI_ST_FAILURE; + } + ret = boottime->free_pool(exit_data); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed to free exit data\n"); + return EFI_ST_FAILURE; + } return EFI_ST_SUCCESS; } diff --git a/lib/uuid.c b/lib/uuid.c index fa20ee39fc3..2d4d6ef7e46 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -238,6 +238,8 @@ void gen_rand_uuid(unsigned char *uuid_bin) unsigned int *ptr = (unsigned int *)&uuid; int i; + srand(get_ticks() + rand()); + /* Set all fields randomly */ for (i = 0; i < sizeof(struct uuid) / sizeof(*ptr); i++) *(ptr + i) = cpu_to_be32(rand()); diff --git a/lib/vsprintf.c b/lib/vsprintf.c index 2403825dc98..3502b8088ff 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -16,7 +16,6 @@ #include <efi_loader.h> #include <div64.h> #include <hexdump.h> -#include <uuid.h> #include <stdarg.h> #include <linux/ctype.h> #include <linux/err.h> diff --git a/lib/xxhash.c b/lib/xxhash.c new file mode 100644 index 00000000000..2fb4dc6d02b --- /dev/null +++ b/lib/xxhash.c @@ -0,0 +1,467 @@ +// SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause) +/* + * xxHash - Extremely Fast Hash algorithm + * Copyright (C) 2012-2016, Yann Collet. + * + * You can contact the author at: + * - xxHash homepage: http://cyan4973.github.io/xxHash/ + * - xxHash source repository: https://github.com/Cyan4973/xxHash + */ + +#include <asm/unaligned.h> +#include <linux/errno.h> +#include <linux/compiler.h> +#include <linux/kernel.h> +#include <linux/compat.h> +#include <linux/string.h> +#include <linux/xxhash.h> + +/*-************************************* + * Macros + **************************************/ +#define xxh_rotl32(x, r) ((x << r) | (x >> (32 - r))) +#define xxh_rotl64(x, r) ((x << r) | (x >> (64 - r))) + +#ifdef __LITTLE_ENDIAN +# define XXH_CPU_LITTLE_ENDIAN 1 +#else +# define XXH_CPU_LITTLE_ENDIAN 0 +#endif + +/*-************************************* + * Constants + **************************************/ +static const uint32_t PRIME32_1 = 2654435761U; +static const uint32_t PRIME32_2 = 2246822519U; +static const uint32_t PRIME32_3 = 3266489917U; +static const uint32_t PRIME32_4 = 668265263U; +static const uint32_t PRIME32_5 = 374761393U; + +static const uint64_t PRIME64_1 = 11400714785074694791ULL; +static const uint64_t PRIME64_2 = 14029467366897019727ULL; +static const uint64_t PRIME64_3 = 1609587929392839161ULL; +static const uint64_t PRIME64_4 = 9650029242287828579ULL; +static const uint64_t PRIME64_5 = 2870177450012600261ULL; + +/*-************************** + * Utils + ***************************/ +void xxh32_copy_state(struct xxh32_state *dst, const struct xxh32_state *src) +{ + memcpy(dst, src, sizeof(*dst)); +} +EXPORT_SYMBOL(xxh32_copy_state); + +void xxh64_copy_state(struct xxh64_state *dst, const struct xxh64_state *src) +{ + memcpy(dst, src, sizeof(*dst)); +} +EXPORT_SYMBOL(xxh64_copy_state); + +/*-*************************** + * Simple Hash Functions + ****************************/ +static uint32_t xxh32_round(uint32_t seed, const uint32_t input) +{ + seed += input * PRIME32_2; + seed = xxh_rotl32(seed, 13); + seed *= PRIME32_1; + return seed; +} + +uint32_t xxh32(const void *input, const size_t len, const uint32_t seed) +{ + const uint8_t *p = (const uint8_t *)input; + const uint8_t *b_end = p + len; + uint32_t h32; + + if (len >= 16) { + const uint8_t *const limit = b_end - 16; + uint32_t v1 = seed + PRIME32_1 + PRIME32_2; + uint32_t v2 = seed + PRIME32_2; + uint32_t v3 = seed + 0; + uint32_t v4 = seed - PRIME32_1; + + do { + v1 = xxh32_round(v1, get_unaligned_le32(p)); + p += 4; + v2 = xxh32_round(v2, get_unaligned_le32(p)); + p += 4; + v3 = xxh32_round(v3, get_unaligned_le32(p)); + p += 4; + v4 = xxh32_round(v4, get_unaligned_le32(p)); + p += 4; + } while (p <= limit); + + h32 = xxh_rotl32(v1, 1) + xxh_rotl32(v2, 7) + + xxh_rotl32(v3, 12) + xxh_rotl32(v4, 18); + } else { + h32 = seed + PRIME32_5; + } + + h32 += (uint32_t)len; + + while (p + 4 <= b_end) { + h32 += get_unaligned_le32(p) * PRIME32_3; + h32 = xxh_rotl32(h32, 17) * PRIME32_4; + p += 4; + } + + while (p < b_end) { + h32 += (*p) * PRIME32_5; + h32 = xxh_rotl32(h32, 11) * PRIME32_1; + p++; + } + + h32 ^= h32 >> 15; + h32 *= PRIME32_2; + h32 ^= h32 >> 13; + h32 *= PRIME32_3; + h32 ^= h32 >> 16; + + return h32; +} +EXPORT_SYMBOL(xxh32); + +static uint64_t xxh64_round(uint64_t acc, const uint64_t input) +{ + acc += input * PRIME64_2; + acc = xxh_rotl64(acc, 31); + acc *= PRIME64_1; + return acc; +} + +static uint64_t xxh64_merge_round(uint64_t acc, uint64_t val) +{ + val = xxh64_round(0, val); + acc ^= val; + acc = acc * PRIME64_1 + PRIME64_4; + return acc; +} + +uint64_t xxh64(const void *input, const size_t len, const uint64_t seed) +{ + const uint8_t *p = (const uint8_t *)input; + const uint8_t *const b_end = p + len; + uint64_t h64; + + if (len >= 32) { + const uint8_t *const limit = b_end - 32; + uint64_t v1 = seed + PRIME64_1 + PRIME64_2; + uint64_t v2 = seed + PRIME64_2; + uint64_t v3 = seed + 0; + uint64_t v4 = seed - PRIME64_1; + + do { + v1 = xxh64_round(v1, get_unaligned_le64(p)); + p += 8; + v2 = xxh64_round(v2, get_unaligned_le64(p)); + p += 8; + v3 = xxh64_round(v3, get_unaligned_le64(p)); + p += 8; + v4 = xxh64_round(v4, get_unaligned_le64(p)); + p += 8; + } while (p <= limit); + + h64 = xxh_rotl64(v1, 1) + xxh_rotl64(v2, 7) + + xxh_rotl64(v3, 12) + xxh_rotl64(v4, 18); + h64 = xxh64_merge_round(h64, v1); + h64 = xxh64_merge_round(h64, v2); + h64 = xxh64_merge_round(h64, v3); + h64 = xxh64_merge_round(h64, v4); + + } else { + h64 = seed + PRIME64_5; + } + + h64 += (uint64_t)len; + + while (p + 8 <= b_end) { + const uint64_t k1 = xxh64_round(0, get_unaligned_le64(p)); + + h64 ^= k1; + h64 = xxh_rotl64(h64, 27) * PRIME64_1 + PRIME64_4; + p += 8; + } + + if (p + 4 <= b_end) { + h64 ^= (uint64_t)(get_unaligned_le32(p)) * PRIME64_1; + h64 = xxh_rotl64(h64, 23) * PRIME64_2 + PRIME64_3; + p += 4; + } + + while (p < b_end) { + h64 ^= (*p) * PRIME64_5; + h64 = xxh_rotl64(h64, 11) * PRIME64_1; + p++; + } + + h64 ^= h64 >> 33; + h64 *= PRIME64_2; + h64 ^= h64 >> 29; + h64 *= PRIME64_3; + h64 ^= h64 >> 32; + + return h64; +} +EXPORT_SYMBOL(xxh64); + +/*-************************************************** + * Advanced Hash Functions + ***************************************************/ +void xxh32_reset(struct xxh32_state *statePtr, const uint32_t seed) +{ + /* use a local state for memcpy() to avoid strict-aliasing warnings */ + struct xxh32_state state; + + memset(&state, 0, sizeof(state)); + state.v1 = seed + PRIME32_1 + PRIME32_2; + state.v2 = seed + PRIME32_2; + state.v3 = seed + 0; + state.v4 = seed - PRIME32_1; + memcpy(statePtr, &state, sizeof(state)); +} +EXPORT_SYMBOL(xxh32_reset); + +void xxh64_reset(struct xxh64_state *statePtr, const uint64_t seed) +{ + /* use a local state for memcpy() to avoid strict-aliasing warnings */ + struct xxh64_state state; + + memset(&state, 0, sizeof(state)); + state.v1 = seed + PRIME64_1 + PRIME64_2; + state.v2 = seed + PRIME64_2; + state.v3 = seed + 0; + state.v4 = seed - PRIME64_1; + memcpy(statePtr, &state, sizeof(state)); +} +EXPORT_SYMBOL(xxh64_reset); + +int xxh32_update(struct xxh32_state *state, const void *input, const size_t len) +{ + const uint8_t *p = (const uint8_t *)input; + const uint8_t *const b_end = p + len; + + if (input == NULL) + return -EINVAL; + + state->total_len_32 += (uint32_t)len; + state->large_len |= (len >= 16) | (state->total_len_32 >= 16); + + if (state->memsize + len < 16) { /* fill in tmp buffer */ + memcpy((uint8_t *)(state->mem32) + state->memsize, input, len); + state->memsize += (uint32_t)len; + return 0; + } + + if (state->memsize) { /* some data left from previous update */ + const uint32_t *p32 = state->mem32; + + memcpy((uint8_t *)(state->mem32) + state->memsize, input, + 16 - state->memsize); + + state->v1 = xxh32_round(state->v1, get_unaligned_le32(p32)); + p32++; + state->v2 = xxh32_round(state->v2, get_unaligned_le32(p32)); + p32++; + state->v3 = xxh32_round(state->v3, get_unaligned_le32(p32)); + p32++; + state->v4 = xxh32_round(state->v4, get_unaligned_le32(p32)); + p32++; + + p += 16-state->memsize; + state->memsize = 0; + } + + if (p <= b_end - 16) { + const uint8_t *const limit = b_end - 16; + uint32_t v1 = state->v1; + uint32_t v2 = state->v2; + uint32_t v3 = state->v3; + uint32_t v4 = state->v4; + + do { + v1 = xxh32_round(v1, get_unaligned_le32(p)); + p += 4; + v2 = xxh32_round(v2, get_unaligned_le32(p)); + p += 4; + v3 = xxh32_round(v3, get_unaligned_le32(p)); + p += 4; + v4 = xxh32_round(v4, get_unaligned_le32(p)); + p += 4; + } while (p <= limit); + + state->v1 = v1; + state->v2 = v2; + state->v3 = v3; + state->v4 = v4; + } + + if (p < b_end) { + memcpy(state->mem32, p, (size_t)(b_end-p)); + state->memsize = (uint32_t)(b_end-p); + } + + return 0; +} +EXPORT_SYMBOL(xxh32_update); + +uint32_t xxh32_digest(const struct xxh32_state *state) +{ + const uint8_t *p = (const uint8_t *)state->mem32; + const uint8_t *const b_end = (const uint8_t *)(state->mem32) + + state->memsize; + uint32_t h32; + + if (state->large_len) { + h32 = xxh_rotl32(state->v1, 1) + xxh_rotl32(state->v2, 7) + + xxh_rotl32(state->v3, 12) + xxh_rotl32(state->v4, 18); + } else { + h32 = state->v3 /* == seed */ + PRIME32_5; + } + + h32 += state->total_len_32; + + while (p + 4 <= b_end) { + h32 += get_unaligned_le32(p) * PRIME32_3; + h32 = xxh_rotl32(h32, 17) * PRIME32_4; + p += 4; + } + + while (p < b_end) { + h32 += (*p) * PRIME32_5; + h32 = xxh_rotl32(h32, 11) * PRIME32_1; + p++; + } + + h32 ^= h32 >> 15; + h32 *= PRIME32_2; + h32 ^= h32 >> 13; + h32 *= PRIME32_3; + h32 ^= h32 >> 16; + + return h32; +} +EXPORT_SYMBOL(xxh32_digest); + +int xxh64_update(struct xxh64_state *state, const void *input, const size_t len) +{ + const uint8_t *p = (const uint8_t *)input; + const uint8_t *const b_end = p + len; + + if (input == NULL) + return -EINVAL; + + state->total_len += len; + + if (state->memsize + len < 32) { /* fill in tmp buffer */ + memcpy(((uint8_t *)state->mem64) + state->memsize, input, len); + state->memsize += (uint32_t)len; + return 0; + } + + if (state->memsize) { /* tmp buffer is full */ + uint64_t *p64 = state->mem64; + + memcpy(((uint8_t *)p64) + state->memsize, input, + 32 - state->memsize); + + state->v1 = xxh64_round(state->v1, get_unaligned_le64(p64)); + p64++; + state->v2 = xxh64_round(state->v2, get_unaligned_le64(p64)); + p64++; + state->v3 = xxh64_round(state->v3, get_unaligned_le64(p64)); + p64++; + state->v4 = xxh64_round(state->v4, get_unaligned_le64(p64)); + + p += 32 - state->memsize; + state->memsize = 0; + } + + if (p + 32 <= b_end) { + const uint8_t *const limit = b_end - 32; + uint64_t v1 = state->v1; + uint64_t v2 = state->v2; + uint64_t v3 = state->v3; + uint64_t v4 = state->v4; + + do { + v1 = xxh64_round(v1, get_unaligned_le64(p)); + p += 8; + v2 = xxh64_round(v2, get_unaligned_le64(p)); + p += 8; + v3 = xxh64_round(v3, get_unaligned_le64(p)); + p += 8; + v4 = xxh64_round(v4, get_unaligned_le64(p)); + p += 8; + } while (p <= limit); + + state->v1 = v1; + state->v2 = v2; + state->v3 = v3; + state->v4 = v4; + } + + if (p < b_end) { + memcpy(state->mem64, p, (size_t)(b_end-p)); + state->memsize = (uint32_t)(b_end - p); + } + + return 0; +} +EXPORT_SYMBOL(xxh64_update); + +uint64_t xxh64_digest(const struct xxh64_state *state) +{ + const uint8_t *p = (const uint8_t *)state->mem64; + const uint8_t *const b_end = (const uint8_t *)state->mem64 + + state->memsize; + uint64_t h64; + + if (state->total_len >= 32) { + const uint64_t v1 = state->v1; + const uint64_t v2 = state->v2; + const uint64_t v3 = state->v3; + const uint64_t v4 = state->v4; + + h64 = xxh_rotl64(v1, 1) + xxh_rotl64(v2, 7) + + xxh_rotl64(v3, 12) + xxh_rotl64(v4, 18); + h64 = xxh64_merge_round(h64, v1); + h64 = xxh64_merge_round(h64, v2); + h64 = xxh64_merge_round(h64, v3); + h64 = xxh64_merge_round(h64, v4); + } else { + h64 = state->v3 + PRIME64_5; + } + + h64 += (uint64_t)state->total_len; + + while (p + 8 <= b_end) { + const uint64_t k1 = xxh64_round(0, get_unaligned_le64(p)); + + h64 ^= k1; + h64 = xxh_rotl64(h64, 27) * PRIME64_1 + PRIME64_4; + p += 8; + } + + if (p + 4 <= b_end) { + h64 ^= (uint64_t)(get_unaligned_le32(p)) * PRIME64_1; + h64 = xxh_rotl64(h64, 23) * PRIME64_2 + PRIME64_3; + p += 4; + } + + while (p < b_end) { + h64 ^= (*p) * PRIME64_5; + h64 = xxh_rotl64(h64, 11) * PRIME64_1; + p++; + } + + h64 ^= h64 >> 33; + h64 *= PRIME64_2; + h64 ^= h64 >> 29; + h64 *= PRIME64_3; + h64 ^= h64 >> 32; + + return h64; +} +EXPORT_SYMBOL(xxh64_digest); diff --git a/lib/zstd/Makefile b/lib/zstd/Makefile new file mode 100644 index 00000000000..33c1df48ec8 --- /dev/null +++ b/lib/zstd/Makefile @@ -0,0 +1,4 @@ +obj-y += zstd_decompress.o + +zstd_decompress-y := huf_decompress.o decompress.o \ + entropy_common.o fse_decompress.o zstd_common.o diff --git a/lib/zstd/bitstream.h b/lib/zstd/bitstream.h new file mode 100644 index 00000000000..73aacc97f49 --- /dev/null +++ b/lib/zstd/bitstream.h @@ -0,0 +1,344 @@ +/* SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause) */ +/* + * bitstream + * Part of FSE library + * header file (to include) + * Copyright (C) 2013-2016, Yann Collet. + * + * You can contact the author at : + * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy + */ +#ifndef BITSTREAM_H_MODULE +#define BITSTREAM_H_MODULE + +/* +* This API consists of small unitary functions, which must be inlined for best performance. +* Since link-time-optimization is not available for all compilers, +* these functions are defined into a .h to be included. +*/ + +/*-**************************************** +* Dependencies +******************************************/ +#include "error_private.h" /* error codes and messages */ +#include "mem.h" /* unaligned access routines */ + +/*========================================= +* Target specific +=========================================*/ +#define STREAM_ACCUMULATOR_MIN_32 25 +#define STREAM_ACCUMULATOR_MIN_64 57 +#define STREAM_ACCUMULATOR_MIN ((U32)(ZSTD_32bits() ? STREAM_ACCUMULATOR_MIN_32 : STREAM_ACCUMULATOR_MIN_64)) + +/*-****************************************** +* bitStream encoding API (write forward) +********************************************/ +/* bitStream can mix input from multiple sources. +* A critical property of these streams is that they encode and decode in **reverse** direction. +* So the first bit sequence you add will be the last to be read, like a LIFO stack. +*/ +typedef struct { + size_t bitContainer; + int bitPos; + char *startPtr; + char *ptr; + char *endPtr; +} BIT_CStream_t; + +ZSTD_STATIC size_t BIT_initCStream(BIT_CStream_t *bitC, void *dstBuffer, size_t dstCapacity); +ZSTD_STATIC void BIT_addBits(BIT_CStream_t *bitC, size_t value, unsigned nbBits); +ZSTD_STATIC void BIT_flushBits(BIT_CStream_t *bitC); +ZSTD_STATIC size_t BIT_closeCStream(BIT_CStream_t *bitC); + +/* Start with initCStream, providing the size of buffer to write into. +* bitStream will never write outside of this buffer. +* `dstCapacity` must be >= sizeof(bitD->bitContainer), otherwise @return will be an error code. +* +* bits are first added to a local register. +* Local register is size_t, hence 64-bits on 64-bits systems, or 32-bits on 32-bits systems. +* Writing data into memory is an explicit operation, performed by the flushBits function. +* Hence keep track how many bits are potentially stored into local register to avoid register overflow. +* After a flushBits, a maximum of 7 bits might still be stored into local register. +* +* Avoid storing elements of more than 24 bits if you want compatibility with 32-bits bitstream readers. +* +* Last operation is to close the bitStream. +* The function returns the final size of CStream in bytes. +* If data couldn't fit into `dstBuffer`, it will return a 0 ( == not storable) +*/ + +/*-******************************************** +* bitStream decoding API (read backward) +**********************************************/ +typedef struct { + size_t bitContainer; + unsigned bitsConsumed; + const char *ptr; + const char *start; +} BIT_DStream_t; + +typedef enum { + BIT_DStream_unfinished = 0, + BIT_DStream_endOfBuffer = 1, + BIT_DStream_completed = 2, + BIT_DStream_overflow = 3 +} BIT_DStream_status; /* result of BIT_reloadDStream() */ +/* 1,2,4,8 would be better for bitmap combinations, but slows down performance a bit ... :( */ + +ZSTD_STATIC size_t BIT_initDStream(BIT_DStream_t *bitD, const void *srcBuffer, size_t srcSize); +ZSTD_STATIC size_t BIT_readBits(BIT_DStream_t *bitD, unsigned nbBits); +ZSTD_STATIC BIT_DStream_status BIT_reloadDStream(BIT_DStream_t *bitD); +ZSTD_STATIC unsigned BIT_endOfDStream(const BIT_DStream_t *bitD); + +/* Start by invoking BIT_initDStream(). +* A chunk of the bitStream is then stored into a local register. +* Local register size is 64-bits on 64-bits systems, 32-bits on 32-bits systems (size_t). +* You can then retrieve bitFields stored into the local register, **in reverse order**. +* Local register is explicitly reloaded from memory by the BIT_reloadDStream() method. +* A reload guarantee a minimum of ((8*sizeof(bitD->bitContainer))-7) bits when its result is BIT_DStream_unfinished. +* Otherwise, it can be less than that, so proceed accordingly. +* Checking if DStream has reached its end can be performed with BIT_endOfDStream(). +*/ + +/*-**************************************** +* unsafe API +******************************************/ +ZSTD_STATIC void BIT_addBitsFast(BIT_CStream_t *bitC, size_t value, unsigned nbBits); +/* faster, but works only if value is "clean", meaning all high bits above nbBits are 0 */ + +ZSTD_STATIC void BIT_flushBitsFast(BIT_CStream_t *bitC); +/* unsafe version; does not check buffer overflow */ + +ZSTD_STATIC size_t BIT_readBitsFast(BIT_DStream_t *bitD, unsigned nbBits); +/* faster, but works only if nbBits >= 1 */ + +/*-************************************************************** +* Internal functions +****************************************************************/ +ZSTD_STATIC unsigned BIT_highbit32(register U32 val) { return 31 - __builtin_clz(val); } + +/*===== Local Constants =====*/ +static const unsigned BIT_mask[] = {0, 1, 3, 7, 0xF, 0x1F, 0x3F, 0x7F, 0xFF, + 0x1FF, 0x3FF, 0x7FF, 0xFFF, 0x1FFF, 0x3FFF, 0x7FFF, 0xFFFF, 0x1FFFF, + 0x3FFFF, 0x7FFFF, 0xFFFFF, 0x1FFFFF, 0x3FFFFF, 0x7FFFFF, 0xFFFFFF, 0x1FFFFFF, 0x3FFFFFF}; /* up to 26 bits */ + +/*-************************************************************** +* bitStream encoding +****************************************************************/ +/*! BIT_initCStream() : + * `dstCapacity` must be > sizeof(void*) + * @return : 0 if success, + otherwise an error code (can be tested using ERR_isError() ) */ +ZSTD_STATIC size_t BIT_initCStream(BIT_CStream_t *bitC, void *startPtr, size_t dstCapacity) +{ + bitC->bitContainer = 0; + bitC->bitPos = 0; + bitC->startPtr = (char *)startPtr; + bitC->ptr = bitC->startPtr; + bitC->endPtr = bitC->startPtr + dstCapacity - sizeof(bitC->ptr); + if (dstCapacity <= sizeof(bitC->ptr)) + return ERROR(dstSize_tooSmall); + return 0; +} + +/*! BIT_addBits() : + can add up to 26 bits into `bitC`. + Does not check for register overflow ! */ +ZSTD_STATIC void BIT_addBits(BIT_CStream_t *bitC, size_t value, unsigned nbBits) +{ + bitC->bitContainer |= (value & BIT_mask[nbBits]) << bitC->bitPos; + bitC->bitPos += nbBits; +} + +/*! BIT_addBitsFast() : + * works only if `value` is _clean_, meaning all high bits above nbBits are 0 */ +ZSTD_STATIC void BIT_addBitsFast(BIT_CStream_t *bitC, size_t value, unsigned nbBits) +{ + bitC->bitContainer |= value << bitC->bitPos; + bitC->bitPos += nbBits; +} + +/*! BIT_flushBitsFast() : + * unsafe version; does not check buffer overflow */ +ZSTD_STATIC void BIT_flushBitsFast(BIT_CStream_t *bitC) +{ + size_t const nbBytes = bitC->bitPos >> 3; + ZSTD_writeLEST(bitC->ptr, bitC->bitContainer); + bitC->ptr += nbBytes; + bitC->bitPos &= 7; + bitC->bitContainer >>= nbBytes * 8; /* if bitPos >= sizeof(bitContainer)*8 --> undefined behavior */ +} + +/*! BIT_flushBits() : + * safe version; check for buffer overflow, and prevents it. + * note : does not signal buffer overflow. This will be revealed later on using BIT_closeCStream() */ +ZSTD_STATIC void BIT_flushBits(BIT_CStream_t *bitC) +{ + size_t const nbBytes = bitC->bitPos >> 3; + ZSTD_writeLEST(bitC->ptr, bitC->bitContainer); + bitC->ptr += nbBytes; + if (bitC->ptr > bitC->endPtr) + bitC->ptr = bitC->endPtr; + bitC->bitPos &= 7; + bitC->bitContainer >>= nbBytes * 8; /* if bitPos >= sizeof(bitContainer)*8 --> undefined behavior */ +} + +/*! BIT_closeCStream() : + * @return : size of CStream, in bytes, + or 0 if it could not fit into dstBuffer */ +ZSTD_STATIC size_t BIT_closeCStream(BIT_CStream_t *bitC) +{ + BIT_addBitsFast(bitC, 1, 1); /* endMark */ + BIT_flushBits(bitC); + + if (bitC->ptr >= bitC->endPtr) + return 0; /* doesn't fit within authorized budget : cancel */ + + return (bitC->ptr - bitC->startPtr) + (bitC->bitPos > 0); +} + +/*-******************************************************** +* bitStream decoding +**********************************************************/ +/*! BIT_initDStream() : +* Initialize a BIT_DStream_t. +* `bitD` : a pointer to an already allocated BIT_DStream_t structure. +* `srcSize` must be the *exact* size of the bitStream, in bytes. +* @return : size of stream (== srcSize) or an errorCode if a problem is detected +*/ +ZSTD_STATIC size_t BIT_initDStream(BIT_DStream_t *bitD, const void *srcBuffer, size_t srcSize) +{ + if (srcSize < 1) { + memset(bitD, 0, sizeof(*bitD)); + return ERROR(srcSize_wrong); + } + + if (srcSize >= sizeof(bitD->bitContainer)) { /* normal case */ + bitD->start = (const char *)srcBuffer; + bitD->ptr = (const char *)srcBuffer + srcSize - sizeof(bitD->bitContainer); + bitD->bitContainer = ZSTD_readLEST(bitD->ptr); + { + BYTE const lastByte = ((const BYTE *)srcBuffer)[srcSize - 1]; + bitD->bitsConsumed = lastByte ? 8 - BIT_highbit32(lastByte) : 0; /* ensures bitsConsumed is always set */ + if (lastByte == 0) + return ERROR(GENERIC); /* endMark not present */ + } + } else { + bitD->start = (const char *)srcBuffer; + bitD->ptr = bitD->start; + bitD->bitContainer = *(const BYTE *)(bitD->start); + switch (srcSize) { + case 7: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[6]) << (sizeof(bitD->bitContainer) * 8 - 16); + case 6: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[5]) << (sizeof(bitD->bitContainer) * 8 - 24); + case 5: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[4]) << (sizeof(bitD->bitContainer) * 8 - 32); + case 4: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[3]) << 24; + case 3: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[2]) << 16; + case 2: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[1]) << 8; + default:; + } + { + BYTE const lastByte = ((const BYTE *)srcBuffer)[srcSize - 1]; + bitD->bitsConsumed = lastByte ? 8 - BIT_highbit32(lastByte) : 0; + if (lastByte == 0) + return ERROR(GENERIC); /* endMark not present */ + } + bitD->bitsConsumed += (U32)(sizeof(bitD->bitContainer) - srcSize) * 8; + } + + return srcSize; +} + +ZSTD_STATIC size_t BIT_getUpperBits(size_t bitContainer, U32 const start) { return bitContainer >> start; } + +ZSTD_STATIC size_t BIT_getMiddleBits(size_t bitContainer, U32 const start, U32 const nbBits) { return (bitContainer >> start) & BIT_mask[nbBits]; } + +ZSTD_STATIC size_t BIT_getLowerBits(size_t bitContainer, U32 const nbBits) { return bitContainer & BIT_mask[nbBits]; } + +/*! BIT_lookBits() : + * Provides next n bits from local register. + * local register is not modified. + * On 32-bits, maxNbBits==24. + * On 64-bits, maxNbBits==56. + * @return : value extracted + */ +ZSTD_STATIC size_t BIT_lookBits(const BIT_DStream_t *bitD, U32 nbBits) +{ + U32 const bitMask = sizeof(bitD->bitContainer) * 8 - 1; + return ((bitD->bitContainer << (bitD->bitsConsumed & bitMask)) >> 1) >> ((bitMask - nbBits) & bitMask); +} + +/*! BIT_lookBitsFast() : +* unsafe version; only works only if nbBits >= 1 */ +ZSTD_STATIC size_t BIT_lookBitsFast(const BIT_DStream_t *bitD, U32 nbBits) +{ + U32 const bitMask = sizeof(bitD->bitContainer) * 8 - 1; + return (bitD->bitContainer << (bitD->bitsConsumed & bitMask)) >> (((bitMask + 1) - nbBits) & bitMask); +} + +ZSTD_STATIC void BIT_skipBits(BIT_DStream_t *bitD, U32 nbBits) { bitD->bitsConsumed += nbBits; } + +/*! BIT_readBits() : + * Read (consume) next n bits from local register and update. + * Pay attention to not read more than nbBits contained into local register. + * @return : extracted value. + */ +ZSTD_STATIC size_t BIT_readBits(BIT_DStream_t *bitD, U32 nbBits) +{ + size_t const value = BIT_lookBits(bitD, nbBits); + BIT_skipBits(bitD, nbBits); + return value; +} + +/*! BIT_readBitsFast() : +* unsafe version; only works only if nbBits >= 1 */ +ZSTD_STATIC size_t BIT_readBitsFast(BIT_DStream_t *bitD, U32 nbBits) +{ + size_t const value = BIT_lookBitsFast(bitD, nbBits); + BIT_skipBits(bitD, nbBits); + return value; +} + +/*! BIT_reloadDStream() : +* Refill `bitD` from buffer previously set in BIT_initDStream() . +* This function is safe, it guarantees it will not read beyond src buffer. +* @return : status of `BIT_DStream_t` internal register. + if status == BIT_DStream_unfinished, internal register is filled with >= (sizeof(bitD->bitContainer)*8 - 7) bits */ +ZSTD_STATIC BIT_DStream_status BIT_reloadDStream(BIT_DStream_t *bitD) +{ + if (bitD->bitsConsumed > (sizeof(bitD->bitContainer) * 8)) /* should not happen => corruption detected */ + return BIT_DStream_overflow; + + if (bitD->ptr >= bitD->start + sizeof(bitD->bitContainer)) { + bitD->ptr -= bitD->bitsConsumed >> 3; + bitD->bitsConsumed &= 7; + bitD->bitContainer = ZSTD_readLEST(bitD->ptr); + return BIT_DStream_unfinished; + } + if (bitD->ptr == bitD->start) { + if (bitD->bitsConsumed < sizeof(bitD->bitContainer) * 8) + return BIT_DStream_endOfBuffer; + return BIT_DStream_completed; + } + { + U32 nbBytes = bitD->bitsConsumed >> 3; + BIT_DStream_status result = BIT_DStream_unfinished; + if (bitD->ptr - nbBytes < bitD->start) { + nbBytes = (U32)(bitD->ptr - bitD->start); /* ptr > start */ + result = BIT_DStream_endOfBuffer; + } + bitD->ptr -= nbBytes; + bitD->bitsConsumed -= nbBytes * 8; + bitD->bitContainer = ZSTD_readLEST(bitD->ptr); /* reminder : srcSize > sizeof(bitD) */ + return result; + } +} + +/*! BIT_endOfDStream() : +* @return Tells if DStream has exactly reached its end (all bits consumed). +*/ +ZSTD_STATIC unsigned BIT_endOfDStream(const BIT_DStream_t *DStream) +{ + return ((DStream->ptr == DStream->start) && (DStream->bitsConsumed == sizeof(DStream->bitContainer) * 8)); +} + +#endif /* BITSTREAM_H_MODULE */ diff --git a/lib/zstd/decompress.c b/lib/zstd/decompress.c new file mode 100644 index 00000000000..ac5ab528bb1 --- /dev/null +++ b/lib/zstd/decompress.c @@ -0,0 +1,2515 @@ +// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause-Clear) +/** + * Copyright (c) 2016-present, Yann Collet, Facebook, Inc. + * All rights reserved. + */ + +/* *************************************************************** +* Tuning parameters +*****************************************************************/ +/*! +* MAXWINDOWSIZE_DEFAULT : +* maximum window size accepted by DStream, by default. +* Frames requiring more memory will be rejected. +*/ +#ifndef ZSTD_MAXWINDOWSIZE_DEFAULT +#define ZSTD_MAXWINDOWSIZE_DEFAULT ((1 << ZSTD_WINDOWLOG_MAX) + 1) /* defined within zstd.h */ +#endif + +/*-******************************************************* +* Dependencies +*********************************************************/ +#include "fse.h" +#include "huf.h" +#include "mem.h" /* low level memory routines */ +#include "zstd_internal.h" +#include <linux/kernel.h> +#include <linux/compat.h> +#include <linux/string.h> /* memcpy, memmove, memset */ + +#define ZSTD_PREFETCH(ptr) __builtin_prefetch(ptr, 0, 0) + +/*-************************************* +* Macros +***************************************/ +#define ZSTD_isError ERR_isError /* for inlining */ +#define FSE_isError ERR_isError +#define HUF_isError ERR_isError + +/*_******************************************************* +* Memory operations +**********************************************************/ +static void ZSTD_copy4(void *dst, const void *src) { memcpy(dst, src, 4); } + +/*-************************************************************* +* Context management +***************************************************************/ +typedef enum { + ZSTDds_getFrameHeaderSize, + ZSTDds_decodeFrameHeader, + ZSTDds_decodeBlockHeader, + ZSTDds_decompressBlock, + ZSTDds_decompressLastBlock, + ZSTDds_checkChecksum, + ZSTDds_decodeSkippableHeader, + ZSTDds_skipFrame +} ZSTD_dStage; + +typedef struct { + FSE_DTable LLTable[FSE_DTABLE_SIZE_U32(LLFSELog)]; + FSE_DTable OFTable[FSE_DTABLE_SIZE_U32(OffFSELog)]; + FSE_DTable MLTable[FSE_DTABLE_SIZE_U32(MLFSELog)]; + HUF_DTable hufTable[HUF_DTABLE_SIZE(HufLog)]; /* can accommodate HUF_decompress4X */ + U64 workspace[HUF_DECOMPRESS_WORKSPACE_SIZE_U32 / 2]; + U32 rep[ZSTD_REP_NUM]; +} ZSTD_entropyTables_t; + +struct ZSTD_DCtx_s { + const FSE_DTable *LLTptr; + const FSE_DTable *MLTptr; + const FSE_DTable *OFTptr; + const HUF_DTable *HUFptr; + ZSTD_entropyTables_t entropy; + const void *previousDstEnd; /* detect continuity */ + const void *base; /* start of curr segment */ + const void *vBase; /* virtual start of previous segment if it was just before curr one */ + const void *dictEnd; /* end of previous segment */ + size_t expected; + ZSTD_frameParams fParams; + blockType_e bType; /* used in ZSTD_decompressContinue(), to transfer blockType between header decoding and block decoding stages */ + ZSTD_dStage stage; + U32 litEntropy; + U32 fseEntropy; + struct xxh64_state xxhState; + size_t headerSize; + U32 dictID; + const BYTE *litPtr; + ZSTD_customMem customMem; + size_t litSize; + size_t rleSize; + BYTE litBuffer[ZSTD_BLOCKSIZE_ABSOLUTEMAX + WILDCOPY_OVERLENGTH]; + BYTE headerBuffer[ZSTD_FRAMEHEADERSIZE_MAX]; +}; /* typedef'd to ZSTD_DCtx within "zstd.h" */ + +size_t ZSTD_DCtxWorkspaceBound(void) { return ZSTD_ALIGN(sizeof(ZSTD_stack)) + ZSTD_ALIGN(sizeof(ZSTD_DCtx)); } + +size_t ZSTD_decompressBegin(ZSTD_DCtx *dctx) +{ + dctx->expected = ZSTD_frameHeaderSize_prefix; + dctx->stage = ZSTDds_getFrameHeaderSize; + dctx->previousDstEnd = NULL; + dctx->base = NULL; + dctx->vBase = NULL; + dctx->dictEnd = NULL; + dctx->entropy.hufTable[0] = (HUF_DTable)((HufLog)*0x1000001); /* cover both little and big endian */ + dctx->litEntropy = dctx->fseEntropy = 0; + dctx->dictID = 0; + ZSTD_STATIC_ASSERT(sizeof(dctx->entropy.rep) == sizeof(repStartValue)); + memcpy(dctx->entropy.rep, repStartValue, sizeof(repStartValue)); /* initial repcodes */ + dctx->LLTptr = dctx->entropy.LLTable; + dctx->MLTptr = dctx->entropy.MLTable; + dctx->OFTptr = dctx->entropy.OFTable; + dctx->HUFptr = dctx->entropy.hufTable; + return 0; +} + +ZSTD_DCtx *ZSTD_createDCtx_advanced(ZSTD_customMem customMem) +{ + ZSTD_DCtx *dctx; + + if (!customMem.customAlloc || !customMem.customFree) + return NULL; + + dctx = (ZSTD_DCtx *)ZSTD_malloc(sizeof(ZSTD_DCtx), customMem); + if (!dctx) + return NULL; + memcpy(&dctx->customMem, &customMem, sizeof(customMem)); + ZSTD_decompressBegin(dctx); + return dctx; +} + +ZSTD_DCtx *ZSTD_initDCtx(void *workspace, size_t workspaceSize) +{ + ZSTD_customMem const stackMem = ZSTD_initStack(workspace, workspaceSize); + return ZSTD_createDCtx_advanced(stackMem); +} + +size_t ZSTD_freeDCtx(ZSTD_DCtx *dctx) +{ + if (dctx == NULL) + return 0; /* support free on NULL */ + ZSTD_free(dctx, dctx->customMem); + return 0; /* reserved as a potential error code in the future */ +} + +void ZSTD_copyDCtx(ZSTD_DCtx *dstDCtx, const ZSTD_DCtx *srcDCtx) +{ + size_t const workSpaceSize = (ZSTD_BLOCKSIZE_ABSOLUTEMAX + WILDCOPY_OVERLENGTH) + ZSTD_frameHeaderSize_max; + memcpy(dstDCtx, srcDCtx, sizeof(ZSTD_DCtx) - workSpaceSize); /* no need to copy workspace */ +} + +static void ZSTD_refDDict(ZSTD_DCtx *dstDCtx, const ZSTD_DDict *ddict); + +/*-************************************************************* +* Decompression section +***************************************************************/ + +/*! ZSTD_isFrame() : + * Tells if the content of `buffer` starts with a valid Frame Identifier. + * Note : Frame Identifier is 4 bytes. If `size < 4`, @return will always be 0. + * Note 2 : Legacy Frame Identifiers are considered valid only if Legacy Support is enabled. + * Note 3 : Skippable Frame Identifiers are considered valid. */ +unsigned ZSTD_isFrame(const void *buffer, size_t size) +{ + if (size < 4) + return 0; + { + U32 const magic = ZSTD_readLE32(buffer); + if (magic == ZSTD_MAGICNUMBER) + return 1; + if ((magic & 0xFFFFFFF0U) == ZSTD_MAGIC_SKIPPABLE_START) + return 1; + } + return 0; +} + +/** ZSTD_frameHeaderSize() : +* srcSize must be >= ZSTD_frameHeaderSize_prefix. +* @return : size of the Frame Header */ +static size_t ZSTD_frameHeaderSize(const void *src, size_t srcSize) +{ + if (srcSize < ZSTD_frameHeaderSize_prefix) + return ERROR(srcSize_wrong); + { + BYTE const fhd = ((const BYTE *)src)[4]; + U32 const dictID = fhd & 3; + U32 const singleSegment = (fhd >> 5) & 1; + U32 const fcsId = fhd >> 6; + return ZSTD_frameHeaderSize_prefix + !singleSegment + ZSTD_did_fieldSize[dictID] + ZSTD_fcs_fieldSize[fcsId] + (singleSegment && !fcsId); + } +} + +/** ZSTD_getFrameParams() : +* decode Frame Header, or require larger `srcSize`. +* @return : 0, `fparamsPtr` is correctly filled, +* >0, `srcSize` is too small, result is expected `srcSize`, +* or an error code, which can be tested using ZSTD_isError() */ +size_t ZSTD_getFrameParams(ZSTD_frameParams *fparamsPtr, const void *src, size_t srcSize) +{ + const BYTE *ip = (const BYTE *)src; + + if (srcSize < ZSTD_frameHeaderSize_prefix) + return ZSTD_frameHeaderSize_prefix; + if (ZSTD_readLE32(src) != ZSTD_MAGICNUMBER) { + if ((ZSTD_readLE32(src) & 0xFFFFFFF0U) == ZSTD_MAGIC_SKIPPABLE_START) { + if (srcSize < ZSTD_skippableHeaderSize) + return ZSTD_skippableHeaderSize; /* magic number + skippable frame length */ + memset(fparamsPtr, 0, sizeof(*fparamsPtr)); + fparamsPtr->frameContentSize = ZSTD_readLE32((const char *)src + 4); + fparamsPtr->windowSize = 0; /* windowSize==0 means a frame is skippable */ + return 0; + } + return ERROR(prefix_unknown); + } + + /* ensure there is enough `srcSize` to fully read/decode frame header */ + { + size_t const fhsize = ZSTD_frameHeaderSize(src, srcSize); + if (srcSize < fhsize) + return fhsize; + } + + { + BYTE const fhdByte = ip[4]; + size_t pos = 5; + U32 const dictIDSizeCode = fhdByte & 3; + U32 const checksumFlag = (fhdByte >> 2) & 1; + U32 const singleSegment = (fhdByte >> 5) & 1; + U32 const fcsID = fhdByte >> 6; + U32 const windowSizeMax = 1U << ZSTD_WINDOWLOG_MAX; + U32 windowSize = 0; + U32 dictID = 0; + U64 frameContentSize = 0; + if ((fhdByte & 0x08) != 0) + return ERROR(frameParameter_unsupported); /* reserved bits, which must be zero */ + if (!singleSegment) { + BYTE const wlByte = ip[pos++]; + U32 const windowLog = (wlByte >> 3) + ZSTD_WINDOWLOG_ABSOLUTEMIN; + if (windowLog > ZSTD_WINDOWLOG_MAX) + return ERROR(frameParameter_windowTooLarge); /* avoids issue with 1 << windowLog */ + windowSize = (1U << windowLog); + windowSize += (windowSize >> 3) * (wlByte & 7); + } + + switch (dictIDSizeCode) { + default: /* impossible */ + case 0: break; + case 1: + dictID = ip[pos]; + pos++; + break; + case 2: + dictID = ZSTD_readLE16(ip + pos); + pos += 2; + break; + case 3: + dictID = ZSTD_readLE32(ip + pos); + pos += 4; + break; + } + switch (fcsID) { + default: /* impossible */ + case 0: + if (singleSegment) + frameContentSize = ip[pos]; + break; + case 1: frameContentSize = ZSTD_readLE16(ip + pos) + 256; break; + case 2: frameContentSize = ZSTD_readLE32(ip + pos); break; + case 3: frameContentSize = ZSTD_readLE64(ip + pos); break; + } + if (!windowSize) + windowSize = (U32)frameContentSize; + if (windowSize > windowSizeMax) + return ERROR(frameParameter_windowTooLarge); + fparamsPtr->frameContentSize = frameContentSize; + fparamsPtr->windowSize = windowSize; + fparamsPtr->dictID = dictID; + fparamsPtr->checksumFlag = checksumFlag; + } + return 0; +} + +/** ZSTD_getFrameContentSize() : +* compatible with legacy mode +* @return : decompressed size of the single frame pointed to be `src` if known, otherwise +* - ZSTD_CONTENTSIZE_UNKNOWN if the size cannot be determined +* - ZSTD_CONTENTSIZE_ERROR if an error occurred (e.g. invalid magic number, srcSize too small) */ +unsigned long long ZSTD_getFrameContentSize(const void *src, size_t srcSize) +{ + { + ZSTD_frameParams fParams; + if (ZSTD_getFrameParams(&fParams, src, srcSize) != 0) + return ZSTD_CONTENTSIZE_ERROR; + if (fParams.windowSize == 0) { + /* Either skippable or empty frame, size == 0 either way */ + return 0; + } else if (fParams.frameContentSize != 0) { + return fParams.frameContentSize; + } else { + return ZSTD_CONTENTSIZE_UNKNOWN; + } + } +} + +/** ZSTD_findDecompressedSize() : + * compatible with legacy mode + * `srcSize` must be the exact length of some number of ZSTD compressed and/or + * skippable frames + * @return : decompressed size of the frames contained */ +unsigned long long ZSTD_findDecompressedSize(const void *src, size_t srcSize) +{ + { + unsigned long long totalDstSize = 0; + while (srcSize >= ZSTD_frameHeaderSize_prefix) { + const U32 magicNumber = ZSTD_readLE32(src); + + if ((magicNumber & 0xFFFFFFF0U) == ZSTD_MAGIC_SKIPPABLE_START) { + size_t skippableSize; + if (srcSize < ZSTD_skippableHeaderSize) + return ERROR(srcSize_wrong); + skippableSize = ZSTD_readLE32((const BYTE *)src + 4) + ZSTD_skippableHeaderSize; + if (srcSize < skippableSize) { + return ZSTD_CONTENTSIZE_ERROR; + } + + src = (const BYTE *)src + skippableSize; + srcSize -= skippableSize; + continue; + } + + { + unsigned long long const ret = ZSTD_getFrameContentSize(src, srcSize); + if (ret >= ZSTD_CONTENTSIZE_ERROR) + return ret; + + /* check for overflow */ + if (totalDstSize + ret < totalDstSize) + return ZSTD_CONTENTSIZE_ERROR; + totalDstSize += ret; + } + { + size_t const frameSrcSize = ZSTD_findFrameCompressedSize(src, srcSize); + if (ZSTD_isError(frameSrcSize)) { + return ZSTD_CONTENTSIZE_ERROR; + } + + src = (const BYTE *)src + frameSrcSize; + srcSize -= frameSrcSize; + } + } + + if (srcSize) { + return ZSTD_CONTENTSIZE_ERROR; + } + + return totalDstSize; + } +} + +/** ZSTD_decodeFrameHeader() : +* `headerSize` must be the size provided by ZSTD_frameHeaderSize(). +* @return : 0 if success, or an error code, which can be tested using ZSTD_isError() */ +static size_t ZSTD_decodeFrameHeader(ZSTD_DCtx *dctx, const void *src, size_t headerSize) +{ + size_t const result = ZSTD_getFrameParams(&(dctx->fParams), src, headerSize); + if (ZSTD_isError(result)) + return result; /* invalid header */ + if (result > 0) + return ERROR(srcSize_wrong); /* headerSize too small */ + if (dctx->fParams.dictID && (dctx->dictID != dctx->fParams.dictID)) + return ERROR(dictionary_wrong); + if (dctx->fParams.checksumFlag) + xxh64_reset(&dctx->xxhState, 0); + return 0; +} + +typedef struct { + blockType_e blockType; + U32 lastBlock; + U32 origSize; +} blockProperties_t; + +/*! ZSTD_getcBlockSize() : +* Provides the size of compressed block from block header `src` */ +size_t ZSTD_getcBlockSize(const void *src, size_t srcSize, blockProperties_t *bpPtr) +{ + if (srcSize < ZSTD_blockHeaderSize) + return ERROR(srcSize_wrong); + { + U32 const cBlockHeader = ZSTD_readLE24(src); + U32 const cSize = cBlockHeader >> 3; + bpPtr->lastBlock = cBlockHeader & 1; + bpPtr->blockType = (blockType_e)((cBlockHeader >> 1) & 3); + bpPtr->origSize = cSize; /* only useful for RLE */ + if (bpPtr->blockType == bt_rle) + return 1; + if (bpPtr->blockType == bt_reserved) + return ERROR(corruption_detected); + return cSize; + } +} + +static size_t ZSTD_copyRawBlock(void *dst, size_t dstCapacity, const void *src, size_t srcSize) +{ + if (srcSize > dstCapacity) + return ERROR(dstSize_tooSmall); + memcpy(dst, src, srcSize); + return srcSize; +} + +static size_t ZSTD_setRleBlock(void *dst, size_t dstCapacity, const void *src, size_t srcSize, size_t regenSize) +{ + if (srcSize != 1) + return ERROR(srcSize_wrong); + if (regenSize > dstCapacity) + return ERROR(dstSize_tooSmall); + memset(dst, *(const BYTE *)src, regenSize); + return regenSize; +} + +/*! ZSTD_decodeLiteralsBlock() : + @return : nb of bytes read from src (< srcSize ) */ +size_t ZSTD_decodeLiteralsBlock(ZSTD_DCtx *dctx, const void *src, size_t srcSize) /* note : srcSize < BLOCKSIZE */ +{ + if (srcSize < MIN_CBLOCK_SIZE) + return ERROR(corruption_detected); + + { + const BYTE *const istart = (const BYTE *)src; + symbolEncodingType_e const litEncType = (symbolEncodingType_e)(istart[0] & 3); + + switch (litEncType) { + case set_repeat: + if (dctx->litEntropy == 0) + return ERROR(dictionary_corrupted); + /* fall-through */ + case set_compressed: + if (srcSize < 5) + return ERROR(corruption_detected); /* srcSize >= MIN_CBLOCK_SIZE == 3; here we need up to 5 for case 3 */ + { + size_t lhSize, litSize, litCSize; + U32 singleStream = 0; + U32 const lhlCode = (istart[0] >> 2) & 3; + U32 const lhc = ZSTD_readLE32(istart); + switch (lhlCode) { + case 0: + case 1: + default: /* note : default is impossible, since lhlCode into [0..3] */ + /* 2 - 2 - 10 - 10 */ + singleStream = !lhlCode; + lhSize = 3; + litSize = (lhc >> 4) & 0x3FF; + litCSize = (lhc >> 14) & 0x3FF; + break; + case 2: + /* 2 - 2 - 14 - 14 */ + lhSize = 4; + litSize = (lhc >> 4) & 0x3FFF; + litCSize = lhc >> 18; + break; + case 3: + /* 2 - 2 - 18 - 18 */ + lhSize = 5; + litSize = (lhc >> 4) & 0x3FFFF; + litCSize = (lhc >> 22) + (istart[4] << 10); + break; + } + if (litSize > ZSTD_BLOCKSIZE_ABSOLUTEMAX) + return ERROR(corruption_detected); + if (litCSize + lhSize > srcSize) + return ERROR(corruption_detected); + + if (HUF_isError( + (litEncType == set_repeat) + ? (singleStream ? HUF_decompress1X_usingDTable(dctx->litBuffer, litSize, istart + lhSize, litCSize, dctx->HUFptr) + : HUF_decompress4X_usingDTable(dctx->litBuffer, litSize, istart + lhSize, litCSize, dctx->HUFptr)) + : (singleStream + ? HUF_decompress1X2_DCtx_wksp(dctx->entropy.hufTable, dctx->litBuffer, litSize, istart + lhSize, litCSize, + dctx->entropy.workspace, sizeof(dctx->entropy.workspace)) + : HUF_decompress4X_hufOnly_wksp(dctx->entropy.hufTable, dctx->litBuffer, litSize, istart + lhSize, litCSize, + dctx->entropy.workspace, sizeof(dctx->entropy.workspace))))) + return ERROR(corruption_detected); + + dctx->litPtr = dctx->litBuffer; + dctx->litSize = litSize; + dctx->litEntropy = 1; + if (litEncType == set_compressed) + dctx->HUFptr = dctx->entropy.hufTable; + memset(dctx->litBuffer + dctx->litSize, 0, WILDCOPY_OVERLENGTH); + return litCSize + lhSize; + } + + case set_basic: { + size_t litSize, lhSize; + U32 const lhlCode = ((istart[0]) >> 2) & 3; + switch (lhlCode) { + case 0: + case 2: + default: /* note : default is impossible, since lhlCode into [0..3] */ + lhSize = 1; + litSize = istart[0] >> 3; + break; + case 1: + lhSize = 2; + litSize = ZSTD_readLE16(istart) >> 4; + break; + case 3: + lhSize = 3; + litSize = ZSTD_readLE24(istart) >> 4; + break; + } + + if (lhSize + litSize + WILDCOPY_OVERLENGTH > srcSize) { /* risk reading beyond src buffer with wildcopy */ + if (litSize + lhSize > srcSize) + return ERROR(corruption_detected); + memcpy(dctx->litBuffer, istart + lhSize, litSize); + dctx->litPtr = dctx->litBuffer; + dctx->litSize = litSize; + memset(dctx->litBuffer + dctx->litSize, 0, WILDCOPY_OVERLENGTH); + return lhSize + litSize; + } + /* direct reference into compressed stream */ + dctx->litPtr = istart + lhSize; + dctx->litSize = litSize; + return lhSize + litSize; + } + + case set_rle: { + U32 const lhlCode = ((istart[0]) >> 2) & 3; + size_t litSize, lhSize; + switch (lhlCode) { + case 0: + case 2: + default: /* note : default is impossible, since lhlCode into [0..3] */ + lhSize = 1; + litSize = istart[0] >> 3; + break; + case 1: + lhSize = 2; + litSize = ZSTD_readLE16(istart) >> 4; + break; + case 3: + lhSize = 3; + litSize = ZSTD_readLE24(istart) >> 4; + if (srcSize < 4) + return ERROR(corruption_detected); /* srcSize >= MIN_CBLOCK_SIZE == 3; here we need lhSize+1 = 4 */ + break; + } + if (litSize > ZSTD_BLOCKSIZE_ABSOLUTEMAX) + return ERROR(corruption_detected); + memset(dctx->litBuffer, istart[lhSize], litSize + WILDCOPY_OVERLENGTH); + dctx->litPtr = dctx->litBuffer; + dctx->litSize = litSize; + return lhSize + 1; + } + default: + return ERROR(corruption_detected); /* impossible */ + } + } +} + +typedef union { + FSE_decode_t realData; + U32 alignedBy4; +} FSE_decode_t4; + +static const FSE_decode_t4 LL_defaultDTable[(1 << LL_DEFAULTNORMLOG) + 1] = { + {{LL_DEFAULTNORMLOG, 1, 1}}, /* header : tableLog, fastMode, fastMode */ + {{0, 0, 4}}, /* 0 : base, symbol, bits */ + {{16, 0, 4}}, + {{32, 1, 5}}, + {{0, 3, 5}}, + {{0, 4, 5}}, + {{0, 6, 5}}, + {{0, 7, 5}}, + {{0, 9, 5}}, + {{0, 10, 5}}, + {{0, 12, 5}}, + {{0, 14, 6}}, + {{0, 16, 5}}, + {{0, 18, 5}}, + {{0, 19, 5}}, + {{0, 21, 5}}, + {{0, 22, 5}}, + {{0, 24, 5}}, + {{32, 25, 5}}, + {{0, 26, 5}}, + {{0, 27, 6}}, + {{0, 29, 6}}, + {{0, 31, 6}}, + {{32, 0, 4}}, + {{0, 1, 4}}, + {{0, 2, 5}}, + {{32, 4, 5}}, + {{0, 5, 5}}, + {{32, 7, 5}}, + {{0, 8, 5}}, + {{32, 10, 5}}, + {{0, 11, 5}}, + {{0, 13, 6}}, + {{32, 16, 5}}, + {{0, 17, 5}}, + {{32, 19, 5}}, + {{0, 20, 5}}, + {{32, 22, 5}}, + {{0, 23, 5}}, + {{0, 25, 4}}, + {{16, 25, 4}}, + {{32, 26, 5}}, + {{0, 28, 6}}, + {{0, 30, 6}}, + {{48, 0, 4}}, + {{16, 1, 4}}, + {{32, 2, 5}}, + {{32, 3, 5}}, + {{32, 5, 5}}, + {{32, 6, 5}}, + {{32, 8, 5}}, + {{32, 9, 5}}, + {{32, 11, 5}}, + {{32, 12, 5}}, + {{0, 15, 6}}, + {{32, 17, 5}}, + {{32, 18, 5}}, + {{32, 20, 5}}, + {{32, 21, 5}}, + {{32, 23, 5}}, + {{32, 24, 5}}, + {{0, 35, 6}}, + {{0, 34, 6}}, + {{0, 33, 6}}, + {{0, 32, 6}}, +}; /* LL_defaultDTable */ + +static const FSE_decode_t4 ML_defaultDTable[(1 << ML_DEFAULTNORMLOG) + 1] = { + {{ML_DEFAULTNORMLOG, 1, 1}}, /* header : tableLog, fastMode, fastMode */ + {{0, 0, 6}}, /* 0 : base, symbol, bits */ + {{0, 1, 4}}, + {{32, 2, 5}}, + {{0, 3, 5}}, + {{0, 5, 5}}, + {{0, 6, 5}}, + {{0, 8, 5}}, + {{0, 10, 6}}, + {{0, 13, 6}}, + {{0, 16, 6}}, + {{0, 19, 6}}, + {{0, 22, 6}}, + {{0, 25, 6}}, + {{0, 28, 6}}, + {{0, 31, 6}}, + {{0, 33, 6}}, + {{0, 35, 6}}, + {{0, 37, 6}}, + {{0, 39, 6}}, + {{0, 41, 6}}, + {{0, 43, 6}}, + {{0, 45, 6}}, + {{16, 1, 4}}, + {{0, 2, 4}}, + {{32, 3, 5}}, + {{0, 4, 5}}, + {{32, 6, 5}}, + {{0, 7, 5}}, + {{0, 9, 6}}, + {{0, 12, 6}}, + {{0, 15, 6}}, + {{0, 18, 6}}, + {{0, 21, 6}}, + {{0, 24, 6}}, + {{0, 27, 6}}, + {{0, 30, 6}}, + {{0, 32, 6}}, + {{0, 34, 6}}, + {{0, 36, 6}}, + {{0, 38, 6}}, + {{0, 40, 6}}, + {{0, 42, 6}}, + {{0, 44, 6}}, + {{32, 1, 4}}, + {{48, 1, 4}}, + {{16, 2, 4}}, + {{32, 4, 5}}, + {{32, 5, 5}}, + {{32, 7, 5}}, + {{32, 8, 5}}, + {{0, 11, 6}}, + {{0, 14, 6}}, + {{0, 17, 6}}, + {{0, 20, 6}}, + {{0, 23, 6}}, + {{0, 26, 6}}, + {{0, 29, 6}}, + {{0, 52, 6}}, + {{0, 51, 6}}, + {{0, 50, 6}}, + {{0, 49, 6}}, + {{0, 48, 6}}, + {{0, 47, 6}}, + {{0, 46, 6}}, +}; /* ML_defaultDTable */ + +static const FSE_decode_t4 OF_defaultDTable[(1 << OF_DEFAULTNORMLOG) + 1] = { + {{OF_DEFAULTNORMLOG, 1, 1}}, /* header : tableLog, fastMode, fastMode */ + {{0, 0, 5}}, /* 0 : base, symbol, bits */ + {{0, 6, 4}}, + {{0, 9, 5}}, + {{0, 15, 5}}, + {{0, 21, 5}}, + {{0, 3, 5}}, + {{0, 7, 4}}, + {{0, 12, 5}}, + {{0, 18, 5}}, + {{0, 23, 5}}, + {{0, 5, 5}}, + {{0, 8, 4}}, + {{0, 14, 5}}, + {{0, 20, 5}}, + {{0, 2, 5}}, + {{16, 7, 4}}, + {{0, 11, 5}}, + {{0, 17, 5}}, + {{0, 22, 5}}, + {{0, 4, 5}}, + {{16, 8, 4}}, + {{0, 13, 5}}, + {{0, 19, 5}}, + {{0, 1, 5}}, + {{16, 6, 4}}, + {{0, 10, 5}}, + {{0, 16, 5}}, + {{0, 28, 5}}, + {{0, 27, 5}}, + {{0, 26, 5}}, + {{0, 25, 5}}, + {{0, 24, 5}}, +}; /* OF_defaultDTable */ + +/*! ZSTD_buildSeqTable() : + @return : nb bytes read from src, + or an error code if it fails, testable with ZSTD_isError() +*/ +static size_t ZSTD_buildSeqTable(FSE_DTable *DTableSpace, const FSE_DTable **DTablePtr, symbolEncodingType_e type, U32 max, U32 maxLog, const void *src, + size_t srcSize, const FSE_decode_t4 *defaultTable, U32 flagRepeatTable, void *workspace, size_t workspaceSize) +{ + const void *const tmpPtr = defaultTable; /* bypass strict aliasing */ + switch (type) { + case set_rle: + if (!srcSize) + return ERROR(srcSize_wrong); + if ((*(const BYTE *)src) > max) + return ERROR(corruption_detected); + FSE_buildDTable_rle(DTableSpace, *(const BYTE *)src); + *DTablePtr = DTableSpace; + return 1; + case set_basic: *DTablePtr = (const FSE_DTable *)tmpPtr; return 0; + case set_repeat: + if (!flagRepeatTable) + return ERROR(corruption_detected); + return 0; + default: /* impossible */ + case set_compressed: { + U32 tableLog; + S16 *norm = (S16 *)workspace; + size_t const spaceUsed32 = ALIGN(sizeof(S16) * (MaxSeq + 1), sizeof(U32)) >> 2; + + if ((spaceUsed32 << 2) > workspaceSize) + return ERROR(GENERIC); + workspace = (U32 *)workspace + spaceUsed32; + workspaceSize -= (spaceUsed32 << 2); + { + size_t const headerSize = FSE_readNCount(norm, &max, &tableLog, src, srcSize); + if (FSE_isError(headerSize)) + return ERROR(corruption_detected); + if (tableLog > maxLog) + return ERROR(corruption_detected); + FSE_buildDTable_wksp(DTableSpace, norm, max, tableLog, workspace, workspaceSize); + *DTablePtr = DTableSpace; + return headerSize; + } + } + } +} + +size_t ZSTD_decodeSeqHeaders(ZSTD_DCtx *dctx, int *nbSeqPtr, const void *src, size_t srcSize) +{ + const BYTE *const istart = (const BYTE *const)src; + const BYTE *const iend = istart + srcSize; + const BYTE *ip = istart; + + /* check */ + if (srcSize < MIN_SEQUENCES_SIZE) + return ERROR(srcSize_wrong); + + /* SeqHead */ + { + int nbSeq = *ip++; + if (!nbSeq) { + *nbSeqPtr = 0; + return 1; + } + if (nbSeq > 0x7F) { + if (nbSeq == 0xFF) { + if (ip + 2 > iend) + return ERROR(srcSize_wrong); + nbSeq = ZSTD_readLE16(ip) + LONGNBSEQ, ip += 2; + } else { + if (ip >= iend) + return ERROR(srcSize_wrong); + nbSeq = ((nbSeq - 0x80) << 8) + *ip++; + } + } + *nbSeqPtr = nbSeq; + } + + /* FSE table descriptors */ + if (ip + 4 > iend) + return ERROR(srcSize_wrong); /* minimum possible size */ + { + symbolEncodingType_e const LLtype = (symbolEncodingType_e)(*ip >> 6); + symbolEncodingType_e const OFtype = (symbolEncodingType_e)((*ip >> 4) & 3); + symbolEncodingType_e const MLtype = (symbolEncodingType_e)((*ip >> 2) & 3); + ip++; + + /* Build DTables */ + { + size_t const llhSize = ZSTD_buildSeqTable(dctx->entropy.LLTable, &dctx->LLTptr, LLtype, MaxLL, LLFSELog, ip, iend - ip, + LL_defaultDTable, dctx->fseEntropy, dctx->entropy.workspace, sizeof(dctx->entropy.workspace)); + if (ZSTD_isError(llhSize)) + return ERROR(corruption_detected); + ip += llhSize; + } + { + size_t const ofhSize = ZSTD_buildSeqTable(dctx->entropy.OFTable, &dctx->OFTptr, OFtype, MaxOff, OffFSELog, ip, iend - ip, + OF_defaultDTable, dctx->fseEntropy, dctx->entropy.workspace, sizeof(dctx->entropy.workspace)); + if (ZSTD_isError(ofhSize)) + return ERROR(corruption_detected); + ip += ofhSize; + } + { + size_t const mlhSize = ZSTD_buildSeqTable(dctx->entropy.MLTable, &dctx->MLTptr, MLtype, MaxML, MLFSELog, ip, iend - ip, + ML_defaultDTable, dctx->fseEntropy, dctx->entropy.workspace, sizeof(dctx->entropy.workspace)); + if (ZSTD_isError(mlhSize)) + return ERROR(corruption_detected); + ip += mlhSize; + } + } + + return ip - istart; +} + +typedef struct { + size_t litLength; + size_t matchLength; + size_t offset; + const BYTE *match; +} seq_t; + +typedef struct { + BIT_DStream_t DStream; + FSE_DState_t stateLL; + FSE_DState_t stateOffb; + FSE_DState_t stateML; + size_t prevOffset[ZSTD_REP_NUM]; + const BYTE *base; + size_t pos; + uPtrDiff gotoDict; +} seqState_t; + +FORCE_NOINLINE +size_t ZSTD_execSequenceLast7(BYTE *op, BYTE *const oend, seq_t sequence, const BYTE **litPtr, const BYTE *const litLimit, const BYTE *const base, + const BYTE *const vBase, const BYTE *const dictEnd) +{ + BYTE *const oLitEnd = op + sequence.litLength; + size_t const sequenceLength = sequence.litLength + sequence.matchLength; + BYTE *const oMatchEnd = op + sequenceLength; /* risk : address space overflow (32-bits) */ + BYTE *const oend_w = oend - WILDCOPY_OVERLENGTH; + const BYTE *const iLitEnd = *litPtr + sequence.litLength; + const BYTE *match = oLitEnd - sequence.offset; + + /* check */ + if (oMatchEnd > oend) + return ERROR(dstSize_tooSmall); /* last match must start at a minimum distance of WILDCOPY_OVERLENGTH from oend */ + if (iLitEnd > litLimit) + return ERROR(corruption_detected); /* over-read beyond lit buffer */ + if (oLitEnd <= oend_w) + return ERROR(GENERIC); /* Precondition */ + + /* copy literals */ + if (op < oend_w) { + ZSTD_wildcopy(op, *litPtr, oend_w - op); + *litPtr += oend_w - op; + op = oend_w; + } + while (op < oLitEnd) + *op++ = *(*litPtr)++; + + /* copy Match */ + if (sequence.offset > (size_t)(oLitEnd - base)) { + /* offset beyond prefix */ + if (sequence.offset > (size_t)(oLitEnd - vBase)) + return ERROR(corruption_detected); + match = dictEnd - (base - match); + if (match + sequence.matchLength <= dictEnd) { + memmove(oLitEnd, match, sequence.matchLength); + return sequenceLength; + } + /* span extDict & currPrefixSegment */ + { + size_t const length1 = dictEnd - match; + memmove(oLitEnd, match, length1); + op = oLitEnd + length1; + sequence.matchLength -= length1; + match = base; + } + } + while (op < oMatchEnd) + *op++ = *match++; + return sequenceLength; +} + +static seq_t ZSTD_decodeSequence(seqState_t *seqState) +{ + seq_t seq; + + U32 const llCode = FSE_peekSymbol(&seqState->stateLL); + U32 const mlCode = FSE_peekSymbol(&seqState->stateML); + U32 const ofCode = FSE_peekSymbol(&seqState->stateOffb); /* <= maxOff, by table construction */ + + U32 const llBits = LL_bits[llCode]; + U32 const mlBits = ML_bits[mlCode]; + U32 const ofBits = ofCode; + U32 const totalBits = llBits + mlBits + ofBits; + + static const U32 LL_base[MaxLL + 1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, + 20, 22, 24, 28, 32, 40, 48, 64, 0x80, 0x100, 0x200, 0x400, 0x800, 0x1000, 0x2000, 0x4000, 0x8000, 0x10000}; + + static const U32 ML_base[MaxML + 1] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 37, 39, 41, + 43, 47, 51, 59, 67, 83, 99, 0x83, 0x103, 0x203, 0x403, 0x803, 0x1003, 0x2003, 0x4003, 0x8003, 0x10003}; + + static const U32 OF_base[MaxOff + 1] = {0, 1, 1, 5, 0xD, 0x1D, 0x3D, 0x7D, 0xFD, 0x1FD, + 0x3FD, 0x7FD, 0xFFD, 0x1FFD, 0x3FFD, 0x7FFD, 0xFFFD, 0x1FFFD, 0x3FFFD, 0x7FFFD, + 0xFFFFD, 0x1FFFFD, 0x3FFFFD, 0x7FFFFD, 0xFFFFFD, 0x1FFFFFD, 0x3FFFFFD, 0x7FFFFFD, 0xFFFFFFD}; + + /* sequence */ + { + size_t offset; + if (!ofCode) + offset = 0; + else { + offset = OF_base[ofCode] + BIT_readBitsFast(&seqState->DStream, ofBits); /* <= (ZSTD_WINDOWLOG_MAX-1) bits */ + if (ZSTD_32bits()) + BIT_reloadDStream(&seqState->DStream); + } + + if (ofCode <= 1) { + offset += (llCode == 0); + if (offset) { + size_t temp = (offset == 3) ? seqState->prevOffset[0] - 1 : seqState->prevOffset[offset]; + temp += !temp; /* 0 is not valid; input is corrupted; force offset to 1 */ + if (offset != 1) + seqState->prevOffset[2] = seqState->prevOffset[1]; + seqState->prevOffset[1] = seqState->prevOffset[0]; + seqState->prevOffset[0] = offset = temp; + } else { + offset = seqState->prevOffset[0]; + } + } else { + seqState->prevOffset[2] = seqState->prevOffset[1]; + seqState->prevOffset[1] = seqState->prevOffset[0]; + seqState->prevOffset[0] = offset; + } + seq.offset = offset; + } + + seq.matchLength = ML_base[mlCode] + ((mlCode > 31) ? BIT_readBitsFast(&seqState->DStream, mlBits) : 0); /* <= 16 bits */ + if (ZSTD_32bits() && (mlBits + llBits > 24)) + BIT_reloadDStream(&seqState->DStream); + + seq.litLength = LL_base[llCode] + ((llCode > 15) ? BIT_readBitsFast(&seqState->DStream, llBits) : 0); /* <= 16 bits */ + if (ZSTD_32bits() || (totalBits > 64 - 7 - (LLFSELog + MLFSELog + OffFSELog))) + BIT_reloadDStream(&seqState->DStream); + + /* ANS state update */ + FSE_updateState(&seqState->stateLL, &seqState->DStream); /* <= 9 bits */ + FSE_updateState(&seqState->stateML, &seqState->DStream); /* <= 9 bits */ + if (ZSTD_32bits()) + BIT_reloadDStream(&seqState->DStream); /* <= 18 bits */ + FSE_updateState(&seqState->stateOffb, &seqState->DStream); /* <= 8 bits */ + + seq.match = NULL; + + return seq; +} + +FORCE_INLINE +size_t ZSTD_execSequence(BYTE *op, BYTE *const oend, seq_t sequence, const BYTE **litPtr, const BYTE *const litLimit, const BYTE *const base, + const BYTE *const vBase, const BYTE *const dictEnd) +{ + BYTE *const oLitEnd = op + sequence.litLength; + size_t const sequenceLength = sequence.litLength + sequence.matchLength; + BYTE *const oMatchEnd = op + sequenceLength; /* risk : address space overflow (32-bits) */ + BYTE *const oend_w = oend - WILDCOPY_OVERLENGTH; + const BYTE *const iLitEnd = *litPtr + sequence.litLength; + const BYTE *match = oLitEnd - sequence.offset; + + /* check */ + if (oMatchEnd > oend) + return ERROR(dstSize_tooSmall); /* last match must start at a minimum distance of WILDCOPY_OVERLENGTH from oend */ + if (iLitEnd > litLimit) + return ERROR(corruption_detected); /* over-read beyond lit buffer */ + if (oLitEnd > oend_w) + return ZSTD_execSequenceLast7(op, oend, sequence, litPtr, litLimit, base, vBase, dictEnd); + + /* copy Literals */ + ZSTD_copy8(op, *litPtr); + if (sequence.litLength > 8) + ZSTD_wildcopy(op + 8, (*litPtr) + 8, + sequence.litLength - 8); /* note : since oLitEnd <= oend-WILDCOPY_OVERLENGTH, no risk of overwrite beyond oend */ + op = oLitEnd; + *litPtr = iLitEnd; /* update for next sequence */ + + /* copy Match */ + if (sequence.offset > (size_t)(oLitEnd - base)) { + /* offset beyond prefix */ + if (sequence.offset > (size_t)(oLitEnd - vBase)) + return ERROR(corruption_detected); + match = dictEnd + (match - base); + if (match + sequence.matchLength <= dictEnd) { + memmove(oLitEnd, match, sequence.matchLength); + return sequenceLength; + } + /* span extDict & currPrefixSegment */ + { + size_t const length1 = dictEnd - match; + memmove(oLitEnd, match, length1); + op = oLitEnd + length1; + sequence.matchLength -= length1; + match = base; + if (op > oend_w || sequence.matchLength < MINMATCH) { + U32 i; + for (i = 0; i < sequence.matchLength; ++i) + op[i] = match[i]; + return sequenceLength; + } + } + } + /* Requirement: op <= oend_w && sequence.matchLength >= MINMATCH */ + + /* match within prefix */ + if (sequence.offset < 8) { + /* close range match, overlap */ + static const U32 dec32table[] = {0, 1, 2, 1, 4, 4, 4, 4}; /* added */ + static const int dec64table[] = {8, 8, 8, 7, 8, 9, 10, 11}; /* subtracted */ + int const sub2 = dec64table[sequence.offset]; + op[0] = match[0]; + op[1] = match[1]; + op[2] = match[2]; + op[3] = match[3]; + match += dec32table[sequence.offset]; + ZSTD_copy4(op + 4, match); + match -= sub2; + } else { + ZSTD_copy8(op, match); + } + op += 8; + match += 8; + + if (oMatchEnd > oend - (16 - MINMATCH)) { + if (op < oend_w) { + ZSTD_wildcopy(op, match, oend_w - op); + match += oend_w - op; + op = oend_w; + } + while (op < oMatchEnd) + *op++ = *match++; + } else { + ZSTD_wildcopy(op, match, (ptrdiff_t)sequence.matchLength - 8); /* works even if matchLength < 8 */ + } + return sequenceLength; +} + +static size_t ZSTD_decompressSequences(ZSTD_DCtx *dctx, void *dst, size_t maxDstSize, const void *seqStart, size_t seqSize) +{ + const BYTE *ip = (const BYTE *)seqStart; + const BYTE *const iend = ip + seqSize; + BYTE *const ostart = (BYTE * const)dst; + BYTE *const oend = ostart + maxDstSize; + BYTE *op = ostart; + const BYTE *litPtr = dctx->litPtr; + const BYTE *const litEnd = litPtr + dctx->litSize; + const BYTE *const base = (const BYTE *)(dctx->base); + const BYTE *const vBase = (const BYTE *)(dctx->vBase); + const BYTE *const dictEnd = (const BYTE *)(dctx->dictEnd); + int nbSeq; + + /* Build Decoding Tables */ + { + size_t const seqHSize = ZSTD_decodeSeqHeaders(dctx, &nbSeq, ip, seqSize); + if (ZSTD_isError(seqHSize)) + return seqHSize; + ip += seqHSize; + } + + /* Regen sequences */ + if (nbSeq) { + seqState_t seqState; + dctx->fseEntropy = 1; + { + U32 i; + for (i = 0; i < ZSTD_REP_NUM; i++) + seqState.prevOffset[i] = dctx->entropy.rep[i]; + } + CHECK_E(BIT_initDStream(&seqState.DStream, ip, iend - ip), corruption_detected); + FSE_initDState(&seqState.stateLL, &seqState.DStream, dctx->LLTptr); + FSE_initDState(&seqState.stateOffb, &seqState.DStream, dctx->OFTptr); + FSE_initDState(&seqState.stateML, &seqState.DStream, dctx->MLTptr); + + for (; (BIT_reloadDStream(&(seqState.DStream)) <= BIT_DStream_completed) && nbSeq;) { + nbSeq--; + { + seq_t const sequence = ZSTD_decodeSequence(&seqState); + size_t const oneSeqSize = ZSTD_execSequence(op, oend, sequence, &litPtr, litEnd, base, vBase, dictEnd); + if (ZSTD_isError(oneSeqSize)) + return oneSeqSize; + op += oneSeqSize; + } + } + + /* check if reached exact end */ + if (nbSeq) + return ERROR(corruption_detected); + /* save reps for next block */ + { + U32 i; + for (i = 0; i < ZSTD_REP_NUM; i++) + dctx->entropy.rep[i] = (U32)(seqState.prevOffset[i]); + } + } + + /* last literal segment */ + { + size_t const lastLLSize = litEnd - litPtr; + if (lastLLSize > (size_t)(oend - op)) + return ERROR(dstSize_tooSmall); + memcpy(op, litPtr, lastLLSize); + op += lastLLSize; + } + + return op - ostart; +} + +FORCE_INLINE seq_t ZSTD_decodeSequenceLong_generic(seqState_t *seqState, int const longOffsets) +{ + seq_t seq; + + U32 const llCode = FSE_peekSymbol(&seqState->stateLL); + U32 const mlCode = FSE_peekSymbol(&seqState->stateML); + U32 const ofCode = FSE_peekSymbol(&seqState->stateOffb); /* <= maxOff, by table construction */ + + U32 const llBits = LL_bits[llCode]; + U32 const mlBits = ML_bits[mlCode]; + U32 const ofBits = ofCode; + U32 const totalBits = llBits + mlBits + ofBits; + + static const U32 LL_base[MaxLL + 1] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, + 20, 22, 24, 28, 32, 40, 48, 64, 0x80, 0x100, 0x200, 0x400, 0x800, 0x1000, 0x2000, 0x4000, 0x8000, 0x10000}; + + static const U32 ML_base[MaxML + 1] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 37, 39, 41, + 43, 47, 51, 59, 67, 83, 99, 0x83, 0x103, 0x203, 0x403, 0x803, 0x1003, 0x2003, 0x4003, 0x8003, 0x10003}; + + static const U32 OF_base[MaxOff + 1] = {0, 1, 1, 5, 0xD, 0x1D, 0x3D, 0x7D, 0xFD, 0x1FD, + 0x3FD, 0x7FD, 0xFFD, 0x1FFD, 0x3FFD, 0x7FFD, 0xFFFD, 0x1FFFD, 0x3FFFD, 0x7FFFD, + 0xFFFFD, 0x1FFFFD, 0x3FFFFD, 0x7FFFFD, 0xFFFFFD, 0x1FFFFFD, 0x3FFFFFD, 0x7FFFFFD, 0xFFFFFFD}; + + /* sequence */ + { + size_t offset; + if (!ofCode) + offset = 0; + else { + if (longOffsets) { + int const extraBits = ofBits - MIN(ofBits, STREAM_ACCUMULATOR_MIN); + offset = OF_base[ofCode] + (BIT_readBitsFast(&seqState->DStream, ofBits - extraBits) << extraBits); + if (ZSTD_32bits() || extraBits) + BIT_reloadDStream(&seqState->DStream); + if (extraBits) + offset += BIT_readBitsFast(&seqState->DStream, extraBits); + } else { + offset = OF_base[ofCode] + BIT_readBitsFast(&seqState->DStream, ofBits); /* <= (ZSTD_WINDOWLOG_MAX-1) bits */ + if (ZSTD_32bits()) + BIT_reloadDStream(&seqState->DStream); + } + } + + if (ofCode <= 1) { + offset += (llCode == 0); + if (offset) { + size_t temp = (offset == 3) ? seqState->prevOffset[0] - 1 : seqState->prevOffset[offset]; + temp += !temp; /* 0 is not valid; input is corrupted; force offset to 1 */ + if (offset != 1) + seqState->prevOffset[2] = seqState->prevOffset[1]; + seqState->prevOffset[1] = seqState->prevOffset[0]; + seqState->prevOffset[0] = offset = temp; + } else { + offset = seqState->prevOffset[0]; + } + } else { + seqState->prevOffset[2] = seqState->prevOffset[1]; + seqState->prevOffset[1] = seqState->prevOffset[0]; + seqState->prevOffset[0] = offset; + } + seq.offset = offset; + } + + seq.matchLength = ML_base[mlCode] + ((mlCode > 31) ? BIT_readBitsFast(&seqState->DStream, mlBits) : 0); /* <= 16 bits */ + if (ZSTD_32bits() && (mlBits + llBits > 24)) + BIT_reloadDStream(&seqState->DStream); + + seq.litLength = LL_base[llCode] + ((llCode > 15) ? BIT_readBitsFast(&seqState->DStream, llBits) : 0); /* <= 16 bits */ + if (ZSTD_32bits() || (totalBits > 64 - 7 - (LLFSELog + MLFSELog + OffFSELog))) + BIT_reloadDStream(&seqState->DStream); + + { + size_t const pos = seqState->pos + seq.litLength; + seq.match = seqState->base + pos - seq.offset; /* single memory segment */ + if (seq.offset > pos) + seq.match += seqState->gotoDict; /* separate memory segment */ + seqState->pos = pos + seq.matchLength; + } + + /* ANS state update */ + FSE_updateState(&seqState->stateLL, &seqState->DStream); /* <= 9 bits */ + FSE_updateState(&seqState->stateML, &seqState->DStream); /* <= 9 bits */ + if (ZSTD_32bits()) + BIT_reloadDStream(&seqState->DStream); /* <= 18 bits */ + FSE_updateState(&seqState->stateOffb, &seqState->DStream); /* <= 8 bits */ + + return seq; +} + +static seq_t ZSTD_decodeSequenceLong(seqState_t *seqState, unsigned const windowSize) +{ + if (ZSTD_highbit32(windowSize) > STREAM_ACCUMULATOR_MIN) { + return ZSTD_decodeSequenceLong_generic(seqState, 1); + } else { + return ZSTD_decodeSequenceLong_generic(seqState, 0); + } +} + +FORCE_INLINE +size_t ZSTD_execSequenceLong(BYTE *op, BYTE *const oend, seq_t sequence, const BYTE **litPtr, const BYTE *const litLimit, const BYTE *const base, + const BYTE *const vBase, const BYTE *const dictEnd) +{ + BYTE *const oLitEnd = op + sequence.litLength; + size_t const sequenceLength = sequence.litLength + sequence.matchLength; + BYTE *const oMatchEnd = op + sequenceLength; /* risk : address space overflow (32-bits) */ + BYTE *const oend_w = oend - WILDCOPY_OVERLENGTH; + const BYTE *const iLitEnd = *litPtr + sequence.litLength; + const BYTE *match = sequence.match; + + /* check */ + if (oMatchEnd > oend) + return ERROR(dstSize_tooSmall); /* last match must start at a minimum distance of WILDCOPY_OVERLENGTH from oend */ + if (iLitEnd > litLimit) + return ERROR(corruption_detected); /* over-read beyond lit buffer */ + if (oLitEnd > oend_w) + return ZSTD_execSequenceLast7(op, oend, sequence, litPtr, litLimit, base, vBase, dictEnd); + + /* copy Literals */ + ZSTD_copy8(op, *litPtr); + if (sequence.litLength > 8) + ZSTD_wildcopy(op + 8, (*litPtr) + 8, + sequence.litLength - 8); /* note : since oLitEnd <= oend-WILDCOPY_OVERLENGTH, no risk of overwrite beyond oend */ + op = oLitEnd; + *litPtr = iLitEnd; /* update for next sequence */ + + /* copy Match */ + if (sequence.offset > (size_t)(oLitEnd - base)) { + /* offset beyond prefix */ + if (sequence.offset > (size_t)(oLitEnd - vBase)) + return ERROR(corruption_detected); + if (match + sequence.matchLength <= dictEnd) { + memmove(oLitEnd, match, sequence.matchLength); + return sequenceLength; + } + /* span extDict & currPrefixSegment */ + { + size_t const length1 = dictEnd - match; + memmove(oLitEnd, match, length1); + op = oLitEnd + length1; + sequence.matchLength -= length1; + match = base; + if (op > oend_w || sequence.matchLength < MINMATCH) { + U32 i; + for (i = 0; i < sequence.matchLength; ++i) + op[i] = match[i]; + return sequenceLength; + } + } + } + /* Requirement: op <= oend_w && sequence.matchLength >= MINMATCH */ + + /* match within prefix */ + if (sequence.offset < 8) { + /* close range match, overlap */ + static const U32 dec32table[] = {0, 1, 2, 1, 4, 4, 4, 4}; /* added */ + static const int dec64table[] = {8, 8, 8, 7, 8, 9, 10, 11}; /* subtracted */ + int const sub2 = dec64table[sequence.offset]; + op[0] = match[0]; + op[1] = match[1]; + op[2] = match[2]; + op[3] = match[3]; + match += dec32table[sequence.offset]; + ZSTD_copy4(op + 4, match); + match -= sub2; + } else { + ZSTD_copy8(op, match); + } + op += 8; + match += 8; + + if (oMatchEnd > oend - (16 - MINMATCH)) { + if (op < oend_w) { + ZSTD_wildcopy(op, match, oend_w - op); + match += oend_w - op; + op = oend_w; + } + while (op < oMatchEnd) + *op++ = *match++; + } else { + ZSTD_wildcopy(op, match, (ptrdiff_t)sequence.matchLength - 8); /* works even if matchLength < 8 */ + } + return sequenceLength; +} + +static size_t ZSTD_decompressSequencesLong(ZSTD_DCtx *dctx, void *dst, size_t maxDstSize, const void *seqStart, size_t seqSize) +{ + const BYTE *ip = (const BYTE *)seqStart; + const BYTE *const iend = ip + seqSize; + BYTE *const ostart = (BYTE * const)dst; + BYTE *const oend = ostart + maxDstSize; + BYTE *op = ostart; + const BYTE *litPtr = dctx->litPtr; + const BYTE *const litEnd = litPtr + dctx->litSize; + const BYTE *const base = (const BYTE *)(dctx->base); + const BYTE *const vBase = (const BYTE *)(dctx->vBase); + const BYTE *const dictEnd = (const BYTE *)(dctx->dictEnd); + unsigned const windowSize = dctx->fParams.windowSize; + int nbSeq; + + /* Build Decoding Tables */ + { + size_t const seqHSize = ZSTD_decodeSeqHeaders(dctx, &nbSeq, ip, seqSize); + if (ZSTD_isError(seqHSize)) + return seqHSize; + ip += seqHSize; + } + + /* Regen sequences */ + if (nbSeq) { +#define STORED_SEQS 4 +#define STOSEQ_MASK (STORED_SEQS - 1) +#define ADVANCED_SEQS 4 + seq_t *sequences = (seq_t *)dctx->entropy.workspace; + int const seqAdvance = MIN(nbSeq, ADVANCED_SEQS); + seqState_t seqState; + int seqNb; + ZSTD_STATIC_ASSERT(sizeof(dctx->entropy.workspace) >= sizeof(seq_t) * STORED_SEQS); + dctx->fseEntropy = 1; + { + U32 i; + for (i = 0; i < ZSTD_REP_NUM; i++) + seqState.prevOffset[i] = dctx->entropy.rep[i]; + } + seqState.base = base; + seqState.pos = (size_t)(op - base); + seqState.gotoDict = (uPtrDiff)dictEnd - (uPtrDiff)base; /* cast to avoid undefined behaviour */ + CHECK_E(BIT_initDStream(&seqState.DStream, ip, iend - ip), corruption_detected); + FSE_initDState(&seqState.stateLL, &seqState.DStream, dctx->LLTptr); + FSE_initDState(&seqState.stateOffb, &seqState.DStream, dctx->OFTptr); + FSE_initDState(&seqState.stateML, &seqState.DStream, dctx->MLTptr); + + /* prepare in advance */ + for (seqNb = 0; (BIT_reloadDStream(&seqState.DStream) <= BIT_DStream_completed) && seqNb < seqAdvance; seqNb++) { + sequences[seqNb] = ZSTD_decodeSequenceLong(&seqState, windowSize); + } + if (seqNb < seqAdvance) + return ERROR(corruption_detected); + + /* decode and decompress */ + for (; (BIT_reloadDStream(&(seqState.DStream)) <= BIT_DStream_completed) && seqNb < nbSeq; seqNb++) { + seq_t const sequence = ZSTD_decodeSequenceLong(&seqState, windowSize); + size_t const oneSeqSize = + ZSTD_execSequenceLong(op, oend, sequences[(seqNb - ADVANCED_SEQS) & STOSEQ_MASK], &litPtr, litEnd, base, vBase, dictEnd); + if (ZSTD_isError(oneSeqSize)) + return oneSeqSize; + ZSTD_PREFETCH(sequence.match); + sequences[seqNb & STOSEQ_MASK] = sequence; + op += oneSeqSize; + } + if (seqNb < nbSeq) + return ERROR(corruption_detected); + + /* finish queue */ + seqNb -= seqAdvance; + for (; seqNb < nbSeq; seqNb++) { + size_t const oneSeqSize = ZSTD_execSequenceLong(op, oend, sequences[seqNb & STOSEQ_MASK], &litPtr, litEnd, base, vBase, dictEnd); + if (ZSTD_isError(oneSeqSize)) + return oneSeqSize; + op += oneSeqSize; + } + + /* save reps for next block */ + { + U32 i; + for (i = 0; i < ZSTD_REP_NUM; i++) + dctx->entropy.rep[i] = (U32)(seqState.prevOffset[i]); + } + } + + /* last literal segment */ + { + size_t const lastLLSize = litEnd - litPtr; + if (lastLLSize > (size_t)(oend - op)) + return ERROR(dstSize_tooSmall); + memcpy(op, litPtr, lastLLSize); + op += lastLLSize; + } + + return op - ostart; +} + +static size_t ZSTD_decompressBlock_internal(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, const void *src, size_t srcSize) +{ /* blockType == blockCompressed */ + const BYTE *ip = (const BYTE *)src; + + if (srcSize >= ZSTD_BLOCKSIZE_ABSOLUTEMAX) + return ERROR(srcSize_wrong); + + /* Decode literals section */ + { + size_t const litCSize = ZSTD_decodeLiteralsBlock(dctx, src, srcSize); + if (ZSTD_isError(litCSize)) + return litCSize; + ip += litCSize; + srcSize -= litCSize; + } + if (sizeof(size_t) > 4) /* do not enable prefetching on 32-bits x86, as it's performance detrimental */ + /* likely because of register pressure */ + /* if that's the correct cause, then 32-bits ARM should be affected differently */ + /* it would be good to test this on ARM real hardware, to see if prefetch version improves speed */ + if (dctx->fParams.windowSize > (1 << 23)) + return ZSTD_decompressSequencesLong(dctx, dst, dstCapacity, ip, srcSize); + return ZSTD_decompressSequences(dctx, dst, dstCapacity, ip, srcSize); +} + +static void ZSTD_checkContinuity(ZSTD_DCtx *dctx, const void *dst) +{ + if (dst != dctx->previousDstEnd) { /* not contiguous */ + dctx->dictEnd = dctx->previousDstEnd; + dctx->vBase = (const char *)dst - ((const char *)(dctx->previousDstEnd) - (const char *)(dctx->base)); + dctx->base = dst; + dctx->previousDstEnd = dst; + } +} + +size_t ZSTD_decompressBlock(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, const void *src, size_t srcSize) +{ + size_t dSize; + ZSTD_checkContinuity(dctx, dst); + dSize = ZSTD_decompressBlock_internal(dctx, dst, dstCapacity, src, srcSize); + dctx->previousDstEnd = (char *)dst + dSize; + return dSize; +} + +/** ZSTD_insertBlock() : + insert `src` block into `dctx` history. Useful to track uncompressed blocks. */ +size_t ZSTD_insertBlock(ZSTD_DCtx *dctx, const void *blockStart, size_t blockSize) +{ + ZSTD_checkContinuity(dctx, blockStart); + dctx->previousDstEnd = (const char *)blockStart + blockSize; + return blockSize; +} + +size_t ZSTD_generateNxBytes(void *dst, size_t dstCapacity, BYTE byte, size_t length) +{ + if (length > dstCapacity) + return ERROR(dstSize_tooSmall); + memset(dst, byte, length); + return length; +} + +/** ZSTD_findFrameCompressedSize() : + * compatible with legacy mode + * `src` must point to the start of a ZSTD frame, ZSTD legacy frame, or skippable frame + * `srcSize` must be at least as large as the frame contained + * @return : the compressed size of the frame starting at `src` */ +size_t ZSTD_findFrameCompressedSize(const void *src, size_t srcSize) +{ + if (srcSize >= ZSTD_skippableHeaderSize && (ZSTD_readLE32(src) & 0xFFFFFFF0U) == ZSTD_MAGIC_SKIPPABLE_START) { + return ZSTD_skippableHeaderSize + ZSTD_readLE32((const BYTE *)src + 4); + } else { + const BYTE *ip = (const BYTE *)src; + const BYTE *const ipstart = ip; + size_t remainingSize = srcSize; + ZSTD_frameParams fParams; + + size_t const headerSize = ZSTD_frameHeaderSize(ip, remainingSize); + if (ZSTD_isError(headerSize)) + return headerSize; + + /* Frame Header */ + { + size_t const ret = ZSTD_getFrameParams(&fParams, ip, remainingSize); + if (ZSTD_isError(ret)) + return ret; + if (ret > 0) + return ERROR(srcSize_wrong); + } + + ip += headerSize; + remainingSize -= headerSize; + + /* Loop on each block */ + while (1) { + blockProperties_t blockProperties; + size_t const cBlockSize = ZSTD_getcBlockSize(ip, remainingSize, &blockProperties); + if (ZSTD_isError(cBlockSize)) + return cBlockSize; + + if (ZSTD_blockHeaderSize + cBlockSize > remainingSize) + return ERROR(srcSize_wrong); + + ip += ZSTD_blockHeaderSize + cBlockSize; + remainingSize -= ZSTD_blockHeaderSize + cBlockSize; + + if (blockProperties.lastBlock) + break; + } + + if (fParams.checksumFlag) { /* Frame content checksum */ + if (remainingSize < 4) + return ERROR(srcSize_wrong); + ip += 4; + remainingSize -= 4; + } + + return ip - ipstart; + } +} + +/*! ZSTD_decompressFrame() : +* @dctx must be properly initialized */ +static size_t ZSTD_decompressFrame(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, const void **srcPtr, size_t *srcSizePtr) +{ + const BYTE *ip = (const BYTE *)(*srcPtr); + BYTE *const ostart = (BYTE * const)dst; + BYTE *const oend = ostart + dstCapacity; + BYTE *op = ostart; + size_t remainingSize = *srcSizePtr; + + /* check */ + if (remainingSize < ZSTD_frameHeaderSize_min + ZSTD_blockHeaderSize) + return ERROR(srcSize_wrong); + + /* Frame Header */ + { + size_t const frameHeaderSize = ZSTD_frameHeaderSize(ip, ZSTD_frameHeaderSize_prefix); + if (ZSTD_isError(frameHeaderSize)) + return frameHeaderSize; + if (remainingSize < frameHeaderSize + ZSTD_blockHeaderSize) + return ERROR(srcSize_wrong); + CHECK_F(ZSTD_decodeFrameHeader(dctx, ip, frameHeaderSize)); + ip += frameHeaderSize; + remainingSize -= frameHeaderSize; + } + + /* Loop on each block */ + while (1) { + size_t decodedSize; + blockProperties_t blockProperties; + size_t const cBlockSize = ZSTD_getcBlockSize(ip, remainingSize, &blockProperties); + if (ZSTD_isError(cBlockSize)) + return cBlockSize; + + ip += ZSTD_blockHeaderSize; + remainingSize -= ZSTD_blockHeaderSize; + if (cBlockSize > remainingSize) + return ERROR(srcSize_wrong); + + switch (blockProperties.blockType) { + case bt_compressed: decodedSize = ZSTD_decompressBlock_internal(dctx, op, oend - op, ip, cBlockSize); break; + case bt_raw: decodedSize = ZSTD_copyRawBlock(op, oend - op, ip, cBlockSize); break; + case bt_rle: decodedSize = ZSTD_generateNxBytes(op, oend - op, *ip, blockProperties.origSize); break; + case bt_reserved: + default: return ERROR(corruption_detected); + } + + if (ZSTD_isError(decodedSize)) + return decodedSize; + if (dctx->fParams.checksumFlag) + xxh64_update(&dctx->xxhState, op, decodedSize); + op += decodedSize; + ip += cBlockSize; + remainingSize -= cBlockSize; + if (blockProperties.lastBlock) + break; + } + + if (dctx->fParams.checksumFlag) { /* Frame content checksum verification */ + U32 const checkCalc = (U32)xxh64_digest(&dctx->xxhState); + U32 checkRead; + if (remainingSize < 4) + return ERROR(checksum_wrong); + checkRead = ZSTD_readLE32(ip); + if (checkRead != checkCalc) + return ERROR(checksum_wrong); + ip += 4; + remainingSize -= 4; + } + + /* Allow caller to get size read */ + *srcPtr = ip; + *srcSizePtr = remainingSize; + return op - ostart; +} + +static const void *ZSTD_DDictDictContent(const ZSTD_DDict *ddict); +static size_t ZSTD_DDictDictSize(const ZSTD_DDict *ddict); + +static size_t ZSTD_decompressMultiFrame(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, const void *src, size_t srcSize, const void *dict, size_t dictSize, + const ZSTD_DDict *ddict) +{ + void *const dststart = dst; + + if (ddict) { + if (dict) { + /* programmer error, these two cases should be mutually exclusive */ + return ERROR(GENERIC); + } + + dict = ZSTD_DDictDictContent(ddict); + dictSize = ZSTD_DDictDictSize(ddict); + } + + while (srcSize >= ZSTD_frameHeaderSize_prefix) { + U32 magicNumber; + + magicNumber = ZSTD_readLE32(src); + if (magicNumber != ZSTD_MAGICNUMBER) { + if ((magicNumber & 0xFFFFFFF0U) == ZSTD_MAGIC_SKIPPABLE_START) { + size_t skippableSize; + if (srcSize < ZSTD_skippableHeaderSize) + return ERROR(srcSize_wrong); + skippableSize = ZSTD_readLE32((const BYTE *)src + 4) + ZSTD_skippableHeaderSize; + if (srcSize < skippableSize) { + return ERROR(srcSize_wrong); + } + + src = (const BYTE *)src + skippableSize; + srcSize -= skippableSize; + continue; + } else { + return ERROR(prefix_unknown); + } + } + + if (ddict) { + /* we were called from ZSTD_decompress_usingDDict */ + ZSTD_refDDict(dctx, ddict); + } else { + /* this will initialize correctly with no dict if dict == NULL, so + * use this in all cases but ddict */ + CHECK_F(ZSTD_decompressBegin_usingDict(dctx, dict, dictSize)); + } + ZSTD_checkContinuity(dctx, dst); + + { + const size_t res = ZSTD_decompressFrame(dctx, dst, dstCapacity, &src, &srcSize); + if (ZSTD_isError(res)) + return res; + /* don't need to bounds check this, ZSTD_decompressFrame will have + * already */ + dst = (BYTE *)dst + res; + dstCapacity -= res; + } + } + + if (srcSize) + return ERROR(srcSize_wrong); /* input not entirely consumed */ + + return (BYTE *)dst - (BYTE *)dststart; +} + +size_t ZSTD_decompress_usingDict(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, const void *src, size_t srcSize, const void *dict, size_t dictSize) +{ + return ZSTD_decompressMultiFrame(dctx, dst, dstCapacity, src, srcSize, dict, dictSize, NULL); +} + +size_t ZSTD_decompressDCtx(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, const void *src, size_t srcSize) +{ + return ZSTD_decompress_usingDict(dctx, dst, dstCapacity, src, srcSize, NULL, 0); +} + +/*-************************************** +* Advanced Streaming Decompression API +* Bufferless and synchronous +****************************************/ +size_t ZSTD_nextSrcSizeToDecompress(ZSTD_DCtx *dctx) { return dctx->expected; } + +ZSTD_nextInputType_e ZSTD_nextInputType(ZSTD_DCtx *dctx) +{ + switch (dctx->stage) { + default: /* should not happen */ + case ZSTDds_getFrameHeaderSize: + case ZSTDds_decodeFrameHeader: return ZSTDnit_frameHeader; + case ZSTDds_decodeBlockHeader: return ZSTDnit_blockHeader; + case ZSTDds_decompressBlock: return ZSTDnit_block; + case ZSTDds_decompressLastBlock: return ZSTDnit_lastBlock; + case ZSTDds_checkChecksum: return ZSTDnit_checksum; + case ZSTDds_decodeSkippableHeader: + case ZSTDds_skipFrame: return ZSTDnit_skippableFrame; + } +} + +int ZSTD_isSkipFrame(ZSTD_DCtx *dctx) { return dctx->stage == ZSTDds_skipFrame; } /* for zbuff */ + +/** ZSTD_decompressContinue() : +* @return : nb of bytes generated into `dst` (necessarily <= `dstCapacity) +* or an error code, which can be tested using ZSTD_isError() */ +size_t ZSTD_decompressContinue(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, const void *src, size_t srcSize) +{ + /* Sanity check */ + if (srcSize != dctx->expected) + return ERROR(srcSize_wrong); + if (dstCapacity) + ZSTD_checkContinuity(dctx, dst); + + switch (dctx->stage) { + case ZSTDds_getFrameHeaderSize: + if (srcSize != ZSTD_frameHeaderSize_prefix) + return ERROR(srcSize_wrong); /* impossible */ + if ((ZSTD_readLE32(src) & 0xFFFFFFF0U) == ZSTD_MAGIC_SKIPPABLE_START) { /* skippable frame */ + memcpy(dctx->headerBuffer, src, ZSTD_frameHeaderSize_prefix); + dctx->expected = ZSTD_skippableHeaderSize - ZSTD_frameHeaderSize_prefix; /* magic number + skippable frame length */ + dctx->stage = ZSTDds_decodeSkippableHeader; + return 0; + } + dctx->headerSize = ZSTD_frameHeaderSize(src, ZSTD_frameHeaderSize_prefix); + if (ZSTD_isError(dctx->headerSize)) + return dctx->headerSize; + memcpy(dctx->headerBuffer, src, ZSTD_frameHeaderSize_prefix); + if (dctx->headerSize > ZSTD_frameHeaderSize_prefix) { + dctx->expected = dctx->headerSize - ZSTD_frameHeaderSize_prefix; + dctx->stage = ZSTDds_decodeFrameHeader; + return 0; + } + dctx->expected = 0; /* not necessary to copy more */ + + case ZSTDds_decodeFrameHeader: + memcpy(dctx->headerBuffer + ZSTD_frameHeaderSize_prefix, src, dctx->expected); + CHECK_F(ZSTD_decodeFrameHeader(dctx, dctx->headerBuffer, dctx->headerSize)); + dctx->expected = ZSTD_blockHeaderSize; + dctx->stage = ZSTDds_decodeBlockHeader; + return 0; + + case ZSTDds_decodeBlockHeader: { + blockProperties_t bp; + size_t const cBlockSize = ZSTD_getcBlockSize(src, ZSTD_blockHeaderSize, &bp); + if (ZSTD_isError(cBlockSize)) + return cBlockSize; + dctx->expected = cBlockSize; + dctx->bType = bp.blockType; + dctx->rleSize = bp.origSize; + if (cBlockSize) { + dctx->stage = bp.lastBlock ? ZSTDds_decompressLastBlock : ZSTDds_decompressBlock; + return 0; + } + /* empty block */ + if (bp.lastBlock) { + if (dctx->fParams.checksumFlag) { + dctx->expected = 4; + dctx->stage = ZSTDds_checkChecksum; + } else { + dctx->expected = 0; /* end of frame */ + dctx->stage = ZSTDds_getFrameHeaderSize; + } + } else { + dctx->expected = 3; /* go directly to next header */ + dctx->stage = ZSTDds_decodeBlockHeader; + } + return 0; + } + case ZSTDds_decompressLastBlock: + case ZSTDds_decompressBlock: { + size_t rSize; + switch (dctx->bType) { + case bt_compressed: rSize = ZSTD_decompressBlock_internal(dctx, dst, dstCapacity, src, srcSize); break; + case bt_raw: rSize = ZSTD_copyRawBlock(dst, dstCapacity, src, srcSize); break; + case bt_rle: rSize = ZSTD_setRleBlock(dst, dstCapacity, src, srcSize, dctx->rleSize); break; + case bt_reserved: /* should never happen */ + default: return ERROR(corruption_detected); + } + if (ZSTD_isError(rSize)) + return rSize; + if (dctx->fParams.checksumFlag) + xxh64_update(&dctx->xxhState, dst, rSize); + + if (dctx->stage == ZSTDds_decompressLastBlock) { /* end of frame */ + if (dctx->fParams.checksumFlag) { /* another round for frame checksum */ + dctx->expected = 4; + dctx->stage = ZSTDds_checkChecksum; + } else { + dctx->expected = 0; /* ends here */ + dctx->stage = ZSTDds_getFrameHeaderSize; + } + } else { + dctx->stage = ZSTDds_decodeBlockHeader; + dctx->expected = ZSTD_blockHeaderSize; + dctx->previousDstEnd = (char *)dst + rSize; + } + return rSize; + } + case ZSTDds_checkChecksum: { + U32 const h32 = (U32)xxh64_digest(&dctx->xxhState); + U32 const check32 = ZSTD_readLE32(src); /* srcSize == 4, guaranteed by dctx->expected */ + if (check32 != h32) + return ERROR(checksum_wrong); + dctx->expected = 0; + dctx->stage = ZSTDds_getFrameHeaderSize; + return 0; + } + case ZSTDds_decodeSkippableHeader: { + memcpy(dctx->headerBuffer + ZSTD_frameHeaderSize_prefix, src, dctx->expected); + dctx->expected = ZSTD_readLE32(dctx->headerBuffer + 4); + dctx->stage = ZSTDds_skipFrame; + return 0; + } + case ZSTDds_skipFrame: { + dctx->expected = 0; + dctx->stage = ZSTDds_getFrameHeaderSize; + return 0; + } + default: + return ERROR(GENERIC); /* impossible */ + } +} + +static size_t ZSTD_refDictContent(ZSTD_DCtx *dctx, const void *dict, size_t dictSize) +{ + dctx->dictEnd = dctx->previousDstEnd; + dctx->vBase = (const char *)dict - ((const char *)(dctx->previousDstEnd) - (const char *)(dctx->base)); + dctx->base = dict; + dctx->previousDstEnd = (const char *)dict + dictSize; + return 0; +} + +/* ZSTD_loadEntropy() : + * dict : must point at beginning of a valid zstd dictionary + * @return : size of entropy tables read */ +static size_t ZSTD_loadEntropy(ZSTD_entropyTables_t *entropy, const void *const dict, size_t const dictSize) +{ + const BYTE *dictPtr = (const BYTE *)dict; + const BYTE *const dictEnd = dictPtr + dictSize; + + if (dictSize <= 8) + return ERROR(dictionary_corrupted); + dictPtr += 8; /* skip header = magic + dictID */ + + { + size_t const hSize = HUF_readDTableX4_wksp(entropy->hufTable, dictPtr, dictEnd - dictPtr, entropy->workspace, sizeof(entropy->workspace)); + if (HUF_isError(hSize)) + return ERROR(dictionary_corrupted); + dictPtr += hSize; + } + + { + short offcodeNCount[MaxOff + 1]; + U32 offcodeMaxValue = MaxOff, offcodeLog; + size_t const offcodeHeaderSize = FSE_readNCount(offcodeNCount, &offcodeMaxValue, &offcodeLog, dictPtr, dictEnd - dictPtr); + if (FSE_isError(offcodeHeaderSize)) + return ERROR(dictionary_corrupted); + if (offcodeLog > OffFSELog) + return ERROR(dictionary_corrupted); + CHECK_E(FSE_buildDTable_wksp(entropy->OFTable, offcodeNCount, offcodeMaxValue, offcodeLog, entropy->workspace, sizeof(entropy->workspace)), dictionary_corrupted); + dictPtr += offcodeHeaderSize; + } + + { + short matchlengthNCount[MaxML + 1]; + unsigned matchlengthMaxValue = MaxML, matchlengthLog; + size_t const matchlengthHeaderSize = FSE_readNCount(matchlengthNCount, &matchlengthMaxValue, &matchlengthLog, dictPtr, dictEnd - dictPtr); + if (FSE_isError(matchlengthHeaderSize)) + return ERROR(dictionary_corrupted); + if (matchlengthLog > MLFSELog) + return ERROR(dictionary_corrupted); + CHECK_E(FSE_buildDTable_wksp(entropy->MLTable, matchlengthNCount, matchlengthMaxValue, matchlengthLog, entropy->workspace, sizeof(entropy->workspace)), dictionary_corrupted); + dictPtr += matchlengthHeaderSize; + } + + { + short litlengthNCount[MaxLL + 1]; + unsigned litlengthMaxValue = MaxLL, litlengthLog; + size_t const litlengthHeaderSize = FSE_readNCount(litlengthNCount, &litlengthMaxValue, &litlengthLog, dictPtr, dictEnd - dictPtr); + if (FSE_isError(litlengthHeaderSize)) + return ERROR(dictionary_corrupted); + if (litlengthLog > LLFSELog) + return ERROR(dictionary_corrupted); + CHECK_E(FSE_buildDTable_wksp(entropy->LLTable, litlengthNCount, litlengthMaxValue, litlengthLog, entropy->workspace, sizeof(entropy->workspace)), dictionary_corrupted); + dictPtr += litlengthHeaderSize; + } + + if (dictPtr + 12 > dictEnd) + return ERROR(dictionary_corrupted); + { + int i; + size_t const dictContentSize = (size_t)(dictEnd - (dictPtr + 12)); + for (i = 0; i < 3; i++) { + U32 const rep = ZSTD_readLE32(dictPtr); + dictPtr += 4; + if (rep == 0 || rep >= dictContentSize) + return ERROR(dictionary_corrupted); + entropy->rep[i] = rep; + } + } + + return dictPtr - (const BYTE *)dict; +} + +static size_t ZSTD_decompress_insertDictionary(ZSTD_DCtx *dctx, const void *dict, size_t dictSize) +{ + if (dictSize < 8) + return ZSTD_refDictContent(dctx, dict, dictSize); + { + U32 const magic = ZSTD_readLE32(dict); + if (magic != ZSTD_DICT_MAGIC) { + return ZSTD_refDictContent(dctx, dict, dictSize); /* pure content mode */ + } + } + dctx->dictID = ZSTD_readLE32((const char *)dict + 4); + + /* load entropy tables */ + { + size_t const eSize = ZSTD_loadEntropy(&dctx->entropy, dict, dictSize); + if (ZSTD_isError(eSize)) + return ERROR(dictionary_corrupted); + dict = (const char *)dict + eSize; + dictSize -= eSize; + } + dctx->litEntropy = dctx->fseEntropy = 1; + + /* reference dictionary content */ + return ZSTD_refDictContent(dctx, dict, dictSize); +} + +size_t ZSTD_decompressBegin_usingDict(ZSTD_DCtx *dctx, const void *dict, size_t dictSize) +{ + CHECK_F(ZSTD_decompressBegin(dctx)); + if (dict && dictSize) + CHECK_E(ZSTD_decompress_insertDictionary(dctx, dict, dictSize), dictionary_corrupted); + return 0; +} + +/* ====== ZSTD_DDict ====== */ + +struct ZSTD_DDict_s { + void *dictBuffer; + const void *dictContent; + size_t dictSize; + ZSTD_entropyTables_t entropy; + U32 dictID; + U32 entropyPresent; + ZSTD_customMem cMem; +}; /* typedef'd to ZSTD_DDict within "zstd.h" */ + +size_t ZSTD_DDictWorkspaceBound(void) { return ZSTD_ALIGN(sizeof(ZSTD_stack)) + ZSTD_ALIGN(sizeof(ZSTD_DDict)); } + +static const void *ZSTD_DDictDictContent(const ZSTD_DDict *ddict) { return ddict->dictContent; } + +static size_t ZSTD_DDictDictSize(const ZSTD_DDict *ddict) { return ddict->dictSize; } + +static void ZSTD_refDDict(ZSTD_DCtx *dstDCtx, const ZSTD_DDict *ddict) +{ + ZSTD_decompressBegin(dstDCtx); /* init */ + if (ddict) { /* support refDDict on NULL */ + dstDCtx->dictID = ddict->dictID; + dstDCtx->base = ddict->dictContent; + dstDCtx->vBase = ddict->dictContent; + dstDCtx->dictEnd = (const BYTE *)ddict->dictContent + ddict->dictSize; + dstDCtx->previousDstEnd = dstDCtx->dictEnd; + if (ddict->entropyPresent) { + dstDCtx->litEntropy = 1; + dstDCtx->fseEntropy = 1; + dstDCtx->LLTptr = ddict->entropy.LLTable; + dstDCtx->MLTptr = ddict->entropy.MLTable; + dstDCtx->OFTptr = ddict->entropy.OFTable; + dstDCtx->HUFptr = ddict->entropy.hufTable; + dstDCtx->entropy.rep[0] = ddict->entropy.rep[0]; + dstDCtx->entropy.rep[1] = ddict->entropy.rep[1]; + dstDCtx->entropy.rep[2] = ddict->entropy.rep[2]; + } else { + dstDCtx->litEntropy = 0; + dstDCtx->fseEntropy = 0; + } + } +} + +static size_t ZSTD_loadEntropy_inDDict(ZSTD_DDict *ddict) +{ + ddict->dictID = 0; + ddict->entropyPresent = 0; + if (ddict->dictSize < 8) + return 0; + { + U32 const magic = ZSTD_readLE32(ddict->dictContent); + if (magic != ZSTD_DICT_MAGIC) + return 0; /* pure content mode */ + } + ddict->dictID = ZSTD_readLE32((const char *)ddict->dictContent + 4); + + /* load entropy tables */ + CHECK_E(ZSTD_loadEntropy(&ddict->entropy, ddict->dictContent, ddict->dictSize), dictionary_corrupted); + ddict->entropyPresent = 1; + return 0; +} + +static ZSTD_DDict *ZSTD_createDDict_advanced(const void *dict, size_t dictSize, unsigned byReference, ZSTD_customMem customMem) +{ + if (!customMem.customAlloc || !customMem.customFree) + return NULL; + + { + ZSTD_DDict *const ddict = (ZSTD_DDict *)ZSTD_malloc(sizeof(ZSTD_DDict), customMem); + if (!ddict) + return NULL; + ddict->cMem = customMem; + + if ((byReference) || (!dict) || (!dictSize)) { + ddict->dictBuffer = NULL; + ddict->dictContent = dict; + } else { + void *const internalBuffer = ZSTD_malloc(dictSize, customMem); + if (!internalBuffer) { + ZSTD_freeDDict(ddict); + return NULL; + } + memcpy(internalBuffer, dict, dictSize); + ddict->dictBuffer = internalBuffer; + ddict->dictContent = internalBuffer; + } + ddict->dictSize = dictSize; + ddict->entropy.hufTable[0] = (HUF_DTable)((HufLog)*0x1000001); /* cover both little and big endian */ + /* parse dictionary content */ + { + size_t const errorCode = ZSTD_loadEntropy_inDDict(ddict); + if (ZSTD_isError(errorCode)) { + ZSTD_freeDDict(ddict); + return NULL; + } + } + + return ddict; + } +} + +/*! ZSTD_initDDict() : +* Create a digested dictionary, to start decompression without startup delay. +* `dict` content is copied inside DDict. +* Consequently, `dict` can be released after `ZSTD_DDict` creation */ +ZSTD_DDict *ZSTD_initDDict(const void *dict, size_t dictSize, void *workspace, size_t workspaceSize) +{ + ZSTD_customMem const stackMem = ZSTD_initStack(workspace, workspaceSize); + return ZSTD_createDDict_advanced(dict, dictSize, 1, stackMem); +} + +size_t ZSTD_freeDDict(ZSTD_DDict *ddict) +{ + if (ddict == NULL) + return 0; /* support free on NULL */ + { + ZSTD_customMem const cMem = ddict->cMem; + ZSTD_free(ddict->dictBuffer, cMem); + ZSTD_free(ddict, cMem); + return 0; + } +} + +/*! ZSTD_getDictID_fromDict() : + * Provides the dictID stored within dictionary. + * if @return == 0, the dictionary is not conformant with Zstandard specification. + * It can still be loaded, but as a content-only dictionary. */ +unsigned ZSTD_getDictID_fromDict(const void *dict, size_t dictSize) +{ + if (dictSize < 8) + return 0; + if (ZSTD_readLE32(dict) != ZSTD_DICT_MAGIC) + return 0; + return ZSTD_readLE32((const char *)dict + 4); +} + +/*! ZSTD_getDictID_fromDDict() : + * Provides the dictID of the dictionary loaded into `ddict`. + * If @return == 0, the dictionary is not conformant to Zstandard specification, or empty. + * Non-conformant dictionaries can still be loaded, but as content-only dictionaries. */ +unsigned ZSTD_getDictID_fromDDict(const ZSTD_DDict *ddict) +{ + if (ddict == NULL) + return 0; + return ZSTD_getDictID_fromDict(ddict->dictContent, ddict->dictSize); +} + +/*! ZSTD_getDictID_fromFrame() : + * Provides the dictID required to decompressed the frame stored within `src`. + * If @return == 0, the dictID could not be decoded. + * This could for one of the following reasons : + * - The frame does not require a dictionary to be decoded (most common case). + * - The frame was built with dictID intentionally removed. Whatever dictionary is necessary is a hidden information. + * Note : this use case also happens when using a non-conformant dictionary. + * - `srcSize` is too small, and as a result, the frame header could not be decoded (only possible if `srcSize < ZSTD_FRAMEHEADERSIZE_MAX`). + * - This is not a Zstandard frame. + * When identifying the exact failure cause, it's possible to used ZSTD_getFrameParams(), which will provide a more precise error code. */ +unsigned ZSTD_getDictID_fromFrame(const void *src, size_t srcSize) +{ + ZSTD_frameParams zfp = {0, 0, 0, 0}; + size_t const hError = ZSTD_getFrameParams(&zfp, src, srcSize); + if (ZSTD_isError(hError)) + return 0; + return zfp.dictID; +} + +/*! ZSTD_decompress_usingDDict() : +* Decompression using a pre-digested Dictionary +* Use dictionary without significant overhead. */ +size_t ZSTD_decompress_usingDDict(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, const void *src, size_t srcSize, const ZSTD_DDict *ddict) +{ + /* pass content and size in case legacy frames are encountered */ + return ZSTD_decompressMultiFrame(dctx, dst, dstCapacity, src, srcSize, NULL, 0, ddict); +} + +/*===================================== +* Streaming decompression +*====================================*/ + +typedef enum { zdss_init, zdss_loadHeader, zdss_read, zdss_load, zdss_flush } ZSTD_dStreamStage; + +/* *** Resource management *** */ +struct ZSTD_DStream_s { + ZSTD_DCtx *dctx; + ZSTD_DDict *ddictLocal; + const ZSTD_DDict *ddict; + ZSTD_frameParams fParams; + ZSTD_dStreamStage stage; + char *inBuff; + size_t inBuffSize; + size_t inPos; + size_t maxWindowSize; + char *outBuff; + size_t outBuffSize; + size_t outStart; + size_t outEnd; + size_t blockSize; + BYTE headerBuffer[ZSTD_FRAMEHEADERSIZE_MAX]; /* tmp buffer to store frame header */ + size_t lhSize; + ZSTD_customMem customMem; + void *legacyContext; + U32 previousLegacyVersion; + U32 legacyVersion; + U32 hostageByte; +}; /* typedef'd to ZSTD_DStream within "zstd.h" */ + +size_t ZSTD_DStreamWorkspaceBound(size_t maxWindowSize) +{ + size_t const blockSize = MIN(maxWindowSize, ZSTD_BLOCKSIZE_ABSOLUTEMAX); + size_t const inBuffSize = blockSize; + size_t const outBuffSize = maxWindowSize + blockSize + WILDCOPY_OVERLENGTH * 2; + return ZSTD_DCtxWorkspaceBound() + ZSTD_ALIGN(sizeof(ZSTD_DStream)) + ZSTD_ALIGN(inBuffSize) + ZSTD_ALIGN(outBuffSize); +} + +static ZSTD_DStream *ZSTD_createDStream_advanced(ZSTD_customMem customMem) +{ + ZSTD_DStream *zds; + + if (!customMem.customAlloc || !customMem.customFree) + return NULL; + + zds = (ZSTD_DStream *)ZSTD_malloc(sizeof(ZSTD_DStream), customMem); + if (zds == NULL) + return NULL; + memset(zds, 0, sizeof(ZSTD_DStream)); + memcpy(&zds->customMem, &customMem, sizeof(ZSTD_customMem)); + zds->dctx = ZSTD_createDCtx_advanced(customMem); + if (zds->dctx == NULL) { + ZSTD_freeDStream(zds); + return NULL; + } + zds->stage = zdss_init; + zds->maxWindowSize = ZSTD_MAXWINDOWSIZE_DEFAULT; + return zds; +} + +ZSTD_DStream *ZSTD_initDStream(size_t maxWindowSize, void *workspace, size_t workspaceSize) +{ + ZSTD_customMem const stackMem = ZSTD_initStack(workspace, workspaceSize); + ZSTD_DStream *zds = ZSTD_createDStream_advanced(stackMem); + if (!zds) { + return NULL; + } + + zds->maxWindowSize = maxWindowSize; + zds->stage = zdss_loadHeader; + zds->lhSize = zds->inPos = zds->outStart = zds->outEnd = 0; + ZSTD_freeDDict(zds->ddictLocal); + zds->ddictLocal = NULL; + zds->ddict = zds->ddictLocal; + zds->legacyVersion = 0; + zds->hostageByte = 0; + + { + size_t const blockSize = MIN(zds->maxWindowSize, ZSTD_BLOCKSIZE_ABSOLUTEMAX); + size_t const neededOutSize = zds->maxWindowSize + blockSize + WILDCOPY_OVERLENGTH * 2; + + zds->inBuff = (char *)ZSTD_malloc(blockSize, zds->customMem); + zds->inBuffSize = blockSize; + zds->outBuff = (char *)ZSTD_malloc(neededOutSize, zds->customMem); + zds->outBuffSize = neededOutSize; + if (zds->inBuff == NULL || zds->outBuff == NULL) { + ZSTD_freeDStream(zds); + return NULL; + } + } + return zds; +} + +ZSTD_DStream *ZSTD_initDStream_usingDDict(size_t maxWindowSize, const ZSTD_DDict *ddict, void *workspace, size_t workspaceSize) +{ + ZSTD_DStream *zds = ZSTD_initDStream(maxWindowSize, workspace, workspaceSize); + if (zds) { + zds->ddict = ddict; + } + return zds; +} + +size_t ZSTD_freeDStream(ZSTD_DStream *zds) +{ + if (zds == NULL) + return 0; /* support free on null */ + { + ZSTD_customMem const cMem = zds->customMem; + ZSTD_freeDCtx(zds->dctx); + zds->dctx = NULL; + ZSTD_freeDDict(zds->ddictLocal); + zds->ddictLocal = NULL; + ZSTD_free(zds->inBuff, cMem); + zds->inBuff = NULL; + ZSTD_free(zds->outBuff, cMem); + zds->outBuff = NULL; + ZSTD_free(zds, cMem); + return 0; + } +} + +/* *** Initialization *** */ + +size_t ZSTD_DStreamInSize(void) { return ZSTD_BLOCKSIZE_ABSOLUTEMAX + ZSTD_blockHeaderSize; } +size_t ZSTD_DStreamOutSize(void) { return ZSTD_BLOCKSIZE_ABSOLUTEMAX; } + +size_t ZSTD_resetDStream(ZSTD_DStream *zds) +{ + zds->stage = zdss_loadHeader; + zds->lhSize = zds->inPos = zds->outStart = zds->outEnd = 0; + zds->legacyVersion = 0; + zds->hostageByte = 0; + return ZSTD_frameHeaderSize_prefix; +} + +/* ***** Decompression ***** */ + +ZSTD_STATIC size_t ZSTD_limitCopy(void *dst, size_t dstCapacity, const void *src, size_t srcSize) +{ + size_t const length = MIN(dstCapacity, srcSize); + memcpy(dst, src, length); + return length; +} + +size_t ZSTD_decompressStream(ZSTD_DStream *zds, ZSTD_outBuffer *output, ZSTD_inBuffer *input) +{ + const char *const istart = (const char *)(input->src) + input->pos; + const char *const iend = (const char *)(input->src) + input->size; + const char *ip = istart; + char *const ostart = (char *)(output->dst) + output->pos; + char *const oend = (char *)(output->dst) + output->size; + char *op = ostart; + U32 someMoreWork = 1; + + while (someMoreWork) { + switch (zds->stage) { + case zdss_init: + ZSTD_resetDStream(zds); /* transparent reset on starting decoding a new frame */ + /* fall-through */ + + case zdss_loadHeader: { + size_t const hSize = ZSTD_getFrameParams(&zds->fParams, zds->headerBuffer, zds->lhSize); + if (ZSTD_isError(hSize)) + return hSize; + if (hSize != 0) { /* need more input */ + size_t const toLoad = hSize - zds->lhSize; /* if hSize!=0, hSize > zds->lhSize */ + if (toLoad > (size_t)(iend - ip)) { /* not enough input to load full header */ + memcpy(zds->headerBuffer + zds->lhSize, ip, iend - ip); + zds->lhSize += iend - ip; + input->pos = input->size; + return (MAX(ZSTD_frameHeaderSize_min, hSize) - zds->lhSize) + + ZSTD_blockHeaderSize; /* remaining header bytes + next block header */ + } + memcpy(zds->headerBuffer + zds->lhSize, ip, toLoad); + zds->lhSize = hSize; + ip += toLoad; + break; + } + + /* check for single-pass mode opportunity */ + if (zds->fParams.frameContentSize && zds->fParams.windowSize /* skippable frame if == 0 */ + && (U64)(size_t)(oend - op) >= zds->fParams.frameContentSize) { + size_t const cSize = ZSTD_findFrameCompressedSize(istart, iend - istart); + if (cSize <= (size_t)(iend - istart)) { + size_t const decompressedSize = ZSTD_decompress_usingDDict(zds->dctx, op, oend - op, istart, cSize, zds->ddict); + if (ZSTD_isError(decompressedSize)) + return decompressedSize; + ip = istart + cSize; + op += decompressedSize; + zds->dctx->expected = 0; + zds->stage = zdss_init; + someMoreWork = 0; + break; + } + } + + /* Consume header */ + ZSTD_refDDict(zds->dctx, zds->ddict); + { + size_t const h1Size = ZSTD_nextSrcSizeToDecompress(zds->dctx); /* == ZSTD_frameHeaderSize_prefix */ + CHECK_F(ZSTD_decompressContinue(zds->dctx, NULL, 0, zds->headerBuffer, h1Size)); + { + size_t const h2Size = ZSTD_nextSrcSizeToDecompress(zds->dctx); + CHECK_F(ZSTD_decompressContinue(zds->dctx, NULL, 0, zds->headerBuffer + h1Size, h2Size)); + } + } + + zds->fParams.windowSize = MAX(zds->fParams.windowSize, 1U << ZSTD_WINDOWLOG_ABSOLUTEMIN); + if (zds->fParams.windowSize > zds->maxWindowSize) + return ERROR(frameParameter_windowTooLarge); + + /* Buffers are preallocated, but double check */ + { + size_t const blockSize = MIN(zds->maxWindowSize, ZSTD_BLOCKSIZE_ABSOLUTEMAX); + size_t const neededOutSize = zds->maxWindowSize + blockSize + WILDCOPY_OVERLENGTH * 2; + if (zds->inBuffSize < blockSize) { + return ERROR(GENERIC); + } + if (zds->outBuffSize < neededOutSize) { + return ERROR(GENERIC); + } + zds->blockSize = blockSize; + } + zds->stage = zdss_read; + } + /* pass-through */ + + case zdss_read: { + size_t const neededInSize = ZSTD_nextSrcSizeToDecompress(zds->dctx); + if (neededInSize == 0) { /* end of frame */ + zds->stage = zdss_init; + someMoreWork = 0; + break; + } + if ((size_t)(iend - ip) >= neededInSize) { /* decode directly from src */ + const int isSkipFrame = ZSTD_isSkipFrame(zds->dctx); + size_t const decodedSize = ZSTD_decompressContinue(zds->dctx, zds->outBuff + zds->outStart, + (isSkipFrame ? 0 : zds->outBuffSize - zds->outStart), ip, neededInSize); + if (ZSTD_isError(decodedSize)) + return decodedSize; + ip += neededInSize; + if (!decodedSize && !isSkipFrame) + break; /* this was just a header */ + zds->outEnd = zds->outStart + decodedSize; + zds->stage = zdss_flush; + break; + } + if (ip == iend) { + someMoreWork = 0; + break; + } /* no more input */ + zds->stage = zdss_load; + /* pass-through */ + } + + case zdss_load: { + size_t const neededInSize = ZSTD_nextSrcSizeToDecompress(zds->dctx); + size_t const toLoad = neededInSize - zds->inPos; /* should always be <= remaining space within inBuff */ + size_t loadedSize; + if (toLoad > zds->inBuffSize - zds->inPos) + return ERROR(corruption_detected); /* should never happen */ + loadedSize = ZSTD_limitCopy(zds->inBuff + zds->inPos, toLoad, ip, iend - ip); + ip += loadedSize; + zds->inPos += loadedSize; + if (loadedSize < toLoad) { + someMoreWork = 0; + break; + } /* not enough input, wait for more */ + + /* decode loaded input */ + { + const int isSkipFrame = ZSTD_isSkipFrame(zds->dctx); + size_t const decodedSize = ZSTD_decompressContinue(zds->dctx, zds->outBuff + zds->outStart, zds->outBuffSize - zds->outStart, + zds->inBuff, neededInSize); + if (ZSTD_isError(decodedSize)) + return decodedSize; + zds->inPos = 0; /* input is consumed */ + if (!decodedSize && !isSkipFrame) { + zds->stage = zdss_read; + break; + } /* this was just a header */ + zds->outEnd = zds->outStart + decodedSize; + zds->stage = zdss_flush; + /* pass-through */ + } + } + + case zdss_flush: { + size_t const toFlushSize = zds->outEnd - zds->outStart; + size_t const flushedSize = ZSTD_limitCopy(op, oend - op, zds->outBuff + zds->outStart, toFlushSize); + op += flushedSize; + zds->outStart += flushedSize; + if (flushedSize == toFlushSize) { /* flush completed */ + zds->stage = zdss_read; + if (zds->outStart + zds->blockSize > zds->outBuffSize) + zds->outStart = zds->outEnd = 0; + break; + } + /* cannot complete flush */ + someMoreWork = 0; + break; + } + default: + return ERROR(GENERIC); /* impossible */ + } + } + + /* result */ + input->pos += (size_t)(ip - istart); + output->pos += (size_t)(op - ostart); + { + size_t nextSrcSizeHint = ZSTD_nextSrcSizeToDecompress(zds->dctx); + if (!nextSrcSizeHint) { /* frame fully decoded */ + if (zds->outEnd == zds->outStart) { /* output fully flushed */ + if (zds->hostageByte) { + if (input->pos >= input->size) { + zds->stage = zdss_read; + return 1; + } /* can't release hostage (not present) */ + input->pos++; /* release hostage */ + } + return 0; + } + if (!zds->hostageByte) { /* output not fully flushed; keep last byte as hostage; will be released when all output is flushed */ + input->pos--; /* note : pos > 0, otherwise, impossible to finish reading last block */ + zds->hostageByte = 1; + } + return 1; + } + nextSrcSizeHint += ZSTD_blockHeaderSize * (ZSTD_nextInputType(zds->dctx) == ZSTDnit_block); /* preload header of next block */ + if (zds->inPos > nextSrcSizeHint) + return ERROR(GENERIC); /* should never happen */ + nextSrcSizeHint -= zds->inPos; /* already loaded*/ + return nextSrcSizeHint; + } +} + +EXPORT_SYMBOL(ZSTD_DCtxWorkspaceBound); +EXPORT_SYMBOL(ZSTD_initDCtx); +EXPORT_SYMBOL(ZSTD_decompressDCtx); +EXPORT_SYMBOL(ZSTD_decompress_usingDict); + +EXPORT_SYMBOL(ZSTD_DDictWorkspaceBound); +EXPORT_SYMBOL(ZSTD_initDDict); +EXPORT_SYMBOL(ZSTD_decompress_usingDDict); + +EXPORT_SYMBOL(ZSTD_DStreamWorkspaceBound); +EXPORT_SYMBOL(ZSTD_initDStream); +EXPORT_SYMBOL(ZSTD_initDStream_usingDDict); +EXPORT_SYMBOL(ZSTD_resetDStream); +EXPORT_SYMBOL(ZSTD_decompressStream); +EXPORT_SYMBOL(ZSTD_DStreamInSize); +EXPORT_SYMBOL(ZSTD_DStreamOutSize); + +EXPORT_SYMBOL(ZSTD_findFrameCompressedSize); +EXPORT_SYMBOL(ZSTD_getFrameContentSize); +EXPORT_SYMBOL(ZSTD_findDecompressedSize); + +EXPORT_SYMBOL(ZSTD_isFrame); +EXPORT_SYMBOL(ZSTD_getDictID_fromDict); +EXPORT_SYMBOL(ZSTD_getDictID_fromDDict); +EXPORT_SYMBOL(ZSTD_getDictID_fromFrame); + +EXPORT_SYMBOL(ZSTD_getFrameParams); +EXPORT_SYMBOL(ZSTD_decompressBegin); +EXPORT_SYMBOL(ZSTD_decompressBegin_usingDict); +EXPORT_SYMBOL(ZSTD_copyDCtx); +EXPORT_SYMBOL(ZSTD_nextSrcSizeToDecompress); +EXPORT_SYMBOL(ZSTD_decompressContinue); +EXPORT_SYMBOL(ZSTD_nextInputType); + +EXPORT_SYMBOL(ZSTD_decompressBlock); +EXPORT_SYMBOL(ZSTD_insertBlock); diff --git a/lib/zstd/entropy_common.c b/lib/zstd/entropy_common.c new file mode 100644 index 00000000000..071fef997e7 --- /dev/null +++ b/lib/zstd/entropy_common.c @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause) +/* + * Common functions of New Generation Entropy library + * Copyright (C) 2016, Yann Collet. + * + * You can contact the author at : + * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy + */ + +/* ************************************* +* Dependencies +***************************************/ +#include "error_private.h" /* ERR_*, ERROR */ +#include "fse.h" +#include "huf.h" +#include "mem.h" + +/*=== Version ===*/ +unsigned FSE_versionNumber(void) { return FSE_VERSION_NUMBER; } + +/*=== Error Management ===*/ +unsigned FSE_isError(size_t code) { return ERR_isError(code); } + +unsigned HUF_isError(size_t code) { return ERR_isError(code); } + +/*-************************************************************** +* FSE NCount encoding-decoding +****************************************************************/ +size_t FSE_readNCount(short *normalizedCounter, unsigned *maxSVPtr, unsigned *tableLogPtr, const void *headerBuffer, size_t hbSize) +{ + const BYTE *const istart = (const BYTE *)headerBuffer; + const BYTE *const iend = istart + hbSize; + const BYTE *ip = istart; + int nbBits; + int remaining; + int threshold; + U32 bitStream; + int bitCount; + unsigned charnum = 0; + int previous0 = 0; + + if (hbSize < 4) + return ERROR(srcSize_wrong); + bitStream = ZSTD_readLE32(ip); + nbBits = (bitStream & 0xF) + FSE_MIN_TABLELOG; /* extract tableLog */ + if (nbBits > FSE_TABLELOG_ABSOLUTE_MAX) + return ERROR(tableLog_tooLarge); + bitStream >>= 4; + bitCount = 4; + *tableLogPtr = nbBits; + remaining = (1 << nbBits) + 1; + threshold = 1 << nbBits; + nbBits++; + + while ((remaining > 1) & (charnum <= *maxSVPtr)) { + if (previous0) { + unsigned n0 = charnum; + while ((bitStream & 0xFFFF) == 0xFFFF) { + n0 += 24; + if (ip < iend - 5) { + ip += 2; + bitStream = ZSTD_readLE32(ip) >> bitCount; + } else { + bitStream >>= 16; + bitCount += 16; + } + } + while ((bitStream & 3) == 3) { + n0 += 3; + bitStream >>= 2; + bitCount += 2; + } + n0 += bitStream & 3; + bitCount += 2; + if (n0 > *maxSVPtr) + return ERROR(maxSymbolValue_tooSmall); + while (charnum < n0) + normalizedCounter[charnum++] = 0; + if ((ip <= iend - 7) || (ip + (bitCount >> 3) <= iend - 4)) { + ip += bitCount >> 3; + bitCount &= 7; + bitStream = ZSTD_readLE32(ip) >> bitCount; + } else { + bitStream >>= 2; + } + } + { + int const max = (2 * threshold - 1) - remaining; + int count; + + if ((bitStream & (threshold - 1)) < (U32)max) { + count = bitStream & (threshold - 1); + bitCount += nbBits - 1; + } else { + count = bitStream & (2 * threshold - 1); + if (count >= threshold) + count -= max; + bitCount += nbBits; + } + + count--; /* extra accuracy */ + remaining -= count < 0 ? -count : count; /* -1 means +1 */ + normalizedCounter[charnum++] = (short)count; + previous0 = !count; + while (remaining < threshold) { + nbBits--; + threshold >>= 1; + } + + if ((ip <= iend - 7) || (ip + (bitCount >> 3) <= iend - 4)) { + ip += bitCount >> 3; + bitCount &= 7; + } else { + bitCount -= (int)(8 * (iend - 4 - ip)); + ip = iend - 4; + } + bitStream = ZSTD_readLE32(ip) >> (bitCount & 31); + } + } /* while ((remaining>1) & (charnum<=*maxSVPtr)) */ + if (remaining != 1) + return ERROR(corruption_detected); + if (bitCount > 32) + return ERROR(corruption_detected); + *maxSVPtr = charnum - 1; + + ip += (bitCount + 7) >> 3; + return ip - istart; +} + +/*! HUF_readStats() : + Read compact Huffman tree, saved by HUF_writeCTable(). + `huffWeight` is destination buffer. + `rankStats` is assumed to be a table of at least HUF_TABLELOG_MAX U32. + @return : size read from `src` , or an error Code . + Note : Needed by HUF_readCTable() and HUF_readDTableX?() . +*/ +size_t HUF_readStats_wksp(BYTE *huffWeight, size_t hwSize, U32 *rankStats, U32 *nbSymbolsPtr, U32 *tableLogPtr, const void *src, size_t srcSize, void *workspace, size_t workspaceSize) +{ + U32 weightTotal; + const BYTE *ip = (const BYTE *)src; + size_t iSize; + size_t oSize; + + if (!srcSize) + return ERROR(srcSize_wrong); + iSize = ip[0]; + /* memset(huffWeight, 0, hwSize); */ /* is not necessary, even though some analyzer complain ... */ + + if (iSize >= 128) { /* special header */ + oSize = iSize - 127; + iSize = ((oSize + 1) / 2); + if (iSize + 1 > srcSize) + return ERROR(srcSize_wrong); + if (oSize >= hwSize) + return ERROR(corruption_detected); + ip += 1; + { + U32 n; + for (n = 0; n < oSize; n += 2) { + huffWeight[n] = ip[n / 2] >> 4; + huffWeight[n + 1] = ip[n / 2] & 15; + } + } + } else { /* header compressed with FSE (normal case) */ + if (iSize + 1 > srcSize) + return ERROR(srcSize_wrong); + oSize = FSE_decompress_wksp(huffWeight, hwSize - 1, ip + 1, iSize, 6, workspace, workspaceSize); /* max (hwSize-1) values decoded, as last one is implied */ + if (FSE_isError(oSize)) + return oSize; + } + + /* collect weight stats */ + memset(rankStats, 0, (HUF_TABLELOG_MAX + 1) * sizeof(U32)); + weightTotal = 0; + { + U32 n; + for (n = 0; n < oSize; n++) { + if (huffWeight[n] >= HUF_TABLELOG_MAX) + return ERROR(corruption_detected); + rankStats[huffWeight[n]]++; + weightTotal += (1 << huffWeight[n]) >> 1; + } + } + if (weightTotal == 0) + return ERROR(corruption_detected); + + /* get last non-null symbol weight (implied, total must be 2^n) */ + { + U32 const tableLog = BIT_highbit32(weightTotal) + 1; + if (tableLog > HUF_TABLELOG_MAX) + return ERROR(corruption_detected); + *tableLogPtr = tableLog; + /* determine last weight */ + { + U32 const total = 1 << tableLog; + U32 const rest = total - weightTotal; + U32 const verif = 1 << BIT_highbit32(rest); + U32 const lastWeight = BIT_highbit32(rest) + 1; + if (verif != rest) + return ERROR(corruption_detected); /* last value must be a clean power of 2 */ + huffWeight[oSize] = (BYTE)lastWeight; + rankStats[lastWeight]++; + } + } + + /* check tree construction validity */ + if ((rankStats[1] < 2) || (rankStats[1] & 1)) + return ERROR(corruption_detected); /* by construction : at least 2 elts of rank 1, must be even */ + + /* results */ + *nbSymbolsPtr = (U32)(oSize + 1); + return iSize + 1; +} diff --git a/lib/zstd/error_private.h b/lib/zstd/error_private.h new file mode 100644 index 00000000000..d4824e25b2a --- /dev/null +++ b/lib/zstd/error_private.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause-Clear) */ +/** + * Copyright (c) 2016-present, Yann Collet, Facebook, Inc. + * All rights reserved. + */ + +/* Note : this module is expected to remain private, do not expose it */ + +#ifndef ERROR_H_MODULE +#define ERROR_H_MODULE + +/* **************************************** +* Dependencies +******************************************/ +#include <linux/types.h> /* size_t */ +#include <linux/zstd.h> /* enum list */ + +/* **************************************** +* Compiler-specific +******************************************/ +#define ERR_STATIC static __attribute__((unused)) + +/*-**************************************** +* Customization (error_public.h) +******************************************/ +typedef ZSTD_ErrorCode ERR_enum; +#define PREFIX(name) ZSTD_error_##name + +/*-**************************************** +* Error codes handling +******************************************/ +#define ERROR(name) ((size_t)-PREFIX(name)) + +ERR_STATIC unsigned ERR_isError(size_t code) { return (code > ERROR(maxCode)); } + +ERR_STATIC ERR_enum ERR_getErrorCode(size_t code) +{ + if (!ERR_isError(code)) + return (ERR_enum)0; + return (ERR_enum)(0 - code); +} + +#endif /* ERROR_H_MODULE */ diff --git a/lib/zstd/fse.h b/lib/zstd/fse.h new file mode 100644 index 00000000000..42f80ff73ec --- /dev/null +++ b/lib/zstd/fse.h @@ -0,0 +1,545 @@ +/* SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause) */ +/* + * FSE : Finite State Entropy codec + * Public Prototypes declaration + * Copyright (C) 2013-2016, Yann Collet. + * + * You can contact the author at : + * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy + */ +#ifndef FSE_H +#define FSE_H + +/*-***************************************** +* Dependencies +******************************************/ +#include <linux/types.h> /* size_t, ptrdiff_t */ + +/*-***************************************** +* FSE_PUBLIC_API : control library symbols visibility +******************************************/ +#define FSE_PUBLIC_API + +/*------ Version ------*/ +#define FSE_VERSION_MAJOR 0 +#define FSE_VERSION_MINOR 9 +#define FSE_VERSION_RELEASE 0 + +#define FSE_LIB_VERSION FSE_VERSION_MAJOR.FSE_VERSION_MINOR.FSE_VERSION_RELEASE +#define FSE_QUOTE(str) #str +#define FSE_EXPAND_AND_QUOTE(str) FSE_QUOTE(str) +#define FSE_VERSION_STRING FSE_EXPAND_AND_QUOTE(FSE_LIB_VERSION) + +#define FSE_VERSION_NUMBER (FSE_VERSION_MAJOR * 100 * 100 + FSE_VERSION_MINOR * 100 + FSE_VERSION_RELEASE) +FSE_PUBLIC_API unsigned FSE_versionNumber(void); /**< library version number; to be used when checking dll version */ + +/*-***************************************** +* Tool functions +******************************************/ +FSE_PUBLIC_API size_t FSE_compressBound(size_t size); /* maximum compressed size */ + +/* Error Management */ +FSE_PUBLIC_API unsigned FSE_isError(size_t code); /* tells if a return value is an error code */ + +/*-***************************************** +* FSE detailed API +******************************************/ +/*! +FSE_compress() does the following: +1. count symbol occurrence from source[] into table count[] +2. normalize counters so that sum(count[]) == Power_of_2 (2^tableLog) +3. save normalized counters to memory buffer using writeNCount() +4. build encoding table 'CTable' from normalized counters +5. encode the data stream using encoding table 'CTable' + +FSE_decompress() does the following: +1. read normalized counters with readNCount() +2. build decoding table 'DTable' from normalized counters +3. decode the data stream using decoding table 'DTable' + +The following API allows targeting specific sub-functions for advanced tasks. +For example, it's possible to compress several blocks using the same 'CTable', +or to save and provide normalized distribution using external method. +*/ + +/* *** COMPRESSION *** */ +/*! FSE_optimalTableLog(): + dynamically downsize 'tableLog' when conditions are met. + It saves CPU time, by using smaller tables, while preserving or even improving compression ratio. + @return : recommended tableLog (necessarily <= 'maxTableLog') */ +FSE_PUBLIC_API unsigned FSE_optimalTableLog(unsigned maxTableLog, size_t srcSize, unsigned maxSymbolValue); + +/*! FSE_normalizeCount(): + normalize counts so that sum(count[]) == Power_of_2 (2^tableLog) + 'normalizedCounter' is a table of short, of minimum size (maxSymbolValue+1). + @return : tableLog, + or an errorCode, which can be tested using FSE_isError() */ +FSE_PUBLIC_API size_t FSE_normalizeCount(short *normalizedCounter, unsigned tableLog, const unsigned *count, size_t srcSize, unsigned maxSymbolValue); + +/*! FSE_NCountWriteBound(): + Provides the maximum possible size of an FSE normalized table, given 'maxSymbolValue' and 'tableLog'. + Typically useful for allocation purpose. */ +FSE_PUBLIC_API size_t FSE_NCountWriteBound(unsigned maxSymbolValue, unsigned tableLog); + +/*! FSE_writeNCount(): + Compactly save 'normalizedCounter' into 'buffer'. + @return : size of the compressed table, + or an errorCode, which can be tested using FSE_isError(). */ +FSE_PUBLIC_API size_t FSE_writeNCount(void *buffer, size_t bufferSize, const short *normalizedCounter, unsigned maxSymbolValue, unsigned tableLog); + +/*! Constructor and Destructor of FSE_CTable. + Note that FSE_CTable size depends on 'tableLog' and 'maxSymbolValue' */ +typedef unsigned FSE_CTable; /* don't allocate that. It's only meant to be more restrictive than void* */ + +/*! FSE_compress_usingCTable(): + Compress `src` using `ct` into `dst` which must be already allocated. + @return : size of compressed data (<= `dstCapacity`), + or 0 if compressed data could not fit into `dst`, + or an errorCode, which can be tested using FSE_isError() */ +FSE_PUBLIC_API size_t FSE_compress_usingCTable(void *dst, size_t dstCapacity, const void *src, size_t srcSize, const FSE_CTable *ct); + +/*! +Tutorial : +---------- +The first step is to count all symbols. FSE_count() does this job very fast. +Result will be saved into 'count', a table of unsigned int, which must be already allocated, and have 'maxSymbolValuePtr[0]+1' cells. +'src' is a table of bytes of size 'srcSize'. All values within 'src' MUST be <= maxSymbolValuePtr[0] +maxSymbolValuePtr[0] will be updated, with its real value (necessarily <= original value) +FSE_count() will return the number of occurrence of the most frequent symbol. +This can be used to know if there is a single symbol within 'src', and to quickly evaluate its compressibility. +If there is an error, the function will return an ErrorCode (which can be tested using FSE_isError()). + +The next step is to normalize the frequencies. +FSE_normalizeCount() will ensure that sum of frequencies is == 2 ^'tableLog'. +It also guarantees a minimum of 1 to any Symbol with frequency >= 1. +You can use 'tableLog'==0 to mean "use default tableLog value". +If you are unsure of which tableLog value to use, you can ask FSE_optimalTableLog(), +which will provide the optimal valid tableLog given sourceSize, maxSymbolValue, and a user-defined maximum (0 means "default"). + +The result of FSE_normalizeCount() will be saved into a table, +called 'normalizedCounter', which is a table of signed short. +'normalizedCounter' must be already allocated, and have at least 'maxSymbolValue+1' cells. +The return value is tableLog if everything proceeded as expected. +It is 0 if there is a single symbol within distribution. +If there is an error (ex: invalid tableLog value), the function will return an ErrorCode (which can be tested using FSE_isError()). + +'normalizedCounter' can be saved in a compact manner to a memory area using FSE_writeNCount(). +'buffer' must be already allocated. +For guaranteed success, buffer size must be at least FSE_headerBound(). +The result of the function is the number of bytes written into 'buffer'. +If there is an error, the function will return an ErrorCode (which can be tested using FSE_isError(); ex : buffer size too small). + +'normalizedCounter' can then be used to create the compression table 'CTable'. +The space required by 'CTable' must be already allocated, using FSE_createCTable(). +You can then use FSE_buildCTable() to fill 'CTable'. +If there is an error, both functions will return an ErrorCode (which can be tested using FSE_isError()). + +'CTable' can then be used to compress 'src', with FSE_compress_usingCTable(). +Similar to FSE_count(), the convention is that 'src' is assumed to be a table of char of size 'srcSize' +The function returns the size of compressed data (without header), necessarily <= `dstCapacity`. +If it returns '0', compressed data could not fit into 'dst'. +If there is an error, the function will return an ErrorCode (which can be tested using FSE_isError()). +*/ + +/* *** DECOMPRESSION *** */ + +/*! FSE_readNCount(): + Read compactly saved 'normalizedCounter' from 'rBuffer'. + @return : size read from 'rBuffer', + or an errorCode, which can be tested using FSE_isError(). + maxSymbolValuePtr[0] and tableLogPtr[0] will also be updated with their respective values */ +FSE_PUBLIC_API size_t FSE_readNCount(short *normalizedCounter, unsigned *maxSymbolValuePtr, unsigned *tableLogPtr, const void *rBuffer, size_t rBuffSize); + +/*! Constructor and Destructor of FSE_DTable. + Note that its size depends on 'tableLog' */ +typedef unsigned FSE_DTable; /* don't allocate that. It's just a way to be more restrictive than void* */ + +/*! FSE_buildDTable(): + Builds 'dt', which must be already allocated, using FSE_createDTable(). + return : 0, or an errorCode, which can be tested using FSE_isError() */ +FSE_PUBLIC_API size_t FSE_buildDTable_wksp(FSE_DTable *dt, const short *normalizedCounter, unsigned maxSymbolValue, unsigned tableLog, void *workspace, size_t workspaceSize); + +/*! FSE_decompress_usingDTable(): + Decompress compressed source `cSrc` of size `cSrcSize` using `dt` + into `dst` which must be already allocated. + @return : size of regenerated data (necessarily <= `dstCapacity`), + or an errorCode, which can be tested using FSE_isError() */ +FSE_PUBLIC_API size_t FSE_decompress_usingDTable(void *dst, size_t dstCapacity, const void *cSrc, size_t cSrcSize, const FSE_DTable *dt); + +/*! +Tutorial : +---------- +(Note : these functions only decompress FSE-compressed blocks. + If block is uncompressed, use memcpy() instead + If block is a single repeated byte, use memset() instead ) + +The first step is to obtain the normalized frequencies of symbols. +This can be performed by FSE_readNCount() if it was saved using FSE_writeNCount(). +'normalizedCounter' must be already allocated, and have at least 'maxSymbolValuePtr[0]+1' cells of signed short. +In practice, that means it's necessary to know 'maxSymbolValue' beforehand, +or size the table to handle worst case situations (typically 256). +FSE_readNCount() will provide 'tableLog' and 'maxSymbolValue'. +The result of FSE_readNCount() is the number of bytes read from 'rBuffer'. +Note that 'rBufferSize' must be at least 4 bytes, even if useful information is less than that. +If there is an error, the function will return an error code, which can be tested using FSE_isError(). + +The next step is to build the decompression tables 'FSE_DTable' from 'normalizedCounter'. +This is performed by the function FSE_buildDTable(). +The space required by 'FSE_DTable' must be already allocated using FSE_createDTable(). +If there is an error, the function will return an error code, which can be tested using FSE_isError(). + +`FSE_DTable` can then be used to decompress `cSrc`, with FSE_decompress_usingDTable(). +`cSrcSize` must be strictly correct, otherwise decompression will fail. +FSE_decompress_usingDTable() result will tell how many bytes were regenerated (<=`dstCapacity`). +If there is an error, the function will return an error code, which can be tested using FSE_isError(). (ex: dst buffer too small) +*/ + +/* *** Dependency *** */ +#include "bitstream.h" + +/* ***************************************** +* Static allocation +*******************************************/ +/* FSE buffer bounds */ +#define FSE_NCOUNTBOUND 512 +#define FSE_BLOCKBOUND(size) (size + (size >> 7)) +#define FSE_COMPRESSBOUND(size) (FSE_NCOUNTBOUND + FSE_BLOCKBOUND(size)) /* Macro version, useful for static allocation */ + +/* It is possible to statically allocate FSE CTable/DTable as a table of FSE_CTable/FSE_DTable using below macros */ +#define FSE_CTABLE_SIZE_U32(maxTableLog, maxSymbolValue) (1 + (1 << (maxTableLog - 1)) + ((maxSymbolValue + 1) * 2)) +#define FSE_DTABLE_SIZE_U32(maxTableLog) (1 + (1 << maxTableLog)) + +/* ***************************************** +* FSE advanced API +*******************************************/ +/* FSE_count_wksp() : + * Same as FSE_count(), but using an externally provided scratch buffer. + * `workSpace` size must be table of >= `1024` unsigned + */ +size_t FSE_count_wksp(unsigned *count, unsigned *maxSymbolValuePtr, const void *source, size_t sourceSize, unsigned *workSpace); + +/* FSE_countFast_wksp() : + * Same as FSE_countFast(), but using an externally provided scratch buffer. + * `workSpace` must be a table of minimum `1024` unsigned + */ +size_t FSE_countFast_wksp(unsigned *count, unsigned *maxSymbolValuePtr, const void *src, size_t srcSize, unsigned *workSpace); + +/*! FSE_count_simple + * Same as FSE_countFast(), but does not use any additional memory (not even on stack). + * This function is unsafe, and will segfault if any value within `src` is `> *maxSymbolValuePtr` (presuming it's also the size of `count`). +*/ +size_t FSE_count_simple(unsigned *count, unsigned *maxSymbolValuePtr, const void *src, size_t srcSize); + +unsigned FSE_optimalTableLog_internal(unsigned maxTableLog, size_t srcSize, unsigned maxSymbolValue, unsigned minus); +/**< same as FSE_optimalTableLog(), which used `minus==2` */ + +size_t FSE_buildCTable_raw(FSE_CTable *ct, unsigned nbBits); +/**< build a fake FSE_CTable, designed for a flat distribution, where each symbol uses nbBits */ + +size_t FSE_buildCTable_rle(FSE_CTable *ct, unsigned char symbolValue); +/**< build a fake FSE_CTable, designed to compress always the same symbolValue */ + +/* FSE_buildCTable_wksp() : + * Same as FSE_buildCTable(), but using an externally allocated scratch buffer (`workSpace`). + * `wkspSize` must be >= `(1<<tableLog)`. + */ +size_t FSE_buildCTable_wksp(FSE_CTable *ct, const short *normalizedCounter, unsigned maxSymbolValue, unsigned tableLog, void *workSpace, size_t wkspSize); + +size_t FSE_buildDTable_raw(FSE_DTable *dt, unsigned nbBits); +/**< build a fake FSE_DTable, designed to read a flat distribution where each symbol uses nbBits */ + +size_t FSE_buildDTable_rle(FSE_DTable *dt, unsigned char symbolValue); +/**< build a fake FSE_DTable, designed to always generate the same symbolValue */ + +size_t FSE_decompress_wksp(void *dst, size_t dstCapacity, const void *cSrc, size_t cSrcSize, unsigned maxLog, void *workspace, size_t workspaceSize); +/**< same as FSE_decompress(), using an externally allocated `workSpace` produced with `FSE_DTABLE_SIZE_U32(maxLog)` */ + +/* ***************************************** +* FSE symbol compression API +*******************************************/ +/*! + This API consists of small unitary functions, which highly benefit from being inlined. + Hence their body are included in next section. +*/ +typedef struct { + ptrdiff_t value; + const void *stateTable; + const void *symbolTT; + unsigned stateLog; +} FSE_CState_t; + +static void FSE_initCState(FSE_CState_t *CStatePtr, const FSE_CTable *ct); + +static void FSE_encodeSymbol(BIT_CStream_t *bitC, FSE_CState_t *CStatePtr, unsigned symbol); + +static void FSE_flushCState(BIT_CStream_t *bitC, const FSE_CState_t *CStatePtr); + +/**< +These functions are inner components of FSE_compress_usingCTable(). +They allow the creation of custom streams, mixing multiple tables and bit sources. + +A key property to keep in mind is that encoding and decoding are done **in reverse direction**. +So the first symbol you will encode is the last you will decode, like a LIFO stack. + +You will need a few variables to track your CStream. They are : + +FSE_CTable ct; // Provided by FSE_buildCTable() +BIT_CStream_t bitStream; // bitStream tracking structure +FSE_CState_t state; // State tracking structure (can have several) + + +The first thing to do is to init bitStream and state. + size_t errorCode = BIT_initCStream(&bitStream, dstBuffer, maxDstSize); + FSE_initCState(&state, ct); + +Note that BIT_initCStream() can produce an error code, so its result should be tested, using FSE_isError(); +You can then encode your input data, byte after byte. +FSE_encodeSymbol() outputs a maximum of 'tableLog' bits at a time. +Remember decoding will be done in reverse direction. + FSE_encodeByte(&bitStream, &state, symbol); + +At any time, you can also add any bit sequence. +Note : maximum allowed nbBits is 25, for compatibility with 32-bits decoders + BIT_addBits(&bitStream, bitField, nbBits); + +The above methods don't commit data to memory, they just store it into local register, for speed. +Local register size is 64-bits on 64-bits systems, 32-bits on 32-bits systems (size_t). +Writing data to memory is a manual operation, performed by the flushBits function. + BIT_flushBits(&bitStream); + +Your last FSE encoding operation shall be to flush your last state value(s). + FSE_flushState(&bitStream, &state); + +Finally, you must close the bitStream. +The function returns the size of CStream in bytes. +If data couldn't fit into dstBuffer, it will return a 0 ( == not compressible) +If there is an error, it returns an errorCode (which can be tested using FSE_isError()). + size_t size = BIT_closeCStream(&bitStream); +*/ + +/* ***************************************** +* FSE symbol decompression API +*******************************************/ +typedef struct { + size_t state; + const void *table; /* precise table may vary, depending on U16 */ +} FSE_DState_t; + +static void FSE_initDState(FSE_DState_t *DStatePtr, BIT_DStream_t *bitD, const FSE_DTable *dt); + +static unsigned char FSE_decodeSymbol(FSE_DState_t *DStatePtr, BIT_DStream_t *bitD); + +static unsigned FSE_endOfDState(const FSE_DState_t *DStatePtr); + +/**< +Let's now decompose FSE_decompress_usingDTable() into its unitary components. +You will decode FSE-encoded symbols from the bitStream, +and also any other bitFields you put in, **in reverse order**. + +You will need a few variables to track your bitStream. They are : + +BIT_DStream_t DStream; // Stream context +FSE_DState_t DState; // State context. Multiple ones are possible +FSE_DTable* DTablePtr; // Decoding table, provided by FSE_buildDTable() + +The first thing to do is to init the bitStream. + errorCode = BIT_initDStream(&DStream, srcBuffer, srcSize); + +You should then retrieve your initial state(s) +(in reverse flushing order if you have several ones) : + errorCode = FSE_initDState(&DState, &DStream, DTablePtr); + +You can then decode your data, symbol after symbol. +For information the maximum number of bits read by FSE_decodeSymbol() is 'tableLog'. +Keep in mind that symbols are decoded in reverse order, like a LIFO stack (last in, first out). + unsigned char symbol = FSE_decodeSymbol(&DState, &DStream); + +You can retrieve any bitfield you eventually stored into the bitStream (in reverse order) +Note : maximum allowed nbBits is 25, for 32-bits compatibility + size_t bitField = BIT_readBits(&DStream, nbBits); + +All above operations only read from local register (which size depends on size_t). +Refueling the register from memory is manually performed by the reload method. + endSignal = FSE_reloadDStream(&DStream); + +BIT_reloadDStream() result tells if there is still some more data to read from DStream. +BIT_DStream_unfinished : there is still some data left into the DStream. +BIT_DStream_endOfBuffer : Dstream reached end of buffer. Its container may no longer be completely filled. +BIT_DStream_completed : Dstream reached its exact end, corresponding in general to decompression completed. +BIT_DStream_tooFar : Dstream went too far. Decompression result is corrupted. + +When reaching end of buffer (BIT_DStream_endOfBuffer), progress slowly, notably if you decode multiple symbols per loop, +to properly detect the exact end of stream. +After each decoded symbol, check if DStream is fully consumed using this simple test : + BIT_reloadDStream(&DStream) >= BIT_DStream_completed + +When it's done, verify decompression is fully completed, by checking both DStream and the relevant states. +Checking if DStream has reached its end is performed by : + BIT_endOfDStream(&DStream); +Check also the states. There might be some symbols left there, if some high probability ones (>50%) are possible. + FSE_endOfDState(&DState); +*/ + +/* ***************************************** +* FSE unsafe API +*******************************************/ +static unsigned char FSE_decodeSymbolFast(FSE_DState_t *DStatePtr, BIT_DStream_t *bitD); +/* faster, but works only if nbBits is always >= 1 (otherwise, result will be corrupted) */ + +/* ***************************************** +* Implementation of inlined functions +*******************************************/ +typedef struct { + int deltaFindState; + U32 deltaNbBits; +} FSE_symbolCompressionTransform; /* total 8 bytes */ + +ZSTD_STATIC void FSE_initCState(FSE_CState_t *statePtr, const FSE_CTable *ct) +{ + const void *ptr = ct; + const U16 *u16ptr = (const U16 *)ptr; + const U32 tableLog = ZSTD_read16(ptr); + statePtr->value = (ptrdiff_t)1 << tableLog; + statePtr->stateTable = u16ptr + 2; + statePtr->symbolTT = ((const U32 *)ct + 1 + (tableLog ? (1 << (tableLog - 1)) : 1)); + statePtr->stateLog = tableLog; +} + +/*! FSE_initCState2() : +* Same as FSE_initCState(), but the first symbol to include (which will be the last to be read) +* uses the smallest state value possible, saving the cost of this symbol */ +ZSTD_STATIC void FSE_initCState2(FSE_CState_t *statePtr, const FSE_CTable *ct, U32 symbol) +{ + FSE_initCState(statePtr, ct); + { + const FSE_symbolCompressionTransform symbolTT = ((const FSE_symbolCompressionTransform *)(statePtr->symbolTT))[symbol]; + const U16 *stateTable = (const U16 *)(statePtr->stateTable); + U32 nbBitsOut = (U32)((symbolTT.deltaNbBits + (1 << 15)) >> 16); + statePtr->value = (nbBitsOut << 16) - symbolTT.deltaNbBits; + statePtr->value = stateTable[(statePtr->value >> nbBitsOut) + symbolTT.deltaFindState]; + } +} + +ZSTD_STATIC void FSE_encodeSymbol(BIT_CStream_t *bitC, FSE_CState_t *statePtr, U32 symbol) +{ + const FSE_symbolCompressionTransform symbolTT = ((const FSE_symbolCompressionTransform *)(statePtr->symbolTT))[symbol]; + const U16 *const stateTable = (const U16 *)(statePtr->stateTable); + U32 nbBitsOut = (U32)((statePtr->value + symbolTT.deltaNbBits) >> 16); + BIT_addBits(bitC, statePtr->value, nbBitsOut); + statePtr->value = stateTable[(statePtr->value >> nbBitsOut) + symbolTT.deltaFindState]; +} + +ZSTD_STATIC void FSE_flushCState(BIT_CStream_t *bitC, const FSE_CState_t *statePtr) +{ + BIT_addBits(bitC, statePtr->value, statePtr->stateLog); + BIT_flushBits(bitC); +} + +/* ====== Decompression ====== */ + +typedef struct { + U16 tableLog; + U16 fastMode; +} FSE_DTableHeader; /* sizeof U32 */ + +typedef struct { + unsigned short newState; + unsigned char symbol; + unsigned char nbBits; +} FSE_decode_t; /* size == U32 */ + +ZSTD_STATIC void FSE_initDState(FSE_DState_t *DStatePtr, BIT_DStream_t *bitD, const FSE_DTable *dt) +{ + const void *ptr = dt; + const FSE_DTableHeader *const DTableH = (const FSE_DTableHeader *)ptr; + DStatePtr->state = BIT_readBits(bitD, DTableH->tableLog); + BIT_reloadDStream(bitD); + DStatePtr->table = dt + 1; +} + +ZSTD_STATIC BYTE FSE_peekSymbol(const FSE_DState_t *DStatePtr) +{ + FSE_decode_t const DInfo = ((const FSE_decode_t *)(DStatePtr->table))[DStatePtr->state]; + return DInfo.symbol; +} + +ZSTD_STATIC void FSE_updateState(FSE_DState_t *DStatePtr, BIT_DStream_t *bitD) +{ + FSE_decode_t const DInfo = ((const FSE_decode_t *)(DStatePtr->table))[DStatePtr->state]; + U32 const nbBits = DInfo.nbBits; + size_t const lowBits = BIT_readBits(bitD, nbBits); + DStatePtr->state = DInfo.newState + lowBits; +} + +ZSTD_STATIC BYTE FSE_decodeSymbol(FSE_DState_t *DStatePtr, BIT_DStream_t *bitD) +{ + FSE_decode_t const DInfo = ((const FSE_decode_t *)(DStatePtr->table))[DStatePtr->state]; + U32 const nbBits = DInfo.nbBits; + BYTE const symbol = DInfo.symbol; + size_t const lowBits = BIT_readBits(bitD, nbBits); + + DStatePtr->state = DInfo.newState + lowBits; + return symbol; +} + +/*! FSE_decodeSymbolFast() : + unsafe, only works if no symbol has a probability > 50% */ +ZSTD_STATIC BYTE FSE_decodeSymbolFast(FSE_DState_t *DStatePtr, BIT_DStream_t *bitD) +{ + FSE_decode_t const DInfo = ((const FSE_decode_t *)(DStatePtr->table))[DStatePtr->state]; + U32 const nbBits = DInfo.nbBits; + BYTE const symbol = DInfo.symbol; + size_t const lowBits = BIT_readBitsFast(bitD, nbBits); + + DStatePtr->state = DInfo.newState + lowBits; + return symbol; +} + +ZSTD_STATIC unsigned FSE_endOfDState(const FSE_DState_t *DStatePtr) { return DStatePtr->state == 0; } + +/* ************************************************************** +* Tuning parameters +****************************************************************/ +/*!MEMORY_USAGE : +* Memory usage formula : N->2^N Bytes (examples : 10 -> 1KB; 12 -> 4KB ; 16 -> 64KB; 20 -> 1MB; etc.) +* Increasing memory usage improves compression ratio +* Reduced memory usage can improve speed, due to cache effect +* Recommended max value is 14, for 16KB, which nicely fits into Intel x86 L1 cache */ +#ifndef FSE_MAX_MEMORY_USAGE +#define FSE_MAX_MEMORY_USAGE 14 +#endif +#ifndef FSE_DEFAULT_MEMORY_USAGE +#define FSE_DEFAULT_MEMORY_USAGE 13 +#endif + +/*!FSE_MAX_SYMBOL_VALUE : +* Maximum symbol value authorized. +* Required for proper stack allocation */ +#ifndef FSE_MAX_SYMBOL_VALUE +#define FSE_MAX_SYMBOL_VALUE 255 +#endif + +/* ************************************************************** +* template functions type & suffix +****************************************************************/ +#define FSE_FUNCTION_TYPE BYTE +#define FSE_FUNCTION_EXTENSION +#define FSE_DECODE_TYPE FSE_decode_t + +/* *************************************************************** +* Constants +*****************************************************************/ +#define FSE_MAX_TABLELOG (FSE_MAX_MEMORY_USAGE - 2) +#define FSE_MAX_TABLESIZE (1U << FSE_MAX_TABLELOG) +#define FSE_MAXTABLESIZE_MASK (FSE_MAX_TABLESIZE - 1) +#define FSE_DEFAULT_TABLELOG (FSE_DEFAULT_MEMORY_USAGE - 2) +#define FSE_MIN_TABLELOG 5 + +#define FSE_TABLELOG_ABSOLUTE_MAX 15 +#if FSE_MAX_TABLELOG > FSE_TABLELOG_ABSOLUTE_MAX +#error "FSE_MAX_TABLELOG > FSE_TABLELOG_ABSOLUTE_MAX is not supported" +#endif + +#define FSE_TABLESTEP(tableSize) ((tableSize >> 1) + (tableSize >> 3) + 3) + +#endif /* FSE_H */ diff --git a/lib/zstd/fse_decompress.c b/lib/zstd/fse_decompress.c new file mode 100644 index 00000000000..3b4522b427d --- /dev/null +++ b/lib/zstd/fse_decompress.c @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause) +/* + * FSE : Finite State Entropy decoder + * Copyright (C) 2013-2015, Yann Collet. + * + * You can contact the author at : + * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy + */ + +/* ************************************************************** +* Compiler specifics +****************************************************************/ +#define FORCE_INLINE static __always_inline + +/* ************************************************************** +* Includes +****************************************************************/ +#include "bitstream.h" +#include "fse.h" +#include <linux/compiler.h> +#include <linux/kernel.h> +#include <linux/string.h> /* memcpy, memset */ + +/* ************************************************************** +* Error Management +****************************************************************/ +#define FSE_isError ERR_isError +#define FSE_STATIC_ASSERT(c) \ + { \ + enum { FSE_static_assert = 1 / (int)(!!(c)) }; \ + } /* use only *after* variable declarations */ + +/* check and forward error code */ +#define CHECK_F(f) \ + { \ + size_t const e = f; \ + if (FSE_isError(e)) \ + return e; \ + } + +/* ************************************************************** +* Templates +****************************************************************/ +/* + designed to be included + for type-specific functions (template emulation in C) + Objective is to write these functions only once, for improved maintenance +*/ + +/* safety checks */ +#ifndef FSE_FUNCTION_EXTENSION +#error "FSE_FUNCTION_EXTENSION must be defined" +#endif +#ifndef FSE_FUNCTION_TYPE +#error "FSE_FUNCTION_TYPE must be defined" +#endif + +/* Function names */ +#define FSE_CAT(X, Y) X##Y +#define FSE_FUNCTION_NAME(X, Y) FSE_CAT(X, Y) +#define FSE_TYPE_NAME(X, Y) FSE_CAT(X, Y) + +/* Function templates */ + +size_t FSE_buildDTable_wksp(FSE_DTable *dt, const short *normalizedCounter, unsigned maxSymbolValue, unsigned tableLog, void *workspace, size_t workspaceSize) +{ + void *const tdPtr = dt + 1; /* because *dt is unsigned, 32-bits aligned on 32-bits */ + FSE_DECODE_TYPE *const tableDecode = (FSE_DECODE_TYPE *)(tdPtr); + U16 *symbolNext = (U16 *)workspace; + + U32 const maxSV1 = maxSymbolValue + 1; + U32 const tableSize = 1 << tableLog; + U32 highThreshold = tableSize - 1; + + /* Sanity Checks */ + if (workspaceSize < sizeof(U16) * (FSE_MAX_SYMBOL_VALUE + 1)) + return ERROR(tableLog_tooLarge); + if (maxSymbolValue > FSE_MAX_SYMBOL_VALUE) + return ERROR(maxSymbolValue_tooLarge); + if (tableLog > FSE_MAX_TABLELOG) + return ERROR(tableLog_tooLarge); + + /* Init, lay down lowprob symbols */ + { + FSE_DTableHeader DTableH; + DTableH.tableLog = (U16)tableLog; + DTableH.fastMode = 1; + { + S16 const largeLimit = (S16)(1 << (tableLog - 1)); + U32 s; + for (s = 0; s < maxSV1; s++) { + if (normalizedCounter[s] == -1) { + tableDecode[highThreshold--].symbol = (FSE_FUNCTION_TYPE)s; + symbolNext[s] = 1; + } else { + if (normalizedCounter[s] >= largeLimit) + DTableH.fastMode = 0; + symbolNext[s] = normalizedCounter[s]; + } + } + } + memcpy(dt, &DTableH, sizeof(DTableH)); + } + + /* Spread symbols */ + { + U32 const tableMask = tableSize - 1; + U32 const step = FSE_TABLESTEP(tableSize); + U32 s, position = 0; + for (s = 0; s < maxSV1; s++) { + int i; + for (i = 0; i < normalizedCounter[s]; i++) { + tableDecode[position].symbol = (FSE_FUNCTION_TYPE)s; + position = (position + step) & tableMask; + while (position > highThreshold) + position = (position + step) & tableMask; /* lowprob area */ + } + } + if (position != 0) + return ERROR(GENERIC); /* position must reach all cells once, otherwise normalizedCounter is incorrect */ + } + + /* Build Decoding table */ + { + U32 u; + for (u = 0; u < tableSize; u++) { + FSE_FUNCTION_TYPE const symbol = (FSE_FUNCTION_TYPE)(tableDecode[u].symbol); + U16 nextState = symbolNext[symbol]++; + tableDecode[u].nbBits = (BYTE)(tableLog - BIT_highbit32((U32)nextState)); + tableDecode[u].newState = (U16)((nextState << tableDecode[u].nbBits) - tableSize); + } + } + + return 0; +} + +/*-******************************************************* +* Decompression (Byte symbols) +*********************************************************/ +size_t FSE_buildDTable_rle(FSE_DTable *dt, BYTE symbolValue) +{ + void *ptr = dt; + FSE_DTableHeader *const DTableH = (FSE_DTableHeader *)ptr; + void *dPtr = dt + 1; + FSE_decode_t *const cell = (FSE_decode_t *)dPtr; + + DTableH->tableLog = 0; + DTableH->fastMode = 0; + + cell->newState = 0; + cell->symbol = symbolValue; + cell->nbBits = 0; + + return 0; +} + +size_t FSE_buildDTable_raw(FSE_DTable *dt, unsigned nbBits) +{ + void *ptr = dt; + FSE_DTableHeader *const DTableH = (FSE_DTableHeader *)ptr; + void *dPtr = dt + 1; + FSE_decode_t *const dinfo = (FSE_decode_t *)dPtr; + const unsigned tableSize = 1 << nbBits; + const unsigned tableMask = tableSize - 1; + const unsigned maxSV1 = tableMask + 1; + unsigned s; + + /* Sanity checks */ + if (nbBits < 1) + return ERROR(GENERIC); /* min size */ + + /* Build Decoding Table */ + DTableH->tableLog = (U16)nbBits; + DTableH->fastMode = 1; + for (s = 0; s < maxSV1; s++) { + dinfo[s].newState = 0; + dinfo[s].symbol = (BYTE)s; + dinfo[s].nbBits = (BYTE)nbBits; + } + + return 0; +} + +FORCE_INLINE size_t FSE_decompress_usingDTable_generic(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, const FSE_DTable *dt, + const unsigned fast) +{ + BYTE *const ostart = (BYTE *)dst; + BYTE *op = ostart; + BYTE *const omax = op + maxDstSize; + BYTE *const olimit = omax - 3; + + BIT_DStream_t bitD; + FSE_DState_t state1; + FSE_DState_t state2; + + /* Init */ + CHECK_F(BIT_initDStream(&bitD, cSrc, cSrcSize)); + + FSE_initDState(&state1, &bitD, dt); + FSE_initDState(&state2, &bitD, dt); + +#define FSE_GETSYMBOL(statePtr) fast ? FSE_decodeSymbolFast(statePtr, &bitD) : FSE_decodeSymbol(statePtr, &bitD) + + /* 4 symbols per loop */ + for (; (BIT_reloadDStream(&bitD) == BIT_DStream_unfinished) & (op < olimit); op += 4) { + op[0] = FSE_GETSYMBOL(&state1); + + if (FSE_MAX_TABLELOG * 2 + 7 > sizeof(bitD.bitContainer) * 8) /* This test must be static */ + BIT_reloadDStream(&bitD); + + op[1] = FSE_GETSYMBOL(&state2); + + if (FSE_MAX_TABLELOG * 4 + 7 > sizeof(bitD.bitContainer) * 8) /* This test must be static */ + { + if (BIT_reloadDStream(&bitD) > BIT_DStream_unfinished) { + op += 2; + break; + } + } + + op[2] = FSE_GETSYMBOL(&state1); + + if (FSE_MAX_TABLELOG * 2 + 7 > sizeof(bitD.bitContainer) * 8) /* This test must be static */ + BIT_reloadDStream(&bitD); + + op[3] = FSE_GETSYMBOL(&state2); + } + + /* tail */ + /* note : BIT_reloadDStream(&bitD) >= FSE_DStream_partiallyFilled; Ends at exactly BIT_DStream_completed */ + while (1) { + if (op > (omax - 2)) + return ERROR(dstSize_tooSmall); + *op++ = FSE_GETSYMBOL(&state1); + if (BIT_reloadDStream(&bitD) == BIT_DStream_overflow) { + *op++ = FSE_GETSYMBOL(&state2); + break; + } + + if (op > (omax - 2)) + return ERROR(dstSize_tooSmall); + *op++ = FSE_GETSYMBOL(&state2); + if (BIT_reloadDStream(&bitD) == BIT_DStream_overflow) { + *op++ = FSE_GETSYMBOL(&state1); + break; + } + } + + return op - ostart; +} + +size_t FSE_decompress_usingDTable(void *dst, size_t originalSize, const void *cSrc, size_t cSrcSize, const FSE_DTable *dt) +{ + const void *ptr = dt; + const FSE_DTableHeader *DTableH = (const FSE_DTableHeader *)ptr; + const U32 fastMode = DTableH->fastMode; + + /* select fast mode (static) */ + if (fastMode) + return FSE_decompress_usingDTable_generic(dst, originalSize, cSrc, cSrcSize, dt, 1); + return FSE_decompress_usingDTable_generic(dst, originalSize, cSrc, cSrcSize, dt, 0); +} + +size_t FSE_decompress_wksp(void *dst, size_t dstCapacity, const void *cSrc, size_t cSrcSize, unsigned maxLog, void *workspace, size_t workspaceSize) +{ + const BYTE *const istart = (const BYTE *)cSrc; + const BYTE *ip = istart; + unsigned tableLog; + unsigned maxSymbolValue = FSE_MAX_SYMBOL_VALUE; + size_t NCountLength; + + FSE_DTable *dt; + short *counting; + size_t spaceUsed32 = 0; + + FSE_STATIC_ASSERT(sizeof(FSE_DTable) == sizeof(U32)); + + dt = (FSE_DTable *)((U32 *)workspace + spaceUsed32); + spaceUsed32 += FSE_DTABLE_SIZE_U32(maxLog); + counting = (short *)((U32 *)workspace + spaceUsed32); + spaceUsed32 += ALIGN(sizeof(short) * (FSE_MAX_SYMBOL_VALUE + 1), sizeof(U32)) >> 2; + + if ((spaceUsed32 << 2) > workspaceSize) + return ERROR(tableLog_tooLarge); + workspace = (U32 *)workspace + spaceUsed32; + workspaceSize -= (spaceUsed32 << 2); + + /* normal FSE decoding mode */ + NCountLength = FSE_readNCount(counting, &maxSymbolValue, &tableLog, istart, cSrcSize); + if (FSE_isError(NCountLength)) + return NCountLength; + // if (NCountLength >= cSrcSize) return ERROR(srcSize_wrong); /* too small input size; supposed to be already checked in NCountLength, only remaining + // case : NCountLength==cSrcSize */ + if (tableLog > maxLog) + return ERROR(tableLog_tooLarge); + ip += NCountLength; + cSrcSize -= NCountLength; + + CHECK_F(FSE_buildDTable_wksp(dt, counting, maxSymbolValue, tableLog, workspace, workspaceSize)); + + return FSE_decompress_usingDTable(dst, dstCapacity, ip, cSrcSize, dt); /* always return, even if it is an error code */ +} diff --git a/lib/zstd/huf.h b/lib/zstd/huf.h new file mode 100644 index 00000000000..01630f5669d --- /dev/null +++ b/lib/zstd/huf.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause) */ +/* + * Huffman coder, part of New Generation Entropy library + * header file + * Copyright (C) 2013-2016, Yann Collet. + * + * You can contact the author at : + * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy + */ +#ifndef HUF_H_298734234 +#define HUF_H_298734234 + +/* *** Dependencies *** */ +#include <linux/types.h> /* size_t */ + +/* *** Tool functions *** */ +#define HUF_BLOCKSIZE_MAX (128 * 1024) /**< maximum input size for a single block compressed with HUF_compress */ +size_t HUF_compressBound(size_t size); /**< maximum compressed size (worst case) */ + +/* Error Management */ +unsigned HUF_isError(size_t code); /**< tells if a return value is an error code */ + +/* *** Advanced function *** */ + +/** HUF_compress4X_wksp() : +* Same as HUF_compress2(), but uses externally allocated `workSpace`, which must be a table of >= 1024 unsigned */ +size_t HUF_compress4X_wksp(void *dst, size_t dstSize, const void *src, size_t srcSize, unsigned maxSymbolValue, unsigned tableLog, void *workSpace, + size_t wkspSize); /**< `workSpace` must be a table of at least HUF_COMPRESS_WORKSPACE_SIZE_U32 unsigned */ + +/* *** Dependencies *** */ +#include "mem.h" /* U32 */ + +/* *** Constants *** */ +#define HUF_TABLELOG_MAX 12 /* max configured tableLog (for static allocation); can be modified up to HUF_ABSOLUTEMAX_TABLELOG */ +#define HUF_TABLELOG_DEFAULT 11 /* tableLog by default, when not specified */ +#define HUF_SYMBOLVALUE_MAX 255 + +#define HUF_TABLELOG_ABSOLUTEMAX 15 /* absolute limit of HUF_MAX_TABLELOG. Beyond that value, code does not work */ +#if (HUF_TABLELOG_MAX > HUF_TABLELOG_ABSOLUTEMAX) +#error "HUF_TABLELOG_MAX is too large !" +#endif + +/* **************************************** +* Static allocation +******************************************/ +/* HUF buffer bounds */ +#define HUF_CTABLEBOUND 129 +#define HUF_BLOCKBOUND(size) (size + (size >> 8) + 8) /* only true if incompressible pre-filtered with fast heuristic */ +#define HUF_COMPRESSBOUND(size) (HUF_CTABLEBOUND + HUF_BLOCKBOUND(size)) /* Macro version, useful for static allocation */ + +/* static allocation of HUF's Compression Table */ +#define HUF_CREATE_STATIC_CTABLE(name, maxSymbolValue) \ + U32 name##hb[maxSymbolValue + 1]; \ + void *name##hv = &(name##hb); \ + HUF_CElt *name = (HUF_CElt *)(name##hv) /* no final ; */ + +/* static allocation of HUF's DTable */ +typedef U32 HUF_DTable; +#define HUF_DTABLE_SIZE(maxTableLog) (1 + (1 << (maxTableLog))) +#define HUF_CREATE_STATIC_DTABLEX2(DTable, maxTableLog) HUF_DTable DTable[HUF_DTABLE_SIZE((maxTableLog)-1)] = {((U32)((maxTableLog)-1) * 0x01000001)} +#define HUF_CREATE_STATIC_DTABLEX4(DTable, maxTableLog) HUF_DTable DTable[HUF_DTABLE_SIZE(maxTableLog)] = {((U32)(maxTableLog)*0x01000001)} + +/* The workspace must have alignment at least 4 and be at least this large */ +#define HUF_COMPRESS_WORKSPACE_SIZE (6 << 10) +#define HUF_COMPRESS_WORKSPACE_SIZE_U32 (HUF_COMPRESS_WORKSPACE_SIZE / sizeof(U32)) + +/* The workspace must have alignment at least 4 and be at least this large */ +#define HUF_DECOMPRESS_WORKSPACE_SIZE (3 << 10) +#define HUF_DECOMPRESS_WORKSPACE_SIZE_U32 (HUF_DECOMPRESS_WORKSPACE_SIZE / sizeof(U32)) + +/* **************************************** +* Advanced decompression functions +******************************************/ +size_t HUF_decompress4X_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize); /**< decodes RLE and uncompressed */ +size_t HUF_decompress4X_hufOnly_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, + size_t workspaceSize); /**< considers RLE and uncompressed as errors */ +size_t HUF_decompress4X2_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, + size_t workspaceSize); /**< single-symbol decoder */ +size_t HUF_decompress4X4_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, + size_t workspaceSize); /**< double-symbols decoder */ + +/* **************************************** +* HUF detailed API +******************************************/ +/*! +HUF_compress() does the following: +1. count symbol occurrence from source[] into table count[] using FSE_count() +2. (optional) refine tableLog using HUF_optimalTableLog() +3. build Huffman table from count using HUF_buildCTable() +4. save Huffman table to memory buffer using HUF_writeCTable_wksp() +5. encode the data stream using HUF_compress4X_usingCTable() + +The following API allows targeting specific sub-functions for advanced tasks. +For example, it's possible to compress several blocks using the same 'CTable', +or to save and regenerate 'CTable' using external methods. +*/ +/* FSE_count() : find it within "fse.h" */ +unsigned HUF_optimalTableLog(unsigned maxTableLog, size_t srcSize, unsigned maxSymbolValue); +typedef struct HUF_CElt_s HUF_CElt; /* incomplete type */ +size_t HUF_writeCTable_wksp(void *dst, size_t maxDstSize, const HUF_CElt *CTable, unsigned maxSymbolValue, unsigned huffLog, void *workspace, size_t workspaceSize); +size_t HUF_compress4X_usingCTable(void *dst, size_t dstSize, const void *src, size_t srcSize, const HUF_CElt *CTable); + +typedef enum { + HUF_repeat_none, /**< Cannot use the previous table */ + HUF_repeat_check, /**< Can use the previous table but it must be checked. Note : The previous table must have been constructed by HUF_compress{1, + 4}X_repeat */ + HUF_repeat_valid /**< Can use the previous table and it is asumed to be valid */ +} HUF_repeat; +/** HUF_compress4X_repeat() : +* Same as HUF_compress4X_wksp(), but considers using hufTable if *repeat != HUF_repeat_none. +* If it uses hufTable it does not modify hufTable or repeat. +* If it doesn't, it sets *repeat = HUF_repeat_none, and it sets hufTable to the table used. +* If preferRepeat then the old table will always be used if valid. */ +size_t HUF_compress4X_repeat(void *dst, size_t dstSize, const void *src, size_t srcSize, unsigned maxSymbolValue, unsigned tableLog, void *workSpace, + size_t wkspSize, HUF_CElt *hufTable, HUF_repeat *repeat, + int preferRepeat); /**< `workSpace` must be a table of at least HUF_COMPRESS_WORKSPACE_SIZE_U32 unsigned */ + +/** HUF_buildCTable_wksp() : + * Same as HUF_buildCTable(), but using externally allocated scratch buffer. + * `workSpace` must be aligned on 4-bytes boundaries, and be at least as large as a table of 1024 unsigned. + */ +size_t HUF_buildCTable_wksp(HUF_CElt *tree, const U32 *count, U32 maxSymbolValue, U32 maxNbBits, void *workSpace, size_t wkspSize); + +/*! HUF_readStats() : + Read compact Huffman tree, saved by HUF_writeCTable(). + `huffWeight` is destination buffer. + @return : size read from `src` , or an error Code . + Note : Needed by HUF_readCTable() and HUF_readDTableXn() . */ +size_t HUF_readStats_wksp(BYTE *huffWeight, size_t hwSize, U32 *rankStats, U32 *nbSymbolsPtr, U32 *tableLogPtr, const void *src, size_t srcSize, + void *workspace, size_t workspaceSize); + +/** HUF_readCTable() : +* Loading a CTable saved with HUF_writeCTable() */ +size_t HUF_readCTable_wksp(HUF_CElt *CTable, unsigned maxSymbolValue, const void *src, size_t srcSize, void *workspace, size_t workspaceSize); + +/* +HUF_decompress() does the following: +1. select the decompression algorithm (X2, X4) based on pre-computed heuristics +2. build Huffman table from save, using HUF_readDTableXn() +3. decode 1 or 4 segments in parallel using HUF_decompressSXn_usingDTable +*/ + +/** HUF_selectDecoder() : +* Tells which decoder is likely to decode faster, +* based on a set of pre-determined metrics. +* @return : 0==HUF_decompress4X2, 1==HUF_decompress4X4 . +* Assumption : 0 < cSrcSize < dstSize <= 128 KB */ +U32 HUF_selectDecoder(size_t dstSize, size_t cSrcSize); + +size_t HUF_readDTableX2_wksp(HUF_DTable *DTable, const void *src, size_t srcSize, void *workspace, size_t workspaceSize); +size_t HUF_readDTableX4_wksp(HUF_DTable *DTable, const void *src, size_t srcSize, void *workspace, size_t workspaceSize); + +size_t HUF_decompress4X_usingDTable(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable); +size_t HUF_decompress4X2_usingDTable(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable); +size_t HUF_decompress4X4_usingDTable(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable); + +/* single stream variants */ + +size_t HUF_compress1X_wksp(void *dst, size_t dstSize, const void *src, size_t srcSize, unsigned maxSymbolValue, unsigned tableLog, void *workSpace, + size_t wkspSize); /**< `workSpace` must be a table of at least HUF_COMPRESS_WORKSPACE_SIZE_U32 unsigned */ +size_t HUF_compress1X_usingCTable(void *dst, size_t dstSize, const void *src, size_t srcSize, const HUF_CElt *CTable); +/** HUF_compress1X_repeat() : +* Same as HUF_compress1X_wksp(), but considers using hufTable if *repeat != HUF_repeat_none. +* If it uses hufTable it does not modify hufTable or repeat. +* If it doesn't, it sets *repeat = HUF_repeat_none, and it sets hufTable to the table used. +* If preferRepeat then the old table will always be used if valid. */ +size_t HUF_compress1X_repeat(void *dst, size_t dstSize, const void *src, size_t srcSize, unsigned maxSymbolValue, unsigned tableLog, void *workSpace, + size_t wkspSize, HUF_CElt *hufTable, HUF_repeat *repeat, + int preferRepeat); /**< `workSpace` must be a table of at least HUF_COMPRESS_WORKSPACE_SIZE_U32 unsigned */ + +size_t HUF_decompress1X_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize); +size_t HUF_decompress1X2_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, + size_t workspaceSize); /**< single-symbol decoder */ +size_t HUF_decompress1X4_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, + size_t workspaceSize); /**< double-symbols decoder */ + +size_t HUF_decompress1X_usingDTable(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, + const HUF_DTable *DTable); /**< automatic selection of sing or double symbol decoder, based on DTable */ +size_t HUF_decompress1X2_usingDTable(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable); +size_t HUF_decompress1X4_usingDTable(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable); + +#endif /* HUF_H_298734234 */ diff --git a/lib/zstd/huf_decompress.c b/lib/zstd/huf_decompress.c new file mode 100644 index 00000000000..97145b06088 --- /dev/null +++ b/lib/zstd/huf_decompress.c @@ -0,0 +1,930 @@ +// SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause) +/* + * Huffman decoder, part of New Generation Entropy library + * Copyright (C) 2013-2016, Yann Collet. + * + * You can contact the author at : + * - Source repository : https://github.com/Cyan4973/FiniteStateEntropy + */ + +/* ************************************************************** +* Compiler specifics +****************************************************************/ +#define FORCE_INLINE static __always_inline + +/* ************************************************************** +* Dependencies +****************************************************************/ +#include "bitstream.h" /* BIT_* */ +#include "fse.h" /* header compression */ +#include "huf.h" +#include <linux/compiler.h> +#include <linux/kernel.h> +#include <linux/string.h> /* memcpy, memset */ + +/* ************************************************************** +* Error Management +****************************************************************/ +#define HUF_STATIC_ASSERT(c) \ + { \ + enum { HUF_static_assert = 1 / (int)(!!(c)) }; \ + } /* use only *after* variable declarations */ + +/*-***************************/ +/* generic DTableDesc */ +/*-***************************/ + +typedef struct { + BYTE maxTableLog; + BYTE tableType; + BYTE tableLog; + BYTE reserved; +} DTableDesc; + +static DTableDesc HUF_getDTableDesc(const HUF_DTable *table) +{ + DTableDesc dtd; + memcpy(&dtd, table, sizeof(dtd)); + return dtd; +} + +/*-***************************/ +/* single-symbol decoding */ +/*-***************************/ + +typedef struct { + BYTE byte; + BYTE nbBits; +} HUF_DEltX2; /* single-symbol decoding */ + +size_t HUF_readDTableX2_wksp(HUF_DTable *DTable, const void *src, size_t srcSize, void *workspace, size_t workspaceSize) +{ + U32 tableLog = 0; + U32 nbSymbols = 0; + size_t iSize; + void *const dtPtr = DTable + 1; + HUF_DEltX2 *const dt = (HUF_DEltX2 *)dtPtr; + + U32 *rankVal; + BYTE *huffWeight; + size_t spaceUsed32 = 0; + + rankVal = (U32 *)workspace + spaceUsed32; + spaceUsed32 += HUF_TABLELOG_ABSOLUTEMAX + 1; + huffWeight = (BYTE *)((U32 *)workspace + spaceUsed32); + spaceUsed32 += ALIGN(HUF_SYMBOLVALUE_MAX + 1, sizeof(U32)) >> 2; + + if ((spaceUsed32 << 2) > workspaceSize) + return ERROR(tableLog_tooLarge); + workspace = (U32 *)workspace + spaceUsed32; + workspaceSize -= (spaceUsed32 << 2); + + HUF_STATIC_ASSERT(sizeof(DTableDesc) == sizeof(HUF_DTable)); + /* memset(huffWeight, 0, sizeof(huffWeight)); */ /* is not necessary, even though some analyzer complain ... */ + + iSize = HUF_readStats_wksp(huffWeight, HUF_SYMBOLVALUE_MAX + 1, rankVal, &nbSymbols, &tableLog, src, srcSize, workspace, workspaceSize); + if (HUF_isError(iSize)) + return iSize; + + /* Table header */ + { + DTableDesc dtd = HUF_getDTableDesc(DTable); + if (tableLog > (U32)(dtd.maxTableLog + 1)) + return ERROR(tableLog_tooLarge); /* DTable too small, Huffman tree cannot fit in */ + dtd.tableType = 0; + dtd.tableLog = (BYTE)tableLog; + memcpy(DTable, &dtd, sizeof(dtd)); + } + + /* Calculate starting value for each rank */ + { + U32 n, nextRankStart = 0; + for (n = 1; n < tableLog + 1; n++) { + U32 const curr = nextRankStart; + nextRankStart += (rankVal[n] << (n - 1)); + rankVal[n] = curr; + } + } + + /* fill DTable */ + { + U32 n; + for (n = 0; n < nbSymbols; n++) { + U32 const w = huffWeight[n]; + U32 const length = (1 << w) >> 1; + U32 u; + HUF_DEltX2 D; + D.byte = (BYTE)n; + D.nbBits = (BYTE)(tableLog + 1 - w); + for (u = rankVal[w]; u < rankVal[w] + length; u++) + dt[u] = D; + rankVal[w] += length; + } + } + + return iSize; +} + +static BYTE HUF_decodeSymbolX2(BIT_DStream_t *Dstream, const HUF_DEltX2 *dt, const U32 dtLog) +{ + size_t const val = BIT_lookBitsFast(Dstream, dtLog); /* note : dtLog >= 1 */ + BYTE const c = dt[val].byte; + BIT_skipBits(Dstream, dt[val].nbBits); + return c; +} + +#define HUF_DECODE_SYMBOLX2_0(ptr, DStreamPtr) *ptr++ = HUF_decodeSymbolX2(DStreamPtr, dt, dtLog) + +#define HUF_DECODE_SYMBOLX2_1(ptr, DStreamPtr) \ + if (ZSTD_64bits() || (HUF_TABLELOG_MAX <= 12)) \ + HUF_DECODE_SYMBOLX2_0(ptr, DStreamPtr) + +#define HUF_DECODE_SYMBOLX2_2(ptr, DStreamPtr) \ + if (ZSTD_64bits()) \ + HUF_DECODE_SYMBOLX2_0(ptr, DStreamPtr) + +FORCE_INLINE size_t HUF_decodeStreamX2(BYTE *p, BIT_DStream_t *const bitDPtr, BYTE *const pEnd, const HUF_DEltX2 *const dt, const U32 dtLog) +{ + BYTE *const pStart = p; + + /* up to 4 symbols at a time */ + while ((BIT_reloadDStream(bitDPtr) == BIT_DStream_unfinished) && (p <= pEnd - 4)) { + HUF_DECODE_SYMBOLX2_2(p, bitDPtr); + HUF_DECODE_SYMBOLX2_1(p, bitDPtr); + HUF_DECODE_SYMBOLX2_2(p, bitDPtr); + HUF_DECODE_SYMBOLX2_0(p, bitDPtr); + } + + /* closer to the end */ + while ((BIT_reloadDStream(bitDPtr) == BIT_DStream_unfinished) && (p < pEnd)) + HUF_DECODE_SYMBOLX2_0(p, bitDPtr); + + /* no more data to retrieve from bitstream, hence no need to reload */ + while (p < pEnd) + HUF_DECODE_SYMBOLX2_0(p, bitDPtr); + + return pEnd - pStart; +} + +static size_t HUF_decompress1X2_usingDTable_internal(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable) +{ + BYTE *op = (BYTE *)dst; + BYTE *const oend = op + dstSize; + const void *dtPtr = DTable + 1; + const HUF_DEltX2 *const dt = (const HUF_DEltX2 *)dtPtr; + BIT_DStream_t bitD; + DTableDesc const dtd = HUF_getDTableDesc(DTable); + U32 const dtLog = dtd.tableLog; + + { + size_t const errorCode = BIT_initDStream(&bitD, cSrc, cSrcSize); + if (HUF_isError(errorCode)) + return errorCode; + } + + HUF_decodeStreamX2(op, &bitD, oend, dt, dtLog); + + /* check */ + if (!BIT_endOfDStream(&bitD)) + return ERROR(corruption_detected); + + return dstSize; +} + +size_t HUF_decompress1X2_usingDTable(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable) +{ + DTableDesc dtd = HUF_getDTableDesc(DTable); + if (dtd.tableType != 0) + return ERROR(GENERIC); + return HUF_decompress1X2_usingDTable_internal(dst, dstSize, cSrc, cSrcSize, DTable); +} + +size_t HUF_decompress1X2_DCtx_wksp(HUF_DTable *DCtx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize) +{ + const BYTE *ip = (const BYTE *)cSrc; + + size_t const hSize = HUF_readDTableX2_wksp(DCtx, cSrc, cSrcSize, workspace, workspaceSize); + if (HUF_isError(hSize)) + return hSize; + if (hSize >= cSrcSize) + return ERROR(srcSize_wrong); + ip += hSize; + cSrcSize -= hSize; + + return HUF_decompress1X2_usingDTable_internal(dst, dstSize, ip, cSrcSize, DCtx); +} + +static size_t HUF_decompress4X2_usingDTable_internal(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable) +{ + /* Check */ + if (cSrcSize < 10) + return ERROR(corruption_detected); /* strict minimum : jump table + 1 byte per stream */ + + { + const BYTE *const istart = (const BYTE *)cSrc; + BYTE *const ostart = (BYTE *)dst; + BYTE *const oend = ostart + dstSize; + const void *const dtPtr = DTable + 1; + const HUF_DEltX2 *const dt = (const HUF_DEltX2 *)dtPtr; + + /* Init */ + BIT_DStream_t bitD1; + BIT_DStream_t bitD2; + BIT_DStream_t bitD3; + BIT_DStream_t bitD4; + size_t const length1 = ZSTD_readLE16(istart); + size_t const length2 = ZSTD_readLE16(istart + 2); + size_t const length3 = ZSTD_readLE16(istart + 4); + size_t const length4 = cSrcSize - (length1 + length2 + length3 + 6); + const BYTE *const istart1 = istart + 6; /* jumpTable */ + const BYTE *const istart2 = istart1 + length1; + const BYTE *const istart3 = istart2 + length2; + const BYTE *const istart4 = istart3 + length3; + const size_t segmentSize = (dstSize + 3) / 4; + BYTE *const opStart2 = ostart + segmentSize; + BYTE *const opStart3 = opStart2 + segmentSize; + BYTE *const opStart4 = opStart3 + segmentSize; + BYTE *op1 = ostart; + BYTE *op2 = opStart2; + BYTE *op3 = opStart3; + BYTE *op4 = opStart4; + U32 endSignal; + DTableDesc const dtd = HUF_getDTableDesc(DTable); + U32 const dtLog = dtd.tableLog; + + if (length4 > cSrcSize) + return ERROR(corruption_detected); /* overflow */ + { + size_t const errorCode = BIT_initDStream(&bitD1, istart1, length1); + if (HUF_isError(errorCode)) + return errorCode; + } + { + size_t const errorCode = BIT_initDStream(&bitD2, istart2, length2); + if (HUF_isError(errorCode)) + return errorCode; + } + { + size_t const errorCode = BIT_initDStream(&bitD3, istart3, length3); + if (HUF_isError(errorCode)) + return errorCode; + } + { + size_t const errorCode = BIT_initDStream(&bitD4, istart4, length4); + if (HUF_isError(errorCode)) + return errorCode; + } + + /* 16-32 symbols per loop (4-8 symbols per stream) */ + endSignal = BIT_reloadDStream(&bitD1) | BIT_reloadDStream(&bitD2) | BIT_reloadDStream(&bitD3) | BIT_reloadDStream(&bitD4); + for (; (endSignal == BIT_DStream_unfinished) && (op4 < (oend - 7));) { + HUF_DECODE_SYMBOLX2_2(op1, &bitD1); + HUF_DECODE_SYMBOLX2_2(op2, &bitD2); + HUF_DECODE_SYMBOLX2_2(op3, &bitD3); + HUF_DECODE_SYMBOLX2_2(op4, &bitD4); + HUF_DECODE_SYMBOLX2_1(op1, &bitD1); + HUF_DECODE_SYMBOLX2_1(op2, &bitD2); + HUF_DECODE_SYMBOLX2_1(op3, &bitD3); + HUF_DECODE_SYMBOLX2_1(op4, &bitD4); + HUF_DECODE_SYMBOLX2_2(op1, &bitD1); + HUF_DECODE_SYMBOLX2_2(op2, &bitD2); + HUF_DECODE_SYMBOLX2_2(op3, &bitD3); + HUF_DECODE_SYMBOLX2_2(op4, &bitD4); + HUF_DECODE_SYMBOLX2_0(op1, &bitD1); + HUF_DECODE_SYMBOLX2_0(op2, &bitD2); + HUF_DECODE_SYMBOLX2_0(op3, &bitD3); + HUF_DECODE_SYMBOLX2_0(op4, &bitD4); + endSignal = BIT_reloadDStream(&bitD1) | BIT_reloadDStream(&bitD2) | BIT_reloadDStream(&bitD3) | BIT_reloadDStream(&bitD4); + } + + /* check corruption */ + if (op1 > opStart2) + return ERROR(corruption_detected); + if (op2 > opStart3) + return ERROR(corruption_detected); + if (op3 > opStart4) + return ERROR(corruption_detected); + /* note : op4 supposed already verified within main loop */ + + /* finish bitStreams one by one */ + HUF_decodeStreamX2(op1, &bitD1, opStart2, dt, dtLog); + HUF_decodeStreamX2(op2, &bitD2, opStart3, dt, dtLog); + HUF_decodeStreamX2(op3, &bitD3, opStart4, dt, dtLog); + HUF_decodeStreamX2(op4, &bitD4, oend, dt, dtLog); + + /* check */ + endSignal = BIT_endOfDStream(&bitD1) & BIT_endOfDStream(&bitD2) & BIT_endOfDStream(&bitD3) & BIT_endOfDStream(&bitD4); + if (!endSignal) + return ERROR(corruption_detected); + + /* decoded size */ + return dstSize; + } +} + +size_t HUF_decompress4X2_usingDTable(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable) +{ + DTableDesc dtd = HUF_getDTableDesc(DTable); + if (dtd.tableType != 0) + return ERROR(GENERIC); + return HUF_decompress4X2_usingDTable_internal(dst, dstSize, cSrc, cSrcSize, DTable); +} + +size_t HUF_decompress4X2_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize) +{ + const BYTE *ip = (const BYTE *)cSrc; + + size_t const hSize = HUF_readDTableX2_wksp(dctx, cSrc, cSrcSize, workspace, workspaceSize); + if (HUF_isError(hSize)) + return hSize; + if (hSize >= cSrcSize) + return ERROR(srcSize_wrong); + ip += hSize; + cSrcSize -= hSize; + + return HUF_decompress4X2_usingDTable_internal(dst, dstSize, ip, cSrcSize, dctx); +} + +/* *************************/ +/* double-symbols decoding */ +/* *************************/ +typedef struct { + U16 sequence; + BYTE nbBits; + BYTE length; +} HUF_DEltX4; /* double-symbols decoding */ + +typedef struct { + BYTE symbol; + BYTE weight; +} sortedSymbol_t; + +/* HUF_fillDTableX4Level2() : + * `rankValOrigin` must be a table of at least (HUF_TABLELOG_MAX + 1) U32 */ +static void HUF_fillDTableX4Level2(HUF_DEltX4 *DTable, U32 sizeLog, const U32 consumed, const U32 *rankValOrigin, const int minWeight, + const sortedSymbol_t *sortedSymbols, const U32 sortedListSize, U32 nbBitsBaseline, U16 baseSeq) +{ + HUF_DEltX4 DElt; + U32 rankVal[HUF_TABLELOG_MAX + 1]; + + /* get pre-calculated rankVal */ + memcpy(rankVal, rankValOrigin, sizeof(rankVal)); + + /* fill skipped values */ + if (minWeight > 1) { + U32 i, skipSize = rankVal[minWeight]; + ZSTD_writeLE16(&(DElt.sequence), baseSeq); + DElt.nbBits = (BYTE)(consumed); + DElt.length = 1; + for (i = 0; i < skipSize; i++) + DTable[i] = DElt; + } + + /* fill DTable */ + { + U32 s; + for (s = 0; s < sortedListSize; s++) { /* note : sortedSymbols already skipped */ + const U32 symbol = sortedSymbols[s].symbol; + const U32 weight = sortedSymbols[s].weight; + const U32 nbBits = nbBitsBaseline - weight; + const U32 length = 1 << (sizeLog - nbBits); + const U32 start = rankVal[weight]; + U32 i = start; + const U32 end = start + length; + + ZSTD_writeLE16(&(DElt.sequence), (U16)(baseSeq + (symbol << 8))); + DElt.nbBits = (BYTE)(nbBits + consumed); + DElt.length = 2; + do { + DTable[i++] = DElt; + } while (i < end); /* since length >= 1 */ + + rankVal[weight] += length; + } + } +} + +typedef U32 rankVal_t[HUF_TABLELOG_MAX][HUF_TABLELOG_MAX + 1]; +typedef U32 rankValCol_t[HUF_TABLELOG_MAX + 1]; + +static void HUF_fillDTableX4(HUF_DEltX4 *DTable, const U32 targetLog, const sortedSymbol_t *sortedList, const U32 sortedListSize, const U32 *rankStart, + rankVal_t rankValOrigin, const U32 maxWeight, const U32 nbBitsBaseline) +{ + U32 rankVal[HUF_TABLELOG_MAX + 1]; + const int scaleLog = nbBitsBaseline - targetLog; /* note : targetLog >= srcLog, hence scaleLog <= 1 */ + const U32 minBits = nbBitsBaseline - maxWeight; + U32 s; + + memcpy(rankVal, rankValOrigin, sizeof(rankVal)); + + /* fill DTable */ + for (s = 0; s < sortedListSize; s++) { + const U16 symbol = sortedList[s].symbol; + const U32 weight = sortedList[s].weight; + const U32 nbBits = nbBitsBaseline - weight; + const U32 start = rankVal[weight]; + const U32 length = 1 << (targetLog - nbBits); + + if (targetLog - nbBits >= minBits) { /* enough room for a second symbol */ + U32 sortedRank; + int minWeight = nbBits + scaleLog; + if (minWeight < 1) + minWeight = 1; + sortedRank = rankStart[minWeight]; + HUF_fillDTableX4Level2(DTable + start, targetLog - nbBits, nbBits, rankValOrigin[nbBits], minWeight, sortedList + sortedRank, + sortedListSize - sortedRank, nbBitsBaseline, symbol); + } else { + HUF_DEltX4 DElt; + ZSTD_writeLE16(&(DElt.sequence), symbol); + DElt.nbBits = (BYTE)(nbBits); + DElt.length = 1; + { + U32 const end = start + length; + U32 u; + for (u = start; u < end; u++) + DTable[u] = DElt; + } + } + rankVal[weight] += length; + } +} + +size_t HUF_readDTableX4_wksp(HUF_DTable *DTable, const void *src, size_t srcSize, void *workspace, size_t workspaceSize) +{ + U32 tableLog, maxW, sizeOfSort, nbSymbols; + DTableDesc dtd = HUF_getDTableDesc(DTable); + U32 const maxTableLog = dtd.maxTableLog; + size_t iSize; + void *dtPtr = DTable + 1; /* force compiler to avoid strict-aliasing */ + HUF_DEltX4 *const dt = (HUF_DEltX4 *)dtPtr; + U32 *rankStart; + + rankValCol_t *rankVal; + U32 *rankStats; + U32 *rankStart0; + sortedSymbol_t *sortedSymbol; + BYTE *weightList; + size_t spaceUsed32 = 0; + + HUF_STATIC_ASSERT((sizeof(rankValCol_t) & 3) == 0); + + rankVal = (rankValCol_t *)((U32 *)workspace + spaceUsed32); + spaceUsed32 += (sizeof(rankValCol_t) * HUF_TABLELOG_MAX) >> 2; + rankStats = (U32 *)workspace + spaceUsed32; + spaceUsed32 += HUF_TABLELOG_MAX + 1; + rankStart0 = (U32 *)workspace + spaceUsed32; + spaceUsed32 += HUF_TABLELOG_MAX + 2; + sortedSymbol = (sortedSymbol_t *)((U32 *)workspace + spaceUsed32); + spaceUsed32 += ALIGN(sizeof(sortedSymbol_t) * (HUF_SYMBOLVALUE_MAX + 1), sizeof(U32)) >> 2; + weightList = (BYTE *)((U32 *)workspace + spaceUsed32); + spaceUsed32 += ALIGN(HUF_SYMBOLVALUE_MAX + 1, sizeof(U32)) >> 2; + + if ((spaceUsed32 << 2) > workspaceSize) + return ERROR(tableLog_tooLarge); + workspace = (U32 *)workspace + spaceUsed32; + workspaceSize -= (spaceUsed32 << 2); + + rankStart = rankStart0 + 1; + memset(rankStats, 0, sizeof(U32) * (2 * HUF_TABLELOG_MAX + 2 + 1)); + + HUF_STATIC_ASSERT(sizeof(HUF_DEltX4) == sizeof(HUF_DTable)); /* if compiler fails here, assertion is wrong */ + if (maxTableLog > HUF_TABLELOG_MAX) + return ERROR(tableLog_tooLarge); + /* memset(weightList, 0, sizeof(weightList)); */ /* is not necessary, even though some analyzer complain ... */ + + iSize = HUF_readStats_wksp(weightList, HUF_SYMBOLVALUE_MAX + 1, rankStats, &nbSymbols, &tableLog, src, srcSize, workspace, workspaceSize); + if (HUF_isError(iSize)) + return iSize; + + /* check result */ + if (tableLog > maxTableLog) + return ERROR(tableLog_tooLarge); /* DTable can't fit code depth */ + + /* find maxWeight */ + for (maxW = tableLog; rankStats[maxW] == 0; maxW--) { + } /* necessarily finds a solution before 0 */ + + /* Get start index of each weight */ + { + U32 w, nextRankStart = 0; + for (w = 1; w < maxW + 1; w++) { + U32 curr = nextRankStart; + nextRankStart += rankStats[w]; + rankStart[w] = curr; + } + rankStart[0] = nextRankStart; /* put all 0w symbols at the end of sorted list*/ + sizeOfSort = nextRankStart; + } + + /* sort symbols by weight */ + { + U32 s; + for (s = 0; s < nbSymbols; s++) { + U32 const w = weightList[s]; + U32 const r = rankStart[w]++; + sortedSymbol[r].symbol = (BYTE)s; + sortedSymbol[r].weight = (BYTE)w; + } + rankStart[0] = 0; /* forget 0w symbols; this is beginning of weight(1) */ + } + + /* Build rankVal */ + { + U32 *const rankVal0 = rankVal[0]; + { + int const rescale = (maxTableLog - tableLog) - 1; /* tableLog <= maxTableLog */ + U32 nextRankVal = 0; + U32 w; + for (w = 1; w < maxW + 1; w++) { + U32 curr = nextRankVal; + nextRankVal += rankStats[w] << (w + rescale); + rankVal0[w] = curr; + } + } + { + U32 const minBits = tableLog + 1 - maxW; + U32 consumed; + for (consumed = minBits; consumed < maxTableLog - minBits + 1; consumed++) { + U32 *const rankValPtr = rankVal[consumed]; + U32 w; + for (w = 1; w < maxW + 1; w++) { + rankValPtr[w] = rankVal0[w] >> consumed; + } + } + } + } + + HUF_fillDTableX4(dt, maxTableLog, sortedSymbol, sizeOfSort, rankStart0, rankVal, maxW, tableLog + 1); + + dtd.tableLog = (BYTE)maxTableLog; + dtd.tableType = 1; + memcpy(DTable, &dtd, sizeof(dtd)); + return iSize; +} + +static U32 HUF_decodeSymbolX4(void *op, BIT_DStream_t *DStream, const HUF_DEltX4 *dt, const U32 dtLog) +{ + size_t const val = BIT_lookBitsFast(DStream, dtLog); /* note : dtLog >= 1 */ + memcpy(op, dt + val, 2); + BIT_skipBits(DStream, dt[val].nbBits); + return dt[val].length; +} + +static U32 HUF_decodeLastSymbolX4(void *op, BIT_DStream_t *DStream, const HUF_DEltX4 *dt, const U32 dtLog) +{ + size_t const val = BIT_lookBitsFast(DStream, dtLog); /* note : dtLog >= 1 */ + memcpy(op, dt + val, 1); + if (dt[val].length == 1) + BIT_skipBits(DStream, dt[val].nbBits); + else { + if (DStream->bitsConsumed < (sizeof(DStream->bitContainer) * 8)) { + BIT_skipBits(DStream, dt[val].nbBits); + if (DStream->bitsConsumed > (sizeof(DStream->bitContainer) * 8)) + /* ugly hack; works only because it's the last symbol. Note : can't easily extract nbBits from just this symbol */ + DStream->bitsConsumed = (sizeof(DStream->bitContainer) * 8); + } + } + return 1; +} + +#define HUF_DECODE_SYMBOLX4_0(ptr, DStreamPtr) ptr += HUF_decodeSymbolX4(ptr, DStreamPtr, dt, dtLog) + +#define HUF_DECODE_SYMBOLX4_1(ptr, DStreamPtr) \ + if (ZSTD_64bits() || (HUF_TABLELOG_MAX <= 12)) \ + ptr += HUF_decodeSymbolX4(ptr, DStreamPtr, dt, dtLog) + +#define HUF_DECODE_SYMBOLX4_2(ptr, DStreamPtr) \ + if (ZSTD_64bits()) \ + ptr += HUF_decodeSymbolX4(ptr, DStreamPtr, dt, dtLog) + +FORCE_INLINE size_t HUF_decodeStreamX4(BYTE *p, BIT_DStream_t *bitDPtr, BYTE *const pEnd, const HUF_DEltX4 *const dt, const U32 dtLog) +{ + BYTE *const pStart = p; + + /* up to 8 symbols at a time */ + while ((BIT_reloadDStream(bitDPtr) == BIT_DStream_unfinished) & (p < pEnd - (sizeof(bitDPtr->bitContainer) - 1))) { + HUF_DECODE_SYMBOLX4_2(p, bitDPtr); + HUF_DECODE_SYMBOLX4_1(p, bitDPtr); + HUF_DECODE_SYMBOLX4_2(p, bitDPtr); + HUF_DECODE_SYMBOLX4_0(p, bitDPtr); + } + + /* closer to end : up to 2 symbols at a time */ + while ((BIT_reloadDStream(bitDPtr) == BIT_DStream_unfinished) & (p <= pEnd - 2)) + HUF_DECODE_SYMBOLX4_0(p, bitDPtr); + + while (p <= pEnd - 2) + HUF_DECODE_SYMBOLX4_0(p, bitDPtr); /* no need to reload : reached the end of DStream */ + + if (p < pEnd) + p += HUF_decodeLastSymbolX4(p, bitDPtr, dt, dtLog); + + return p - pStart; +} + +static size_t HUF_decompress1X4_usingDTable_internal(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable) +{ + BIT_DStream_t bitD; + + /* Init */ + { + size_t const errorCode = BIT_initDStream(&bitD, cSrc, cSrcSize); + if (HUF_isError(errorCode)) + return errorCode; + } + + /* decode */ + { + BYTE *const ostart = (BYTE *)dst; + BYTE *const oend = ostart + dstSize; + const void *const dtPtr = DTable + 1; /* force compiler to not use strict-aliasing */ + const HUF_DEltX4 *const dt = (const HUF_DEltX4 *)dtPtr; + DTableDesc const dtd = HUF_getDTableDesc(DTable); + HUF_decodeStreamX4(ostart, &bitD, oend, dt, dtd.tableLog); + } + + /* check */ + if (!BIT_endOfDStream(&bitD)) + return ERROR(corruption_detected); + + /* decoded size */ + return dstSize; +} + +size_t HUF_decompress1X4_usingDTable(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable) +{ + DTableDesc dtd = HUF_getDTableDesc(DTable); + if (dtd.tableType != 1) + return ERROR(GENERIC); + return HUF_decompress1X4_usingDTable_internal(dst, dstSize, cSrc, cSrcSize, DTable); +} + +size_t HUF_decompress1X4_DCtx_wksp(HUF_DTable *DCtx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize) +{ + const BYTE *ip = (const BYTE *)cSrc; + + size_t const hSize = HUF_readDTableX4_wksp(DCtx, cSrc, cSrcSize, workspace, workspaceSize); + if (HUF_isError(hSize)) + return hSize; + if (hSize >= cSrcSize) + return ERROR(srcSize_wrong); + ip += hSize; + cSrcSize -= hSize; + + return HUF_decompress1X4_usingDTable_internal(dst, dstSize, ip, cSrcSize, DCtx); +} + +static size_t HUF_decompress4X4_usingDTable_internal(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable) +{ + if (cSrcSize < 10) + return ERROR(corruption_detected); /* strict minimum : jump table + 1 byte per stream */ + + { + const BYTE *const istart = (const BYTE *)cSrc; + BYTE *const ostart = (BYTE *)dst; + BYTE *const oend = ostart + dstSize; + const void *const dtPtr = DTable + 1; + const HUF_DEltX4 *const dt = (const HUF_DEltX4 *)dtPtr; + + /* Init */ + BIT_DStream_t bitD1; + BIT_DStream_t bitD2; + BIT_DStream_t bitD3; + BIT_DStream_t bitD4; + size_t const length1 = ZSTD_readLE16(istart); + size_t const length2 = ZSTD_readLE16(istart + 2); + size_t const length3 = ZSTD_readLE16(istart + 4); + size_t const length4 = cSrcSize - (length1 + length2 + length3 + 6); + const BYTE *const istart1 = istart + 6; /* jumpTable */ + const BYTE *const istart2 = istart1 + length1; + const BYTE *const istart3 = istart2 + length2; + const BYTE *const istart4 = istart3 + length3; + size_t const segmentSize = (dstSize + 3) / 4; + BYTE *const opStart2 = ostart + segmentSize; + BYTE *const opStart3 = opStart2 + segmentSize; + BYTE *const opStart4 = opStart3 + segmentSize; + BYTE *op1 = ostart; + BYTE *op2 = opStart2; + BYTE *op3 = opStart3; + BYTE *op4 = opStart4; + U32 endSignal; + DTableDesc const dtd = HUF_getDTableDesc(DTable); + U32 const dtLog = dtd.tableLog; + + if (length4 > cSrcSize) + return ERROR(corruption_detected); /* overflow */ + { + size_t const errorCode = BIT_initDStream(&bitD1, istart1, length1); + if (HUF_isError(errorCode)) + return errorCode; + } + { + size_t const errorCode = BIT_initDStream(&bitD2, istart2, length2); + if (HUF_isError(errorCode)) + return errorCode; + } + { + size_t const errorCode = BIT_initDStream(&bitD3, istart3, length3); + if (HUF_isError(errorCode)) + return errorCode; + } + { + size_t const errorCode = BIT_initDStream(&bitD4, istart4, length4); + if (HUF_isError(errorCode)) + return errorCode; + } + + /* 16-32 symbols per loop (4-8 symbols per stream) */ + endSignal = BIT_reloadDStream(&bitD1) | BIT_reloadDStream(&bitD2) | BIT_reloadDStream(&bitD3) | BIT_reloadDStream(&bitD4); + for (; (endSignal == BIT_DStream_unfinished) & (op4 < (oend - (sizeof(bitD4.bitContainer) - 1)));) { + HUF_DECODE_SYMBOLX4_2(op1, &bitD1); + HUF_DECODE_SYMBOLX4_2(op2, &bitD2); + HUF_DECODE_SYMBOLX4_2(op3, &bitD3); + HUF_DECODE_SYMBOLX4_2(op4, &bitD4); + HUF_DECODE_SYMBOLX4_1(op1, &bitD1); + HUF_DECODE_SYMBOLX4_1(op2, &bitD2); + HUF_DECODE_SYMBOLX4_1(op3, &bitD3); + HUF_DECODE_SYMBOLX4_1(op4, &bitD4); + HUF_DECODE_SYMBOLX4_2(op1, &bitD1); + HUF_DECODE_SYMBOLX4_2(op2, &bitD2); + HUF_DECODE_SYMBOLX4_2(op3, &bitD3); + HUF_DECODE_SYMBOLX4_2(op4, &bitD4); + HUF_DECODE_SYMBOLX4_0(op1, &bitD1); + HUF_DECODE_SYMBOLX4_0(op2, &bitD2); + HUF_DECODE_SYMBOLX4_0(op3, &bitD3); + HUF_DECODE_SYMBOLX4_0(op4, &bitD4); + + endSignal = BIT_reloadDStream(&bitD1) | BIT_reloadDStream(&bitD2) | BIT_reloadDStream(&bitD3) | BIT_reloadDStream(&bitD4); + } + + /* check corruption */ + if (op1 > opStart2) + return ERROR(corruption_detected); + if (op2 > opStart3) + return ERROR(corruption_detected); + if (op3 > opStart4) + return ERROR(corruption_detected); + /* note : op4 already verified within main loop */ + + /* finish bitStreams one by one */ + HUF_decodeStreamX4(op1, &bitD1, opStart2, dt, dtLog); + HUF_decodeStreamX4(op2, &bitD2, opStart3, dt, dtLog); + HUF_decodeStreamX4(op3, &bitD3, opStart4, dt, dtLog); + HUF_decodeStreamX4(op4, &bitD4, oend, dt, dtLog); + + /* check */ + { + U32 const endCheck = BIT_endOfDStream(&bitD1) & BIT_endOfDStream(&bitD2) & BIT_endOfDStream(&bitD3) & BIT_endOfDStream(&bitD4); + if (!endCheck) + return ERROR(corruption_detected); + } + + /* decoded size */ + return dstSize; + } +} + +size_t HUF_decompress4X4_usingDTable(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable) +{ + DTableDesc dtd = HUF_getDTableDesc(DTable); + if (dtd.tableType != 1) + return ERROR(GENERIC); + return HUF_decompress4X4_usingDTable_internal(dst, dstSize, cSrc, cSrcSize, DTable); +} + +size_t HUF_decompress4X4_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize) +{ + const BYTE *ip = (const BYTE *)cSrc; + + size_t hSize = HUF_readDTableX4_wksp(dctx, cSrc, cSrcSize, workspace, workspaceSize); + if (HUF_isError(hSize)) + return hSize; + if (hSize >= cSrcSize) + return ERROR(srcSize_wrong); + ip += hSize; + cSrcSize -= hSize; + + return HUF_decompress4X4_usingDTable_internal(dst, dstSize, ip, cSrcSize, dctx); +} + +/* ********************************/ +/* Generic decompression selector */ +/* ********************************/ + +size_t HUF_decompress1X_usingDTable(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable) +{ + DTableDesc const dtd = HUF_getDTableDesc(DTable); + return dtd.tableType ? HUF_decompress1X4_usingDTable_internal(dst, maxDstSize, cSrc, cSrcSize, DTable) + : HUF_decompress1X2_usingDTable_internal(dst, maxDstSize, cSrc, cSrcSize, DTable); +} + +size_t HUF_decompress4X_usingDTable(void *dst, size_t maxDstSize, const void *cSrc, size_t cSrcSize, const HUF_DTable *DTable) +{ + DTableDesc const dtd = HUF_getDTableDesc(DTable); + return dtd.tableType ? HUF_decompress4X4_usingDTable_internal(dst, maxDstSize, cSrc, cSrcSize, DTable) + : HUF_decompress4X2_usingDTable_internal(dst, maxDstSize, cSrc, cSrcSize, DTable); +} + +typedef struct { + U32 tableTime; + U32 decode256Time; +} algo_time_t; +static const algo_time_t algoTime[16 /* Quantization */][3 /* single, double, quad */] = { + /* single, double, quad */ + {{0, 0}, {1, 1}, {2, 2}}, /* Q==0 : impossible */ + {{0, 0}, {1, 1}, {2, 2}}, /* Q==1 : impossible */ + {{38, 130}, {1313, 74}, {2151, 38}}, /* Q == 2 : 12-18% */ + {{448, 128}, {1353, 74}, {2238, 41}}, /* Q == 3 : 18-25% */ + {{556, 128}, {1353, 74}, {2238, 47}}, /* Q == 4 : 25-32% */ + {{714, 128}, {1418, 74}, {2436, 53}}, /* Q == 5 : 32-38% */ + {{883, 128}, {1437, 74}, {2464, 61}}, /* Q == 6 : 38-44% */ + {{897, 128}, {1515, 75}, {2622, 68}}, /* Q == 7 : 44-50% */ + {{926, 128}, {1613, 75}, {2730, 75}}, /* Q == 8 : 50-56% */ + {{947, 128}, {1729, 77}, {3359, 77}}, /* Q == 9 : 56-62% */ + {{1107, 128}, {2083, 81}, {4006, 84}}, /* Q ==10 : 62-69% */ + {{1177, 128}, {2379, 87}, {4785, 88}}, /* Q ==11 : 69-75% */ + {{1242, 128}, {2415, 93}, {5155, 84}}, /* Q ==12 : 75-81% */ + {{1349, 128}, {2644, 106}, {5260, 106}}, /* Q ==13 : 81-87% */ + {{1455, 128}, {2422, 124}, {4174, 124}}, /* Q ==14 : 87-93% */ + {{722, 128}, {1891, 145}, {1936, 146}}, /* Q ==15 : 93-99% */ +}; + +/** HUF_selectDecoder() : +* Tells which decoder is likely to decode faster, +* based on a set of pre-determined metrics. +* @return : 0==HUF_decompress4X2, 1==HUF_decompress4X4 . +* Assumption : 0 < cSrcSize < dstSize <= 128 KB */ +U32 HUF_selectDecoder(size_t dstSize, size_t cSrcSize) +{ + /* decoder timing evaluation */ + U32 const Q = (U32)(cSrcSize * 16 / dstSize); /* Q < 16 since dstSize > cSrcSize */ + U32 const D256 = (U32)(dstSize >> 8); + U32 const DTime0 = algoTime[Q][0].tableTime + (algoTime[Q][0].decode256Time * D256); + U32 DTime1 = algoTime[Q][1].tableTime + (algoTime[Q][1].decode256Time * D256); + DTime1 += DTime1 >> 3; /* advantage to algorithm using less memory, for cache eviction */ + + return DTime1 < DTime0; +} + +typedef size_t (*decompressionAlgo)(void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize); + +size_t HUF_decompress4X_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize) +{ + /* validation checks */ + if (dstSize == 0) + return ERROR(dstSize_tooSmall); + if (cSrcSize > dstSize) + return ERROR(corruption_detected); /* invalid */ + if (cSrcSize == dstSize) { + memcpy(dst, cSrc, dstSize); + return dstSize; + } /* not compressed */ + if (cSrcSize == 1) { + memset(dst, *(const BYTE *)cSrc, dstSize); + return dstSize; + } /* RLE */ + + { + U32 const algoNb = HUF_selectDecoder(dstSize, cSrcSize); + return algoNb ? HUF_decompress4X4_DCtx_wksp(dctx, dst, dstSize, cSrc, cSrcSize, workspace, workspaceSize) + : HUF_decompress4X2_DCtx_wksp(dctx, dst, dstSize, cSrc, cSrcSize, workspace, workspaceSize); + } +} + +size_t HUF_decompress4X_hufOnly_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize) +{ + /* validation checks */ + if (dstSize == 0) + return ERROR(dstSize_tooSmall); + if ((cSrcSize >= dstSize) || (cSrcSize <= 1)) + return ERROR(corruption_detected); /* invalid */ + + { + U32 const algoNb = HUF_selectDecoder(dstSize, cSrcSize); + return algoNb ? HUF_decompress4X4_DCtx_wksp(dctx, dst, dstSize, cSrc, cSrcSize, workspace, workspaceSize) + : HUF_decompress4X2_DCtx_wksp(dctx, dst, dstSize, cSrc, cSrcSize, workspace, workspaceSize); + } +} + +size_t HUF_decompress1X_DCtx_wksp(HUF_DTable *dctx, void *dst, size_t dstSize, const void *cSrc, size_t cSrcSize, void *workspace, size_t workspaceSize) +{ + /* validation checks */ + if (dstSize == 0) + return ERROR(dstSize_tooSmall); + if (cSrcSize > dstSize) + return ERROR(corruption_detected); /* invalid */ + if (cSrcSize == dstSize) { + memcpy(dst, cSrc, dstSize); + return dstSize; + } /* not compressed */ + if (cSrcSize == 1) { + memset(dst, *(const BYTE *)cSrc, dstSize); + return dstSize; + } /* RLE */ + + { + U32 const algoNb = HUF_selectDecoder(dstSize, cSrcSize); + return algoNb ? HUF_decompress1X4_DCtx_wksp(dctx, dst, dstSize, cSrc, cSrcSize, workspace, workspaceSize) + : HUF_decompress1X2_DCtx_wksp(dctx, dst, dstSize, cSrc, cSrcSize, workspace, workspaceSize); + } +} diff --git a/lib/zstd/mem.h b/lib/zstd/mem.h new file mode 100644 index 00000000000..7225b39742c --- /dev/null +++ b/lib/zstd/mem.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause-Clear) */ +/** + * Copyright (c) 2016-present, Yann Collet, Facebook, Inc. + * All rights reserved. + */ + +#ifndef MEM_H_MODULE +#define MEM_H_MODULE + +/*-**************************************** +* Dependencies +******************************************/ +#include <asm/unaligned.h> +#include <compiler.h> +#include <linux/string.h> /* memcpy */ +#include <linux/types.h> /* size_t, ptrdiff_t */ + +/*-**************************************** +* Compiler specifics +******************************************/ +#define ZSTD_STATIC static __inline __attribute__((unused)) + +/*-************************************************************** +* Basic Types +*****************************************************************/ +typedef uint8_t BYTE; +typedef uint16_t U16; +typedef int16_t S16; +typedef uint32_t U32; +typedef int32_t S32; +typedef uint64_t U64; +typedef int64_t S64; +typedef ptrdiff_t iPtrDiff; +typedef uintptr_t uPtrDiff; + +/*-************************************************************** +* Memory I/O +*****************************************************************/ +ZSTD_STATIC unsigned ZSTD_32bits(void) { return sizeof(size_t) == 4; } +ZSTD_STATIC unsigned ZSTD_64bits(void) { return sizeof(size_t) == 8; } + +#if defined(__LITTLE_ENDIAN) +#define ZSTD_LITTLE_ENDIAN 1 +#else +#define ZSTD_LITTLE_ENDIAN 0 +#endif + +ZSTD_STATIC unsigned ZSTD_isLittleEndian(void) { return ZSTD_LITTLE_ENDIAN; } + +ZSTD_STATIC U16 ZSTD_read16(const void *memPtr) { return get_unaligned((const U16 *)memPtr); } + +ZSTD_STATIC U32 ZSTD_read32(const void *memPtr) { return get_unaligned((const U32 *)memPtr); } + +ZSTD_STATIC U64 ZSTD_read64(const void *memPtr) { return get_unaligned((const U64 *)memPtr); } + +ZSTD_STATIC size_t ZSTD_readST(const void *memPtr) { return get_unaligned((const size_t *)memPtr); } + +ZSTD_STATIC void ZSTD_write16(void *memPtr, U16 value) { put_unaligned(value, (U16 *)memPtr); } + +ZSTD_STATIC void ZSTD_write32(void *memPtr, U32 value) { put_unaligned(value, (U32 *)memPtr); } + +ZSTD_STATIC void ZSTD_write64(void *memPtr, U64 value) { put_unaligned(value, (U64 *)memPtr); } + +/*=== Little endian r/w ===*/ + +ZSTD_STATIC U16 ZSTD_readLE16(const void *memPtr) { return get_unaligned_le16(memPtr); } + +ZSTD_STATIC void ZSTD_writeLE16(void *memPtr, U16 val) { put_unaligned_le16(val, memPtr); } + +ZSTD_STATIC U32 ZSTD_readLE24(const void *memPtr) { return ZSTD_readLE16(memPtr) + (((const BYTE *)memPtr)[2] << 16); } + +ZSTD_STATIC void ZSTD_writeLE24(void *memPtr, U32 val) +{ + ZSTD_writeLE16(memPtr, (U16)val); + ((BYTE *)memPtr)[2] = (BYTE)(val >> 16); +} + +ZSTD_STATIC U32 ZSTD_readLE32(const void *memPtr) { return get_unaligned_le32(memPtr); } + +ZSTD_STATIC void ZSTD_writeLE32(void *memPtr, U32 val32) { put_unaligned_le32(val32, memPtr); } + +ZSTD_STATIC U64 ZSTD_readLE64(const void *memPtr) { return get_unaligned_le64(memPtr); } + +ZSTD_STATIC void ZSTD_writeLE64(void *memPtr, U64 val64) { put_unaligned_le64(val64, memPtr); } + +ZSTD_STATIC size_t ZSTD_readLEST(const void *memPtr) +{ + if (ZSTD_32bits()) + return (size_t)ZSTD_readLE32(memPtr); + else + return (size_t)ZSTD_readLE64(memPtr); +} + +ZSTD_STATIC void ZSTD_writeLEST(void *memPtr, size_t val) +{ + if (ZSTD_32bits()) + ZSTD_writeLE32(memPtr, (U32)val); + else + ZSTD_writeLE64(memPtr, (U64)val); +} + +/*=== Big endian r/w ===*/ + +ZSTD_STATIC U32 ZSTD_readBE32(const void *memPtr) { return get_unaligned_be32(memPtr); } + +ZSTD_STATIC void ZSTD_writeBE32(void *memPtr, U32 val32) { put_unaligned_be32(val32, memPtr); } + +ZSTD_STATIC U64 ZSTD_readBE64(const void *memPtr) { return get_unaligned_be64(memPtr); } + +ZSTD_STATIC void ZSTD_writeBE64(void *memPtr, U64 val64) { put_unaligned_be64(val64, memPtr); } + +ZSTD_STATIC size_t ZSTD_readBEST(const void *memPtr) +{ + if (ZSTD_32bits()) + return (size_t)ZSTD_readBE32(memPtr); + else + return (size_t)ZSTD_readBE64(memPtr); +} + +ZSTD_STATIC void ZSTD_writeBEST(void *memPtr, size_t val) +{ + if (ZSTD_32bits()) + ZSTD_writeBE32(memPtr, (U32)val); + else + ZSTD_writeBE64(memPtr, (U64)val); +} + +/* function safe only for comparisons */ +ZSTD_STATIC U32 ZSTD_readMINMATCH(const void *memPtr, U32 length) +{ + switch (length) { + default: + case 4: return ZSTD_read32(memPtr); + case 3: + if (ZSTD_isLittleEndian()) + return ZSTD_read32(memPtr) << 8; + else + return ZSTD_read32(memPtr) >> 8; + } +} + +#endif /* MEM_H_MODULE */ diff --git a/lib/zstd/zstd_common.c b/lib/zstd/zstd_common.c new file mode 100644 index 00000000000..9a217e15739 --- /dev/null +++ b/lib/zstd/zstd_common.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause-Clear) +/** + * Copyright (c) 2016-present, Yann Collet, Facebook, Inc. + * All rights reserved. + */ + +/*-************************************* +* Dependencies +***************************************/ +#include "error_private.h" +#include "zstd_internal.h" /* declaration of ZSTD_isError, ZSTD_getErrorName, ZSTD_getErrorCode, ZSTD_getErrorString, ZSTD_versionNumber */ +#include <linux/kernel.h> + +/*=************************************************************** +* Custom allocator +****************************************************************/ + +#define stack_push(stack, size) \ + ({ \ + void *const ptr = ZSTD_PTR_ALIGN((stack)->ptr); \ + (stack)->ptr = (char *)ptr + (size); \ + (stack)->ptr <= (stack)->end ? ptr : NULL; \ + }) + +ZSTD_customMem ZSTD_initStack(void *workspace, size_t workspaceSize) +{ + ZSTD_customMem stackMem = {ZSTD_stackAlloc, ZSTD_stackFree, workspace}; + ZSTD_stack *stack = (ZSTD_stack *)workspace; + /* Verify preconditions */ + if (!workspace || workspaceSize < sizeof(ZSTD_stack) || workspace != ZSTD_PTR_ALIGN(workspace)) { + ZSTD_customMem error = {NULL, NULL, NULL}; + return error; + } + /* Initialize the stack */ + stack->ptr = workspace; + stack->end = (char *)workspace + workspaceSize; + stack_push(stack, sizeof(ZSTD_stack)); + return stackMem; +} + +void *ZSTD_stackAllocAll(void *opaque, size_t *size) +{ + ZSTD_stack *stack = (ZSTD_stack *)opaque; + *size = (BYTE const *)stack->end - (BYTE *)ZSTD_PTR_ALIGN(stack->ptr); + return stack_push(stack, *size); +} + +void *ZSTD_stackAlloc(void *opaque, size_t size) +{ + ZSTD_stack *stack = (ZSTD_stack *)opaque; + return stack_push(stack, size); +} +void ZSTD_stackFree(void *opaque, void *address) +{ + (void)opaque; + (void)address; +} + +void *ZSTD_malloc(size_t size, ZSTD_customMem customMem) { return customMem.customAlloc(customMem.opaque, size); } + +void ZSTD_free(void *ptr, ZSTD_customMem customMem) +{ + if (ptr != NULL) + customMem.customFree(customMem.opaque, ptr); +} diff --git a/lib/zstd/zstd_internal.h b/lib/zstd/zstd_internal.h new file mode 100644 index 00000000000..551340c8b51 --- /dev/null +++ b/lib/zstd/zstd_internal.h @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause-Clear) */ +/** + * Copyright (c) 2016-present, Yann Collet, Facebook, Inc. + * All rights reserved. + */ + +#ifndef ZSTD_CCOMMON_H_MODULE +#define ZSTD_CCOMMON_H_MODULE + +/*-******************************************************* +* Compiler specifics +*********************************************************/ +#define FORCE_INLINE static __always_inline +#define FORCE_NOINLINE static noinline + +/*-************************************* +* Dependencies +***************************************/ +#include "error_private.h" +#include "mem.h" +#include <linux/compiler.h> +#include <linux/kernel.h> +#include <linux/xxhash.h> +#include <linux/zstd.h> + +/*-************************************* +* shared macros +***************************************/ +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define CHECK_F(f) \ + { \ + size_t const errcod = f; \ + if (ERR_isError(errcod)) \ + return errcod; \ + } /* check and Forward error code */ +#define CHECK_E(f, e) \ + { \ + size_t const errcod = f; \ + if (ERR_isError(errcod)) \ + return ERROR(e); \ + } /* check and send Error code */ +#define ZSTD_STATIC_ASSERT(c) \ + { \ + enum { ZSTD_static_assert = 1 / (int)(!!(c)) }; \ + } + +/*-************************************* +* Common constants +***************************************/ +#define ZSTD_OPT_NUM (1 << 12) +#define ZSTD_DICT_MAGIC 0xEC30A437 /* v0.7+ */ + +#define ZSTD_REP_NUM 3 /* number of repcodes */ +#define ZSTD_REP_CHECK (ZSTD_REP_NUM) /* number of repcodes to check by the optimal parser */ +#define ZSTD_REP_MOVE (ZSTD_REP_NUM - 1) +#define ZSTD_REP_MOVE_OPT (ZSTD_REP_NUM) +static const U32 repStartValue[ZSTD_REP_NUM] = {1, 4, 8}; + +#define KB *(1 << 10) +#define MB *(1 << 20) +#define GB *(1U << 30) + +#define BIT7 128 +#define BIT6 64 +#define BIT5 32 +#define BIT4 16 +#define BIT1 2 +#define BIT0 1 + +#define ZSTD_WINDOWLOG_ABSOLUTEMIN 10 +static const size_t ZSTD_fcs_fieldSize[4] = {0, 2, 4, 8}; +static const size_t ZSTD_did_fieldSize[4] = {0, 1, 2, 4}; + +#define ZSTD_BLOCKHEADERSIZE 3 /* C standard doesn't allow `static const` variable to be init using another `static const` variable */ +static const size_t ZSTD_blockHeaderSize = ZSTD_BLOCKHEADERSIZE; +typedef enum { bt_raw, bt_rle, bt_compressed, bt_reserved } blockType_e; + +#define MIN_SEQUENCES_SIZE 1 /* nbSeq==0 */ +#define MIN_CBLOCK_SIZE (1 /*litCSize*/ + 1 /* RLE or RAW */ + MIN_SEQUENCES_SIZE /* nbSeq==0 */) /* for a non-null block */ + +#define HufLog 12 +typedef enum { set_basic, set_rle, set_compressed, set_repeat } symbolEncodingType_e; + +#define LONGNBSEQ 0x7F00 + +#define MINMATCH 3 +#define EQUAL_READ32 4 + +#define Litbits 8 +#define MaxLit ((1 << Litbits) - 1) +#define MaxML 52 +#define MaxLL 35 +#define MaxOff 28 +#define MaxSeq MAX(MaxLL, MaxML) /* Assumption : MaxOff < MaxLL,MaxML */ +#define MLFSELog 9 +#define LLFSELog 9 +#define OffFSELog 8 + +static const U32 LL_bits[MaxLL + 1] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; +static const S16 LL_defaultNorm[MaxLL + 1] = {4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 2, 1, 1, 1, 1, 1, -1, -1, -1, -1}; +#define LL_DEFAULTNORMLOG 6 /* for static allocation */ +static const U32 LL_defaultNormLog = LL_DEFAULTNORMLOG; + +static const U32 ML_bits[MaxML + 1] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; +static const S16 ML_defaultNorm[MaxML + 1] = {1, 4, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1}; +#define ML_DEFAULTNORMLOG 6 /* for static allocation */ +static const U32 ML_defaultNormLog = ML_DEFAULTNORMLOG; + +static const S16 OF_defaultNorm[MaxOff + 1] = {1, 1, 1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, -1, -1, -1, -1, -1}; +#define OF_DEFAULTNORMLOG 5 /* for static allocation */ +static const U32 OF_defaultNormLog = OF_DEFAULTNORMLOG; + +/*-******************************************* +* Shared functions to include for inlining +*********************************************/ +ZSTD_STATIC void ZSTD_copy8(void *dst, const void *src) { + memcpy(dst, src, 8); +} +/*! ZSTD_wildcopy() : +* custom version of memcpy(), can copy up to 7 bytes too many (8 bytes if length==0) */ +#define WILDCOPY_OVERLENGTH 8 +ZSTD_STATIC void ZSTD_wildcopy(void *dst, const void *src, ptrdiff_t length) +{ + const BYTE* ip = (const BYTE*)src; + BYTE* op = (BYTE*)dst; + BYTE* const oend = op + length; + /* Work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81388. + * Avoid the bad case where the loop only runs once by handling the + * special case separately. This doesn't trigger the bug because it + * doesn't involve pointer/integer overflow. + */ + if (length <= 8) + return ZSTD_copy8(dst, src); + do { + ZSTD_copy8(op, ip); + op += 8; + ip += 8; + } while (op < oend); +} + +/*-******************************************* +* Private interfaces +*********************************************/ +typedef struct ZSTD_stats_s ZSTD_stats_t; + +typedef struct { + U32 off; + U32 len; +} ZSTD_match_t; + +typedef struct { + U32 price; + U32 off; + U32 mlen; + U32 litlen; + U32 rep[ZSTD_REP_NUM]; +} ZSTD_optimal_t; + +typedef struct seqDef_s { + U32 offset; + U16 litLength; + U16 matchLength; +} seqDef; + +typedef struct { + seqDef *sequencesStart; + seqDef *sequences; + BYTE *litStart; + BYTE *lit; + BYTE *llCode; + BYTE *mlCode; + BYTE *ofCode; + U32 longLengthID; /* 0 == no longLength; 1 == Lit.longLength; 2 == Match.longLength; */ + U32 longLengthPos; + /* opt */ + ZSTD_optimal_t *priceTable; + ZSTD_match_t *matchTable; + U32 *matchLengthFreq; + U32 *litLengthFreq; + U32 *litFreq; + U32 *offCodeFreq; + U32 matchLengthSum; + U32 matchSum; + U32 litLengthSum; + U32 litSum; + U32 offCodeSum; + U32 log2matchLengthSum; + U32 log2matchSum; + U32 log2litLengthSum; + U32 log2litSum; + U32 log2offCodeSum; + U32 factor; + U32 staticPrices; + U32 cachedPrice; + U32 cachedLitLength; + const BYTE *cachedLiterals; +} seqStore_t; + +const seqStore_t *ZSTD_getSeqStore(const ZSTD_CCtx *ctx); +void ZSTD_seqToCodes(const seqStore_t *seqStorePtr); +int ZSTD_isSkipFrame(ZSTD_DCtx *dctx); + +/*= Custom memory allocation functions */ +typedef void *(*ZSTD_allocFunction)(void *opaque, size_t size); +typedef void (*ZSTD_freeFunction)(void *opaque, void *address); +typedef struct { + ZSTD_allocFunction customAlloc; + ZSTD_freeFunction customFree; + void *opaque; +} ZSTD_customMem; + +void *ZSTD_malloc(size_t size, ZSTD_customMem customMem); +void ZSTD_free(void *ptr, ZSTD_customMem customMem); + +/*====== stack allocation ======*/ + +typedef struct { + void *ptr; + const void *end; +} ZSTD_stack; + +#define ZSTD_ALIGN(x) ALIGN(x, sizeof(size_t)) +#define ZSTD_PTR_ALIGN(p) PTR_ALIGN(p, sizeof(size_t)) + +ZSTD_customMem ZSTD_initStack(void *workspace, size_t workspaceSize); + +void *ZSTD_stackAllocAll(void *opaque, size_t *size); +void *ZSTD_stackAlloc(void *opaque, size_t size); +void ZSTD_stackFree(void *opaque, void *address); + +/*====== common function ======*/ + +ZSTD_STATIC U32 ZSTD_highbit32(U32 val) { return 31 - __builtin_clz(val); } + +/* hidden functions */ + +/* ZSTD_invalidateRepCodes() : + * ensures next compression will not use repcodes from previous block. + * Note : only works with regular variant; + * do not use with extDict variant ! */ +void ZSTD_invalidateRepCodes(ZSTD_CCtx *cctx); + +size_t ZSTD_freeCCtx(ZSTD_CCtx *cctx); +size_t ZSTD_freeDCtx(ZSTD_DCtx *dctx); +size_t ZSTD_freeCDict(ZSTD_CDict *cdict); +size_t ZSTD_freeDDict(ZSTD_DDict *cdict); +size_t ZSTD_freeCStream(ZSTD_CStream *zcs); +size_t ZSTD_freeDStream(ZSTD_DStream *zds); + +#endif /* ZSTD_CCOMMON_H_MODULE */ diff --git a/lib/zstd/zstd_opt.h b/lib/zstd/zstd_opt.h new file mode 100644 index 00000000000..af0aaf5b20d --- /dev/null +++ b/lib/zstd/zstd_opt.h @@ -0,0 +1,1004 @@ +/* SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause-Clear) */ +/** + * Copyright (c) 2016-present, Przemyslaw Skibinski, Yann Collet, Facebook, Inc. + * All rights reserved. + */ + +/* Note : this file is intended to be included within zstd_compress.c */ + +#ifndef ZSTD_OPT_H_91842398743 +#define ZSTD_OPT_H_91842398743 + +#define ZSTD_LITFREQ_ADD 2 +#define ZSTD_FREQ_DIV 4 +#define ZSTD_MAX_PRICE (1 << 30) + +/*-************************************* +* Price functions for optimal parser +***************************************/ +FORCE_INLINE void ZSTD_setLog2Prices(seqStore_t *ssPtr) +{ + ssPtr->log2matchLengthSum = ZSTD_highbit32(ssPtr->matchLengthSum + 1); + ssPtr->log2litLengthSum = ZSTD_highbit32(ssPtr->litLengthSum + 1); + ssPtr->log2litSum = ZSTD_highbit32(ssPtr->litSum + 1); + ssPtr->log2offCodeSum = ZSTD_highbit32(ssPtr->offCodeSum + 1); + ssPtr->factor = 1 + ((ssPtr->litSum >> 5) / ssPtr->litLengthSum) + ((ssPtr->litSum << 1) / (ssPtr->litSum + ssPtr->matchSum)); +} + +ZSTD_STATIC void ZSTD_rescaleFreqs(seqStore_t *ssPtr, const BYTE *src, size_t srcSize) +{ + unsigned u; + + ssPtr->cachedLiterals = NULL; + ssPtr->cachedPrice = ssPtr->cachedLitLength = 0; + ssPtr->staticPrices = 0; + + if (ssPtr->litLengthSum == 0) { + if (srcSize <= 1024) + ssPtr->staticPrices = 1; + + for (u = 0; u <= MaxLit; u++) + ssPtr->litFreq[u] = 0; + for (u = 0; u < srcSize; u++) + ssPtr->litFreq[src[u]]++; + + ssPtr->litSum = 0; + ssPtr->litLengthSum = MaxLL + 1; + ssPtr->matchLengthSum = MaxML + 1; + ssPtr->offCodeSum = (MaxOff + 1); + ssPtr->matchSum = (ZSTD_LITFREQ_ADD << Litbits); + + for (u = 0; u <= MaxLit; u++) { + ssPtr->litFreq[u] = 1 + (ssPtr->litFreq[u] >> ZSTD_FREQ_DIV); + ssPtr->litSum += ssPtr->litFreq[u]; + } + for (u = 0; u <= MaxLL; u++) + ssPtr->litLengthFreq[u] = 1; + for (u = 0; u <= MaxML; u++) + ssPtr->matchLengthFreq[u] = 1; + for (u = 0; u <= MaxOff; u++) + ssPtr->offCodeFreq[u] = 1; + } else { + ssPtr->matchLengthSum = 0; + ssPtr->litLengthSum = 0; + ssPtr->offCodeSum = 0; + ssPtr->matchSum = 0; + ssPtr->litSum = 0; + + for (u = 0; u <= MaxLit; u++) { + ssPtr->litFreq[u] = 1 + (ssPtr->litFreq[u] >> (ZSTD_FREQ_DIV + 1)); + ssPtr->litSum += ssPtr->litFreq[u]; + } + for (u = 0; u <= MaxLL; u++) { + ssPtr->litLengthFreq[u] = 1 + (ssPtr->litLengthFreq[u] >> (ZSTD_FREQ_DIV + 1)); + ssPtr->litLengthSum += ssPtr->litLengthFreq[u]; + } + for (u = 0; u <= MaxML; u++) { + ssPtr->matchLengthFreq[u] = 1 + (ssPtr->matchLengthFreq[u] >> ZSTD_FREQ_DIV); + ssPtr->matchLengthSum += ssPtr->matchLengthFreq[u]; + ssPtr->matchSum += ssPtr->matchLengthFreq[u] * (u + 3); + } + ssPtr->matchSum *= ZSTD_LITFREQ_ADD; + for (u = 0; u <= MaxOff; u++) { + ssPtr->offCodeFreq[u] = 1 + (ssPtr->offCodeFreq[u] >> ZSTD_FREQ_DIV); + ssPtr->offCodeSum += ssPtr->offCodeFreq[u]; + } + } + + ZSTD_setLog2Prices(ssPtr); +} + +FORCE_INLINE U32 ZSTD_getLiteralPrice(seqStore_t *ssPtr, U32 litLength, const BYTE *literals) +{ + U32 price, u; + + if (ssPtr->staticPrices) + return ZSTD_highbit32((U32)litLength + 1) + (litLength * 6); + + if (litLength == 0) + return ssPtr->log2litLengthSum - ZSTD_highbit32(ssPtr->litLengthFreq[0] + 1); + + /* literals */ + if (ssPtr->cachedLiterals == literals) { + U32 const additional = litLength - ssPtr->cachedLitLength; + const BYTE *literals2 = ssPtr->cachedLiterals + ssPtr->cachedLitLength; + price = ssPtr->cachedPrice + additional * ssPtr->log2litSum; + for (u = 0; u < additional; u++) + price -= ZSTD_highbit32(ssPtr->litFreq[literals2[u]] + 1); + ssPtr->cachedPrice = price; + ssPtr->cachedLitLength = litLength; + } else { + price = litLength * ssPtr->log2litSum; + for (u = 0; u < litLength; u++) + price -= ZSTD_highbit32(ssPtr->litFreq[literals[u]] + 1); + + if (litLength >= 12) { + ssPtr->cachedLiterals = literals; + ssPtr->cachedPrice = price; + ssPtr->cachedLitLength = litLength; + } + } + + /* literal Length */ + { + const BYTE LL_deltaCode = 19; + const BYTE llCode = (litLength > 63) ? (BYTE)ZSTD_highbit32(litLength) + LL_deltaCode : LL_Code[litLength]; + price += LL_bits[llCode] + ssPtr->log2litLengthSum - ZSTD_highbit32(ssPtr->litLengthFreq[llCode] + 1); + } + + return price; +} + +FORCE_INLINE U32 ZSTD_getPrice(seqStore_t *seqStorePtr, U32 litLength, const BYTE *literals, U32 offset, U32 matchLength, const int ultra) +{ + /* offset */ + U32 price; + BYTE const offCode = (BYTE)ZSTD_highbit32(offset + 1); + + if (seqStorePtr->staticPrices) + return ZSTD_getLiteralPrice(seqStorePtr, litLength, literals) + ZSTD_highbit32((U32)matchLength + 1) + 16 + offCode; + + price = offCode + seqStorePtr->log2offCodeSum - ZSTD_highbit32(seqStorePtr->offCodeFreq[offCode] + 1); + if (!ultra && offCode >= 20) + price += (offCode - 19) * 2; + + /* match Length */ + { + const BYTE ML_deltaCode = 36; + const BYTE mlCode = (matchLength > 127) ? (BYTE)ZSTD_highbit32(matchLength) + ML_deltaCode : ML_Code[matchLength]; + price += ML_bits[mlCode] + seqStorePtr->log2matchLengthSum - ZSTD_highbit32(seqStorePtr->matchLengthFreq[mlCode] + 1); + } + + return price + ZSTD_getLiteralPrice(seqStorePtr, litLength, literals) + seqStorePtr->factor; +} + +ZSTD_STATIC void ZSTD_updatePrice(seqStore_t *seqStorePtr, U32 litLength, const BYTE *literals, U32 offset, U32 matchLength) +{ + U32 u; + + /* literals */ + seqStorePtr->litSum += litLength * ZSTD_LITFREQ_ADD; + for (u = 0; u < litLength; u++) + seqStorePtr->litFreq[literals[u]] += ZSTD_LITFREQ_ADD; + + /* literal Length */ + { + const BYTE LL_deltaCode = 19; + const BYTE llCode = (litLength > 63) ? (BYTE)ZSTD_highbit32(litLength) + LL_deltaCode : LL_Code[litLength]; + seqStorePtr->litLengthFreq[llCode]++; + seqStorePtr->litLengthSum++; + } + + /* match offset */ + { + BYTE const offCode = (BYTE)ZSTD_highbit32(offset + 1); + seqStorePtr->offCodeSum++; + seqStorePtr->offCodeFreq[offCode]++; + } + + /* match Length */ + { + const BYTE ML_deltaCode = 36; + const BYTE mlCode = (matchLength > 127) ? (BYTE)ZSTD_highbit32(matchLength) + ML_deltaCode : ML_Code[matchLength]; + seqStorePtr->matchLengthFreq[mlCode]++; + seqStorePtr->matchLengthSum++; + } + + ZSTD_setLog2Prices(seqStorePtr); +} + +#define SET_PRICE(pos, mlen_, offset_, litlen_, price_) \ + { \ + while (last_pos < pos) { \ + opt[last_pos + 1].price = ZSTD_MAX_PRICE; \ + last_pos++; \ + } \ + opt[pos].mlen = mlen_; \ + opt[pos].off = offset_; \ + opt[pos].litlen = litlen_; \ + opt[pos].price = price_; \ + } + +/* Update hashTable3 up to ip (excluded) + Assumption : always within prefix (i.e. not within extDict) */ +FORCE_INLINE +U32 ZSTD_insertAndFindFirstIndexHash3(ZSTD_CCtx *zc, const BYTE *ip) +{ + U32 *const hashTable3 = zc->hashTable3; + U32 const hashLog3 = zc->hashLog3; + const BYTE *const base = zc->base; + U32 idx = zc->nextToUpdate3; + const U32 target = zc->nextToUpdate3 = (U32)(ip - base); + const size_t hash3 = ZSTD_hash3Ptr(ip, hashLog3); + + while (idx < target) { + hashTable3[ZSTD_hash3Ptr(base + idx, hashLog3)] = idx; + idx++; + } + + return hashTable3[hash3]; +} + +/*-************************************* +* Binary Tree search +***************************************/ +static U32 ZSTD_insertBtAndGetAllMatches(ZSTD_CCtx *zc, const BYTE *const ip, const BYTE *const iLimit, U32 nbCompares, const U32 mls, U32 extDict, + ZSTD_match_t *matches, const U32 minMatchLen) +{ + const BYTE *const base = zc->base; + const U32 curr = (U32)(ip - base); + const U32 hashLog = zc->params.cParams.hashLog; + const size_t h = ZSTD_hashPtr(ip, hashLog, mls); + U32 *const hashTable = zc->hashTable; + U32 matchIndex = hashTable[h]; + U32 *const bt = zc->chainTable; + const U32 btLog = zc->params.cParams.chainLog - 1; + const U32 btMask = (1U << btLog) - 1; + size_t commonLengthSmaller = 0, commonLengthLarger = 0; + const BYTE *const dictBase = zc->dictBase; + const U32 dictLimit = zc->dictLimit; + const BYTE *const dictEnd = dictBase + dictLimit; + const BYTE *const prefixStart = base + dictLimit; + const U32 btLow = btMask >= curr ? 0 : curr - btMask; + const U32 windowLow = zc->lowLimit; + U32 *smallerPtr = bt + 2 * (curr & btMask); + U32 *largerPtr = bt + 2 * (curr & btMask) + 1; + U32 matchEndIdx = curr + 8; + U32 dummy32; /* to be nullified at the end */ + U32 mnum = 0; + + const U32 minMatch = (mls == 3) ? 3 : 4; + size_t bestLength = minMatchLen - 1; + + if (minMatch == 3) { /* HC3 match finder */ + U32 const matchIndex3 = ZSTD_insertAndFindFirstIndexHash3(zc, ip); + if (matchIndex3 > windowLow && (curr - matchIndex3 < (1 << 18))) { + const BYTE *match; + size_t currMl = 0; + if ((!extDict) || matchIndex3 >= dictLimit) { + match = base + matchIndex3; + if (match[bestLength] == ip[bestLength]) + currMl = ZSTD_count(ip, match, iLimit); + } else { + match = dictBase + matchIndex3; + if (ZSTD_readMINMATCH(match, MINMATCH) == + ZSTD_readMINMATCH(ip, MINMATCH)) /* assumption : matchIndex3 <= dictLimit-4 (by table construction) */ + currMl = ZSTD_count_2segments(ip + MINMATCH, match + MINMATCH, iLimit, dictEnd, prefixStart) + MINMATCH; + } + + /* save best solution */ + if (currMl > bestLength) { + bestLength = currMl; + matches[mnum].off = ZSTD_REP_MOVE_OPT + curr - matchIndex3; + matches[mnum].len = (U32)currMl; + mnum++; + if (currMl > ZSTD_OPT_NUM) + goto update; + if (ip + currMl == iLimit) + goto update; /* best possible, and avoid read overflow*/ + } + } + } + + hashTable[h] = curr; /* Update Hash Table */ + + while (nbCompares-- && (matchIndex > windowLow)) { + U32 *nextPtr = bt + 2 * (matchIndex & btMask); + size_t matchLength = MIN(commonLengthSmaller, commonLengthLarger); /* guaranteed minimum nb of common bytes */ + const BYTE *match; + + if ((!extDict) || (matchIndex + matchLength >= dictLimit)) { + match = base + matchIndex; + if (match[matchLength] == ip[matchLength]) { + matchLength += ZSTD_count(ip + matchLength + 1, match + matchLength + 1, iLimit) + 1; + } + } else { + match = dictBase + matchIndex; + matchLength += ZSTD_count_2segments(ip + matchLength, match + matchLength, iLimit, dictEnd, prefixStart); + if (matchIndex + matchLength >= dictLimit) + match = base + matchIndex; /* to prepare for next usage of match[matchLength] */ + } + + if (matchLength > bestLength) { + if (matchLength > matchEndIdx - matchIndex) + matchEndIdx = matchIndex + (U32)matchLength; + bestLength = matchLength; + matches[mnum].off = ZSTD_REP_MOVE_OPT + curr - matchIndex; + matches[mnum].len = (U32)matchLength; + mnum++; + if (matchLength > ZSTD_OPT_NUM) + break; + if (ip + matchLength == iLimit) /* equal : no way to know if inf or sup */ + break; /* drop, to guarantee consistency (miss a little bit of compression) */ + } + + if (match[matchLength] < ip[matchLength]) { + /* match is smaller than curr */ + *smallerPtr = matchIndex; /* update smaller idx */ + commonLengthSmaller = matchLength; /* all smaller will now have at least this guaranteed common length */ + if (matchIndex <= btLow) { + smallerPtr = &dummy32; + break; + } /* beyond tree size, stop the search */ + smallerPtr = nextPtr + 1; /* new "smaller" => larger of match */ + matchIndex = nextPtr[1]; /* new matchIndex larger than previous (closer to curr) */ + } else { + /* match is larger than curr */ + *largerPtr = matchIndex; + commonLengthLarger = matchLength; + if (matchIndex <= btLow) { + largerPtr = &dummy32; + break; + } /* beyond tree size, stop the search */ + largerPtr = nextPtr; + matchIndex = nextPtr[0]; + } + } + + *smallerPtr = *largerPtr = 0; + +update: + zc->nextToUpdate = (matchEndIdx > curr + 8) ? matchEndIdx - 8 : curr + 1; + return mnum; +} + +/** Tree updater, providing best match */ +static U32 ZSTD_BtGetAllMatches(ZSTD_CCtx *zc, const BYTE *const ip, const BYTE *const iLimit, const U32 maxNbAttempts, const U32 mls, ZSTD_match_t *matches, + const U32 minMatchLen) +{ + if (ip < zc->base + zc->nextToUpdate) + return 0; /* skipped area */ + ZSTD_updateTree(zc, ip, iLimit, maxNbAttempts, mls); + return ZSTD_insertBtAndGetAllMatches(zc, ip, iLimit, maxNbAttempts, mls, 0, matches, minMatchLen); +} + +static U32 ZSTD_BtGetAllMatches_selectMLS(ZSTD_CCtx *zc, /* Index table will be updated */ + const BYTE *ip, const BYTE *const iHighLimit, const U32 maxNbAttempts, const U32 matchLengthSearch, + ZSTD_match_t *matches, const U32 minMatchLen) +{ + switch (matchLengthSearch) { + case 3: return ZSTD_BtGetAllMatches(zc, ip, iHighLimit, maxNbAttempts, 3, matches, minMatchLen); + default: + case 4: return ZSTD_BtGetAllMatches(zc, ip, iHighLimit, maxNbAttempts, 4, matches, minMatchLen); + case 5: return ZSTD_BtGetAllMatches(zc, ip, iHighLimit, maxNbAttempts, 5, matches, minMatchLen); + case 7: + case 6: return ZSTD_BtGetAllMatches(zc, ip, iHighLimit, maxNbAttempts, 6, matches, minMatchLen); + } +} + +/** Tree updater, providing best match */ +static U32 ZSTD_BtGetAllMatches_extDict(ZSTD_CCtx *zc, const BYTE *const ip, const BYTE *const iLimit, const U32 maxNbAttempts, const U32 mls, + ZSTD_match_t *matches, const U32 minMatchLen) +{ + if (ip < zc->base + zc->nextToUpdate) + return 0; /* skipped area */ + ZSTD_updateTree_extDict(zc, ip, iLimit, maxNbAttempts, mls); + return ZSTD_insertBtAndGetAllMatches(zc, ip, iLimit, maxNbAttempts, mls, 1, matches, minMatchLen); +} + +static U32 ZSTD_BtGetAllMatches_selectMLS_extDict(ZSTD_CCtx *zc, /* Index table will be updated */ + const BYTE *ip, const BYTE *const iHighLimit, const U32 maxNbAttempts, const U32 matchLengthSearch, + ZSTD_match_t *matches, const U32 minMatchLen) +{ + switch (matchLengthSearch) { + case 3: return ZSTD_BtGetAllMatches_extDict(zc, ip, iHighLimit, maxNbAttempts, 3, matches, minMatchLen); + default: + case 4: return ZSTD_BtGetAllMatches_extDict(zc, ip, iHighLimit, maxNbAttempts, 4, matches, minMatchLen); + case 5: return ZSTD_BtGetAllMatches_extDict(zc, ip, iHighLimit, maxNbAttempts, 5, matches, minMatchLen); + case 7: + case 6: return ZSTD_BtGetAllMatches_extDict(zc, ip, iHighLimit, maxNbAttempts, 6, matches, minMatchLen); + } +} + +/*-******************************* +* Optimal parser +*********************************/ +FORCE_INLINE +void ZSTD_compressBlock_opt_generic(ZSTD_CCtx *ctx, const void *src, size_t srcSize, const int ultra) +{ + seqStore_t *seqStorePtr = &(ctx->seqStore); + const BYTE *const istart = (const BYTE *)src; + const BYTE *ip = istart; + const BYTE *anchor = istart; + const BYTE *const iend = istart + srcSize; + const BYTE *const ilimit = iend - 8; + const BYTE *const base = ctx->base; + const BYTE *const prefixStart = base + ctx->dictLimit; + + const U32 maxSearches = 1U << ctx->params.cParams.searchLog; + const U32 sufficient_len = ctx->params.cParams.targetLength; + const U32 mls = ctx->params.cParams.searchLength; + const U32 minMatch = (ctx->params.cParams.searchLength == 3) ? 3 : 4; + + ZSTD_optimal_t *opt = seqStorePtr->priceTable; + ZSTD_match_t *matches = seqStorePtr->matchTable; + const BYTE *inr; + U32 offset, rep[ZSTD_REP_NUM]; + + /* init */ + ctx->nextToUpdate3 = ctx->nextToUpdate; + ZSTD_rescaleFreqs(seqStorePtr, (const BYTE *)src, srcSize); + ip += (ip == prefixStart); + { + U32 i; + for (i = 0; i < ZSTD_REP_NUM; i++) + rep[i] = ctx->rep[i]; + } + + /* Match Loop */ + while (ip < ilimit) { + U32 cur, match_num, last_pos, litlen, price; + U32 u, mlen, best_mlen, best_off, litLength; + memset(opt, 0, sizeof(ZSTD_optimal_t)); + last_pos = 0; + litlen = (U32)(ip - anchor); + + /* check repCode */ + { + U32 i, last_i = ZSTD_REP_CHECK + (ip == anchor); + for (i = (ip == anchor); i < last_i; i++) { + const S32 repCur = (i == ZSTD_REP_MOVE_OPT) ? (rep[0] - 1) : rep[i]; + if ((repCur > 0) && (repCur < (S32)(ip - prefixStart)) && + (ZSTD_readMINMATCH(ip, minMatch) == ZSTD_readMINMATCH(ip - repCur, minMatch))) { + mlen = (U32)ZSTD_count(ip + minMatch, ip + minMatch - repCur, iend) + minMatch; + if (mlen > sufficient_len || mlen >= ZSTD_OPT_NUM) { + best_mlen = mlen; + best_off = i; + cur = 0; + last_pos = 1; + goto _storeSequence; + } + best_off = i - (ip == anchor); + do { + price = ZSTD_getPrice(seqStorePtr, litlen, anchor, best_off, mlen - MINMATCH, ultra); + if (mlen > last_pos || price < opt[mlen].price) + SET_PRICE(mlen, mlen, i, litlen, price); /* note : macro modifies last_pos */ + mlen--; + } while (mlen >= minMatch); + } + } + } + + match_num = ZSTD_BtGetAllMatches_selectMLS(ctx, ip, iend, maxSearches, mls, matches, minMatch); + + if (!last_pos && !match_num) { + ip++; + continue; + } + + if (match_num && (matches[match_num - 1].len > sufficient_len || matches[match_num - 1].len >= ZSTD_OPT_NUM)) { + best_mlen = matches[match_num - 1].len; + best_off = matches[match_num - 1].off; + cur = 0; + last_pos = 1; + goto _storeSequence; + } + + /* set prices using matches at position = 0 */ + best_mlen = (last_pos) ? last_pos : minMatch; + for (u = 0; u < match_num; u++) { + mlen = (u > 0) ? matches[u - 1].len + 1 : best_mlen; + best_mlen = matches[u].len; + while (mlen <= best_mlen) { + price = ZSTD_getPrice(seqStorePtr, litlen, anchor, matches[u].off - 1, mlen - MINMATCH, ultra); + if (mlen > last_pos || price < opt[mlen].price) + SET_PRICE(mlen, mlen, matches[u].off, litlen, price); /* note : macro modifies last_pos */ + mlen++; + } + } + + if (last_pos < minMatch) { + ip++; + continue; + } + + /* initialize opt[0] */ + { + U32 i; + for (i = 0; i < ZSTD_REP_NUM; i++) + opt[0].rep[i] = rep[i]; + } + opt[0].mlen = 1; + opt[0].litlen = litlen; + + /* check further positions */ + for (cur = 1; cur <= last_pos; cur++) { + inr = ip + cur; + + if (opt[cur - 1].mlen == 1) { + litlen = opt[cur - 1].litlen + 1; + if (cur > litlen) { + price = opt[cur - litlen].price + ZSTD_getLiteralPrice(seqStorePtr, litlen, inr - litlen); + } else + price = ZSTD_getLiteralPrice(seqStorePtr, litlen, anchor); + } else { + litlen = 1; + price = opt[cur - 1].price + ZSTD_getLiteralPrice(seqStorePtr, litlen, inr - 1); + } + + if (cur > last_pos || price <= opt[cur].price) + SET_PRICE(cur, 1, 0, litlen, price); + + if (cur == last_pos) + break; + + if (inr > ilimit) /* last match must start at a minimum distance of 8 from oend */ + continue; + + mlen = opt[cur].mlen; + if (opt[cur].off > ZSTD_REP_MOVE_OPT) { + opt[cur].rep[2] = opt[cur - mlen].rep[1]; + opt[cur].rep[1] = opt[cur - mlen].rep[0]; + opt[cur].rep[0] = opt[cur].off - ZSTD_REP_MOVE_OPT; + } else { + opt[cur].rep[2] = (opt[cur].off > 1) ? opt[cur - mlen].rep[1] : opt[cur - mlen].rep[2]; + opt[cur].rep[1] = (opt[cur].off > 0) ? opt[cur - mlen].rep[0] : opt[cur - mlen].rep[1]; + opt[cur].rep[0] = + ((opt[cur].off == ZSTD_REP_MOVE_OPT) && (mlen != 1)) ? (opt[cur - mlen].rep[0] - 1) : (opt[cur - mlen].rep[opt[cur].off]); + } + + best_mlen = minMatch; + { + U32 i, last_i = ZSTD_REP_CHECK + (mlen != 1); + for (i = (opt[cur].mlen != 1); i < last_i; i++) { /* check rep */ + const S32 repCur = (i == ZSTD_REP_MOVE_OPT) ? (opt[cur].rep[0] - 1) : opt[cur].rep[i]; + if ((repCur > 0) && (repCur < (S32)(inr - prefixStart)) && + (ZSTD_readMINMATCH(inr, minMatch) == ZSTD_readMINMATCH(inr - repCur, minMatch))) { + mlen = (U32)ZSTD_count(inr + minMatch, inr + minMatch - repCur, iend) + minMatch; + + if (mlen > sufficient_len || cur + mlen >= ZSTD_OPT_NUM) { + best_mlen = mlen; + best_off = i; + last_pos = cur + 1; + goto _storeSequence; + } + + best_off = i - (opt[cur].mlen != 1); + if (mlen > best_mlen) + best_mlen = mlen; + + do { + if (opt[cur].mlen == 1) { + litlen = opt[cur].litlen; + if (cur > litlen) { + price = opt[cur - litlen].price + ZSTD_getPrice(seqStorePtr, litlen, inr - litlen, + best_off, mlen - MINMATCH, ultra); + } else + price = ZSTD_getPrice(seqStorePtr, litlen, anchor, best_off, mlen - MINMATCH, ultra); + } else { + litlen = 0; + price = opt[cur].price + ZSTD_getPrice(seqStorePtr, 0, NULL, best_off, mlen - MINMATCH, ultra); + } + + if (cur + mlen > last_pos || price <= opt[cur + mlen].price) + SET_PRICE(cur + mlen, mlen, i, litlen, price); + mlen--; + } while (mlen >= minMatch); + } + } + } + + match_num = ZSTD_BtGetAllMatches_selectMLS(ctx, inr, iend, maxSearches, mls, matches, best_mlen); + + if (match_num > 0 && (matches[match_num - 1].len > sufficient_len || cur + matches[match_num - 1].len >= ZSTD_OPT_NUM)) { + best_mlen = matches[match_num - 1].len; + best_off = matches[match_num - 1].off; + last_pos = cur + 1; + goto _storeSequence; + } + + /* set prices using matches at position = cur */ + for (u = 0; u < match_num; u++) { + mlen = (u > 0) ? matches[u - 1].len + 1 : best_mlen; + best_mlen = matches[u].len; + + while (mlen <= best_mlen) { + if (opt[cur].mlen == 1) { + litlen = opt[cur].litlen; + if (cur > litlen) + price = opt[cur - litlen].price + ZSTD_getPrice(seqStorePtr, litlen, ip + cur - litlen, + matches[u].off - 1, mlen - MINMATCH, ultra); + else + price = ZSTD_getPrice(seqStorePtr, litlen, anchor, matches[u].off - 1, mlen - MINMATCH, ultra); + } else { + litlen = 0; + price = opt[cur].price + ZSTD_getPrice(seqStorePtr, 0, NULL, matches[u].off - 1, mlen - MINMATCH, ultra); + } + + if (cur + mlen > last_pos || (price < opt[cur + mlen].price)) + SET_PRICE(cur + mlen, mlen, matches[u].off, litlen, price); + + mlen++; + } + } + } + + best_mlen = opt[last_pos].mlen; + best_off = opt[last_pos].off; + cur = last_pos - best_mlen; + + /* store sequence */ +_storeSequence: /* cur, last_pos, best_mlen, best_off have to be set */ + opt[0].mlen = 1; + + while (1) { + mlen = opt[cur].mlen; + offset = opt[cur].off; + opt[cur].mlen = best_mlen; + opt[cur].off = best_off; + best_mlen = mlen; + best_off = offset; + if (mlen > cur) + break; + cur -= mlen; + } + + for (u = 0; u <= last_pos;) { + u += opt[u].mlen; + } + + for (cur = 0; cur < last_pos;) { + mlen = opt[cur].mlen; + if (mlen == 1) { + ip++; + cur++; + continue; + } + offset = opt[cur].off; + cur += mlen; + litLength = (U32)(ip - anchor); + + if (offset > ZSTD_REP_MOVE_OPT) { + rep[2] = rep[1]; + rep[1] = rep[0]; + rep[0] = offset - ZSTD_REP_MOVE_OPT; + offset--; + } else { + if (offset != 0) { + best_off = (offset == ZSTD_REP_MOVE_OPT) ? (rep[0] - 1) : (rep[offset]); + if (offset != 1) + rep[2] = rep[1]; + rep[1] = rep[0]; + rep[0] = best_off; + } + if (litLength == 0) + offset--; + } + + ZSTD_updatePrice(seqStorePtr, litLength, anchor, offset, mlen - MINMATCH); + ZSTD_storeSeq(seqStorePtr, litLength, anchor, offset, mlen - MINMATCH); + anchor = ip = ip + mlen; + } + } /* for (cur=0; cur < last_pos; ) */ + + /* Save reps for next block */ + { + int i; + for (i = 0; i < ZSTD_REP_NUM; i++) + ctx->repToConfirm[i] = rep[i]; + } + + /* Last Literals */ + { + size_t const lastLLSize = iend - anchor; + memcpy(seqStorePtr->lit, anchor, lastLLSize); + seqStorePtr->lit += lastLLSize; + } +} + +FORCE_INLINE +void ZSTD_compressBlock_opt_extDict_generic(ZSTD_CCtx *ctx, const void *src, size_t srcSize, const int ultra) +{ + seqStore_t *seqStorePtr = &(ctx->seqStore); + const BYTE *const istart = (const BYTE *)src; + const BYTE *ip = istart; + const BYTE *anchor = istart; + const BYTE *const iend = istart + srcSize; + const BYTE *const ilimit = iend - 8; + const BYTE *const base = ctx->base; + const U32 lowestIndex = ctx->lowLimit; + const U32 dictLimit = ctx->dictLimit; + const BYTE *const prefixStart = base + dictLimit; + const BYTE *const dictBase = ctx->dictBase; + const BYTE *const dictEnd = dictBase + dictLimit; + + const U32 maxSearches = 1U << ctx->params.cParams.searchLog; + const U32 sufficient_len = ctx->params.cParams.targetLength; + const U32 mls = ctx->params.cParams.searchLength; + const U32 minMatch = (ctx->params.cParams.searchLength == 3) ? 3 : 4; + + ZSTD_optimal_t *opt = seqStorePtr->priceTable; + ZSTD_match_t *matches = seqStorePtr->matchTable; + const BYTE *inr; + + /* init */ + U32 offset, rep[ZSTD_REP_NUM]; + { + U32 i; + for (i = 0; i < ZSTD_REP_NUM; i++) + rep[i] = ctx->rep[i]; + } + + ctx->nextToUpdate3 = ctx->nextToUpdate; + ZSTD_rescaleFreqs(seqStorePtr, (const BYTE *)src, srcSize); + ip += (ip == prefixStart); + + /* Match Loop */ + while (ip < ilimit) { + U32 cur, match_num, last_pos, litlen, price; + U32 u, mlen, best_mlen, best_off, litLength; + U32 curr = (U32)(ip - base); + memset(opt, 0, sizeof(ZSTD_optimal_t)); + last_pos = 0; + opt[0].litlen = (U32)(ip - anchor); + + /* check repCode */ + { + U32 i, last_i = ZSTD_REP_CHECK + (ip == anchor); + for (i = (ip == anchor); i < last_i; i++) { + const S32 repCur = (i == ZSTD_REP_MOVE_OPT) ? (rep[0] - 1) : rep[i]; + const U32 repIndex = (U32)(curr - repCur); + const BYTE *const repBase = repIndex < dictLimit ? dictBase : base; + const BYTE *const repMatch = repBase + repIndex; + if ((repCur > 0 && repCur <= (S32)curr) && + (((U32)((dictLimit - 1) - repIndex) >= 3) & (repIndex > lowestIndex)) /* intentional overflow */ + && (ZSTD_readMINMATCH(ip, minMatch) == ZSTD_readMINMATCH(repMatch, minMatch))) { + /* repcode detected we should take it */ + const BYTE *const repEnd = repIndex < dictLimit ? dictEnd : iend; + mlen = (U32)ZSTD_count_2segments(ip + minMatch, repMatch + minMatch, iend, repEnd, prefixStart) + minMatch; + + if (mlen > sufficient_len || mlen >= ZSTD_OPT_NUM) { + best_mlen = mlen; + best_off = i; + cur = 0; + last_pos = 1; + goto _storeSequence; + } + + best_off = i - (ip == anchor); + litlen = opt[0].litlen; + do { + price = ZSTD_getPrice(seqStorePtr, litlen, anchor, best_off, mlen - MINMATCH, ultra); + if (mlen > last_pos || price < opt[mlen].price) + SET_PRICE(mlen, mlen, i, litlen, price); /* note : macro modifies last_pos */ + mlen--; + } while (mlen >= minMatch); + } + } + } + + match_num = ZSTD_BtGetAllMatches_selectMLS_extDict(ctx, ip, iend, maxSearches, mls, matches, minMatch); /* first search (depth 0) */ + + if (!last_pos && !match_num) { + ip++; + continue; + } + + { + U32 i; + for (i = 0; i < ZSTD_REP_NUM; i++) + opt[0].rep[i] = rep[i]; + } + opt[0].mlen = 1; + + if (match_num && (matches[match_num - 1].len > sufficient_len || matches[match_num - 1].len >= ZSTD_OPT_NUM)) { + best_mlen = matches[match_num - 1].len; + best_off = matches[match_num - 1].off; + cur = 0; + last_pos = 1; + goto _storeSequence; + } + + best_mlen = (last_pos) ? last_pos : minMatch; + + /* set prices using matches at position = 0 */ + for (u = 0; u < match_num; u++) { + mlen = (u > 0) ? matches[u - 1].len + 1 : best_mlen; + best_mlen = matches[u].len; + litlen = opt[0].litlen; + while (mlen <= best_mlen) { + price = ZSTD_getPrice(seqStorePtr, litlen, anchor, matches[u].off - 1, mlen - MINMATCH, ultra); + if (mlen > last_pos || price < opt[mlen].price) + SET_PRICE(mlen, mlen, matches[u].off, litlen, price); + mlen++; + } + } + + if (last_pos < minMatch) { + ip++; + continue; + } + + /* check further positions */ + for (cur = 1; cur <= last_pos; cur++) { + inr = ip + cur; + + if (opt[cur - 1].mlen == 1) { + litlen = opt[cur - 1].litlen + 1; + if (cur > litlen) { + price = opt[cur - litlen].price + ZSTD_getLiteralPrice(seqStorePtr, litlen, inr - litlen); + } else + price = ZSTD_getLiteralPrice(seqStorePtr, litlen, anchor); + } else { + litlen = 1; + price = opt[cur - 1].price + ZSTD_getLiteralPrice(seqStorePtr, litlen, inr - 1); + } + + if (cur > last_pos || price <= opt[cur].price) + SET_PRICE(cur, 1, 0, litlen, price); + + if (cur == last_pos) + break; + + if (inr > ilimit) /* last match must start at a minimum distance of 8 from oend */ + continue; + + mlen = opt[cur].mlen; + if (opt[cur].off > ZSTD_REP_MOVE_OPT) { + opt[cur].rep[2] = opt[cur - mlen].rep[1]; + opt[cur].rep[1] = opt[cur - mlen].rep[0]; + opt[cur].rep[0] = opt[cur].off - ZSTD_REP_MOVE_OPT; + } else { + opt[cur].rep[2] = (opt[cur].off > 1) ? opt[cur - mlen].rep[1] : opt[cur - mlen].rep[2]; + opt[cur].rep[1] = (opt[cur].off > 0) ? opt[cur - mlen].rep[0] : opt[cur - mlen].rep[1]; + opt[cur].rep[0] = + ((opt[cur].off == ZSTD_REP_MOVE_OPT) && (mlen != 1)) ? (opt[cur - mlen].rep[0] - 1) : (opt[cur - mlen].rep[opt[cur].off]); + } + + best_mlen = minMatch; + { + U32 i, last_i = ZSTD_REP_CHECK + (mlen != 1); + for (i = (mlen != 1); i < last_i; i++) { + const S32 repCur = (i == ZSTD_REP_MOVE_OPT) ? (opt[cur].rep[0] - 1) : opt[cur].rep[i]; + const U32 repIndex = (U32)(curr + cur - repCur); + const BYTE *const repBase = repIndex < dictLimit ? dictBase : base; + const BYTE *const repMatch = repBase + repIndex; + if ((repCur > 0 && repCur <= (S32)(curr + cur)) && + (((U32)((dictLimit - 1) - repIndex) >= 3) & (repIndex > lowestIndex)) /* intentional overflow */ + && (ZSTD_readMINMATCH(inr, minMatch) == ZSTD_readMINMATCH(repMatch, minMatch))) { + /* repcode detected */ + const BYTE *const repEnd = repIndex < dictLimit ? dictEnd : iend; + mlen = (U32)ZSTD_count_2segments(inr + minMatch, repMatch + minMatch, iend, repEnd, prefixStart) + minMatch; + + if (mlen > sufficient_len || cur + mlen >= ZSTD_OPT_NUM) { + best_mlen = mlen; + best_off = i; + last_pos = cur + 1; + goto _storeSequence; + } + + best_off = i - (opt[cur].mlen != 1); + if (mlen > best_mlen) + best_mlen = mlen; + + do { + if (opt[cur].mlen == 1) { + litlen = opt[cur].litlen; + if (cur > litlen) { + price = opt[cur - litlen].price + ZSTD_getPrice(seqStorePtr, litlen, inr - litlen, + best_off, mlen - MINMATCH, ultra); + } else + price = ZSTD_getPrice(seqStorePtr, litlen, anchor, best_off, mlen - MINMATCH, ultra); + } else { + litlen = 0; + price = opt[cur].price + ZSTD_getPrice(seqStorePtr, 0, NULL, best_off, mlen - MINMATCH, ultra); + } + + if (cur + mlen > last_pos || price <= opt[cur + mlen].price) + SET_PRICE(cur + mlen, mlen, i, litlen, price); + mlen--; + } while (mlen >= minMatch); + } + } + } + + match_num = ZSTD_BtGetAllMatches_selectMLS_extDict(ctx, inr, iend, maxSearches, mls, matches, minMatch); + + if (match_num > 0 && (matches[match_num - 1].len > sufficient_len || cur + matches[match_num - 1].len >= ZSTD_OPT_NUM)) { + best_mlen = matches[match_num - 1].len; + best_off = matches[match_num - 1].off; + last_pos = cur + 1; + goto _storeSequence; + } + + /* set prices using matches at position = cur */ + for (u = 0; u < match_num; u++) { + mlen = (u > 0) ? matches[u - 1].len + 1 : best_mlen; + best_mlen = matches[u].len; + + while (mlen <= best_mlen) { + if (opt[cur].mlen == 1) { + litlen = opt[cur].litlen; + if (cur > litlen) + price = opt[cur - litlen].price + ZSTD_getPrice(seqStorePtr, litlen, ip + cur - litlen, + matches[u].off - 1, mlen - MINMATCH, ultra); + else + price = ZSTD_getPrice(seqStorePtr, litlen, anchor, matches[u].off - 1, mlen - MINMATCH, ultra); + } else { + litlen = 0; + price = opt[cur].price + ZSTD_getPrice(seqStorePtr, 0, NULL, matches[u].off - 1, mlen - MINMATCH, ultra); + } + + if (cur + mlen > last_pos || (price < opt[cur + mlen].price)) + SET_PRICE(cur + mlen, mlen, matches[u].off, litlen, price); + + mlen++; + } + } + } /* for (cur = 1; cur <= last_pos; cur++) */ + + best_mlen = opt[last_pos].mlen; + best_off = opt[last_pos].off; + cur = last_pos - best_mlen; + + /* store sequence */ +_storeSequence: /* cur, last_pos, best_mlen, best_off have to be set */ + opt[0].mlen = 1; + + while (1) { + mlen = opt[cur].mlen; + offset = opt[cur].off; + opt[cur].mlen = best_mlen; + opt[cur].off = best_off; + best_mlen = mlen; + best_off = offset; + if (mlen > cur) + break; + cur -= mlen; + } + + for (u = 0; u <= last_pos;) { + u += opt[u].mlen; + } + + for (cur = 0; cur < last_pos;) { + mlen = opt[cur].mlen; + if (mlen == 1) { + ip++; + cur++; + continue; + } + offset = opt[cur].off; + cur += mlen; + litLength = (U32)(ip - anchor); + + if (offset > ZSTD_REP_MOVE_OPT) { + rep[2] = rep[1]; + rep[1] = rep[0]; + rep[0] = offset - ZSTD_REP_MOVE_OPT; + offset--; + } else { + if (offset != 0) { + best_off = (offset == ZSTD_REP_MOVE_OPT) ? (rep[0] - 1) : (rep[offset]); + if (offset != 1) + rep[2] = rep[1]; + rep[1] = rep[0]; + rep[0] = best_off; + } + + if (litLength == 0) + offset--; + } + + ZSTD_updatePrice(seqStorePtr, litLength, anchor, offset, mlen - MINMATCH); + ZSTD_storeSeq(seqStorePtr, litLength, anchor, offset, mlen - MINMATCH); + anchor = ip = ip + mlen; + } + } /* for (cur=0; cur < last_pos; ) */ + + /* Save reps for next block */ + { + int i; + for (i = 0; i < ZSTD_REP_NUM; i++) + ctx->repToConfirm[i] = rep[i]; + } + + /* Last Literals */ + { + size_t lastLLSize = iend - anchor; + memcpy(seqStorePtr->lit, anchor, lastLLSize); + seqStorePtr->lit += lastLLSize; + } +} + +#endif /* ZSTD_OPT_H_91842398743 */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index c450e1157a5..bc86b848a21 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -118,7 +118,6 @@ CONFIG_BMP_32BPP CONFIG_BOARDDIR CONFIG_BOARDNAME CONFIG_BOARDNAME_LOCAL -CONFIG_BOARD_AXM CONFIG_BOARD_COMMON CONFIG_BOARD_ECC_SUPPORT CONFIG_BOARD_IS_OPENRD_BASE @@ -128,7 +127,6 @@ CONFIG_BOARD_NAME CONFIG_BOARD_POSTCLK_INIT CONFIG_BOARD_REVISION_TAG CONFIG_BOARD_SIZE_LIMIT -CONFIG_BOARD_TAURUS CONFIG_BOOGER CONFIG_BOOTBLOCK CONFIG_BOOTFILE @@ -1939,7 +1937,6 @@ CONFIG_ST_SMI CONFIG_SUNXI_GPIO CONFIG_SUNXI_MAX_FB_SIZE CONFIG_SUPERH_ON_CHIP_R8A66597 -CONFIG_SUPPORT_EMMC_BOOT CONFIG_SUVD3 CONFIG_SXNI855T CONFIG_SYSFLAGS_ADDR diff --git a/test/dm/cache.c b/test/dm/cache.c new file mode 100644 index 00000000000..d4144aab76f --- /dev/null +++ b/test/dm/cache.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#include <common.h> +#include <dm.h> +#include <dm/test.h> + +static int dm_test_reset(struct unit_test_state *uts) +{ + struct udevice *dev_cache; + struct cache_info; + + ut_assertok(uclass_get_device(UCLASS_CACHE, 0, &dev_cache)); + ut_assertok(cache_get_info(dev, &info)); + + return 0; +} +DM_TEST(dm_test_reset, DM_TESTF_SCAN_FDT); diff --git a/test/print_ut.c b/test/print_ut.c index f0f1d6010a1..0bc548dca83 100644 --- a/test/print_ut.c +++ b/test/print_ut.c @@ -79,14 +79,18 @@ static int do_ut_print(cmd_tbl_t *cmdtp, int flag, int argc, assert(s == str); assert(!strcmp("\n\nU-Boo\n\n", s)); - s = display_options_get_banner(true, str, 1); - assert(s == str); - assert(!strcmp("", s)); - - s = display_options_get_banner(true, str, 2); - assert(s == str); - assert(!strcmp("\n", s)); - + /* Assert that we do not overwrite memory before the buffer */ + str[0] = '`'; + s = display_options_get_banner(true, str + 1, 1); + assert(s == str + 1); + assert(!strcmp("`", str)); + + str[0] = '~'; + s = display_options_get_banner(true, str + 1, 2); + assert(s == str + 1); + assert(!strcmp("~\n", str)); + + /* The last two characters are set to \n\n for all buffer sizes > 2 */ s = display_options_get_banner(false, str, sizeof(str)); assert(s == str); assert(!strcmp("U-Boot \n\n", s)); diff --git a/tools/Makefile b/tools/Makefile index 12a3027e234..eadeba417dc 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -272,6 +272,7 @@ subdir- += env ifneq ($(CROSS_BUILD_TOOLS),) override HOSTCC = $(CC) +override HOSTCFLAGS = $(CFLAGS) quiet_cmd_crosstools_strip = STRIP $^ cmd_crosstools_strip = $(STRIP) $^; touch $@ diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 1ed0f7e9cb9..cfada0ee115 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -1742,7 +1742,7 @@ static int parse_config(struct env_opts *opts) if (ENVSIZE(0) != ENVSIZE(1)) { fprintf(stderr, - "Redundant environments have unequal size"); + "Redundant environments have unequal size\n"); return -1; } } diff --git a/tools/kwbimage.c b/tools/kwbimage.c index dffaf9043a0..b8f8d38212f 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -701,7 +701,7 @@ int kwb_verify(RSA *key, void *data, int datasz, struct sig_v1 *sig, goto err_ctx; } - if (!EVP_VerifyFinal(ctx, sig->sig, sizeof(sig->sig), evp_key)) { + if (EVP_VerifyFinal(ctx, sig->sig, sizeof(sig->sig), evp_key) != 1) { ret = openssl_err("Could not verify signature"); goto err_ctx; } |