diff options
152 files changed, 4251 insertions, 12225 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index e45b5a55663..dc8e048dde4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -412,9 +412,13 @@ F: drivers/mmc/mtk-sd.c F: drivers/phy/phy-mtk-* F: drivers/pinctrl/mediatek/ F: drivers/power/domain/mtk-power-domain.c +F: drivers/pci/pcie_mediatek_gen3.c +F: drivers/pci/pcie_mediatek.c +F: drivers/pwm/pwm-mtk.c F: drivers/ram/mediatek/ F: drivers/spi/mtk_snfi_spi.c F: drivers/spi/mtk_spim.c +F: drivers/spi/mtk_snor.c F: drivers/timer/mtk_timer.c F: drivers/usb/host/xhci-mtk.c F: drivers/usb/mtu3/ @@ -422,6 +426,7 @@ F: drivers/watchdog/mtk_wdt.c F: drivers/net/mtk_eth.c F: drivers/net/mtk_eth.h F: drivers/reset/reset-mediatek.c +F: drivers/serial/serial_mtk.c F: include/dt-bindings/clock/mediatek,* F: include/dt-bindings/power/mediatek,* F: tools/mtk_image.c diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7a3b3b45a43..b7df72453ac 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -530,56 +530,12 @@ dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \ stm32h743i-eval.dtb \ stm32h750i-art-pi.dtb -dtb-$(CONFIG_MACH_SUNIV) += \ - suniv-f1c100s-licheepi-nano.dtb dtb-$(CONFIG_MACH_SUN4I) += \ - sun4i-a10-a1000.dtb \ - sun4i-a10-ba10-tvbox.dtb \ - sun4i-a10-chuwi-v7-cw0825.dtb \ - sun4i-a10-cubieboard.dtb \ - sun4i-a10-dserve-dsrv9703c.dtb \ - sun4i-a10-gemei-g9.dtb \ - sun4i-a10-hackberry.dtb \ - sun4i-a10-hyundai-a7hd.dtb \ - sun4i-a10-inet1.dtb \ sun4i-a10-inet-3f.dtb \ - sun4i-a10-inet-3w.dtb \ - sun4i-a10-inet97fv2.dtb \ - sun4i-a10-inet9f-rev03.dtb \ - sun4i-a10-itead-iteaduino-plus.dtb \ - sun4i-a10-jesurun-q5.dtb \ - sun4i-a10-marsboard.dtb \ - sun4i-a10-mini-xplus.dtb \ - sun4i-a10-mk802.dtb \ - sun4i-a10-mk802ii.dtb \ - sun4i-a10-olinuxino-lime.dtb \ - sun4i-a10-pcduino.dtb \ - sun4i-a10-pcduino2.dtb \ - sun4i-a10-pov-protab2-ips9.dtb \ - sun4i-a10-topwise-a721.dtb + sun4i-a10-inet-3w.dtb dtb-$(CONFIG_MACH_SUN5I) += \ - sun5i-a10s-auxtek-t003.dtb \ - sun5i-a10s-auxtek-t004.dtb \ - sun5i-a10s-mk802.dtb \ - sun5i-a10s-olinuxino-micro.dtb \ - sun5i-a10s-r7-tv-dongle.dtb \ - sun5i-a10s-wobo-i5.dtb \ sun5i-a13-ampe-a76.dtb \ - sun5i-a13-difrnce-dit4350.dtb \ - sun5i-a13-empire-electronix-d709.dtb \ - sun5i-a13-empire-electronix-m712.dtb \ - sun5i-a13-hsg-h702.dtb \ - sun5i-a13-inet-86vs.dtb \ - sun5i-a13-inet-98v-rev2.dtb \ - sun5i-a13-licheepi-one.dtb \ - sun5i-a13-olinuxino.dtb \ - sun5i-a13-olinuxino-micro.dtb \ - sun5i-a13-pocketbook-touch-lux-3.dtb \ - sun5i-a13-q8-tablet.dtb \ - sun5i-a13-utoo-p66.dtb \ - sun5i-gr8-chip-pro.dtb \ - sun5i-gr8-evb.dtb \ - sun5i-r8-chip.dtb + sun5i-a13-inet-86vs.dtb dtb-$(CONFIG_MACH_SUN6I) += \ sun6i-a31-app4-evb1.dtb \ sun6i-a31-colombus.dtb \ diff --git a/arch/arm/dts/mt7981-emmc-rfb.dts b/arch/arm/dts/mt7981-emmc-rfb.dts index 9aa7cd8f6e5..d6590f01cf8 100644 --- a/arch/arm/dts/mt7981-emmc-rfb.dts +++ b/arch/arm/dts/mt7981-emmc-rfb.dts @@ -95,6 +95,14 @@ }; }; + /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */ + three_pwm_pins_1: three-pwm-pins { + mux { + function = "pwm"; + groups = "pwm0_0", "pwm1_1", "pwm2"; + }; + }; + mmc0_pins_default: mmc0default { mux { function = "flash"; diff --git a/arch/arm/dts/mt7981-rfb.dts b/arch/arm/dts/mt7981-rfb.dts index 22a022acb62..d6ebd6539c3 100644 --- a/arch/arm/dts/mt7981-rfb.dts +++ b/arch/arm/dts/mt7981-rfb.dts @@ -123,6 +123,14 @@ groups = "pwm0_1", "pwm1_0", "pwm2"; }; }; + + /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */ + three_pwm_pins_1: three-pwm-pins { + mux { + function = "pwm"; + groups = "pwm0_0", "pwm1_1", "pwm2"; + }; + }; }; &spi0 { @@ -143,6 +151,8 @@ compatible = "spi-nand"; reg = <0>; spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; }; }; @@ -164,6 +174,8 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; }; }; diff --git a/arch/arm/dts/mt7981-sd-rfb.dts b/arch/arm/dts/mt7981-sd-rfb.dts index 7d708084042..2adbc374725 100644 --- a/arch/arm/dts/mt7981-sd-rfb.dts +++ b/arch/arm/dts/mt7981-sd-rfb.dts @@ -95,6 +95,14 @@ }; }; + /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */ + three_pwm_pins_1: three-pwm-pins { + mux { + function = "pwm"; + groups = "pwm0_0", "pwm1_1", "pwm2"; + }; + }; + mmc0_pins_default: mmc0default { mux { function = "flash"; @@ -110,7 +118,7 @@ }; conf-clk { pins = "SPI1_CS"; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <MTK_DRIVE_8mA>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; conf-rst { @@ -132,10 +140,12 @@ }; &mmc0 { + assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D4>, + <&topckgen CLK_TOP_CB_NET2_D2>; pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_default>; bus-width = <4>; - max-frequency = <52000000>; + max-frequency = <50000000>; cap-sd-highspeed; r_smpl = <0>; vmmc-supply = <®_3p3v>; diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi index a9991a121f1..2844ab010de 100644 --- a/arch/arm/dts/mt7981.dtsi +++ b/arch/arm/dts/mt7981.dtsi @@ -137,8 +137,14 @@ <&infracfg CLK_INFRA_PWM1_CK>, <&infracfg CLK_INFRA_PWM2_CK>, <&infracfg CLK_INFRA_PWM3_CK>; - assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>; + assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&infracfg CLK_INFRA_PWM1_SEL>, + <&infracfg CLK_INFRA_PWM2_SEL>, + <&infracfg CLK_INFRA_PWM3_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_PWM_SEL>, + <&topckgen CLK_TOP_PWM_SEL>, + <&topckgen CLK_TOP_PWM_SEL>; clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; status = "disabled"; }; @@ -300,13 +306,13 @@ reg = <0x11230000 0x1000>, <0x11C20000 0x1000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&topckgen CLK_TOP_EMMC_400M>, - <&topckgen CLK_TOP_EMMC_208M>, + clocks = <&topckgen CLK_TOP_EMMC_208M>, + <&topckgen CLK_TOP_EMMC_400M>, <&infracfg CLK_INFRA_MSDC_CK>; - assigned-clocks = <&topckgen CLK_TOP_EMMC_400M_SEL>, - <&topckgen CLK_TOP_EMMC_208M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D2>, - <&topckgen CLK_TOP_CB_M_D2>; + assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>, + <&topckgen CLK_TOP_EMMC_400M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_CB_NET2_D2>; clock-names = "source", "hclk", "source_cg"; status = "disabled"; }; diff --git a/arch/arm/dts/mt7986a-rfb.dts b/arch/arm/dts/mt7986a-rfb.dts index e5c9be7da82..67d14a99dae 100644 --- a/arch/arm/dts/mt7986a-rfb.dts +++ b/arch/arm/dts/mt7986a-rfb.dts @@ -190,12 +190,16 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; }; spi_nand@1 { compatible = "spi-nand"; reg = <1>; spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; }; }; diff --git a/arch/arm/dts/mt7986b-rfb.dts b/arch/arm/dts/mt7986b-rfb.dts index 8196845a123..f98b04ab140 100644 --- a/arch/arm/dts/mt7986b-rfb.dts +++ b/arch/arm/dts/mt7986b-rfb.dts @@ -177,12 +177,16 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; }; spi_nand@1 { compatible = "spi-nand"; reg = <1>; spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; }; }; diff --git a/arch/arm/dts/mt7988-rfb.dts b/arch/arm/dts/mt7988-rfb.dts index 2c114284309..2579d7099fb 100644 --- a/arch/arm/dts/mt7988-rfb.dts +++ b/arch/arm/dts/mt7988-rfb.dts @@ -50,19 +50,36 @@ status = "okay"; }; -ð { +ð0 { status = "okay"; - mediatek,gmac-id = <0>; phy-mode = "usxgmii"; mediatek,switch = "mt7988"; fixed-link { - speed = <1000>; + speed = <10000>; full-duplex; pause; }; }; +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +/* PCIE2 not working in u-boot */ +&pcie2 { + status = "disabled"; +}; + +/* PCIE3 not working in u-boot */ +&pcie3 { + status = "disabled"; +}; + &pinctrl { i2c1_pins: i2c1-pins { mux { @@ -84,6 +101,19 @@ function = "spi"; groups = "spi0", "spi0_wp_hold"; }; + + conf-pu { + pins = "SPI0_CSB", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_11>; + }; + }; spi2_pins: spi2-pins { @@ -91,6 +121,18 @@ function = "spi"; groups = "spi2", "spi2_wp_hold"; }; + + conf-pu { + pins = "SPI2_CSB", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_11>; + }; }; mmc0_pins_default: mmc0default { @@ -104,18 +146,25 @@ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; input-enable; + drive-strength = <MTK_DRIVE_4mA>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ }; conf-clk { pins = "EMMC_CK"; + drive-strength = <MTK_DRIVE_6mA>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ }; conf-dsl { pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ }; conf-rst { pins = "EMMC_RSTB"; + drive-strength = <MTK_DRIVE_4mA>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ }; }; }; @@ -144,6 +193,8 @@ compatible = "spi-nand"; reg = <0>; spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; }; }; @@ -165,6 +216,8 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; }; }; diff --git a/arch/arm/dts/mt7988-sd-rfb.dts b/arch/arm/dts/mt7988-sd-rfb.dts index 9aa198b84ab..38727a271b2 100644 --- a/arch/arm/dts/mt7988-sd-rfb.dts +++ b/arch/arm/dts/mt7988-sd-rfb.dts @@ -41,14 +41,13 @@ status = "okay"; }; -ð { +ð0 { status = "okay"; - mediatek,gmac-id = <0>; phy-mode = "usxgmii"; mediatek,switch = "mt7988"; fixed-link { - speed = <1000>; + speed = <10000>; full-duplex; pause; }; diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi index e120e5084ce..f2bfde547e6 100644 --- a/arch/arm/dts/mt7988.dtsi +++ b/arch/arm/dts/mt7988.dtsi @@ -188,6 +188,152 @@ status = "okay"; }; + pcie2: pcie@11280000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11280000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <3>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20200000 0 0x20200000 0 0x07e00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + phys = <&xphyu3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc2 0>, + <0 0 0 2 &pcie_intc2 1>, + <0 0 0 3 &pcie_intc2 2>, + <0 0 0 4 &pcie_intc2 3>; + + pcie_intc2: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie3: pcie@11290000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11290000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <2>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x28200000 0 0x28200000 0 0x07e00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + use-dedicated-phy; + + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc3 0>, + <0 0 0 2 &pcie_intc3 1>, + <0 0 0 3 &pcie_intc3 2>, + <0 0 0 4 &pcie_intc3 3>; + pcie_intc3: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie0: pcie@11300000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11300000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <0>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x30200000 0 0x30200000 0 0x07e00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + use-dedicated-phy; + + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie1: pcie@11310000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11310000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <1>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x38200000 0 0x38200000 0 0x07e00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + use-dedicated-phy; + + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + usbtphy: usb-phy@11c50000 { compatible = "mediatek,mt7988", "mediatek,generic-tphy-v2"; @@ -215,6 +361,22 @@ }; }; + xphy: xphy@11e10000 { + compatible = "mediatek,mt7988", "mediatek,xsphy"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + xphyu3port0: usb-phy@11e13000 { + reg = <0 0x11e13400 0 0x500>; + clocks = <&dummy_clk>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + xfi_pextp0: syscon@11f20000 { compatible = "mediatek,mt7988-xfi_pextp_0", "syscon"; reg = <0 0x11f20000 0 0x10000>; @@ -425,11 +587,11 @@ #reset-cells = <1>; }; - eth: ethernet@15100000 { + eth0: ethernet@15110100 { compatible = "mediatek,mt7988-eth", "syscon"; reg = <0 0x15100000 0 0x20000>; + mediatek,gmac-id = <0>; mediatek,ethsys = <ðdma>; - mediatek,sgmiisys = <&sgmiisys0>; mediatek,usxgmiisys = <&usxgmiisys0>; mediatek,xfi_pextp = <&xfi_pextp0>; mediatek,xfi_pll = <&xfi_pll>; @@ -442,4 +604,42 @@ mediatek,mcm; status = "disabled"; }; + + eth1: ethernet@15110200 { + compatible = "mediatek,mt7988-eth", "syscon"; + reg = <0 0x15100000 0 0x20000>; + mediatek,gmac-id = <1>; + mediatek,ethsys = <ðdma>; + mediatek,sgmiisys = <&sgmiisys1>; + mediatek,usxgmiisys = <&usxgmiisys1>; + mediatek,xfi_pextp = <&xfi_pextp1>; + mediatek,xfi_pll = <&xfi_pll>; + mediatek,infracfg = <&topmisc>; + mediatek,toprgu = <&watchdog>; + resets = <ðdma ETHDMA_FE_RST>; + reset-names = "fe"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,mcm; + status = "disabled"; + }; + + eth2: ethernet@15110300 { + compatible = "mediatek,mt7988-eth", "syscon"; + reg = <0 0x15100000 0 0x20000>; + mediatek,gmac-id = <2>; + mediatek,ethsys = <ðdma>; + mediatek,sgmiisys = <&sgmiisys0>; + mediatek,usxgmiisys = <&usxgmiisys0>; + mediatek,xfi_pextp = <&xfi_pextp0>; + mediatek,xfi_pll = <&xfi_pll>; + mediatek,infracfg = <&topmisc>; + mediatek,toprgu = <&watchdog>; + resets = <ðdma ETHDMA_FE_RST>; + reset-names = "fe"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,mcm; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/nuvoton-npcm845-evb.dts b/arch/arm/dts/nuvoton-npcm845-evb.dts index 0d3aaa0fffe..1535defe38f 100644 --- a/arch/arm/dts/nuvoton-npcm845-evb.dts +++ b/arch/arm/dts/nuvoton-npcm845-evb.dts @@ -190,6 +190,7 @@ snps,mdio-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* gpio92 */ snps,reset-active-low; snps,reset-delays-us = <0 10000 1000000>; + snps,bitbang-delay = <1>; snps,reset-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; /* gpio93 */ status = "okay"; }; diff --git a/arch/arm/dts/sun4i-a10-a1000.dts b/arch/arm/dts/sun4i-a10-a1000.dts deleted file mode 100644 index 20f9ed24485..00000000000 --- a/arch/arm/dts/sun4i-a10-a1000.dts +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright 2013 Emilio López - * - * Emilio López <emilio@elopez.com.ar> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Mele A1000"; - compatible = "mele,a1000", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "a1000:red:usr"; - gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - label = "a1000:blue:pwr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <20000>; - enable-active-high; - gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/dts/sun4i-a10-ba10-tvbox.dts deleted file mode 100644 index 816d534ac09..00000000000 --- a/arch/arm/dts/sun4i-a10-ba10-tvbox.dts +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright 2014 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "BA10 tvbox"; - compatible = "allwinner,ba10-tvbox", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - regulator-boot-on; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts deleted file mode 100644 index 74262988881..00000000000 --- a/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "Chuwi V7 CW0825"; - compatible = "chuwi,v7-cw0825", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - ft5306de4: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <1024>; - touchscreen-size-y = <768>; - }; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-800 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <800000>; - }; - - button-1000 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <1000000>; - }; - - button-1200 { - label = "Back"; - linux,code = <KEY_BACK>; - channel = <0>; - voltage = <1200000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-cubieboard.dts b/arch/arm/dts/sun4i-a10-cubieboard.dts deleted file mode 100644 index 0645d606423..00000000000 --- a/arch/arm/dts/sun4i-a10-cubieboard.dts +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright 2012 Stefan Roese - * Stefan Roese <sr@denx.de> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Cubietech Cubieboard"; - compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_cubieboard>; - - led-0 { - label = "cubieboard:blue:usr"; - gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* LED1 */ - }; - - led-1 { - label = "cubieboard:green:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* LED2 */ - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_cubieboard: led-pins { - pins = "PH20", "PH21"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_ahci_5v { - status = "okay"; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pi_pins>, - <&spi0_cs0_pi_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts deleted file mode 100644 index 63e77c05bfd..00000000000 --- a/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Copyright 2016 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pwm/pwm.h> - -/ { - model = "Dserve DSRV9703C"; - compatible = "dserve,dsrv9703c", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - power-supply = <®_vcc3v3>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - haptics { - compatible = "regulator-haptic"; - haptic-supply = <®_motor>; - min-microvolt = <3000000>; - max-microvolt = <3000000>; - }; - - reg_motor: reg-motor { - compatible = "regulator-fixed"; - regulator-name = "vcc-motor"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - enable-active-high; - gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - }; -}; - -&codec { - allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - /* pull-ups and devices require AXP209 LDO3 */ - status = "failed"; -}; - -&i2c2 { - status = "okay"; - - ft5406ee8: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <1024>; - touchscreen-size-y = <768>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-400 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <400000>; - }; - - button-800 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <800000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-gemei-g9.dts b/arch/arm/dts/sun4i-a10-gemei-g9.dts deleted file mode 100644 index ea7a59dcf8f..00000000000 --- a/arch/arm/dts/sun4i-a10-gemei-g9.dts +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright 2015 Priit Laes - * - * Priit Laes <plaes@plaes.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "Gemei G9 Tablet"; - compatible = "gemei,g9", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -/* - * TODO: - * 2x cameras via CSI - * AXP battery management - * NAND - * OTG - * Touchscreen - gt801_2plus1 @ i2c adapter 2 @ 0x48 - */ -&codec { - /* PH15 controls power to external amplifier (ft2012q) */ - allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - /* Accelerometer */ - bma250@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&pio>; - interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH00 / EINT0 */ - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - - status = "okay"; - - button-158 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <158730>; - }; - - button-349 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <349206>; - }; - - button-1142 { - label = "Esc"; - linux,code = <KEY_ESC>; - channel = <0>; - voltage = <1142856>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */ - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-hackberry.dts b/arch/arm/dts/sun4i-a10-hackberry.dts deleted file mode 100644 index 47dea092250..00000000000 --- a/arch/arm/dts/sun4i-a10-hackberry.dts +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Miniand Hackberry"; - compatible = "miniand,hackberry", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <20000>; - enable-active-high; - gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy0>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts deleted file mode 100644 index bf2044bac42..00000000000 --- a/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Hyundai A7HD"; - compatible = "hyundai,a7hd", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-inet1.dts b/arch/arm/dts/sun4i-a10-inet1.dts deleted file mode 100644 index 60e432a0ef1..00000000000 --- a/arch/arm/dts/sun4i-a10-inet1.dts +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pwm/pwm.h> - -/ { - model = "iNet-1"; - compatible = "inet-tek,inet1", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - power-supply = <®_vcc3v3>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - /* Accelerometer */ - bma250@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&pio>; - interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */ - }; -}; - -&i2c2 { - status = "okay"; - - ft5x: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - wake-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* PB13 */ - touchscreen-size-x = <600>; - touchscreen-size-y = <1024>; - touchscreen-swapped-x-y; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <200000>; - }; - - button-1000 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <1000000>; - }; - - button-1200 { - label = "Home"; - linux,code = <KEY_HOMEPAGE>; - channel = <0>; - voltage = <1200000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-inet97fv2.dts b/arch/arm/dts/sun4i-a10-inet97fv2.dts deleted file mode 100644 index 76016f2ca29..00000000000 --- a/arch/arm/dts/sun4i-a10-inet97fv2.dts +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright 2014 Open Source Support GmbH - * - * David Lanzendörfer <david.lanzendoerfer@o2s.ch> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "INet-97F Rev 02"; - compatible = "primux,inet97fv2", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - ft5406ee8: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Menu"; - linux,code = <KEY_MENU>; - channel = <0>; - voltage = <200000>; - }; - - button-600 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <600000>; - }; - - button-800 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <800000>; - }; - - button-1000 { - label = "Home"; - linux,code = <KEY_HOMEPAGE>; - channel = <0>; - voltage = <1000000>; - }; - - button-1200 { - label = "Esc"; - linux,code = <KEY_ESC>; - channel = <0>; - voltage = <1200000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts deleted file mode 100644 index 62e7aa587f8..00000000000 --- a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts +++ /dev/null @@ -1,357 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "iNet-9F Rev 03"; - compatible = "inet-tek,inet9f-rev03", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys-polled"; - poll-interval = <20>; - - event-left-joystick-left { - label = "Left Joystick Left"; - linux,code = <ABS_X>; - linux,input-type = <EV_ABS>; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */ - }; - - event-left-joystick-right { - label = "Left Joystick Right"; - linux,code = <ABS_X>; - linux,input-type = <EV_ABS>; - linux,input-value = <1>; - gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */ - }; - - event-left-joystick-up { - label = "Left Joystick Up"; - linux,code = <ABS_Y>; - linux,input-type = <EV_ABS>; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */ - }; - - event-left-joystick-down { - label = "Left Joystick Down"; - linux,code = <ABS_Y>; - linux,input-type = <EV_ABS>; - linux,input-value = <1>; - gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */ - }; - - event-right-joystick-left { - label = "Right Joystick Left"; - linux,code = <ABS_Z>; - linux,input-type = <EV_ABS>; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */ - }; - - event-right-joystick-right { - label = "Right Joystick Right"; - linux,code = <ABS_Z>; - linux,input-type = <EV_ABS>; - linux,input-value = <1>; - gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */ - }; - - event-right-joystick-up { - label = "Right Joystick Up"; - linux,code = <ABS_RZ>; - linux,input-type = <EV_ABS>; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */ - }; - - event-right-joystick-down { - label = "Right Joystick Down"; - linux,code = <ABS_RZ>; - linux,input-type = <EV_ABS>; - linux,input-value = <1>; - gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */ - }; - - event-dpad-left { - label = "DPad Left"; - linux,code = <ABS_HAT0X>; - linux,input-type = <EV_ABS>; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */ - }; - - event-dpad-right { - label = "DPad Right"; - linux,code = <ABS_HAT0X>; - linux,input-type = <EV_ABS>; - linux,input-value = <1>; - gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */ - }; - - event-dpad-up { - label = "DPad Up"; - linux,code = <ABS_HAT0Y>; - linux,input-type = <EV_ABS>; - linux,input-value = <0xffffffff>; /* -1 */ - gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */ - }; - - event-dpad-down { - label = "DPad Down"; - linux,code = <ABS_HAT0Y>; - linux,input-type = <EV_ABS>; - linux,input-value = <1>; - gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */ - }; - - event-x { - label = "Button X"; - linux,code = <BTN_X>; - gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */ - }; - - event-y { - label = "Button Y"; - linux,code = <BTN_Y>; - gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */ - }; - - event-a { - label = "Button A"; - linux,code = <BTN_A>; - gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */ - }; - - event-b { - label = "Button B"; - linux,code = <BTN_B>; - gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */ - }; - - event-select { - label = "Select Button"; - linux,code = <BTN_SELECT>; - gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */ - }; - - event-start { - label = "Start Button"; - linux,code = <BTN_START>; - gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */ - }; - - event-top-left { - label = "Top Left Button"; - linux,code = <BTN_TL>; - gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */ - }; - - event-top-right { - label = "Top Right Button"; - linux,code = <BTN_TR>; - gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */ - }; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - /* Accelerometer */ - bma250@18 { - compatible = "bosch,bma250"; - reg = <0x18>; - interrupt-parent = <&pio>; - interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */ - }; -}; - -&i2c2 { - status = "okay"; - - ft5406ee8: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Menu"; - linux,code = <KEY_MENU>; - channel = <0>; - voltage = <200000>; - }; - - button-600 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <600000>; - }; - - button-800 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <800000>; - }; - - button-1000 { - label = "Home"; - linux,code = <KEY_HOMEPAGE>; - channel = <0>; - voltage = <1000000>; - }; - - button-1200 { - label = "Esc"; - linux,code = <KEY_ESC>; - channel = <0>; - voltage = <1200000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts deleted file mode 100644 index d4e319d16aa..00000000000 --- a/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright 2015 Josef Gajdusek <atx@atx.name> - * Copyright 2015 - Marcus Cooper <codekipper@gmail.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-itead-core-common.dtsi" - -/ { - model = "Iteaduino Plus A10"; - compatible = "itead,iteaduino-plus-a10", "allwinner,sun4i-a10"; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins>; - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - axp209: pmic@34 { - interrupts = <0>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -®_ahci_5v { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pi_pins>, - <&spi0_cs0_pi_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_pb_pins>; -}; diff --git a/arch/arm/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/dts/sun4i-a10-jesurun-q5.dts deleted file mode 100644 index 1aeb0bd5519..00000000000 --- a/arch/arm/dts/sun4i-a10-jesurun-q5.dts +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright 2015 Gábor Nyers - * - * Gábor Nyers <gabor.nyers@gmail.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Jesurun Q5"; - compatible = "jesurun,q5", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "q5:green:usr"; - gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */ - }; - - }; - - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <20000>; - enable-active-high; - gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ - }; -}; - -&ahci { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&mdio { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - regulator-boot-on; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-marsboard.dts b/arch/arm/dts/sun4i-a10-marsboard.dts deleted file mode 100644 index 81fdb217d33..00000000000 --- a/arch/arm/dts/sun4i-a10-marsboard.dts +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright 2015 Aleksei Mamlin - * Aleksei Mamlin <mamlinav@gmail.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "HAOYU Electronics Marsboard A10"; - compatible = "haoyu,a10-marsboard", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "marsboard:red1:usr"; - gpios = <&pio 1 5 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - label = "marsboard:red2:usr"; - gpios = <&pio 1 6 GPIO_ACTIVE_HIGH>; - }; - - led-2 { - label = "marsboard:red3:usr"; - gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; - }; - - led-3 { - label = "marsboard:red4:usr"; - gpios = <&pio 1 8 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&ahci { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pi_pins>, - <&spi0_cs0_pi_pin>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-mini-xplus.dts b/arch/arm/dts/sun4i-a10-mini-xplus.dts deleted file mode 100644 index f9d74e21031..00000000000 --- a/arch/arm/dts/sun4i-a10-mini-xplus.dts +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "PineRiver Mini X-Plus"; - compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins>; - status = "okay"; -}; - -&ir0_rx_pins { - /* The ir receiver is not always populated */ - bias-pull-up; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - regulator-boot-on; - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-mk802.dts b/arch/arm/dts/sun4i-a10-mk802.dts deleted file mode 100644 index 059fe9c5d02..00000000000 --- a/arch/arm/dts/sun4i-a10-mk802.dts +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "MK802"; - compatible = "allwinner,mk802", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; -}; - -&codec { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-mk802ii.dts b/arch/arm/dts/sun4i-a10-mk802ii.dts deleted file mode 100644 index 17dcdf03111..00000000000 --- a/arch/arm/dts/sun4i-a10-mk802ii.dts +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "MK802ii"; - compatible = "allwinner,mk802ii", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/dts/sun4i-a10-olinuxino-lime.dts deleted file mode 100644 index 83d283cf663..00000000000 --- a/arch/arm/dts/sun4i-a10-olinuxino-lime.dts +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Copyright 2014 - Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Olimex A10-OLinuXino-LIME"; - compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinolime>; - - led { - label = "a10-olinuxino-lime:green:usr"; - gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ahci { - target-supply = <®_ahci_5v>; - status = "okay"; -}; - -&cpu0 { - /* - * The A10-Lime is known to be unstable when running at 1008 MHz - */ - operating-points = - /* kHz uV */ - <912000 1350000>, - <864000 1300000>, - <624000 1250000>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_olinuxinolime: led-pin { - pins = "PH2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_ahci_5v { - gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-pcduino.dts b/arch/arm/dts/sun4i-a10-pcduino.dts deleted file mode 100644 index a332d61fd56..00000000000 --- a/arch/arm/dts/sun4i-a10-pcduino.dts +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Copyright 2014 Zoltan HERPAI - * Zoltan HERPAI <wigyori@uid0.hu> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "LinkSprite pcDuino"; - compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "pcduino:green:tx"; - gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; - }; - - led-1 { - label = "pcduino:green:rx"; - gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-back { - label = "Key Back"; - linux,code = <KEY_BACK>; - gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; - }; - - key-home { - label = "Key Home"; - linux,code = <KEY_HOME>; - gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; - }; - - key-menu { - label = "Key Menu"; - linux,code = <KEY_MENU>; - gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ - usb2_vbus-supply = <®_vcc5v0>; /* USB2 VBUS is always on */ - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-pcduino2.dts b/arch/arm/dts/sun4i-a10-pcduino2.dts deleted file mode 100644 index bc4f128965e..00000000000 --- a/arch/arm/dts/sun4i-a10-pcduino2.dts +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2015 Siarhei Siamashka <siarhei.siamashka@gmail.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * The LinkSprite pcDuino2 board is almost identical to the older - * LinkSprite pcDuino1 board. The only software visible difference - * is that the pcDuino2 board got a USB VBUS voltage regulator, which - * is controlled by the PD2 pin (pulled-up by default). Also one of - * the USB host ports has been replaced with a USB WIFI chip. - */ - -#include "sun4i-a10-pcduino.dts" - -/ { - model = "LinkSprite pcDuino2"; - compatible = "linksprite,a10-pcduino2", "allwinner,sun4i-a10"; -}; - -®_usb2_vbus { - gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc3v3>; /* USB WIFI is always on */ - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts deleted file mode 100644 index c3259694764..00000000000 --- a/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pwm/pwm.h> - -/ { - model = "Point of View Protab2-IPS9"; - compatible = "pov,protab2-ips9", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - power-supply = <®_vcc3v3>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - /* pull-ups and devices require AXP209 LDO3 */ - status = "failed"; -}; - -&i2c2 { - status = "okay"; - - touchscreen@5c { - compatible = "pixcir,pixcir_tangoc"; - reg = <0x5c>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */ - attb-gpio = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* PH21 */ - enable-gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; - wake-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <1024>; - touchscreen-size-y = <768>; - touchscreen-inverted-x; - touchscreen-inverted-y; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-400 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <400000>; - }; - - button-800 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <800000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10-topwise-a721.dts b/arch/arm/dts/sun4i-a10-topwise-a721.dts deleted file mode 100644 index 3628f12d252..00000000000 --- a/arch/arm/dts/sun4i-a10-topwise-a721.dts +++ /dev/null @@ -1,242 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2020 Pascal Roeleven <dev@pascalroeleven.nl> - */ - -/dts-v1/; -#include "sun4i-a10.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pwm/pwm.h> - -/ { - model = "Topwise A721"; - compatible = "topwise,a721", "allwinner,sun4i-a10"; - - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 100000 PWM_POLARITY_INVERTED>; - power-supply = <®_vbat>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - brightness-levels = <0 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - panel { - compatible = "starry,kr070pe2t"; - backlight = <&backlight>; - power-supply = <®_lcd_power>; - - port { - panel_input: endpoint { - remote-endpoint = <&tcon0_out_panel>; - }; - }; - }; - - reg_lcd_power: reg-lcd-power { - compatible = "regulator-fixed"; - regulator-name = "reg-lcd-power"; - gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ - enable-active-high; - }; - - reg_vbat: reg-vbat { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - accelerometer@4c { - compatible = "fsl,mma7660"; - reg = <0x4c>; - }; -}; - -&i2c2 { - status = "okay"; - - touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&pio>; - interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - vcc-supply = <®_vcc3v3>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-571 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <571428>; - }; - - button-761 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <761904>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - vcc-pb-supply = <®_vcc3v3>; - vcc-pf-supply = <®_vcc3v3>; - vcc-ph-supply = <®_vcc3v3>; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - status = "okay"; -}; - -®_usb1_vbus { - status = "okay"; -}; - -®_usb2_vbus { - status = "okay"; -}; - -&tcon0_out { - tcon0_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun4i-a10.dtsi b/arch/arm/dts/sun4i-a10.dtsi deleted file mode 100644 index 51a6464aab9..00000000000 --- a/arch/arm/dts/sun4i-a10.dtsi +++ /dev/null @@ -1,1271 +0,0 @@ -/* - * Copyright 2012 Stefan Roese - * Stefan Roese <sr@denx.de> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include <dt-bindings/thermal/thermal.h> -#include <dt-bindings/dma/sun4i-a10.h> -#include <dt-bindings/clock/sun4i-a10-ccu.h> -#include <dt-bindings/reset/sun4i-a10-ccu.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - aliases { - ethernet0 = &emac; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer-lcd0-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, - <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, - <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>; - status = "disabled"; - }; - - framebuffer-fe0-lcd0-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; - clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>, - <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, - <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, - <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>, - <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; - status = "disabled"; - }; - - framebuffer-fe0-lcd0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_fe0-de_be0-lcd0"; - clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>, - <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>, - <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>, - <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; - status = "disabled"; - }; - - framebuffer-fe0-lcd0-tve0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; - clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>, - <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>, - <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>, - <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>, - <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - clocks = <&ccu CLK_CPU>; - clock-latency = <244144>; /* 8 32k periods */ - operating-points = - /* kHz uV */ - <1008000 1400000>, - <912000 1350000>, - <864000 1300000>, - <624000 1250000>; - #cooling-cells = <2>; - }; - }; - - thermal-zones { - cpu-thermal { - /* milliseconds */ - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&rtp>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu-alert0 { - /* milliCelsius */ - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - /* milliCelsius */ - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: clk-24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: clk-32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - }; - - de: display-engine { - compatible = "allwinner,sun4i-a10-display-engine"; - allwinner,pipelines = <&fe0>, <&fe1>; - status = "disabled"; - }; - - pmu { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - default-pool { - compatible = "shared-dma-pool"; - size = <0x6000000>; - alloc-ranges = <0x40000000 0x10000000>; - reusable; - linux,cma-default; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - system-control@1c00000 { - compatible = "allwinner,sun4i-a10-system-control"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_a: sram@0 { - compatible = "mmio-sram"; - reg = <0x00000000 0xc000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00000000 0xc000>; - - emac_sram: sram-section@8000 { - compatible = "allwinner,sun4i-a10-sram-a3-a4"; - reg = <0x8000 0x4000>; - status = "disabled"; - }; - }; - - sram_d: sram@10000 { - compatible = "mmio-sram"; - reg = <0x00010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00010000 0x1000>; - - otg_sram: sram-section@0 { - compatible = "allwinner,sun4i-a10-sram-d"; - reg = <0x0000 0x1000>; - status = "disabled"; - }; - }; - - sram_c: sram@1d00000 { - compatible = "mmio-sram"; - reg = <0x01d00000 0xd0000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01d00000 0xd0000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x80000>; - }; - }; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <27>; - clocks = <&ccu CLK_AHB_DMA>; - #dma-cells = <2>; - }; - - nfc: nand-controller@1c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = <37>; - clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 3>; - dma-names = "rxtx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@1c05000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c05000 0x1000>; - interrupts = <10>; - clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 27>, - <&dma SUN4I_DMA_DEDICATED 26>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c06000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <11>; - clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 9>, - <&dma SUN4I_DMA_DEDICATED 8>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac: ethernet@1c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - reg = <0x01c0b000 0x1000>; - interrupts = <55>; - clocks = <&ccu CLK_AHB_EMAC>; - allwinner,sram = <&emac_sram 1>; - pinctrl-names = "default"; - pinctrl-0 = <&emac_pins>; - status = "disabled"; - }; - - mdio: mdio@1c0b080 { - compatible = "allwinner,sun4i-a10-mdio"; - reg = <0x01c0b080 0x14>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun4i-a10-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = <44>; - resets = <&ccu RST_TCON0>; - reset-names = "lcd"; - clocks = <&ccu CLK_AHB_LCD0>, - <&ccu CLK_TCON0_CH0>, - <&ccu CLK_TCON0_CH1>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon0-pixel-clock"; - #clock-cells = <0>; - dmas = <&dma SUN4I_DMA_DEDICATED 14>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon0>; - }; - - tcon0_in_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon0>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - tcon1: lcd-controller@1c0d000 { - compatible = "allwinner,sun4i-a10-tcon"; - reg = <0x01c0d000 0x1000>; - interrupts = <45>; - resets = <&ccu RST_TCON1>; - reset-names = "lcd"; - clocks = <&ccu CLK_AHB_LCD1>, - <&ccu CLK_TCON1_CH0>, - <&ccu CLK_TCON1_CH1>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon1-pixel-clock"; - #clock-cells = <0>; - dmas = <&dma SUN4I_DMA_DEDICATED 15>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon1_in_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_out_tcon1>; - }; - - tcon1_in_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_out_tcon1>; - }; - }; - - tcon1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon1_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon1>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun4i-a10-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_VE>; - interrupts = <53>; - allwinner,sram = <&ve_sram 1>; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; - interrupts = <32>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; - interrupts = <33>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; - interrupts = <34>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc3: mmc@1c12000 { - compatible = "allwinner,sun4i-a10-mmc"; - reg = <0x01c12000 0x1000>; - clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>; - clock-names = "ahb", "mmc"; - interrupts = <35>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@1c13000 { - compatible = "allwinner,sun4i-a10-musb"; - reg = <0x01c13000 0x0400>; - clocks = <&ccu CLK_AHB_OTG>; - interrupts = <38>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - allwinner,sram = <&otg_sram 1>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun4i-a10-usb-phy"; - reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>; - reg-names = "phy_ctrl", "pmu1", "pmu2"; - clocks = <&ccu CLK_USB_PHY>; - clock-names = "usb_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>; - reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; - status = "disabled"; - }; - - ehci0: usb@1c14000 { - compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; - reg = <0x01c14000 0x100>; - interrupts = <39>; - clocks = <&ccu CLK_AHB_EHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@1c14400 { - compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; - reg = <0x01c14400 0x100>; - interrupts = <64>; - clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - crypto: crypto-engine@1c15000 { - compatible = "allwinner,sun4i-a10-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = <86>; - clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; - clock-names = "ahb", "mod"; - }; - - hdmi: hdmi@1c16000 { - compatible = "allwinner,sun4i-a10-hdmi"; - reg = <0x01c16000 0x1000>; - interrupts = <58>; - clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, - <&ccu CLK_PLL_VIDEO0_2X>, - <&ccu CLK_PLL_VIDEO1_2X>; - clock-names = "ahb", "mod", "pll-0", "pll-1"; - dmas = <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_DEDICATED 24>; - dma-names = "ddc-tx", "ddc-rx", "audio-tx"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - hdmi_in_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_out_hdmi>; - }; - - hdmi_in_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - spi2: spi@1c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; - interrupts = <12>; - clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 29>, - <&dma SUN4I_DMA_DEDICATED 28>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ahci: sata@1c18000 { - compatible = "allwinner,sun4i-a10-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = <56>; - clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>; - status = "disabled"; - }; - - ehci1: usb@1c1c000 { - compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; - reg = <0x01c1c000 0x100>; - interrupts = <40>; - clocks = <&ccu CLK_AHB_EHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@1c1c400 { - compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; - reg = <0x01c1c400 0x100>; - interrupts = <65>; - clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - csi1: csi@1c1d000 { - compatible = "allwinner,sun4i-a10-csi1"; - reg = <0x01c1d000 0x1000>; - interrupts = <43>; - clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>; - clock-names = "bus", "ram"; - resets = <&ccu RST_CSI1>; - status = "disabled"; - }; - - spi3: spi@1c1f000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c1f000 0x1000>; - interrupts = <50>; - clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 31>, - <&dma SUN4I_DMA_DEDICATED 30>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun4i-a10-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - intc: interrupt-controller@1c20400 { - compatible = "allwinner,sun4i-a10-ic"; - reg = <0x01c20400 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun4i-a10-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = <28>; - clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - can0_ph_pins: can0-ph-pins { - pins = "PH20", "PH21"; - function = "can"; - }; - - /omit-if-no-ref/ - csi1_8bits_pg_pins: csi1-8bits-pg-pins { - pins = "PG0", "PG2", "PG3", "PG4", "PG5", - "PG6", "PG7", "PG8", "PG9", "PG10", - "PG11"; - function = "csi1"; - }; - - /omit-if-no-ref/ - csi1_24bits_ph_pins: csi1-24bits-ph-pins { - pins = "PH0", "PH1", "PH2", "PH3", "PH4", - "PH5", "PH6", "PH7", "PH8", "PH9", - "PH10", "PH11", "PH12", "PH13", "PH14", - "PH15", "PH16", "PH17", "PH18", "PH19", - "PH20", "PH21", "PH22", "PH23", "PH24", - "PH25", "PH26", "PH27"; - function = "csi1"; - }; - - /omit-if-no-ref/ - csi1_clk_pg_pin: csi1-clk-pg-pin { - pins = "PG1"; - function = "csi1"; - }; - - emac_pins: emac0-pins { - pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - function = "emac"; - }; - - i2c0_pins: i2c0-pins { - pins = "PB0", "PB1"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PB18", "PB19"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PB20", "PB21"; - function = "i2c2"; - }; - - ir0_rx_pins: ir0-rx-pin { - pins = "PB4"; - function = "ir0"; - }; - - ir0_tx_pins: ir0-tx-pin { - pins = "PB3"; - function = "ir0"; - }; - - ir1_rx_pins: ir1-rx-pin { - pins = "PB23"; - function = "ir1"; - }; - - ir1_tx_pins: ir1-tx-pin { - pins = "PB22"; - function = "ir1"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - ps2_ch0_pins: ps2-ch0-pins { - pins = "PI20", "PI21"; - function = "ps2"; - }; - - ps2_ch1_ph_pins: ps2-ch1-ph-pins { - pins = "PH12", "PH13"; - function = "ps2"; - }; - - pwm0_pin: pwm0-pin { - pins = "PB2"; - function = "pwm"; - }; - - pwm1_pin: pwm1-pin { - pins = "PI3"; - function = "pwm"; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PB13"; - function = "spdif"; - bias-pull-up; - }; - - spi0_pi_pins: spi0-pi-pins { - pins = "PI11", "PI12", "PI13"; - function = "spi0"; - }; - - spi0_cs0_pi_pin: spi0-cs0-pi-pin { - pins = "PI10"; - function = "spi0"; - }; - - spi1_pins: spi1-pins { - pins = "PI17", "PI18", "PI19"; - function = "spi1"; - }; - - spi1_cs0_pin: spi1-cs0-pin { - pins = "PI16"; - function = "spi1"; - }; - - spi2_pb_pins: spi2-pb-pins { - pins = "PB15", "PB16", "PB17"; - function = "spi2"; - }; - - spi2_pc_pins: spi2-pc-pins { - pins = "PC20", "PC21", "PC22"; - function = "spi2"; - }; - - spi2_cs0_pb_pin: spi2-cs0-pb-pin { - pins = "PB14"; - function = "spi2"; - }; - - spi2_cs0_pc_pins: spi2-cs0-pc-pin { - pins = "PC19"; - function = "spi2"; - }; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB22", "PB23"; - function = "uart0"; - }; - - uart0_pf_pins: uart0-pf-pins { - pins = "PF2", "PF4"; - function = "uart0"; - }; - - uart1_pins: uart1-pins { - pins = "PA10", "PA11"; - function = "uart1"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = <22>, - <23>, - <24>, - <25>, - <67>, - <68>; - clocks = <&osc24M>; - }; - - wdt: watchdog@1c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - interrupts = <24>; - clocks = <&osc24M>; - }; - - rtc: rtc@1c20d00 { - compatible = "allwinner,sun4i-a10-rtc"; - reg = <0x01c20d00 0x20>; - interrupts = <24>; - }; - - pwm: pwm@1c20e00 { - compatible = "allwinner,sun4i-a10-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - spdif: spdif@1c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-spdif"; - reg = <0x01c21000 0x400>; - interrupts = <13>; - clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; - clock-names = "apb", "spdif"; - dmas = <&dma SUN4I_DMA_NORMAL 2>, - <&dma SUN4I_DMA_NORMAL 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ir0: ir@1c21800 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>; - clock-names = "apb", "ir"; - interrupts = <5>; - reg = <0x01c21800 0x40>; - status = "disabled"; - }; - - ir1: ir@1c21c00 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>; - clock-names = "apb", "ir"; - interrupts = <6>; - reg = <0x01c21c00 0x40>; - status = "disabled"; - }; - - i2s0: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c22400 0x400>; - interrupts = <16>; - clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 3>, - <&dma SUN4I_DMA_NORMAL 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = <31>; - status = "disabled"; - }; - - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-codec"; - reg = <0x01c22c00 0x40>; - interrupts = <30>; - clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; - clock-names = "apb", "codec"; - dmas = <&dma SUN4I_DMA_NORMAL 19>, - <&dma SUN4I_DMA_NORMAL 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sid: eeprom@1c23800 { - compatible = "allwinner,sun4i-a10-sid"; - reg = <0x01c23800 0x10>; - }; - - rtp: rtp@1c25000 { - compatible = "allwinner,sun4i-a10-ts"; - reg = <0x01c25000 0x100>; - interrupts = <29>; - #thermal-sensor-cells = <0>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = <1>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = <2>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = <3>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART2>; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = <4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART3>; - status = "disabled"; - }; - - uart4: serial@1c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = <17>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART4>; - status = "disabled"; - }; - - uart5: serial@1c29400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29400 0x400>; - interrupts = <18>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART5>; - status = "disabled"; - }; - - uart6: serial@1c29800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29800 0x400>; - interrupts = <19>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART6>; - status = "disabled"; - }; - - uart7: serial@1c29c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29c00 0x400>; - interrupts = <20>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART7>; - status = "disabled"; - }; - - ps20: ps2@1c2a000 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a000 0x400>; - interrupts = <62>; - clocks = <&ccu CLK_APB1_PS20>; - status = "disabled"; - }; - - ps21: ps2@1c2a400 { - compatible = "allwinner,sun4i-a10-ps2"; - reg = <0x01c2a400 0x400>; - interrupts = <63>; - clocks = <&ccu CLK_APB1_PS21>; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = <7>; - clocks = <&ccu CLK_APB1_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = <8>; - clocks = <&ccu CLK_APB1_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = <9>; - clocks = <&ccu CLK_APB1_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - can0: can@1c2bc00 { - compatible = "allwinner,sun4i-a10-can"; - reg = <0x01c2bc00 0x400>; - interrupts = <26>; - clocks = <&ccu CLK_APB1_CAN>; - status = "disabled"; - }; - - mali: gpu@1c40000 { - compatible = "allwinner,sun4i-a10-mali", "arm,mali-400"; - reg = <0x01c40000 0x10000>; - interrupts = <69>, - <70>, - <71>, - <72>, - <73>; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pmu"; - clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_GPU>; - - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <384000000>; - }; - - fe0: display-frontend@1e00000 { - compatible = "allwinner,sun4i-a10-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = <47>; - clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, - <&ccu CLK_DRAM_DE_FE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_FE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe0>; - }; - - fe0_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_fe0>; - }; - }; - }; - }; - - fe1: display-frontend@1e20000 { - compatible = "allwinner,sun4i-a10-display-frontend"; - reg = <0x01e20000 0x20000>; - interrupts = <48>; - clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>, - <&ccu CLK_DRAM_DE_FE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_FE1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fe1_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_fe1>; - }; - - fe1_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_fe1>; - }; - }; - }; - }; - - be1: display-backend@1e40000 { - compatible = "allwinner,sun4i-a10-display-backend"; - reg = <0x01e40000 0x10000>; - interrupts = <48>; - clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>, - <&ccu CLK_DRAM_DE_BE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_BE1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be1_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be1>; - }; - - be1_in_fe1: endpoint@1 { - reg = <1>; - remote-endpoint = <&fe1_out_be1>; - }; - }; - - be1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be1_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be1>; - }; - - be1_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_be1>; - }; - }; - }; - }; - - be0: display-backend@1e60000 { - compatible = "allwinner,sun4i-a10-display-backend"; - reg = <0x01e60000 0x10000>; - interrupts = <47>; - clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>, - <&ccu CLK_DRAM_DE_BE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_BE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_fe0: endpoint@0 { - reg = <0>; - remote-endpoint = <&fe0_out_be0>; - }; - - be0_in_fe1: endpoint@1 { - reg = <1>; - remote-endpoint = <&fe1_out_be0>; - }; - }; - - be0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - be0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_be0>; - }; - - be0_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_be0>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/dts/sun5i-a10s-auxtek-t003.dts deleted file mode 100644 index 04b0e6d2876..00000000000 --- a/arch/arm/dts/sun5i-a10s-auxtek-t003.dts +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Auxtek t003 A10s hdmi tv-stick"; - compatible = "allwinner,auxtek-t003", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_t003>; - - led { - label = "t003-tv-dongle:red:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ - default-state = "on"; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp152: pmic@30 { - compatible = "x-powers,axp152"; - reg = <0x30>; - interrupts = <0>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_t003: led-pin { - pins = "PB2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb0_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/dts/sun5i-a10s-auxtek-t004.dts deleted file mode 100644 index 667bc2dc1ea..00000000000 --- a/arch/arm/dts/sun5i-a10s-auxtek-t004.dts +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Auxtek t004 A10s hdmi tv-stick"; - compatible = "allwinner,auxtek-t004", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_t004>; - - led { - label = "t004-tv-dongle:red:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ - default-state = "on"; - }; - }; - - reg_vmmc1: vmmc1 { - compatible = "regulator-fixed"; - regulator-name = "vmmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 1 18 GPIO_ACTIVE_HIGH>; /* PB18 */ - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp152: pmic@30 { - compatible = "x-powers,axp152"; - reg = <0x30>; - interrupts = <0>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vmmc1>; - bus-width = <4>; - non-removable; - cap-sdio-irq; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_t004: led-pin { - pins = "PB2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb1_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i-a10s-mk802.dts b/arch/arm/dts/sun5i-a10s-mk802.dts deleted file mode 100644 index d0219404c23..00000000000 --- a/arch/arm/dts/sun5i-a10s-mk802.dts +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "MK802-A10s"; - compatible = "allwinner,a10s-mk802", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "mk802:red:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp152: pmic@30 { - compatible = "x-powers,axp152"; - reg = <0x30>; - interrupts = <0>; - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts deleted file mode 100644 index 5832bb31fc5..00000000000 --- a/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "Olimex A10s-Olinuxino Micro"; - compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - serial1 = &uart2; - serial2 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxino>; - - led { - label = "a10s-olinuxino-micro:green:usr"; - gpios = <&pio 4 3 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&be0 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pa_pins>; - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c0 { - status = "okay"; - - axp152: pmic@30 { - reg = <0x30>; - interrupts = <0>; - }; -}; - -#include "axp152.dtsi" - -&i2c1 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c16"; - pagesize = <16>; - reg = <0x50>; - read-only; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-191 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <191274>; - }; - - button-392 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <392644>; - }; - - button-601 { - label = "Menu"; - linux,code = <KEY_MENU>; - channel = <0>; - voltage = <601151>; - }; - - button-795 { - label = "Enter"; - linux,code = <KEY_ENTER>; - channel = <0>; - voltage = <795090>; - }; - - button-987 { - label = "Home"; - linux,code = <KEY_HOMEPAGE>; - channel = <0>; - voltage = <987387>; - }; -}; - -&mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_olinuxino: led-pin { - pins = "PE3"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb0_vbus { - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pb_pins>, - <&spi2_cs0_pb_pin>; - status = "okay"; -}; - -&tcon0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pc_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts deleted file mode 100644 index 964360f0610..00000000000 --- a/arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright 2014 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "R7 A10s hdmi tv-stick"; - compatible = "allwinner,r7-tv-dongle", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_r7>; - - led { - label = "r7-tv-dongle:green:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - led_pins_r7: led-pin { - pins = "PB2"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb1_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/dts/sun5i-a10s-wobo-i5.dts deleted file mode 100644 index ef8baa99268..00000000000 --- a/arch/arm/dts/sun5i-a10s-wobo-i5.dts +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright 2015 Jelle van der Waa <jelle@vdwaa.nl> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a10s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "A10s-Wobo i5"; - compatible = "wobo,a10s-wobo-i5", "allwinner,sun5i-a10s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "a10s-wobo-i5:blue:usr"; - gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_emac_3v3: emac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "emac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <20000>; - enable-active-high; - gpio = <&pio 0 2 GPIO_ACTIVE_HIGH>; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_pd_pins>; - phy-handle = <&phy1>; - status = "okay"; -}; - -&emac_sram { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&mdio { - phy-supply = <®_emac_3v3>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi1"; -}; - -®_ldo4 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi2"; -}; - -®_usb1_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i-a10s.dtsi b/arch/arm/dts/sun5i-a10s.dtsi deleted file mode 100644 index 09c486b608b..00000000000 --- a/arch/arm/dts/sun5i-a10s.dtsi +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright 2013 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun5i.dtsi" - -#include <dt-bindings/dma/sun4i-a10.h> - -/ { - aliases { - ethernet0 = &emac; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer-lcd0-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-hdmi"; - clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>, - <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>, - <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>; - status = "disabled"; - }; - }; - - display-engine { - compatible = "allwinner,sun5i-a10s-display-engine"; - allwinner,pipelines = <&fe0>; - }; - - soc { - hdmi: hdmi@1c16000 { - compatible = "allwinner,sun5i-a10s-hdmi"; - reg = <0x01c16000 0x1000>; - interrupts = <58>; - clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, - <&ccu CLK_PLL_VIDEO0_2X>, - <&ccu CLK_PLL_VIDEO1_2X>; - clock-names = "ahb", "mod", "pll-0", "pll-1"; - dmas = <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_NORMAL 16>, - <&dma SUN4I_DMA_DEDICATED 24>; - dma-names = "ddc-tx", "ddc-rx", "audio-tx"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - - hdmi_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - pwm: pwm@1c20e00 { - compatible = "allwinner,sun5i-a10s-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&ccu CLK_HOSC>; - #pwm-cells = <3>; - status = "disabled"; - }; - }; -}; - -&ccu { - compatible = "allwinner,sun5i-a10s-ccu"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - -&pio { - compatible = "allwinner,sun5i-a10s-pinctrl"; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB19", "PB20"; - function = "uart0"; - }; - - uart2_pc_pins: uart2-pc-pins { - pins = "PC18", "PC19"; - function = "uart2"; - }; - - emac_pa_pins: emac-pa-pins { - pins = "PA0", "PA1", "PA2", - "PA3", "PA4", "PA5", "PA6", - "PA7", "PA8", "PA9", "PA10", - "PA11", "PA12", "PA13", "PA14", - "PA15", "PA16"; - function = "emac"; - }; - - mmc1_pins: mmc1-pins { - pins = "PG3", "PG4", "PG5", - "PG6", "PG7", "PG8"; - function = "mmc1"; - drive-strength = <30>; - }; - - spi2_pb_pins: spi2-pb-pins { - pins = "PB12", "PB13", "PB14"; - function = "spi2"; - }; - - spi2_cs0_pb_pin: spi2-cs0-pb-pin { - pins = "PB11"; - function = "spi2"; - }; -}; - -&tcon0_out { - tcon0_out_hdmi: endpoint@2 { - reg = <2>; - remote-endpoint = <&hdmi_in_tcon0>; - allwinner,tcon-channel = <1>; - }; -}; diff --git a/arch/arm/dts/sun5i-a13-difrnce-dit4350.dts b/arch/arm/dts/sun5i-a13-difrnce-dit4350.dts deleted file mode 100644 index 894c4c4f9a1..00000000000 --- a/arch/arm/dts/sun5i-a13-difrnce-dit4350.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2016 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" - -/ { - model = "Difrnce DIT4350"; - compatible = "difrnce,dit4350", "allwinner,sun5i-a13"; -}; diff --git a/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts deleted file mode 100644 index d059388d725..00000000000 --- a/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pwm/pwm.h> - -/ { - model = "Empire Electronix D709 tablet"; - compatible = "empire-electronix,d709", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - power-supply = <®_vcc3v3>; - /* TODO: backlight uses axp gpio1 as enable pin */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <200000>; - }; - - button-400 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i-a13-empire-electronix-m712.dts b/arch/arm/dts/sun5i-a13-empire-electronix-m712.dts deleted file mode 100644 index b1e2afd9de5..00000000000 --- a/arch/arm/dts/sun5i-a13-empire-electronix-m712.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2016 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "Empire Electronix M712 tablet"; - compatible = "empire-electronix,m712", "allwinner,sun5i-a13"; -}; diff --git a/arch/arm/dts/sun5i-a13-hsg-h702.dts b/arch/arm/dts/sun5i-a13-hsg-h702.dts deleted file mode 100644 index 9b9f2a57485..00000000000 --- a/arch/arm/dts/sun5i-a13-hsg-h702.dts +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai <wens@csie.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "HSG H702"; - compatible = "hsg,h702", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&i2c1 { - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <200000>; - }; - - button-400 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i-a13-inet-98v-rev2.dts b/arch/arm/dts/sun5i-a13-inet-98v-rev2.dts deleted file mode 100644 index 439ae3b537d..00000000000 --- a/arch/arm/dts/sun5i-a13-inet-98v-rev2.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" - -/ { - model = "INet-98V Rev 02"; - compatible = "primux,inet98v-rev2", "allwinner,sun5i-a13"; -}; diff --git a/arch/arm/dts/sun5i-a13-licheepi-one.dts b/arch/arm/dts/sun5i-a13-licheepi-one.dts deleted file mode 100644 index 3a6c4bd0a44..00000000000 --- a/arch/arm/dts/sun5i-a13-licheepi-one.dts +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright 2016 Icenowy Zheng <icenowy@aosc.xyz> - * - * Based on sun5i-a13-olinuxino.dts, which is - * Copyright 2012 Maxime Ripard <maxime.ripard@free-electrons.com> - * Copyright 2013 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "Lichee Pi One"; - compatible = "licheepi,licheepi-one", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "licheepi:red:usr"; - gpios = <&pio 2 5 GPIO_ACTIVE_LOW>; - }; - - led-1 { - label = "licheepi:green:usr"; - gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - led-2 { - label = "licheepi:blue:usr"; - gpios = <&pio 2 4 GPIO_ACTIVE_LOW>; - }; - - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "disabled"; -}; - -&i2c2 { - status = "disabled"; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-984 { - label = "Home"; - linux,code = <KEY_HOMEPAGE>; - channel = <0>; - voltage = <984126>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - broken-cd; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pc_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - broken-cd; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -#include "axp209.dtsi" - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "csi-1.8v"; -}; - -®_ldo4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "csi-2.8v"; -}; - -®_usb0_vbus { - gpio = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/dts/sun5i-a13-olinuxino-micro.dts deleted file mode 100644 index bfe1075e62c..00000000000 --- a/arch/arm/dts/sun5i-a13-olinuxino-micro.dts +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard <maxime.ripard@free-electrons.com> - * Copyright 2013 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Olimex A13-Olinuxino Micro"; - compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxinom>; - - led { - label = "a13-olinuxino-micro:green:power"; - gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_olinuxinom: led-pin { - pins = "PG9"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i-a13-olinuxino.dts b/arch/arm/dts/sun5i-a13-olinuxino.dts deleted file mode 100644 index fadeae3cd8b..00000000000 --- a/arch/arm/dts/sun5i-a13-olinuxino.dts +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "Olimex A13-Olinuxino"; - compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olinuxino>; - - led { - gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - bridge { - compatible = "dumb-vga-dac"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&tcon0_out_vga>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_bridge_out>; - }; - }; - }; -}; - -&be0 { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupts = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-191 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <191274>; - }; - - button-392 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <392644>; - }; - - button-601 { - label = "Menu"; - linux,code = <KEY_MENU>; - channel = <0>; - voltage = <601151>; - }; - - button-795 { - label = "Enter"; - linux,code = <KEY_ENTER>; - channel = <0>; - voltage = <795090>; - }; - - button-987 { - label = "Home"; - linux,code = <KEY_HOMEPAGE>; - channel = <0>; - voltage = <987387>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - led_pins_olinuxino: led-pin { - pins = "PG9"; - function = "gpio_out"; - drive-strength = <20>; - }; -}; - -®_usb0_vbus { - status = "okay"; - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ -}; - -®_usb1_vbus { - gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rgb666_pins>; - status = "okay"; -}; - -&tcon0_out { - tcon0_out_vga: endpoint@0 { - reg = <0>; - remote-endpoint = <&vga_bridge_in>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i-a13-pocketbook-touch-lux-3.dts b/arch/arm/dts/sun5i-a13-pocketbook-touch-lux-3.dts deleted file mode 100644 index d60407772e5..00000000000 --- a/arch/arm/dts/sun5i-a13-pocketbook-touch-lux-3.dts +++ /dev/null @@ -1,258 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2019 Ondrej Jirman <megous@megous.com> - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pwm/pwm.h> - -/ { - model = "PocketBook Touch Lux 3"; - compatible = "pocketbook,touch-lux-3", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - enable-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - power-supply = <®_vcc3v3>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led { - gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */ - default-state = "on"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - label = "GPIO Keys"; - - key-right { - label = "Right"; - linux,code = <KEY_RIGHT>; - gpios = <&pio 6 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG9 */ - }; - - key-left { - label = "Left"; - linux,code = <KEY_LEFT>; - gpios = <&pio 6 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG10 */ - }; - }; - - reg_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vdd-1v8-nor-ctp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&pio 2 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_1v8_nor: regulator-nor { - compatible = "regulator-fixed"; - regulator-name = "vdd-nor"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&pio 2 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_1v8>; - regulator-always-on; - }; - - reg_1v8_ctp: regulator-ctp { - compatible = "regulator-fixed"; - regulator-name = "vdd-ctp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&pio 2 13 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_1v8>; - }; - - reg_3v3_mmc0: regulator-mmc0 { - compatible = "regulator-fixed"; - regulator-name = "vdd-mmc0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 4 4 GPIO_ACTIVE_LOW>; /* PE4 */ - vin-supply = <®_vcc3v3>; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&i2c2 { - status = "okay"; - - /* Touchpanel is connected here. */ -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Home"; - linux,code = <KEY_HOME>; - channel = <0>; - voltage = <200000>; - }; - - button-400 { - label = "Menu"; - linux,code = <KEY_MENU>; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_3v3_mmc0>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pc_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; - /* We need this otherwise the LDO3 would overload */ - regulator-soft-start; - regulator-ramp-delay = <1600>; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pe_pins>, <&spi2_cs0_pe_pin>; - status = "okay"; - - epd_flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "macronix,mx25u4033", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <4000000>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_ldo3>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i-a13-q8-tablet.dts b/arch/arm/dts/sun5i-a13-q8-tablet.dts deleted file mode 100644 index f9fc1c8b60b..00000000000 --- a/arch/arm/dts/sun5i-a13-q8-tablet.dts +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" - -/ { - model = "Q8 A13 Tablet"; - compatible = "allwinner,q8-a13", "allwinner,sun5i-a13"; - - panel: panel { - compatible = "bananapi,s070wv20-ct16"; - power-supply = <®_vcc3v3>; - enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */ - backlight = <&backlight>; - - port { - panel_input: endpoint { - remote-endpoint = <&tcon0_out_lcd>; - }; - }; - }; -}; - -&be0 { - status = "okay"; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rgb666_pins>; - status = "okay"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; diff --git a/arch/arm/dts/sun5i-a13-utoo-p66.dts b/arch/arm/dts/sun5i-a13-utoo-p66.dts deleted file mode 100644 index be486d28d04..00000000000 --- a/arch/arm/dts/sun5i-a13-utoo-p66.dts +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-a13.dtsi" -#include "sun5i-reference-design-tablet.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "Utoo P66"; - compatible = "utoo,p66", "allwinner,sun5i-a13"; - - /* The P66 uses the uart pins as gpios */ - aliases { - /delete-property/serial0; - }; - - chosen { - /delete-property/stdout-path; - }; - - i2c_lcd: i2c { - /* The lcd panel i2c interface is hooked up via gpios */ - compatible = "i2c-gpio"; - sda-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */ - scl-gpios = <&pio 6 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG10 */ - i2c-gpio,delay-us = <5>; - }; -}; - -&backlight { - /* Note levels of 10 / 20% result in backlight off */ - brightness-levels = <0 30 40 50 60 70 80 90 100>; - default-brightness-level = <6>; -}; - -&codec { - allwinner,pa-gpios = <&pio 6 3 GPIO_ACTIVE_HIGH>; /* PG3 */ -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - status = "okay"; - - mmccard: mmccard@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; - -®_usb0_vbus { - gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ -}; - -&touchscreen { - compatible = "chipone,icn8318"; - reg = <0x40>; - /* The P66 uses a different EINT then the reference design */ - interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ - /* The icn8318 binding expects wake-gpios instead of power-gpios */ - wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - status = "okay"; -}; - -&uart1 { - /* The P66 uses the uart pins as gpios */ - status = "disabled"; -}; diff --git a/arch/arm/dts/sun5i-a13.dtsi b/arch/arm/dts/sun5i-a13.dtsi deleted file mode 100644 index 2c9152b151b..00000000000 --- a/arch/arm/dts/sun5i-a13.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright 2012 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun5i.dtsi" - -#include <dt-bindings/thermal/thermal.h> - -/ { - thermal-zones { - cpu-thermal { - /* milliseconds */ - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&rtp>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu-alert0 { - /* milliCelsius */ - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - /* milliCelsius */ - temperature = <100000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - display-engine { - compatible = "allwinner,sun5i-a13-display-engine"; - allwinner,pipelines = <&fe0>; - }; - - soc { - pwm: pwm@1c20e00 { - compatible = "allwinner,sun5i-a13-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&ccu CLK_HOSC>; - #pwm-cells = <3>; - status = "disabled"; - }; - - }; -}; - -&ccu { - compatible = "allwinner,sun5i-a13-ccu"; -}; - -&cpu0 { - clock-latency = <244144>; /* 8 32k periods */ - operating-points = - /* kHz uV */ - <1008000 1400000>, - <912000 1350000>, - <864000 1300000>, - <624000 1200000>, - <576000 1200000>, - <432000 1200000>; - #cooling-cells = <2>; -}; - -&pio { - compatible = "allwinner,sun5i-a13-pinctrl"; -}; diff --git a/arch/arm/dts/sun5i-gr8-chip-pro.dts b/arch/arm/dts/sun5i-gr8-chip-pro.dts deleted file mode 100644 index ffbd99c176d..00000000000 --- a/arch/arm/dts/sun5i-gr8-chip-pro.dts +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright 2016 Free Electrons - * Copyright 2016 NextThing Co - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-gr8.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "NextThing C.H.I.P. Pro"; - compatible = "nextthing,chip-pro", "nextthing,gr8"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "chip-pro:white:status"; - gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - mmc0_pwrseq: pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ - }; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - - /* - * The interrupt is routed through the "External Fast - * Interrupt Request" pin (ball G13 of the module) - * directly to the main interrupt controller, without - * any other controller interfering. - */ - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "disabled"; -}; - -&i2s0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk_pin>, <&i2s0_data_pins>; - status = "disabled"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc0_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; - status = "okay"; - - nand@0 { - reg = <0>; - allwinner,rb = <0>; - nand-ecc-mode = "hw"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>, <&pwm1_pins>; - status = "disabled"; -}; - -®_dcdc2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; - regulator-always-on; -}; - -®_dcdc3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-sys"; - regulator-always-on; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; - regulator-always-on; -}; - -/* - * Both LDO3 and LDO4 are used in parallel to power up the - * WiFi/BT chip. - */ -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-1"; - regulator-always-on; -}; - -®_ldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; - regulator-always-on; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pd_pins>, <&uart2_cts_rts_pd_pins>; - status = "disabled"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>; - status = "okay"; -}; - -&usb_otg { - /* - * The CHIP Pro doesn't have a controllable VBUS, nor does it - * have any 5v rail on the board itself. - * - * If one wants to use it as a true OTG port, it should be - * done in the baseboard, and its DT / overlay will add it. - */ - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb1_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i-gr8-evb.dts b/arch/arm/dts/sun5i-gr8-evb.dts deleted file mode 100644 index f4fe258ef06..00000000000 --- a/arch/arm/dts/sun5i-gr8-evb.dts +++ /dev/null @@ -1,333 +0,0 @@ -/* - * Copyright 2016 Free Electrons - * Copyright 2016 NextThing Co - * - * Mylène Josserand <mylene.josserand@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-gr8.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "NextThing GR8-EVB"; - compatible = "nextthing,gr8-evb", "nextthing,gr8"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - serial0 = &uart1; - serial1 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 10000 0>; - enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; - power-supply = <®_vcc3v3>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - }; - - sound-analog { - compatible = "simple-audio-card"; - simple-audio-card,name = "gr8-evb-wm8978"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <512>; - - simple-audio-card,cpu { - sound-dai = <&i2s0>; - }; - - simple-audio-card,codec { - sound-dai = <&wm8978>; - }; - }; - - sound-spdif { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&be0 { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - - /* - * The interrupt is routed through the "External Fast - * Interrupt Request" pin (ball G13 of the module) - * directly to the main interrupt controller, without - * any other controller interfering. - */ - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - status = "okay"; - - wm8978: codec@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8978"; - reg = <0x1a>; - }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2s0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk_pin>, <&i2s0_data_pins>; - status = "okay"; -}; - -&ir0 { - pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pin>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-190 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <190000>; - }; - - button-390 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <390000>; - }; - - button-600 { - label = "Menu"; - linux,code = <KEY_MENU>; - channel = <0>; - voltage = <600000>; - }; - - button-800 { - label = "Search"; - linux,code = <KEY_SEARCH>; - channel = <0>; - voltage = <800000>; - }; - - button-980 { - label = "Home"; - linux,code = <KEY_HOMEPAGE>; - channel = <0>; - voltage = <980000>; - }; - - button-1180 { - label = "Esc"; - linux,code = <KEY_ESC>; - channel = <0>; - voltage = <1180000>; - }; - - button-1400 { - label = "Enter"; - linux,code = <KEY_ENTER>; - channel = <0>; - voltage = <1400000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; - - /* MLC Support sucks for now */ - status = "disabled"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "okay"; -}; - -®_dcdc2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; - regulator-always-on; -}; - -®_dcdc3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-sys"; - regulator-always-on; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; - regulator-always-on; -}; - -®_usb1_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&rtp { - allwinner,ts-attached; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "okay"; -}; - -&tve0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pins>; - status = "okay"; -}; - -&usb_otg { - /* - * The GR8-EVB has a somewhat interesting design. There's a - * pin supposed to control VBUS, an ID pin, a VBUS detect pin, - * so everything should work just fine. - * - * Except that the pin supposed to control VBUS is not - * connected to any controllable output, neither to the SoC - * through a GPIO or to the PMIC, and it is pulled down, - * meaning that we will never be able to enable VBUS on this - * board. - */ - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i-gr8.dtsi b/arch/arm/dts/sun5i-gr8.dtsi deleted file mode 100644 index 98a8fd5e89e..00000000000 --- a/arch/arm/dts/sun5i-gr8.dtsi +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright 2016 Mylène Josserand - * - * Mylène Josserand <mylene.josserand@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun5i.dtsi" - -#include <dt-bindings/clock/sun5i-ccu.h> -#include <dt-bindings/dma/sun4i-a10.h> -#include <dt-bindings/reset/sun5i-ccu.h> - -/ { - display-engine { - compatible = "allwinner,sun5i-a13-display-engine"; - allwinner,pipelines = <&fe0>; - }; - - soc { - pwm: pwm@1c20e00 { - compatible = "allwinner,sun5i-a10s-pwm"; - reg = <0x01c20e00 0xc>; - clocks = <&ccu CLK_HOSC>; - #pwm-cells = <3>; - status = "disabled"; - }; - - spdif: spdif@1c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-spdif"; - reg = <0x01c21000 0x400>; - interrupts = <13>; - clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>; - clock-names = "apb", "spdif"; - dmas = <&dma SUN4I_DMA_NORMAL 2>, - <&dma SUN4I_DMA_NORMAL 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s0: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-i2s"; - reg = <0x01c22400 0x400>; - interrupts = <16>; - clocks = <&ccu CLK_APB0_I2S>, <&ccu CLK_I2S>; - clock-names = "apb", "mod"; - dmas = <&dma SUN4I_DMA_NORMAL 3>, - <&dma SUN4I_DMA_NORMAL 3>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; -}; - -&ccu { - compatible = "nextthing,gr8-ccu"; -}; - -&pio { - compatible = "nextthing,gr8-pinctrl"; - - i2s0_data_pins: i2s0-data-pins { - pins = "PB6", "PB7", "PB8", "PB9"; - function = "i2s0"; - }; - - i2s0_mclk_pin: i2s0-mclk-pin { - pins = "PB5"; - function = "i2s0"; - }; - - pwm1_pins: pwm1-pin { - pins = "PG13"; - function = "pwm1"; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PB10"; - function = "spdif"; - bias-pull-up; - }; - - uart1_cts_rts_pins: uart1-cts-rts-pins { - pins = "PG5", "PG6"; - function = "uart1"; - }; -}; diff --git a/arch/arm/dts/sun5i-r8-chip.dts b/arch/arm/dts/sun5i-r8-chip.dts deleted file mode 100644 index 8c784a2c086..00000000000 --- a/arch/arm/dts/sun5i-r8-chip.dts +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright 2015 Free Electrons - * Copyright 2015 NextThing Co - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun5i-r8.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "NextThing C.H.I.P."; - compatible = "nextthing,chip", "allwinner,sun5i-r8", "allwinner,sun5i-a13"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - serial0 = &uart1; - serial1 = &uart3; - spi0 = &spi2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "chip:white:status"; - gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - mmc0_pwrseq: pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */ - }; - - onewire { - compatible = "w1-gpio"; - gpios = <&pio 3 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PD2 */ - }; -}; - -&be0 { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - - /* - * The interrupt is routed through the "External Fast - * Interrupt Request" pin (ball G13 of the module) - * directly to the main interrupt controller, without - * any other controller interfering. - */ - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -&i2c1 { - status = "disabled"; -}; - -&i2c2 { - status = "okay"; - - xio: gpio@38 { - compatible = "nxp,pcf8574a"; - reg = <0x38>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&pio>; - interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&mmc0_pins { - bias-pull-up; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&mmc0_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "cpuvdd"; - regulator-always-on; -}; - -®_dcdc3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "corevdd"; - regulator-always-on; -}; - -®_ldo1 { - regulator-name = "rtcvdd"; -}; - -®_ldo2 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; - regulator-always-on; -}; - -/* - * Both LDO3 and LDO4 are used in parallel to power up the WiFi/BT - * Chip. - * - * If those are not enabled, the SDIO part will not enumerate, and - * since there's no way currently to pass DT infos to an SDIO device, - * we cannot really do better than this ugly hack for now. - */ -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-1"; - regulator-always-on; -}; - -®_ldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; - regulator-always-on; -}; - -®_ldo5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8"; -}; - -®_usb0_vbus { - vin-supply = <®_vcc5v0>; - gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pe_pins>; - status = "disabled"; -}; - -&tcon0 { - status = "okay"; -}; - -&tve0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>, - <&uart3_cts_rts_pg_pins>; - status = "okay"; - - bluetooth { - compatible = "realtek,rtl8723bs-bt"; - device-wake-gpios = <&axp_gpio 3 GPIO_ACTIVE_HIGH>; - host-wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - }; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - status = "okay"; - - usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_vcc5v0>; -}; diff --git a/arch/arm/dts/sun5i-r8.dtsi b/arch/arm/dts/sun5i-r8.dtsi deleted file mode 100644 index de35dbcd119..00000000000 --- a/arch/arm/dts/sun5i-r8.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2015 Free Electrons - * Copyright 2015 NextThing Co - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun5i-a13.dtsi" - diff --git a/arch/arm/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/dts/sun5i-reference-design-tablet.dtsi deleted file mode 100644 index 6847f66699a..00000000000 --- a/arch/arm/dts/sun5i-reference-design-tablet.dtsi +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "sunxi-reference-design-tablet.dtsi" - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pwm/pwm.h> - -/ { - aliases { - serial0 = &uart1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; /* AXP GPIO1 */ - power-supply = <®_vcc3v0>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&codec { - allwinner,pa-gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&i2c1 { - /* - * The gsl1680 is rated at 400KHz and it will not work reliable at - * 100KHz, this has been confirmed on multiple different q8 tablets. - * All other devices on this bus are also rated for 400KHz. - */ - clock-frequency = <400000>; - - touchscreen: touchscreen@40 { - reg = <0x40>; - interrupt-parent = <&pio>; - interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */ - power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ - /* Tablet dts must provide reg and compatible */ - status = "disabled"; - }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -&lradc { - vref-supply = <®_ldo2>; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pg_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ - usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun5i.dtsi b/arch/arm/dts/sun5i.dtsi deleted file mode 100644 index d7c7b454a11..00000000000 --- a/arch/arm/dts/sun5i.dtsi +++ /dev/null @@ -1,819 +0,0 @@ -/* - * Copyright 2012-2015 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include <dt-bindings/clock/sun5i-ccu.h> -#include <dt-bindings/dma/sun4i-a10.h> -#include <dt-bindings/reset/sun5i-ccu.h> - -/ { - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - clocks = <&ccu CLK_CPU>; - }; - }; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer-lcd0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0"; - clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, - <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>; - status = "disabled"; - }; - - framebuffer-lcd0-tve0 { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>, - <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, - <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>; - status = "disabled"; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: clk-24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: clk-32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - default-pool { - compatible = "shared-dma-pool"; - size = <0x6000000>; - alloc-ranges = <0x40000000 0x10000000>; - reusable; - linux,cma-default; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - dma-ranges; - ranges; - - system-control@1c00000 { - compatible = "allwinner,sun5i-a13-system-control"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_a: sram@0 { - compatible = "mmio-sram"; - reg = <0x00000000 0xc000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00000000 0xc000>; - - emac_sram: sram-section@8000 { - compatible = "allwinner,sun5i-a13-sram-a3-a4", - "allwinner,sun4i-a10-sram-a3-a4"; - reg = <0x8000 0x4000>; - status = "disabled"; - }; - }; - - sram_d: sram@10000 { - compatible = "mmio-sram"; - reg = <0x00010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00010000 0x1000>; - - otg_sram: sram-section@0 { - compatible = "allwinner,sun5i-a13-sram-d", - "allwinner,sun4i-a10-sram-d"; - reg = <0x0000 0x1000>; - status = "disabled"; - }; - }; - - sram_c: sram@1d00000 { - compatible = "mmio-sram"; - reg = <0x01d00000 0xd0000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01d00000 0xd0000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun5i-a13-sram-c1", - "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x80000>; - }; - }; - }; - - mbus: dram-controller@1c01000 { - compatible = "allwinner,sun5i-a13-mbus"; - reg = <0x01c01000 0x1000>; - clocks = <&ccu CLK_MBUS>; - #address-cells = <1>; - #size-cells = <1>; - dma-ranges = <0x00000000 0x40000000 0x20000000>; - #interconnect-cells = <1>; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun4i-a10-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <27>; - clocks = <&ccu CLK_AHB_DMA>; - #dma-cells = <2>; - }; - - nfc: nand-controller@1c03000 { - compatible = "allwinner,sun4i-a10-nand"; - reg = <0x01c03000 0x1000>; - interrupts = <37>; - clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 3>; - dma-names = "rxtx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@1c05000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c05000 0x1000>; - interrupts = <10>; - clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 27>, - <&dma SUN4I_DMA_DEDICATED 26>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c06000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <11>; - clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 9>, - <&dma SUN4I_DMA_DEDICATED 8>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - tve0: tv-encoder@1c0a000 { - compatible = "allwinner,sun4i-a10-tv-encoder"; - reg = <0x01c0a000 0x1000>; - clocks = <&ccu CLK_AHB_TVE>; - resets = <&ccu RST_TVE>; - status = "disabled"; - - port { - - tve0_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_tve0>; - }; - }; - }; - - emac: ethernet@1c0b000 { - compatible = "allwinner,sun4i-a10-emac"; - reg = <0x01c0b000 0x1000>; - interrupts = <55>; - clocks = <&ccu CLK_AHB_EMAC>; - allwinner,sram = <&emac_sram 1>; - status = "disabled"; - }; - - mdio: mdio@1c0b080 { - compatible = "allwinner,sun4i-a10-mdio"; - reg = <0x01c0b080 0x14>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun5i-a13-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = <44>; - dmas = <&dma SUN4I_DMA_DEDICATED 14>; - resets = <&ccu RST_LCD>; - reset-names = "lcd"; - clocks = <&ccu CLK_AHB_LCD>, - <&ccu CLK_TCON_CH0>, - <&ccu CLK_TCON_CH1>; - clock-names = "ahb", - "tcon-ch0", - "tcon-ch1"; - clock-output-names = "tcon-data-clock"; - #clock-cells = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - reg = <0>; - - tcon0_in_be0: endpoint { - remote-endpoint = <&be0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_tve0: endpoint@1 { - reg = <1>; - remote-endpoint = <&tve0_in_tcon0>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun5i-a13-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_VE>; - interrupts = <53>; - allwinner,sram = <&ve_sram 1>; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; - interrupts = <32>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; - interrupts = <33>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun5i-a13-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; - interrupts = <34>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@1c13000 { - compatible = "allwinner,sun4i-a10-musb"; - reg = <0x01c13000 0x0400>; - clocks = <&ccu CLK_AHB_OTG>; - interrupts = <38>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - allwinner,sram = <&otg_sram 1>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c13400 { - #phy-cells = <1>; - compatible = "allwinner,sun5i-a13-usb-phy"; - reg = <0x01c13400 0x10>, <0x01c14800 0x4>; - reg-names = "phy_ctrl", "pmu1"; - clocks = <&ccu CLK_USB_PHY0>; - clock-names = "usb_phy"; - resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>; - reset-names = "usb0_reset", "usb1_reset"; - status = "disabled"; - }; - - ehci0: usb@1c14000 { - compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; - reg = <0x01c14000 0x100>; - interrupts = <39>; - clocks = <&ccu CLK_AHB_EHCI>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@1c14400 { - compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; - reg = <0x01c14400 0x100>; - interrupts = <40>; - clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - crypto: crypto-engine@1c15000 { - compatible = "allwinner,sun5i-a13-crypto", - "allwinner,sun4i-a10-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = <54>; - clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; - clock-names = "ahb", "mod"; - }; - - spi2: spi@1c17000 { - compatible = "allwinner,sun4i-a10-spi"; - reg = <0x01c17000 0x1000>; - interrupts = <12>; - clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; - clock-names = "ahb", "mod"; - dmas = <&dma SUN4I_DMA_DEDICATED 29>, - <&dma SUN4I_DMA_DEDICATED 28>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ccu: clock@1c20000 { - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - intc: interrupt-controller@1c20400 { - compatible = "allwinner,sun4i-a10-ic"; - reg = <0x01c20400 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - pio: pinctrl@1c20800 { - reg = <0x01c20800 0x400>; - interrupts = <28>; - clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - emac_pd_pins: emac-pd-pins { - pins = "PD6", "PD7", "PD10", - "PD11", "PD12", "PD13", "PD14", - "PD15", "PD18", "PD19", "PD20", - "PD21", "PD22", "PD23", "PD24", - "PD25", "PD26", "PD27"; - function = "emac"; - }; - - i2c0_pins: i2c0-pins { - pins = "PB0", "PB1"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PB15", "PB16"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PB17", "PB18"; - function = "i2c2"; - }; - - ir0_rx_pin: ir0-rx-pin { - pins = "PB4"; - function = "ir0"; - }; - - lcd_rgb565_pins: lcd-rgb565-pins { - pins = "PD3", "PD4", "PD5", "PD6", "PD7", - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", - "PD19", "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - function = "lcd0"; - }; - - lcd_rgb666_pins: lcd-rgb666-pins { - pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", - "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - function = "lcd0"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_4bit_pc_pins: mmc2-4bit-pc-pins { - pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - mmc2_4bit_pe_pins: mmc2-4bit-pe-pins { - pins = "PE4", "PE5", "PE6", "PE7", - "PE8", "PE9"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_8bit_pins: mmc2-8bit-pins { - pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", "PC13", - "PC14", "PC15"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - nand_pins: nand-pins { - pins = "PC0", "PC1", "PC2", - "PC5", "PC8", "PC9", "PC10", - "PC11", "PC12", "PC13", "PC14", - "PC15"; - function = "nand0"; - }; - - nand_cs0_pin: nand-cs0-pin { - pins = "PC4"; - function = "nand0"; - }; - - nand_rb0_pin: nand-rb0-pin { - pins = "PC6"; - function = "nand0"; - }; - - pwm0_pin: pwm0-pin { - pins = "PB2"; - function = "pwm"; - }; - - spi2_pe_pins: spi2-pe-pins { - pins = "PE1", "PE2", "PE3"; - function = "spi2"; - }; - - spi2_cs0_pe_pin: spi2-cs0-pe-pin { - pins = "PE0"; - function = "spi2"; - }; - - uart1_pe_pins: uart1-pe-pins { - pins = "PE10", "PE11"; - function = "uart1"; - }; - - uart1_pg_pins: uart1-pg-pins { - pins = "PG3", "PG4"; - function = "uart1"; - }; - - uart2_pd_pins: uart2-pd-pins { - pins = "PD2", "PD3"; - function = "uart2"; - }; - - uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins { - pins = "PD4", "PD5"; - function = "uart2"; - }; - - uart3_pg_pins: uart3-pg-pins { - pins = "PG9", "PG10"; - function = "uart3"; - }; - - uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins { - pins = "PG11", "PG12"; - function = "uart3"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0x90>; - interrupts = <22>, - <23>, - <24>, - <25>, - <67>, - <68>; - clocks = <&ccu CLK_HOSC>; - }; - - wdt: watchdog@1c20c90 { - compatible = "allwinner,sun4i-a10-wdt"; - reg = <0x01c20c90 0x10>; - interrupts = <24>; - clocks = <&osc24M>; - }; - - ir0: ir@1c21800 { - compatible = "allwinner,sun4i-a10-ir"; - clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>; - clock-names = "apb", "ir"; - interrupts = <5>; - reg = <0x01c21800 0x40>; - status = "disabled"; - }; - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x100>; - interrupts = <31>; - status = "disabled"; - }; - - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun4i-a10-codec"; - reg = <0x01c22c00 0x40>; - interrupts = <30>; - clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; - clock-names = "apb", "codec"; - dmas = <&dma SUN4I_DMA_NORMAL 19>, - <&dma SUN4I_DMA_NORMAL 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sid: eeprom@1c23800 { - compatible = "allwinner,sun4i-a10-sid"; - reg = <0x01c23800 0x10>; - }; - - rtp: rtp@1c25000 { - compatible = "allwinner,sun5i-a13-ts"; - reg = <0x01c25000 0x100>; - interrupts = <29>; - #thermal-sensor-cells = <0>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = <1>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = <2>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = <3>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART2>; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = <4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_APB1_UART3>; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = <7>; - clocks = <&ccu CLK_APB1_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = <8>; - clocks = <&ccu CLK_APB1_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun4i-a10-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = <9>; - clocks = <&ccu CLK_APB1_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mali: gpu@1c40000 { - compatible = "allwinner,sun4i-a10-mali", "arm,mali-400"; - reg = <0x01c40000 0x10000>; - interrupts = <69>, <70>, <71>, <72>, <73>; - interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pmu"; - clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_GPU>; - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <320000000>; - }; - - timer@1c60000 { - compatible = "allwinner,sun5i-a13-hstimer"; - reg = <0x01c60000 0x1000>; - interrupts = <82>, <83>; - clocks = <&ccu CLK_AHB_HSTIMER>; - }; - - fe0: display-frontend@1e00000 { - compatible = "allwinner,sun5i-a13-display-frontend"; - reg = <0x01e00000 0x20000>; - interrupts = <47>; - clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>, - <&ccu CLK_DRAM_DE_FE>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_FE>; - interconnects = <&mbus 19>; - interconnect-names = "dma-mem"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - reg = <1>; - - fe0_out_be0: endpoint { - remote-endpoint = <&be0_in_fe0>; - }; - }; - }; - }; - - be0: display-backend@1e60000 { - compatible = "allwinner,sun5i-a13-display-backend"; - reg = <0x01e60000 0x10000>; - interrupts = <47>; - clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, - <&ccu CLK_DRAM_DE_BE>; - clock-names = "ahb", "mod", - "ram"; - resets = <&ccu RST_DE_BE>; - interconnects = <&mbus 18>; - interconnect-names = "dma-mem"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - reg = <0>; - - be0_in_fe0: endpoint { - remote-endpoint = <&fe0_out_be0>; - }; - }; - - be0_out: port@1 { - reg = <1>; - - be0_out_tcon0: endpoint { - remote-endpoint = <&tcon0_in_be0>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts deleted file mode 100644 index 43896723a99..00000000000 --- a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright 2018 Icenowy Zheng <icenowy@aosc.io> - */ - -/dts-v1/; -#include "suniv-f1c100s.dtsi" - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Lichee Pi Nano"; - compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; - - aliases { - mmc0 = &mmc0; - serial0 = &uart0; - spi0 = &spi0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - disable-wp; - status = "okay"; - vmmc-supply = <®_vcc3v3>; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pc_pins>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&otg_sram { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pe_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */ - status = "okay"; -}; diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi deleted file mode 100644 index 3c61d59ab5f..00000000000 --- a/arch/arm/dts/suniv-f1c100s.dtsi +++ /dev/null @@ -1,330 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright 2018 Icenowy Zheng <icenowy@aosc.io> - * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com> - */ - -#include <dt-bindings/clock/suniv-ccu-f1c100s.h> -#include <dt-bindings/reset/suniv-ccu-f1c100s.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - clocks { - osc24M: clk-24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: clk-32k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - reg = <0x0>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram-controller@1c00000 { - compatible = "allwinner,suniv-f1c100s-system-control", - "allwinner,sun4i-a10-system-control"; - reg = <0x01c00000 0x30>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_d: sram@10000 { - compatible = "mmio-sram"; - reg = <0x00010000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00010000 0x1000>; - - otg_sram: sram-section@0 { - compatible = "allwinner,suniv-f1c100s-sram-d", - "allwinner,sun4i-a10-sram-d"; - reg = <0x0000 0x1000>; - status = "disabled"; - }; - }; - }; - - spi0: spi@1c05000 { - compatible = "allwinner,suniv-f1c100s-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c05000 0x1000>; - interrupts = <10>; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c06000 { - compatible = "allwinner,suniv-f1c100s-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <11>; - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI1>; - status = "disabled"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,suniv-f1c100s-mmc", - "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = <23>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,suniv-f1c100s-mmc", - "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = <24>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@1c13000 { - compatible = "allwinner,suniv-f1c100s-musb"; - reg = <0x01c13000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = <26>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - allwinner,sram = <&otg_sram 1>; - status = "disabled"; - }; - - usbphy: phy@1c13400 { - compatible = "allwinner,suniv-f1c100s-usb-phy"; - reg = <0x01c13400 0x10>; - reg-names = "phy_ctrl"; - clocks = <&ccu CLK_USB_PHY0>; - clock-names = "usb0_phy"; - resets = <&ccu RST_USB_PHY0>; - reset-names = "usb0_reset"; - #phy-cells = <1>; - status = "disabled"; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,suniv-f1c100s-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - intc: interrupt-controller@1c20400 { - compatible = "allwinner,suniv-f1c100s-ic"; - reg = <0x01c20400 0x400>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,suniv-f1c100s-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = <38>, <39>, <40>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - }; - - /omit-if-no-ref/ - i2c0_pd_pins: i2c0-pd-pins { - pins = "PD0", "PD12"; - function = "i2c0"; - }; - - spi0_pc_pins: spi0-pc-pins { - pins = "PC0", "PC1", "PC2", "PC3"; - function = "spi0"; - }; - - uart0_pe_pins: uart0-pe-pins { - pins = "PE0", "PE1"; - function = "uart0"; - }; - - /omit-if-no-ref/ - uart1_pa_pins: uart1-pa-pins { - pins = "PA2", "PA3"; - function = "uart1"; - }; - }; - - i2c0: i2c@1c27000 { - compatible = "allwinner,suniv-f1c100s-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x01c27000 0x400>; - interrupts = <7>; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@1c27400 { - compatible = "allwinner,suniv-f1c100s-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x01c27400 0x400>; - interrupts = <8>; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@1c27800 { - compatible = "allwinner,suniv-f1c100s-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x01c27800 0x400>; - interrupts = <9>; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - timer@1c20c00 { - compatible = "allwinner,suniv-f1c100s-timer"; - reg = <0x01c20c00 0x90>; - interrupts = <13>, <14>, <15>; - clocks = <&osc24M>; - }; - - wdt: watchdog@1c20ca0 { - compatible = "allwinner,suniv-f1c100s-wdt", - "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = <16>; - clocks = <&osc32k>; - }; - - pwm: pwm@1c21000 { - compatible = "allwinner,suniv-f1c100s-pwm", - "allwinner,sun7i-a20-pwm"; - reg = <0x01c21000 0x400>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - ir: ir@1c22c00 { - compatible = "allwinner,suniv-f1c100s-ir", - "allwinner,sun6i-a31-ir"; - reg = <0x01c22c00 0x400>; - clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&ccu RST_BUS_IR>; - interrupts = <6>; - status = "disabled"; - }; - - lradc: lradc@1c23400 { - compatible = "allwinner,suniv-f1c100s-lradc", - "allwinner,sun8i-a83t-r-lradc"; - reg = <0x01c23400 0x400>; - interrupts = <22>; - status = "disabled"; - }; - - uart0: serial@1c25000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c25000 0x400>; - interrupts = <1>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@1c25400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c25400 0x400>; - interrupts = <2>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@1c25800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c25800 0x400>; - interrupts = <3>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/suniv-f1c200s-lctech-pi.dts b/arch/arm/dts/suniv-f1c200s-lctech-pi.dts deleted file mode 100644 index 2d2a3f026df..00000000000 --- a/arch/arm/dts/suniv-f1c200s-lctech-pi.dts +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Arm Ltd, - * based on work: - * Copyright 2022 Icenowy Zheng <uwu@icenowy.me> - */ - -/dts-v1/; -#include "suniv-f1c100s.dtsi" - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Lctech Pi F1C200s"; - compatible = "lctech,pi-f1c200s", "allwinner,suniv-f1c200s", - "allwinner,suniv-f1c100s"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_vcc3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - disable-wp; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pc_pins>; - status = "okay"; - - flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pa_pins>; - status = "okay"; -}; - -/* - * This is a Type-C socket, but CC1/2 are not connected, and VBUS is connected - * to Vin, which supplies the board. Host mode works (if the board is powered - * otherwise), but peripheral is probably the intention. - */ -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts b/arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts deleted file mode 100644 index 184c245041a..00000000000 --- a/arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Icenowy Zheng <uwu@icenowy.me> - */ - -/dts-v1/; -#include "suniv-f1c100s.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> - -/ { - model = "Popcorn Computer PopStick v1.1"; - compatible = "sourceparts,popstick-v1.1", "sourceparts,popstick", - "allwinner,suniv-f1c200s", "allwinner,suniv-f1c100s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>; /* PE6 */ - linux,default-trigger = "heartbeat"; - }; - }; - - reg_vcc3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&mmc0 { - cd-gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */ - bus-width = <4>; - disable-wp; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pc_pins>; - status = "okay"; - - flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pe_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index a84a57e5b41..76dd33c9477 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -267,31 +267,23 @@ struct sunxi_ccm_reg { #define CCM_CPU_AXI_DEFAULT_FACTORS 0x301 #ifdef CONFIG_MACH_SUN50I_H6 /* H6 */ -#define CCM_PLL6_DEFAULT 0xa0006300 -/* psi_ahb1_ahb2 bit field */ +#define CCM_PLL6_DEFAULT 0xa0006300 #define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000102 - -/* ahb3 bit field */ #define CCM_AHB3_DEFAULT 0x03000002 - -/* apb1 bit field */ #define CCM_APB1_DEFAULT 0x03000102 + #elif CONFIG_MACH_SUN50I_H616 /* H616 */ -#define CCM_PLL6_DEFAULT 0xa8003100 -/* psi_ahb1_ahb2 bit field */ +#define CCM_PLL6_DEFAULT 0xa8003100 #define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002 - -/* ahb3 bit field */ #define CCM_AHB3_DEFAULT 0x03000002 - -/* apb1 bit field */ #define CCM_APB1_DEFAULT 0x03000102 + #elif CONFIG_MACH_SUN8I_R528 /* R528 */ + #define CCM_PLL6_DEFAULT 0xe8216300 #define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002 -//#define CCM_AHB3_DEFAULT 0x03000002 #define CCM_APB1_DEFAULT 0x03000102 #endif diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index 2cc7c890449..45cc9912f94 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -8,6 +8,7 @@ #define _MAILBOX_S10_H_ /* user define Uboot ID */ +#include <linux/bitfield.h> #include <linux/bitops.h> #define MBOX_CLIENT_ID_UBOOT 0xB #define MBOX_ID_UBOOT 0x1 @@ -57,6 +58,9 @@ #define MBOX_RESP_CLIENT_GET(resp) \ (((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB) +#define MBOX_CFG_STATUS_MAJOR_ERR_MSK GENMASK(31, 16) +#define MBOX_CFG_STATUS_MINOR_ERR_MSK GENMASK(15, 0) + /* Response error list */ enum ALT_SDM_MBOX_RESP_CODE { /* CMD completed successfully, but check resp ARGS for any errors */ @@ -162,6 +166,220 @@ enum ALT_SDM_MBOX_RESP_CODE { #define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007 #define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008 +enum MBOX_CFGSTAT_MAJOR_ERR_CODE { + MBOX_CFGSTATE_MAJOR_ERR_UNK = -1, + MBOX_CFGSTATE_MAJOR_ERR_WRONG_BL31_VER = 0x0, + MBOX_CFGSTATE_MAJOR_ERR_STATE_CONFIG = 0x1000, + MBOX_CFGSTATE_MAJOR_ERR_BITSTREAM_ERR = 0xf001, + MBOX_CFGSTATE_MAJOR_ERR_EXT_HW_ACCESS_FAIL, + MBOX_CFGSTATE_MAJOR_ERR_BITSTREAM_CORRUPTION, + MBOX_CFGSTATE_MAJOR_ERR_INTERNAL_ERR, + MBOX_CFGSTATE_MAJOR_ERR_DEVICE_ERR, + MBOX_CFGSTATE_MAJOR_ERR_HPS_WDT, + MBOX_CFGSTATE_MAJOR_ERR_INTERNAL_UNKNOWN_ERR, + MBOX_CFGSTATE_MAJOR_ERR_SYSTEM_INIT_ERR, + MBOX_CFGSTATE_MAJOR_ERR_DECRYPTION_ERR, + MBOX_CFGSTATE_MAJOR_ERR_VERIFY_IMAGE_ERR = 0xf00b +}; + +enum MBOX_CFGSTAT_MINOR_ERR_CODE { + MBOX_CFGSTATE_MINOR_ERR_UNK = -1, + MBOX_CFGSTATE_MINOR_ERR_BASIC_ERR = 0x0, + MBOX_CFGSTATE_MINOR_ERR_CNT_RESP_ERR, + MBOX_CFGSTATE_MINOR_ERR_QSPI_DEV_ERR, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_INV, + MBOX_CFGSTATE_MINOR_ERR_BS_INCOMPATIBLE, + MBOX_CFGSTATE_MINOR_ERR_BS_INV_SHA, + MBOX_CFGSTATE_MINOR_ERR_ROUTE_FAIL, + MBOX_CFGSTATE_MINOR_ERR_GO_BIT_ALREADY_SET, + MBOX_CFGSTATE_MINOR_ERR_CPU_BLK_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACT_SKIP_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACT_MCAST_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACT_IND_SZ_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACT_IF_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACT_PIN_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACT_FUSEFLTR_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACT_GENERIC_FAIL, + MBOX_CFGSTATE_MINOR_ERR_DATA_STARVE_ERR, + MBOX_CFGSTATE_MINOR_ERR_CNT_RAM_INIT_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACT_SETUP_S4, + MBOX_CFGSTATE_MINOR_ERR_WIPE_DATA_STARVE, + MBOX_CFGSTATE_MINOR_ERR_FUSE_RD_FAIL, + MBOX_CFGSTATE_MINOR_ERR_AUTH_FAIL, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SHA_FAIL, + MBOX_CFGSTATE_MINOR_ERR_SKIP_DATA_RAM_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACT_FIXED_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACT_MCAST_FLTR_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACT_SECTOR_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACT_HASH_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACT_DECOMP_SETUP_FAIL, + MBOX_CFGSTATE_MINOR_ERR_INTERNAL_OS_ERR, + MBOX_CFGSTATE_MINOR_ERR_WIPE_FAIL, + MBOX_CFGSTATE_MINOR_ERR_CNOC_ERR, + MBOX_CFGSTATE_MINOR_ERR_PMF_RESUME_FAIL, + MBOX_CFGSTATE_MINOR_ERR_PMF_RUN_FAIL, + MBOX_CFGSTATE_MINOR_ERR_PMF_PAUSE_FAIL, + MBOX_CFGSTATE_MINOR_ERR_RET_INT_ASSERT_FAIL, + MBOX_CFGSTATE_MINOR_ERR_STATE_MACHINE_ERR, + MBOX_CFGSTATE_MINOR_ERR_CMF_TRANSITION_FAIL, + MBOX_CFGSTATE_MINOR_ERR_SHA_SETUP_FAIL, + MBOX_CFGSTATE_MINOR_ERR_WR_DMA_TIMEOUT, + MBOX_CFGSTATE_MINOR_ERR_MEM_ALLOC_FAIL, + MBOX_CFGSTATE_MINOR_ERR_SYNC_RD_FAIL, + MBOX_CFGSTATE_MINOR_ERR_CHK_CFG_REQ_FAIL, + MBOX_CFGSTATE_MINOR_ERR_HPS_CFG_REQ_FAIL, + MBOX_CFGSTATE_MINOR_ERR_CFG_HANDLE_ERR, + MBOX_CFGSTATE_MINOR_ERR_INV_ACTION_ITEM, + MBOX_CFGSTATE_MINOR_ERR_SKIP_DATA_PREBUF_ERR, + MBOX_CFGSTATE_MINOR_ERR_MBOX_TIMEOUT, + MBOX_CFGSTATE_MINOR_ERR_AVST_FIFO_OVERFLOW_ERR, + MBOX_CFGSTATE_MINOR_ERR_RD_DMA_TIMEOUT, + MBOX_CFGSTATE_MINOR_ERR_PMF_INIT_ERR, + MBOX_CFGSTATE_MINOR_ERR_PMF_SHUTDOWN_ERR, + MBOX_CFGSTATE_MINOR_ERR_BITSTREAM_INTERRUPTED, + MBOX_CFGSTATE_MINOR_ERR_FPGA_MBOX_WIPE_TIMEOUT, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_TYPE_INV, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_VERSION_INV, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_DEVICE_TYPE_INV, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_DESIGN_HASH_ERR, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_EXT_REF_CLK_ERR, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PWR_TBL_INV, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PIN_TBL_OFST_ERR, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PIN_TBL_INV, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_NO_PIN_TBL, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_CFG_CLK_PLL_FAILED, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_AS_CLK_FAILED, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_POF_ID_FAILED, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PW_TBL_OFST_ERR, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PP_TBL_OFST_ERR, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PP_TBL_INV, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SP_TBL_OFST_ERR, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SP_TBL_INV, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SU_TBL_OFST_ERR, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SU_TBL_INV, + MBOX_CFGSTATE_MINOR_ERR_MBOX_TASK_CRYPTO_SRC_CLR_ERR, + MBOX_CFGSTATE_MINOR_ERR_MBOX_TASK_EVENT_GROUP_POST_ERR, + MBOX_CFGSTATE_MINOR_ERR_TRNG_TEST_FAIL, + MBOX_CFGSTATE_MINOR_ERR_MBOX_TASK_ANTI_DOS_TMR_INIT_ERR, + MBOX_CFGSTATE_MINOR_ERR_OS_STK_CHK_ERR, + MBOX_CFGSTATE_MINOR_ERR_MBOX_TASK_INIT, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_COMPAT_ID_MATCH_ERR, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_COMPAT_ID_INV, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_AES_ECRYPT_CHK_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACT_KEY_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACT_KEY_CHALLENGE_FAIL, + MBOX_CFGSTATE_MINOR_ERR_MBOX_TASK_MSGQ_DEQUEUE_FAIL, + MBOX_CFGSTATE_MINOR_ERR_SECT_COMPAT_CHK_ERR, + MBOX_CFGSTATE_MINOR_ERR_SECT_COMPAT_UPDATE_ERR, + MBOX_CFGSTATE_MINOR_ERR_SECT_SEC_CHK_FAILED, + MBOX_CFGSTATE_MINOR_ERR_CNT_RAM_ECC_ERR_UNRECOVERABLE, + MBOX_CFGSTATE_MINOR_ERR_MBOX_REFORMAT_INPUT_ERR, + MBOX_CFGSTATE_MINOR_ERR_MBOX_REFORMAT_OUTPUT_ERR, + MBOX_CFGSTATE_MINOR_ERR_MBOX_WLBL_ERR, + MBOX_CFGSTATE_MINOR_ERR_MBOX_HOOK_CB_ERR, + MBOX_CFGSTATE_MINOR_ERR_CMF_RLD_DECOMP_LOAD_ERR, + MBOX_CFGSTATE_MINOR_ERR_CMF_RLD_DECOMP_RUN_ERR, + MBOX_CFGSTATE_MINOR_ERR_CNT_PERIPH_ECC_ERR_UNRECOVERABLE, + MBOX_CFGSTATE_MINOR_ERR_MAIN_SECT_ADDR_ERR, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SCRAMBLE_RATIO_CHK_FAIL, + MBOX_CFGSTATE_MINOR_ERR_TAMPER_EVENT_TRIGGERED, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_ANTI_TAMPER_TBL_INV, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_EXT_CLCK_MODE_DISALLOWED, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SEC_OPTIONS_INIT_FAIL, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_EN_USR_CAN_FUSE_INV, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_AS_DEVICE_NO_SGX_ERR, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_POF_ID_LIMIT_EXCEED_ERR, + MBOX_CFGSTATE_MINOR_ERR_PROVISION_CMF_INV_STATE, + MBOX_CFGSTATE_MINOR_ERR_PROVISION_CMF_FATAL_ERR, + MBOX_CFGSTATE_MINOR_ERR_PROVISION_CMF_SM_EXIT_FAIL, + MBOX_CFGSTATE_MINOR_ERR_PROVISION_CMF_SM_ENTRY_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACTION_DATA_UNSUPPORTED_CTX, + MBOX_CFGSTATE_MINOR_ERR_CMF_EXCEPTION, + MBOX_CFGSTATE_MINOR_ERR_ECC_INIT_FAIL, + MBOX_CFGSTATE_MINOR_ERR_DEFAULT_UNREGISTERED_ISR, + MBOX_CFGSTATE_MINOR_ERR_GENERAL_TIMEOUT, + MBOX_CFGSTATE_MINOR_ERR_ACT_OPERATION_CLK_FAIL, + MBOX_CFGSTATE_MINOR_ERR_ACT_VERIFY_HASH_FAIL, + MBOX_CFGSTATE_MINOR_ERR_CFG_STATE_UPDATE_ERR, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_READ_DDR_HASH_FAIL, + MBOX_CFGSTATE_MINOR_ERR_CVP_FLOW_ERR, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_KEYED_HASH_ERR, + MBOX_CFGSTATE_MINOR_ERR_CMF_DESC_BAD_JTAG_ID = 0x7a, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PMF_NOT_SUPPORTED = 0x7d, + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_ANTI_TAMPER_NOT_SUPPORTED, + MBOX_CFGSTATE_MINOR_ERR_ACT_RECOVERY_FAIL = 0x80, + MBOX_CFGSTATE_MINOR_ERR_COLD_RESET_CMF_CORRUPTED, + MBOX_CFGSTATE_MINOR_ERR_COLD_RESET_IO_HPS_CORRUPTED, + MBOX_CFGSTATE_MINOR_ERR_COLD_RESET_FPGA_CORRUPTED, + MBOX_CFGSTATE_MINOR_ERR_CRC_CHK_FAIL, + MBOX_CFGSTATE_MINOR_ERR_COMPAT_TBL_SFIXED_VALUE_INV, + MBOX_CFGSTATE_MINOR_ERR_FEATURE_EN_FUSE_NOT_BLOWN = 0x87, + MBOX_CFGSTATE_MINOR_ERR_UIB_REFCLK_MISSING, + MBOX_CFGSTATE_MINOR_ERR_UIB_REFCLK_TIMEOUT, + MBOX_CFGSTATE_MINOR_ERR_UIB_REFCLK_TIMEOUT_MISSING, + MBOX_CFGSTATE_MINOR_ERR_TRAMP_SYNC_BLCK_ERR = 0xc001, + MBOX_CFGSTATE_MINOR_ERR_TRAMP_SSBL_SHA_ERR, + MBOX_CFGSTATE_MINOR_ERR_TRAMP_BLCK0_SHA_MISMATCH_ERR, + MBOX_CFGSTATE_MINOR_ERR_TRAMP_BLCK0_AUTH_ERR, + MBOX_CFGSTATE_MINOR_ERR_TRAMP_TRAMP_LOAD_ERR, + MBOX_CFGSTATE_MINOR_ERR_TRAMP_CMF_SIZE_ERR, + MBOX_CFGSTATE_MINOR_ERR_TRAMP_TRANSITION_ERR, + MBOX_CFGSTATE_MINOR_ERR_TRAMP_SYNC_ERR, + MBOX_CFGSTATE_MINOR_ERR_TRAMP_LOAD_CERT_ERR, + MBOX_CFGSTATE_MINOR_ERR_TRAMP_LOAD_NOT_ALLOWED_ERR, + MBOX_CFGSTATE_MINOR_ERR_TRAMP_FUSE_ERR, + MBOX_CFGSTATE_MINOR_ERR_TRAMP_INPUT_BUFFER_ERR = 0xc00d, + MBOX_CFGSTATE_MINOR_ERR_TRAMP_CMF_TYPE_ERR, + MBOX_CFGSTATE_MINOR_ERR_TRAMP_QSPI_INDR_READ_START_ERR, + MBOX_CFGSTATE_MINOR_ERR_PMF_I2C_COMM_ERR = 0xc801, + MBOX_CFGSTATE_MINOR_ERR_PMF_TARGET_VOLTAGE_ERR, + MBOX_CFGSTATE_MINOR_ERR_PMF_HANDSHAKE_ERR, + MBOX_CFGSTATE_MINOR_ERR_PMF_ITD_OUT_OF_RANGE_ERR, + MBOX_CFGSTATE_MINOR_ERR_PMF_PWR_TABLE_ERR, + MBOX_CFGSTATE_MINOR_ERR_PMF_EFUSE_DECODE_ERR, + MBOX_CFGSTATE_MINOR_ERR_PMF_VCCL_PWRGOOD_ERR, + MBOX_CFGSTATE_MINOR_ERR_PMF_CLR_FAULTS_ERR, + MBOX_CFGSTATE_MINOR_ERR_PMF_VOUT_MODE_ERR, + MBOX_CFGSTATE_MINOR_ERR_PMF_PAGE_COMMAND_ERR, + MBOX_CFGSTATE_MINOR_ERR_PMF_VOUT_COMMAND_ERR, + MBOX_CFGSTATE_MINOR_ERR_PMF_READ_VOUT_ERR, + MBOX_CFGSTATE_MINOR_ERR_PMF_LTM4677_DEFAULT_ADC_CTRL_ERR, + MBOX_CFGSTATE_MINOR_ERR_PMF_FIRST_I2C_CMD_FAILED_ERR, + MBOX_CFGSTATE_MINOR_ERR_RSU_CMF_AUTH_ERR = 0xd001, + MBOX_CFGSTATE_MINOR_ERR_RSU_USER_AUTH_ERR, + MBOX_CFGSTATE_MINOR_ERR_RSU_CMF_DESC_SHA_MISMATCH, + MBOX_CFGSTATE_MINOR_ERR_RSU_POINTERS_NOT_FOUND_ERR, + MBOX_CFGSTATE_MINOR_ERR_RSU_QSPI_FREQ_CHANGE, + MBOX_CFGSTATE_MINOR_ERR_RSU_FACTORY_IMG_FAILED, + MBOX_CFGSTATE_MINOR_ERR_RSU_CMF_TYPE_ERR, + MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_SIG_DESC_ERR, + MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_INTERNAL_AUTH_ERR, + MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_COPY_FAILED, + MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_ERASE_FAILED, + MBOX_CFGSTATE_MINOR_ERR_RSU_RM_UCMF_FROM_CPB_FAILED, + MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_COMBINED_APP_AUTH_ERR, + MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_FLASH_ACCESS_ERR, + MBOX_CFGSTATE_MINOR_ERR_RSU_DCMF_DCIO_CORRUPTED, + MBOX_CFGSTATE_MINOR_ERR_RSU_DCMF_CPB0_CORRUPTED, + MBOX_CFGSTATE_MINOR_ERR_RSU_DCMF_CPB1_CORRUPTED, + MBOX_CFGSTATE_MINOR_ERR_RSU_PROVISION_COMPLETE, + MBOX_CFGSTATE_MINOR_ERR_RSU_PROVISION_ERR, + MBOX_CFGSTATE_MINOR_ERR_SYSINIT_EFUSE_INIT_FAIL = 0xe001, + MBOX_CFGSTATE_MINOR_ERR_SYSINIT_SEC_PROT_ERR, + MBOX_CFGSTATE_MINOR_ERR_SYSINIT_EFUSE_LCK_ERR, + MBOX_CFGSTATE_MINOR_ERR_SYSINIT_SEC_BBRAM_CLEAN_ERR, + MBOX_CFGSTATE_MINOR_ERR_SYSINIT_ENG_LOAD_DIMK_ERR, + MBOX_CFGSTATE_MINOR_ERR_SYSINIT_SEC_UKV_CLEAN_ERR, + MBOX_CFGSTATE_MINOR_ERR_SYSINIT_EFUSE_ZERO_ERR, + MBOX_CFGSTATE_MINOR_ERR_SYSINIT_ENG_LOAD_ERR, + MBOX_CFGSTATE_MINOR_ERR_SYSINIT_PERST_INIT_FAIL, + MBOX_CFGSTATE_MINOR_ERR_SYSINIT_DIMK_INIT_FAIL, + MBOX_CFGSTATE_MINOR_ERR_SYSINIT_PERST_SECONDARY_INIT_FAIL, + MBOX_CFGSTATE_MINOR_ERR_SYSINIT_BR_INFO_INIT_FAIL, + MBOX_CFGSTATE_MINOR_ERR_SYSINIT_CMF_DESC_FAIL, + MBOX_CFGSTATE_MINOR_ERR_SYSINIT_DRNG_INIT_FAIL +}; + #define RCF_SOFTFUNC_STATUS_CONF_DONE BIT(0) #define RCF_SOFTFUNC_STATUS_INIT_DONE BIT(1) #define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index a8009664fee..78eff247978 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -145,7 +145,7 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF -#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F +#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0xFF0F0F0F #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SYSMGR_SOC64_DDR_MODE_MSK BIT(0) diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 2b4f26040fe..b69bd3e47ec 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -88,6 +88,8 @@ static __always_inline int mbox_write_cmd_buffer(u32 *cin, u32 data, MBOX_WRITE_CMD_BUF(data, (*cin)++); *cin %= MBOX_CMD_BUFFER_SIZE; MBOX_WRITEL(*cin, MBOX_CIN); + if (is_cmdbuf_overflow) + *is_cmdbuf_overflow = 0; break; } timeout--; @@ -96,10 +98,6 @@ static __always_inline int mbox_write_cmd_buffer(u32 *cin, u32 data, if (!timeout) return -ETIMEDOUT; - /* Wait for the SDM to drain the FIFO command buffer */ - if (is_cmdbuf_overflow && *is_cmdbuf_overflow) - return mbox_wait_for_cmdbuf_empty(*cin); - return 0; } @@ -125,13 +123,11 @@ static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len, return ret; } - /* If SDM doorbell is not triggered after the last data is - * written into mailbox FIFO command buffer, trigger the - * SDM doorbell again to ensure SDM able to read the remaining - * data. + /* + * Always trigger the SDM doorbell at the end to ensure SDM able to read + * the remaining data. */ - if (!is_cmdbuf_overflow) - MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM); + MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM); return 0; } diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 8065161e61e..ba1b1541437 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -52,78 +52,76 @@ config DRAM_SUN50I_H616 like H616. if DRAM_SUN50I_H616 -config DRAM_SUN50I_H616_DX_ODT - hex "H616 DRAM DX ODT parameter" +config DRAM_SUNXI_DX_ODT + hex "DRAM DX ODT parameter" help DX ODT value from vendor DRAM settings. -config DRAM_SUN50I_H616_DX_DRI - hex "H616 DRAM DX DRI parameter" +config DRAM_SUNXI_DX_DRI + hex "DRAM DX DRI parameter" help DX DRI value from vendor DRAM settings. -config DRAM_SUN50I_H616_CA_DRI - hex "H616 DRAM CA DRI parameter" +config DRAM_SUNXI_CA_DRI + hex "DRAM CA DRI parameter" help CA DRI value from vendor DRAM settings. -config DRAM_SUN50I_H616_ODT_EN - hex "H616 DRAM ODT EN parameter" +config DRAM_SUNXI_ODT_EN + hex "DRAM ODT EN parameter" default 0x1 help ODT EN value from vendor DRAM settings. -config DRAM_SUN50I_H616_TPR0 - hex "H616 DRAM TPR0 parameter" +config DRAM_SUNXI_TPR0 + hex "DRAM TPR0 parameter" default 0x0 help TPR0 value from vendor DRAM settings. -config DRAM_SUN50I_H616_TPR2 - hex "H616 DRAM TPR2 parameter" +config DRAM_SUNXI_TPR2 + hex "DRAM TPR2 parameter" default 0x0 help TPR2 value from vendor DRAM settings. -config DRAM_SUN50I_H616_TPR6 - hex "H616 DRAM TPR6 parameter" +config DRAM_SUNXI_TPR6 + hex "DRAM TPR6 parameter" default 0x3300c080 help TPR6 value from vendor DRAM settings. -config DRAM_SUN50I_H616_TPR10 - hex "H616 DRAM TPR10 parameter" +config DRAM_SUNXI_TPR10 + hex "DRAM TPR10 parameter" help TPR10 value from vendor DRAM settings. It tells which features should be configured, like write leveling, read calibration, etc. -config DRAM_SUN50I_H616_TPR11 - hex "H616 DRAM TPR11 parameter" +config DRAM_SUNXI_TPR11 + hex "DRAM TPR11 parameter" default 0x0 help TPR11 value from vendor DRAM settings. -config DRAM_SUN50I_H616_TPR12 - hex "H616 DRAM TPR12 parameter" +config DRAM_SUNXI_TPR12 + hex "DRAM TPR12 parameter" default 0x0 help TPR12 value from vendor DRAM settings. choice - prompt "H616 PHY pin mapping selection" - default DRAM_SUN50I_H616_PHY_ADDR_MAP_0 + prompt "DRAM PHY pin mapping selection" + default DRAM_SUNXI_PHY_ADDR_MAP_0 -config DRAM_SUN50I_H616_PHY_ADDR_MAP_0 - bool "H313/H616/H618" +config DRAM_SUNXI_PHY_ADDR_MAP_0 + bool "DRAM PHY address map 0" help - The pin mapping selection used by the H313, H616, H618, and - possibly other dies which use the H616 DRAM controller. + This pin mapping selection should be used by the H313, H616, H618. -config DRAM_SUN50I_H616_PHY_ADDR_MAP_1 - bool "H700" +config DRAM_SUNXI_PHY_ADDR_MAP_1 + bool "DRAM PHY address map 1" help - The pin mapping selection used by the H700 and possibly other - dies which use the H616 DRAM controller. + This pin mapping selection should be used by the H700. endchoice endif @@ -279,6 +277,7 @@ config MACH_SUNIV select SUPPORT_SPL select SKIP_LOWLEVEL_INIT_ONLY select SPL_SKIP_LOWLEVEL_INIT_ONLY + imply OF_UPSTREAM config MACH_SUN4I bool "sun4i (Allwinner A10)" @@ -288,6 +287,7 @@ config MACH_SUN4I select SUPPORT_SPL imply SPL_SYS_I2C_LEGACY imply SYS_I2C_LEGACY + imply OF_UPSTREAM config MACH_SUN5I bool "sun5i (Allwinner A13)" @@ -297,6 +297,7 @@ config MACH_SUN5I select SUPPORT_SPL imply SPL_SYS_I2C_LEGACY imply SYS_I2C_LEGACY + imply OF_UPSTREAM config MACH_SUN6I bool "sun6i (Allwinner A31)" diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 863c4f1d7a8..b3554cc64bf 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -226,7 +226,7 @@ static void mctl_set_addrmap(const struct dram_config *config) mctl_ctl->addrmap[8] = 0x3F3F; } -#ifdef CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_1 +#ifdef CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1 static const u8 phy_init[] = { #ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333 0x08, 0x02, 0x12, 0x05, 0x15, 0x17, 0x18, 0x0b, @@ -245,7 +245,7 @@ static const u8 phy_init[] = { 0x18, 0x04, 0x1a #endif }; -#else /* CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_0 */ +#else /* CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_0 */ static const u8 phy_init[] = { #ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333 0x07, 0x0b, 0x02, 0x16, 0x0d, 0x0e, 0x14, 0x19, @@ -264,7 +264,7 @@ static const u8 phy_init[] = { 0x18, 0x03, 0x1a #endif }; -#endif /* CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_0 */ +#endif /* CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_0 */ #define MASK_BYTE(reg, nr) (((reg) >> ((nr) * 8)) & 0x1f) static void mctl_phy_configure_odt(const struct dram_para *para) { @@ -1409,16 +1409,16 @@ static const struct dram_para para = { #elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4) .type = SUNXI_DRAM_TYPE_LPDDR4, #endif - .dx_odt = CONFIG_DRAM_SUN50I_H616_DX_ODT, - .dx_dri = CONFIG_DRAM_SUN50I_H616_DX_DRI, - .ca_dri = CONFIG_DRAM_SUN50I_H616_CA_DRI, - .odt_en = CONFIG_DRAM_SUN50I_H616_ODT_EN, - .tpr0 = CONFIG_DRAM_SUN50I_H616_TPR0, - .tpr2 = CONFIG_DRAM_SUN50I_H616_TPR2, - .tpr6 = CONFIG_DRAM_SUN50I_H616_TPR6, - .tpr10 = CONFIG_DRAM_SUN50I_H616_TPR10, - .tpr11 = CONFIG_DRAM_SUN50I_H616_TPR11, - .tpr12 = CONFIG_DRAM_SUN50I_H616_TPR12, + .dx_odt = CONFIG_DRAM_SUNXI_DX_ODT, + .dx_dri = CONFIG_DRAM_SUNXI_DX_DRI, + .ca_dri = CONFIG_DRAM_SUNXI_CA_DRI, + .odt_en = CONFIG_DRAM_SUNXI_ODT_EN, + .tpr0 = CONFIG_DRAM_SUNXI_TPR0, + .tpr2 = CONFIG_DRAM_SUNXI_TPR2, + .tpr6 = CONFIG_DRAM_SUNXI_TPR6, + .tpr10 = CONFIG_DRAM_SUNXI_TPR10, + .tpr11 = CONFIG_DRAM_SUNXI_TPR11, + .tpr12 = CONFIG_DRAM_SUNXI_TPR12, }; unsigned long sunxi_dram_init(void) diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c index e7f492a13bc..9d24c8cd412 100644 --- a/board/mediatek/mt7622/mt7622_rfb.c +++ b/board/mediatek/mt7622/mt7622_rfb.c @@ -15,10 +15,3 @@ int board_init(void) { return 0; } - -int board_late_init(void) -{ - gd->env_valid = 1; //to load environment variable from persistent store - env_relocate(); - return 0; -} diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c index 9ff861cd3f4..ebdd5fb2abe 100644 --- a/board/phytec/common/k3/board.c +++ b/board/phytec/common/k3/board.c @@ -148,6 +148,12 @@ int board_late_init(void) case BOOT_DEVICE_ETHERNET: env_set("boot", "net"); break; + case BOOT_DEVICE_UART: + env_set("boot", "uart"); + break; + case BOOT_DEVICE_DFU: + env_set("boot", "usbdfu"); + break; }; if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) { diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index a0e098e010e..b199fdaa59b 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -7,6 +7,7 @@ #include <asm/arch/hardware.h> #include <asm/io.h> #include <spl.h> +#include <asm/arch/k3-ddr.h> #include <fdt_support.h> #include "phycore-ddr-data.h" @@ -97,6 +98,8 @@ int dram_init_banksize(void) { u8 ram_size; + memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS); + if (!IS_ENABLED(CONFIG_CPU_V7R)) return fdtdec_setup_memory_banksize(); @@ -178,17 +181,11 @@ int update_ddrss_timings(void) int do_board_detect(void) { - return update_ddrss_timings(); -} -#endif - -#if IS_ENABLED(CONFIG_XPL_BUILD) -void spl_perform_fixups(struct spl_image_info *spl_image) -{ + int ret; + void *fdt = (void *)gd->fdt_blob; + int bank; u64 start[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; - int bank; - int ret; dram_init(); dram_init_banksize(); @@ -198,7 +195,21 @@ void spl_perform_fixups(struct spl_image_info *spl_image) size[bank] = gd->bd->bi_dram[bank].size; } - ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, CONFIG_NR_DRAM_BANKS); + ret = fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS); + if (ret) + return ret; + + return update_ddrss_timings(); +} +#endif + +#if IS_ENABLED(CONFIG_XPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + if (IS_ENABLED(CONFIG_K3_DDRSS) && IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); + else + fixup_memory_node(spl_image); } #endif diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 824c322a0dc..c7a2205ed61 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -14,6 +14,7 @@ #include <dm.h> #include <env.h> #include <hang.h> +#include <i2c.h> #include <image.h> #include <init.h> #include <log.h> @@ -577,7 +578,6 @@ void sunxi_board_init(void) #ifdef CONFIG_AXP_DCDC1_VOLT power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); - power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); #endif #ifdef CONFIG_AXP_DCDC2_VOLT power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); @@ -586,6 +586,9 @@ void sunxi_board_init(void) #ifdef CONFIG_AXP_DCDC4_VOLT power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); #endif +#ifdef CONFIG_AXP_DCDC5_VOLT + power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); +#endif #ifdef CONFIG_AXP_ALDO1_VOLT power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); @@ -876,6 +879,27 @@ static void bluetooth_dt_fixup(void *blob) "local-bd-address", bdaddr, ETH_ALEN, 1); } +#define PINEPHONE_LIS3MDL_I2C_ADDR 0x1e +#define PINEPHONE_LIS3MDL_I2C_BUS 1 /* I2C1 */ + +static void board_dt_fixup(void *blob) +{ + struct udevice *bus, *dev; + + if (IS_ENABLED(CONFIG_PINEPHONE_DT_SELECTION) && + !fdt_node_check_compatible(blob, 0, "pine64,pinephone-1.2")) { + if (!uclass_get_device_by_seq(UCLASS_I2C, + PINEPHONE_LIS3MDL_I2C_BUS, + &bus)) { + dm_i2c_probe(bus, PINEPHONE_LIS3MDL_I2C_ADDR, 0, &dev); + fdt_set_status_by_compatible(blob, "st,lis3mdl-magn", + dev ? FDT_STATUS_OKAY : FDT_STATUS_DISABLED); + fdt_set_status_by_compatible(blob, "voltafield,af8133j", + dev ? FDT_STATUS_DISABLED : FDT_STATUS_OKAY); + } + } +} + int ft_board_setup(void *blob, struct bd_info *bd) { int __maybe_unused r; @@ -889,6 +913,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_ethernet(blob); bluetooth_dt_fixup(blob); + board_dt_fixup(blob); #ifdef CONFIG_VIDEO_DT_SIMPLEFB r = sunxi_simplefb_setup(blob); diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index 57e91d0f017..96e3d19038b 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-olinuxino-lime" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=480 diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index 841fe0d3f09..5a10fce7273 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a10s-olinuxino-micro" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index befe6d86b25..5001ce9ce52 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a13-olinuxino-micro" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index 689ea533ee9..bc0fc0efe0a 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a13-olinuxino" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index 1087512235a..e38ecf56929 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76" +# CONFIG_OF_UPSTREAM is not set CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig index 7d81f12f766..520939538f8 100644 --- a/configs/Auxtek-T003_defconfig +++ b/configs/Auxtek-T003_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a10s-auxtek-t003" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig index 4c7154b04c4..8b3a9eac788 100644 --- a/configs/Auxtek-T004_defconfig +++ b/configs/Auxtek-T004_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a10s-auxtek-t004" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig index cd9bdbfd36f..c220d269ab6 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-r8-chip" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index 59df41a1502..05874125f4b 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun5i-gr8-chip-pro" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-gr8-chip-pro" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index 02b3e69584f..40f52d1a8d3 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-chuwi-v7-cw0825" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig index ab3f65ad667..9fc57c23f43 100644 --- a/configs/Cubieboard_defconfig +++ b/configs/Cubieboard_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-cubieboard" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=480 diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig index 4bd3b569392..18b1cfaa811 100644 --- a/configs/Empire_electronix_d709_defconfig +++ b/configs/Empire_electronix_d709_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a13-empire-electronix-d709" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig index 18873dba340..abaf386563e 100644 --- a/configs/Empire_electronix_m712_defconfig +++ b/configs/Empire_electronix_m712_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-m712" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a13-empire-electronix-m712" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index 482e0fb7a83..541f98db9e1 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-hyundai-a7hd" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_EMR1=4 diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig index 49dcfa098ee..0e1a7780c3d 100644 --- a/configs/Linksprite_pcDuino_defconfig +++ b/configs/Linksprite_pcDuino_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-pcduino" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_USB1_VBUS_PIN="" diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig index 3c5312d8824..c7608ed0fdc 100644 --- a/configs/Marsboard_A10_defconfig +++ b/configs/Marsboard_A10_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-marsboard" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_AHCI=y diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index 9ac2e4839d9..93e73ebe3f1 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-a1000" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_VIDEO_VGA=y diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index e8bc1485766..e64352b4b6a 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-mini-xplus" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_USB0_VBUS_PIN="PB9" diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index 88a082c0567..d74ef2127d9 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a13-utoo-p66" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig index 9e9bddb7649..9f6d2a78f48 100644 --- a/configs/Wobo_i5_defconfig +++ b/configs/Wobo_i5_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a10s-wobo-i5" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 diff --git a/configs/anbernic_rg35xx_h700_defconfig b/configs/anbernic_rg35xx_h700_defconfig index cd3d6bfba06..c5c40a158d3 100644 --- a/configs/anbernic_rg35xx_h700_defconfig +++ b/configs/anbernic_rg35xx_h700_defconfig @@ -2,16 +2,16 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h700-anbernic-rg35xx-2024" CONFIG_SPL=y -CONFIG_DRAM_SUN50I_H616_DX_ODT=0x08080808 -CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e -CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e -CONFIG_DRAM_SUN50I_H616_ODT_EN=0x7887bbbb -CONFIG_DRAM_SUN50I_H616_TPR2=0x1 -CONFIG_DRAM_SUN50I_H616_TPR6=0x40808080 -CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6633 -CONFIG_DRAM_SUN50I_H616_TPR11=0x1b1f1e1c -CONFIG_DRAM_SUN50I_H616_TPR12=0x06060606 -CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_1=y +CONFIG_DRAM_SUNXI_DX_ODT=0x08080808 +CONFIG_DRAM_SUNXI_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUNXI_CA_DRI=0x0e0e +CONFIG_DRAM_SUNXI_ODT_EN=0x7887bbbb +CONFIG_DRAM_SUNXI_TPR2=0x1 +CONFIG_DRAM_SUNXI_TPR6=0x40808080 +CONFIG_DRAM_SUNXI_TPR10=0x402f6633 +CONFIG_DRAM_SUNXI_TPR11=0x1b1f1e1c +CONFIG_DRAM_SUNXI_TPR12=0x06060606 +CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1=y CONFIG_MACH_SUN50I_H616=y CONFIG_SUNXI_DRAM_H616_LPDDR4=y CONFIG_DRAM_CLK=672 diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig index 4a58146e614..c93fa34eb57 100644 --- a/configs/arbel_evb_defconfig +++ b/configs/arbel_evb_defconfig @@ -80,6 +80,10 @@ CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_PINCTRL_NPCM8XX=y CONFIG_DM_REGULATOR=y +CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ADDR=0 CONFIG_DM_REGULATOR_NPCM8XX=y CONFIG_RNG_NPCM=y CONFIG_DM_SERIAL=y diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index b89dd8ea62b..c76f36ec37e 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-ba10-tvbox" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=384 diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig index f54a83d929d..b0604302c97 100644 --- a/configs/difrnce_dit4350_defconfig +++ b/configs/difrnce_dit4350_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-difrnce-dit4350" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a13-difrnce-dit4350" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig index f5ff69d7d63..06a79c935d7 100644 --- a/configs/dserve_dsrv9703c_defconfig +++ b/configs/dserve_dsrv9703c_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-dserve-dsrv9703c" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-dserve-dsrv9703c" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_USB0_VBUS_PIN="PB9" diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig index 5cc1a1d57f4..5ab210b345b 100644 --- a/configs/iNet_3F_defconfig +++ b/configs/iNet_3F_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f" +# CONFIG_OF_UPSTREAM is not set CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig index 38b20109a57..415575cc228 100644 --- a/configs/iNet_3W_defconfig +++ b/configs/iNet_3W_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w" +# CONFIG_OF_UPSTREAM is not set CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig index 2c8ecb51de0..42c9da9f947 100644 --- a/configs/iNet_86VS_defconfig +++ b/configs/iNet_86VS_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs" +# CONFIG_OF_UPSTREAM is not set CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig index f81120b1197..68a6df50e42 100644 --- a/configs/inet1_defconfig +++ b/configs/inet1_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-inet1" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig index d5d2dc32c93..a5414e2c502 100644 --- a/configs/inet97fv2_defconfig +++ b/configs/inet97fv2_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet97fv2" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-inet97fv2" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig index e4da6c14d04..48b20c0eefa 100644 --- a/configs/inet98v_rev2_defconfig +++ b/configs/inet98v_rev2_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-98v-rev2" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a13-inet-98v-rev2" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig index 4485f930236..5b0cda10f3b 100644 --- a/configs/inet9f_rev03_defconfig +++ b/configs/inet9f_rev03_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet9f-rev03" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-inet9f-rev03" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index c99be7cea4e..b41c2cf3c05 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-jesurun-q5" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=312 diff --git a/configs/lctech_pi_f1c200s_defconfig b/configs/lctech_pi_f1c200s_defconfig index e1e8d3aaaa3..1588b3b4955 100644 --- a/configs/lctech_pi_f1c200s_defconfig +++ b/configs/lctech_pi_f1c200s_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c200s-lctech-pi" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/suniv-f1c200s-lctech-pi" CONFIG_SPL=y CONFIG_MACH_SUNIV=y CONFIG_DRAM_CLK=156 diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig index d59affb0d9c..051b1901f20 100644 --- a/configs/licheepi_nano_defconfig +++ b/configs/licheepi_nano_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/suniv-f1c100s-licheepi-nano" CONFIG_SPL=y CONFIG_MACH_SUNIV=y CONFIG_DRAM_CLK=156 diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig index 21f7a6e535d..d3d7402f828 100644 --- a/configs/mk802_a10s_defconfig +++ b/configs/mk802_a10s_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a10s-mk802" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig index 416565e5af2..8ebd5e9cbc3 100644 --- a/configs/mk802_defconfig +++ b/configs/mk802_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-mk802" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_USB2_VBUS_PIN="PH12" diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig index 965a9cd5c4b..c56a4c7c6a0 100644 --- a/configs/mk802ii_defconfig +++ b/configs/mk802ii_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-mk802ii" CONFIG_SPL=y CONFIG_MACH_SUN4I=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig index 4acf521e7fd..f69be08cc3f 100644 --- a/configs/mt7629_rfb_defconfig +++ b/configs/mt7629_rfb_defconfig @@ -18,7 +18,7 @@ CONFIG_SPL_STACK=0x106000 CONFIG_SPL_TEXT_BASE=0x201000 CONFIG_SPL_STACK_R=y CONFIG_SYS_BOOTM_LEN=0x4000000 -CONFIG_SYS_LOAD_ADDR=0x42007f1c +CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_SPL_PAYLOAD="u-boot-lzma.img" CONFIG_BUILD_TARGET="u-boot-mtk.bin" CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin" diff --git a/configs/mt7988_rfb_defconfig b/configs/mt7988_rfb_defconfig index 4d7454d5d39..eebf7fb43ba 100644 --- a/configs/mt7988_rfb_defconfig +++ b/configs/mt7988_rfb_defconfig @@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb" CONFIG_TARGET_MT7988=y -CONFIG_SYS_LOAD_ADDR=0x46000000 +CONFIG_SYS_LOAD_ADDR=0x44000000 CONFIG_DEBUG_UART_BASE=0x11000000 CONFIG_DEBUG_UART_CLOCK=40000000 CONFIG_DEBUG_UART=y diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index f60ee7375da..f2265ea5179 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -2,10 +2,10 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h616-orangepi-zero2" CONFIG_SPL=y -CONFIG_DRAM_SUN50I_H616_DX_ODT=0x08080808 -CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e -CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e -CONFIG_DRAM_SUN50I_H616_TPR10=0xf83438 +CONFIG_DRAM_SUNXI_DX_ODT=0x08080808 +CONFIG_DRAM_SUNXI_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUNXI_CA_DRI=0x0e0e +CONFIG_DRAM_SUNXI_TPR10=0xf83438 CONFIG_MACH_SUN50I_H616=y CONFIG_SUNXI_DRAM_H616_DDR3_1333=y CONFIG_USB1_VBUS_PIN="PC16" diff --git a/configs/orangepi_zero2w_defconfig b/configs/orangepi_zero2w_defconfig index cbb702d85b3..ec030f32403 100644 --- a/configs/orangepi_zero2w_defconfig +++ b/configs/orangepi_zero2w_defconfig @@ -2,14 +2,14 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h618-orangepi-zero2w" CONFIG_SPL=y -CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707 -CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e -CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e -CONFIG_DRAM_SUN50I_H616_ODT_EN=0xaaaaeeee -CONFIG_DRAM_SUN50I_H616_TPR6=0x48808080 -CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663 -CONFIG_DRAM_SUN50I_H616_TPR11=0x26262524 -CONFIG_DRAM_SUN50I_H616_TPR12=0x100f100f +CONFIG_DRAM_SUNXI_DX_ODT=0x07070707 +CONFIG_DRAM_SUNXI_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUNXI_CA_DRI=0x0e0e +CONFIG_DRAM_SUNXI_ODT_EN=0xaaaaeeee +CONFIG_DRAM_SUNXI_TPR6=0x48808080 +CONFIG_DRAM_SUNXI_TPR10=0x402f6663 +CONFIG_DRAM_SUNXI_TPR11=0x26262524 +CONFIG_DRAM_SUNXI_TPR12=0x100f100f CONFIG_MACH_SUN50I_H616=y CONFIG_SUNXI_DRAM_H616_LPDDR4=y CONFIG_DRAM_CLK=792 diff --git a/configs/orangepi_zero3_defconfig b/configs/orangepi_zero3_defconfig index 4e9b0ec4d33..63f9a735378 100644 --- a/configs/orangepi_zero3_defconfig +++ b/configs/orangepi_zero3_defconfig @@ -2,14 +2,14 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h618-orangepi-zero3" CONFIG_SPL=y -CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707 -CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e -CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e -CONFIG_DRAM_SUN50I_H616_ODT_EN=0xaaaaeeee -CONFIG_DRAM_SUN50I_H616_TPR6=0x44000000 -CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663 -CONFIG_DRAM_SUN50I_H616_TPR11=0x24242624 -CONFIG_DRAM_SUN50I_H616_TPR12=0x0f0f100f +CONFIG_DRAM_SUNXI_DX_ODT=0x07070707 +CONFIG_DRAM_SUNXI_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUNXI_CA_DRI=0x0e0e +CONFIG_DRAM_SUNXI_ODT_EN=0xaaaaeeee +CONFIG_DRAM_SUNXI_TPR6=0x44000000 +CONFIG_DRAM_SUNXI_TPR10=0x402f6663 +CONFIG_DRAM_SUNXI_TPR11=0x24242624 +CONFIG_DRAM_SUNXI_TPR12=0x0f0f100f CONFIG_MACH_SUN50I_H616=y CONFIG_SUNXI_DRAM_H616_LPDDR4=y CONFIG_DRAM_CLK=792 diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index a856e69d88c..c5ddcd72852 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -21,7 +21,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_TEXT_BASE=0x43c00000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index bc450004722..3027a94b0d1 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -72,6 +72,7 @@ CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_ASKENV=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -88,6 +89,8 @@ CONFIG_OF_OVERLAY_LIST="ti/k3-am6xx-phycore-disable-spi-nor ti/k3-am6xx-phycore- CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_MMC_ENV_DEV=1 @@ -112,11 +115,9 @@ CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y -CONFIG_DM_PCA953X=y -CONFIG_SPL_DM_PCA953X=y +CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig index 9d39204a439..99aa29622ba 100644 --- a/configs/pinephone_defconfig +++ b/configs/pinephone_defconfig @@ -10,7 +10,10 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_PINEPHONE_DT_SELECTION=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x61000000 CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.2" +CONFIG_SYS_I2C_MVTWSI=y CONFIG_LED_STATUS=y CONFIG_LED_STATUS_GPIO=y CONFIG_LED_STATUS0=y diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig index a62c9f8fa37..330c97fd6dc 100644 --- a/configs/pov_protab2_ips9_defconfig +++ b/configs/pov_protab2_ips9_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pov-protab2-ips9" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-pov-protab2-ips9" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig index 36252e5f89a..93a257853b3 100644 --- a/configs/q8_a13_tablet_defconfig +++ b/configs/q8_a13_tablet_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-q8-tablet" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a13-q8-tablet" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=384 diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig index 8875a09b2c9..0c9f6197c2c 100644 --- a/configs/r7-tv-dongle_defconfig +++ b/configs/r7-tv-dongle_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a10s-r7-tv-dongle" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=384 diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig index 3fee7c2e50c..4f3d0ec7443 100644 --- a/configs/sunxi_Gemei_G9_defconfig +++ b/configs/sunxi_Gemei_G9_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-gemei-g9" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 diff --git a/configs/tanix_tx1_defconfig b/configs/tanix_tx1_defconfig index 706306b1444..28cf9513c30 100644 --- a/configs/tanix_tx1_defconfig +++ b/configs/tanix_tx1_defconfig @@ -2,14 +2,14 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h313-tanix-tx1" CONFIG_SPL=y -CONFIG_DRAM_SUN50I_H616_DX_ODT=0x06060606 -CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0d0d0d0d -CONFIG_DRAM_SUN50I_H616_CA_DRI=0x1919 -CONFIG_DRAM_SUN50I_H616_ODT_EN=0x9988eeee -CONFIG_DRAM_SUN50I_H616_TPR6=0x2fb08080 -CONFIG_DRAM_SUN50I_H616_TPR10=0x402f4469 -CONFIG_DRAM_SUN50I_H616_TPR11=0x0e0f0d0d -CONFIG_DRAM_SUN50I_H616_TPR12=0x11131213 +CONFIG_DRAM_SUNXI_DX_ODT=0x06060606 +CONFIG_DRAM_SUNXI_DX_DRI=0x0d0d0d0d +CONFIG_DRAM_SUNXI_CA_DRI=0x1919 +CONFIG_DRAM_SUNXI_ODT_EN=0x9988eeee +CONFIG_DRAM_SUNXI_TPR6=0x2fb08080 +CONFIG_DRAM_SUNXI_TPR10=0x402f4469 +CONFIG_DRAM_SUNXI_TPR11=0x0e0f0d0d +CONFIG_DRAM_SUNXI_TPR12=0x11131213 CONFIG_MACH_SUN50I_H616=y CONFIG_SUNXI_DRAM_H616_LPDDR3=y CONFIG_R_I2C_ENABLE=y diff --git a/configs/transpeed-8k618-t_defconfig b/configs/transpeed-8k618-t_defconfig index 1d5a0c264b3..221614762e8 100644 --- a/configs/transpeed-8k618-t_defconfig +++ b/configs/transpeed-8k618-t_defconfig @@ -2,13 +2,13 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h618-transpeed-8k618-t" CONFIG_SPL=y -CONFIG_DRAM_SUN50I_H616_DX_ODT=0x03030303 -CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e -CONFIG_DRAM_SUN50I_H616_CA_DRI=0x1f12 -CONFIG_DRAM_SUN50I_H616_TPR0=0xc0001002 -CONFIG_DRAM_SUN50I_H616_TPR10=0x2f1107 -CONFIG_DRAM_SUN50I_H616_TPR11=0xddddcccc -CONFIG_DRAM_SUN50I_H616_TPR12=0xeddc7665 +CONFIG_DRAM_SUNXI_DX_ODT=0x03030303 +CONFIG_DRAM_SUNXI_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUNXI_CA_DRI=0x1f12 +CONFIG_DRAM_SUNXI_TPR0=0xc0001002 +CONFIG_DRAM_SUNXI_TPR10=0x2f1107 +CONFIG_DRAM_SUNXI_TPR11=0xddddcccc +CONFIG_DRAM_SUNXI_TPR12=0xeddc7665 CONFIG_MACH_SUN50I_H616=y CONFIG_SUNXI_DRAM_H616_DDR3_1333=y CONFIG_DRAM_CLK=648 diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig index f876cc91f6e..bd9b611d6f5 100644 --- a/configs/x96_mate_defconfig +++ b/configs/x96_mate_defconfig @@ -2,13 +2,13 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h616-x96-mate" CONFIG_SPL=y -CONFIG_DRAM_SUN50I_H616_DX_ODT=0x03030303 -CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e -CONFIG_DRAM_SUN50I_H616_CA_DRI=0x1c12 -CONFIG_DRAM_SUN50I_H616_TPR0=0xc0000c05 -CONFIG_DRAM_SUN50I_H616_TPR10=0x2f0007 -CONFIG_DRAM_SUN50I_H616_TPR11=0xffffdddd -CONFIG_DRAM_SUN50I_H616_TPR12=0xfedf7557 +CONFIG_DRAM_SUNXI_DX_ODT=0x03030303 +CONFIG_DRAM_SUNXI_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUNXI_CA_DRI=0x1c12 +CONFIG_DRAM_SUNXI_TPR0=0xc0000c05 +CONFIG_DRAM_SUNXI_TPR10=0x2f0007 +CONFIG_DRAM_SUNXI_TPR11=0xffffdddd +CONFIG_DRAM_SUNXI_TPR12=0xfedf7557 CONFIG_MACH_SUN50I_H616=y CONFIG_SUNXI_DRAM_H616_DDR3_1333=y CONFIG_R_I2C_ENABLE=y diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 97073918006..60814652322 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -359,6 +359,7 @@ static const struct mtk_parent infra_pcie_parents[] = { .id = _id, .mux_reg = (_reg) + 0x8, \ .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ + .gate_shift = -1, .upd_shift = -1, \ .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ } diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c index c5cc77243d0..f9d6f9c1749 100644 --- a/drivers/clk/mediatek/clk-mt7986.c +++ b/drivers/clk/mediatek/clk-mt7986.c @@ -366,6 +366,7 @@ static const struct mtk_parent infra_pcie_parents[] = { .id = _id, .mux_reg = (_reg) + 0x8, \ .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ + .gate_shift = -1, .upd_shift = -1, \ .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ } diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c index 8f4e8f4e8c9..73fd9c6bea6 100644 --- a/drivers/clk/mediatek/clk-mt7988.c +++ b/drivers/clk/mediatek/clk-mt7988.c @@ -485,6 +485,7 @@ static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = { .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \ .mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .parent = _parents, \ + .gate_shift = -1, .upd_shift = -1, \ .num_parents = ARRAY_SIZE(_parents), \ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ } diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c index 5a65bd98779..5fe4dbdfd32 100644 --- a/drivers/fpga/intel_sdm_mb.c +++ b/drivers/fpga/intel_sdm_mb.c @@ -22,18 +22,630 @@ #define BITSTREAM_CHUNK_SIZE 0xFFFF0 #define RECONFIG_STATUS_POLL_RETRY_MAX 100 +static const struct mbox_cfgstat_major_err { + int err_no; + const char *error_name; +} mbox_cfgstat_major_err[] = { + {MBOX_CFGSTATE_MAJOR_ERR_WRONG_BL31_VER, + "Please check ATF BL31 version, require v2.11 above to print more error status."}, + {MBOX_CFGSTATE_MAJOR_ERR_STATE_CONFIG, + "Mailbox in configuration state."}, + {MBOX_CFGSTATE_MAJOR_ERR_BITSTREAM_ERR, + "Bitstream Invalid."}, + {MBOX_CFGSTATE_MAJOR_ERR_EXT_HW_ACCESS_FAIL, + "External HW access failure."}, + {MBOX_CFGSTATE_MAJOR_ERR_BITSTREAM_CORRUPTION, + "Bitstream valid but corrupted. Bitstream corruption error when reading the bitstream from the source." + }, + {MBOX_CFGSTATE_MAJOR_ERR_INTERNAL_ERR, + "Bitstream element not understood. Internal error."}, + {MBOX_CFGSTATE_MAJOR_ERR_DEVICE_ERR, + "Unable to communicate on internal configuration network. Device operation error."}, + {MBOX_CFGSTATE_MAJOR_ERR_HPS_WDT, + "HPS Watchdog Timer. HPS watchdog timeout failure."}, + {MBOX_CFGSTATE_MAJOR_ERR_INTERNAL_UNKNOWN_ERR, + "Other unknown error occurred"}, + {MBOX_CFGSTATE_MAJOR_ERR_SYSTEM_INIT_ERR, + "Error before main CMF start. System initialization failure."}, + {MBOX_CFGSTATE_MAJOR_ERR_DECRYPTION_ERR, + "Decryption Error."}, + {MBOX_CFGSTATE_MAJOR_ERR_VERIFY_IMAGE_ERR, + "Verify image error."}, + {MBOX_CFGSTATE_MAJOR_ERR_UNK, + "Unknown error number at major field!"} +}; + +#define MBOX_CFGSTAT_MAJOR_ERR_MAX ARRAY_SIZE(mbox_cfgstat_major_err) + +static const struct mbox_cfgstat_minor_err { + int err_no; + const char *error_name; +} mbox_cfgstat_minor_err[] = { + {MBOX_CFGSTATE_MINOR_ERR_BASIC_ERR, + "Catchall Error."}, + {MBOX_CFGSTATE_MINOR_ERR_CNT_RESP_ERR, + "Detected an error during configuration. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_QSPI_DEV_ERR, + "QSPI Device related error. Detected QSPI device related error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_INV, + "Bitstream section main descriptor invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_BS_INCOMPATIBLE, + "Bistream not compatible with device. Detected an error during configuration due to incompatible bitstream with the device." + }, + {MBOX_CFGSTATE_MINOR_ERR_BS_INV_SHA, + "Bitstream invalid SHA setting. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_ROUTE_FAIL, + "Bitstream processing route failed. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_GO_BIT_ALREADY_SET, + "Failed DMA during bitstream processing. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_CPU_BLK_FAIL, + "Failed DMA during bitstream processing. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_ACT_SKIP_FAIL, + "Skip action failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_MCAST_FAIL, + "Multicast Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_IND_SZ_FAIL, + "Index Size Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_IF_FAIL, + "If Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_PIN_FAIL, + "Pin Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_FUSEFLTR_FAIL, + "Fuse Filter Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_GENERIC_FAIL, + "Other Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_DATA_STARVE_ERR, + "Datapath starved. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_CNT_RAM_INIT_FAIL, + "CNT/SSM RAM Initialization Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_SETUP_S4, + "S4 Setup Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_WIPE_DATA_STARVE, + "Datapath starved during wipe. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_FUSE_RD_FAIL, + "eFUSE Read Failure. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_AUTH_FAIL, + "Authentication Failure. Detected a bitstream authentication error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SHA_FAIL, + "Bitstream Section Main Descriptor Hash Check Failed. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_SKIP_DATA_RAM_FAIL, + "Skip Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_FIXED_FAIL, + "Fixed Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_MCAST_FLTR_FAIL, + "Multicast Filter Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_SECTOR_FAIL, + "Sector Group Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_HASH_FAIL, + "Hash Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_DECOMP_SETUP_FAIL, + "Decompression Setup Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_INTERNAL_OS_ERR, + "RTOS Error. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_WIPE_FAIL, + "Wipe Bitstream Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_CNOC_ERR, + "Internal Configuration Network Failure. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_RESUME_FAIL, + "Power Management Firmware Failed Resume. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_RUN_FAIL, + "Power Management Firmware Failed Run. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_PMF_PAUSE_FAIL, + "Power Management Firmware Failed Pause. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_RET_INT_ASSERT_FAIL, + "Internal Configuration Network Return Interrupt Failure. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_STATE_MACHINE_ERR, + "Configuration State Machine Error. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_CMF_TRANSITION_FAIL, + "Error during CMF load/reload. Detected a firmware transition error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_SHA_SETUP_FAIL, + "Error setting up SHA engine. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_WR_DMA_TIMEOUT, + "Write DMA timed out. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MEM_ALLOC_FAIL, + "Out of Memory. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_SYNC_RD_FAIL, + "Sync Block Read Fail. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_CHK_CFG_REQ_FAIL, + "Configuration Status Check Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_HPS_CFG_REQ_FAIL, + "HPS Configuration Request Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_CFG_HANDLE_ERR, + "Driver Handle Error. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_INV_ACTION_ITEM, + "Bistream contains invalid action. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_SKIP_DATA_PREBUF_ERR, + "Prebuffer Error during Skip Action. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_TIMEOUT, + "Mailbox Processing Timeout. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_AVST_FIFO_OVERFLOW_ERR, + "AVST FIFO Overflow. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_RD_DMA_TIMEOUT, + "Read DMA timed out. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_PMF_INIT_ERR, + "Power Management Firmware Initialization Error. Detected a PMBUS error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_SHUTDOWN_ERR, + "Power Management Firmware Shutdown Error. Detected a PMBUS error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_BITSTREAM_INTERRUPTED, + "Bitstream processing was interrupted by another event. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_FPGA_MBOX_WIPE_TIMEOUT, + "Mailbox Wipe Timeout. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_TYPE_INV, + "Bitstream Section Main Descriptor Type is Invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_VERSION_INV, + "Bitstream Section Main Descriptor Version is Invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_DEVICE_TYPE_INV, + "Bitstream Section Main Descriptor Device is Invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_DESIGN_HASH_ERR, + "Bitstream Section Main Descriptor Hash Mismatch. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_EXT_REF_CLK_ERR, + "Bitstream Section Main Descriptor External Clock Setting Invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PWR_TBL_INV, + "Bitstream Section Main Descriptor Power Table is invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PIN_TBL_OFST_ERR, + "Bitstream Section Main Descriptor Offset to Pin Table is Invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PIN_TBL_INV, + "Bitstream Section Main Descriptor Pin Table is Invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_NO_PIN_TBL, + "Bitstream Section Main Descriptor missing pin table. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_CFG_CLK_PLL_FAILED, + "Bitstream Section Main Descriptor PLL setting failure. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_AS_CLK_FAILED, + "Bitstream Section Main Descriptor QSPI Clock Setting Failure. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_POF_ID_FAILED, + "Bitstream Section Main Descriptor POF ID not valid. Detected an incompatible PR bitstream during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PW_TBL_OFST_ERR, + "code not used."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PP_TBL_OFST_ERR, + "code not used."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PP_TBL_INV, + "code not used."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SP_TBL_OFST_ERR, + "code not used."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SP_TBL_INV, + "code not used."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SU_TBL_OFST_ERR, + "code not used."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SU_TBL_INV, + "code not used."}, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_TASK_CRYPTO_SRC_CLR_ERR, + "Mailbox Source Failed to Clear. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_TASK_EVENT_GROUP_POST_ERR, + "Mailbox Event Post Error. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_TRNG_TEST_FAIL, + "True Random Number Generator Failed Test. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_TASK_ANTI_DOS_TMR_INIT_ERR, + "Mailbox Anti-DOS Timer failed initialization. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_OS_STK_CHK_ERR, + "RTOS Stack Check Error. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_TASK_INIT, + "Mailbox Task failed to initialize. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_COMPAT_ID_MATCH_ERR, + "Bitstream Section Main Descriptor Compatibility ID mismatch. Detected a bitstream error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_COMPAT_ID_INV, + "Bitstream Section Main Descriptor Compatibility ID not Valid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_AES_ECRYPT_CHK_FAIL, + "Bitstream Section Main Descriptor AES Test Failed. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_ACT_KEY_FAIL, + "Key Action Failure. Detected a bitstream decryption error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_ACT_KEY_CHALLENGE_FAIL, + "Key Challenge Failure. Detected a bitstream decryption error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_TASK_MSGQ_DEQUEUE_FAIL, + "Mailbox Task Queue failed to dequeue. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_SECT_COMPAT_CHK_ERR, + "Bitstream Section Compatibility Check Error. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_SECT_COMPAT_UPDATE_ERR, + "Bitstream Section Compatibility Update Error. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_SECT_SEC_CHK_FAILED, + "Bitstream Section Security Check Failed. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_CNT_RAM_ECC_ERR_UNRECOVERABLE, + "Unrecoverable Error in CNT/SSM RAM. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_REFORMAT_INPUT_ERR, + "Mailbox Input Processing Error. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_REFORMAT_OUTPUT_ERR, + "Mailbox Output Processing Error. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_WLBL_ERR, + "(Provision only) Provision CMF's allowed mailbox cmd group is invalid. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MBOX_HOOK_CB_ERR, + "Mailbox Callback Error. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_CMF_RLD_DECOMP_LOAD_ERR, + "CMF Reload failed to load Decompression Code. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_CMF_RLD_DECOMP_RUN_ERR, + "CMF Reload failed to run Decompression Code. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_CNT_PERIPH_ECC_ERR_UNRECOVERABLE, + "Unrecoverable Error in CNT/SSM Peripheral. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_SECT_ADDR_ERR, + "(Provision only) invalid Flash image CMF header's main section address. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SCRAMBLE_RATIO_CHK_FAIL, + "Bitstream Section Main Descriptor Invalid Scrambler Ratio. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_TAMPER_EVENT_TRIGGERED, + "Tamper Detected. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_ANTI_TAMPER_TBL_INV, + "Bitstream Section Main Descriptor Anti Tamper Table Invalid. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_EXT_CLCK_MODE_DISALLOWED, + "External Clock info presented, but external clock not allowed on device. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_SEC_OPTIONS_INIT_FAIL, + "Bitstream Section Main Descriptor Security Option Initialization Failed. Detected an error during configuration due to a corrupted bitstream." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_EN_USR_CAN_FUSE_INV, + "User cancellation fuse table initialization failed. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_AS_DEVICE_NO_SGX_ERR, + "Not yet turned on for Rearch code. Detected an incompatible bitstream during configuration. You cannot use the bitstream from an advanced security-enabled devices on a non-advanced security-enabled device." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_POF_ID_LIMIT_EXCEED_ERR, + "Not yet turned on for Rearch code. Detected an invalid bitstream during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_PROVISION_CMF_INV_STATE, + "(Provision only) Internal state machine wrong state. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_PROVISION_CMF_FATAL_ERR, + "(Provision only) Fatal error detected with Provision CMF. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_PROVISION_CMF_SM_EXIT_FAIL, + "(Provision only) State machine's state function exit error. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_PROVISION_CMF_SM_ENTRY_FAIL, + "(Provision only) State machine's state function entry error. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_ACTION_DATA_UNSUPPORTED_CTX, + "Not yet turned on for Rearch code. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_CMF_EXCEPTION, + "Processor Exception. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ECC_INIT_FAIL, + "SDM Peripheral ECC Initialization Failure. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_DEFAULT_UNREGISTERED_ISR, + "Unregistered Interrupt Occurred. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_GENERAL_TIMEOUT, + "Execution Timeout. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_OPERATION_CLK_FAIL, + "Clock Operation Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_ACT_VERIFY_HASH_FAIL, + "Verify Hash Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_CFG_STATE_UPDATE_ERR, + "Error updating configuration state. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_READ_DDR_HASH_FAIL, + "Error while reading HPS DDR hash from main descriptor."}, + {MBOX_CFGSTATE_MINOR_ERR_CVP_FLOW_ERR, + "Error during CvP Phase 2 data flow handling or handshake."}, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_KEYED_HASH_ERR, + "Encountered keyed hash error while processing a main descriptor."}, + {MBOX_CFGSTATE_MINOR_ERR_CMF_DESC_BAD_JTAG_ID, + "New CMF Descriptor JTAG ID mismatch with original configured CMF JTAG ID." + }, + {MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_PMF_NOT_SUPPORTED, + "The IO Descriptor contains a power table but the current CMF does not support PMF. Bitstream incompatile with Firmware." + }, + { + MBOX_CFGSTATE_MINOR_ERR_MAIN_DESC_ANTI_TAMPER_NOT_SUPPORTED, + "The IO Descriptor contains anti-tamper setting but the current CMF does not support anti-tamper. Bitstream incompatile with Firmware." + }, + {MBOX_CFGSTATE_MINOR_ERR_ACT_RECOVERY_FAIL, + "Recovery Action Failed. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_COLD_RESET_CMF_CORRUPTED, + "Error when process CMF section after cold reset. Detected CMF section error or incompatible upon cold reset using JTAG or AVST." + }, + {MBOX_CFGSTATE_MINOR_ERR_COLD_RESET_IO_HPS_CORRUPTED, + "Error when process IO/HPIO/HPS section after cold reset and hps wipe. Detected an error when try to bring up HPS again after cold reset." + }, + {MBOX_CFGSTATE_MINOR_ERR_COLD_RESET_FPGA_CORRUPTED, + "Error when process FPGA section header after cold reset. Detected an error in FPGA after successfully bring up HPS." + }, + {MBOX_CFGSTATE_MINOR_ERR_CRC_CHK_FAIL, + " CRC32 Check Fail. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_COMPAT_TBL_SFIXED_VALUE_INV, + "Error when process compatibility table in main section header. SFixed offset value in compatibility table is not valid." + }, + { + MBOX_CFGSTATE_MINOR_ERR_FEATURE_EN_FUSE_NOT_BLOWN, + "Error bitstream contains feature(s) that are only allowed when a feature fuse is blown on the device, and the device did not have the feature fuse blown. Bitstream requires feature enable fuse to be blown." + }, + {MBOX_CFGSTATE_MINOR_ERR_UIB_REFCLK_MISSING, + "UIB REFCLK missing. Device requires refclk to proceed configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_UIB_REFCLK_TIMEOUT, + "UIB REFCLK timeout. Device requires refclk to proceed configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_UIB_REFCLK_TIMEOUT_MISSING, + "UIB REFCLK missing and timeout. Device requires refclk to proceed configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_SYNC_BLCK_ERR, + "Sync block before SSBL processing failure. Detected a firmware error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_SSBL_SHA_ERR, + "SSBL sha mismatch with bitstream. Detected a bitstream error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_BLCK0_SHA_MISMATCH_ERR, + "Block0 Sha mismatch when trampoline reloads. Detected a bitstream error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_BLCK0_AUTH_ERR, + "Trampoline authentication failure. Detected a bitstream error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_TRAMP_LOAD_ERR, + "Trampoline Load compressed tramp failure. Detected a bitstream error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_CMF_SIZE_ERR, + "Trampoline failed to retrieve SSBL or TSBL load information. Detected a bitstream error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_TRANSITION_ERR, + "Trampoline failed to find a bootable DCMF. Detected an error during application images transition." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_SYNC_ERR, + "Only used by RMA and ENG loader on legacy code. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_LOAD_CERT_ERR, + "Main CMF failed to authenticate a certificate bitstream. Detected a bitstream authentication error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_LOAD_NOT_ALLOWED_ERR, + "Only used by Provision CMF, failure to initialize HW drivers. Detected an error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_FUSE_ERR, + "Only used by RMA and Eng loader on Legacy code. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_INPUT_BUFFER_ERR, + "Provision CMF only, Trampoline inbuf HW access error. Detected a hardware error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_CMF_TYPE_ERR, + "Trampoline/DCMF loading another CMF andfound CMF type mismatched with current one. Detected a bitstream error during reconfiguration." + }, + {MBOX_CFGSTATE_MINOR_ERR_TRAMP_QSPI_INDR_READ_START_ERR, + "Trampoline QSPI indirect read start error. Detected an error when accessing the QSPI flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_I2C_COMM_ERR, + "Generic I2C error, ie Bad Address."}, + {MBOX_CFGSTATE_MINOR_ERR_PMF_TARGET_VOLTAGE_ERR, + "Failed to reach Target Voltage. Voltage Regulator unable to achieve the requested voltage." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_HANDSHAKE_ERR, + "Slave Mode ALERT/VOUT_COMMAND handshake did not happen."}, + {MBOX_CFGSTATE_MINOR_ERR_PMF_ITD_OUT_OF_RANGE_ERR, + "Fuse values calculated voltage greater that cutoff max. ITD fuse is out of range." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_PWR_TABLE_ERR, + "Error while reading or processing the Power Table. Internal Error while reading or decoding the Bitstream's Power Table." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_EFUSE_DECODE_ERR, + "Error while reading or decoding the efuse values. Internal Error while reading or decoding the efuse values." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_VCCL_PWRGOOD_ERR, + "Failed to verify the vccl power is good. Failed to validate the vccl power is valid on the board." + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_CLR_FAULTS_ERR, + "Error while sending CLEAR_FAULTS command. Error while sending CLEAR_FAULTS command," + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_VOUT_MODE_ERR, + "Error while sending VOUT_MODE command. Error while sending VOUT_MODE command,"}, + {MBOX_CFGSTATE_MINOR_ERR_PMF_PAGE_COMMAND_ERR, + "Error while sending PAGE_COMMAND command. Error while sending PAGE_COMMAND command," + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_VOUT_COMMAND_ERR, + "Error while sending VOUT_COMMAND command. Error while sending VOUT_COMMAND command," + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_READ_VOUT_ERR, + "Error while sending READ_VOUT command. Error while sending READ_VOUT command,"}, + {MBOX_CFGSTATE_MINOR_ERR_PMF_LTM4677_DEFAULT_ADC_CTRL_ERR, + "Error while sending the vendor specific LTM4677 MFR_ADC_CTRL command. Error while sending the vendor specific LTM4677 MFR_ADC_CTRL command," + }, + {MBOX_CFGSTATE_MINOR_ERR_PMF_FIRST_I2C_CMD_FAILED_ERR, + "First I2C messaged failed, ie Bad Address. The first I2C command has failed, no response from Voltage Regulator." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_CMF_AUTH_ERR, + "Failed to authenticate CMF section. Detected a firmware authentication error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_USER_AUTH_ERR, + "Failed to authenticate USER section. Detected a bitstream authentication error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_CMF_DESC_SHA_MISMATCH, + "Block0 SHA mismatch when DCMF loads an APP image. Detected an error when loading the application image from flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_POINTERS_NOT_FOUND_ERR, + "RSU CPB table parsing failed. Detected an error when parsing the RSU CPB block." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_QSPI_FREQ_CHANGE, + "QSPI reference clock freq update failed. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_FACTORY_IMG_FAILED, + "RSU factory image failed to boot. Detected an error when loading the factory image. Check the factory image validity. If corrupted, regenerate and reprogram again the factory image in the flash. When authentication enabled," + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_CMF_TYPE_ERR, + "APP image CMF type mismatched with DCMF. Detected an error when loading the application image." + }, + { + MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_SIG_DESC_ERR, + "UCMF reports failure in parsing of an signature block, can be from new DCMF, new DCIO or new Factory. Detected an error during factory image update in flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_INTERNAL_AUTH_ERR, + "UCMF reports authentication failure of new DCMF, new DCIO or new Factory. Detected an error during DCMF update in flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_COPY_FAILED, + "UCMF reports QSPI flash write failure while upgrading DCMF, DCIO or Factory. Detected an error during DCMF update in flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_ERASE_FAILED, + "UCMF reports QSPI flash erase failure while upgrading DCMF, DCIO or Factory. Detected an error during DCMF update in flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_RM_UCMF_FROM_CPB_FAILED, + "UCMF reports failure to remove UCMF address from RSU CPB table. Detected an error during RSU CPB table update in flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_COMBINED_APP_AUTH_ERR, + "UCMF reports authentication failure of new combined app image. Detected an error during combined app image update in flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_UCMF_FLASH_ACCESS_ERR, + "UCMF failed to upgrade for more than max retry times. Detected an error during DCMF update in flash." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_DCMF_DCIO_CORRUPTED, + "DCMF reports failure when parse dcio section, causing force factory boot. Detected an error when parsing dcio section." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_DCMF_CPB0_CORRUPTED, + "DCMF reports failure when parse cpb0 and thus cpb1 is used. Detected an error in RSU CPB0 table." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_DCMF_CPB1_CORRUPTED, + "DCMF reports failure when parse both cpb0 and cpb1, causing force factory boot. Detected an error in both RSU CPB0 and CPB1 table." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_PROVISION_COMPLETE, + "Non-JTAG Provisioning Successful. Non-Jtag Provisioning was Successful DCMF will load next highest priority application image." + }, + {MBOX_CFGSTATE_MINOR_ERR_RSU_PROVISION_ERR, + "Non-JTAG Provisioning Failed. An error occurred while provisioning the device."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_EFUSE_INIT_FAIL, + "Efuse cache generation failure. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_SEC_PROT_ERR, + "Security lock and disable driver failure. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_EFUSE_LCK_ERR, + "efuse lock operation failure."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_SEC_BBRAM_CLEAN_ERR, + "BBRAM clean up failure."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_ENG_LOAD_DIMK_ERR, + "DIMK failed to derive device identity."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_SEC_UKV_CLEAN_ERR, + "Key Vault clean up failure."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_EFUSE_ZERO_ERR, + "No security efuse allowed."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_ENG_LOAD_ERR, + "efuse policy check failed."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_PERST_INIT_FAIL, + "Peristent data initialization failure. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_DIMK_INIT_FAIL, + "DIMK Initialization failure. Detected an error during configuration."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_PERST_SECONDARY_INIT_FAIL, + "Handoff data include CMF main and signature blocks validation failure. Detected an error during configuration." + }, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_BR_INFO_INIT_FAIL, + "CMF Bootrom header validation failure."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_CMF_DESC_FAIL, + "CMF Descriptor failure."}, + {MBOX_CFGSTATE_MINOR_ERR_SYSINIT_DRNG_INIT_FAIL, + "DRNG Initialization failed."}, + {MBOX_CFGSTATE_MINOR_ERR_UNK, + "Unknown error number at minor field!"} +}; + +#define MBOX_CFGSTAT_MINOR_ERR_MAX ARRAY_SIZE(mbox_cfgstat_minor_err) + +struct mbox_err_msg { + const char *major_err_str; + const char *minor_err_str; +}; + +static void mbox_cfgstat_to_str(int err, struct mbox_err_msg *err_msg) +{ + int i; + u32 major_err; + u32 minor_err; + + major_err = FIELD_GET(MBOX_CFG_STATUS_MAJOR_ERR_MSK, err); + + minor_err = FIELD_GET(MBOX_CFG_STATUS_MINOR_ERR_MSK, err); + + if (!err_msg) { + printf("Invalid argument\n"); + return; + } + + err_msg->major_err_str = ""; + err_msg->minor_err_str = ""; + + /* + * In the case of getting error number 0, meaning the + * ATF BL31 is not supporting the feature yet thus, + * the SMC call will return 0 at the second argument + * return the message to indicate that current BL31 + * is not yet supporting feature and need to check + * the BL31 version. + */ + if (err == 0) { + err_msg->major_err_str = mbox_cfgstat_major_err[err].error_name; + return; + } + + /* Initialize the major error string with unknown error */ + err_msg->major_err_str = mbox_cfgstat_major_err[0].error_name; + + for (i = 0; i < MBOX_CFGSTAT_MAJOR_ERR_MAX - 1; i++) { + if (mbox_cfgstat_major_err[i].err_no == major_err) { + err_msg->major_err_str = mbox_cfgstat_major_err[i].error_name; + break; + } + } + + /* Return configuration state if device still under config state */ + if (major_err == MBOX_CFGSTATE_MAJOR_ERR_STATE_CONFIG) + return; + + /* Initialize the minor error string with unknown error */ + err_msg->minor_err_str = mbox_cfgstat_minor_err[0].error_name; + + for (i = 0; i < MBOX_CFGSTAT_MINOR_ERR_MAX - 1; i++) { + if (mbox_cfgstat_minor_err[i].err_no == minor_err) { + err_msg->minor_err_str = mbox_cfgstat_minor_err[i].error_name; + break; + } + } +} + /* * Polling the FPGA configuration status. * Return 0 for success, non-zero for error. */ -static int reconfig_status_polling_resp(void) +static int reconfig_status_polling_resp(uint32_t *error_status) { int ret; + u64 res_buf[3]; unsigned long start = get_timer(0); while (1) { ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0, - NULL, 0); + res_buf, ARRAY_SIZE(res_buf)); + + if (error_status) + *error_status = (uint32_t)res_buf[0]; if (!ret) return 0; /* configuration success */ @@ -120,29 +732,44 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) { int ret; u64 arg = 1; + u32 err_status = 0; + u64 res_buf[3]; + struct mbox_err_msg err_msg; debug("Invoking FPGA_CONFIG_START...\n"); ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0); if (ret) { - puts("Failure in RECONFIG mailbox command!\n"); + puts("U-Boot SMC: Failure in RECONFIG mailbox command!\n"); return ret; } ret = send_bitstream(rbf_data, rbf_size); if (ret) { - puts("Error sending bitstream!\n"); + puts("\nU-Boot SMC: Error sending bitstream!\n"); + ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0, + res_buf, ARRAY_SIZE(res_buf)); + + err_status = res_buf[0]; + mbox_cfgstat_to_str(err_status, &err_msg); + printf("SDM: Config status: (0x%x)\nSDM Err: %s\n%s\n", err_status, + err_msg.major_err_str, err_msg.minor_err_str); + return ret; } /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US); - debug("Polling with MBOX_RECONFIG_STATUS...\n"); - ret = reconfig_status_polling_resp(); + debug("U-Boot SMC: Polling with MBOX_RECONFIG_STATUS...\n"); + ret = reconfig_status_polling_resp(&err_status); if (ret) { - puts("FPGA reconfiguration failed!"); + printf("\nU-Boot SMC: FPGA reconfiguration failed!\n"); + mbox_cfgstat_to_str(err_status, &err_msg); + printf("SDM: Config status: (0x%x)\nSDM Err:%s\n%s\n", err_status, + err_msg.major_err_str, err_msg.minor_err_str); + return ret; } diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index dcf6b4c81fc..1563404ca17 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -966,26 +966,7 @@ config TSEC_ENET This driver implements support for the (Enhanced) Three-Speed Ethernet Controller found on Freescale SoCs. -config MEDIATEK_ETH - bool "MediaTek Ethernet GMAC Driver" - select PHYLIB - select DM_GPIO - select DM_RESET - help - This Driver support MediaTek Ethernet GMAC - Say Y to enable support for the MediaTek Ethernet GMAC. - -if MEDIATEK_ETH - -config MTK_ETH_SGMII - bool - default y if ARCH_MEDIATEK && !TARGET_MT7623 - -config MTK_ETH_XGMII - bool - default y if TARGET_MT7987 || TARGET_MT7988 - -endif # MEDIATEK_ETH +source "drivers/net/mtk_eth/Kconfig" config HIFEMAC_ETH bool "HiSilicon Fast Ethernet Controller" diff --git a/drivers/net/Makefile b/drivers/net/Makefile index c6217f08f14..80d70212971 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -69,7 +69,7 @@ obj-$(CONFIG_MDIO_MUX_MESON_GXL) += mdio_mux_meson_gxl.o obj-$(CONFIG_MDIO_MUX_MMIOREG) += mdio_mux_mmioreg.o obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o -obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o +obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth/ obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o obj-$(CONFIG_MT7620_ETH) += mt7620-eth.o obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 07b0f49ef58..94d8f1b4c04 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -784,6 +784,39 @@ int designware_eth_probe(struct udevice *dev) priv->bus = miiphy_get_dev_by_name(dev->name); priv->dev = dev; +#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO) + if (dev_read_bool(dev, "snps,bitbang-mii")) { + int bus_idx; + + debug("\n%s: use bitbang mii..\n", dev->name); + ret = gpio_request_by_name(dev, "snps,mdc-gpio", 0, + &priv->mdc_gpio, GPIOD_IS_OUT + | GPIOD_IS_OUT_ACTIVE); + if (ret) { + debug("no mdc-gpio\n"); + return ret; + } + ret = gpio_request_by_name(dev, "snps,mdio-gpio", 0, + &priv->mdio_gpio, GPIOD_IS_OUT + | GPIOD_IS_OUT_ACTIVE); + if (ret) { + debug("no mdio-gpio\n"); + return ret; + } + priv->bb_delay = dev_read_u32_default(dev, "snps,bitbang-delay", 1); + + for (bus_idx = 0; bus_idx < bb_miiphy_buses_num; bus_idx++) { + if (!bb_miiphy_buses[bus_idx].priv) { + bb_miiphy_buses[bus_idx].priv = priv; + strlcpy(bb_miiphy_buses[bus_idx].name, priv->bus->name, + MDIO_NAME_LEN); + priv->bus->read = bb_miiphy_read; + priv->bus->write = bb_miiphy_write; + break; + } + } + } +#endif ret = dw_phy_init(priv, dev); debug("%s, ret=%d\n", __func__, ret); if (!ret) @@ -894,3 +927,83 @@ static struct pci_device_id supported[] = { }; U_BOOT_PCI_DEVICE(eth_designware, supported); + +#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO) +static int dw_eth_bb_mdio_active(struct bb_miiphy_bus *bus) +{ + struct dw_eth_dev *priv = bus->priv; + struct gpio_desc *desc = &priv->mdio_gpio; + + desc->flags = 0; + dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + return 0; +} + +static int dw_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct dw_eth_dev *priv = bus->priv; + struct gpio_desc *desc = &priv->mdio_gpio; + + desc->flags = 0; + dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_IN); + + return 0; +} + +static int dw_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct dw_eth_dev *priv = bus->priv; + + if (v) + dm_gpio_set_value(&priv->mdio_gpio, 1); + else + dm_gpio_set_value(&priv->mdio_gpio, 0); + + return 0; +} + +static int dw_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + struct dw_eth_dev *priv = bus->priv; + + *v = dm_gpio_get_value(&priv->mdio_gpio); + + return 0; +} + +static int dw_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct dw_eth_dev *priv = bus->priv; + + if (v) + dm_gpio_set_value(&priv->mdc_gpio, 1); + else + dm_gpio_set_value(&priv->mdc_gpio, 0); + + return 0; +} + +static int dw_eth_bb_delay(struct bb_miiphy_bus *bus) +{ + struct dw_eth_dev *priv = bus->priv; + + udelay(priv->bb_delay); + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = BB_MII_DEVNAME, + .mdio_active = dw_eth_bb_mdio_active, + .mdio_tristate = dw_eth_bb_mdio_tristate, + .set_mdio = dw_eth_bb_set_mdio, + .get_mdio = dw_eth_bb_get_mdio, + .set_mdc = dw_eth_bb_set_mdc, + .delay = dw_eth_bb_delay, + .priv = NULL, + } +}; + +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); +#endif diff --git a/drivers/net/designware.h b/drivers/net/designware.h index e47101ccaf6..cccf9d54e02 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -229,7 +229,11 @@ struct dw_eth_dev { u32 max_speed; u32 tx_currdescnum; u32 rx_currdescnum; - +#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO) + u32 bb_delay; + struct gpio_desc mdc_gpio; + struct gpio_desc mdio_gpio; +#endif struct eth_mac_regs *mac_regs_p; struct eth_dma_regs *dma_regs_p; #if CONFIG_IS_ENABLED(DM_GPIO) diff --git a/drivers/net/dwc_eth_xgmac.c b/drivers/net/dwc_eth_xgmac.c index d3e5f9255f5..cf8227b1b4d 100644 --- a/drivers/net/dwc_eth_xgmac.c +++ b/drivers/net/dwc_eth_xgmac.c @@ -152,7 +152,9 @@ static int xgmac_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, ret = xgmac_mdio_wait_idle(xgmac); if (ret) { - pr_err("MDIO not idle at entry: %d\n", ret); + pr_err("%s MDIO not idle at entry: %d\n", + xgmac->dev->name, ret); + return ret; } @@ -172,7 +174,9 @@ static int xgmac_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, ret = xgmac_mdio_wait_idle(xgmac); if (ret) { - pr_err("MDIO not idle at entry: %d\n", ret); + pr_err("%s MDIO not idle at entry: %d\n", + xgmac->dev->name, ret); + return ret; } @@ -181,7 +185,9 @@ static int xgmac_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, ret = xgmac_mdio_wait_idle(xgmac); if (ret) { - pr_err("MDIO read didn't complete: %d\n", ret); + pr_err("%s MDIO read didn't complete: %d\n", + xgmac->dev->name, ret); + return ret; } @@ -206,7 +212,9 @@ static int xgmac_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, ret = xgmac_mdio_wait_idle(xgmac); if (ret) { - pr_err("MDIO not idle at entry: %d\n", ret); + pr_err("%s MDIO not idle at entry: %d\n", + xgmac->dev->name, ret); + return ret; } @@ -229,7 +237,9 @@ static int xgmac_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, ret = xgmac_mdio_wait_idle(xgmac); if (ret) { - pr_err("MDIO not idle at entry: %d\n", ret); + pr_err("%s MDIO not idle at entry: %d\n", + xgmac->dev->name, ret); + return ret; } @@ -238,7 +248,9 @@ static int xgmac_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, ret = xgmac_mdio_wait_idle(xgmac); if (ret) { - pr_err("MDIO write didn't complete: %d\n", ret); + pr_err("%s MDIO write didn't complete: %d\n", + xgmac->dev->name, ret); + return ret; } @@ -323,7 +335,7 @@ static int xgmac_adjust_link(struct udevice *dev) else ret = xgmac_set_half_duplex(dev); if (ret < 0) { - pr_err("xgmac_set_*_duplex() failed: %d\n", ret); + pr_err("%s xgmac_set_*_duplex() failed: %d\n", dev->name, ret); return ret; } @@ -341,26 +353,28 @@ static int xgmac_adjust_link(struct udevice *dev) ret = xgmac_set_mii_speed_10(dev); break; default: - pr_err("invalid speed %d\n", xgmac->phy->speed); + pr_err("%s invalid speed %d\n", dev->name, xgmac->phy->speed); return -EINVAL; } if (ret < 0) { - pr_err("xgmac_set_*mii_speed*() failed: %d\n", ret); + pr_err("%s xgmac_set_*mii_speed*() failed: %d\n", dev->name, ret); return ret; } if (en_calibration) { ret = xgmac->config->ops->xgmac_calibrate_pads(dev); if (ret < 0) { - pr_err("xgmac_calibrate_pads() failed: %d\n", - ret); + pr_err("%s xgmac_calibrate_pads() failed: %d\n", + dev->name, ret); + return ret; } } else { ret = xgmac->config->ops->xgmac_disable_calibration(dev); if (ret < 0) { - pr_err("xgmac_disable_calibration() failed: %d\n", - ret); + pr_err("%s xgmac_disable_calibration() failed: %d\n", + dev->name, ret); + return ret; } } @@ -456,7 +470,7 @@ static int xgmac_start(struct udevice *dev) ret = xgmac->config->ops->xgmac_start_resets(dev); if (ret < 0) { - pr_err("xgmac_start_resets() failed: %d\n", ret); + pr_err("%s xgmac_start_resets() failed: %d\n", dev->name, ret); goto err; } @@ -466,13 +480,13 @@ static int xgmac_start(struct udevice *dev) XGMAC_DMA_MODE_SWR, false, xgmac->config->swr_wait, false); if (ret) { - pr_err("XGMAC_DMA_MODE_SWR stuck: %d\n", ret); + pr_err("%s XGMAC_DMA_MODE_SWR stuck: %d\n", dev->name, ret); goto err_stop_resets; } ret = xgmac->config->ops->xgmac_calibrate_pads(dev); if (ret < 0) { - pr_err("xgmac_calibrate_pads() failed: %d\n", ret); + pr_err("%s xgmac_calibrate_pads() failed: %d\n", dev->name, ret); goto err_stop_resets; } @@ -485,14 +499,16 @@ static int xgmac_start(struct udevice *dev) xgmac->phy = phy_connect(xgmac->mii, addr, dev, xgmac->config->interface(dev)); if (!xgmac->phy) { - pr_err("phy_connect() failed\n"); + pr_err("%s phy_connect() failed\n", dev->name); goto err_stop_resets; } if (xgmac->max_speed) { ret = phy_set_supported(xgmac->phy, xgmac->max_speed); if (ret) { - pr_err("phy_set_supported() failed: %d\n", ret); + pr_err("%s phy_set_supported() failed: %d\n", + dev->name, ret); + goto err_shutdown_phy; } } @@ -500,25 +516,25 @@ static int xgmac_start(struct udevice *dev) xgmac->phy->node = xgmac->phy_of_node; ret = phy_config(xgmac->phy); if (ret < 0) { - pr_err("phy_config() failed: %d\n", ret); + pr_err("%s phy_config() failed: %d\n", dev->name, ret); goto err_shutdown_phy; } } ret = phy_startup(xgmac->phy); if (ret < 0) { - pr_err("phy_startup() failed: %d\n", ret); + pr_err("%s phy_startup() failed: %d\n", dev->name, ret); goto err_shutdown_phy; } if (!xgmac->phy->link) { - pr_err("No link\n"); + pr_err("%s No link\n", dev->name); goto err_shutdown_phy; } ret = xgmac_adjust_link(dev); if (ret < 0) { - pr_err("xgmac_adjust_link() failed: %d\n", ret); + pr_err("%s xgmac_adjust_link() failed: %d\n", dev->name, ret); goto err_shutdown_phy; } @@ -611,7 +627,7 @@ static int xgmac_start(struct udevice *dev) ret = xgmac_write_hwaddr(dev); if (ret < 0) { - pr_err("xgmac_write_hwaddr() failed: %d\n", ret); + pr_err("%s xgmac_write_hwaddr() failed: %d\n", dev->name, ret); goto err; } @@ -738,7 +754,7 @@ err_shutdown_phy: err_stop_resets: xgmac->config->ops->xgmac_stop_resets(dev); err: - pr_err("FAILED: %d\n", ret); + pr_err("%s FAILED: %d\n", dev->name, ret); return ret; } @@ -1047,7 +1063,7 @@ static int xgmac_probe(struct udevice *dev) xgmac->regs = dev_read_addr(dev); if (xgmac->regs == FDT_ADDR_T_NONE) { - pr_err("dev_read_addr() failed\n"); + pr_err("%s dev_read_addr() failed\n", dev->name); return -ENODEV; } xgmac->mac_regs = (void *)(xgmac->regs + XGMAC_MAC_REGS_BASE); @@ -1058,19 +1074,23 @@ static int xgmac_probe(struct udevice *dev) ret = xgmac_probe_resources_core(dev); if (ret < 0) { - pr_err("xgmac_probe_resources_core() failed: %d\n", ret); + pr_err("%s xgmac_probe_resources_core() failed: %d\n", + dev->name, ret); + return ret; } ret = xgmac->config->ops->xgmac_probe_resources(dev); if (ret < 0) { - pr_err("xgmac_probe_resources() failed: %d\n", ret); + pr_err("%s xgmac_probe_resources() failed: %d\n", + dev->name, ret); + goto err_remove_resources_core; } ret = xgmac->config->ops->xgmac_start_clks(dev); if (ret < 0) { - pr_err("xgmac_start_clks() failed: %d\n", ret); + pr_err("%s xgmac_start_clks() failed: %d\n", dev->name, ret); return ret; } @@ -1080,7 +1100,7 @@ static int xgmac_probe(struct udevice *dev) if (!xgmac->mii) { xgmac->mii = mdio_alloc(); if (!xgmac->mii) { - pr_err("mdio_alloc() failed\n"); + pr_err("%s mdio_alloc() failed\n", dev->name); ret = -ENOMEM; goto err_stop_clks; } @@ -1091,7 +1111,9 @@ static int xgmac_probe(struct udevice *dev) ret = mdio_register(xgmac->mii); if (ret < 0) { - pr_err("mdio_register() failed: %d\n", ret); + pr_err("%s mdio_register() failed: %d\n", + dev->name, ret); + goto err_free_mdio; } } diff --git a/drivers/net/dwc_eth_xgmac_socfpga.c b/drivers/net/dwc_eth_xgmac_socfpga.c index 87fb7e887e7..c89c8a188b7 100644 --- a/drivers/net/dwc_eth_xgmac_socfpga.c +++ b/drivers/net/dwc_eth_xgmac_socfpga.c @@ -29,6 +29,25 @@ #define SOCFPGA_XGMAC_SYSCON_ARG_COUNT 2 +phy_interface_t dwxgmac_of_get_mac_mode(struct udevice *dev) +{ + const char *mac_mode; + int i; + + debug("%s(dev=%p):\n", __func__, dev); + mac_mode = dev_read_string(dev, "mac-mode"); + if (!mac_mode) + return PHY_INTERFACE_MODE_NA; + + if (mac_mode) { + for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++) { + if (!strcmp(mac_mode, phy_interface_strings[i])) + return i; + } + } + return PHY_INTERFACE_MODE_NA; +} + static int dwxgmac_socfpga_do_setphy(struct udevice *dev, u32 modereg) { struct xgmac_priv *xgmac = dev_get_priv(dev); @@ -66,12 +85,17 @@ static int xgmac_probe_resources_socfpga(struct udevice *dev) struct ofnode_phandle_args args; void *range; phy_interface_t interface; + phy_interface_t mac_mode; int ret; u32 modereg; interface = xgmac->config->interface(dev); + mac_mode = dwxgmac_of_get_mac_mode(dev); + + if (mac_mode == PHY_INTERFACE_MODE_NA) + mac_mode = interface; - switch (interface) { + switch (mac_mode) { case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; @@ -80,6 +104,7 @@ static int xgmac_probe_resources_socfpga(struct udevice *dev) modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; break; default: diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index a9e2d8c0972..a55f3e29f9f 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -106,6 +106,9 @@ static int dwmac_socfpga_probe(struct udevice *dev) modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; break; default: diff --git a/drivers/net/mtk_eth/Kconfig b/drivers/net/mtk_eth/Kconfig new file mode 100644 index 00000000000..e8cdf408237 --- /dev/null +++ b/drivers/net/mtk_eth/Kconfig @@ -0,0 +1,39 @@ + +config MEDIATEK_ETH + bool "MediaTek Ethernet GMAC Driver" + select PHYLIB + select DM_GPIO + select DM_RESET + help + This Driver support MediaTek Ethernet GMAC + Say Y to enable support for the MediaTek Ethernet GMAC. + +if MEDIATEK_ETH + +config MTK_ETH_SGMII + bool + default y if ARCH_MEDIATEK && !TARGET_MT7623 + +config MTK_ETH_XGMII + bool + default y if TARGET_MT7987 || TARGET_MT7988 + +config MTK_ETH_SWITCH_MT7530 + bool "Support for MediaTek MT7530 ethernet switch" + default y if TARGET_MT7623 || SOC_MT7621 + +config MTK_ETH_SWITCH_MT7531 + bool "Support for MediaTek MT7531 ethernet switch" + default y if TARGET_MT7622 || TARGET_MT7629 || TARGET_MT7981 || \ + TARGET_MT7986 || TARGET_MT7987 + +config MTK_ETH_SWITCH_MT7988 + bool "Support for MediaTek MT7988 built-in ethernet switch" + depends on TARGET_MT7988 + default y + +config MTK_ETH_SWITCH_AN8855 + bool "Support for Airoha AN8855 ethernet switch" + default y if TARGET_MT7981 || TARGET_MT7987 + +endif # MEDIATEK_ETH diff --git a/drivers/net/mtk_eth/Makefile b/drivers/net/mtk_eth/Makefile new file mode 100644 index 00000000000..a342325ed5d --- /dev/null +++ b/drivers/net/mtk_eth/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025 MediaTek Inc. +# Author: Weijie Gao <weijie.gao@mediatek.com> + +obj-y += mtk_eth.o +obj-$(CONFIG_MTK_ETH_SWITCH_MT7530) += mt753x.o mt7530.o +obj-$(CONFIG_MTK_ETH_SWITCH_MT7531) += mt753x.o mt7531.o +obj-$(CONFIG_MTK_ETH_SWITCH_MT7988) += mt753x.o mt7988.o +obj-$(CONFIG_MTK_ETH_SWITCH_AN8855) += an8855.o diff --git a/drivers/net/mtk_eth/an8855.c b/drivers/net/mtk_eth/an8855.c new file mode 100644 index 00000000000..4bd7506a58b --- /dev/null +++ b/drivers/net/mtk_eth/an8855.c @@ -0,0 +1,1096 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * + * Author: Neal Yen <neal.yen@mediatek.com> + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <phy.h> +#include <miiphy.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/mdio.h> +#include <linux/mii.h> +#include "mtk_eth.h" + +/* AN8855 Register Definitions */ +#define AN8855_SYS_CTRL_REG 0x100050c0 +#define AN8855_SW_SYS_RST BIT(31) + +#define AN8855_PMCR_REG(p) (0x10210000 + (p) * 0x200) +#define AN8855_FORCE_MODE_LNK BIT(31) +#define AN8855_FORCE_MODE 0xb31593f0 + +#define AN8855_PORT_CTRL_BASE (0x10208000) +#define AN8855_PORT_CTRL_REG(p, r) (AN8855_PORT_CTRL_BASE + (p) * 0x200 + (r)) + +#define AN8855_PORTMATRIX_REG(p) AN8855_PORT_CTRL_REG(p, 0x44) + +#define AN8855_PVC(p) AN8855_PORT_CTRL_REG(p, 0x10) +#define AN8855_STAG_VPID_S 16 +#define AN8855_STAG_VPID_M 0xffff0000 +#define AN8855_VLAN_ATTR_S 6 +#define AN8855_VLAN_ATTR_M 0xc0 + +#define VLAN_ATTR_USER 0 + +#define AN8855_INT_MASK 0x100050F0 +#define AN8855_INT_SYS_BIT BIT(15) + +#define AN8855_RG_CLK_CPU_ICG 0x10005034 +#define AN8855_MCU_ENABLE BIT(3) + +#define AN8855_RG_TIMER_CTL 0x1000a100 +#define AN8855_WDOG_ENABLE BIT(25) + +#define AN8855_CKGCR 0x10213e1c + +#define AN8855_SCU_BASE 0x10000000 +#define AN8855_RG_RGMII_TXCK_C (AN8855_SCU_BASE + 0x1d0) +#define AN8855_RG_GPIO_LED_MODE (AN8855_SCU_BASE + 0x0054) +#define AN8855_RG_GPIO_LED_SEL(i) (AN8855_SCU_BASE + (0x0058 + ((i) * 4))) +#define AN8855_RG_INTB_MODE (AN8855_SCU_BASE + 0x0080) +#define AN8855_RG_GDMP_RAM (AN8855_SCU_BASE + 0x10000) +#define AN8855_RG_GPIO_L_INV (AN8855_SCU_BASE + 0x0010) +#define AN8855_RG_GPIO_CTRL (AN8855_SCU_BASE + 0xa300) +#define AN8855_RG_GPIO_DATA (AN8855_SCU_BASE + 0xa304) +#define AN8855_RG_GPIO_OE (AN8855_SCU_BASE + 0xa314) + +#define AN8855_HSGMII_AN_CSR_BASE 0x10220000 +#define AN8855_SGMII_REG_AN0 (AN8855_HSGMII_AN_CSR_BASE + 0x000) +#define AN8855_SGMII_REG_AN_13 (AN8855_HSGMII_AN_CSR_BASE + 0x034) +#define AN8855_SGMII_REG_AN_FORCE_CL37 (AN8855_HSGMII_AN_CSR_BASE + 0x060) + +#define AN8855_HSGMII_CSR_PCS_BASE 0x10220000 +#define AN8855_RG_HSGMII_PCS_CTROL_1 (AN8855_HSGMII_CSR_PCS_BASE + 0xa00) +#define AN8855_RG_AN_SGMII_MODE_FORCE (AN8855_HSGMII_CSR_PCS_BASE + 0xa24) + +#define AN8855_MULTI_SGMII_CSR_BASE 0x10224000 +#define AN8855_SGMII_STS_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x018) +#define AN8855_MSG_RX_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x100) +#define AN8855_MSG_RX_LIK_STS_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x514) +#define AN8855_MSG_RX_LIK_STS_2 (AN8855_MULTI_SGMII_CSR_BASE + 0x51c) +#define AN8855_PHY_RX_FORCE_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x520) + +#define AN8855_XFI_CSR_PCS_BASE 0x10225000 +#define AN8855_RG_USXGMII_AN_CONTROL_0 (AN8855_XFI_CSR_PCS_BASE + 0xbf8) + +#define AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000 +#define AN8855_RG_RATE_ADAPT_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x000) +#define AN8855_RATE_ADP_P0_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x100) +#define AN8855_MII_RA_AN_ENABLE (AN8855_MULTI_PHY_RA_CSR_BASE + 0x300) + +#define AN8855_QP_DIG_CSR_BASE 0x1022a000 +#define AN8855_QP_CK_RST_CTRL_4 (AN8855_QP_DIG_CSR_BASE + 0x310) +#define AN8855_QP_DIG_MODE_CTRL_0 (AN8855_QP_DIG_CSR_BASE + 0x324) +#define AN8855_QP_DIG_MODE_CTRL_1 (AN8855_QP_DIG_CSR_BASE + 0x330) + +#define AN8855_QP_PMA_TOP_BASE 0x1022e000 +#define AN8855_PON_RXFEDIG_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x100) +#define AN8855_PON_RXFEDIG_CTRL_9 (AN8855_QP_PMA_TOP_BASE + 0x124) + +#define AN8855_SS_LCPLL_PWCTL_SETTING_2 (AN8855_QP_PMA_TOP_BASE + 0x208) +#define AN8855_SS_LCPLL_TDC_FLT_2 (AN8855_QP_PMA_TOP_BASE + 0x230) +#define AN8855_SS_LCPLL_TDC_FLT_5 (AN8855_QP_PMA_TOP_BASE + 0x23c) +#define AN8855_SS_LCPLL_TDC_PCW_1 (AN8855_QP_PMA_TOP_BASE + 0x248) +#define AN8855_INTF_CTRL_8 (AN8855_QP_PMA_TOP_BASE + 0x320) +#define AN8855_INTF_CTRL_9 (AN8855_QP_PMA_TOP_BASE + 0x324) +#define AN8855_PLL_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x400) +#define AN8855_PLL_CTRL_2 (AN8855_QP_PMA_TOP_BASE + 0x408) +#define AN8855_PLL_CTRL_3 (AN8855_QP_PMA_TOP_BASE + 0x40c) +#define AN8855_PLL_CTRL_4 (AN8855_QP_PMA_TOP_BASE + 0x410) +#define AN8855_PLL_CK_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x414) +#define AN8855_RX_DLY_0 (AN8855_QP_PMA_TOP_BASE + 0x614) +#define AN8855_RX_CTRL_2 (AN8855_QP_PMA_TOP_BASE + 0x630) +#define AN8855_RX_CTRL_5 (AN8855_QP_PMA_TOP_BASE + 0x63c) +#define AN8855_RX_CTRL_6 (AN8855_QP_PMA_TOP_BASE + 0x640) +#define AN8855_RX_CTRL_7 (AN8855_QP_PMA_TOP_BASE + 0x644) +#define AN8855_RX_CTRL_8 (AN8855_QP_PMA_TOP_BASE + 0x648) +#define AN8855_RX_CTRL_26 (AN8855_QP_PMA_TOP_BASE + 0x690) +#define AN8855_RX_CTRL_42 (AN8855_QP_PMA_TOP_BASE + 0x6d0) + +#define AN8855_QP_ANA_CSR_BASE 0x1022f000 +#define AN8855_RG_QP_RX_DAC_EN (AN8855_QP_ANA_CSR_BASE + 0x00) +#define AN8855_RG_QP_RXAFE_RESERVE (AN8855_QP_ANA_CSR_BASE + 0x04) +#define AN8855_RG_QP_CDR_LPF_MJV_LIM (AN8855_QP_ANA_CSR_BASE + 0x0c) +#define AN8855_RG_QP_CDR_LPF_SETVALUE (AN8855_QP_ANA_CSR_BASE + 0x14) +#define AN8855_RG_QP_CDR_PR_CKREF_DIV1 (AN8855_QP_ANA_CSR_BASE + 0x18) +#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE (AN8855_QP_ANA_CSR_BASE + 0x1c) +#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF (AN8855_QP_ANA_CSR_BASE + 0x20) +#define AN8855_RG_QP_TX_MODE_16B_EN (AN8855_QP_ANA_CSR_BASE + 0x28) +#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL (AN8855_QP_ANA_CSR_BASE + 0x3c) +#define AN8855_RG_QP_PLL_SDM_ORD (AN8855_QP_ANA_CSR_BASE + 0x40) + +#define AN8855_ETHER_SYS_BASE 0x1028c800 +#define RG_GPHY_AFE_PWD (AN8855_ETHER_SYS_BASE + 0x40) + +#define AN8855_PKG_SEL 0x10000094 +#define PAG_SEL_AN8855H 0x2 + +/* PHY LED Register bitmap of define */ +#define PHY_LED_CTRL_SELECT 0x3e8 +#define PHY_SINGLE_LED_ON_CTRL(i) (0x3e0 + ((i) * 2)) +#define PHY_SINGLE_LED_BLK_CTRL(i) (0x3e1 + ((i) * 2)) +#define PHY_SINGLE_LED_ON_DUR(i) (0x3e9 + ((i) * 2)) +#define PHY_SINGLE_LED_BLK_DUR(i) (0x3ea + ((i) * 2)) + +#define PHY_PMA_CTRL (0x340) + +#define PHY_DEV1F 0x1f + +#define PHY_LED_ON_CTRL(i) (0x24 + ((i) * 2)) +#define LED_ON_EN (1 << 15) +#define LED_ON_POL (1 << 14) +#define LED_ON_EVT_MASK (0x7f) + +/* LED ON Event */ +#define LED_ON_EVT_FORCE (1 << 6) +#define LED_ON_EVT_LINK_HD (1 << 5) +#define LED_ON_EVT_LINK_FD (1 << 4) +#define LED_ON_EVT_LINK_DOWN (1 << 3) +#define LED_ON_EVT_LINK_10M (1 << 2) +#define LED_ON_EVT_LINK_100M (1 << 1) +#define LED_ON_EVT_LINK_1000M (1 << 0) + +#define PHY_LED_BLK_CTRL(i) (0x25 + ((i) * 2)) +#define LED_BLK_EVT_MASK (0x3ff) +/* LED Blinking Event */ +#define LED_BLK_EVT_FORCE (1 << 9) +#define LED_BLK_EVT_10M_RX_ACT (1 << 5) +#define LED_BLK_EVT_10M_TX_ACT (1 << 4) +#define LED_BLK_EVT_100M_RX_ACT (1 << 3) +#define LED_BLK_EVT_100M_TX_ACT (1 << 2) +#define LED_BLK_EVT_1000M_RX_ACT (1 << 1) +#define LED_BLK_EVT_1000M_TX_ACT (1 << 0) + +#define PHY_LED_BCR (0x21) +#define LED_BCR_EXT_CTRL (1 << 15) +#define LED_BCR_CLK_EN (1 << 3) +#define LED_BCR_TIME_TEST (1 << 2) +#define LED_BCR_MODE_MASK (3) +#define LED_BCR_MODE_DISABLE (0) + +#define PHY_LED_ON_DUR (0x22) +#define LED_ON_DUR_MASK (0xffff) + +#define PHY_LED_BLK_DUR (0x23) +#define LED_BLK_DUR_MASK (0xffff) + +#define PHY_LED_BLINK_DUR_CTRL (0x720) + +/* Definition of LED */ +#define LED_ON_EVENT (LED_ON_EVT_LINK_1000M | \ + LED_ON_EVT_LINK_100M | LED_ON_EVT_LINK_10M |\ + LED_ON_EVT_LINK_HD | LED_ON_EVT_LINK_FD) + +#define LED_BLK_EVENT (LED_BLK_EVT_1000M_TX_ACT | \ + LED_BLK_EVT_1000M_RX_ACT | \ + LED_BLK_EVT_100M_TX_ACT | \ + LED_BLK_EVT_100M_RX_ACT | \ + LED_BLK_EVT_10M_TX_ACT | \ + LED_BLK_EVT_10M_RX_ACT) + +#define LED_FREQ AIR_LED_BLK_DUR_64M + +#define AN8855_NUM_PHYS 5 +#define AN8855_NUM_PORTS 6 +#define AN8855_PHY_ADDR(base, addr) (((base) + (addr)) & 0x1f) + +/* PHY LED Register bitmap of define */ +#define PHY_LED_CTRL_SELECT 0x3e8 +#define PHY_SINGLE_LED_ON_CTRL(i) (0x3e0 + ((i) * 2)) +#define PHY_SINGLE_LED_BLK_CTRL(i) (0x3e1 + ((i) * 2)) +#define PHY_SINGLE_LED_ON_DUR(i) (0x3e9 + ((i) * 2)) +#define PHY_SINGLE_LED_BLK_DUR(i) (0x3ea + ((i) * 2)) + +/* AN8855 LED */ +enum an8855_led_blk_dur { + AIR_LED_BLK_DUR_32M, + AIR_LED_BLK_DUR_64M, + AIR_LED_BLK_DUR_128M, + AIR_LED_BLK_DUR_256M, + AIR_LED_BLK_DUR_512M, + AIR_LED_BLK_DUR_1024M, + AIR_LED_BLK_DUR_LAST +}; + +enum an8855_led_polarity { + LED_LOW, + LED_HIGH, +}; + +enum an8855_led_mode { + AN8855_LED_MODE_DISABLE, + AN8855_LED_MODE_USER_DEFINE, + AN8855_LED_MODE_LAST +}; + +enum phy_led_idx { + P0_LED0, + P0_LED1, + P0_LED2, + P0_LED3, + P1_LED0, + P1_LED1, + P1_LED2, + P1_LED3, + P2_LED0, + P2_LED1, + P2_LED2, + P2_LED3, + P3_LED0, + P3_LED1, + P3_LED2, + P3_LED3, + P4_LED0, + P4_LED1, + P4_LED2, + P4_LED3, + PHY_LED_MAX +}; + +struct an8855_led_cfg { + u16 en; + u8 phy_led_idx; + u16 pol; + u16 on_cfg; + u16 blk_cfg; + u8 led_freq; +}; + +struct an8855_switch_priv { + struct mtk_eth_switch_priv epriv; + struct mii_dev *mdio_bus; + u32 phy_base; +}; + +/* AN8855 Reference Board */ +static const struct an8855_led_cfg led_cfg[] = { +/************************************************************************* + * Enable, LED idx, LED Polarity, LED ON event, LED Blink event LED Freq + ************************************************************************* + */ + /* GPIO0 */ + {1, P4_LED0, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO1 */ + {1, P4_LED1, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO2 */ + {1, P0_LED0, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO3 */ + {1, P0_LED1, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO4 */ + {1, P1_LED0, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO5 */ + {1, P1_LED1, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO6 */ + {0, PHY_LED_MAX, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO7 */ + {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO8 */ + {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO9 */ + {1, P2_LED0, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO10 */ + {1, P2_LED1, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO11 */ + {1, P3_LED0, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO12 */ + {1, P3_LED1, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO13 */ + {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO14 */ + {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO15 */ + {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO16 */ + {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO17 */ + {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO18 */ + {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO19 */ + {0, PHY_LED_MAX, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, + /* GPIO20 */ + {0, PHY_LED_MAX, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, +}; + +static int __an8855_reg_read(struct mtk_eth_priv *priv, u8 phy_base, u32 reg, u32 *data) +{ + int ret, low_word, high_word; + + ret = mtk_mii_write(priv, phy_base, 0x1f, 0x4); + if (ret) + return ret; + + ret = mtk_mii_write(priv, phy_base, 0x10, 0); + if (ret) + return ret; + + ret = mtk_mii_write(priv, phy_base, 0x15, ((reg >> 16) & 0xFFFF)); + if (ret) + return ret; + + ret = mtk_mii_write(priv, phy_base, 0x16, (reg & 0xFFFF)); + if (ret) + return ret; + + low_word = mtk_mii_read(priv, phy_base, 0x18); + if (low_word < 0) + return low_word; + + high_word = mtk_mii_read(priv, phy_base, 0x17); + if (high_word < 0) + return high_word; + + ret = mtk_mii_write(priv, phy_base, 0x1f, 0); + if (ret) + return ret; + + ret = mtk_mii_write(priv, phy_base, 0x10, 0); + if (ret) + return ret; + + if (data) + *data = ((u32)high_word << 16) | (low_word & 0xffff); + + return 0; +} + +static int an8855_reg_read(struct an8855_switch_priv *priv, u32 reg, u32 *data) +{ + return __an8855_reg_read(priv->epriv.eth, priv->phy_base, reg, data); +} + +static int an8855_reg_write(struct an8855_switch_priv *priv, u32 reg, u32 data) +{ + int ret; + + ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x1f, 0x4); + if (ret) + return ret; + + ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x10, 0); + if (ret) + return ret; + + ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x11, + ((reg >> 16) & 0xFFFF)); + if (ret) + return ret; + + ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x12, + (reg & 0xFFFF)); + if (ret) + return ret; + + ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x13, + ((data >> 16) & 0xFFFF)); + if (ret) + return ret; + + ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x14, + (data & 0xFFFF)); + if (ret) + return ret; + + ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x1f, 0); + if (ret) + return ret; + + ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x10, 0); + if (ret) + return ret; + + return 0; +} + +static int an8855_phy_cl45_read(struct an8855_switch_priv *priv, int port, + int devad, int regnum, u16 *data) +{ + u16 phy_addr = AN8855_PHY_ADDR(priv->phy_base, port); + + *data = mtk_mmd_ind_read(priv->epriv.eth, phy_addr, devad, regnum); + + return 0; +} + +static int an8855_phy_cl45_write(struct an8855_switch_priv *priv, int port, + int devad, int regnum, u16 data) +{ + u16 phy_addr = AN8855_PHY_ADDR(priv->phy_base, port); + + mtk_mmd_ind_write(priv->epriv.eth, phy_addr, devad, regnum, data); + + return 0; +} + +static int an8855_port_sgmii_init(struct an8855_switch_priv *priv, u32 port) +{ + u32 val = 0; + + if (port != 5) { + printf("an8855: port %d is not a SGMII port\n", port); + return -EINVAL; + } + + /* PLL */ + an8855_reg_read(priv, AN8855_QP_DIG_MODE_CTRL_1, &val); + val &= ~(0x3 << 2); + val |= (0x1 << 2); + an8855_reg_write(priv, AN8855_QP_DIG_MODE_CTRL_1, val); + + /* PLL - LPF */ + an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); + val &= ~(0x3 << 0); + val |= (0x1 << 0); + val &= ~(0x7 << 2); + val |= (0x5 << 2); + val &= ~GENMASK(7, 6); + val &= ~(0x7 << 8); + val |= (0x3 << 8); + val |= BIT(29); + val &= ~GENMASK(13, 12); + an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); + + /* PLL - ICO */ + an8855_reg_read(priv, AN8855_PLL_CTRL_4, &val); + val |= BIT(2); + an8855_reg_write(priv, AN8855_PLL_CTRL_4, val); + + an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); + val &= ~BIT(14); + an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); + + /* PLL - CHP */ + an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); + val &= ~(0xf << 16); + val |= (0x6 << 16); + an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); + + /* PLL - PFD */ + an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); + val &= ~(0x3 << 20); + val |= (0x1 << 20); + val &= ~(0x3 << 24); + val |= (0x1 << 24); + val &= ~BIT(26); + an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); + + /* PLL - POSTDIV */ + an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); + val |= BIT(22); + val &= ~BIT(27); + val &= ~BIT(28); + an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); + + /* PLL - SDM */ + an8855_reg_read(priv, AN8855_PLL_CTRL_4, &val); + val &= ~GENMASK(4, 3); + an8855_reg_write(priv, AN8855_PLL_CTRL_4, val); + + an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); + val &= ~BIT(30); + an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); + + an8855_reg_read(priv, AN8855_SS_LCPLL_PWCTL_SETTING_2, &val); + val &= ~(0x3 << 16); + val |= (0x1 << 16); + an8855_reg_write(priv, AN8855_SS_LCPLL_PWCTL_SETTING_2, val); + + an8855_reg_write(priv, AN8855_SS_LCPLL_TDC_FLT_2, 0x7a000000); + an8855_reg_write(priv, AN8855_SS_LCPLL_TDC_PCW_1, 0x7a000000); + + an8855_reg_read(priv, AN8855_SS_LCPLL_TDC_FLT_5, &val); + val &= ~BIT(24); + an8855_reg_write(priv, AN8855_SS_LCPLL_TDC_FLT_5, val); + + an8855_reg_read(priv, AN8855_PLL_CK_CTRL_0, &val); + val &= ~BIT(8); + an8855_reg_write(priv, AN8855_PLL_CK_CTRL_0, val); + + /* PLL - SS */ + an8855_reg_read(priv, AN8855_PLL_CTRL_3, &val); + val &= ~GENMASK(15, 0); + an8855_reg_write(priv, AN8855_PLL_CTRL_3, val); + + an8855_reg_read(priv, AN8855_PLL_CTRL_4, &val); + val &= ~GENMASK(1, 0); + an8855_reg_write(priv, AN8855_PLL_CTRL_4, val); + + an8855_reg_read(priv, AN8855_PLL_CTRL_3, &val); + val &= ~GENMASK(31, 16); + an8855_reg_write(priv, AN8855_PLL_CTRL_3, val); + + /* PLL - TDC */ + an8855_reg_read(priv, AN8855_PLL_CK_CTRL_0, &val); + val &= ~BIT(9); + an8855_reg_write(priv, AN8855_PLL_CK_CTRL_0, val); + + an8855_reg_read(priv, AN8855_RG_QP_PLL_SDM_ORD, &val); + val |= BIT(3); + val |= BIT(4); + an8855_reg_write(priv, AN8855_RG_QP_PLL_SDM_ORD, val); + + an8855_reg_read(priv, AN8855_RG_QP_RX_DAC_EN, &val); + val &= ~(0x3 << 16); + val |= (0x2 << 16); + an8855_reg_write(priv, AN8855_RG_QP_RX_DAC_EN, val); + + /* TCL Disable (only for Co-SIM) */ + an8855_reg_read(priv, AN8855_PON_RXFEDIG_CTRL_0, &val); + val &= ~BIT(12); + an8855_reg_write(priv, AN8855_PON_RXFEDIG_CTRL_0, val); + + /* TX Init */ + an8855_reg_read(priv, AN8855_RG_QP_TX_MODE_16B_EN, &val); + val &= ~BIT(0); + val &= ~(0xffff << 16); + val |= (0x4 << 16); + an8855_reg_write(priv, AN8855_RG_QP_TX_MODE_16B_EN, val); + + /* RX Control */ + an8855_reg_read(priv, AN8855_RG_QP_RXAFE_RESERVE, &val); + val |= BIT(11); + an8855_reg_write(priv, AN8855_RG_QP_RXAFE_RESERVE, val); + + an8855_reg_read(priv, AN8855_RG_QP_CDR_LPF_MJV_LIM, &val); + val &= ~(0x3 << 4); + val |= (0x1 << 4); + an8855_reg_write(priv, AN8855_RG_QP_CDR_LPF_MJV_LIM, val); + + an8855_reg_read(priv, AN8855_RG_QP_CDR_LPF_SETVALUE, &val); + val &= ~(0xf << 25); + val |= (0x1 << 25); + val &= ~(0x7 << 29); + val |= (0x3 << 29); + an8855_reg_write(priv, AN8855_RG_QP_CDR_LPF_SETVALUE, val); + + an8855_reg_read(priv, AN8855_RG_QP_CDR_PR_CKREF_DIV1, &val); + val &= ~(0x1f << 8); + val |= (0xf << 8); + an8855_reg_write(priv, AN8855_RG_QP_CDR_PR_CKREF_DIV1, val); + + an8855_reg_read(priv, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, &val); + val &= ~(0x3f << 0); + val |= (0x19 << 0); + val &= ~BIT(6); + an8855_reg_write(priv, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, val); + + an8855_reg_read(priv, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF, &val); + val &= ~(0x7f << 6); + val |= (0x21 << 6); + val &= ~(0x3 << 16); + val |= (0x2 << 16); + val &= ~BIT(13); + an8855_reg_write(priv, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF, val); + + an8855_reg_read(priv, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, &val); + val &= ~BIT(30); + an8855_reg_write(priv, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, val); + + an8855_reg_read(priv, AN8855_RG_QP_CDR_PR_CKREF_DIV1, &val); + val &= ~(0x7 << 24); + val |= (0x4 << 24); + an8855_reg_write(priv, AN8855_RG_QP_CDR_PR_CKREF_DIV1, val); + + an8855_reg_read(priv, AN8855_PLL_CTRL_0, &val); + val |= BIT(0); + an8855_reg_write(priv, AN8855_PLL_CTRL_0, val); + + an8855_reg_read(priv, AN8855_RX_CTRL_26, &val); + val &= ~BIT(23); + val |= BIT(26); + an8855_reg_write(priv, AN8855_RX_CTRL_26, val); + + an8855_reg_read(priv, AN8855_RX_DLY_0, &val); + val &= ~(0xff << 0); + val |= (0x6f << 0); + val |= GENMASK(13, 8); + an8855_reg_write(priv, AN8855_RX_DLY_0, val); + + an8855_reg_read(priv, AN8855_RX_CTRL_42, &val); + val &= ~(0x1fff << 0); + val |= (0x150 << 0); + an8855_reg_write(priv, AN8855_RX_CTRL_42, val); + + an8855_reg_read(priv, AN8855_RX_CTRL_2, &val); + val &= ~(0x1fff << 16); + val |= (0x150 << 16); + an8855_reg_write(priv, AN8855_RX_CTRL_2, val); + + an8855_reg_read(priv, AN8855_PON_RXFEDIG_CTRL_9, &val); + val &= ~(0x7 << 0); + val |= (0x1 << 0); + an8855_reg_write(priv, AN8855_PON_RXFEDIG_CTRL_9, val); + + an8855_reg_read(priv, AN8855_RX_CTRL_8, &val); + val &= ~(0xfff << 16); + val |= (0x200 << 16); + val &= ~(0x7fff << 14); + val |= (0xfff << 14); + an8855_reg_write(priv, AN8855_RX_CTRL_8, val); + + /* Frequency memter */ + an8855_reg_read(priv, AN8855_RX_CTRL_5, &val); + val &= ~(0xfffff << 10); + val |= (0x10 << 10); + an8855_reg_write(priv, AN8855_RX_CTRL_5, val); + + an8855_reg_read(priv, AN8855_RX_CTRL_6, &val); + val &= ~(0xfffff << 0); + val |= (0x64 << 0); + an8855_reg_write(priv, AN8855_RX_CTRL_6, val); + + an8855_reg_read(priv, AN8855_RX_CTRL_7, &val); + val &= ~(0xfffff << 0); + val |= (0x2710 << 0); + an8855_reg_write(priv, AN8855_RX_CTRL_7, val); + + /* PCS Init */ + an8855_reg_read(priv, AN8855_RG_HSGMII_PCS_CTROL_1, &val); + val &= ~BIT(30); + an8855_reg_write(priv, AN8855_RG_HSGMII_PCS_CTROL_1, val); + + /* Rate Adaption */ + an8855_reg_read(priv, AN8855_RATE_ADP_P0_CTRL_0, &val); + val &= ~BIT(31); + an8855_reg_write(priv, AN8855_RATE_ADP_P0_CTRL_0, val); + + an8855_reg_read(priv, AN8855_RG_RATE_ADAPT_CTRL_0, &val); + val |= BIT(0); + val |= BIT(4); + val |= GENMASK(27, 26); + an8855_reg_write(priv, AN8855_RG_RATE_ADAPT_CTRL_0, val); + + /* Disable AN */ + an8855_reg_read(priv, AN8855_SGMII_REG_AN0, &val); + val &= ~BIT(12); + an8855_reg_write(priv, AN8855_SGMII_REG_AN0, val); + + /* Force Speed */ + an8855_reg_read(priv, AN8855_SGMII_STS_CTRL_0, &val); + val |= BIT(2); + val |= GENMASK(5, 4); + an8855_reg_write(priv, AN8855_SGMII_STS_CTRL_0, val); + + /* bypass flow control to MAC */ + an8855_reg_write(priv, AN8855_MSG_RX_LIK_STS_0, 0x01010107); + an8855_reg_write(priv, AN8855_MSG_RX_LIK_STS_2, 0x00000EEF); + + return 0; +} + +static void an8855_led_set_usr_def(struct an8855_switch_priv *priv, u8 entity, + enum an8855_led_polarity pol, u16 on_evt, + u16 blk_evt, u8 led_freq) +{ + u32 cl45_data; + + if (pol == LED_HIGH) + on_evt |= LED_ON_POL; + else + on_evt &= ~LED_ON_POL; + + /* LED on event */ + an8855_phy_cl45_write(priv, (entity / 4), 0x1e, + PHY_SINGLE_LED_ON_CTRL(entity % 4), + on_evt | LED_ON_EN); + + /* LED blink event */ + an8855_phy_cl45_write(priv, (entity / 4), 0x1e, + PHY_SINGLE_LED_BLK_CTRL(entity % 4), + blk_evt); + + /* LED freq */ + switch (led_freq) { + case AIR_LED_BLK_DUR_32M: + cl45_data = 0x30e; + break; + + case AIR_LED_BLK_DUR_64M: + cl45_data = 0x61a; + break; + + case AIR_LED_BLK_DUR_128M: + cl45_data = 0xc35; + break; + + case AIR_LED_BLK_DUR_256M: + cl45_data = 0x186a; + break; + + case AIR_LED_BLK_DUR_512M: + cl45_data = 0x30d4; + break; + + case AIR_LED_BLK_DUR_1024M: + cl45_data = 0x61a8; + break; + + default: + cl45_data = 0; + break; + } + + an8855_phy_cl45_write(priv, (entity / 4), 0x1e, + PHY_SINGLE_LED_BLK_DUR(entity % 4), + cl45_data); + + an8855_phy_cl45_write(priv, (entity / 4), 0x1e, + PHY_SINGLE_LED_ON_DUR(entity % 4), + (cl45_data >> 1)); + + /* Disable DATA & BAD_SSD for port LED blink behavior */ + cl45_data = mtk_mmd_ind_read(priv->epriv.eth, (entity / 4), 0x1e, PHY_PMA_CTRL); + cl45_data &= ~BIT(0); + cl45_data &= ~BIT(15); + an8855_phy_cl45_write(priv, (entity / 4), 0x1e, PHY_PMA_CTRL, cl45_data); +} + +static int an8855_led_set_mode(struct an8855_switch_priv *priv, u8 mode) +{ + u16 cl45_data; + + an8855_phy_cl45_read(priv, 0, 0x1f, PHY_LED_BCR, &cl45_data); + + switch (mode) { + case AN8855_LED_MODE_DISABLE: + cl45_data &= ~LED_BCR_EXT_CTRL; + cl45_data &= ~LED_BCR_MODE_MASK; + cl45_data |= LED_BCR_MODE_DISABLE; + break; + + case AN8855_LED_MODE_USER_DEFINE: + cl45_data |= LED_BCR_EXT_CTRL; + cl45_data |= LED_BCR_CLK_EN; + break; + + default: + printf("an8855: LED mode%d is not supported!\n", mode); + return -EINVAL; + } + + an8855_phy_cl45_write(priv, 0, 0x1f, PHY_LED_BCR, cl45_data); + + return 0; +} + +static int an8855_led_set_state(struct an8855_switch_priv *priv, u8 entity, + u8 state) +{ + u16 cl45_data = 0; + + /* Change to per port contorl */ + an8855_phy_cl45_read(priv, (entity / 4), 0x1e, PHY_LED_CTRL_SELECT, + &cl45_data); + + if (state == 1) + cl45_data |= (1 << (entity % 4)); + else + cl45_data &= ~(1 << (entity % 4)); + + an8855_phy_cl45_write(priv, (entity / 4), 0x1e, PHY_LED_CTRL_SELECT, + cl45_data); + + /* LED enable setting */ + an8855_phy_cl45_read(priv, (entity / 4), 0x1e, + PHY_SINGLE_LED_ON_CTRL(entity % 4), &cl45_data); + + if (state == 1) + cl45_data |= LED_ON_EN; + else + cl45_data &= ~LED_ON_EN; + + an8855_phy_cl45_write(priv, (entity / 4), 0x1e, + PHY_SINGLE_LED_ON_CTRL(entity % 4), cl45_data); + + return 0; +} + +static int an8855_led_init(struct an8855_switch_priv *priv) +{ + u32 val, id, tmp_id = 0; + int ret; + + ret = an8855_led_set_mode(priv, AN8855_LED_MODE_USER_DEFINE); + if (ret) { + printf("an8855: led_set_mode failed with %d!\n", ret); + return ret; + } + + for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { + ret = an8855_led_set_state(priv, led_cfg[id].phy_led_idx, + led_cfg[id].en); + if (ret != 0) { + printf("an8855: led_set_state failed with %d!\n", ret); + return ret; + } + + if (led_cfg[id].en == 1) { + an8855_led_set_usr_def(priv, + led_cfg[id].phy_led_idx, + led_cfg[id].pol, + led_cfg[id].on_cfg, + led_cfg[id].blk_cfg, + led_cfg[id].led_freq); + } + } + + /* Setting for System LED & Loop LED */ + an8855_reg_write(priv, AN8855_RG_GPIO_OE, 0x0); + an8855_reg_write(priv, AN8855_RG_GPIO_CTRL, 0x0); + an8855_reg_write(priv, AN8855_RG_GPIO_L_INV, 0); + + an8855_reg_write(priv, AN8855_RG_GPIO_CTRL, 0x1001); + an8855_reg_read(priv, AN8855_RG_GPIO_DATA, &val); + val |= GENMASK(3, 1); + val &= ~(BIT(0)); + val &= ~(BIT(6)); + an8855_reg_write(priv, AN8855_RG_GPIO_DATA, val); + + an8855_reg_read(priv, AN8855_RG_GPIO_OE, &val); + val |= 0x41; + an8855_reg_write(priv, AN8855_RG_GPIO_OE, val); + + /* Mapping between GPIO & LED */ + val = 0; + for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { + /* Skip GPIO6, due to GPIO6 does not support PORT LED */ + if (id == 6) + continue; + + if (led_cfg[id].en == 1) { + if (id < 7) + val |= led_cfg[id].phy_led_idx << ((id % 4) * 8); + else + val |= led_cfg[id].phy_led_idx << (((id - 1) % 4) * 8); + } + + if (id < 7) + tmp_id = id; + else + tmp_id = id - 1; + + if ((tmp_id % 4) == 0x3) { + an8855_reg_write(priv, + AN8855_RG_GPIO_LED_SEL(tmp_id / 4), + val); + val = 0; + } + } + + /* Turn on LAN LED mode */ + val = 0; + for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { + if (led_cfg[id].en == 1) + val |= 0x1 << id; + } + an8855_reg_write(priv, AN8855_RG_GPIO_LED_MODE, val); + + /* Force clear blink pulse for per port LED */ + an8855_phy_cl45_write(priv, 0, 0x1f, PHY_LED_BLINK_DUR_CTRL, 0x1f); + udelay(1000); + an8855_phy_cl45_write(priv, 0, 0x1f, PHY_LED_BLINK_DUR_CTRL, 0); + + return 0; +} + +static void an8855_port_isolation(struct an8855_switch_priv *priv) +{ + u32 i; + + for (i = 0; i < AN8855_NUM_PORTS; i++) { + /* Set port matrix mode */ + if (i != 5) + an8855_reg_write(priv, AN8855_PORTMATRIX_REG(i), 0x20); + else + an8855_reg_write(priv, AN8855_PORTMATRIX_REG(i), 0x1f); + + /* Set port mode to user port */ + an8855_reg_write(priv, AN8855_PVC(i), + (0x8100 << AN8855_STAG_VPID_S) | + (VLAN_ATTR_USER << AN8855_VLAN_ATTR_S)); + } +} + +static void an8855_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable) +{ + struct an8855_switch_priv *priv = (struct an8855_switch_priv *)swpriv; + u32 pmcr = AN8855_FORCE_MODE_LNK; + + if (enable) + pmcr = AN8855_FORCE_MODE; + + an8855_reg_write(priv, AN8855_PMCR_REG(5), pmcr); +} + +static int an8855_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct an8855_switch_priv *priv = bus->priv; + + if (devad < 0) + return mtk_mii_read(priv->epriv.eth, addr, reg); + + return mtk_mmd_ind_read(priv->epriv.eth, addr, devad, reg); +} + +static int an8855_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct an8855_switch_priv *priv = bus->priv; + + if (devad < 0) + return mtk_mii_write(priv->epriv.eth, addr, reg, val); + + return mtk_mmd_ind_write(priv->epriv.eth, addr, devad, reg, val); +} + +static int an8855_mdio_register(struct an8855_switch_priv *priv) +{ + struct mii_dev *mdio_bus = mdio_alloc(); + int ret; + + if (!mdio_bus) + return -ENOMEM; + + mdio_bus->read = an8855_mdio_read; + mdio_bus->write = an8855_mdio_write; + snprintf(mdio_bus->name, sizeof(mdio_bus->name), priv->epriv.sw->name); + + mdio_bus->priv = priv; + + ret = mdio_register(mdio_bus); + if (ret) { + mdio_free(mdio_bus); + return ret; + } + + priv->mdio_bus = mdio_bus; + + return 0; +} + +static int an8855_setup(struct mtk_eth_switch_priv *swpriv) +{ + struct an8855_switch_priv *priv = (struct an8855_switch_priv *)swpriv; + u16 phy_addr, phy_val; + u32 i, id, val = 0; + int ret; + + priv->phy_base = 1; + + /* Turn off PHYs */ + for (i = 0; i < AN8855_NUM_PHYS; i++) { + phy_addr = AN8855_PHY_ADDR(priv->phy_base, i); + phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR); + phy_val |= BMCR_PDOWN; + mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val); + } + + /* Force MAC link down before reset */ + an8855_reg_write(priv, AN8855_PMCR_REG(5), AN8855_FORCE_MODE_LNK); + + /* Switch soft reset */ + an8855_reg_write(priv, AN8855_SYS_CTRL_REG, AN8855_SW_SYS_RST); + udelay(100000); + + an8855_reg_read(priv, AN8855_PKG_SEL, &val); + if ((val & 0x7) == PAG_SEL_AN8855H) { + /* Release power down */ + an8855_reg_write(priv, RG_GPHY_AFE_PWD, 0x0); + + /* Invert for LED activity change */ + an8855_reg_read(priv, AN8855_RG_GPIO_L_INV, &val); + for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { + if ((led_cfg[id].pol == LED_HIGH) && + (led_cfg[id].en == 1)) + val |= 0x1 << id; + } + an8855_reg_write(priv, AN8855_RG_GPIO_L_INV, (val | 0x1)); + + /* MCU NOP CMD */ + an8855_reg_write(priv, AN8855_RG_GDMP_RAM, 0x846); + an8855_reg_write(priv, AN8855_RG_GDMP_RAM + 4, 0x4a); + + /* Enable MCU */ + an8855_reg_read(priv, AN8855_RG_CLK_CPU_ICG, &val); + an8855_reg_write(priv, AN8855_RG_CLK_CPU_ICG, + val | AN8855_MCU_ENABLE); + udelay(1000); + + /* Disable MCU watchdog */ + an8855_reg_read(priv, AN8855_RG_TIMER_CTL, &val); + an8855_reg_write(priv, AN8855_RG_TIMER_CTL, + (val & (~AN8855_WDOG_ENABLE))); + + /* LED settings for T830 reference board */ + ret = an8855_led_init(priv); + if (ret < 0) { + printf("an8855: an8855_led_init failed with %d\n", ret); + return ret; + } + } + + switch (priv->epriv.phy_interface) { + case PHY_INTERFACE_MODE_2500BASEX: + an8855_port_sgmii_init(priv, 5); + break; + + default: + break; + } + + an8855_reg_read(priv, AN8855_CKGCR, &val); + val &= ~(0x3); + an8855_reg_write(priv, AN8855_CKGCR, val); + + /* Enable port isolation to block inter-port communication */ + an8855_port_isolation(priv); + + /* Turn on PHYs */ + for (i = 0; i < AN8855_NUM_PHYS; i++) { + phy_addr = AN8855_PHY_ADDR(priv->phy_base, i); + phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR); + phy_val &= ~BMCR_PDOWN; + mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val); + } + + return an8855_mdio_register(priv); +} + +static int an8855_cleanup(struct mtk_eth_switch_priv *swpriv) +{ + struct an8855_switch_priv *priv = (struct an8855_switch_priv *)swpriv; + + mdio_unregister(priv->mdio_bus); + + return 0; +} + +static int an8855_detect(struct mtk_eth_priv *priv) +{ + int ret; + u32 val; + + ret = __an8855_reg_read(priv, 1, 0x10005000, &val); + if (ret) + return ret; + + if (val == 0x8855) + return 0; + + return -ENODEV; +} + +MTK_ETH_SWITCH(an8855) = { + .name = "an8855", + .desc = "Airoha AN8855", + .priv_size = sizeof(struct an8855_switch_priv), + .reset_wait_time = 100, + + .detect = an8855_detect, + .setup = an8855_setup, + .cleanup = an8855_cleanup, + .mac_control = an8855_mac_control, +}; diff --git a/drivers/net/mtk_eth/mt7530.c b/drivers/net/mtk_eth/mt7530.c new file mode 100644 index 00000000000..3065d35e126 --- /dev/null +++ b/drivers/net/mtk_eth/mt7530.c @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + * Author: Mark Lee <mark-mc.lee@mediatek.com> + */ + +#include <miiphy.h> +#include <linux/delay.h> +#include <linux/mdio.h> +#include <linux/mii.h> +#include "mtk_eth.h" +#include "mt753x.h" + +#define CHIP_REV 0x7ffc +#define CHIP_NAME_S 16 +#define CHIP_NAME_M 0xffff0000 +#define CHIP_REV_S 0 +#define CHIP_REV_M 0x0f + +static void mt7530_core_reg_write(struct mt753x_switch_priv *priv, u32 reg, + u32 val) +{ + u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0); + + mtk_mmd_ind_write(priv->epriv.eth, phy_addr, 0x1f, reg, val); +} + +static int mt7530_pad_clk_setup(struct mt753x_switch_priv *priv, int mode) +{ + u32 ncpo1, ssc_delta; + + switch (mode) { + case PHY_INTERFACE_MODE_RGMII: + ncpo1 = 0x0c80; + ssc_delta = 0x87; + break; + + default: + printf("error: xMII mode %d is not supported\n", mode); + return -EINVAL; + } + + /* Disable MT7530 core clock */ + mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0); + + /* Disable MT7530 PLL */ + mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1, + (2 << RG_GSWPLL_POSDIV_200M_S) | + (32 << RG_GSWPLL_FBKDIV_200M_S)); + + /* For MT7530 core clock = 500Mhz */ + mt7530_core_reg_write(priv, CORE_GSWPLL_GRP2, + (1 << RG_GSWPLL_POSDIV_500M_S) | + (25 << RG_GSWPLL_FBKDIV_500M_S)); + + /* Enable MT7530 PLL */ + mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1, + (2 << RG_GSWPLL_POSDIV_200M_S) | + (32 << RG_GSWPLL_FBKDIV_200M_S) | + RG_GSWPLL_EN_PRE); + + udelay(20); + + mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); + + /* Setup the MT7530 TRGMII Tx Clock */ + mt7530_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1); + mt7530_core_reg_write(priv, CORE_PLL_GROUP6, 0); + mt7530_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta); + mt7530_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta); + mt7530_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | + RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); + + mt7530_core_reg_write(priv, CORE_PLL_GROUP2, + RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | + (1 << RG_SYSPLL_POSDIV_S)); + + mt7530_core_reg_write(priv, CORE_PLL_GROUP7, + RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) | + RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); + + /* Enable MT7530 core clock */ + mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, + REG_GSWCK_EN | REG_TRGMIICK_EN); + + return 0; +} + +static void mt7530_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + u32 pmcr = FORCE_MODE; + + if (enable) + pmcr = priv->pmcr; + + mt753x_reg_write(priv, PMCR_REG(6), pmcr); +} + +static int mt7530_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct mt753x_switch_priv *priv = bus->priv; + + if (devad < 0) + return mtk_mii_read(priv->epriv.eth, addr, reg); + + return mtk_mmd_ind_read(priv->epriv.eth, addr, devad, reg); +} + +static int mt7530_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct mt753x_switch_priv *priv = bus->priv; + + if (devad < 0) + return mtk_mii_write(priv->epriv.eth, addr, reg, val); + + return mtk_mmd_ind_write(priv->epriv.eth, addr, devad, reg, val); +} + +static int mt7530_mdio_register(struct mt753x_switch_priv *priv) +{ + struct mii_dev *mdio_bus = mdio_alloc(); + int ret; + + if (!mdio_bus) + return -ENOMEM; + + mdio_bus->read = mt7530_mdio_read; + mdio_bus->write = mt7530_mdio_write; + snprintf(mdio_bus->name, sizeof(mdio_bus->name), priv->epriv.sw->name); + + mdio_bus->priv = priv; + + ret = mdio_register(mdio_bus); + if (ret) { + mdio_free(mdio_bus); + return ret; + } + + priv->mdio_bus = mdio_bus; + + return 0; +} + +static int mt7530_setup(struct mtk_eth_switch_priv *swpriv) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + u16 phy_addr, phy_val; + u32 i, val, txdrv; + + priv->smi_addr = MT753X_DFL_SMI_ADDR; + priv->reg_read = mt753x_mdio_reg_read; + priv->reg_write = mt753x_mdio_reg_write; + + if (!MTK_HAS_CAPS(priv->epriv.soc->caps, MTK_TRGMII_MT7621_CLK)) { + /* Select 250MHz clk for RGMII mode */ + mtk_ethsys_rmw(priv->epriv.eth, ETHSYS_CLKCFG0_REG, + ETHSYS_TRGMII_CLK_SEL362_5, 0); + + txdrv = 8; + } else { + txdrv = 4; + } + + /* Modify HWTRAP first to allow direct access to internal PHYs */ + mt753x_reg_read(priv, HWTRAP_REG, &val); + val |= CHG_TRAP; + val &= ~C_MDIO_BPS; + mt753x_reg_write(priv, MHWTRAP_REG, val); + + /* Calculate the phy base address */ + val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3; + priv->phy_base = (val | 0x7) + 1; + + /* Turn off PHYs */ + for (i = 0; i < MT753X_NUM_PHYS; i++) { + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); + phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR); + phy_val |= BMCR_PDOWN; + mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val); + } + + /* Force MAC link down before reset */ + mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); + mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); + + /* MT7530 reset */ + mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); + udelay(100); + + val = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | + MAC_MODE | FORCE_MODE | + MAC_TX_EN | MAC_RX_EN | + BKOFF_EN | BACKPR_EN | + (SPEED_1000M << FORCE_SPD_S) | + FORCE_DPX | FORCE_LINK; + + /* MT7530 Port6: Forced 1000M/FD, FC disabled */ + priv->pmcr = val; + + /* MT7530 Port5: Forced link down */ + mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); + + /* Keep MAC link down before starting eth */ + mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); + + /* MT7530 Port6: Set to RGMII */ + mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII); + + /* Hardware Trap: Enable Port6, Disable Port5 */ + mt753x_reg_read(priv, HWTRAP_REG, &val); + val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS | + (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) | + (P5_INTF_MODE_RGMII << P5_INTF_MODE_S); + val &= ~(C_MDIO_BPS | P6_INTF_DIS); + mt753x_reg_write(priv, MHWTRAP_REG, val); + + /* Setup switch core pll */ + mt7530_pad_clk_setup(priv, priv->epriv.phy_interface); + + /* Lower Tx Driving for TRGMII path */ + for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) + mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i), + (txdrv << TD_DM_DRVP_S) | + (txdrv << TD_DM_DRVN_S)); + + for (i = 0 ; i < NUM_TRGMII_CTRL; i++) + mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16); + + /* Enable port isolation to block inter-port communication */ + mt753x_port_isolation(priv); + + /* Turn on PHYs */ + for (i = 0; i < MT753X_NUM_PHYS; i++) { + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); + phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR); + phy_val &= ~BMCR_PDOWN; + mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val); + } + + return mt7530_mdio_register(priv); +} + +static int mt7530_cleanup(struct mtk_eth_switch_priv *swpriv) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + + mdio_unregister(priv->mdio_bus); + + return 0; +} + +static int mt7530_detect(struct mtk_eth_priv *priv) +{ + int ret; + u32 rev; + + ret = __mt753x_mdio_reg_read(priv, MT753X_DFL_SMI_ADDR, CHIP_REV, &rev); + if (ret) + return ret; + + if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == 0x7530) + return 0; + + return -ENODEV; +} + +MTK_ETH_SWITCH(mt7530) = { + .name = "mt7530", + .desc = "MediaTek MT7530", + .priv_size = sizeof(struct mt753x_switch_priv), + .reset_wait_time = 1000, + + .detect = mt7530_detect, + .setup = mt7530_setup, + .cleanup = mt7530_cleanup, + .mac_control = mt7530_mac_control, +}; diff --git a/drivers/net/mtk_eth/mt7531.c b/drivers/net/mtk_eth/mt7531.c new file mode 100644 index 00000000000..32d6bebbbdb --- /dev/null +++ b/drivers/net/mtk_eth/mt7531.c @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + * Author: Mark Lee <mark-mc.lee@mediatek.com> + */ + +#include <miiphy.h> +#include <linux/delay.h> +#include <linux/mdio.h> +#include <linux/mii.h> +#include "mtk_eth.h" +#include "mt753x.h" + +#define CHIP_REV 0x781C +#define CHIP_NAME_S 16 +#define CHIP_NAME_M 0xffff0000 +#define CHIP_REV_S 0 +#define CHIP_REV_M 0x0f +#define CHIP_REV_E1 0x0 + +static int mt7531_core_reg_read(struct mt753x_switch_priv *priv, u32 reg) +{ + u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0); + + return mt7531_mmd_read(priv, phy_addr, 0x1f, reg); +} + +static void mt7531_core_reg_write(struct mt753x_switch_priv *priv, u32 reg, + u32 val) +{ + u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0); + + mt7531_mmd_write(priv, phy_addr, 0x1f, reg, val); +} + +static void mt7531_core_pll_setup(struct mt753x_switch_priv *priv) +{ + /* Step 1 : Disable MT7531 COREPLL */ + mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, 0); + + /* Step 2: switch to XTAL output */ + mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_CLKSW, SW_CLKSW); + + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, 0); + + /* Step 3: disable PLLGP and enable program PLLGP */ + mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_PLLGP, SW_PLLGP); + + /* Step 4: program COREPLL output frequency to 500MHz */ + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_POSDIV_M, + 2 << RG_COREPLL_POSDIV_S); + udelay(25); + + /* Currently, support XTAL 25Mhz only */ + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_M, + 0x140000 << RG_COREPLL_SDM_PCW_S); + + /* Set feedback divide ratio update signal to high */ + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, + RG_COREPLL_SDM_PCW_CHG); + + /* Wait for at least 16 XTAL clocks */ + udelay(10); + + /* Step 5: set feedback divide ratio update signal to low */ + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, 0); + + /* add enable 325M clock for SGMII */ + mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); + + /* add enable 250SSC clock for RGMII */ + mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); + + /*Step 6: Enable MT7531 PLL */ + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, RG_COREPLL_EN); + + mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, EN_COREPLL); + + udelay(25); +} + +static int mt7531_port_sgmii_init(struct mt753x_switch_priv *priv, u32 port) +{ + if (port != 5 && port != 6) { + printf("mt7531: port %d is not a SGMII port\n", port); + return -EINVAL; + } + + /* Set SGMII GEN2 speed(2.5G) */ + mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK, + FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); + + /* Disable SGMII AN */ + mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port), + SGMII_AN_ENABLE, 0); + + /* SGMII force mode setting */ + mt753x_reg_write(priv, MT7531_SGMII_MODE(port), SGMII_FORCE_MODE); + + /* Release PHYA power down state */ + mt753x_reg_rmw(priv, MT7531_QPHY_PWR_STATE_CTRL(port), + SGMII_PHYA_PWD, 0); + + return 0; +} + +static int mt7531_port_rgmii_init(struct mt753x_switch_priv *priv, u32 port) +{ + u32 val; + + if (port != 5) { + printf("error: RGMII mode is not available for port %d\n", + port); + return -EINVAL; + } + + mt753x_reg_read(priv, MT7531_CLKGEN_CTRL, &val); + val |= GP_CLK_EN; + val &= ~GP_MODE_M; + val |= GP_MODE_RGMII << GP_MODE_S; + val |= TXCLK_NO_REVERSE; + val |= RXCLK_NO_DELAY; + val &= ~CLK_SKEW_IN_M; + val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S; + val &= ~CLK_SKEW_OUT_M; + val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S; + mt753x_reg_write(priv, MT7531_CLKGEN_CTRL, val); + + return 0; +} + +static void mt7531_phy_setting(struct mt753x_switch_priv *priv) +{ + int i; + u32 val; + + for (i = 0; i < MT753X_NUM_PHYS; i++) { + /* Enable HW auto downshift */ + mt7531_mii_write(priv, i, 0x1f, 0x1); + val = mt7531_mii_read(priv, i, PHY_EXT_REG_14); + val |= PHY_EN_DOWN_SHFIT; + mt7531_mii_write(priv, i, PHY_EXT_REG_14, val); + + /* PHY link down power saving enable */ + val = mt7531_mii_read(priv, i, PHY_EXT_REG_17); + val |= PHY_LINKDOWN_POWER_SAVING_EN; + mt7531_mii_write(priv, i, PHY_EXT_REG_17, val); + + val = mt7531_mmd_read(priv, i, 0x1e, PHY_DEV1E_REG_0C6); + val &= ~PHY_POWER_SAVING_M; + val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S; + mt7531_mmd_write(priv, i, 0x1e, PHY_DEV1E_REG_0C6, val); + } +} + +static void mt7531_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + u32 pmcr = FORCE_MODE_LNK; + + if (enable) + pmcr = priv->pmcr; + + mt753x_reg_write(priv, PMCR_REG(5), pmcr); + mt753x_reg_write(priv, PMCR_REG(6), pmcr); +} + +static int mt7531_setup(struct mtk_eth_switch_priv *swpriv) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + u32 i, val, pmcr, port5_sgmii; + u16 phy_addr, phy_val; + + priv->smi_addr = MT753X_DFL_SMI_ADDR; + priv->phy_base = (priv->smi_addr + 1) & MT753X_SMI_ADDR_MASK; + priv->reg_read = mt753x_mdio_reg_read; + priv->reg_write = mt753x_mdio_reg_write; + + /* Turn off PHYs */ + for (i = 0; i < MT753X_NUM_PHYS; i++) { + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); + phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR); + phy_val |= BMCR_PDOWN; + mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val); + } + + /* Force MAC link down before reset */ + mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); + mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); + + /* Switch soft reset */ + mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); + udelay(100); + + /* Enable MDC input Schmitt Trigger */ + mt753x_reg_rmw(priv, MT7531_SMT0_IOLB, SMT_IOLB_5_SMI_MDC_EN, + SMT_IOLB_5_SMI_MDC_EN); + + mt7531_core_pll_setup(priv); + + mt753x_reg_read(priv, MT7531_TOP_SIG_SR, &val); + port5_sgmii = !!(val & PAD_DUAL_SGMII_EN); + + /* port5 support either RGMII or SGMII, port6 only support SGMII. */ + switch (priv->epriv.phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + if (!port5_sgmii) + mt7531_port_rgmii_init(priv, 5); + break; + + case PHY_INTERFACE_MODE_2500BASEX: + mt7531_port_sgmii_init(priv, 6); + if (port5_sgmii) + mt7531_port_sgmii_init(priv, 5); + break; + + default: + break; + } + + pmcr = MT7531_FORCE_MODE | + (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | + MAC_MODE | MAC_TX_EN | MAC_RX_EN | + BKOFF_EN | BACKPR_EN | + FORCE_RX_FC | FORCE_TX_FC | + (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | + FORCE_LINK; + + priv->pmcr = pmcr; + + /* Keep MAC link down before starting eth */ + mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); + mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); + + /* Enable port isolation to block inter-port communication */ + mt753x_port_isolation(priv); + + /* Turn on PHYs */ + for (i = 0; i < MT753X_NUM_PHYS; i++) { + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); + phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR); + phy_val &= ~BMCR_PDOWN; + mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val); + } + + mt7531_phy_setting(priv); + + /* Enable Internal PHYs */ + val = mt7531_core_reg_read(priv, CORE_PLL_GROUP4); + val |= MT7531_BYPASS_MODE; + val &= ~MT7531_POWER_ON_OFF; + mt7531_core_reg_write(priv, CORE_PLL_GROUP4, val); + + return mt7531_mdio_register(priv); +} + +static int mt7531_cleanup(struct mtk_eth_switch_priv *swpriv) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + + mdio_unregister(priv->mdio_bus); + + return 0; +} + +static int mt7531_detect(struct mtk_eth_priv *priv) +{ + int ret; + u32 rev; + + ret = __mt753x_mdio_reg_read(priv, MT753X_DFL_SMI_ADDR, CHIP_REV, &rev); + if (ret) + return ret; + + if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == 0x7531) + return 0; + + return -ENODEV; +} + +MTK_ETH_SWITCH(mt7531) = { + .name = "mt7531", + .desc = "MediaTek MT7531", + .priv_size = sizeof(struct mt753x_switch_priv), + .reset_wait_time = 200, + + .detect = mt7531_detect, + .setup = mt7531_setup, + .cleanup = mt7531_cleanup, + .mac_control = mt7531_mac_control, +}; diff --git a/drivers/net/mtk_eth/mt753x.c b/drivers/net/mtk_eth/mt753x.c new file mode 100644 index 00000000000..cdd52f3ff1b --- /dev/null +++ b/drivers/net/mtk_eth/mt753x.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + * Author: Mark Lee <mark-mc.lee@mediatek.com> + */ + +#include <errno.h> +#include <time.h> +#include "mtk_eth.h" +#include "mt753x.h" + +/* + * MT753x Internal Register Address Bits + * ------------------------------------------------------------------- + * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 | + * |----------------------------------------|---------------|--------| + * | Page Address | Reg Address | Unused | + * ------------------------------------------------------------------- + */ + +int __mt753x_mdio_reg_read(struct mtk_eth_priv *priv, u32 smi_addr, u32 reg, + u32 *data) +{ + int ret, low_word, high_word; + + /* Write page address */ + ret = mtk_mii_write(priv, smi_addr, 0x1f, reg >> 6); + if (ret) + return ret; + + /* Read low word */ + low_word = mtk_mii_read(priv, smi_addr, (reg >> 2) & 0xf); + if (low_word < 0) + return low_word; + + /* Read high word */ + high_word = mtk_mii_read(priv, smi_addr, 0x10); + if (high_word < 0) + return high_word; + + if (data) + *data = ((u32)high_word << 16) | (low_word & 0xffff); + + return 0; +} + +int mt753x_mdio_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data) +{ + return __mt753x_mdio_reg_read(priv->epriv.eth, priv->smi_addr, reg, + data); +} + +int mt753x_mdio_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data) +{ + int ret; + + /* Write page address */ + ret = mtk_mii_write(priv->epriv.eth, priv->smi_addr, 0x1f, reg >> 6); + if (ret) + return ret; + + /* Write low word */ + ret = mtk_mii_write(priv->epriv.eth, priv->smi_addr, (reg >> 2) & 0xf, + data & 0xffff); + if (ret) + return ret; + + /* Write high word */ + return mtk_mii_write(priv->epriv.eth, priv->smi_addr, 0x10, data >> 16); +} + +int mt753x_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data) +{ + return priv->reg_read(priv, reg, data); +} + +int mt753x_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data) +{ + return priv->reg_write(priv, reg, data); +} + +void mt753x_reg_rmw(struct mt753x_switch_priv *priv, u32 reg, u32 clr, u32 set) +{ + u32 val; + + priv->reg_read(priv, reg, &val); + val &= ~clr; + val |= set; + priv->reg_write(priv, reg, val); +} + +/* Indirect MDIO clause 22/45 access */ +static int mt7531_mii_rw(struct mt753x_switch_priv *priv, int phy, int reg, + u16 data, u32 cmd, u32 st) +{ + u32 val, timeout_ms; + ulong timeout; + int ret = 0; + + val = (st << MDIO_ST_S) | + ((cmd << MDIO_CMD_S) & MDIO_CMD_M) | + ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | + ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); + + if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR) + val |= data & MDIO_RW_DATA_M; + + mt753x_reg_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST); + + timeout_ms = 100; + timeout = get_timer(0); + while (1) { + mt753x_reg_read(priv, MT7531_PHY_IAC, &val); + + if ((val & PHY_ACS_ST) == 0) + break; + + if (get_timer(timeout) > timeout_ms) + return -ETIMEDOUT; + } + + if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) { + mt753x_reg_read(priv, MT7531_PHY_IAC, &val); + ret = val & MDIO_RW_DATA_M; + } + + return ret; +} + +int mt7531_mii_read(struct mt753x_switch_priv *priv, u8 phy, u8 reg) +{ + u8 phy_addr; + + if (phy >= MT753X_NUM_PHYS) + return -EINVAL; + + phy_addr = MT753X_PHY_ADDR(priv->phy_base, phy); + + return mt7531_mii_rw(priv, phy_addr, reg, 0, MDIO_CMD_READ, + MDIO_ST_C22); +} + +int mt7531_mii_write(struct mt753x_switch_priv *priv, u8 phy, u8 reg, u16 val) +{ + u8 phy_addr; + + if (phy >= MT753X_NUM_PHYS) + return -EINVAL; + + phy_addr = MT753X_PHY_ADDR(priv->phy_base, phy); + + return mt7531_mii_rw(priv, phy_addr, reg, val, MDIO_CMD_WRITE, + MDIO_ST_C22); +} + +int mt7531_mmd_read(struct mt753x_switch_priv *priv, u8 addr, u8 devad, + u16 reg) +{ + u8 phy_addr; + int ret; + + if (addr >= MT753X_NUM_PHYS) + return -EINVAL; + + phy_addr = MT753X_PHY_ADDR(priv->phy_base, addr); + + ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, + MDIO_ST_C45); + if (ret) + return ret; + + return mt7531_mii_rw(priv, phy_addr, devad, 0, MDIO_CMD_READ_C45, + MDIO_ST_C45); +} + +int mt7531_mmd_write(struct mt753x_switch_priv *priv, u8 addr, u8 devad, + u16 reg, u16 val) +{ + u8 phy_addr; + int ret; + + if (addr >= MT753X_NUM_PHYS) + return 0; + + phy_addr = MT753X_PHY_ADDR(priv->phy_base, addr); + + ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, + MDIO_ST_C45); + if (ret) + return ret; + + return mt7531_mii_rw(priv, phy_addr, devad, val, MDIO_CMD_WRITE, + MDIO_ST_C45); +} + +static int mt7531_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct mt753x_switch_priv *priv = bus->priv; + + if (devad < 0) + return mt7531_mii_read(priv, addr, reg); + + return mt7531_mmd_read(priv, addr, devad, reg); +} + +static int mt7531_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct mt753x_switch_priv *priv = bus->priv; + + if (devad < 0) + return mt7531_mii_write(priv, addr, reg, val); + + return mt7531_mmd_write(priv, addr, devad, reg, val); +} + +int mt7531_mdio_register(struct mt753x_switch_priv *priv) +{ + struct mii_dev *mdio_bus = mdio_alloc(); + int ret; + + if (!mdio_bus) + return -ENOMEM; + + mdio_bus->read = mt7531_mdio_read; + mdio_bus->write = mt7531_mdio_write; + snprintf(mdio_bus->name, sizeof(mdio_bus->name), priv->epriv.sw->name); + + mdio_bus->priv = priv; + + ret = mdio_register(mdio_bus); + if (ret) { + mdio_free(mdio_bus); + return ret; + } + + priv->mdio_bus = mdio_bus; + + return 0; +} + +void mt753x_port_isolation(struct mt753x_switch_priv *priv) +{ + u32 i; + + for (i = 0; i < MT753X_NUM_PORTS; i++) { + /* Set port matrix mode */ + if (i != 6) + mt753x_reg_write(priv, PCR_REG(i), + (0x40 << PORT_MATRIX_S)); + else + mt753x_reg_write(priv, PCR_REG(i), + (0x3f << PORT_MATRIX_S)); + + /* Set port mode to user port */ + mt753x_reg_write(priv, PVC_REG(i), + (0x8100 << STAG_VPID_S) | + (VLAN_ATTR_USER << VLAN_ATTR_S)); + } +} diff --git a/drivers/net/mtk_eth/mt753x.h b/drivers/net/mtk_eth/mt753x.h new file mode 100644 index 00000000000..65046a1421c --- /dev/null +++ b/drivers/net/mtk_eth/mt753x.h @@ -0,0 +1,286 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2025 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + * Author: Mark Lee <mark-mc.lee@mediatek.com> + */ + +#ifndef _MTK_ETH_MT753X_H_ +#define _MTK_ETH_MT753X_H_ + +#include <phy.h> +#include <miiphy.h> +#include <linux/bitops.h> +#include <linux/bitfield.h> + +struct mtk_eth_priv; + +#define MT753X_NUM_PHYS 5 +#define MT753X_NUM_PORTS 7 +#define MT753X_DFL_SMI_ADDR 31 +#define MT753X_SMI_ADDR_MASK 0x1f + +#define MT753X_PHY_ADDR(base, addr) \ + (((base) + (addr)) & 0x1f) + +/* MT7530 Registers */ +#define PCR_REG(p) (0x2004 + (p) * 0x100) +#define PORT_MATRIX_S 16 +#define PORT_MATRIX_M 0xff0000 + +#define PVC_REG(p) (0x2010 + (p) * 0x100) +#define STAG_VPID_S 16 +#define STAG_VPID_M 0xffff0000 +#define VLAN_ATTR_S 6 +#define VLAN_ATTR_M 0xc0 + +/* VLAN_ATTR: VLAN attributes */ +#define VLAN_ATTR_USER 0 +#define VLAN_ATTR_STACK 1 +#define VLAN_ATTR_TRANSLATION 2 +#define VLAN_ATTR_TRANSPARENT 3 + +#define PMCR_REG(p) (0x3000 + (p) * 0x100) +/* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR + * MT7531 specific fields are defined below + */ +#define FORCE_MODE_EEE1G BIT(25) +#define FORCE_MODE_EEE100 BIT(26) +#define FORCE_MODE_TX_FC BIT(27) +#define FORCE_MODE_RX_FC BIT(28) +#define FORCE_MODE_DPX BIT(29) +#define FORCE_MODE_SPD BIT(30) +#define FORCE_MODE_LNK BIT(31) +#define MT7531_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ + FORCE_MODE_DPX | FORCE_MODE_SPD | \ + FORCE_MODE_LNK +#define MT7988_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ + FORCE_MODE_DPX | FORCE_MODE_SPD | \ + FORCE_MODE_LNK + +/* MT7531 SGMII Registers */ +#define MT7531_SGMII_REG_BASE 0x5000 +#define MT7531_SGMII_REG_PORT_BASE 0x1000 +#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \ + (p) * MT7531_SGMII_REG_PORT_BASE + (r)) +#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(((p) - 5), 0x00) +#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(((p) - 5), 0x20) +#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(((p) - 5), 0xe8) +#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(((p) - 5), 0x128) +#define MT7531_PHYA_ANA_SYSPLL(p) MT7531_SGMII_REG(((p) - 5), 0x158) +/* XXX: all fields of MT7531 SGMII are defined under SGMSYS */ + +/* MT753x System Control Register */ +#define SYS_CTRL_REG 0x7000 +#define SW_PHY_RST BIT(2) +#define SW_SYS_RST BIT(1) +#define SW_REG_RST BIT(0) + +/* MT7531 */ +#define MT7531_PHY_IAC 0x701c +/* XXX: all fields are defined under GMAC_PIAC_REG */ + +#define MT7531_CLKGEN_CTRL 0x7500 +#define CLK_SKEW_OUT_S 8 +#define CLK_SKEW_OUT_M 0x300 +#define CLK_SKEW_IN_S 6 +#define CLK_SKEW_IN_M 0xc0 +#define RXCLK_NO_DELAY BIT(5) +#define TXCLK_NO_REVERSE BIT(4) +#define GP_MODE_S 1 +#define GP_MODE_M 0x06 +#define GP_CLK_EN BIT(0) + +/* Values of GP_MODE */ +#define GP_MODE_RGMII 0 +#define GP_MODE_MII 1 +#define GP_MODE_REV_MII 2 + +/* Values of CLK_SKEW_IN */ +#define CLK_SKEW_IN_NO_CHANGE 0 +#define CLK_SKEW_IN_DELAY_100PPS 1 +#define CLK_SKEW_IN_DELAY_200PPS 2 +#define CLK_SKEW_IN_REVERSE 3 + +/* Values of CLK_SKEW_OUT */ +#define CLK_SKEW_OUT_NO_CHANGE 0 +#define CLK_SKEW_OUT_DELAY_100PPS 1 +#define CLK_SKEW_OUT_DELAY_200PPS 2 +#define CLK_SKEW_OUT_REVERSE 3 + +#define HWTRAP_REG 0x7800 +/* MT7530 Modified Hardware Trap Status Registers */ +#define MHWTRAP_REG 0x7804 +#define CHG_TRAP BIT(16) +#define LOOPDET_DIS BIT(14) +#define P5_INTF_SEL_S 13 +#define P5_INTF_SEL_M 0x2000 +#define SMI_ADDR_S 11 +#define SMI_ADDR_M 0x1800 +#define XTAL_FSEL_S 9 +#define XTAL_FSEL_M 0x600 +#define P6_INTF_DIS BIT(8) +#define P5_INTF_MODE_S 7 +#define P5_INTF_MODE_M 0x80 +#define P5_INTF_DIS BIT(6) +#define C_MDIO_BPS BIT(5) +#define CHIP_MODE_S 0 +#define CHIP_MODE_M 0x0f + +/* P5_INTF_SEL: Interface type of Port5 */ +#define P5_INTF_SEL_GPHY 0 +#define P5_INTF_SEL_GMAC5 1 + +/* P5_INTF_MODE: Interface mode of Port5 */ +#define P5_INTF_MODE_GMII_MII 0 +#define P5_INTF_MODE_RGMII 1 + +#define MT7530_P6ECR 0x7830 +#define P6_INTF_MODE_M 0x3 +#define P6_INTF_MODE_S 0 + +/* P6_INTF_MODE: Interface mode of Port6 */ +#define P6_INTF_MODE_RGMII 0 +#define P6_INTF_MODE_TRGMII 1 + +#define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8) +#define RD_TAP_S 0 +#define RD_TAP_M 0x7f + +#define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8) +/* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */ + +/* TOP Signals Status Register */ +#define MT7531_TOP_SIG_SR 0x780c +#define PAD_MCM_SMI_EN BIT(0) +#define PAD_DUAL_SGMII_EN BIT(1) + +/* MT7531 PLLGP Registers */ +#define MT7531_PLLGP_EN 0x7820 +#define EN_COREPLL BIT(2) +#define SW_CLKSW BIT(1) +#define SW_PLLGP BIT(0) + +#define MT7531_PLLGP_CR0 0x78a8 +#define RG_COREPLL_EN BIT(22) +#define RG_COREPLL_POSDIV_S 23 +#define RG_COREPLL_POSDIV_M 0x3800000 +#define RG_COREPLL_SDM_PCW_S 1 +#define RG_COREPLL_SDM_PCW_M 0x3ffffe +#define RG_COREPLL_SDM_PCW_CHG BIT(0) + +/* MT7531 RGMII and SGMII PLL clock */ +#define MT7531_ANA_PLLGP_CR2 0x78b0 +#define MT7531_ANA_PLLGP_CR5 0x78bc + +/* MT7531 GPIO GROUP IOLB SMT0 Control */ +#define MT7531_SMT0_IOLB 0x7f04 +#define SMT_IOLB_5_SMI_MDC_EN BIT(5) + +/* MT7530 GPHY MDIO MMD Registers */ +#define CORE_PLL_GROUP2 0x401 +#define RG_SYSPLL_EN_NORMAL BIT(15) +#define RG_SYSPLL_VODEN BIT(14) +#define RG_SYSPLL_POSDIV_S 5 +#define RG_SYSPLL_POSDIV_M 0x60 + +#define CORE_PLL_GROUP4 0x403 +#define MT7531_BYPASS_MODE BIT(4) +#define MT7531_POWER_ON_OFF BIT(5) +#define RG_SYSPLL_DDSFBK_EN BIT(12) +#define RG_SYSPLL_BIAS_EN BIT(11) +#define RG_SYSPLL_BIAS_LPF_EN BIT(10) + +#define CORE_PLL_GROUP5 0x404 +#define RG_LCDDS_PCW_NCPO1_S 0 +#define RG_LCDDS_PCW_NCPO1_M 0xffff + +#define CORE_PLL_GROUP6 0x405 +#define RG_LCDDS_PCW_NCPO0_S 0 +#define RG_LCDDS_PCW_NCPO0_M 0xffff + +#define CORE_PLL_GROUP7 0x406 +#define RG_LCDDS_PWDB BIT(15) +#define RG_LCDDS_ISO_EN BIT(13) +#define RG_LCCDS_C_S 4 +#define RG_LCCDS_C_M 0x70 +#define RG_LCDDS_PCW_NCPO_CHG BIT(3) + +#define CORE_PLL_GROUP10 0x409 +#define RG_LCDDS_SSC_DELTA_S 0 +#define RG_LCDDS_SSC_DELTA_M 0xfff + +#define CORE_PLL_GROUP11 0x40a +#define RG_LCDDS_SSC_DELTA1_S 0 +#define RG_LCDDS_SSC_DELTA1_M 0xfff + +#define CORE_GSWPLL_GRP1 0x40d +#define RG_GSWPLL_POSDIV_200M_S 12 +#define RG_GSWPLL_POSDIV_200M_M 0x3000 +#define RG_GSWPLL_EN_PRE BIT(11) +#define RG_GSWPLL_FBKDIV_200M_S 0 +#define RG_GSWPLL_FBKDIV_200M_M 0xff + +#define CORE_GSWPLL_GRP2 0x40e +#define RG_GSWPLL_POSDIV_500M_S 8 +#define RG_GSWPLL_POSDIV_500M_M 0x300 +#define RG_GSWPLL_FBKDIV_500M_S 0 +#define RG_GSWPLL_FBKDIV_500M_M 0xff + +#define CORE_TRGMII_GSW_CLK_CG 0x410 +#define REG_GSWCK_EN BIT(0) +#define REG_TRGMIICK_EN BIT(1) + +/* Extend PHY Control Register 3 */ +#define PHY_EXT_REG_14 0x14 + +/* Fields of PHY_EXT_REG_14 */ +#define PHY_EN_DOWN_SHFIT BIT(4) + +/* Extend PHY Control Register 4 */ +#define PHY_EXT_REG_17 0x17 + +/* Fields of PHY_EXT_REG_17 */ +#define PHY_LINKDOWN_POWER_SAVING_EN BIT(4) + +/* PHY RXADC Control Register 7 */ +#define PHY_DEV1E_REG_0C6 0x0c6 + +/* Fields of PHY_DEV1E_REG_0C6 */ +#define PHY_POWER_SAVING_S 8 +#define PHY_POWER_SAVING_M 0x300 +#define PHY_POWER_SAVING_TX 0x0 + +struct mt753x_switch_priv { + struct mtk_eth_switch_priv epriv; + struct mii_dev *mdio_bus; + u32 smi_addr; + u32 phy_base; + u32 pmcr; + + int (*reg_read)(struct mt753x_switch_priv *priv, u32 reg, u32 *data); + int (*reg_write)(struct mt753x_switch_priv *priv, u32 reg, u32 data); +}; + +int __mt753x_mdio_reg_read(struct mtk_eth_priv *priv, u32 smi_addr, u32 reg, + u32 *data); +int mt753x_mdio_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data); +int mt753x_mdio_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data); + +int mt753x_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data); +int mt753x_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data); +void mt753x_reg_rmw(struct mt753x_switch_priv *priv, u32 reg, u32 clr, u32 set); + +int mt7531_mii_read(struct mt753x_switch_priv *priv, u8 phy, u8 reg); +int mt7531_mii_write(struct mt753x_switch_priv *priv, u8 phy, u8 reg, u16 val); +int mt7531_mmd_read(struct mt753x_switch_priv *priv, u8 addr, u8 devad, + u16 reg); +int mt7531_mmd_write(struct mt753x_switch_priv *priv, u8 addr, u8 devad, + u16 reg, u16 val); + +int mt7531_mdio_register(struct mt753x_switch_priv *priv); + +void mt753x_port_isolation(struct mt753x_switch_priv *priv); + +#endif /* _MTK_ETH_MT753X_H_ */ diff --git a/drivers/net/mtk_eth/mt7988.c b/drivers/net/mtk_eth/mt7988.c new file mode 100644 index 00000000000..a416d87840c --- /dev/null +++ b/drivers/net/mtk_eth/mt7988.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + * Author: Mark Lee <mark-mc.lee@mediatek.com> + */ + +#include <miiphy.h> +#include <linux/delay.h> +#include <linux/mdio.h> +#include <linux/mii.h> +#include <linux/io.h> +#include "mtk_eth.h" +#include "mt753x.h" + +static int mt7988_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data) +{ + *data = readl(priv->epriv.ethsys_base + GSW_BASE + reg); + + return 0; +} + +static int mt7988_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data) +{ + writel(data, priv->epriv.ethsys_base + GSW_BASE + reg); + + return 0; +} + +static void mt7988_phy_setting(struct mt753x_switch_priv *priv) +{ + u16 val; + u32 i; + + for (i = 0; i < MT753X_NUM_PHYS; i++) { + /* Enable HW auto downshift */ + mt7531_mii_write(priv, i, 0x1f, 0x1); + val = mt7531_mii_read(priv, i, PHY_EXT_REG_14); + val |= PHY_EN_DOWN_SHFIT; + mt7531_mii_write(priv, i, PHY_EXT_REG_14, val); + + /* PHY link down power saving enable */ + val = mt7531_mii_read(priv, i, PHY_EXT_REG_17); + val |= PHY_LINKDOWN_POWER_SAVING_EN; + mt7531_mii_write(priv, i, PHY_EXT_REG_17, val); + } +} + +static void mt7988_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + u32 pmcr = FORCE_MODE_LNK; + + if (enable) + pmcr = priv->pmcr; + + mt7988_reg_write(priv, PMCR_REG(6), pmcr); +} + +static int mt7988_setup(struct mtk_eth_switch_priv *swpriv) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + u16 phy_addr, phy_val; + u32 pmcr; + int i; + + priv->smi_addr = MT753X_DFL_SMI_ADDR; + priv->phy_base = (priv->smi_addr + 1) & MT753X_SMI_ADDR_MASK; + priv->reg_read = mt7988_reg_read; + priv->reg_write = mt7988_reg_write; + + /* Turn off PHYs */ + for (i = 0; i < MT753X_NUM_PHYS; i++) { + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); + phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR); + phy_val |= BMCR_PDOWN; + mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val); + } + + switch (priv->epriv.phy_interface) { + case PHY_INTERFACE_MODE_USXGMII: + /* Use CPU bridge instead of actual USXGMII path */ + + /* Disable GDM1 RX CRC stripping */ + /* mtk_fe_rmw(priv, 0x500, BIT(16), 0); */ + + /* Set GDM1 no drop */ + mtk_fe_rmw(priv->epriv.eth, PSE_NO_DROP_CFG_REG, 0, + PSE_NO_DROP_GDM1); + + /* Enable GSW CPU bridge as USXGMII */ + /* mtk_fe_rmw(priv, 0x504, BIT(31), BIT(31)); */ + + /* Enable GDM1 to GSW CPU bridge */ + mtk_gmac_rmw(priv->epriv.eth, GMAC_MAC_MISC_REG, 0, BIT(0)); + + /* XGMAC force link up */ + mtk_gmac_rmw(priv->epriv.eth, GMAC_XGMAC_STS_REG, 0, + P1_XGMAC_FORCE_LINK); + + /* Setup GSW CPU bridge IPG */ + mtk_gmac_rmw(priv->epriv.eth, GMAC_GSW_CFG_REG, + GSWTX_IPG_M | GSWRX_IPG_M, + (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S)); + break; + default: + printf("Error: MT7988 GSW does not support %s interface\n", + phy_string_for_interface(priv->epriv.phy_interface)); + break; + } + + pmcr = MT7988_FORCE_MODE | + (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | + MAC_MODE | MAC_TX_EN | MAC_RX_EN | + BKOFF_EN | BACKPR_EN | + FORCE_RX_FC | FORCE_TX_FC | + (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | + FORCE_LINK; + + priv->pmcr = pmcr; + + /* Keep MAC link down before starting eth */ + mt7988_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); + + /* Enable port isolation to block inter-port communication */ + mt753x_port_isolation(priv); + + /* Turn on PHYs */ + for (i = 0; i < MT753X_NUM_PHYS; i++) { + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); + phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR); + phy_val &= ~BMCR_PDOWN; + mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val); + } + + mt7988_phy_setting(priv); + + return mt7531_mdio_register(priv); +} + +static int mt7531_cleanup(struct mtk_eth_switch_priv *swpriv) +{ + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; + + mdio_unregister(priv->mdio_bus); + + return 0; +} + +MTK_ETH_SWITCH(mt7988) = { + .name = "mt7988", + .desc = "MediaTek MT7988 built-in switch", + .priv_size = sizeof(struct mt753x_switch_priv), + .reset_wait_time = 50, + + .setup = mt7988_setup, + .cleanup = mt7531_cleanup, + .mac_control = mt7988_mac_control, +}; diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth/mtk_eth.c index 454caa3cd3a..5d6a42bceb4 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth/mtk_eth.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2018 MediaTek Inc. + * Copyright (C) 2025 MediaTek Inc. * * Author: Weijie Gao <weijie.gao@mediatek.com> * Author: Mark Lee <mark-mc.lee@mediatek.com> @@ -35,14 +35,6 @@ #define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN) #define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE) -#define MT753X_NUM_PHYS 5 -#define MT753X_NUM_PORTS 7 -#define MT753X_DFL_SMI_ADDR 31 -#define MT753X_SMI_ADDR_MASK 0x1f - -#define MT753X_PHY_ADDR(base, addr) \ - (((base) + (addr)) & 0x1f) - #define GDMA_FWD_TO_CPU \ (0x20000000 | \ GDM_ICS_EN | \ @@ -75,32 +67,6 @@ (DP_DISCARD << MC_DP_S) | \ (DP_DISCARD << UN_DP_S)) -enum mtk_switch { - SW_NONE, - SW_MT7530, - SW_MT7531, - SW_MT7988, -}; - -/* struct mtk_soc_data - This is the structure holding all differences - * among various plaforms - * @caps Flags shown the extra capability for the SoC - * @ana_rgc3: The offset for register ANA_RGC3 related to - * sgmiisys syscon - * @gdma_count: Number of GDMAs - * @pdma_base: Register base of PDMA block - * @txd_size: Tx DMA descriptor size. - * @rxd_size: Rx DMA descriptor size. - */ -struct mtk_soc_data { - u32 caps; - u32 ana_rgc3; - u32 gdma_count; - u32 pdma_base; - u32 txd_size; - u32 rxd_size; -}; - struct mtk_eth_priv { char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); @@ -113,7 +79,6 @@ struct mtk_eth_priv { void __iomem *fe_base; void __iomem *gmac_base; void __iomem *sgmii_base; - void __iomem *gsw_base; struct regmap *ethsys_regmap; @@ -125,11 +90,6 @@ struct mtk_eth_priv { struct regmap *toprgu_regmap; struct mii_dev *mdio_bus; - int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg); - int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val); - int (*mmd_read)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg); - int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, - u16 val); const struct mtk_soc_data *soc; int gmac_id; @@ -143,13 +103,8 @@ struct mtk_eth_priv { int phy_interface; int phy_addr; - enum mtk_switch sw; - int (*switch_init)(struct mtk_eth_priv *priv); - void (*switch_mac_control)(struct mtk_eth_priv *priv, bool enable); - u32 mt753x_smi_addr; - u32 mt753x_phy_base; - u32 mt753x_pmcr; - u32 mt753x_reset_wait_time; + struct mtk_eth_switch_priv *swpriv; + const char *swname; struct gpio_desc rst_gpio; int mcm; @@ -184,7 +139,7 @@ static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg, writel(val, priv->fe_base + gdma_base + reg); } -static void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) +void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) { clrsetbits_le32(priv->fe_base + reg, clr, set); } @@ -199,13 +154,12 @@ static void mtk_gmac_write(struct mtk_eth_priv *priv, u32 reg, u32 val) writel(val, priv->gmac_base + reg); } -static void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) +void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) { clrsetbits_le32(priv->gmac_base + reg, clr, set); } -static void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, - u32 set) +void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) { uint val; @@ -226,16 +180,6 @@ static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, regmap_write(priv->infra_regmap, reg, val); } -static u32 mtk_gsw_read(struct mtk_eth_priv *priv, u32 reg) -{ - return readl(priv->gsw_base + reg); -} - -static void mtk_gsw_write(struct mtk_eth_priv *priv, u32 reg, u32 val) -{ - writel(val, priv->gsw_base + reg); -} - /* Direct MDIO clause 22/45 access via SoC */ static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data, u32 cmd, u32 st) @@ -269,19 +213,19 @@ static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data, } /* Direct MDIO clause 22 read via SoC */ -static int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg) +int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg) { return mtk_mii_rw(priv, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22); } /* Direct MDIO clause 22 write via SoC */ -static int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data) +int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data) { return mtk_mii_rw(priv, phy, reg, data, MDIO_CMD_WRITE, MDIO_ST_C22); } /* Direct MDIO clause 45 read via SoC */ -static int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) +int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) { int ret; @@ -294,8 +238,8 @@ static int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) } /* Direct MDIO clause 45 write via SoC */ -static int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, - u16 reg, u16 val) +int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, + u16 val) { int ret; @@ -308,232 +252,52 @@ static int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, } /* Indirect MDIO clause 45 read via MII registers */ -static int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, - u16 reg) +int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) { int ret; - ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, - (MMD_ADDR << MMD_CMD_S) | - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); + ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG, + (MMD_ADDR << MMD_CMD_S) | + ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); if (ret) return ret; - ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); + ret = mtk_mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); if (ret) return ret; - ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, - (MMD_DATA << MMD_CMD_S) | - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); + ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG, + (MMD_DATA << MMD_CMD_S) | + ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); if (ret) return ret; - return priv->mii_read(priv, addr, MII_MMD_ADDR_DATA_REG); + return mtk_mii_read(priv, addr, MII_MMD_ADDR_DATA_REG); } /* Indirect MDIO clause 45 write via MII registers */ -static int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, - u16 reg, u16 val) +int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, + u16 val) { int ret; - ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, - (MMD_ADDR << MMD_CMD_S) | - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); + ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG, + (MMD_ADDR << MMD_CMD_S) | + ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); if (ret) return ret; - ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); + ret = mtk_mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); if (ret) return ret; - ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, - (MMD_DATA << MMD_CMD_S) | - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); + ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG, + (MMD_DATA << MMD_CMD_S) | + ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); if (ret) return ret; - return priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val); -} - -/* - * MT7530 Internal Register Address Bits - * ------------------------------------------------------------------- - * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 | - * |----------------------------------------|---------------|--------| - * | Page Address | Reg Address | Unused | - * ------------------------------------------------------------------- - */ - -static int mt753x_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data) -{ - int ret, low_word, high_word; - - if (priv->sw == SW_MT7988) { - *data = mtk_gsw_read(priv, reg); - return 0; - } - - /* Write page address */ - ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6); - if (ret) - return ret; - - /* Read low word */ - low_word = mtk_mii_read(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf); - if (low_word < 0) - return low_word; - - /* Read high word */ - high_word = mtk_mii_read(priv, priv->mt753x_smi_addr, 0x10); - if (high_word < 0) - return high_word; - - if (data) - *data = ((u32)high_word << 16) | (low_word & 0xffff); - - return 0; -} - -static int mt753x_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data) -{ - int ret; - - if (priv->sw == SW_MT7988) { - mtk_gsw_write(priv, reg, data); - return 0; - } - - /* Write page address */ - ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6); - if (ret) - return ret; - - /* Write low word */ - ret = mtk_mii_write(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf, - data & 0xffff); - if (ret) - return ret; - - /* Write high word */ - return mtk_mii_write(priv, priv->mt753x_smi_addr, 0x10, data >> 16); -} - -static void mt753x_reg_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, - u32 set) -{ - u32 val; - - mt753x_reg_read(priv, reg, &val); - val &= ~clr; - val |= set; - mt753x_reg_write(priv, reg, val); -} - -/* Indirect MDIO clause 22/45 access */ -static int mt7531_mii_rw(struct mtk_eth_priv *priv, int phy, int reg, u16 data, - u32 cmd, u32 st) -{ - ulong timeout; - u32 val, timeout_ms; - int ret = 0; - - val = (st << MDIO_ST_S) | - ((cmd << MDIO_CMD_S) & MDIO_CMD_M) | - ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | - ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); - - if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR) - val |= data & MDIO_RW_DATA_M; - - mt753x_reg_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST); - - timeout_ms = 100; - timeout = get_timer(0); - while (1) { - mt753x_reg_read(priv, MT7531_PHY_IAC, &val); - - if ((val & PHY_ACS_ST) == 0) - break; - - if (get_timer(timeout) > timeout_ms) - return -ETIMEDOUT; - } - - if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) { - mt753x_reg_read(priv, MT7531_PHY_IAC, &val); - ret = val & MDIO_RW_DATA_M; - } - - return ret; -} - -static int mt7531_mii_ind_read(struct mtk_eth_priv *priv, u8 phy, u8 reg) -{ - u8 phy_addr; - - if (phy >= MT753X_NUM_PHYS) - return -EINVAL; - - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy); - - return mt7531_mii_rw(priv, phy_addr, reg, 0, MDIO_CMD_READ, - MDIO_ST_C22); -} - -static int mt7531_mii_ind_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, - u16 val) -{ - u8 phy_addr; - - if (phy >= MT753X_NUM_PHYS) - return -EINVAL; - - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy); - - return mt7531_mii_rw(priv, phy_addr, reg, val, MDIO_CMD_WRITE, - MDIO_ST_C22); -} - -static int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, - u16 reg) -{ - u8 phy_addr; - int ret; - - if (addr >= MT753X_NUM_PHYS) - return -EINVAL; - - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr); - - ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, - MDIO_ST_C45); - if (ret) - return ret; - - return mt7531_mii_rw(priv, phy_addr, devad, 0, MDIO_CMD_READ_C45, - MDIO_ST_C45); -} - -static int mt7531_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, - u16 reg, u16 val) -{ - u8 phy_addr; - int ret; - - if (addr >= MT753X_NUM_PHYS) - return 0; - - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr); - - ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, - MDIO_ST_C45); - if (ret) - return ret; - - return mt7531_mii_rw(priv, phy_addr, devad, val, MDIO_CMD_WRITE, - MDIO_ST_C45); + return mtk_mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val); } static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) @@ -541,9 +305,9 @@ static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) struct mtk_eth_priv *priv = bus->priv; if (devad < 0) - return priv->mii_read(priv, addr, reg); - else - return priv->mmd_read(priv, addr, devad, reg); + return mtk_mii_read(priv, addr, reg); + + return mtk_mmd_read(priv, addr, devad, reg); } static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, @@ -552,9 +316,9 @@ static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, struct mtk_eth_priv *priv = bus->priv; if (devad < 0) - return priv->mii_write(priv, addr, reg, val); - else - return priv->mmd_write(priv, addr, devad, reg, val); + return mtk_mii_write(priv, addr, reg, val); + + return mtk_mmd_write(priv, addr, devad, reg, val); } static int mtk_mdio_register(struct udevice *dev) @@ -566,28 +330,6 @@ static int mtk_mdio_register(struct udevice *dev) if (!mdio_bus) return -ENOMEM; - /* Assign MDIO access APIs according to the switch/phy */ - switch (priv->sw) { - case SW_MT7530: - priv->mii_read = mtk_mii_read; - priv->mii_write = mtk_mii_write; - priv->mmd_read = mtk_mmd_ind_read; - priv->mmd_write = mtk_mmd_ind_write; - break; - case SW_MT7531: - case SW_MT7988: - priv->mii_read = mt7531_mii_ind_read; - priv->mii_write = mt7531_mii_ind_write; - priv->mmd_read = mt7531_mmd_ind_read; - priv->mmd_write = mt7531_mmd_ind_write; - break; - default: - priv->mii_read = mtk_mii_read; - priv->mii_write = mtk_mii_write; - priv->mmd_read = mtk_mmd_read; - priv->mmd_write = mtk_mmd_write; - } - mdio_bus->read = mtk_mdio_read; mdio_bus->write = mtk_mdio_write; snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name); @@ -604,531 +346,91 @@ static int mtk_mdio_register(struct udevice *dev) return 0; } -static int mt753x_core_reg_read(struct mtk_eth_priv *priv, u32 reg) -{ - u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0); - - return priv->mmd_read(priv, phy_addr, 0x1f, reg); -} - -static void mt753x_core_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 val) -{ - u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0); - - priv->mmd_write(priv, phy_addr, 0x1f, reg, val); -} - -static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode) -{ - u32 ncpo1, ssc_delta; - - switch (mode) { - case PHY_INTERFACE_MODE_RGMII: - ncpo1 = 0x0c80; - ssc_delta = 0x87; - break; - default: - printf("error: xMII mode %d not supported\n", mode); - return -EINVAL; - } - - /* Disable MT7530 core clock */ - mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0); - - /* Disable MT7530 PLL */ - mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1, - (2 << RG_GSWPLL_POSDIV_200M_S) | - (32 << RG_GSWPLL_FBKDIV_200M_S)); - - /* For MT7530 core clock = 500Mhz */ - mt753x_core_reg_write(priv, CORE_GSWPLL_GRP2, - (1 << RG_GSWPLL_POSDIV_500M_S) | - (25 << RG_GSWPLL_FBKDIV_500M_S)); - - /* Enable MT7530 PLL */ - mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1, - (2 << RG_GSWPLL_POSDIV_200M_S) | - (32 << RG_GSWPLL_FBKDIV_200M_S) | - RG_GSWPLL_EN_PRE); - - udelay(20); - - mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); - - /* Setup the MT7530 TRGMII Tx Clock */ - mt753x_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1); - mt753x_core_reg_write(priv, CORE_PLL_GROUP6, 0); - mt753x_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta); - mt753x_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta); - mt753x_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | - RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); - - mt753x_core_reg_write(priv, CORE_PLL_GROUP2, - RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | - (1 << RG_SYSPLL_POSDIV_S)); - - mt753x_core_reg_write(priv, CORE_PLL_GROUP7, - RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) | - RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); - - /* Enable MT7530 core clock */ - mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, - REG_GSWCK_EN | REG_TRGMIICK_EN); - - return 0; -} - -static void mt7530_mac_control(struct mtk_eth_priv *priv, bool enable) -{ - u32 pmcr = FORCE_MODE; - - if (enable) - pmcr = priv->mt753x_pmcr; - - mt753x_reg_write(priv, PMCR_REG(6), pmcr); -} - -static int mt7530_setup(struct mtk_eth_priv *priv) -{ - u16 phy_addr, phy_val; - u32 val, txdrv; - int i; - - if (!MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) { - /* Select 250MHz clk for RGMII mode */ - mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG, - ETHSYS_TRGMII_CLK_SEL362_5, 0); - - txdrv = 8; - } else { - txdrv = 4; - } - - /* Modify HWTRAP first to allow direct access to internal PHYs */ - mt753x_reg_read(priv, HWTRAP_REG, &val); - val |= CHG_TRAP; - val &= ~C_MDIO_BPS; - mt753x_reg_write(priv, MHWTRAP_REG, val); - - /* Calculate the phy base address */ - val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3; - priv->mt753x_phy_base = (val | 0x7) + 1; - - /* Turn off PHYs */ - for (i = 0; i < MT753X_NUM_PHYS; i++) { - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); - phy_val |= BMCR_PDOWN; - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); - } - - /* Force MAC link down before reset */ - mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); - mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); - - /* MT7530 reset */ - mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); - udelay(100); - - val = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | - MAC_MODE | FORCE_MODE | - MAC_TX_EN | MAC_RX_EN | - BKOFF_EN | BACKPR_EN | - (SPEED_1000M << FORCE_SPD_S) | - FORCE_DPX | FORCE_LINK; - - /* MT7530 Port6: Forced 1000M/FD, FC disabled */ - priv->mt753x_pmcr = val; - - /* MT7530 Port5: Forced link down */ - mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); - - /* Keep MAC link down before starting eth */ - mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); - - /* MT7530 Port6: Set to RGMII */ - mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII); - - /* Hardware Trap: Enable Port6, Disable Port5 */ - mt753x_reg_read(priv, HWTRAP_REG, &val); - val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS | - (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) | - (P5_INTF_MODE_RGMII << P5_INTF_MODE_S); - val &= ~(C_MDIO_BPS | P6_INTF_DIS); - mt753x_reg_write(priv, MHWTRAP_REG, val); - - /* Setup switch core pll */ - mt7530_pad_clk_setup(priv, priv->phy_interface); - - /* Lower Tx Driving for TRGMII path */ - for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) - mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i), - (txdrv << TD_DM_DRVP_S) | - (txdrv << TD_DM_DRVN_S)); - - for (i = 0 ; i < NUM_TRGMII_CTRL; i++) - mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16); - - /* Turn on PHYs */ - for (i = 0; i < MT753X_NUM_PHYS; i++) { - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); - phy_val &= ~BMCR_PDOWN; - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); - } - - return 0; -} - -static void mt7531_core_pll_setup(struct mtk_eth_priv *priv, int mcm) +static int mtk_switch_init(struct mtk_eth_priv *priv) { - /* Step 1 : Disable MT7531 COREPLL */ - mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, 0); - - /* Step 2: switch to XTAL output */ - mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_CLKSW, SW_CLKSW); - - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, 0); - - /* Step 3: disable PLLGP and enable program PLLGP */ - mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_PLLGP, SW_PLLGP); - - /* Step 4: program COREPLL output frequency to 500MHz */ - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_POSDIV_M, - 2 << RG_COREPLL_POSDIV_S); - udelay(25); - - /* Currently, support XTAL 25Mhz only */ - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_M, - 0x140000 << RG_COREPLL_SDM_PCW_S); - - /* Set feedback divide ratio update signal to high */ - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, - RG_COREPLL_SDM_PCW_CHG); - - /* Wait for at least 16 XTAL clocks */ - udelay(10); - - /* Step 5: set feedback divide ratio update signal to low */ - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, 0); - - /* add enable 325M clock for SGMII */ - mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); - - /* add enable 250SSC clock for RGMII */ - mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); - - /*Step 6: Enable MT7531 PLL */ - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, RG_COREPLL_EN); - - mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, EN_COREPLL); - - udelay(25); -} - -static int mt7531_port_sgmii_init(struct mtk_eth_priv *priv, - u32 port) -{ - if (port != 5 && port != 6) { - printf("mt7531: port %d is not a SGMII port\n", port); - return -EINVAL; - } - - /* Set SGMII GEN2 speed(2.5G) */ - mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK, - FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); - - /* Disable SGMII AN */ - mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port), - SGMII_AN_ENABLE, 0); - - /* SGMII force mode setting */ - mt753x_reg_write(priv, MT7531_SGMII_MODE(port), SGMII_FORCE_MODE); - - /* Release PHYA power down state */ - mt753x_reg_rmw(priv, MT7531_QPHY_PWR_STATE_CTRL(port), - SGMII_PHYA_PWD, 0); - - return 0; -} - -static int mt7531_port_rgmii_init(struct mtk_eth_priv *priv, u32 port) -{ - u32 val; - - if (port != 5) { - printf("error: RGMII mode is not available for port %d\n", - port); - return -EINVAL; - } - - mt753x_reg_read(priv, MT7531_CLKGEN_CTRL, &val); - val |= GP_CLK_EN; - val &= ~GP_MODE_M; - val |= GP_MODE_RGMII << GP_MODE_S; - val |= TXCLK_NO_REVERSE; - val |= RXCLK_NO_DELAY; - val &= ~CLK_SKEW_IN_M; - val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S; - val &= ~CLK_SKEW_OUT_M; - val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S; - mt753x_reg_write(priv, MT7531_CLKGEN_CTRL, val); - - return 0; -} - -static void mt7531_phy_setting(struct mtk_eth_priv *priv) -{ - int i; - u32 val; - - for (i = 0; i < MT753X_NUM_PHYS; i++) { - /* Enable HW auto downshift */ - priv->mii_write(priv, i, 0x1f, 0x1); - val = priv->mii_read(priv, i, PHY_EXT_REG_14); - val |= PHY_EN_DOWN_SHFIT; - priv->mii_write(priv, i, PHY_EXT_REG_14, val); - - /* PHY link down power saving enable */ - val = priv->mii_read(priv, i, PHY_EXT_REG_17); - val |= PHY_LINKDOWN_POWER_SAVING_EN; - priv->mii_write(priv, i, PHY_EXT_REG_17, val); - - val = priv->mmd_read(priv, i, 0x1e, PHY_DEV1E_REG_0C6); - val &= ~PHY_POWER_SAVING_M; - val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S; - priv->mmd_write(priv, i, 0x1e, PHY_DEV1E_REG_0C6, val); - } -} - -static void mt7531_mac_control(struct mtk_eth_priv *priv, bool enable) -{ - u32 pmcr = FORCE_MODE_LNK; - - if (enable) - pmcr = priv->mt753x_pmcr; - - mt753x_reg_write(priv, PMCR_REG(5), pmcr); - mt753x_reg_write(priv, PMCR_REG(6), pmcr); -} - -static int mt7531_setup(struct mtk_eth_priv *priv) -{ - u16 phy_addr, phy_val; - u32 val; - u32 pmcr; - u32 port5_sgmii; - int i; - - priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) & - MT753X_SMI_ADDR_MASK; - - /* Turn off PHYs */ - for (i = 0; i < MT753X_NUM_PHYS; i++) { - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); - phy_val |= BMCR_PDOWN; - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); - } - - /* Force MAC link down before reset */ - mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); - mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); - - /* Switch soft reset */ - mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); - udelay(100); - - /* Enable MDC input Schmitt Trigger */ - mt753x_reg_rmw(priv, MT7531_SMT0_IOLB, SMT_IOLB_5_SMI_MDC_EN, - SMT_IOLB_5_SMI_MDC_EN); - - mt7531_core_pll_setup(priv, priv->mcm); - - mt753x_reg_read(priv, MT7531_TOP_SIG_SR, &val); - port5_sgmii = !!(val & PAD_DUAL_SGMII_EN); - - /* port5 support either RGMII or SGMII, port6 only support SGMII. */ - switch (priv->phy_interface) { - case PHY_INTERFACE_MODE_RGMII: - if (!port5_sgmii) - mt7531_port_rgmii_init(priv, 5); - break; - case PHY_INTERFACE_MODE_2500BASEX: - mt7531_port_sgmii_init(priv, 6); - if (port5_sgmii) - mt7531_port_sgmii_init(priv, 5); - break; - default: - break; - } - - pmcr = MT7531_FORCE_MODE | - (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | - MAC_MODE | MAC_TX_EN | MAC_RX_EN | - BKOFF_EN | BACKPR_EN | - FORCE_RX_FC | FORCE_TX_FC | - (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | - FORCE_LINK; - - priv->mt753x_pmcr = pmcr; - - /* Keep MAC link down before starting eth */ - mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); - mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); - - /* Turn on PHYs */ - for (i = 0; i < MT753X_NUM_PHYS; i++) { - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); - phy_val &= ~BMCR_PDOWN; - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); - } - - mt7531_phy_setting(priv); - - /* Enable Internal PHYs */ - val = mt753x_core_reg_read(priv, CORE_PLL_GROUP4); - val |= MT7531_BYPASS_MODE; - val &= ~MT7531_POWER_ON_OFF; - mt753x_core_reg_write(priv, CORE_PLL_GROUP4, val); - - return 0; -} - -static void mt7988_phy_setting(struct mtk_eth_priv *priv) -{ - u16 val; - u32 i; - - for (i = 0; i < MT753X_NUM_PHYS; i++) { - /* Enable HW auto downshift */ - priv->mii_write(priv, i, 0x1f, 0x1); - val = priv->mii_read(priv, i, PHY_EXT_REG_14); - val |= PHY_EN_DOWN_SHFIT; - priv->mii_write(priv, i, PHY_EXT_REG_14, val); - - /* PHY link down power saving enable */ - val = priv->mii_read(priv, i, PHY_EXT_REG_17); - val |= PHY_LINKDOWN_POWER_SAVING_EN; - priv->mii_write(priv, i, PHY_EXT_REG_17, val); - } -} - -static void mt7988_mac_control(struct mtk_eth_priv *priv, bool enable) -{ - u32 pmcr = FORCE_MODE_LNK; - - if (enable) - pmcr = priv->mt753x_pmcr; - - mt753x_reg_write(priv, PMCR_REG(6), pmcr); -} - -static int mt7988_setup(struct mtk_eth_priv *priv) -{ - u16 phy_addr, phy_val; - u32 pmcr; - int i; - - priv->gsw_base = regmap_get_range(priv->ethsys_regmap, 0) + GSW_BASE; - - priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) & - MT753X_SMI_ADDR_MASK; - - /* Turn off PHYs */ - for (i = 0; i < MT753X_NUM_PHYS; i++) { - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); - phy_val |= BMCR_PDOWN; - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); - } - - switch (priv->phy_interface) { - case PHY_INTERFACE_MODE_USXGMII: - /* Use CPU bridge instead of actual USXGMII path */ - - /* Set GDM1 no drop */ - mtk_fe_rmw(priv, PSE_NO_DROP_CFG_REG, 0, PSE_NO_DROP_GDM1); - - /* Enable GDM1 to GSW CPU bridge */ - mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, BIT(0)); - - /* XGMAC force link up */ - mtk_gmac_rmw(priv, GMAC_XGMAC_STS_REG, 0, P1_XGMAC_FORCE_LINK); - - /* Setup GSW CPU bridge IPG */ - mtk_gmac_rmw(priv, GMAC_GSW_CFG_REG, GSWTX_IPG_M | GSWRX_IPG_M, - (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S)); - break; - default: - printf("Error: MT7988 GSW does not support %s interface\n", - phy_string_for_interface(priv->phy_interface)); - break; - } + struct mtk_eth_switch *swdrvs = ll_entry_start(struct mtk_eth_switch, + mtk_eth_switch); + const u32 n_swdrvs = ll_entry_count(struct mtk_eth_switch, + mtk_eth_switch); + struct mtk_eth_switch *tmp, *swdrv = NULL; + u32 reset_wait_time = 500; + size_t priv_size; + int ret; - pmcr = MT7988_FORCE_MODE | - (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | - MAC_MODE | MAC_TX_EN | MAC_RX_EN | - BKOFF_EN | BACKPR_EN | - FORCE_RX_FC | FORCE_TX_FC | - (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | - FORCE_LINK; - - priv->mt753x_pmcr = pmcr; - - /* Keep MAC link down before starting eth */ - mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); - - /* Turn on PHYs */ - for (i = 0; i < MT753X_NUM_PHYS; i++) { - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); - phy_val &= ~BMCR_PDOWN; - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); + if (strcmp(priv->swname, "auto")) { + for (tmp = swdrvs; tmp < swdrvs + n_swdrvs; tmp++) { + if (!strcmp(tmp->name, priv->swname)) { + swdrv = tmp; + break; + } + } } - mt7988_phy_setting(priv); - - return 0; -} - -static int mt753x_switch_init(struct mtk_eth_priv *priv) -{ - int ret; - int i; + if (swdrv) + reset_wait_time = swdrv->reset_wait_time; /* Global reset switch */ if (priv->mcm) { reset_assert(&priv->rst_mcm); udelay(1000); reset_deassert(&priv->rst_mcm); - mdelay(priv->mt753x_reset_wait_time); + mdelay(reset_wait_time); } else if (dm_gpio_is_valid(&priv->rst_gpio)) { dm_gpio_set_value(&priv->rst_gpio, 0); udelay(1000); dm_gpio_set_value(&priv->rst_gpio, 1); - mdelay(priv->mt753x_reset_wait_time); + mdelay(reset_wait_time); } - ret = priv->switch_init(priv); - if (ret) - return ret; + if (!swdrv) { + for (tmp = swdrvs; tmp < swdrvs + n_swdrvs; tmp++) { + if (!tmp->detect) + continue; - /* Set port isolation */ - for (i = 0; i < MT753X_NUM_PORTS; i++) { - /* Set port matrix mode */ - if (i != 6) - mt753x_reg_write(priv, PCR_REG(i), - (0x40 << PORT_MATRIX_S)); - else - mt753x_reg_write(priv, PCR_REG(i), - (0x3f << PORT_MATRIX_S)); + ret = tmp->detect(priv); + if (!ret) { + swdrv = tmp; + break; + } + } + + if (!swdrv) { + printf("Error: unable to detect switch\n"); + return -ENODEV; + } + } else { + if (swdrv->detect) { + ret = swdrv->detect(priv); + if (ret) { + printf("Error: switch probing failed\n"); + return -ENODEV; + } + } + } + + printf("%s\n", swdrv->desc); + + priv_size = swdrv->priv_size; + if (priv_size < sizeof(struct mtk_eth_switch_priv)) + priv_size = sizeof(struct mtk_eth_switch_priv); + + priv->swpriv = calloc(1, priv_size); + if (!priv->swpriv) { + printf("Error: no memory for switch data\n"); + return -ENOMEM; + } + + priv->swpriv->eth = priv; + priv->swpriv->soc = priv->soc; + priv->swpriv->phy_interface = priv->phy_interface; + priv->swpriv->sw = swdrv; + priv->swpriv->ethsys_base = regmap_get_range(priv->ethsys_regmap, 0); - /* Set port mode to user port */ - mt753x_reg_write(priv, PVC_REG(i), - (0x8100 << STAG_VPID_S) | - (VLAN_ATTR_USER << VLAN_ATTR_S)); + ret = swdrv->setup(priv->swpriv); + if (ret) { + free(priv->swpriv); + priv->swpriv = NULL; + return ret; } return 0; @@ -1759,7 +1061,8 @@ static int mtk_eth_start(struct udevice *dev) } if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) { - if (priv->sw == SW_MT7988 && priv->gmac_id == 0) { + if (priv->swpriv && !strcmp(priv->swpriv->sw->name, "mt7988") && + priv->gmac_id == 0) { mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_BRIDGE_TO_CPU); @@ -1778,11 +1081,12 @@ static int mtk_eth_start(struct udevice *dev) mtk_eth_fifo_init(priv); - if (priv->switch_mac_control) - priv->switch_mac_control(priv, true); - - /* Start PHY */ - if (priv->sw == SW_NONE) { + if (priv->swpriv) { + /* Enable communication with switch */ + if (priv->swpriv->sw->mac_control) + priv->swpriv->sw->mac_control(priv->swpriv, true); + } else { + /* Start PHY */ ret = mtk_phy_start(priv); if (ret) return ret; @@ -1799,8 +1103,10 @@ static void mtk_eth_stop(struct udevice *dev) { struct mtk_eth_priv *priv = dev_get_priv(dev); - if (priv->switch_mac_control) - priv->switch_mac_control(priv, false); + if (priv->swpriv) { + if (priv->swpriv->sw->mac_control) + priv->swpriv->sw->mac_control(priv->swpriv, false); + } mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0); @@ -1953,11 +1259,11 @@ static int mtk_eth_probe(struct udevice *dev) return ret; /* Probe phy if switch is not specified */ - if (priv->sw == SW_NONE) + if (!priv->swname) return mtk_phy_probe(dev); /* Initialize switch */ - return mt753x_switch_init(priv); + return mtk_switch_init(priv); } static int mtk_eth_remove(struct udevice *dev) @@ -1971,6 +1277,12 @@ static int mtk_eth_remove(struct udevice *dev) /* Stop possibly started DMA */ mtk_eth_stop(dev); + if (priv->swpriv) { + if (priv->swpriv->sw->cleanup) + priv->swpriv->sw->cleanup(priv->swpriv); + free(priv->swpriv); + } + return 0; } @@ -1980,7 +1292,6 @@ static int mtk_eth_of_to_plat(struct udevice *dev) struct mtk_eth_priv *priv = dev_get_priv(dev); struct ofnode_phandle_args args; struct regmap *regmap; - const char *str; ofnode subnode; int ret; @@ -2126,36 +1437,8 @@ static int mtk_eth_of_to_plat(struct udevice *dev) return PTR_ERR(priv->toprgu_regmap); } - /* check for switch first, otherwise phy will be used */ - priv->sw = SW_NONE; - priv->switch_init = NULL; - priv->switch_mac_control = NULL; - str = dev_read_string(dev, "mediatek,switch"); - - if (str) { - if (!strcmp(str, "mt7530")) { - priv->sw = SW_MT7530; - priv->switch_init = mt7530_setup; - priv->switch_mac_control = mt7530_mac_control; - priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; - priv->mt753x_reset_wait_time = 1000; - } else if (!strcmp(str, "mt7531")) { - priv->sw = SW_MT7531; - priv->switch_init = mt7531_setup; - priv->switch_mac_control = mt7531_mac_control; - priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; - priv->mt753x_reset_wait_time = 200; - } else if (!strcmp(str, "mt7988")) { - priv->sw = SW_MT7988; - priv->switch_init = mt7988_setup; - priv->switch_mac_control = mt7988_mac_control; - priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; - priv->mt753x_reset_wait_time = 50; - } else { - printf("error: unsupported switch\n"); - return -EINVAL; - } - + priv->swname = dev_read_string(dev, "mediatek,switch"); + if (priv->swname) { priv->mcm = dev_read_bool(dev, "mediatek,mcm"); if (priv->mcm) { ret = reset_get_by_name(dev, "mcm", &priv->rst_mcm); @@ -2194,6 +1477,15 @@ static const struct mtk_soc_data mt7988_data = { .rxd_size = sizeof(struct mtk_rx_dma_v2), }; +static const struct mtk_soc_data mt7987_data = { + .caps = MT7987_CAPS, + .ana_rgc3 = 0x128, + .gdma_count = 3, + .pdma_base = PDMA_V3_BASE, + .txd_size = sizeof(struct mtk_tx_dma_v2), + .rxd_size = sizeof(struct mtk_rx_dma_v2), +}; + static const struct mtk_soc_data mt7986_data = { .caps = MT7986_CAPS, .ana_rgc3 = 0x128, @@ -2248,6 +1540,7 @@ static const struct mtk_soc_data mt7621_data = { static const struct udevice_id mtk_eth_ids[] = { { .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data }, + { .compatible = "mediatek,mt7987-eth", .data = (ulong)&mt7987_data }, { .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data }, { .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data }, { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data }, @@ -2271,10 +1564,10 @@ U_BOOT_DRIVER(mtk_eth) = { .id = UCLASS_ETH, .of_match = mtk_eth_ids, .of_to_plat = mtk_eth_of_to_plat, - .plat_auto = sizeof(struct eth_pdata), + .plat_auto = sizeof(struct eth_pdata), .probe = mtk_eth_probe, .remove = mtk_eth_remove, .ops = &mtk_eth_ops, - .priv_auto = sizeof(struct mtk_eth_priv), + .priv_auto = sizeof(struct mtk_eth_priv), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth/mtk_eth.h index 1aa037907c5..0ad32799128 100644 --- a/drivers/net/mtk_eth.h +++ b/drivers/net/mtk_eth/mtk_eth.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 MediaTek Inc. + * Copyright (C) 2025 MediaTek Inc. * * Author: Weijie Gao <weijie.gao@mediatek.com> * Author: Mark Lee <mark-mc.lee@mediatek.com> @@ -9,9 +9,55 @@ #ifndef _MTK_ETH_H_ #define _MTK_ETH_H_ +#include <linker_lists.h> #include <linux/bitops.h> #include <linux/bitfield.h> +struct mtk_eth_priv; +struct mtk_eth_switch_priv; + +/* struct mtk_soc_data - This is the structure holding all differences + * among various plaforms + * @caps Flags shown the extra capability for the SoC + * @ana_rgc3: The offset for register ANA_RGC3 related to + * sgmiisys syscon + * @gdma_count: Number of GDMAs + * @pdma_base: Register base of PDMA block + * @txd_size: Tx DMA descriptor size. + * @rxd_size: Rx DMA descriptor size. + */ +struct mtk_soc_data { + u32 caps; + u32 ana_rgc3; + u32 gdma_count; + u32 pdma_base; + u32 txd_size; + u32 rxd_size; +}; + +struct mtk_eth_switch { + const char *name; + const char *desc; + size_t priv_size; + u32 reset_wait_time; + + int (*detect)(struct mtk_eth_priv *priv); + int (*setup)(struct mtk_eth_switch_priv *priv); + int (*cleanup)(struct mtk_eth_switch_priv *priv); + void (*mac_control)(struct mtk_eth_switch_priv *priv, bool enable); +}; + +#define MTK_ETH_SWITCH(__name) \ + ll_entry_declare(struct mtk_eth_switch, __name, mtk_eth_switch) + +struct mtk_eth_switch_priv { + struct mtk_eth_priv *eth; + const struct mtk_eth_switch *sw; + const struct mtk_soc_data *soc; + void *ethsys_base; + int phy_interface; +}; + enum mkt_eth_capabilities { MTK_TRGMII_BIT, MTK_TRGMII_MT7621_CLK_BIT, @@ -36,7 +82,6 @@ enum mkt_eth_capabilities { /* Supported path present on SoCs */ #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) - #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) #define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT) #define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT) @@ -59,6 +104,8 @@ enum mkt_eth_capabilities { #define MT7986_CAPS (MTK_NETSYS_V2) +#define MT7987_CAPS (MTK_NETSYS_V3 | MTK_GMAC2_U3_QPHY | MTK_INFRA) + #define MT7988_CAPS (MTK_NETSYS_V3 | MTK_INFRA) /* Frame Engine Register Bases */ @@ -72,7 +119,6 @@ enum mkt_eth_capabilities { #define GSW_BASE 0x20000 /* Ethernet subsystem registers */ - #define ETHSYS_SYSCFG1_REG 0x14 #define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2)) #define SYSCFG1_GE_MODE_M 0x3 @@ -191,7 +237,6 @@ enum mkt_eth_capabilities { #define DP_DISCARD 7 /* GMAC Registers */ - #define GMAC_PPSC_REG 0x0000 #define PHY_MDC_CFG GENMASK(29, 24) #define MDC_TURBO BIT(20) @@ -272,6 +317,8 @@ enum mkt_eth_capabilities { #define RX_RST BIT(31) #define RXC_DQSISEL BIT(30) +#define NUM_TRGMII_CTRL 5 + #define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8) #define TD_DM_DRVN_S 4 #define TD_DM_DRVN_M 0xf0 @@ -288,164 +335,7 @@ enum mkt_eth_capabilities { #define XGMAC_FORCE_TX_FC BIT(5) #define XGMAC_FORCE_RX_FC BIT(4) -/* MT7530 Registers */ - -#define PCR_REG(p) (0x2004 + (p) * 0x100) -#define PORT_MATRIX_S 16 -#define PORT_MATRIX_M 0xff0000 - -#define PVC_REG(p) (0x2010 + (p) * 0x100) -#define STAG_VPID_S 16 -#define STAG_VPID_M 0xffff0000 -#define VLAN_ATTR_S 6 -#define VLAN_ATTR_M 0xc0 - -/* VLAN_ATTR: VLAN attributes */ -#define VLAN_ATTR_USER 0 -#define VLAN_ATTR_STACK 1 -#define VLAN_ATTR_TRANSLATION 2 -#define VLAN_ATTR_TRANSPARENT 3 - -#define PMCR_REG(p) (0x3000 + (p) * 0x100) -/* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR - * MT7531 specific fields are defined below - */ -#define FORCE_MODE_EEE1G BIT(25) -#define FORCE_MODE_EEE100 BIT(26) -#define FORCE_MODE_TX_FC BIT(27) -#define FORCE_MODE_RX_FC BIT(28) -#define FORCE_MODE_DPX BIT(29) -#define FORCE_MODE_SPD BIT(30) -#define FORCE_MODE_LNK BIT(31) -#define MT7531_FORCE_MODE FORCE_MODE_EEE1G | FORCE_MODE_EEE100 |\ - FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ - FORCE_MODE_DPX | FORCE_MODE_SPD | \ - FORCE_MODE_LNK -#define MT7988_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ - FORCE_MODE_DPX | FORCE_MODE_SPD | \ - FORCE_MODE_LNK - -/* MT7531 SGMII Registers */ -#define MT7531_SGMII_REG_BASE 0x5000 -#define MT7531_SGMII_REG_PORT_BASE 0x1000 -#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \ - (p) * MT7531_SGMII_REG_PORT_BASE + (r)) -#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(((p) - 5), 0x00) -#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(((p) - 5), 0x20) -#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(((p) - 5), 0xe8) -#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(((p) - 5), 0x128) -/* XXX: all fields of MT7531 SGMII are defined under SGMSYS */ - -/* MT753x System Control Register */ -#define SYS_CTRL_REG 0x7000 -#define SW_PHY_RST BIT(2) -#define SW_SYS_RST BIT(1) -#define SW_REG_RST BIT(0) - -/* MT7531 */ -#define MT7531_PHY_IAC 0x701c -/* XXX: all fields are defined under GMAC_PIAC_REG */ - -#define MT7531_CLKGEN_CTRL 0x7500 -#define CLK_SKEW_OUT_S 8 -#define CLK_SKEW_OUT_M 0x300 -#define CLK_SKEW_IN_S 6 -#define CLK_SKEW_IN_M 0xc0 -#define RXCLK_NO_DELAY BIT(5) -#define TXCLK_NO_REVERSE BIT(4) -#define GP_MODE_S 1 -#define GP_MODE_M 0x06 -#define GP_CLK_EN BIT(0) - -/* Values of GP_MODE */ -#define GP_MODE_RGMII 0 -#define GP_MODE_MII 1 -#define GP_MODE_REV_MII 2 - -/* Values of CLK_SKEW_IN */ -#define CLK_SKEW_IN_NO_CHANGE 0 -#define CLK_SKEW_IN_DELAY_100PPS 1 -#define CLK_SKEW_IN_DELAY_200PPS 2 -#define CLK_SKEW_IN_REVERSE 3 - -/* Values of CLK_SKEW_OUT */ -#define CLK_SKEW_OUT_NO_CHANGE 0 -#define CLK_SKEW_OUT_DELAY_100PPS 1 -#define CLK_SKEW_OUT_DELAY_200PPS 2 -#define CLK_SKEW_OUT_REVERSE 3 - -#define HWTRAP_REG 0x7800 -/* MT7530 Modified Hardware Trap Status Registers */ -#define MHWTRAP_REG 0x7804 -#define CHG_TRAP BIT(16) -#define LOOPDET_DIS BIT(14) -#define P5_INTF_SEL_S 13 -#define P5_INTF_SEL_M 0x2000 -#define SMI_ADDR_S 11 -#define SMI_ADDR_M 0x1800 -#define XTAL_FSEL_S 9 -#define XTAL_FSEL_M 0x600 -#define P6_INTF_DIS BIT(8) -#define P5_INTF_MODE_S 7 -#define P5_INTF_MODE_M 0x80 -#define P5_INTF_DIS BIT(6) -#define C_MDIO_BPS BIT(5) -#define CHIP_MODE_S 0 -#define CHIP_MODE_M 0x0f - -/* P5_INTF_SEL: Interface type of Port5 */ -#define P5_INTF_SEL_GPHY 0 -#define P5_INTF_SEL_GMAC5 1 - -/* P5_INTF_MODE: Interface mode of Port5 */ -#define P5_INTF_MODE_GMII_MII 0 -#define P5_INTF_MODE_RGMII 1 - -#define MT7530_P6ECR 0x7830 -#define P6_INTF_MODE_M 0x3 -#define P6_INTF_MODE_S 0 - -/* P6_INTF_MODE: Interface mode of Port6 */ -#define P6_INTF_MODE_RGMII 0 -#define P6_INTF_MODE_TRGMII 1 - -#define NUM_TRGMII_CTRL 5 - -#define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8) -#define RD_TAP_S 0 -#define RD_TAP_M 0x7f - -#define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8) -/* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */ - -/* TOP Signals Status Register */ -#define MT7531_TOP_SIG_SR 0x780c -#define PAD_MCM_SMI_EN BIT(0) -#define PAD_DUAL_SGMII_EN BIT(1) - -/* MT7531 PLLGP Registers */ -#define MT7531_PLLGP_EN 0x7820 -#define EN_COREPLL BIT(2) -#define SW_CLKSW BIT(1) -#define SW_PLLGP BIT(0) - -#define MT7531_PLLGP_CR0 0x78a8 -#define RG_COREPLL_EN BIT(22) -#define RG_COREPLL_POSDIV_S 23 -#define RG_COREPLL_POSDIV_M 0x3800000 -#define RG_COREPLL_SDM_PCW_S 1 -#define RG_COREPLL_SDM_PCW_M 0x3ffffe -#define RG_COREPLL_SDM_PCW_CHG BIT(0) - -/* MT7531 RGMII and SGMII PLL clock */ -#define MT7531_ANA_PLLGP_CR2 0x78b0 -#define MT7531_ANA_PLLGP_CR5 0x78bc - -/* MT7531 GPIO GROUP IOLB SMT0 Control */ -#define MT7531_SMT0_IOLB 0x7f04 -#define SMT_IOLB_5_SMI_MDC_EN BIT(5) - -/* MT7530 GPHY MDIO Indirect Access Registers */ +/* MDIO Indirect Access Registers */ #define MII_MMD_ACC_CTL_REG 0x0d #define MMD_CMD_S 14 #define MMD_CMD_M 0xc000 @@ -460,80 +350,6 @@ enum mkt_eth_capabilities { #define MII_MMD_ADDR_DATA_REG 0x0e -/* MT7530 GPHY MDIO MMD Registers */ -#define CORE_PLL_GROUP2 0x401 -#define RG_SYSPLL_EN_NORMAL BIT(15) -#define RG_SYSPLL_VODEN BIT(14) -#define RG_SYSPLL_POSDIV_S 5 -#define RG_SYSPLL_POSDIV_M 0x60 - -#define CORE_PLL_GROUP4 0x403 -#define MT7531_BYPASS_MODE BIT(4) -#define MT7531_POWER_ON_OFF BIT(5) -#define RG_SYSPLL_DDSFBK_EN BIT(12) -#define RG_SYSPLL_BIAS_EN BIT(11) -#define RG_SYSPLL_BIAS_LPF_EN BIT(10) - -#define CORE_PLL_GROUP5 0x404 -#define RG_LCDDS_PCW_NCPO1_S 0 -#define RG_LCDDS_PCW_NCPO1_M 0xffff - -#define CORE_PLL_GROUP6 0x405 -#define RG_LCDDS_PCW_NCPO0_S 0 -#define RG_LCDDS_PCW_NCPO0_M 0xffff - -#define CORE_PLL_GROUP7 0x406 -#define RG_LCDDS_PWDB BIT(15) -#define RG_LCDDS_ISO_EN BIT(13) -#define RG_LCCDS_C_S 4 -#define RG_LCCDS_C_M 0x70 -#define RG_LCDDS_PCW_NCPO_CHG BIT(3) - -#define CORE_PLL_GROUP10 0x409 -#define RG_LCDDS_SSC_DELTA_S 0 -#define RG_LCDDS_SSC_DELTA_M 0xfff - -#define CORE_PLL_GROUP11 0x40a -#define RG_LCDDS_SSC_DELTA1_S 0 -#define RG_LCDDS_SSC_DELTA1_M 0xfff - -#define CORE_GSWPLL_GRP1 0x40d -#define RG_GSWPLL_POSDIV_200M_S 12 -#define RG_GSWPLL_POSDIV_200M_M 0x3000 -#define RG_GSWPLL_EN_PRE BIT(11) -#define RG_GSWPLL_FBKDIV_200M_S 0 -#define RG_GSWPLL_FBKDIV_200M_M 0xff - -#define CORE_GSWPLL_GRP2 0x40e -#define RG_GSWPLL_POSDIV_500M_S 8 -#define RG_GSWPLL_POSDIV_500M_M 0x300 -#define RG_GSWPLL_FBKDIV_500M_S 0 -#define RG_GSWPLL_FBKDIV_500M_M 0xff - -#define CORE_TRGMII_GSW_CLK_CG 0x410 -#define REG_GSWCK_EN BIT(0) -#define REG_TRGMIICK_EN BIT(1) - -/* Extend PHY Control Register 3 */ -#define PHY_EXT_REG_14 0x14 - -/* Fields of PHY_EXT_REG_14 */ -#define PHY_EN_DOWN_SHFIT BIT(4) - -/* Extend PHY Control Register 4 */ -#define PHY_EXT_REG_17 0x17 - -/* Fields of PHY_EXT_REG_17 */ -#define PHY_LINKDOWN_POWER_SAVING_EN BIT(4) - -/* PHY RXADC Control Register 7 */ -#define PHY_DEV1E_REG_0C6 0x0c6 - -/* Fields of PHY_DEV1E_REG_0C6 */ -#define PHY_POWER_SAVING_S 8 -#define PHY_POWER_SAVING_M 0x300 -#define PHY_POWER_SAVING_TX 0x0 - /* PDMA descriptors */ struct mtk_rx_dma { unsigned int rxd1; @@ -597,4 +413,17 @@ struct mtk_tx_dma_v2 { #define PDMA_V2_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V2_RXD2_PLEN0_M, (_v)) #define PDMA_V2_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V2_RXD2_PLEN0_M, (_v)) +void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set); +void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set); +void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set); + +int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg); +int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data); +int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg); +int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, + u16 val); +int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg); +int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, + u16 val); + #endif /* _MTK_ETH_H_ */ diff --git a/drivers/pci/pcie_mediatek_gen3.c b/drivers/pci/pcie_mediatek_gen3.c index 0149edae0bf..1818d4c1e30 100644 --- a/drivers/pci/pcie_mediatek_gen3.c +++ b/drivers/pci/pcie_mediatek_gen3.c @@ -83,6 +83,28 @@ struct mtk_pcie { struct phy phy; }; +static pci_dev_t convert_bdf(const struct udevice *controller, pci_dev_t bdf) +{ + int bdfs[3]; + + bdfs[0] = PCI_BUS(bdf); + bdfs[1] = PCI_DEV(bdf); + bdfs[2] = PCI_FUNC(bdf); + + /* + * One MediaTek PCIe Gen3 controller has only one port, where PCI bus 0 on + * this port represents the controller itself and bus 1 represents the + * external PCIe device. If multiple PCIe controllers are probed in U-Boot, + * U-Boot will use bus numbers greater than 2 as input parameters. Therefore, + * we should convert the BDF bus number to either 0 or 1 by subtracting the + * offset by controller->seq_ + */ + + bdfs[0] = bdfs[0] - controller->seq_; + + return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]); +} + static void mtk_pcie_config_tlp_header(const struct udevice *bus, pci_dev_t devfn, int where, int size) @@ -91,6 +113,8 @@ static void mtk_pcie_config_tlp_header(const struct udevice *bus, int bytes; u32 val; + devfn = convert_bdf(bus, devfn); + size = 1 << size; bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3); diff --git a/drivers/pwm/pwm-mtk.c b/drivers/pwm/pwm-mtk.c index 9776a41ff48..5cf2eba2ba0 100644 --- a/drivers/pwm/pwm-mtk.c +++ b/drivers/pwm/pwm-mtk.c @@ -192,7 +192,7 @@ static const struct mtk_pwm_soc mt7629_data = { }; static const struct mtk_pwm_soc mt7981_data = { - .num_pwms = 2, + .num_pwms = 3, .pwm45_fixup = false, .reg_ver = PWM_REG_V2, }; diff --git a/drivers/spi/mtk_spim.c b/drivers/spi/mtk_spim.c index b66bcfc4233..2b2c31b4b3f 100644 --- a/drivers/spi/mtk_spim.c +++ b/drivers/spi/mtk_spim.c @@ -359,6 +359,9 @@ static bool mtk_spim_supports_op(struct spi_slave *slave, struct udevice *bus = dev_get_parent(slave->dev); struct mtk_spim_priv *priv = dev_get_priv(bus); + if (!spi_mem_default_supports_op(slave, op)) + return false; + if (op->cmd.buswidth == 0 || op->cmd.buswidth > 4 || op->addr.buswidth > 4 || op->dummy.buswidth > 4 || op->data.buswidth > 4) @@ -648,7 +651,7 @@ static int mtk_spim_probe(struct udevice *dev) struct mtk_spim_priv *priv = dev_get_priv(dev); int ret; - priv->base = devfdt_get_addr_ptr(dev); + priv->base = dev_read_addr_ptr(dev); if (!priv->base) return -EINVAL; |