diff options
697 files changed, 21781 insertions, 8300 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index e1b2f87b974..93111eb6127 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -2,7 +2,7 @@ variables: windows_vm: windows-2019 ubuntu_vm: ubuntu-22.04 macos_vm: macOS-12 - ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240227-14Mar2024 + ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240808-21Aug2024 # Add '-u 0' options for Azure pipelines, otherwise we get "permission # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # since our $(ci_runner_image) user is not root. diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 0a15b7352cd..7d621031b85 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -10,7 +10,7 @@ default: # Grab our configured image. The source for this is found # in the u-boot tree at tools/docker/Dockerfile -image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240227-14Mar2024 +image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240808-21Aug2024 # We run some tests in different order, to catch some failures quicker. stages: @@ -1,6 +1,6 @@ # # For a description of the syntax of this configuration file, -# see the file Documentation/kbuild/kconfig-language.txt in the +# see the file Documentation/kbuild/kconfig-language.rst in the # Linux kernel source tree. # mainmenu "U-Boot $(UBOOTVERSION) Configuration" diff --git a/MAINTAINERS b/MAINTAINERS index daaf0345d0e..7ab39d91a55 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -617,6 +617,7 @@ R: Sumit Garg <sumit.garg@linaro.org> L: u-boot-qcom@groups.io S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-snapdragon.git +F: configs/qcm6490_defconfig F: drivers/*/*/pm8???-* F: drivers/gpio/msm_gpio.c F: drivers/mmc/msm_sdhci.c @@ -3,7 +3,7 @@ VERSION = 2024 PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = -rc3 +EXTRAVERSION = -rc4 NAME = # *DOCUMENTATION* diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 22e748868a7..5169fc627fa 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -10,7 +10,6 @@ #include <linux/compiler.h> #include <linux/kernel.h> #include <linux/log2.h> -#include <lmb.h> #include <asm/arcregs.h> #include <asm/arc-bcr.h> #include <asm/cache.h> @@ -820,16 +819,3 @@ void sync_n_cleanup_cache_all(void) __ic_entire_invalidate(); } - -static ulong get_sp(void) -{ - ulong ret; - - asm("mov %0, sp" : "=r"(ret) : ); - return ret; -} - -void arch_lmb_reserve(struct lmb *lmb) -{ - arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); -} diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 76a69d7f958..dd748328293 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -117,7 +117,7 @@ static void mxs_spl_console_init(void) gd->bd = &bdata; gd->baudrate = CONFIG_BAUDRATE; serial_init(); - gd->have_console = 1; + gd->flags |= GD_FLG_HAVE_CONSOLE; #endif } diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index c3f8dac648b..631d9efa5e1 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -339,6 +339,31 @@ static void map_range(u64 virt, u64 phys, u64 size, int level, } } +void mmu_map_region(phys_addr_t addr, u64 size, bool emergency) +{ + u64 va_bits; + int level = 0; + u64 attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; + + attrs |= PTE_TYPE_BLOCK | PTE_BLOCK_AF; + + get_tcr(NULL, &va_bits); + if (va_bits < 39) + level = 1; + + if (emergency) + map_range(addr, addr, size, level, + (u64 *)gd->arch.tlb_emerg, attrs); + + /* Switch pagetables while we update the primary one */ + __asm_switch_ttbr(gd->arch.tlb_emerg); + + map_range(addr, addr, size, level, + (u64 *)gd->arch.tlb_addr, attrs); + + __asm_switch_ttbr(gd->arch.tlb_addr); +} + static void add_map(struct mm_region *map) { u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF; diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 4d59e98e808..56d4af518d8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -987,14 +987,8 @@ dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \ at91sam9g25-gardena-smart-gateway.dtb -dtb-$(CONFIG_TARGET_ETHERNUT5) += ethernut5.dtb - dtb-$(CONFIG_TARGET_USB_A9263) += usb_a9263.dtb -dtb-$(CONFIG_TARGET_OMAP3_EVM) += \ - omap3-evm-37xx.dtb \ - omap3-evm.dtb - dtb-$(CONFIG_TARGET_DEVKIT8000) += omap3-devkit8000.dtb dtb-$(CONFIG_TARGET_SAMA7G5EK) += \ diff --git a/arch/arm/dts/at91sam9xe.dtsi b/arch/arm/dts/at91sam9xe.dtsi deleted file mode 100644 index 0278f63b2da..00000000000 --- a/arch/arm/dts/at91sam9xe.dtsi +++ /dev/null @@ -1,60 +0,0 @@ -/* - * at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC - * - * Copyright (C) 2015 Atmel, - * 2015 Alexandre Belloni <alexandre.Belloni@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "at91sam9260.dtsi" - -/ { - model = "Atmel AT91SAM9XE family SoC"; - compatible = "atmel,at91sam9xe", "atmel,at91sam9260"; - - sram0: sram@002ff000 { - status = "disabled"; - }; - - sram1: sram@00300000 { - compatible = "mmio-sram"; - reg = <0x00300000 0x4000>; - }; -}; diff --git a/arch/arm/dts/ethernut5.dts b/arch/arm/dts/ethernut5.dts deleted file mode 100644 index 5c24deaf4b6..00000000000 --- a/arch/arm/dts/ethernut5.dts +++ /dev/null @@ -1,96 +0,0 @@ -/* - * ethernut5.dts - Device Tree file for Ethernut 5 board - * - * Copyright (C) 2012 egnite GmbH <info@egnite.de> - * - * Licensed under GPLv2. - */ -/dts-v1/; -#include "at91sam9xe.dtsi" - -/ { - model = "Ethernut 5"; - compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2"; - }; - - memory { - reg = <0x20000000 0x08000000>; - }; - - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <18432000>; - }; - }; - - ahb { - apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - - usart0: serial@fffb0000 { - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - }; - - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - - gpios = <0 - &pioC 14 GPIO_ACTIVE_HIGH - 0 - >; - - root@0 { - label = "root"; - reg = <0x0 0x08000000>; - }; - - data@20000 { - label = "data"; - reg = <0x08000000 0x38000000>; - }; - }; - - usb0: ohci@00500000 { - num-ports = <2>; - status = "okay"; - }; - }; - - i2c-gpio-0 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - pcf8563@50 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; -}; diff --git a/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi b/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi index 78457ef68f4..c8c0fc1fba7 100644 --- a/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi @@ -10,6 +10,22 @@ }; }; +&aips2 { + bootph-all; +}; + +&pinctrl_uart2 { + bootph-all; +}; + +&soc { + bootph-all; +}; + +&uart2 { + bootph-all; +}; + &wdog1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx6sl-evk.dts b/arch/arm/dts/imx6sl-evk.dts deleted file mode 100644 index f16c830f1e9..00000000000 --- a/arch/arm/dts/imx6sl-evk.dts +++ /dev/null @@ -1,658 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -//Copyright (C) 2013 Freescale Semiconductor, Inc. - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include "imx6sl.dtsi" - -/ { - model = "Freescale i.MX6 SoloLite EVK Board"; - compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; - - chosen { - stdout-path = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - backlight_display: backlight_display { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led>; - - user { - label = "debug"; - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - reg_aud3v: regulator-aud3v { - compatible = "regulator-fixed"; - regulator-name = "wm8962-supply-3v15"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-boot-on; - }; - - reg_aud4v: regulator-aud4v { - compatible = "regulator-fixed"; - regulator-name = "wm8962-supply-4v2"; - regulator-min-microvolt = <4325000>; - regulator-max-microvolt = <4325000>; - regulator-boot-on; - }; - - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lcd_3v3>; - regulator-name = "lcd-3v3"; - gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lcd_5v: regulator-lcd-5v { - compatible = "regulator-fixed"; - regulator-name = "lcd-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - sound { - compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hp>; - model = "wm8962-audio"; - ssi-controller = <&ssi2>; - audio-codec = <&codec>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - mux-int-port = <2>; - mux-ext-port = <3>; - hp-det-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; - }; - - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux3>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p32", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_fec>; - pinctrl-1 = <&pinctrl_fec_sleep>; - phy-mode = "rmii"; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - codec: wm8962@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>; - DCVDD-supply = <&vgen3_reg>; - DBVDD-supply = <®_aud3v>; - AVDD-supply = <&vgen3_reg>; - CPVDD-supply = <&vgen3_reg>; - MICVDD-supply = <®_aud3v>; - PLLVDD-supply = <&vgen3_reg>; - SPKVDD1-supply = <®_aud4v>; - SPKVDD2-supply = <®_aud4v>; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6sl-evk { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 - MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059 - MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059 - MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059 - MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 - MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 - MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 - MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 - >; - }; - - pinctrl_audmux3: audmux3grp { - fsl,pins = < - MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 - MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 - MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 - MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 - MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 - MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 - MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 - MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 - MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 - MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 - MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 - MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 - MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 - MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 - MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8 - >; - }; - - pinctrl_fec_sleep: fecgrp-sleep { - fsl,pins = < - MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080 - MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080 - MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080 - MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080 - MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080 - MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080 - MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080 - MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080 - >; - }; - - pinctrl_hp: hpgrp { - fsl,pins = < - MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 - MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 - >; - }; - - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1 - MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_kpp: kppgrp { - fsl,pins = < - MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 - MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010 - MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0 - MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0 - MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0 - MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0 - >; - }; - - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0 - MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0 - MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0 - MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0 - MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0 - MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0 - MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0 - MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0 - MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0 - MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0 - MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0 - MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0 - MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0 - MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0 - MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0 - MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0 - MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0 - MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0 - MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0 - MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0 - MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0 - MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0 - MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0 - MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0 - MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0 - MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0 - MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0 - MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0 - >; - }; - - pinctrl_led: ledgrp { - fsl,pins = < - MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059 - >; - }; - - pinctrl_pwm1: pwmgrp { - fsl,pins = < - MX6SL_PAD_PWM1__PWM1_OUT 0x110b0 - >; - }; - - pinctrl_reg_lcd_3v3: reglcd3v3grp { - fsl,pins = < - MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 - MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 - MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - >; - }; - }; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - linux,keymap = < - MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */ - MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */ - MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */ - MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */ - MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */ - MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */ - MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */ - MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */ - >; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - -&pwm1 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -®_vdd1p1 { - vin-supply = <&sw2_reg>; -}; - -®_vdd2p5 { - vin-supply = <&sw2_reg>; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/arch/arm/dts/imx6sl-pinfunc.h b/arch/arm/dts/imx6sl-pinfunc.h deleted file mode 100644 index bcf16060ecd..00000000000 --- a/arch/arm/dts/imx6sl-pinfunc.h +++ /dev/null @@ -1,1073 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6SL_PINFUNC_H -#define __DTS_IMX6SL_PINFUNC_H - -/* - * The pin function ID is a tuple of - * <mux_reg conf_reg input_reg mux_mode input_val> - */ -#define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 -#define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 -#define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 -#define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 -#define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 -#define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x050 0x2a8 0x80c 0x2 0x0 -#define MX6SL_PAD_AUD_RXC__FEC_TX_CLK 0x050 0x2a8 0x70c 0x3 0x0 -#define MX6SL_PAD_AUD_RXC__I2C3_SDA 0x050 0x2a8 0x730 0x4 0x0 -#define MX6SL_PAD_AUD_RXC__GPIO1_IO01 0x050 0x2a8 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_RXC__ECSPI3_SS1 0x050 0x2a8 0x6c4 0x6 0x0 -#define MX6SL_PAD_AUD_RXD__AUD3_RXD 0x054 0x2ac 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI 0x054 0x2ac 0x6bc 0x1 0x0 -#define MX6SL_PAD_AUD_RXD__UART4_RX_DATA 0x054 0x2ac 0x814 0x2 0x0 -#define MX6SL_PAD_AUD_RXD__UART4_TX_DATA 0x054 0x2ac 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_RXD__FEC_RX_ER 0x054 0x2ac 0x708 0x3 0x0 -#define MX6SL_PAD_AUD_RXD__SD1_LCTL 0x054 0x2ac 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_RXD__GPIO1_IO02 0x054 0x2ac 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_RXFS__AUD3_RXFS 0x058 0x2b0 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_RXFS__I2C1_SCL 0x058 0x2b0 0x71c 0x1 0x0 -#define MX6SL_PAD_AUD_RXFS__UART3_RX_DATA 0x058 0x2b0 0x80c 0x2 0x1 -#define MX6SL_PAD_AUD_RXFS__UART3_TX_DATA 0x058 0x2b0 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_RXFS__FEC_MDIO 0x058 0x2b0 0x6f4 0x3 0x0 -#define MX6SL_PAD_AUD_RXFS__I2C3_SCL 0x058 0x2b0 0x72c 0x4 0x0 -#define MX6SL_PAD_AUD_RXFS__GPIO1_IO00 0x058 0x2b0 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_RXFS__ECSPI3_SS0 0x058 0x2b0 0x6c0 0x6 0x0 -#define MX6SL_PAD_AUD_TXC__AUD3_TXC 0x05c 0x2b4 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_TXC__ECSPI3_MISO 0x05c 0x2b4 0x6b8 0x1 0x0 -#define MX6SL_PAD_AUD_TXC__UART4_TX_DATA 0x05c 0x2b4 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_TXC__UART4_RX_DATA 0x05c 0x2b4 0x814 0x2 0x1 -#define MX6SL_PAD_AUD_TXC__FEC_RX_DV 0x05c 0x2b4 0x704 0x3 0x0 -#define MX6SL_PAD_AUD_TXC__SD2_LCTL 0x05c 0x2b4 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_TXC__GPIO1_IO03 0x05c 0x2b4 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_TXD__AUD3_TXD 0x060 0x2b8 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK 0x060 0x2b8 0x6b0 0x1 0x0 -#define MX6SL_PAD_AUD_TXD__UART4_CTS_B 0x060 0x2b8 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_TXD__UART4_RTS_B 0x060 0x2b8 0x810 0x2 0x0 -#define MX6SL_PAD_AUD_TXD__FEC_TX_DATA0 0x060 0x2b8 0x000 0x3 0x0 -#define MX6SL_PAD_AUD_TXD__SD4_LCTL 0x060 0x2b8 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_TXD__GPIO1_IO05 0x060 0x2b8 0x000 0x5 0x0 -#define MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x064 0x2bc 0x000 0x0 0x0 -#define MX6SL_PAD_AUD_TXFS__PWM3_OUT 0x064 0x2bc 0x000 0x1 0x0 -#define MX6SL_PAD_AUD_TXFS__UART4_RTS_B 0x064 0x2bc 0x810 0x2 0x1 -#define MX6SL_PAD_AUD_TXFS__UART4_CTS_B 0x064 0x2bc 0x000 0x2 0x0 -#define MX6SL_PAD_AUD_TXFS__FEC_RX_DATA1 0x064 0x2bc 0x6fc 0x3 0x0 -#define MX6SL_PAD_AUD_TXFS__SD3_LCTL 0x064 0x2bc 0x000 0x4 0x0 -#define MX6SL_PAD_AUD_TXFS__GPIO1_IO04 0x064 0x2bc 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x068 0x358 0x684 0x0 0x0 -#define MX6SL_PAD_ECSPI1_MISO__AUD4_TXFS 0x068 0x358 0x5f8 0x1 0x0 -#define MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x068 0x358 0x818 0x2 0x0 -#define MX6SL_PAD_ECSPI1_MISO__UART5_CTS_B 0x068 0x358 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR0 0x068 0x358 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI1_MISO__SD2_WP 0x068 0x358 0x834 0x4 0x0 -#define MX6SL_PAD_ECSPI1_MISO__GPIO4_IO10 0x068 0x358 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x06c 0x35c 0x688 0x0 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__AUD4_TXC 0x06c 0x35c 0x5f4 0x1 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x06c 0x35c 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__UART5_RX_DATA 0x06c 0x35c 0x81c 0x2 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x06c 0x35c 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x06c 0x35c 0x000 0x4 0x0 -#define MX6SL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x06c 0x35c 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x070 0x360 0x67c 0x0 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__AUD4_TXD 0x070 0x360 0x5e8 0x1 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x070 0x360 0x81c 0x2 0x1 -#define MX6SL_PAD_ECSPI1_SCLK__UART5_TX_DATA 0x070 0x360 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x070 0x360 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__SD2_RESET 0x070 0x360 0x000 0x4 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x070 0x360 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x070 0x360 0x820 0x6 0x0 -#define MX6SL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x074 0x364 0x68c 0x0 0x0 -#define MX6SL_PAD_ECSPI1_SS0__AUD4_RXD 0x074 0x364 0x5e4 0x1 0x0 -#define MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x074 0x364 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI1_SS0__UART5_RTS_B 0x074 0x364 0x818 0x2 0x1 -#define MX6SL_PAD_ECSPI1_SS0__EPDC_BDR1 0x074 0x364 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI1_SS0__SD2_CD_B 0x074 0x364 0x830 0x4 0x0 -#define MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x074 0x364 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x074 0x364 0x000 0x6 0x0 -#define MX6SL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x078 0x368 0x6a0 0x0 0x0 -#define MX6SL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x078 0x368 0x000 0x1 0x0 -#define MX6SL_PAD_ECSPI2_MISO__UART3_RTS_B 0x078 0x368 0x808 0x2 0x0 -#define MX6SL_PAD_ECSPI2_MISO__UART3_CTS_B 0x078 0x368 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI2_MISO__CSI_MCLK 0x078 0x368 0x000 0x3 0x0 -#define MX6SL_PAD_ECSPI2_MISO__SD1_WP 0x078 0x368 0x82c 0x4 0x0 -#define MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x078 0x368 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x078 0x368 0x824 0x6 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x07c 0x36c 0x6a4 0x0 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x07c 0x36c 0x000 0x1 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__UART3_TX_DATA 0x07c 0x36c 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__UART3_RX_DATA 0x07c 0x36c 0x80c 0x2 0x2 -#define MX6SL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x07c 0x36c 0x670 0x3 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x07c 0x36c 0x000 0x4 0x0 -#define MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x07c 0x36c 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x080 0x370 0x69c 0x0 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x080 0x370 0x7f4 0x1 0x1 -#define MX6SL_PAD_ECSPI2_SCLK__UART3_RX_DATA 0x080 0x370 0x80c 0x2 0x3 -#define MX6SL_PAD_ECSPI2_SCLK__UART3_TX_DATA 0x080 0x370 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x080 0x370 0x674 0x3 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__SD1_RESET 0x080 0x370 0x000 0x4 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x080 0x370 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x080 0x370 0x820 0x6 0x1 -#define MX6SL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x084 0x374 0x6a8 0x0 0x0 -#define MX6SL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x084 0x374 0x698 0x1 0x0 -#define MX6SL_PAD_ECSPI2_SS0__UART3_CTS_B 0x084 0x374 0x000 0x2 0x0 -#define MX6SL_PAD_ECSPI2_SS0__UART3_RTS_B 0x084 0x374 0x808 0x2 0x1 -#define MX6SL_PAD_ECSPI2_SS0__CSI_VSYNC 0x084 0x374 0x678 0x3 0x0 -#define MX6SL_PAD_ECSPI2_SS0__SD1_CD_B 0x084 0x374 0x828 0x4 0x0 -#define MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x084 0x374 0x000 0x5 0x0 -#define MX6SL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x084 0x374 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x088 0x378 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_BDR0__SD4_CLK 0x088 0x378 0x850 0x1 0x0 -#define MX6SL_PAD_EPDC_BDR0__UART3_RTS_B 0x088 0x378 0x808 0x2 0x2 -#define MX6SL_PAD_EPDC_BDR0__UART3_CTS_B 0x088 0x378 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_BDR0__EIM_ADDR26 0x088 0x378 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_BDR0__SPDC_RL 0x088 0x378 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_BDR0__GPIO2_IO05 0x088 0x378 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_BDR0__EPDC_SDCE7 0x088 0x378 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_BDR1__EPDC_BDR1 0x08c 0x37c 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_BDR1__SD4_CMD 0x08c 0x37c 0x858 0x1 0x0 -#define MX6SL_PAD_EPDC_BDR1__UART3_CTS_B 0x08c 0x37c 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_BDR1__UART3_RTS_B 0x08c 0x37c 0x808 0x2 0x3 -#define MX6SL_PAD_EPDC_BDR1__EIM_CRE 0x08c 0x37c 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_BDR1__SPDC_UD 0x08c 0x37c 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_BDR1__GPIO2_IO06 0x08c 0x37c 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_BDR1__EPDC_SDCE8 0x08c 0x37c 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x090 0x380 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D0__ECSPI4_MOSI 0x090 0x380 0x6d8 0x1 0x0 -#define MX6SL_PAD_EPDC_D0__LCD_DATA24 0x090 0x380 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D0__CSI_DATA00 0x090 0x380 0x630 0x3 0x0 -#define MX6SL_PAD_EPDC_D0__SPDC_DATA00 0x090 0x380 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D0__GPIO1_IO07 0x090 0x380 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x094 0x384 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D1__ECSPI4_MISO 0x094 0x384 0x6d4 0x1 0x0 -#define MX6SL_PAD_EPDC_D1__LCD_DATA25 0x094 0x384 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D1__CSI_DATA01 0x094 0x384 0x634 0x3 0x0 -#define MX6SL_PAD_EPDC_D1__SPDC_DATA01 0x094 0x384 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D1__GPIO1_IO08 0x094 0x384 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x098 0x388 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D10__ECSPI3_SS0 0x098 0x388 0x6c0 0x1 0x1 -#define MX6SL_PAD_EPDC_D10__EPDC_PWR_CTRL2 0x098 0x388 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D10__EIM_ADDR18 0x098 0x388 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D10__SPDC_DATA10 0x098 0x388 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D10__GPIO1_IO17 0x098 0x388 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D10__SD4_WP 0x098 0x388 0x87c 0x6 0x0 -#define MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x09c 0x38c 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D11__ECSPI3_SCLK 0x09c 0x38c 0x6b0 0x1 0x1 -#define MX6SL_PAD_EPDC_D11__EPDC_PWR_CTRL3 0x09c 0x38c 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D11__EIM_ADDR19 0x09c 0x38c 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D11__SPDC_DATA11 0x09c 0x38c 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D11__GPIO1_IO18 0x09c 0x38c 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D11__SD4_CD_B 0x09c 0x38c 0x854 0x6 0x0 -#define MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x0a0 0x390 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x0a0 0x390 0x804 0x1 0x0 -#define MX6SL_PAD_EPDC_D12__UART2_TX_DATA 0x0a0 0x390 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D12__EPDC_PWR_COM 0x0a0 0x390 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D12__EIM_ADDR20 0x0a0 0x390 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D12__SPDC_DATA12 0x0a0 0x390 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D12__GPIO1_IO19 0x0a0 0x390 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D12__ECSPI3_SS1 0x0a0 0x390 0x6c4 0x6 0x1 -#define MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x0a4 0x394 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x0a4 0x394 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D13__UART2_RX_DATA 0x0a4 0x394 0x804 0x1 0x1 -#define MX6SL_PAD_EPDC_D13__EPDC_PWR_IRQ 0x0a4 0x394 0x6e8 0x2 0x0 -#define MX6SL_PAD_EPDC_D13__EIM_ADDR21 0x0a4 0x394 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D13__SPDC_DATA13 0x0a4 0x394 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D13__GPIO1_IO20 0x0a4 0x394 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D13__ECSPI3_SS2 0x0a4 0x394 0x6c8 0x6 0x0 -#define MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x0a8 0x398 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x0a8 0x398 0x800 0x1 0x0 -#define MX6SL_PAD_EPDC_D14__UART2_CTS_B 0x0a8 0x398 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D14__EPDC_PWR_STAT 0x0a8 0x398 0x6ec 0x2 0x0 -#define MX6SL_PAD_EPDC_D14__EIM_ADDR22 0x0a8 0x398 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D14__SPDC_DATA14 0x0a8 0x398 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D14__GPIO1_IO21 0x0a8 0x398 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D14__ECSPI3_SS3 0x0a8 0x398 0x6cc 0x6 0x0 -#define MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x0ac 0x39c 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x0ac 0x39c 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D15__UART2_RTS_B 0x0ac 0x39c 0x800 0x1 0x1 -#define MX6SL_PAD_EPDC_D15__EPDC_PWR_WAKE 0x0ac 0x39c 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D15__EIM_ADDR23 0x0ac 0x39c 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D15__SPDC_DATA15 0x0ac 0x39c 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D15__GPIO1_IO22 0x0ac 0x39c 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D15__ECSPI3_RDY 0x0ac 0x39c 0x6b4 0x6 0x1 -#define MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x0b0 0x3a0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D2__ECSPI4_SS0 0x0b0 0x3a0 0x6dc 0x1 0x0 -#define MX6SL_PAD_EPDC_D2__LCD_DATA26 0x0b0 0x3a0 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D2__CSI_DATA02 0x0b0 0x3a0 0x638 0x3 0x0 -#define MX6SL_PAD_EPDC_D2__SPDC_DATA02 0x0b0 0x3a0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D2__GPIO1_IO09 0x0b0 0x3a0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x0b4 0x3a4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D3__ECSPI4_SCLK 0x0b4 0x3a4 0x6d0 0x1 0x0 -#define MX6SL_PAD_EPDC_D3__LCD_DATA27 0x0b4 0x3a4 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D3__CSI_DATA03 0x0b4 0x3a4 0x63c 0x3 0x0 -#define MX6SL_PAD_EPDC_D3__SPDC_DATA03 0x0b4 0x3a4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D3__GPIO1_IO10 0x0b4 0x3a4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x0b8 0x3a8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D4__ECSPI4_SS1 0x0b8 0x3a8 0x6e0 0x1 0x0 -#define MX6SL_PAD_EPDC_D4__LCD_DATA28 0x0b8 0x3a8 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D4__CSI_DATA04 0x0b8 0x3a8 0x640 0x3 0x0 -#define MX6SL_PAD_EPDC_D4__SPDC_DATA04 0x0b8 0x3a8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D4__GPIO1_IO11 0x0b8 0x3a8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x0bc 0x3ac 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D5__ECSPI4_SS2 0x0bc 0x3ac 0x6e4 0x1 0x0 -#define MX6SL_PAD_EPDC_D5__LCD_DATA29 0x0bc 0x3ac 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D5__CSI_DATA05 0x0bc 0x3ac 0x644 0x3 0x0 -#define MX6SL_PAD_EPDC_D5__SPDC_DATA05 0x0bc 0x3ac 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D5__GPIO1_IO12 0x0bc 0x3ac 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x0c0 0x3b0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D6__ECSPI4_SS3 0x0c0 0x3b0 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D6__LCD_DATA30 0x0c0 0x3b0 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D6__CSI_DATA06 0x0c0 0x3b0 0x648 0x3 0x0 -#define MX6SL_PAD_EPDC_D6__SPDC_DATA06 0x0c0 0x3b0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D6__GPIO1_IO13 0x0c0 0x3b0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x0c4 0x3b4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D7__ECSPI4_RDY 0x0c4 0x3b4 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_D7__LCD_DATA31 0x0c4 0x3b4 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D7__CSI_DATA07 0x0c4 0x3b4 0x64c 0x3 0x0 -#define MX6SL_PAD_EPDC_D7__SPDC_DATA07 0x0c4 0x3b4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D7__GPIO1_IO14 0x0c4 0x3b4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x0c8 0x3b8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D8__ECSPI3_MOSI 0x0c8 0x3b8 0x6bc 0x1 0x1 -#define MX6SL_PAD_EPDC_D8__EPDC_PWR_CTRL0 0x0c8 0x3b8 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D8__EIM_ADDR16 0x0c8 0x3b8 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D8__SPDC_DATA08 0x0c8 0x3b8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D8__GPIO1_IO15 0x0c8 0x3b8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D8__SD4_RESET 0x0c8 0x3b8 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x0cc 0x3bc 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_D9__ECSPI3_MISO 0x0cc 0x3bc 0x6b8 0x1 0x1 -#define MX6SL_PAD_EPDC_D9__EPDC_PWR_CTRL1 0x0cc 0x3bc 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_D9__EIM_ADDR17 0x0cc 0x3bc 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_D9__SPDC_DATA09 0x0cc 0x3bc 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_D9__GPIO1_IO16 0x0cc 0x3bc 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_D9__SD4_VSELECT 0x0cc 0x3bc 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0d0 0x3c0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x0d0 0x3c0 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKR 0x0d0 0x3c0 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x0d0 0x3c0 0x674 0x3 0x1 -#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKL 0x0d0 0x3c0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_GDCLK__GPIO1_IO31 0x0d0 0x3c0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_GDCLK__SD2_RESET 0x0d0 0x3c0 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x0d4 0x3c4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_GDOE__ECSPI2_SS3 0x0d4 0x3c4 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_GDOE__SPDC_YOER 0x0d4 0x3c4 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x0d4 0x3c4 0x670 0x3 0x1 -#define MX6SL_PAD_EPDC_GDOE__SPDC_YOEL 0x0d4 0x3c4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_GDOE__GPIO2_IO00 0x0d4 0x3c4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_GDOE__SD2_VSELECT 0x0d4 0x3c4 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x0d8 0x3c8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_GDRL__ECSPI2_RDY 0x0d8 0x3c8 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUR 0x0d8 0x3c8 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x0d8 0x3c8 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUL 0x0d8 0x3c8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_GDRL__GPIO2_IO01 0x0d8 0x3c8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_GDRL__SD2_WP 0x0d8 0x3c8 0x834 0x6 0x1 -#define MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x0dc 0x3cc 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_GDSP__PWM4_OUT 0x0dc 0x3cc 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODR 0x0dc 0x3cc 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x0dc 0x3cc 0x678 0x3 0x1 -#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODL 0x0dc 0x3cc 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_GDSP__GPIO2_IO02 0x0dc 0x3cc 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_GDSP__SD2_CD_B 0x0dc 0x3cc 0x830 0x6 0x1 -#define MX6SL_PAD_EPDC_PWRCOM__EPDC_PWR_COM 0x0e0 0x3d0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__SD4_DATA0 0x0e0 0x3d0 0x85c 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__LCD_DATA20 0x0e0 0x3d0 0x7c8 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__EIM_BCLK 0x0e0 0x3d0 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x0e0 0x3d0 0x5dc 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__GPIO2_IO11 0x0e0 0x3d0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCOM__SD3_RESET 0x0e0 0x3d0 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__EPDC_PWR_CTRL0 0x0e4 0x3d4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__AUD5_RXC 0x0e4 0x3d4 0x604 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__LCD_DATA16 0x0e4 0x3d4 0x7b8 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__EIM_RW 0x0e4 0x3d4 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__SPDC_YCKL 0x0e4 0x3d4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x0e4 0x3d4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL0__SD4_RESET 0x0e4 0x3d4 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__EPDC_PWR_CTRL1 0x0e8 0x3d8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__AUD5_TXFS 0x0e8 0x3d8 0x610 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__LCD_DATA17 0x0e8 0x3d8 0x7bc 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__EIM_OE_B 0x0e8 0x3d8 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__SPDC_YOEL 0x0e8 0x3d8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x0e8 0x3d8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL1__SD4_VSELECT 0x0e8 0x3d8 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__EPDC_PWR_CTRL2 0x0ec 0x3dc 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__AUD5_TXD 0x0ec 0x3dc 0x600 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__LCD_DATA18 0x0ec 0x3dc 0x7c0 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__EIM_CS0_B 0x0ec 0x3dc 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__SPDC_YDIOUL 0x0ec 0x3dc 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x0ec 0x3dc 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL2__SD4_WP 0x0ec 0x3dc 0x87c 0x6 0x1 -#define MX6SL_PAD_EPDC_PWRCTRL3__EPDC_PWR_CTRL3 0x0f0 0x3e0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__AUD5_TXC 0x0f0 0x3e0 0x60c 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__LCD_DATA19 0x0f0 0x3e0 0x7c4 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__EIM_CS1_B 0x0f0 0x3e0 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__SPDC_YDIODL 0x0f0 0x3e0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x0f0 0x3e0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRCTRL3__SD4_CD_B 0x0f0 0x3e0 0x854 0x6 0x1 -#define MX6SL_PAD_EPDC_PWRINT__EPDC_PWR_IRQ 0x0f4 0x3e4 0x6e8 0x0 0x1 -#define MX6SL_PAD_EPDC_PWRINT__SD4_DATA1 0x0f4 0x3e4 0x860 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRINT__LCD_DATA21 0x0f4 0x3e4 0x7cc 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRINT__EIM_ACLK_FREERUN 0x0f4 0x3e4 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRINT__USB_OTG2_ID 0x0f4 0x3e4 0x5e0 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRINT__GPIO2_IO12 0x0f4 0x3e4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRINT__SD3_VSELECT 0x0f4 0x3e4 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__EPDC_PWR_STAT 0x0f8 0x3e8 0x6ec 0x0 0x1 -#define MX6SL_PAD_EPDC_PWRSTAT__SD4_DATA2 0x0f8 0x3e8 0x864 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__LCD_DATA22 0x0f8 0x3e8 0x7d0 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__EIM_WAIT_B 0x0f8 0x3e8 0x884 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__ARM_EVENTI 0x0f8 0x3e8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x0f8 0x3e8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRSTAT__SD3_WP 0x0f8 0x3e8 0x84c 0x6 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__EPDC_PWR_WAKE 0x0fc 0x3ec 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__SD4_DATA3 0x0fc 0x3ec 0x868 0x1 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__LCD_DATA23 0x0fc 0x3ec 0x7d4 0x2 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__EIM_DTACK_B 0x0fc 0x3ec 0x880 0x3 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__ARM_EVENTO 0x0fc 0x3ec 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x0fc 0x3ec 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_PWRWAKEUP__SD3_CD_B 0x0fc 0x3ec 0x838 0x6 0x0 -#define MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100 0x3f0 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x100 0x3f0 0x6ac 0x1 0x0 -#define MX6SL_PAD_EPDC_SDCE0__PWM3_OUT 0x100 0x3f0 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCE0__EIM_CS2_B 0x100 0x3f0 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCE0__SPDC_YCKR 0x100 0x3f0 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCE0__GPIO1_IO27 0x100 0x3f0 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x104 0x3f4 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCE1__WDOG2_B 0x104 0x3f4 0x000 0x1 0x0 -#define MX6SL_PAD_EPDC_SDCE1__PWM4_OUT 0x104 0x3f4 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCE1__EIM_LBA_B 0x104 0x3f4 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCE1__SPDC_YOER 0x104 0x3f4 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCE1__GPIO1_IO28 0x104 0x3f4 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x108 0x3f8 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x108 0x3f8 0x72c 0x1 0x1 -#define MX6SL_PAD_EPDC_SDCE2__PWM1_OUT 0x108 0x3f8 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCE2__EIM_EB0_B 0x108 0x3f8 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCE2__SPDC_YDIOUR 0x108 0x3f8 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x108 0x3f8 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x10c 0x3fc 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x10c 0x3fc 0x730 0x1 0x1 -#define MX6SL_PAD_EPDC_SDCE3__PWM2_OUT 0x10c 0x3fc 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCE3__EIM_EB1_B 0x10c 0x3fc 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCE3__SPDC_YDIODR 0x10c 0x3fc 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCE3__GPIO1_IO30 0x10c 0x3fc 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x110 0x400 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x110 0x400 0x6a4 0x1 0x1 -#define MX6SL_PAD_EPDC_SDCLK__I2C2_SCL 0x110 0x400 0x724 0x2 0x0 -#define MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110 0x400 0x650 0x3 0x0 -#define MX6SL_PAD_EPDC_SDCLK__SPDC_CL 0x110 0x400 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDCLK__GPIO1_IO23 0x110 0x400 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x114 0x404 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDLE__ECSPI2_MISO 0x114 0x404 0x6a0 0x1 0x1 -#define MX6SL_PAD_EPDC_SDLE__I2C2_SDA 0x114 0x404 0x728 0x2 0x0 -#define MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x114 0x404 0x654 0x3 0x0 -#define MX6SL_PAD_EPDC_SDLE__SPDC_LD 0x114 0x404 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDLE__GPIO1_IO24 0x114 0x404 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x118 0x408 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDOE__ECSPI2_SS0 0x118 0x408 0x6a8 0x1 0x1 -#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOR 0x118 0x408 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDOE__CSI_DATA10 0x118 0x408 0x658 0x3 0x0 -#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOL 0x118 0x408 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x118 0x408 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x11c 0x40c 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x11c 0x40c 0x69c 0x1 0x1 -#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x11c 0x40c 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_SDSHR__CSI_DATA11 0x11c 0x40c 0x65c 0x3 0x0 -#define MX6SL_PAD_EPDC_SDSHR__SPDC_XDIOR 0x11c 0x40c 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x11c 0x40c 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x120 0x410 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_VCOM0__AUD5_RXFS 0x120 0x410 0x608 0x1 0x0 -#define MX6SL_PAD_EPDC_VCOM0__UART3_RX_DATA 0x120 0x410 0x80c 0x2 0x4 -#define MX6SL_PAD_EPDC_VCOM0__UART3_TX_DATA 0x120 0x410 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_VCOM0__EIM_ADDR24 0x120 0x410 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_VCOM0__SPDC_VCOM0 0x120 0x410 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x120 0x410 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x120 0x410 0x000 0x6 0x0 -#define MX6SL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x124 0x414 0x000 0x0 0x0 -#define MX6SL_PAD_EPDC_VCOM1__AUD5_RXD 0x124 0x414 0x5fc 0x1 0x0 -#define MX6SL_PAD_EPDC_VCOM1__UART3_TX_DATA 0x124 0x414 0x000 0x2 0x0 -#define MX6SL_PAD_EPDC_VCOM1__UART3_RX_DATA 0x124 0x414 0x80c 0x2 0x5 -#define MX6SL_PAD_EPDC_VCOM1__EIM_ADDR25 0x124 0x414 0x000 0x3 0x0 -#define MX6SL_PAD_EPDC_VCOM1__SPDC_VCOM1 0x124 0x414 0x000 0x4 0x0 -#define MX6SL_PAD_EPDC_VCOM1__GPIO2_IO04 0x124 0x414 0x000 0x5 0x0 -#define MX6SL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x124 0x414 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x128 0x418 0x704 0x0 0x1 -#define MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x128 0x418 0x860 0x1 0x1 -#define MX6SL_PAD_FEC_CRS_DV__AUD6_TXC 0x128 0x418 0x624 0x2 0x0 -#define MX6SL_PAD_FEC_CRS_DV__ECSPI4_MISO 0x128 0x418 0x6d4 0x3 0x1 -#define MX6SL_PAD_FEC_CRS_DV__GPT_COMPARE2 0x128 0x418 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x128 0x418 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_CRS_DV__ARM_TRACE31 0x128 0x418 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_MDC__FEC_MDC 0x12c 0x41c 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_MDC__SD4_DATA4 0x12c 0x41c 0x86c 0x1 0x0 -#define MX6SL_PAD_FEC_MDC__AUDIO_CLK_OUT 0x12c 0x41c 0x000 0x2 0x0 -#define MX6SL_PAD_FEC_MDC__SD1_RESET 0x12c 0x41c 0x000 0x3 0x0 -#define MX6SL_PAD_FEC_MDC__SD3_RESET 0x12c 0x41c 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x12c 0x41c 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_MDC__ARM_TRACE29 0x12c 0x41c 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x130 0x420 0x6f4 0x0 0x1 -#define MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130 0x420 0x850 0x1 0x1 -#define MX6SL_PAD_FEC_MDIO__AUD6_RXFS 0x130 0x420 0x620 0x2 0x0 -#define MX6SL_PAD_FEC_MDIO__ECSPI4_SS0 0x130 0x420 0x6dc 0x3 0x1 -#define MX6SL_PAD_FEC_MDIO__GPT_CAPTURE1 0x130 0x420 0x710 0x4 0x0 -#define MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x130 0x420 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_MDIO__ARM_TRACE26 0x130 0x420 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x134 0x424 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_REF_CLK__SD4_RESET 0x134 0x424 0x000 0x1 0x0 -#define MX6SL_PAD_FEC_REF_CLK__WDOG1_B 0x134 0x424 0x000 0x2 0x0 -#define MX6SL_PAD_FEC_REF_CLK__PWM4_OUT 0x134 0x424 0x000 0x3 0x0 -#define MX6SL_PAD_FEC_REF_CLK__CCM_PMIC_READY 0x134 0x424 0x62c 0x4 0x0 -#define MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x134 0x424 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_REF_CLK__SPDIF_EXT_CLK 0x134 0x424 0x7f4 0x6 0x2 -#define MX6SL_PAD_FEC_RX_ER__FEC_RX_ER 0x138 0x428 0x708 0x0 0x1 -#define MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x138 0x428 0x85c 0x1 0x1 -#define MX6SL_PAD_FEC_RX_ER__AUD6_RXD 0x138 0x428 0x614 0x2 0x0 -#define MX6SL_PAD_FEC_RX_ER__ECSPI4_MOSI 0x138 0x428 0x6d8 0x3 0x1 -#define MX6SL_PAD_FEC_RX_ER__GPT_COMPARE1 0x138 0x428 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x138 0x428 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_RX_ER__ARM_TRACE25 0x138 0x428 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x13c 0x42c 0x6f8 0x0 0x0 -#define MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x13c 0x42c 0x870 0x1 0x0 -#define MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x13c 0x42c 0x5dc 0x2 0x1 -#define MX6SL_PAD_FEC_RXD0__SD1_VSELECT 0x13c 0x42c 0x000 0x3 0x0 -#define MX6SL_PAD_FEC_RXD0__SD3_VSELECT 0x13c 0x42c 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x13c 0x42c 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_RXD0__ARM_TRACE24 0x13c 0x42c 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x140 0x430 0x6fc 0x0 0x1 -#define MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x140 0x430 0x864 0x1 0x1 -#define MX6SL_PAD_FEC_RXD1__AUD6_TXFS 0x140 0x430 0x628 0x2 0x0 -#define MX6SL_PAD_FEC_RXD1__ECSPI4_SS1 0x140 0x430 0x6e0 0x3 0x1 -#define MX6SL_PAD_FEC_RXD1__GPT_COMPARE3 0x140 0x430 0x000 0x4 0x0 -#define MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x140 0x430 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_RXD1__FEC_COL 0x140 0x430 0x6f0 0x6 0x0 -#define MX6SL_PAD_FEC_TX_CLK__FEC_TX_CLK 0x144 0x434 0x70c 0x0 0x1 -#define MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x144 0x434 0x858 0x1 0x1 -#define MX6SL_PAD_FEC_TX_CLK__AUD6_RXC 0x144 0x434 0x61c 0x2 0x0 -#define MX6SL_PAD_FEC_TX_CLK__ECSPI4_SCLK 0x144 0x434 0x6d0 0x3 0x1 -#define MX6SL_PAD_FEC_TX_CLK__GPT_CAPTURE2 0x144 0x434 0x714 0x4 0x0 -#define MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x144 0x434 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_TX_CLK__ARM_TRACE27 0x144 0x434 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x148 0x438 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x148 0x438 0x874 0x1 0x0 -#define MX6SL_PAD_FEC_TX_EN__SPDIF_IN 0x148 0x438 0x7f0 0x2 0x0 -#define MX6SL_PAD_FEC_TX_EN__SD1_WP 0x148 0x438 0x82c 0x3 0x1 -#define MX6SL_PAD_FEC_TX_EN__SD3_WP 0x148 0x438 0x84c 0x4 0x1 -#define MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x148 0x438 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_TX_EN__ARM_TRACE28 0x148 0x438 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x14c 0x43c 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x14c 0x43c 0x868 0x1 0x1 -#define MX6SL_PAD_FEC_TXD0__AUD6_TXD 0x14c 0x43c 0x618 0x2 0x0 -#define MX6SL_PAD_FEC_TXD0__ECSPI4_SS2 0x14c 0x43c 0x6e4 0x3 0x1 -#define MX6SL_PAD_FEC_TXD0__GPT_CLKIN 0x14c 0x43c 0x718 0x4 0x0 -#define MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x14c 0x43c 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_TXD0__ARM_TRACE30 0x14c 0x43c 0x000 0x6 0x0 -#define MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x150 0x440 0x000 0x0 0x0 -#define MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x150 0x440 0x878 0x1 0x0 -#define MX6SL_PAD_FEC_TXD1__SPDIF_OUT 0x150 0x440 0x000 0x2 0x0 -#define MX6SL_PAD_FEC_TXD1__SD1_CD_B 0x150 0x440 0x828 0x3 0x1 -#define MX6SL_PAD_FEC_TXD1__SD3_CD_B 0x150 0x440 0x838 0x4 0x1 -#define MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x150 0x440 0x000 0x5 0x0 -#define MX6SL_PAD_FEC_TXD1__FEC_RX_CLK 0x150 0x440 0x700 0x6 0x0 -#define MX6SL_PAD_HSIC_DAT__USB_H_DATA 0x154 0x444 0x000 0x0 0x0 -#define MX6SL_PAD_HSIC_DAT__I2C1_SCL 0x154 0x444 0x71c 0x1 0x1 -#define MX6SL_PAD_HSIC_DAT__PWM1_OUT 0x154 0x444 0x000 0x2 0x0 -#define MX6SL_PAD_HSIC_DAT__XTALOSC_REF_CLK_24M 0x154 0x444 0x000 0x3 0x0 -#define MX6SL_PAD_HSIC_DAT__GPIO3_IO19 0x154 0x444 0x000 0x5 0x0 -#define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE 0x158 0x448 0x000 0x0 0x0 -#define MX6SL_PAD_HSIC_STROBE__I2C1_SDA 0x158 0x448 0x720 0x1 0x1 -#define MX6SL_PAD_HSIC_STROBE__PWM2_OUT 0x158 0x448 0x000 0x2 0x0 -#define MX6SL_PAD_HSIC_STROBE__XTALOSC_REF_CLK_32K 0x158 0x448 0x000 0x3 0x0 -#define MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x158 0x448 0x000 0x5 0x0 -#define MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x15c 0x44c 0x71c 0x0 0x2 -#define MX6SL_PAD_I2C1_SCL__UART1_RTS_B 0x15c 0x44c 0x7f8 0x1 0x0 -#define MX6SL_PAD_I2C1_SCL__UART1_CTS_B 0x15c 0x44c 0x000 0x1 0x0 -#define MX6SL_PAD_I2C1_SCL__ECSPI3_SS2 0x15c 0x44c 0x6c8 0x2 0x1 -#define MX6SL_PAD_I2C1_SCL__FEC_RX_DATA0 0x15c 0x44c 0x6f8 0x3 0x1 -#define MX6SL_PAD_I2C1_SCL__SD3_RESET 0x15c 0x44c 0x000 0x4 0x0 -#define MX6SL_PAD_I2C1_SCL__GPIO3_IO12 0x15c 0x44c 0x000 0x5 0x0 -#define MX6SL_PAD_I2C1_SCL__ECSPI1_SS1 0x15c 0x44c 0x690 0x6 0x0 -#define MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x160 0x450 0x720 0x0 0x2 -#define MX6SL_PAD_I2C1_SDA__UART1_CTS_B 0x160 0x450 0x000 0x1 0x0 -#define MX6SL_PAD_I2C1_SDA__UART1_RTS_B 0x160 0x450 0x7f8 0x1 0x1 -#define MX6SL_PAD_I2C1_SDA__ECSPI3_SS3 0x160 0x450 0x6cc 0x2 0x1 -#define MX6SL_PAD_I2C1_SDA__FEC_TX_EN 0x160 0x450 0x000 0x3 0x0 -#define MX6SL_PAD_I2C1_SDA__SD3_VSELECT 0x160 0x450 0x000 0x4 0x0 -#define MX6SL_PAD_I2C1_SDA__GPIO3_IO13 0x160 0x450 0x000 0x5 0x0 -#define MX6SL_PAD_I2C1_SDA__ECSPI1_SS2 0x160 0x450 0x694 0x6 0x0 -#define MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x164 0x454 0x724 0x0 0x1 -#define MX6SL_PAD_I2C2_SCL__AUD4_RXFS 0x164 0x454 0x5f0 0x1 0x0 -#define MX6SL_PAD_I2C2_SCL__SPDIF_IN 0x164 0x454 0x7f0 0x2 0x1 -#define MX6SL_PAD_I2C2_SCL__FEC_TX_DATA1 0x164 0x454 0x000 0x3 0x0 -#define MX6SL_PAD_I2C2_SCL__SD3_WP 0x164 0x454 0x84c 0x4 0x2 -#define MX6SL_PAD_I2C2_SCL__GPIO3_IO14 0x164 0x454 0x000 0x5 0x0 -#define MX6SL_PAD_I2C2_SCL__ECSPI1_RDY 0x164 0x454 0x680 0x6 0x0 -#define MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x168 0x458 0x728 0x0 0x1 -#define MX6SL_PAD_I2C2_SDA__AUD4_RXC 0x168 0x458 0x5ec 0x1 0x0 -#define MX6SL_PAD_I2C2_SDA__SPDIF_OUT 0x168 0x458 0x000 0x2 0x0 -#define MX6SL_PAD_I2C2_SDA__FEC_REF_OUT 0x168 0x458 0x000 0x3 0x0 -#define MX6SL_PAD_I2C2_SDA__SD3_CD_B 0x168 0x458 0x838 0x4 0x2 -#define MX6SL_PAD_I2C2_SDA__GPIO3_IO15 0x168 0x458 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL0__KEY_COL0 0x16c 0x474 0x734 0x0 0x0 -#define MX6SL_PAD_KEY_COL0__I2C2_SCL 0x16c 0x474 0x724 0x1 0x2 -#define MX6SL_PAD_KEY_COL0__LCD_DATA00 0x16c 0x474 0x778 0x2 0x0 -#define MX6SL_PAD_KEY_COL0__EIM_AD00 0x16c 0x474 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL0__SD1_CD_B 0x16c 0x474 0x828 0x4 0x2 -#define MX6SL_PAD_KEY_COL0__GPIO3_IO24 0x16c 0x474 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL1__KEY_COL1 0x170 0x478 0x738 0x0 0x0 -#define MX6SL_PAD_KEY_COL1__ECSPI4_MOSI 0x170 0x478 0x6d8 0x1 0x2 -#define MX6SL_PAD_KEY_COL1__LCD_DATA02 0x170 0x478 0x780 0x2 0x0 -#define MX6SL_PAD_KEY_COL1__EIM_AD02 0x170 0x478 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL1__SD3_DATA4 0x170 0x478 0x83c 0x4 0x0 -#define MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x170 0x478 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL2__KEY_COL2 0x174 0x47c 0x73c 0x0 0x0 -#define MX6SL_PAD_KEY_COL2__ECSPI4_SS0 0x174 0x47c 0x6dc 0x1 0x2 -#define MX6SL_PAD_KEY_COL2__LCD_DATA04 0x174 0x47c 0x788 0x2 0x0 -#define MX6SL_PAD_KEY_COL2__EIM_AD04 0x174 0x47c 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL2__SD3_DATA6 0x174 0x47c 0x844 0x4 0x0 -#define MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x174 0x47c 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL3__KEY_COL3 0x178 0x480 0x740 0x0 0x0 -#define MX6SL_PAD_KEY_COL3__AUD6_RXFS 0x178 0x480 0x620 0x1 0x1 -#define MX6SL_PAD_KEY_COL3__LCD_DATA06 0x178 0x480 0x790 0x2 0x0 -#define MX6SL_PAD_KEY_COL3__EIM_AD06 0x178 0x480 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL3__SD4_DATA6 0x178 0x480 0x874 0x4 0x1 -#define MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x178 0x480 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL3__SD1_RESET 0x178 0x480 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_COL4__KEY_COL4 0x17c 0x484 0x744 0x0 0x0 -#define MX6SL_PAD_KEY_COL4__AUD6_RXD 0x17c 0x484 0x614 0x1 0x1 -#define MX6SL_PAD_KEY_COL4__LCD_DATA08 0x17c 0x484 0x798 0x2 0x0 -#define MX6SL_PAD_KEY_COL4__EIM_AD08 0x17c 0x484 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL4__SD4_CLK 0x17c 0x484 0x850 0x4 0x2 -#define MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x17c 0x484 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL4__USB_OTG1_PWR 0x17c 0x484 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_COL5__KEY_COL5 0x180 0x488 0x748 0x0 0x0 -#define MX6SL_PAD_KEY_COL5__AUD6_TXFS 0x180 0x488 0x628 0x1 0x1 -#define MX6SL_PAD_KEY_COL5__LCD_DATA10 0x180 0x488 0x7a0 0x2 0x0 -#define MX6SL_PAD_KEY_COL5__EIM_AD10 0x180 0x488 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL5__SD4_DATA0 0x180 0x488 0x85c 0x4 0x2 -#define MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x180 0x488 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL5__USB_OTG2_PWR 0x180 0x488 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_COL6__KEY_COL6 0x184 0x48c 0x74c 0x0 0x0 -#define MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x184 0x48c 0x814 0x1 0x2 -#define MX6SL_PAD_KEY_COL6__UART4_TX_DATA 0x184 0x48c 0x000 0x1 0x0 -#define MX6SL_PAD_KEY_COL6__LCD_DATA12 0x184 0x48c 0x7a8 0x2 0x0 -#define MX6SL_PAD_KEY_COL6__EIM_AD12 0x184 0x48c 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL6__SD4_DATA2 0x184 0x48c 0x864 0x4 0x2 -#define MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x184 0x48c 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL6__SD3_RESET 0x184 0x48c 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_COL7__KEY_COL7 0x188 0x490 0x750 0x0 0x0 -#define MX6SL_PAD_KEY_COL7__UART4_RTS_B 0x188 0x490 0x810 0x1 0x2 -#define MX6SL_PAD_KEY_COL7__UART4_CTS_B 0x188 0x490 0x000 0x1 0x0 -#define MX6SL_PAD_KEY_COL7__LCD_DATA14 0x188 0x490 0x7b0 0x2 0x0 -#define MX6SL_PAD_KEY_COL7__EIM_AD14 0x188 0x490 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_COL7__SD4_DATA4 0x188 0x490 0x86c 0x4 0x1 -#define MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x188 0x490 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_COL7__SD1_WP 0x188 0x490 0x82c 0x6 0x2 -#define MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x18c 0x494 0x754 0x0 0x0 -#define MX6SL_PAD_KEY_ROW0__I2C2_SDA 0x18c 0x494 0x728 0x1 0x2 -#define MX6SL_PAD_KEY_ROW0__LCD_DATA01 0x18c 0x494 0x77c 0x2 0x0 -#define MX6SL_PAD_KEY_ROW0__EIM_AD01 0x18c 0x494 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW0__SD1_WP 0x18c 0x494 0x82c 0x4 0x3 -#define MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x18c 0x494 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x190 0x498 0x758 0x0 0x0 -#define MX6SL_PAD_KEY_ROW1__ECSPI4_MISO 0x190 0x498 0x6d4 0x1 0x2 -#define MX6SL_PAD_KEY_ROW1__LCD_DATA03 0x190 0x498 0x784 0x2 0x0 -#define MX6SL_PAD_KEY_ROW1__EIM_AD03 0x190 0x498 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW1__SD3_DATA5 0x190 0x498 0x840 0x4 0x0 -#define MX6SL_PAD_KEY_ROW1__GPIO3_IO27 0x190 0x498 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x194 0x49c 0x75c 0x0 0x0 -#define MX6SL_PAD_KEY_ROW2__ECSPI4_SCLK 0x194 0x49c 0x6d0 0x1 0x2 -#define MX6SL_PAD_KEY_ROW2__LCD_DATA05 0x194 0x49c 0x78c 0x2 0x0 -#define MX6SL_PAD_KEY_ROW2__EIM_AD05 0x194 0x49c 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW2__SD3_DATA7 0x194 0x49c 0x848 0x4 0x0 -#define MX6SL_PAD_KEY_ROW2__GPIO3_IO29 0x194 0x49c 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW3__KEY_ROW3 0x198 0x4a0 0x760 0x0 0x0 -#define MX6SL_PAD_KEY_ROW3__AUD6_RXC 0x198 0x4a0 0x61c 0x1 0x1 -#define MX6SL_PAD_KEY_ROW3__LCD_DATA07 0x198 0x4a0 0x794 0x2 0x0 -#define MX6SL_PAD_KEY_ROW3__EIM_AD07 0x198 0x4a0 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW3__SD4_DATA7 0x198 0x4a0 0x878 0x4 0x1 -#define MX6SL_PAD_KEY_ROW3__GPIO3_IO31 0x198 0x4a0 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW3__SD1_VSELECT 0x198 0x4a0 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_ROW4__KEY_ROW4 0x19c 0x4a4 0x764 0x0 0x0 -#define MX6SL_PAD_KEY_ROW4__AUD6_TXC 0x19c 0x4a4 0x624 0x1 0x1 -#define MX6SL_PAD_KEY_ROW4__LCD_DATA09 0x19c 0x4a4 0x79c 0x2 0x0 -#define MX6SL_PAD_KEY_ROW4__EIM_AD09 0x19c 0x4a4 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW4__SD4_CMD 0x19c 0x4a4 0x858 0x4 0x2 -#define MX6SL_PAD_KEY_ROW4__GPIO4_IO01 0x19c 0x4a4 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW4__USB_OTG1_OC 0x19c 0x4a4 0x824 0x6 0x1 -#define MX6SL_PAD_KEY_ROW5__KEY_ROW5 0x1a0 0x4a8 0x768 0x0 0x0 -#define MX6SL_PAD_KEY_ROW5__AUD6_TXD 0x1a0 0x4a8 0x618 0x1 0x1 -#define MX6SL_PAD_KEY_ROW5__LCD_DATA11 0x1a0 0x4a8 0x7a4 0x2 0x0 -#define MX6SL_PAD_KEY_ROW5__EIM_AD11 0x1a0 0x4a8 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW5__SD4_DATA1 0x1a0 0x4a8 0x860 0x4 0x2 -#define MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x1a0 0x4a8 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x1a0 0x4a8 0x820 0x6 0x2 -#define MX6SL_PAD_KEY_ROW6__KEY_ROW6 0x1a4 0x4ac 0x76c 0x0 0x0 -#define MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1a4 0x4ac 0x000 0x1 0x0 -#define MX6SL_PAD_KEY_ROW6__UART4_RX_DATA 0x1a4 0x4ac 0x814 0x1 0x3 -#define MX6SL_PAD_KEY_ROW6__LCD_DATA13 0x1a4 0x4ac 0x7ac 0x2 0x0 -#define MX6SL_PAD_KEY_ROW6__EIM_AD13 0x1a4 0x4ac 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW6__SD4_DATA3 0x1a4 0x4ac 0x868 0x4 0x2 -#define MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x1a4 0x4ac 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW6__SD3_VSELECT 0x1a4 0x4ac 0x000 0x6 0x0 -#define MX6SL_PAD_KEY_ROW7__KEY_ROW7 0x1a8 0x4b0 0x770 0x0 0x0 -#define MX6SL_PAD_KEY_ROW7__UART4_CTS_B 0x1a8 0x4b0 0x000 0x1 0x0 -#define MX6SL_PAD_KEY_ROW7__UART4_RTS_B 0x1a8 0x4b0 0x810 0x1 0x3 -#define MX6SL_PAD_KEY_ROW7__LCD_DATA15 0x1a8 0x4b0 0x7b4 0x2 0x0 -#define MX6SL_PAD_KEY_ROW7__EIM_AD15 0x1a8 0x4b0 0x000 0x3 0x0 -#define MX6SL_PAD_KEY_ROW7__SD4_DATA5 0x1a8 0x4b0 0x870 0x4 0x1 -#define MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x1a8 0x4b0 0x000 0x5 0x0 -#define MX6SL_PAD_KEY_ROW7__SD1_CD_B 0x1a8 0x4b0 0x828 0x6 0x3 -#define MX6SL_PAD_LCD_CLK__LCD_CLK 0x1ac 0x4b4 0x000 0x0 0x0 -#define MX6SL_PAD_LCD_CLK__SD4_DATA4 0x1ac 0x4b4 0x86c 0x1 0x2 -#define MX6SL_PAD_LCD_CLK__LCD_WR_RWN 0x1ac 0x4b4 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_CLK__EIM_RW 0x1ac 0x4b4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_CLK__PWM4_OUT 0x1ac 0x4b4 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x1ac 0x4b4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0 0x4b8 0x778 0x0 0x1 -#define MX6SL_PAD_LCD_DAT0__ECSPI1_MOSI 0x1b0 0x4b8 0x688 0x1 0x1 -#define MX6SL_PAD_LCD_DAT0__USB_OTG2_ID 0x1b0 0x4b8 0x5e0 0x2 0x1 -#define MX6SL_PAD_LCD_DAT0__PWM1_OUT 0x1b0 0x4b8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT0__UART5_DTR_B 0x1b0 0x4b8 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x1b0 0x4b8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT0__ARM_TRACE00 0x1b0 0x4b8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT0__SRC_BOOT_CFG00 0x1b0 0x4b8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b4 0x4bc 0x77c 0x0 0x1 -#define MX6SL_PAD_LCD_DAT1__ECSPI1_MISO 0x1b4 0x4bc 0x684 0x1 0x1 -#define MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x1b4 0x4bc 0x5dc 0x2 0x2 -#define MX6SL_PAD_LCD_DAT1__PWM2_OUT 0x1b4 0x4bc 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT1__AUD4_RXFS 0x1b4 0x4bc 0x5f0 0x4 0x1 -#define MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x1b4 0x4bc 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT1__ARM_TRACE01 0x1b4 0x4bc 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT1__SRC_BOOT_CFG01 0x1b4 0x4bc 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b8 0x4c0 0x7a0 0x0 0x1 -#define MX6SL_PAD_LCD_DAT10__KEY_COL1 0x1b8 0x4c0 0x738 0x1 0x1 -#define MX6SL_PAD_LCD_DAT10__CSI_DATA07 0x1b8 0x4c0 0x64c 0x2 0x1 -#define MX6SL_PAD_LCD_DAT10__EIM_DATA04 0x1b8 0x4c0 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT10__ECSPI2_MISO 0x1b8 0x4c0 0x6a0 0x4 0x2 -#define MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x1b8 0x4c0 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT10__ARM_TRACE10 0x1b8 0x4c0 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT10__SRC_BOOT_CFG10 0x1b8 0x4c0 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1bc 0x4c4 0x7a4 0x0 0x1 -#define MX6SL_PAD_LCD_DAT11__KEY_ROW1 0x1bc 0x4c4 0x758 0x1 0x1 -#define MX6SL_PAD_LCD_DAT11__CSI_DATA06 0x1bc 0x4c4 0x648 0x2 0x1 -#define MX6SL_PAD_LCD_DAT11__EIM_DATA05 0x1bc 0x4c4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT11__ECSPI2_SS1 0x1bc 0x4c4 0x6ac 0x4 0x1 -#define MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x1bc 0x4c4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT11__ARM_TRACE11 0x1bc 0x4c4 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT11__SRC_BOOT_CFG11 0x1bc 0x4c4 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1c0 0x4c8 0x7a8 0x0 0x1 -#define MX6SL_PAD_LCD_DAT12__KEY_COL2 0x1c0 0x4c8 0x73c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT12__CSI_DATA05 0x1c0 0x4c8 0x644 0x2 0x1 -#define MX6SL_PAD_LCD_DAT12__EIM_DATA06 0x1c0 0x4c8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT12__UART5_RTS_B 0x1c0 0x4c8 0x818 0x4 0x2 -#define MX6SL_PAD_LCD_DAT12__UART5_CTS_B 0x1c0 0x4c8 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x1c0 0x4c8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT12__ARM_TRACE12 0x1c0 0x4c8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT12__SRC_BOOT_CFG12 0x1c0 0x4c8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1c4 0x4cc 0x7ac 0x0 0x1 -#define MX6SL_PAD_LCD_DAT13__KEY_ROW2 0x1c4 0x4cc 0x75c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT13__CSI_DATA04 0x1c4 0x4cc 0x640 0x2 0x1 -#define MX6SL_PAD_LCD_DAT13__EIM_DATA07 0x1c4 0x4cc 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT13__UART5_CTS_B 0x1c4 0x4cc 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT13__UART5_RTS_B 0x1c4 0x4cc 0x818 0x4 0x3 -#define MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x1c4 0x4cc 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT13__ARM_TRACE13 0x1c4 0x4cc 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT13__SRC_BOOT_CFG13 0x1c4 0x4cc 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1c8 0x4d0 0x7b0 0x0 0x1 -#define MX6SL_PAD_LCD_DAT14__KEY_COL3 0x1c8 0x4d0 0x740 0x1 0x1 -#define MX6SL_PAD_LCD_DAT14__CSI_DATA03 0x1c8 0x4d0 0x63c 0x2 0x1 -#define MX6SL_PAD_LCD_DAT14__EIM_DATA08 0x1c8 0x4d0 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT14__UART5_RX_DATA 0x1c8 0x4d0 0x81c 0x4 0x2 -#define MX6SL_PAD_LCD_DAT14__UART5_TX_DATA 0x1c8 0x4d0 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x1c8 0x4d0 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT14__ARM_TRACE14 0x1c8 0x4d0 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT14__SRC_BOOT_CFG14 0x1c8 0x4d0 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1cc 0x4d4 0x7b4 0x0 0x1 -#define MX6SL_PAD_LCD_DAT15__KEY_ROW3 0x1cc 0x4d4 0x760 0x1 0x1 -#define MX6SL_PAD_LCD_DAT15__CSI_DATA02 0x1cc 0x4d4 0x638 0x2 0x1 -#define MX6SL_PAD_LCD_DAT15__EIM_DATA09 0x1cc 0x4d4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT15__UART5_TX_DATA 0x1cc 0x4d4 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT15__UART5_RX_DATA 0x1cc 0x4d4 0x81c 0x4 0x3 -#define MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x1cc 0x4d4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT15__ARM_TRACE15 0x1cc 0x4d4 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT15__SRC_BOOT_CFG15 0x1cc 0x4d4 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1d0 0x4d8 0x7b8 0x0 0x1 -#define MX6SL_PAD_LCD_DAT16__KEY_COL4 0x1d0 0x4d8 0x744 0x1 0x1 -#define MX6SL_PAD_LCD_DAT16__CSI_DATA01 0x1d0 0x4d8 0x634 0x2 0x1 -#define MX6SL_PAD_LCD_DAT16__EIM_DATA10 0x1d0 0x4d8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT16__I2C2_SCL 0x1d0 0x4d8 0x724 0x4 0x3 -#define MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x1d0 0x4d8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT16__ARM_TRACE16 0x1d0 0x4d8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT16__SRC_BOOT_CFG24 0x1d0 0x4d8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1d4 0x4dc 0x7bc 0x0 0x1 -#define MX6SL_PAD_LCD_DAT17__KEY_ROW4 0x1d4 0x4dc 0x764 0x1 0x1 -#define MX6SL_PAD_LCD_DAT17__CSI_DATA00 0x1d4 0x4dc 0x630 0x2 0x1 -#define MX6SL_PAD_LCD_DAT17__EIM_DATA11 0x1d4 0x4dc 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT17__I2C2_SDA 0x1d4 0x4dc 0x728 0x4 0x3 -#define MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x1d4 0x4dc 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT17__ARM_TRACE17 0x1d4 0x4dc 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT17__SRC_BOOT_CFG25 0x1d4 0x4dc 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1d8 0x4e0 0x7c0 0x0 0x1 -#define MX6SL_PAD_LCD_DAT18__KEY_COL5 0x1d8 0x4e0 0x748 0x1 0x1 -#define MX6SL_PAD_LCD_DAT18__CSI_DATA15 0x1d8 0x4e0 0x66c 0x2 0x0 -#define MX6SL_PAD_LCD_DAT18__EIM_DATA12 0x1d8 0x4e0 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT18__GPT_CAPTURE1 0x1d8 0x4e0 0x710 0x4 0x1 -#define MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x1d8 0x4e0 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT18__ARM_TRACE18 0x1d8 0x4e0 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT18__SRC_BOOT_CFG26 0x1d8 0x4e0 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1dc 0x4e4 0x7c4 0x0 0x1 -#define MX6SL_PAD_LCD_DAT19__KEY_ROW5 0x1dc 0x4e4 0x768 0x1 0x1 -#define MX6SL_PAD_LCD_DAT19__CSI_DATA14 0x1dc 0x4e4 0x668 0x2 0x0 -#define MX6SL_PAD_LCD_DAT19__EIM_DATA13 0x1dc 0x4e4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT19__GPT_CAPTURE2 0x1dc 0x4e4 0x714 0x4 0x1 -#define MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x1dc 0x4e4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT19__ARM_TRACE19 0x1dc 0x4e4 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT19__SRC_BOOT_CFG27 0x1dc 0x4e4 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1e0 0x4e8 0x780 0x0 0x1 -#define MX6SL_PAD_LCD_DAT2__ECSPI1_SS0 0x1e0 0x4e8 0x68c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT2__EPIT2_OUT 0x1e0 0x4e8 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_DAT2__PWM3_OUT 0x1e0 0x4e8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT2__AUD4_RXC 0x1e0 0x4e8 0x5ec 0x4 0x1 -#define MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x1e0 0x4e8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT2__ARM_TRACE02 0x1e0 0x4e8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT2__SRC_BOOT_CFG02 0x1e0 0x4e8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1e4 0x4ec 0x7c8 0x0 0x1 -#define MX6SL_PAD_LCD_DAT20__KEY_COL6 0x1e4 0x4ec 0x74c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT20__CSI_DATA13 0x1e4 0x4ec 0x664 0x2 0x0 -#define MX6SL_PAD_LCD_DAT20__EIM_DATA14 0x1e4 0x4ec 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT20__GPT_COMPARE1 0x1e4 0x4ec 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x1e4 0x4ec 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT20__ARM_TRACE20 0x1e4 0x4ec 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT20__SRC_BOOT_CFG28 0x1e4 0x4ec 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1e8 0x4f0 0x7cc 0x0 0x1 -#define MX6SL_PAD_LCD_DAT21__KEY_ROW6 0x1e8 0x4f0 0x76c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT21__CSI_DATA12 0x1e8 0x4f0 0x660 0x2 0x0 -#define MX6SL_PAD_LCD_DAT21__EIM_DATA15 0x1e8 0x4f0 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT21__GPT_COMPARE2 0x1e8 0x4f0 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x1e8 0x4f0 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT21__ARM_TRACE21 0x1e8 0x4f0 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT21__SRC_BOOT_CFG29 0x1e8 0x4f0 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1ec 0x4f4 0x7d0 0x0 0x1 -#define MX6SL_PAD_LCD_DAT22__KEY_COL7 0x1ec 0x4f4 0x750 0x1 0x1 -#define MX6SL_PAD_LCD_DAT22__CSI_DATA11 0x1ec 0x4f4 0x65c 0x2 0x1 -#define MX6SL_PAD_LCD_DAT22__EIM_EB3_B 0x1ec 0x4f4 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT22__GPT_COMPARE3 0x1ec 0x4f4 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x1ec 0x4f4 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT22__ARM_TRACE22 0x1ec 0x4f4 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT22__SRC_BOOT_CFG30 0x1ec 0x4f4 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1f0 0x4f8 0x7d4 0x0 0x1 -#define MX6SL_PAD_LCD_DAT23__KEY_ROW7 0x1f0 0x4f8 0x770 0x1 0x1 -#define MX6SL_PAD_LCD_DAT23__CSI_DATA10 0x1f0 0x4f8 0x658 0x2 0x1 -#define MX6SL_PAD_LCD_DAT23__EIM_EB2_B 0x1f0 0x4f8 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT23__GPT_CLKIN 0x1f0 0x4f8 0x718 0x4 0x1 -#define MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x1f0 0x4f8 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT23__ARM_TRACE23 0x1f0 0x4f8 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT23__SRC_BOOT_CFG31 0x1f0 0x4f8 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1f4 0x4fc 0x784 0x0 0x1 -#define MX6SL_PAD_LCD_DAT3__ECSPI1_SCLK 0x1f4 0x4fc 0x67c 0x1 0x1 -#define MX6SL_PAD_LCD_DAT3__UART5_DSR_B 0x1f4 0x4fc 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_DAT3__PWM4_OUT 0x1f4 0x4fc 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT3__AUD4_RXD 0x1f4 0x4fc 0x5e4 0x4 0x1 -#define MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x1f4 0x4fc 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT3__ARM_TRACE03 0x1f4 0x4fc 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT3__SRC_BOOT_CFG03 0x1f4 0x4fc 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1f8 0x500 0x788 0x0 0x1 -#define MX6SL_PAD_LCD_DAT4__ECSPI1_SS1 0x1f8 0x500 0x690 0x1 0x1 -#define MX6SL_PAD_LCD_DAT4__CSI_VSYNC 0x1f8 0x500 0x678 0x2 0x2 -#define MX6SL_PAD_LCD_DAT4__WDOG2_RESET_B_DEB 0x1f8 0x500 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT4__AUD4_TXC 0x1f8 0x500 0x5f4 0x4 0x1 -#define MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x1f8 0x500 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT4__ARM_TRACE04 0x1f8 0x500 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT4__SRC_BOOT_CFG04 0x1f8 0x500 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1fc 0x504 0x78c 0x0 0x1 -#define MX6SL_PAD_LCD_DAT5__ECSPI1_SS2 0x1fc 0x504 0x694 0x1 0x1 -#define MX6SL_PAD_LCD_DAT5__CSI_HSYNC 0x1fc 0x504 0x670 0x2 0x2 -#define MX6SL_PAD_LCD_DAT5__EIM_CS3_B 0x1fc 0x504 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT5__AUD4_TXFS 0x1fc 0x504 0x5f8 0x4 0x1 -#define MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x1fc 0x504 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT5__ARM_TRACE05 0x1fc 0x504 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT5__SRC_BOOT_CFG05 0x1fc 0x504 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x200 0x508 0x790 0x0 0x1 -#define MX6SL_PAD_LCD_DAT6__ECSPI1_SS3 0x200 0x508 0x698 0x1 0x1 -#define MX6SL_PAD_LCD_DAT6__CSI_PIXCLK 0x200 0x508 0x674 0x2 0x2 -#define MX6SL_PAD_LCD_DAT6__EIM_DATA00 0x200 0x508 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT6__AUD4_TXD 0x200 0x508 0x5e8 0x4 0x1 -#define MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x200 0x508 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT6__ARM_TRACE06 0x200 0x508 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT6__SRC_BOOT_CFG06 0x200 0x508 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x204 0x50c 0x794 0x0 0x1 -#define MX6SL_PAD_LCD_DAT7__ECSPI1_RDY 0x204 0x50c 0x680 0x1 0x1 -#define MX6SL_PAD_LCD_DAT7__CSI_MCLK 0x204 0x50c 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_DAT7__EIM_DATA01 0x204 0x50c 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT7__AUDIO_CLK_OUT 0x204 0x50c 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x204 0x50c 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT7__ARM_TRACE07 0x204 0x50c 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT7__SRC_BOOT_CFG07 0x204 0x50c 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x208 0x510 0x798 0x0 0x1 -#define MX6SL_PAD_LCD_DAT8__KEY_COL0 0x208 0x510 0x734 0x1 0x1 -#define MX6SL_PAD_LCD_DAT8__CSI_DATA09 0x208 0x510 0x654 0x2 0x1 -#define MX6SL_PAD_LCD_DAT8__EIM_DATA02 0x208 0x510 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT8__ECSPI2_SCLK 0x208 0x510 0x69c 0x4 0x2 -#define MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x208 0x510 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT8__ARM_TRACE08 0x208 0x510 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT8__SRC_BOOT_CFG08 0x208 0x510 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x20c 0x514 0x79c 0x0 0x1 -#define MX6SL_PAD_LCD_DAT9__KEY_ROW0 0x20c 0x514 0x754 0x1 0x1 -#define MX6SL_PAD_LCD_DAT9__CSI_DATA08 0x20c 0x514 0x650 0x2 0x1 -#define MX6SL_PAD_LCD_DAT9__EIM_DATA03 0x20c 0x514 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_DAT9__ECSPI2_MOSI 0x20c 0x514 0x6a4 0x4 0x2 -#define MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x20c 0x514 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_DAT9__ARM_TRACE09 0x20c 0x514 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_DAT9__SRC_BOOT_CFG09 0x20c 0x514 0x000 0x7 0x0 -#define MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x210 0x518 0x000 0x0 0x0 -#define MX6SL_PAD_LCD_ENABLE__SD4_DATA5 0x210 0x518 0x870 0x1 0x2 -#define MX6SL_PAD_LCD_ENABLE__LCD_RD_E 0x210 0x518 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_ENABLE__EIM_OE_B 0x210 0x518 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_ENABLE__UART2_RX_DATA 0x210 0x518 0x804 0x4 0x2 -#define MX6SL_PAD_LCD_ENABLE__UART2_TX_DATA 0x210 0x518 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x210 0x518 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x214 0x51c 0x774 0x0 0x0 -#define MX6SL_PAD_LCD_HSYNC__SD4_DATA6 0x214 0x51c 0x874 0x1 0x2 -#define MX6SL_PAD_LCD_HSYNC__LCD_CS 0x214 0x51c 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_HSYNC__EIM_CS0_B 0x214 0x51c 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_HSYNC__UART2_TX_DATA 0x214 0x51c 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_HSYNC__UART2_RX_DATA 0x214 0x51c 0x804 0x4 0x3 -#define MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x214 0x51c 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x214 0x51c 0x000 0x6 0x0 -#define MX6SL_PAD_LCD_RESET__LCD_RESET 0x218 0x520 0x000 0x0 0x0 -#define MX6SL_PAD_LCD_RESET__EIM_DTACK_B 0x218 0x520 0x880 0x1 0x1 -#define MX6SL_PAD_LCD_RESET__LCD_BUSY 0x218 0x520 0x774 0x2 0x1 -#define MX6SL_PAD_LCD_RESET__EIM_WAIT_B 0x218 0x520 0x884 0x3 0x1 -#define MX6SL_PAD_LCD_RESET__UART2_CTS_B 0x218 0x520 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_RESET__UART2_RTS_B 0x218 0x520 0x800 0x4 0x2 -#define MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x218 0x520 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_RESET__CCM_PMIC_READY 0x218 0x520 0x62c 0x6 0x1 -#define MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x21c 0x524 0x000 0x0 0x0 -#define MX6SL_PAD_LCD_VSYNC__SD4_DATA7 0x21c 0x524 0x878 0x1 0x2 -#define MX6SL_PAD_LCD_VSYNC__LCD_RS 0x21c 0x524 0x000 0x2 0x0 -#define MX6SL_PAD_LCD_VSYNC__EIM_CS1_B 0x21c 0x524 0x000 0x3 0x0 -#define MX6SL_PAD_LCD_VSYNC__UART2_RTS_B 0x21c 0x524 0x800 0x4 0x3 -#define MX6SL_PAD_LCD_VSYNC__UART2_CTS_B 0x21c 0x524 0x000 0x4 0x0 -#define MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x21c 0x524 0x000 0x5 0x0 -#define MX6SL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x21c 0x524 0x000 0x6 0x0 -#define MX6SL_PAD_PWM1__PWM1_OUT 0x220 0x528 0x000 0x0 0x0 -#define MX6SL_PAD_PWM1__CCM_CLKO 0x220 0x528 0x000 0x1 0x0 -#define MX6SL_PAD_PWM1__AUDIO_CLK_OUT 0x220 0x528 0x000 0x2 0x0 -#define MX6SL_PAD_PWM1__FEC_REF_OUT 0x220 0x528 0x000 0x3 0x0 -#define MX6SL_PAD_PWM1__CSI_MCLK 0x220 0x528 0x000 0x4 0x0 -#define MX6SL_PAD_PWM1__GPIO3_IO23 0x220 0x528 0x000 0x5 0x0 -#define MX6SL_PAD_PWM1__EPIT1_OUT 0x220 0x528 0x000 0x6 0x0 -#define MX6SL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x224 0x52c 0x000 0x0 0x0 -#define MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x224 0x52c 0x72c 0x1 0x2 -#define MX6SL_PAD_REF_CLK_24M__PWM3_OUT 0x224 0x52c 0x000 0x2 0x0 -#define MX6SL_PAD_REF_CLK_24M__USB_OTG2_ID 0x224 0x52c 0x5e0 0x3 0x2 -#define MX6SL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x224 0x52c 0x62c 0x4 0x2 -#define MX6SL_PAD_REF_CLK_24M__GPIO3_IO21 0x224 0x52c 0x000 0x5 0x0 -#define MX6SL_PAD_REF_CLK_24M__SD3_WP 0x224 0x52c 0x84c 0x6 0x3 -#define MX6SL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x228 0x530 0x000 0x0 0x0 -#define MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x228 0x530 0x730 0x1 0x2 -#define MX6SL_PAD_REF_CLK_32K__PWM4_OUT 0x228 0x530 0x000 0x2 0x0 -#define MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x228 0x530 0x5dc 0x3 0x3 -#define MX6SL_PAD_REF_CLK_32K__SD1_LCTL 0x228 0x530 0x000 0x4 0x0 -#define MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x228 0x530 0x000 0x5 0x0 -#define MX6SL_PAD_REF_CLK_32K__SD3_CD_B 0x228 0x530 0x838 0x6 0x3 -#define MX6SL_PAD_SD1_CLK__SD1_CLK 0x22c 0x534 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_CLK__FEC_MDIO 0x22c 0x534 0x6f4 0x1 0x2 -#define MX6SL_PAD_SD1_CLK__KEY_COL0 0x22c 0x534 0x734 0x2 0x2 -#define MX6SL_PAD_SD1_CLK__EPDC_SDCE4 0x22c 0x534 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x22c 0x534 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_CMD__SD1_CMD 0x230 0x538 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_CMD__FEC_TX_CLK 0x230 0x538 0x70c 0x1 0x2 -#define MX6SL_PAD_SD1_CMD__KEY_ROW0 0x230 0x538 0x754 0x2 0x2 -#define MX6SL_PAD_SD1_CMD__EPDC_SDCE5 0x230 0x538 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_CMD__GPIO5_IO14 0x230 0x538 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x234 0x53c 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT0__FEC_RX_ER 0x234 0x53c 0x708 0x1 0x2 -#define MX6SL_PAD_SD1_DAT0__KEY_COL1 0x234 0x53c 0x738 0x2 0x2 -#define MX6SL_PAD_SD1_DAT0__EPDC_SDCE6 0x234 0x53c 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x234 0x53c 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x238 0x540 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT1__FEC_RX_DV 0x238 0x540 0x704 0x1 0x2 -#define MX6SL_PAD_SD1_DAT1__KEY_ROW1 0x238 0x540 0x758 0x2 0x2 -#define MX6SL_PAD_SD1_DAT1__EPDC_SDCE7 0x238 0x540 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x238 0x540 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x23c 0x544 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT2__FEC_RX_DATA1 0x23c 0x544 0x6fc 0x1 0x2 -#define MX6SL_PAD_SD1_DAT2__KEY_COL2 0x23c 0x544 0x73c 0x2 0x2 -#define MX6SL_PAD_SD1_DAT2__EPDC_SDCE8 0x23c 0x544 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x23c 0x544 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x240 0x548 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT3__FEC_TX_DATA0 0x240 0x548 0x000 0x1 0x0 -#define MX6SL_PAD_SD1_DAT3__KEY_ROW2 0x240 0x548 0x75c 0x2 0x2 -#define MX6SL_PAD_SD1_DAT3__EPDC_SDCE9 0x240 0x548 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x240 0x548 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x244 0x54c 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT4__FEC_MDC 0x244 0x54c 0x000 0x1 0x0 -#define MX6SL_PAD_SD1_DAT4__KEY_COL3 0x244 0x54c 0x740 0x2 0x2 -#define MX6SL_PAD_SD1_DAT4__EPDC_SDCLK_N 0x244 0x54c 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x244 0x54c 0x814 0x4 0x4 -#define MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x244 0x54c 0x000 0x4 0x0 -#define MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x244 0x54c 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x248 0x550 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT5__FEC_RX_DATA0 0x248 0x550 0x6f8 0x1 0x2 -#define MX6SL_PAD_SD1_DAT5__KEY_ROW3 0x248 0x550 0x760 0x2 0x2 -#define MX6SL_PAD_SD1_DAT5__EPDC_SDOED 0x248 0x550 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x248 0x550 0x000 0x4 0x0 -#define MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x248 0x550 0x814 0x4 0x5 -#define MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x248 0x550 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x24c 0x554 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT6__FEC_TX_EN 0x24c 0x554 0x000 0x1 0x0 -#define MX6SL_PAD_SD1_DAT6__KEY_COL4 0x24c 0x554 0x744 0x2 0x2 -#define MX6SL_PAD_SD1_DAT6__EPDC_SDOEZ 0x24c 0x554 0x000 0x3 0x0 -#define MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x24c 0x554 0x810 0x4 0x4 -#define MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x24c 0x554 0x000 0x4 0x0 -#define MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x24c 0x554 0x000 0x5 0x0 -#define MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x250 0x558 0x000 0x0 0x0 -#define MX6SL_PAD_SD1_DAT7__FEC_TX_DATA1 0x250 0x558 0x000 0x1 0x0 -#define MX6SL_PAD_SD1_DAT7__KEY_ROW4 0x250 0x558 0x764 0x2 0x2 -#define MX6SL_PAD_SD1_DAT7__CCM_PMIC_READY 0x250 0x558 0x62c 0x3 0x3 -#define MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x250 0x558 0x000 0x4 0x0 -#define MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x250 0x558 0x810 0x4 0x5 -#define MX6SL_PAD_SD1_DAT7__GPIO5_IO10 0x250 0x558 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_CLK__SD2_CLK 0x254 0x55c 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_CLK__AUD4_RXFS 0x254 0x55c 0x5f0 0x1 0x2 -#define MX6SL_PAD_SD2_CLK__ECSPI3_SCLK 0x254 0x55c 0x6b0 0x2 0x2 -#define MX6SL_PAD_SD2_CLK__CSI_DATA00 0x254 0x55c 0x630 0x3 0x2 -#define MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x254 0x55c 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_CMD__SD2_CMD 0x258 0x560 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_CMD__AUD4_RXC 0x258 0x560 0x5ec 0x1 0x2 -#define MX6SL_PAD_SD2_CMD__ECSPI3_SS0 0x258 0x560 0x6c0 0x2 0x2 -#define MX6SL_PAD_SD2_CMD__CSI_DATA01 0x258 0x560 0x634 0x3 0x2 -#define MX6SL_PAD_SD2_CMD__EPIT1_OUT 0x258 0x560 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x258 0x560 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x25c 0x564 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT0__AUD4_RXD 0x25c 0x564 0x5e4 0x1 0x2 -#define MX6SL_PAD_SD2_DAT0__ECSPI3_MOSI 0x25c 0x564 0x6bc 0x2 0x2 -#define MX6SL_PAD_SD2_DAT0__CSI_DATA02 0x25c 0x564 0x638 0x3 0x2 -#define MX6SL_PAD_SD2_DAT0__UART5_RTS_B 0x25c 0x564 0x818 0x4 0x4 -#define MX6SL_PAD_SD2_DAT0__UART5_CTS_B 0x25c 0x564 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x25c 0x564 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x260 0x568 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT1__AUD4_TXC 0x260 0x568 0x5f4 0x1 0x2 -#define MX6SL_PAD_SD2_DAT1__ECSPI3_MISO 0x260 0x568 0x6b8 0x2 0x2 -#define MX6SL_PAD_SD2_DAT1__CSI_DATA03 0x260 0x568 0x63c 0x3 0x2 -#define MX6SL_PAD_SD2_DAT1__UART5_CTS_B 0x260 0x568 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT1__UART5_RTS_B 0x260 0x568 0x818 0x4 0x5 -#define MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x260 0x568 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x264 0x56c 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT2__AUD4_TXFS 0x264 0x56c 0x5f8 0x1 0x2 -#define MX6SL_PAD_SD2_DAT2__FEC_COL 0x264 0x56c 0x6f0 0x2 0x1 -#define MX6SL_PAD_SD2_DAT2__CSI_DATA04 0x264 0x56c 0x640 0x3 0x2 -#define MX6SL_PAD_SD2_DAT2__UART5_RX_DATA 0x264 0x56c 0x81c 0x4 0x4 -#define MX6SL_PAD_SD2_DAT2__UART5_TX_DATA 0x264 0x56c 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x264 0x56c 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x268 0x570 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT3__AUD4_TXD 0x268 0x570 0x5e8 0x1 0x2 -#define MX6SL_PAD_SD2_DAT3__FEC_RX_CLK 0x268 0x570 0x700 0x2 0x1 -#define MX6SL_PAD_SD2_DAT3__CSI_DATA05 0x268 0x570 0x644 0x3 0x2 -#define MX6SL_PAD_SD2_DAT3__UART5_TX_DATA 0x268 0x570 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT3__UART5_RX_DATA 0x268 0x570 0x81c 0x4 0x5 -#define MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x268 0x570 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x26c 0x574 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT4__SD3_DATA4 0x26c 0x574 0x83c 0x1 0x1 -#define MX6SL_PAD_SD2_DAT4__UART2_RX_DATA 0x26c 0x574 0x804 0x2 0x4 -#define MX6SL_PAD_SD2_DAT4__UART2_TX_DATA 0x26c 0x574 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_DAT4__CSI_DATA06 0x26c 0x574 0x648 0x3 0x2 -#define MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x26c 0x574 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_DAT4__GPIO5_IO02 0x26c 0x574 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x270 0x578 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT5__SD3_DATA5 0x270 0x578 0x840 0x1 0x1 -#define MX6SL_PAD_SD2_DAT5__UART2_TX_DATA 0x270 0x578 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_DAT5__UART2_RX_DATA 0x270 0x578 0x804 0x2 0x5 -#define MX6SL_PAD_SD2_DAT5__CSI_DATA07 0x270 0x578 0x64c 0x3 0x2 -#define MX6SL_PAD_SD2_DAT5__SPDIF_IN 0x270 0x578 0x7f0 0x4 0x2 -#define MX6SL_PAD_SD2_DAT5__GPIO4_IO31 0x270 0x578 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x274 0x57c 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT6__SD3_DATA6 0x274 0x57c 0x844 0x1 0x1 -#define MX6SL_PAD_SD2_DAT6__UART2_RTS_B 0x274 0x57c 0x800 0x2 0x4 -#define MX6SL_PAD_SD2_DAT6__UART2_CTS_B 0x274 0x57c 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_DAT6__CSI_DATA08 0x274 0x57c 0x650 0x3 0x2 -#define MX6SL_PAD_SD2_DAT6__SD2_WP 0x274 0x57c 0x834 0x4 0x2 -#define MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x274 0x57c 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x278 0x580 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_DAT7__SD3_DATA7 0x278 0x580 0x848 0x1 0x1 -#define MX6SL_PAD_SD2_DAT7__UART2_CTS_B 0x278 0x580 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_DAT7__UART2_RTS_B 0x278 0x580 0x800 0x2 0x5 -#define MX6SL_PAD_SD2_DAT7__CSI_DATA09 0x278 0x580 0x654 0x3 0x2 -#define MX6SL_PAD_SD2_DAT7__SD2_CD_B 0x278 0x580 0x830 0x4 0x2 -#define MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x278 0x580 0x000 0x5 0x0 -#define MX6SL_PAD_SD2_RST__SD2_RESET 0x27c 0x584 0x000 0x0 0x0 -#define MX6SL_PAD_SD2_RST__FEC_REF_OUT 0x27c 0x584 0x000 0x1 0x0 -#define MX6SL_PAD_SD2_RST__WDOG2_B 0x27c 0x584 0x000 0x2 0x0 -#define MX6SL_PAD_SD2_RST__SPDIF_OUT 0x27c 0x584 0x000 0x3 0x0 -#define MX6SL_PAD_SD2_RST__CSI_MCLK 0x27c 0x584 0x000 0x4 0x0 -#define MX6SL_PAD_SD2_RST__GPIO4_IO27 0x27c 0x584 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_CLK__SD3_CLK 0x280 0x588 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_CLK__AUD5_RXFS 0x280 0x588 0x608 0x1 0x1 -#define MX6SL_PAD_SD3_CLK__KEY_COL5 0x280 0x588 0x748 0x2 0x2 -#define MX6SL_PAD_SD3_CLK__CSI_DATA10 0x280 0x588 0x658 0x3 0x2 -#define MX6SL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x280 0x588 0x000 0x4 0x0 -#define MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x280 0x588 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_CLK__USB_OTG1_PWR 0x280 0x588 0x000 0x6 0x0 -#define MX6SL_PAD_SD3_CMD__SD3_CMD 0x284 0x58c 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_CMD__AUD5_RXC 0x284 0x58c 0x604 0x1 0x1 -#define MX6SL_PAD_SD3_CMD__KEY_ROW5 0x284 0x58c 0x768 0x2 0x2 -#define MX6SL_PAD_SD3_CMD__CSI_DATA11 0x284 0x58c 0x65c 0x3 0x2 -#define MX6SL_PAD_SD3_CMD__USB_OTG2_ID 0x284 0x58c 0x5e0 0x4 0x3 -#define MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x284 0x58c 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_CMD__USB_OTG2_PWR 0x284 0x58c 0x000 0x6 0x0 -#define MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x288 0x590 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_DAT0__AUD5_RXD 0x288 0x590 0x5fc 0x1 0x1 -#define MX6SL_PAD_SD3_DAT0__KEY_COL6 0x288 0x590 0x74c 0x2 0x2 -#define MX6SL_PAD_SD3_DAT0__CSI_DATA12 0x288 0x590 0x660 0x3 0x1 -#define MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x288 0x590 0x5dc 0x4 0x4 -#define MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x288 0x590 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x28c 0x594 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_DAT1__AUD5_TXC 0x28c 0x594 0x60c 0x1 0x1 -#define MX6SL_PAD_SD3_DAT1__KEY_ROW6 0x28c 0x594 0x76c 0x2 0x2 -#define MX6SL_PAD_SD3_DAT1__CSI_DATA13 0x28c 0x594 0x664 0x3 0x1 -#define MX6SL_PAD_SD3_DAT1__SD1_VSELECT 0x28c 0x594 0x000 0x4 0x0 -#define MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x28c 0x594 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_DAT1__JTAG_DE_B 0x28c 0x594 0x000 0x6 0x0 -#define MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x290 0x598 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_DAT2__AUD5_TXFS 0x290 0x598 0x610 0x1 0x1 -#define MX6SL_PAD_SD3_DAT2__KEY_COL7 0x290 0x598 0x750 0x2 0x2 -#define MX6SL_PAD_SD3_DAT2__CSI_DATA14 0x290 0x598 0x668 0x3 0x1 -#define MX6SL_PAD_SD3_DAT2__EPIT1_OUT 0x290 0x598 0x000 0x4 0x0 -#define MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x290 0x598 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x290 0x598 0x820 0x6 0x3 -#define MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x294 0x59c 0x000 0x0 0x0 -#define MX6SL_PAD_SD3_DAT3__AUD5_TXD 0x294 0x59c 0x600 0x1 0x1 -#define MX6SL_PAD_SD3_DAT3__KEY_ROW7 0x294 0x59c 0x770 0x2 0x2 -#define MX6SL_PAD_SD3_DAT3__CSI_DATA15 0x294 0x59c 0x66c 0x3 0x1 -#define MX6SL_PAD_SD3_DAT3__EPIT2_OUT 0x294 0x59c 0x000 0x4 0x0 -#define MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x294 0x59c 0x000 0x5 0x0 -#define MX6SL_PAD_SD3_DAT3__USB_OTG1_OC 0x294 0x59c 0x824 0x6 0x2 -#define MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x298 0x5a0 0x7fc 0x0 0x0 -#define MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x298 0x5a0 0x000 0x0 0x0 -#define MX6SL_PAD_UART1_RXD__PWM1_OUT 0x298 0x5a0 0x000 0x1 0x0 -#define MX6SL_PAD_UART1_RXD__UART4_RX_DATA 0x298 0x5a0 0x814 0x2 0x6 -#define MX6SL_PAD_UART1_RXD__UART4_TX_DATA 0x298 0x5a0 0x000 0x2 0x0 -#define MX6SL_PAD_UART1_RXD__FEC_COL 0x298 0x5a0 0x6f0 0x3 0x2 -#define MX6SL_PAD_UART1_RXD__UART5_RX_DATA 0x298 0x5a0 0x81c 0x4 0x6 -#define MX6SL_PAD_UART1_RXD__UART5_TX_DATA 0x298 0x5a0 0x000 0x4 0x0 -#define MX6SL_PAD_UART1_RXD__GPIO3_IO16 0x298 0x5a0 0x000 0x5 0x0 -#define MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x29c 0x5a4 0x000 0x0 0x0 -#define MX6SL_PAD_UART1_TXD__UART1_RX_DATA 0x29c 0x5a4 0x7fc 0x0 0x1 -#define MX6SL_PAD_UART1_TXD__PWM2_OUT 0x29c 0x5a4 0x000 0x1 0x0 -#define MX6SL_PAD_UART1_TXD__UART4_TX_DATA 0x29c 0x5a4 0x000 0x2 0x0 -#define MX6SL_PAD_UART1_TXD__UART4_RX_DATA 0x29c 0x5a4 0x814 0x2 0x7 -#define MX6SL_PAD_UART1_TXD__FEC_RX_CLK 0x29c 0x5a4 0x700 0x3 0x2 -#define MX6SL_PAD_UART1_TXD__UART5_TX_DATA 0x29c 0x5a4 0x000 0x4 0x0 -#define MX6SL_PAD_UART1_TXD__UART5_RX_DATA 0x29c 0x5a4 0x81c 0x4 0x7 -#define MX6SL_PAD_UART1_TXD__GPIO3_IO17 0x29c 0x5a4 0x000 0x5 0x0 -#define MX6SL_PAD_UART1_TXD__UART5_DCD_B 0x29c 0x5a4 0x000 0x7 0x0 -#define MX6SL_PAD_WDOG_B__WDOG1_B 0x2a0 0x5a8 0x000 0x0 0x0 -#define MX6SL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x2a0 0x5a8 0x000 0x1 0x0 -#define MX6SL_PAD_WDOG_B__UART5_RI_B 0x2a0 0x5a8 0x000 0x2 0x0 -#define MX6SL_PAD_WDOG_B__GPIO3_IO18 0x2a0 0x5a8 0x000 0x5 0x0 - -#endif /* __DTS_IMX6SL_PINFUNC_H */ diff --git a/arch/arm/dts/imx6sl.dtsi b/arch/arm/dts/imx6sl.dtsi deleted file mode 100644 index 271f4b971a8..00000000000 --- a/arch/arm/dts/imx6sl.dtsi +++ /dev/null @@ -1,1005 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2013 Freescale Semiconductor, Inc. - -#include <dt-bindings/interrupt-controller/irq.h> -#include "imx6sl-pinfunc.h" -#include <dt-bindings/clock/imx6sl-clock.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - mmc3 = &usdhc4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - usb0 = &usbotg1; - usb1 = &usbotg2; - usb2 = &usbh; - usbphy0 = &usbphy1; - usbphy1 = &usbphy2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0x0>; - next-level-cache = <&L2>; - operating-points = - /* kHz uV */ - <996000 1275000>, - <792000 1175000>, - <396000 975000>; - fsl,soc-operating-points = - /* ARM kHz SOC-PU uV */ - <996000 1225000>, - <792000 1175000>, - <396000 1175000>; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, - <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, - <&clks IMX6SL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; - }; - }; - - clocks { - ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&gpc>; - interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gpc>; - ranges; - - ocram: sram@900000 { - compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; - clocks = <&clks IMX6SL_CLK_OCRAM>; - }; - - intc: interrupt-controller@a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; - interrupt-parent = <&intc>; - }; - - L2: cache-controller@a02000 { - compatible = "arm,pl310-cache"; - reg = <0x00a02000 0x1000>; - interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <4 2 3>; - arm,data-latency = <4 2 3>; - }; - - aips1: bus@2000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x100000>; - ranges; - - spba: spba-bus@2000000 { - compatible = "fsl,spba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02000000 0x40000>; - ranges; - - spdif: spdif@2004000 { - compatible = "fsl,imx6sl-spdif", - "fsl,imx35-spdif"; - reg = <0x02004000 0x4000>; - interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 14 18 0>, - <&sdma 15 18 0>; - dma-names = "rx", "tx"; - clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>, - <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>, - <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>, - <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>, - <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>; - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "spba"; - status = "disabled"; - }; - - ecspi1: spi@2008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; - reg = <0x02008000 0x4000>; - interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ECSPI1>, - <&clks IMX6SL_CLK_ECSPI1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi2: spi@200c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; - reg = <0x0200c000 0x4000>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ECSPI2>, - <&clks IMX6SL_CLK_ECSPI2>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi3: spi@2010000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; - reg = <0x02010000 0x4000>; - interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ECSPI3>, - <&clks IMX6SL_CLK_ECSPI3>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi4: spi@2014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; - reg = <0x02014000 0x4000>; - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ECSPI4>, - <&clks IMX6SL_CLK_ECSPI4>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart5: serial@2018000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02018000 0x4000>; - interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@2020000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@2024000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02024000 0x4000>; - interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ssi1: ssi@2028000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sl-ssi", - "fsl,imx51-ssi"; - reg = <0x02028000 0x4000>; - interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI1_IPG>, - <&clks IMX6SL_CLK_SSI1>; - clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, - <&sdma 38 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi2: ssi@202c000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sl-ssi", - "fsl,imx51-ssi"; - reg = <0x0202c000 0x4000>; - interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI2_IPG>, - <&clks IMX6SL_CLK_SSI2>; - clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, - <&sdma 42 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - ssi3: ssi@2030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx6sl-ssi", - "fsl,imx51-ssi"; - reg = <0x02030000 0x4000>; - interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI3_IPG>, - <&clks IMX6SL_CLK_SSI3>; - clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, - <&sdma 46 1 0>; - dma-names = "rx", "tx"; - fsl,fifo-depth = <15>; - status = "disabled"; - }; - - uart3: serial@2034000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02034000 0x4000>; - interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@2038000 { - compatible = "fsl,imx6sl-uart", - "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02038000 0x4000>; - interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_UART>, - <&clks IMX6SL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; - dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - }; - - pwm1: pwm@2080000 { - #pwm-cells = <3>; - compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; - reg = <0x02080000 0x4000>; - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PERCLK>, - <&clks IMX6SL_CLK_PWM1>; - clock-names = "ipg", "per"; - }; - - pwm2: pwm@2084000 { - #pwm-cells = <3>; - compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; - reg = <0x02084000 0x4000>; - interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PERCLK>, - <&clks IMX6SL_CLK_PWM2>; - clock-names = "ipg", "per"; - }; - - pwm3: pwm@2088000 { - #pwm-cells = <3>; - compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; - reg = <0x02088000 0x4000>; - interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PERCLK>, - <&clks IMX6SL_CLK_PWM3>; - clock-names = "ipg", "per"; - }; - - pwm4: pwm@208c000 { - #pwm-cells = <3>; - compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; - reg = <0x0208c000 0x4000>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_PERCLK>, - <&clks IMX6SL_CLK_PWM4>; - clock-names = "ipg", "per"; - }; - - gpt: timer@2098000 { - compatible = "fsl,imx6sl-gpt"; - reg = <0x02098000 0x4000>; - interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_GPT>, - <&clks IMX6SL_CLK_GPT_SERIAL>; - clock-names = "ipg", "per"; - }; - - gpio1: gpio@209c000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x0209c000 0x4000>; - interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, - <0 67 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>, - <&iomuxc 3 23 1>, <&iomuxc 4 25 1>, - <&iomuxc 5 24 1>, <&iomuxc 6 19 1>, - <&iomuxc 7 36 2>, <&iomuxc 9 44 8>, - <&iomuxc 17 38 6>, <&iomuxc 23 68 4>, - <&iomuxc 27 64 4>, <&iomuxc 31 52 1>; - }; - - gpio2: gpio@20a0000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x020a0000 0x4000>; - interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, - <0 69 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>, - <&iomuxc 5 34 2>, <&iomuxc 7 57 4>, - <&iomuxc 11 56 1>, <&iomuxc 12 61 3>, - <&iomuxc 15 107 1>, <&iomuxc 16 132 2>, - <&iomuxc 18 135 1>, <&iomuxc 19 134 1>, - <&iomuxc 20 108 2>, <&iomuxc 22 120 1>, - <&iomuxc 23 125 7>, <&iomuxc 30 110 2>; - }; - - gpio3: gpio@20a4000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x020a4000 0x4000>; - interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, - <0 71 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>, - <&iomuxc 12 97 4>, <&iomuxc 16 166 3>, - <&iomuxc 19 85 2>, <&iomuxc 21 137 2>, - <&iomuxc 23 136 1>, <&iomuxc 24 91 1>, - <&iomuxc 25 99 1>, <&iomuxc 26 92 1>, - <&iomuxc 27 100 1>, <&iomuxc 28 93 1>, - <&iomuxc 29 101 1>, <&iomuxc 30 94 1>, - <&iomuxc 31 102 1>; - }; - - gpio4: gpio@20a8000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x020a8000 0x4000>; - interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, - <0 73 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>, - <&iomuxc 2 96 1>, <&iomuxc 3 104 1>, - <&iomuxc 4 97 1>, <&iomuxc 5 105 1>, - <&iomuxc 6 98 1>, <&iomuxc 7 106 1>, - <&iomuxc 8 28 1>, <&iomuxc 9 27 1>, - <&iomuxc 10 26 1>, <&iomuxc 11 29 1>, - <&iomuxc 12 32 1>, <&iomuxc 13 31 1>, - <&iomuxc 14 30 1>, <&iomuxc 15 33 1>, - <&iomuxc 16 84 1>, <&iomuxc 17 79 2>, - <&iomuxc 19 78 1>, <&iomuxc 20 76 1>, - <&iomuxc 21 81 2>, <&iomuxc 23 75 1>, - <&iomuxc 24 83 1>, <&iomuxc 25 74 1>, - <&iomuxc 26 77 1>, <&iomuxc 27 159 1>, - <&iomuxc 28 154 1>, <&iomuxc 29 157 1>, - <&iomuxc 30 152 1>, <&iomuxc 31 156 1>; - }; - - gpio5: gpio@20ac000 { - compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; - reg = <0x020ac000 0x4000>; - interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, - <0 75 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>, - <&iomuxc 2 155 1>, <&iomuxc 3 153 1>, - <&iomuxc 4 150 1>, <&iomuxc 5 149 1>, - <&iomuxc 6 144 1>, <&iomuxc 7 147 1>, - <&iomuxc 8 142 1>, <&iomuxc 9 146 1>, - <&iomuxc 10 148 1>, <&iomuxc 11 141 1>, - <&iomuxc 12 145 1>, <&iomuxc 13 143 1>, - <&iomuxc 14 140 1>, <&iomuxc 15 139 1>, - <&iomuxc 16 164 2>, <&iomuxc 18 160 1>, - <&iomuxc 19 162 1>, <&iomuxc 20 163 1>, - <&iomuxc 21 161 1>; - }; - - kpp: keypad@20b8000 { - compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; - reg = <0x020b8000 0x4000>; - interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_IPG>; - status = "disabled"; - }; - - wdog1: watchdog@20bc000 { - compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; - reg = <0x020bc000 0x4000>; - interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_IPG>; - }; - - wdog2: watchdog@20c0000 { - compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; - reg = <0x020c0000 0x4000>; - interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_IPG>; - status = "disabled"; - }; - - clks: clock-controller@20c4000 { - compatible = "fsl,imx6sl-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, - <0 88 IRQ_TYPE_LEVEL_HIGH>; - #clock-cells = <1>; - }; - - anatop: anatop@20c8000 { - compatible = "fsl,imx6sl-anatop", - "fsl,imx6q-anatop", - "syscon", "simple-mfd"; - reg = <0x020c8000 0x1000>; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, - <0 54 IRQ_TYPE_LEVEL_HIGH>, - <0 127 IRQ_TYPE_LEVEL_HIGH>; - - reg_vdd1p1: regulator-1p1 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - anatop-reg-offset = <0x110>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <4>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1375000>; - anatop-enable-bit = <0>; - }; - - reg_vdd3p0: regulator-3p0 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; - anatop-enable-bit = <0>; - }; - - reg_vdd2p5: regulator-2p5 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd2p5"; - regulator-min-microvolt = <2250000>; - regulator-max-microvolt = <2750000>; - regulator-always-on; - anatop-reg-offset = <0x130>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2100000>; - anatop-max-voltage = <2850000>; - anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddarm"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <0>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <24>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_pu: regulator-vddpu { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddpu"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <9>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <26>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - reg_soc: regulator-vddsoc { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddsoc"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <18>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <28>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; - }; - - tempmon: tempmon { - compatible = "fsl,imx6q-tempmon"; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gpc>; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; - }; - }; - - usbphy1: usbphy@20c9000 { - compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; - reg = <0x020c9000 0x1000>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBPHY1>; - fsl,anatop = <&anatop>; - }; - - usbphy2: usbphy@20ca000 { - compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; - reg = <0x020ca000 0x1000>; - interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBPHY2>; - fsl,anatop = <&anatop>; - }; - - snvs: snvs@20cc000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x020cc000 0x4000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, - <0 20 IRQ_TYPE_LEVEL_HIGH>; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - value = <0x60>; - mask = <0x60>; - status = "disabled"; - }; - }; - - epit1: epit@20d0000 { - reg = <0x020d0000 0x4000>; - interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; - }; - - epit2: epit@20d4000 { - reg = <0x020d4000 0x4000>; - interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; - }; - - src: reset-controller@20d8000 { - compatible = "fsl,imx6sl-src", "fsl,imx51-src"; - reg = <0x020d8000 0x4000>; - interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, - <0 96 IRQ_TYPE_LEVEL_HIGH>; - #reset-cells = <1>; - }; - - gpc: gpc@20dc000 { - compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&intc>; - clocks = <&clks IMX6SL_CLK_IPG>; - clock-names = "ipg"; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - power-domain@0 { - reg = <0>; - #power-domain-cells = <0>; - }; - - pd_pu: power-domain@1 { - reg = <1>; - #power-domain-cells = <0>; - power-supply = <®_pu>; - clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, - <&clks IMX6SL_CLK_GPU2D_PODF>; - }; - - pd_disp: power-domain@2 { - reg = <2>; - #power-domain-cells = <0>; - clocks = <&clks IMX6SL_CLK_LCDIF_AXI>, - <&clks IMX6SL_CLK_LCDIF_PIX>, - <&clks IMX6SL_CLK_EPDC_AXI>, - <&clks IMX6SL_CLK_EPDC_PIX>, - <&clks IMX6SL_CLK_PXP_AXI>; - }; - }; - }; - - gpr: iomuxc-gpr@20e0000 { - compatible = "fsl,imx6sl-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x020e0000 0x38>; - }; - - iomuxc: pinctrl@20e0000 { - compatible = "fsl,imx6sl-iomuxc"; - reg = <0x020e0000 0x4000>; - }; - - csi: csi@20e4000 { - reg = <0x020e4000 0x4000>; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - spdc: spdc@20e8000 { - reg = <0x020e8000 0x4000>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; - }; - - sdma: sdma@20ec000 { - compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma"; - reg = <0x020ec000 0x4000>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SDMA>, - <&clks IMX6SL_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - /* imx6sl reuses imx6q sdma firmware */ - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - - pxp: pxp@20f0000 { - reg = <0x020f0000 0x4000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; - }; - - epdc: epdc@20f4000 { - reg = <0x020f4000 0x4000>; - interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; - }; - - lcdif: lcdif@20f8000 { - compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; - reg = <0x020f8000 0x4000>; - interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_LCDIF_PIX>, - <&clks IMX6SL_CLK_LCDIF_AXI>, - <&clks IMX6SL_CLK_DUMMY>; - clock-names = "pix", "axi", "disp_axi"; - status = "disabled"; - power-domains = <&pd_disp>; - }; - - dcp: crypto@20fc000 { - compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp"; - reg = <0x020fc000 0x4000>; - interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, - <0 100 IRQ_TYPE_LEVEL_HIGH>, - <0 101 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - aips2: bus@2100000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x02100000 0x100000>; - ranges; - - usbotg1: usb@2184000 { - compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; - reg = <0x02184000 0x200>; - interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbotg2: usb@2184200 { - compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; - reg = <0x02184200 0x200>; - interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBOH3>; - fsl,usbphy = <&usbphy2>; - fsl,usbmisc = <&usbmisc 1>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbh: usb@2184400 { - compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; - reg = <0x02184400 0x200>; - interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBOH3>; - fsl,usbphy = <&usbphynop1>; - phy_type = "hsic"; - fsl,usbmisc = <&usbmisc 2>; - dr_mode = "host"; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - status = "disabled"; - }; - - usbmisc: usbmisc@2184800 { - #index-cells = <1>; - compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; - clocks = <&clks IMX6SL_CLK_USBOH3>; - }; - - fec: ethernet@2188000 { - compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; - reg = <0x02188000 0x4000>; - interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_ENET>, - <&clks IMX6SL_CLK_ENET_REF>; - clock-names = "ipg", "ahb"; - status = "disabled"; - }; - - usdhc1: mmc@2190000 { - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; - reg = <0x02190000 0x4000>; - interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USDHC1>, - <&clks IMX6SL_CLK_USDHC1>, - <&clks IMX6SL_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: mmc@2194000 { - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; - reg = <0x02194000 0x4000>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USDHC2>, - <&clks IMX6SL_CLK_USDHC2>, - <&clks IMX6SL_CLK_USDHC2>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: mmc@2198000 { - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; - reg = <0x02198000 0x4000>; - interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USDHC3>, - <&clks IMX6SL_CLK_USDHC3>, - <&clks IMX6SL_CLK_USDHC3>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - usdhc4: mmc@219c000 { - compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; - reg = <0x0219c000 0x4000>; - interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USDHC4>, - <&clks IMX6SL_CLK_USDHC4>, - <&clks IMX6SL_CLK_USDHC4>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; - - i2c1: i2c@21a0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; - reg = <0x021a0000 0x4000>; - interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_I2C1>; - status = "disabled"; - }; - - i2c2: i2c@21a4000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; - reg = <0x021a4000 0x4000>; - interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_I2C2>; - status = "disabled"; - }; - - i2c3: i2c@21a8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; - reg = <0x021a8000 0x4000>; - interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_I2C3>; - status = "disabled"; - }; - - memory-controller@21b0000 { - compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; - clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>; - }; - - rngb: rngb@21b4000 { - compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb"; - reg = <0x021b4000 0x4000>; - interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_DUMMY>; - }; - - weim: weim@21b8000 { - #address-cells = <2>; - #size-cells = <1>; - reg = <0x021b8000 0x4000>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; - fsl,weim-cs-gpr = <&gpr>; - status = "disabled"; - }; - - ocotp: efuse@21bc000 { - compatible = "fsl,imx6sl-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6SL_CLK_OCOTP>; - #address-cells = <1>; - #size-cells = <1>; - - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; - - tempmon_calib: calib@38 { - reg = <0x38 4>; - }; - - tempmon_temp_grade: temp-grade@20 { - reg = <0x20 4>; - }; - }; - - audmux: audmux@21d8000 { - compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux"; - reg = <0x021d8000 0x4000>; - status = "disabled"; - }; - }; - - gpu_2d: gpu@2200000 { - compatible = "vivante,gc"; - reg = <0x02200000 0x4000>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, - <&clks IMX6SL_CLK_GPU2D_OVG>; - clock-names = "bus", "core"; - power-domains = <&pd_pu>; - }; - - gpu_vg: gpu@2204000 { - compatible = "vivante,gc"; - reg = <0x02204000 0x4000>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, - <&clks IMX6SL_CLK_GPU2D_OVG>; - clock-names = "bus", "core"; - power-domains = <&pd_pu>; - }; - }; -}; diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts index 6b9f40e5558..0912b953db0 100644 --- a/arch/arm/dts/k3-am625-r5-sk.dts +++ b/arch/arm/dts/k3-am625-r5-sk.dts @@ -83,3 +83,8 @@ reg = <0x00 0x0fc40000 0x00 0x100>, <0x00 0x60000000 0x00 0x08000000>; }; + +&main_pktdma { + ti,sci = <&dm_tifs>; + bootph-all; +}; diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts index f177f563527..4d6aab5ccc3 100644 --- a/arch/arm/dts/k3-am69-r5-sk.dts +++ b/arch/arm/dts/k3-am69-r5-sk.dts @@ -97,6 +97,12 @@ <0x0 0x58000000 0x0 0x8000000>; }; +&fss { + /* enable ranges missing from the FSS node */ + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>, + <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>; +}; + &mcu_ringacc { ti,sci = <&dm_tifs>; }; diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index fb7e2e50239..94760c78dd3 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -89,6 +89,12 @@ <0x0 0x50000000 0x0 0x8000000>; }; +&fss { + /* enable ranges missing from the FSS node */ + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>, + <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>; +}; + &mcu_ringacc { ti,sci = <&dm_tifs>; }; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index c7e344350c8..ce55ea6bae0 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -62,3 +62,9 @@ reg = <0x0 0x47050000 0x0 0x100>, <0x0 0x58000000 0x0 0x8000000>; }; + +&fss { + /* enable ranges missing from the FSS node */ + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>, + <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>; +}; diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts index 96a13b2cb2b..5470490e47b 100644 --- a/arch/arm/dts/k3-j721e-r5-sk.dts +++ b/arch/arm/dts/k3-j721e-r5-sk.dts @@ -57,3 +57,9 @@ reg = <0x0 0x47040000 0x0 0x100>, <0x0 0x50000000 0x0 0x8000000>; }; + +&fss { + /* enable ranges missing from the FSS node */ + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>, + <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>; +}; diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts index bef4573d3d2..d2c75229363 100644 --- a/arch/arm/dts/k3-j784s4-r5-evm.dts +++ b/arch/arm/dts/k3-j784s4-r5-evm.dts @@ -97,6 +97,12 @@ <0x0 0x58000000 0x0 0x8000000>; }; +&fss { + /* enable ranges missing from the FSS node */ + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>, + <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>; +}; + &mcu_ringacc { ti,sci = <&dm_tifs>; }; diff --git a/arch/arm/dts/nuvoton-npcm845-yosemite4-pincfg.dtsi b/arch/arm/dts/nuvoton-npcm845-yosemite4-pincfg.dtsi new file mode 100644 index 00000000000..0abe8b04446 --- /dev/null +++ b/arch/arm/dts/nuvoton-npcm845-yosemite4-pincfg.dtsi @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com + +/ { + pinctrl: pinctrl@f0800000 { + gpio234_pins: gpio234-pins { + pins = "GPIO234/PWM10/SMB20_SCL"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio61_pins: gpio61-pins { + pins = "GPIO61/SI1_nDTR_BOUT"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio46_pins: gpio46-pins { + pins = "GPIO46/SI1_nDSR/CP_TCK_SWCLK/TP_TCK_SWCLK/CP_TP_TCK_SWCLK"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio54_pins: gpio54-pins { + pins = "GPIO54/SI2_nDSR/BU4_TXD"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio55_pins: gpio55-pins { + pins = "GPIO55/SI2_RI2/BU4_RXD"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio121_pins: gpio121-pins { + pins = "GPIO121/SMB2C_SCL"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio108_pins: gpio108-pins { + pins = "GPIO108/SG1_MDC"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio109_pins: gpio109-pins { + pins = "GPIO109/SG1_MDIO"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio183_pins: gpio183-pins { + pins = "GPIO183/SPI3_SEL"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio184_pins: gpio184-pins { + pins = "GPIO184/SPI3_D0/STRAP13"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio189_pins: gpio189-pins { + pins = "GPIO189/SPI3_D3/SPI3_nCS3"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio92_pins: gpio92-pins { + pins = "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio35_pins: gpio35-pins { + pins = "GPI35/MCBPCK"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio36_pins: gpio36-pins { + pins = "GPI36/SYSBPCK"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio62_pins: gpio62-pins { + pins = "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio45_pins: gpio45-pins { + pins = "GPIO45/SI1_nDCD/CP_TMS_SWIO/TP_TMS_SWIO/CP_TP_TMS_SWIO"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio83_pins: gpio83-pins { + pins = "GPIO83/PWM3"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio144_pins: gpio144-pins { + pins = "GPIO144/PWM4"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio145_pins: gpio145-pins { + pins = "GPIO145/PWM5"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio146_pins: gpio146-pins { + pins = "GPIO146/PWM6"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio159_pins: gpio159-pins { + pins = "GPIO159/MMC_DT3"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio127_pins: gpio127-pins { + pins = "GPIO127/SMB1B_SCL/CP1_GPIO0"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + gpio15_pins: gpio15-pins { + pins = "GPIO15/GSPI_CS/SMB5C_SDA"; + bias-disable; + input-enable; + event-clear; + persist-enable; + }; + }; +}; diff --git a/arch/arm/dts/nuvoton-npcm845-yosemite4.dts b/arch/arm/dts/nuvoton-npcm845-yosemite4.dts new file mode 100644 index 00000000000..1a5d5035a09 --- /dev/null +++ b/arch/arm/dts/nuvoton-npcm845-yosemite4.dts @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2024 Nuvoton Technology + +/dts-v1/; + +#include <dt-bindings/phy/nuvoton,npcm-usbphy.h> +#include "nuvoton-npcm845.dtsi" +#include "nuvoton-npcm845-yosemite4-pincfg.dtsi" + +/ { + model = "Nuvoton npcm845 yosemite4"; + compatible = "nuvoton,npcm845"; + + aliases { + serial0 = &serial0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + ethernet3 = &gmac3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + i2c14 = &i2c14; + i2c15 = &i2c15; + i2c16 = &i2c16; + i2c17 = &i2c17; + i2c18 = &i2c18; + i2c19 = &i2c19; + i2c20 = &i2c20; + i2c21 = &i2c21; + i2c22 = &i2c22; + i2c23 = &i2c23; + i2c24 = &i2c24; + i2c25 = &i2c25; + i2c26 = &i2c26; + spi0 = &fiu0; + spi1 = &fiu1; + spi3 = &fiu3; + spi4 = &fiux; + spi5 = &pspi; + usb0 = &udc0; + usb1 = &ehci1; + usb2 = &udc8; + }; + + chosen { + stdout-path = &serial0; + }; + + memory { + reg = <0x0 0x0 0x0 0x40000000>; + }; + + tpm@0 { + compatible = "microsoft,ftpm"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + vsbr2: vsbr2 { + compatible = "regulator-npcm845"; + regulator-name = "vr2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vsbv8: vsbv8 { + compatible = "regulator-npcm845"; + regulator-name = "v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vsbv5: vsbv5 { + compatible = "regulator-npcm845"; + regulator-name = "v5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + +}; + +&serial0 { + status = "okay"; +}; + +&watchdog1 { + status = "okay"; +}; + +&fiu0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0cs1_pins>; + spi-nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + }; + spi_flash@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <25000000>; + }; +}; + +&fiu1 { + status = "okay"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + }; +}; + +&fiu3 { + pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>; + status = "okay"; + vqspi-supply = <&vsbv5>; + vqspi-microvolt = <3300000>; + spi-nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + }; +}; + +&fiux { + nuvoton,spix-mode; + status = "okay"; +}; + +&pspi { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; + +&usbphy3 { + status = "okay"; +}; + +&udc0 { + status = "okay"; + phys = <&usbphy1 NPCM_UDC0_7>; +}; + +&ehci1 { + status = "okay"; + phys = <&usbphy2 NPCM_USBH1>; +}; + +&udc8 { + status = "okay"; + phys = <&usbphy3 NPCM_UDC8>; +}; + +&rng { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&sha { + status = "okay"; +}; + +&otp { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < + &spix_pins + &r1_pins + &r1en_pins + &r1oen_pins + &r2_pins + &r2en_pins + &r2oen_pins + &gpio234_pins + &gpio61_pins + &gpio46_pins + &gpio54_pins + &gpio55_pins + &gpio121_pins + &gpio108_pins + &gpio109_pins + &gpio183_pins + &gpio184_pins + &gpio189_pins + &gpio92_pins + &gpio35_pins + &gpio36_pins + &gpio62_pins + &gpio45_pins + &gpio83_pins + &gpio144_pins + &gpio145_pins + &gpio146_pins + &gpio159_pins + &gpio127_pins + &gpio15_pins + >; +}; diff --git a/arch/arm/dts/omap3-evm-37xx.dts b/arch/arm/dts/omap3-evm-37xx.dts deleted file mode 100644 index abd403c228c..00000000000 --- a/arch/arm/dts/omap3-evm-37xx.dts +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "omap36xx.dtsi" -#include "omap3-evm-common.dtsi" -#include "omap3-evm-processor-common.dtsi" - -/ { - model = "TI OMAP37XX EVM (TMDSEVM3730)"; - compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3"; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_2_pins>; - - ehci_phy_pins: pinmux_ehci_phy_pins { - pinctrl-single,pins = < - - /* EHCI PHY reset GPIO etk_d7.gpio_21 */ - OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) - - /* EHCI VBUS etk_d8.gpio_22 */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) - >; - }; - - /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - - /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) - - /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) - - /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d15.hsusb2_data1 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) - >; - }; -}; - -&gpmc { - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "hynix,h8kds0un0mer-4em"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x280000 0x500000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x780000 0x1f880000>; - }; - }; -}; diff --git a/arch/arm/dts/omap3-evm-common.dtsi b/arch/arm/dts/omap3-evm-common.dtsi deleted file mode 100644 index 17c89df6ce6..00000000000 --- a/arch/arm/dts/omap3-evm-common.dtsi +++ /dev/null @@ -1,198 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common support for omap3 EVM boards - */ - -#include <dt-bindings/input/input.h> -#include "omap-gpmc-smsc911x.dtsi" - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; /* gpio_22 */ - startup-delay-us = <70000>; - enable-active-high; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ - vcc-supply = <&hsusb2_power>; - #phy-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - ledb { - label = "omap3evm::ledb"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ - linux,default-trigger = "default-on"; - }; - }; - - wl12xx_vmmc: wl12xx_vmmc { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* gpio150 */ - startup-delay-us = <70000>; - enable-active-high; - vin-supply = <&vmmc2>; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" -#include "omap3-panel-sharp-ls037v7dw01.dtsi" - -&backlight0 { - gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; -}; - -&twl { - twl_power: power { - compatible = "ti,twl4030-power-omap3-evm", "ti,twl4030-power-idle"; - ti,use_poweroff; - }; -}; - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; - - /* - * TVP5146 Video decoder-in for analog input support. - */ - tvp5146@5c { - compatible = "ti,tvp5146m2"; - reg = <0x5c>; - }; -}; - -&lcd_3v3 { - gpio = <&gpio5 25 GPIO_ACTIVE_LOW>; /* gpio153 */ -}; - -&lcd0 { - enable-gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; /* gpio152, lcd INI */ - reset-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd RESB */ - mode-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH /* gpio154, lcd MO */ - &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */ - &gpio1 3 GPIO_ACTIVE_HIGH>; /* gpio3, lcd UD */ -}; - -&mcspi1 { - tsc2046@0 { - interrupt-parent = <&gpio6>; - interrupts = <15 0>; /* gpio175 */ - pendown-gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - }; -}; - -&mmc1 { - interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; - vmmc-supply = <&vmmc1>; - vqmmc-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - interrupts-extended = <&intc 86 &omap3_pmx_core 0x12e>; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - /* gpio_149 with uart1_rts pad as wakeirq */ - interrupts-extended = <&gpio5 21 IRQ_TYPE_EDGE_RISING>, - <&omap3_pmx_core 0x14e>; - interrupt-names = "irq", "wakeup"; - ref-clock-frequency = <38400000>; - }; -}; - -&twl_gpio { - ti,use-leds; -}; - -&twl_keypad { - linux,keymap = < - MATRIX_KEY(2, 2, KEY_1) - MATRIX_KEY(1, 1, KEY_2) - MATRIX_KEY(0, 0, KEY_3) - MATRIX_KEY(3, 2, KEY_4) - MATRIX_KEY(2, 1, KEY_5) - MATRIX_KEY(1, 0, KEY_6) - MATRIX_KEY(1, 3, KEY_7) - MATRIX_KEY(3, 1, KEY_8) - MATRIX_KEY(2, 0, KEY_9) - MATRIX_KEY(2, 3, KEY_KPASTERISK) - MATRIX_KEY(0, 2, KEY_0) - MATRIX_KEY(3, 0, KEY_KPDOT) - /* s4 not wired */ - MATRIX_KEY(1, 2, KEY_BACKSPACE) - MATRIX_KEY(0, 1, KEY_ENTER) - >; -}; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&gpmc { - ethernet@gpmc { - interrupt-parent = <&gpio6>; - interrupts = <16 8>; - reg = <5 0 0xff>; - }; -}; - -&vaux2 { - regulator-name = "usb_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; -}; diff --git a/arch/arm/dts/omap3-evm-processor-common.dtsi b/arch/arm/dts/omap3-evm-processor-common.dtsi deleted file mode 100644 index e6ba30a2116..00000000000 --- a/arch/arm/dts/omap3-evm-processor-common.dtsi +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Common support for omap3 EVM 35xx/37xx processor modules - */ - -/ { - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - wl12xx_vmmc: wl12xx_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - }; -}; - -&dss { - vdds_dsi-supply = <&vpll2>; - vdda_video-supply = <&lcd_3v3>; - pinctrl-names = "default"; - pinctrl-0 = < - &dss_dpi_pins1 - &dss_dpi_pins2 - >; -}; - -&hsusb2_phy { - pinctrl-names = "default"; - pinctrl-0 = <&ehci_phy_pins>; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; - - dss_dpi_pins1: pinmux_dss_dpi_pins2 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ - OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ - OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ - OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ - >; - }; - - /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ - >; - }; - - /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */ - on_board_gpio_61: pinmux_ehci_port_select_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) - >; - }; - - /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - - /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* mcspi2_cs1.hsusb2_data3 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) - >; - }; - - /* - * Note that gpio_150 pulled high with internal pull to prevent wlcore - * reset on return from off mode in idle. - */ - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_cts.gpio_150 */ - OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ - >; - }; - - smsc911x_pins: pinmux_smsc911x_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ - >; - }; -}; - -&omap3_pmx_wkup { - dss_dpi_pins2: pinmux_dss_dpi_pins1 { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ - OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ - OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ - >; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart1 { - interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; -}; - -&uart2 { - interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; -}; - -&uart3 { - interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -/* - * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface - * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. - */ -&gpio2 { - en-usb2-port-hog { - gpio-hog; - gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ - output-low; - line-name = "enable usb2 port"; - }; -}; - -/* T2_GPIO_2 low to route GPIO_61 to on-board devices */ -&twl_gpio { - en_on_board_gpio_61 { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "en_hsusb2_clk"; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ - <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for LAN9220 */ - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&smsc911x_pins>; - }; -}; diff --git a/arch/arm/dts/omap3-evm.dts b/arch/arm/dts/omap3-evm.dts deleted file mode 100644 index f95eea63b35..00000000000 --- a/arch/arm/dts/omap3-evm.dts +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "omap34xx.dtsi" -#include "omap3-evm-common.dtsi" -#include "omap3-evm-processor-common.dtsi" - -/ { - model = "TI OMAP35XX EVM (TMDSEVM3530)"; - compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_2_pins>; - - ehci_phy_pins: pinmux_ehci_phy_pins { - pinctrl-single,pins = < - - /* EHCI PHY reset GPIO etk_d7.gpio_21 */ - OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) - - /* EHCI VBUS etk_d8.gpio_22 */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) - >; - }; - - /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - - /* etk_d10.hsusb2_clk */ - OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) - - /* etk_d11.hsusb2_stp */ - OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) - - /* etk_d12.hsusb2_dir */ - OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d13.hsusb2_nxt */ - OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d14.hsusb2_data0 */ - OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) - - /* etk_d15.hsusb2_data1 */ - OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) - >; - }; -}; - -&gpmc { - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "micron,mt29f2g16abdhc"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - }; -}; diff --git a/arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi b/arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi deleted file mode 100644 index 2dbb687d4df..00000000000 --- a/arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common file for omap dpi panels with QVGA and reset pins - * - * Note that the board specifc DTS file needs to specify - * at minimum the GPIO enable-gpios for display, and - * gpios for gpio-backlight. - */ - -/ { - aliases { - display0 = &lcd0; - }; - - backlight0: backlight { - compatible = "gpio-backlight"; - default-on; - }; - - /* 3.3V GPIO controlled regulator for LCD_ENVDD */ - lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <70000>; - }; - - lcd0: display { - compatible = "sharp,ls037v7dw01"; - label = "lcd"; - power-supply = <&lcd_3v3>; - envdd-supply = <&lcd_3v3>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "okay"; - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <18>; - }; - }; -}; - -&mcspi1 { - tsc2046@0 { - reg = <0>; /* CS0 */ - compatible = "ti,tsc2046"; - spi-max-frequency = <1000000>; - vcc-supply = <&lcd_3v3>; - ti,x-min = /bits/ 16 <0>; - ti,x-max = /bits/ 16 <8000>; - ti,y-min = /bits/ 16 <0>; - ti,y-max = /bits/ 16 <4800>; - ti,x-plate-ohms = /bits/ 16 <40>; - ti,pressure-max = /bits/ 16 <255>; - ti,swap-xy; - wakeup-source; - }; -}; diff --git a/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi b/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi new file mode 100644 index 00000000000..fbe72595f5a --- /dev/null +++ b/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Linaro Ltd. + */ +/ { + /* When running as the primary bootloader there is no prior + * stage to populate the memory layout for us. We *should* + * have two nodes here, but ABL does NOT like that. + * sooo we're stuck with this. + */ + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x3A800000>, + <0 0xC0000000 0 0x01800000>, + <0 0xC3400000 0 0x3CC00000>, + <1 0x00000000 1 0x00000000>; + }; +}; + +&usb_1_dwc3 { + dr_mode = "host"; + /delete-property/ usb-role-switch; +}; + +// RAM Entry 0 : Base 0x0080000000 Size 0x003A800000 +// RAM Entry 1 : Base 0x00C0000000 Size 0x0001800000 +// RAM Entry 2 : Base 0x00C3400000 Size 0x003CC00000 +// RAM Entry 3 : Base 0x0100000000 Size 0x0100000000 diff --git a/arch/arm/include/asm/arch-rockchip/timer.h b/arch/arm/include/asm/arch-rockchip/timer.h index 77b54220447..b5fc738c98c 100644 --- a/arch/arm/include/asm/arch-rockchip/timer.h +++ b/arch/arm/include/asm/arch-rockchip/timer.h @@ -15,4 +15,7 @@ struct rk_timer { u32 timer_int_status; }; +/** rockchip_stimer_init() - Set up the timer ready for use */ +void rockchip_stimer_init(void); + #endif diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index a29b849d903..d4ac567e7ed 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -26,6 +26,7 @@ #define ELE_GET_EVENTS_REQ (0xA2) #define ELE_COMMIT_REQ (0xA8) #define ELE_START_RNG (0xA3) +#define ELE_CMD_DERIVE_KEY (0xA9) #define ELE_GENERATE_DEK_BLOB (0xAF) #define ELE_ENABLE_PATCH_REQ (0xC3) #define ELE_RELEASE_RDC_REQ (0xC4) @@ -143,6 +144,7 @@ int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respon int ele_release_caam(u32 core_did, u32 *response); int ele_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response); int ele_get_events(u32 *events, u32 *events_cnt, u32 *response); +int ele_derive_huk(u8 *key, size_t key_size, u8 *ctx, size_t seed_size); int ele_commit(u16 fuse_id, u32 *response, u32 *info_type); int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_output_size); int ele_dump_buffer(u32 *buffer, u32 buffer_length); diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 7e30cac32a0..2237d7d0066 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -277,6 +277,16 @@ void protect_secure_region(void); void smp_kick_all_cpus(void); void flush_l3_cache(void); + +/** + * mmu_map_region() - map a region of previously unmapped memory. + * Will be mapped MT_NORMAL & PTE_BLOCK_INNER_SHARE. + * + * @start: Start address of the region + * @size: Size of the region + * @emerg: Also map the region in the emergency table + */ +void mmu_map_region(phys_addr_t start, u64 size, bool emerg); void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs); /* diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c index 7c49462c8eb..c7fff01c435 100644 --- a/arch/arm/lib/bdinfo.c +++ b/arch/arm/lib/bdinfo.c @@ -58,7 +58,7 @@ void arch_print_bdinfo(void) printf("Board Type = %ld\n", gd->board_type); #endif #if CONFIG_IS_ENABLED(SYS_MALLOC_F) - printf("Early malloc usage: %lx / %x\n", gd->malloc_ptr, + printf("Early malloc usage: %x / %x\n", gd->malloc_ptr, CONFIG_VAL(SYS_MALLOC_F_LEN)); #endif } diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c index ea1b937add7..2b21ec0734e 100644 --- a/arch/arm/lib/stack.c +++ b/arch/arm/lib/stack.c @@ -11,7 +11,6 @@ * Marius Groeger <mgroeger@sysgo.de> */ #include <init.h> -#include <lmb.h> #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; @@ -33,16 +32,3 @@ int arch_reserve_stacks(void) return 0; } - -static ulong get_sp(void) -{ - ulong ret; - - asm("mov %0, sp" : "=r"(ret) : ); - return ret; -} - -void arch_lmb_reserve(struct lmb *lmb) -{ - arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 16384); -} diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 8bace3005eb..0b6d290b8ac 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -773,23 +773,20 @@ u64 get_page_table_size(void) int board_late_init(void) { - struct lmb lmb; u32 status = 0; - lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); - /* somewhat based on the Linux Kernel boot requirements: * align by 2M and maximal FDT size 2M */ - status |= env_set_hex("loadaddr", lmb_alloc(&lmb, SZ_1G, SZ_2M)); - status |= env_set_hex("fdt_addr_r", lmb_alloc(&lmb, SZ_2M, SZ_2M)); - status |= env_set_hex("kernel_addr_r", lmb_alloc(&lmb, SZ_128M, SZ_2M)); - status |= env_set_hex("ramdisk_addr_r", lmb_alloc(&lmb, SZ_1G, SZ_2M)); + status |= env_set_hex("loadaddr", lmb_alloc(SZ_1G, SZ_2M)); + status |= env_set_hex("fdt_addr_r", lmb_alloc(SZ_2M, SZ_2M)); + status |= env_set_hex("kernel_addr_r", lmb_alloc(SZ_128M, SZ_2M)); + status |= env_set_hex("ramdisk_addr_r", lmb_alloc(SZ_1G, SZ_2M)); status |= env_set_hex("kernel_comp_addr_r", - lmb_alloc(&lmb, KERNEL_COMP_SIZE, SZ_2M)); + lmb_alloc(KERNEL_COMP_SIZE, SZ_2M)); status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE); - status |= env_set_hex("scriptaddr", lmb_alloc(&lmb, SZ_4M, SZ_2M)); - status |= env_set_hex("pxefile_addr_r", lmb_alloc(&lmb, SZ_4M, SZ_2M)); + status |= env_set_hex("scriptaddr", lmb_alloc(SZ_4M, SZ_2M)); + status |= env_set_hex("pxefile_addr_r", lmb_alloc(SZ_4M, SZ_2M)); if (status) log_warning("late_init: Failed to set run time variables\n"); diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 8a8ac53e4f8..7c4ccc427c8 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -11,10 +11,6 @@ config AT91SAM9G20 bool select CPU_ARM926EJS -config AT91SAM9XE - bool - select CPU_ARM926EJS - config AT91SAM9261 bool select CPU_ARM926EJS @@ -75,10 +71,6 @@ config TARGET_AT91SAM9260EK select AT91SAM9260 select BOARD_EARLY_INIT_F -config TARGET_ETHERNUT5 - bool "Ethernut5 board" - select AT91SAM9XE - config TARGET_GURNARD bool "Support gurnard" select AT91SAM9G45 @@ -340,21 +332,6 @@ config AT91RESET_EXTRST config SYS_SOC default "at91" -config AT91_EFLASH - bool "Support AT91 flash driver" - depends on AT91SAM9XE - select USE_SYS_MAX_FLASH_BANKS - help - Enable the driver for the embedded flash used in the Atmel - AT91SAM9XE devices. - -config EFLASH_PROTSECTORS - int "Number of flash sectors to protect from erasing" - depends on AT91_EFLASH - help - If non-zero, this will be the number of sectors of the flash to disallow - U-Boot to ease, starting from the beginning of flash. - config AT91_GPIO_PULLUP bool "Keep pullups on peripheral pins" depends on CPU_ARM926EJS @@ -389,7 +366,6 @@ source "board/atmel/sama5d4ek/Kconfig" source "board/bluewater/gurnard/Kconfig" source "board/calao/usb_a9263/Kconfig" source "board/conclusive/kstr-sama5d27/Kconfig" -source "board/egnite/ethernut5/Kconfig" source "board/esd/meesc/Kconfig" source "board/gardena/smart-gateway-at91sam/Kconfig" source "board/l+g/vinco/Kconfig" diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile index 902dd3a60e3..a8916862b3f 100644 --- a/arch/arm/mach-at91/arm926ejs/Makefile +++ b/arch/arm/mach-at91/arm926ejs/Makefile @@ -5,7 +5,6 @@ obj-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o obj-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o -obj-$(CONFIG_AT91SAM9XE) += at91sam9260_devices.o obj-$(CONFIG_AT91SAM9261) += at91sam9261_devices.o obj-$(CONFIG_AT91SAM9G10) += at91sam9261_devices.o obj-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o @@ -15,7 +14,6 @@ obj-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o obj-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o obj-$(CONFIG_SAM9X60) += sam9x60_devices.o -obj-$(CONFIG_AT91_EFLASH) += eflash.o obj-y += clock.o obj-y += cpu.o ifndef CONFIG_$(SPL_TPL_)SYSRESET diff --git a/arch/arm/mach-at91/arm926ejs/eflash.c b/arch/arm/mach-at91/arm926ejs/eflash.c deleted file mode 100644 index bb66700566e..00000000000 --- a/arch/arm/mach-at91/arm926ejs/eflash.c +++ /dev/null @@ -1,255 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de - */ - -/* - * this driver supports the enhanced embedded flash in the Atmel - * AT91SAM9XE devices with the following geometry: - * - * AT91SAM9XE128: 1 plane of 8 regions of 32 pages (total 256 pages) - * AT91SAM9XE256: 1 plane of 16 regions of 32 pages (total 512 pages) - * AT91SAM9XE512: 1 plane of 32 regions of 32 pages (total 1024 pages) - * (the exact geometry is read from the flash at runtime, so any - * future devices should already be covered) - * - * Regions can be write/erase protected. - * Whole (!) pages can be individually written with erase on the fly. - * Writing partial pages will corrupt the rest of the page. - * - * The flash is presented to u-boot with each region being a sector, - * having the following effects: - * Each sector can be hardware protected (protect on/off). - * Each page in a sector can be rewritten anytime. - * Since pages are erased when written, the "erase" does nothing. - * The first "CONFIG_EFLASH_PROTSECTORS" cannot be unprotected - * by u-Boot commands. - * - * Note: Redundant environment will not work in this flash since - * it does use partial page writes. Make sure the environment spans - * whole pages! - */ - -/* - * optional TODOs (nice to have features): - * - * make the driver coexist with other NOR flash drivers - * (use an index into flash_info[], requires work - * in those other drivers, too) - * Make the erase command fill the sectors with 0xff - * (if the flashes grow larger in the future and - * someone puts a jffs2 into them) - * do a read-modify-write for partially programmed pages - */ -#include <display_options.h> -#include <flash.h> -#include <log.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/at91_eefc.h> -#include <asm/arch/at91_dbu.h> - -/* checks to detect configuration errors */ -#if CONFIG_SYS_MAX_FLASH_BANKS!=1 -#error eflash: this driver can only handle 1 bank -#endif - -/* global structure */ -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; -static u32 pagesize; - -unsigned long flash_init(void) -{ - at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC; - at91_dbu_t *dbu = (at91_dbu_t *) ATMEL_BASE_DBGU; - u32 id, size, nplanes, planesize, nlocks; - u32 addr, i, tmp=0; - - debug("eflash: init\n"); - - flash_info[0].flash_id = FLASH_UNKNOWN; - - /* check if its an AT91ARM9XE SoC */ - if ((readl(&dbu->cidr) & AT91_DBU_CID_ARCH_MASK) != AT91_DBU_CID_ARCH_9XExx) { - puts("eflash: not an AT91SAM9XE\n"); - return 0; - } - - /* now query the eflash for its structure */ - writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GETD, &eefc->fcr); - while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) - ; - id = readl(&eefc->frr); /* word 0 */ - size = readl(&eefc->frr); /* word 1 */ - pagesize = readl(&eefc->frr); /* word 2 */ - nplanes = readl(&eefc->frr); /* word 3 */ - planesize = readl(&eefc->frr); /* word 4 */ - debug("id=%08x size=%u pagesize=%u planes=%u planesize=%u\n", - id, size, pagesize, nplanes, planesize); - for (i=1; i<nplanes; i++) { - tmp = readl(&eefc->frr); /* words 5..4+nplanes-1 */ - }; - nlocks = readl(&eefc->frr); /* word 4+nplanes */ - debug("nlocks=%u\n", nlocks); - /* since we are going to use the lock regions as sectors, check count */ - if (nlocks > CONFIG_SYS_MAX_FLASH_SECT) { - printf("eflash: number of lock regions(%u) "\ - "> CONFIG_SYS_MAX_FLASH_SECT. reducing...\n", - nlocks); - nlocks = CONFIG_SYS_MAX_FLASH_SECT; - } - flash_info[0].size = size; - flash_info[0].sector_count = nlocks; - flash_info[0].flash_id = id; - - addr = ATMEL_BASE_FLASH; - for (i=0; i<nlocks; i++) { - tmp = readl(&eefc->frr); /* words 4+nplanes+1.. */ - flash_info[0].start[i] = addr; - flash_info[0].protect[i] = 0; - addr += tmp; - }; - - /* now read the protection information for all regions */ - writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr); - while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) - ; - for (i=0; i<flash_info[0].sector_count; i++) { - if (i%32 == 0) - tmp = readl(&eefc->frr); - flash_info[0].protect[i] = (tmp >> (i%32)) & 1; -#if CONFIG_VAL(EFLASH_PROTSECTORS) - if (i < CONFIG_EFLASH_PROTSECTORS) - flash_info[0].protect[i] = 1; -#endif - } - - return size; -} - -void flash_print_info(flash_info_t *info) -{ - int i; - - puts("AT91SAM9XE embedded flash\n Size: "); - print_size(info->size, " in "); - printf("%d Sectors\n", info->sector_count); - - printf(" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -int flash_real_protect (flash_info_t *info, long sector, int prot) -{ - at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC; - u32 pagenum = (info->start[sector]-ATMEL_BASE_FLASH)/pagesize; - u32 i, tmp=0; - - debug("protect sector=%ld prot=%d\n", sector, prot); - -#if CONFIG_VAL(EFLASH_PROTSECTORS) - if (sector < CONFIG_EFLASH_PROTSECTORS) { - if (!prot) { - printf("eflash: sector %lu cannot be unprotected\n", - sector); - } - return 1; /* return anyway, caller does not care for result */ - } -#endif - if (prot) { - writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_SLB | - (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); - } else { - writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_CLB | - (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); - } - while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) - ; - /* now re-read the protection information for all regions */ - writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr); - while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) - ; - for (i=0; i<info->sector_count; i++) { - if (i%32 == 0) - tmp = readl(&eefc->frr); - info->protect[i] = (tmp >> (i%32)) & 1; - } - return 0; -} - -static u32 erase_write_page (u32 pagenum) -{ - at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC; - - debug("erase+write page=%u\n", pagenum); - - /* give erase and write page command */ - writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_EWP | - (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); - while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) - ; - /* return status */ - return readl(&eefc->fsr) - & (AT91_EEFC_FSR_FCMDE | AT91_EEFC_FSR_FLOCKE); -} - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - debug("erase first=%d last=%d\n", s_first, s_last); - puts("this flash does not need and support erasing!\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - */ - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - u32 pagenum; - u32 *src32, *dst32; - u32 i; - - debug("write src=%08lx addr=%08lx cnt=%lx\n", - (ulong)src, addr, cnt); - - /* REQUIRE addr to be on a page start, abort if not */ - if (addr % pagesize) { - printf ("eflash: start %08lx is not on page start\n"\ - " write aborted\n", addr); - return 1; - } - - /* now start copying data */ - pagenum = (addr-ATMEL_BASE_FLASH)/pagesize; - src32 = (u32 *) src; - dst32 = (u32 *) addr; - while (cnt > 0) { - i = pagesize / 4; - /* fill page buffer */ - while (i--) - *dst32++ = *src32++; - /* write page */ - if (erase_write_page(pagenum)) - return 1; - pagenum++; - if (cnt > pagesize) - cnt -= pagesize; - else - cnt = 0; - } - return 0; -} diff --git a/arch/arm/mach-at91/include/mach/at91_dbu.h b/arch/arm/mach-at91/include/mach/at91_dbu.h deleted file mode 100644 index 91bb686bc10..00000000000 --- a/arch/arm/mach-at91/include/mach/at91_dbu.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - * - * Debug Unit - * Based on AT91SAM9XE datasheet - */ - -#ifndef AT91_DBU_H -#define AT91_DBU_H - -#ifndef __ASSEMBLY__ - -typedef struct at91_dbu { - u32 cr; /* Control Register WO */ - u32 mr; /* Mode Register RW */ - u32 ier; /* Interrupt Enable Register WO */ - u32 idr; /* Interrupt Disable Register WO */ - u32 imr; /* Interrupt Mask Register RO */ - u32 sr; /* Status Register RO */ - u32 rhr; /* Receive Holding Register RO */ - u32 thr; /* Transmit Holding Register WO */ - u32 brgr; /* Baud Rate Generator Register RW */ - u32 res1[7];/* 0x0024 - 0x003C Reserved */ - u32 cidr; /* Chip ID Register RO */ - u32 exid; /* Chip ID Extension Register RO */ - u32 fnr; /* Force NTRST Register RW */ -} at91_dbu_t; - -#endif /* __ASSEMBLY__ */ - -#define AT91_DBU_CID_ARCH_MASK 0x0ff00000 -#define AT91_DBU_CID_ARCH_9xx 0x01900000 -#define AT91_DBU_CID_ARCH_9XExx 0x02900000 - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_eefc.h b/arch/arm/mach-at91/include/mach/at91_eefc.h deleted file mode 100644 index e7bb2bfecba..00000000000 --- a/arch/arm/mach-at91/include/mach/at91_eefc.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - * - * Enhanced Embedded Flash Controller - * Based on AT91SAM9XE datasheet - */ - -#ifndef AT91_EEFC_H -#define AT91_EEFC_H - -#ifndef __ASSEMBLY__ - -typedef struct at91_eefc { - u32 fmr; /* Flash Mode Register RW */ - u32 fcr; /* Flash Command Register WO */ - u32 fsr; /* Flash Status Register RO */ - u32 frr; /* Flash Result Register RO */ -} at91_eefc_t; - -#endif /* __ASSEMBLY__ */ - -#define AT91_EEFC_FMR_FWS_MASK 0x00000f00 -#define AT91_EEFC_FMR_FRDY_BIT 0x00000001 - -#define AT91_EEFC_FCR_KEY 0x5a000000 -#define AT91_EEFC_FCR_FARG_MASK 0x00ffff00 -#define AT91_EEFC_FCR_FARG_SHIFT 8 -#define AT91_EEFC_FCR_FCMD_GETD 0x0 -#define AT91_EEFC_FCR_FCMD_WP 0x1 -#define AT91_EEFC_FCR_FCMD_WPL 0x2 -#define AT91_EEFC_FCR_FCMD_EWP 0x3 -#define AT91_EEFC_FCR_FCMD_EWPL 0x4 -#define AT91_EEFC_FCR_FCMD_EA 0x5 -#define AT91_EEFC_FCR_FCMD_SLB 0x8 -#define AT91_EEFC_FCR_FCMD_CLB 0x9 -#define AT91_EEFC_FCR_FCMD_GLB 0xA -#define AT91_EEFC_FCR_FCMD_SGPB 0xB -#define AT91_EEFC_FCR_FCMD_CGPB 0xC -#define AT91_EEFC_FCR_FCMD_GGPB 0xD - -#define AT91_EEFC_FSR_FRDY 1 -#define AT91_EEFC_FSR_FCMDE 2 -#define AT91_EEFC_FSR_FLOCKE 4 - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index 103db269533..bdd46ee0eae 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -7,7 +7,7 @@ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de * * Definitions for the SoCs: - * AT91SAM9260, AT91SAM9G20, AT91SAM9XE + * AT91SAM9260, AT91SAM9G20 * * Note that those SoCs are mostly software and pin compatible, * therefore this file applies to all of them. Differences between @@ -142,15 +142,7 @@ /* * SoC specific defines */ -#if defined(CONFIG_AT91SAM9XE) -# define ATMEL_CPU_NAME "AT91SAM9XE" -# define ATMEL_ID_TWI1 25 /* TWI 1 */ -# define ATMEL_BASE_FLASH 0x00200000 /* Internal FLASH */ -# define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM */ -# define ATMEL_BASE_TWI1 0xfffd8000 -# define ATMEL_BASE_EEFC 0xfffffa00 -# define ATMEL_BASE_GPBR 0xfffffd60 -#elif defined(CONFIG_AT91SAM9260) +#if defined(CONFIG_AT91SAM9260) # define ATMEL_CPU_NAME "AT91SAM9260" # define ATMEL_ID_USART5 25 /* USART 5 */ # define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */ diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index 0a16c8ff088..988ef492b62 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -9,8 +9,7 @@ #if defined(CONFIG_AT91RM9200) # include <asm/arch/at91rm9200.h> -#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) || \ - defined(CONFIG_AT91SAM9XE) +#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) # include <asm/arch/at91sam9260.h> #elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) # include <asm/arch/at91sam9261.h> diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c index bd5a06447b9..219d7fbf957 100644 --- a/arch/arm/mach-exynos/spl_boot.c +++ b/arch/arm/mach-exynos/spl_boot.c @@ -312,7 +312,7 @@ static void setup_global_data(gd_t *gdp) memzero((void *)gd, sizeof(gd_t)); gd->flags |= GD_FLG_RELOC; gd->baudrate = CONFIG_BAUDRATE; - gd->have_console = 1; + gd->flags |= GD_FLG_HAVE_CONSOLE; } void board_init_f(unsigned long bootflag) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index c34bc25c0bf..134e42028c3 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -1,6 +1,8 @@ config MACH_IMX bool +if MACH_IMX + config HAS_CAAM bool @@ -200,3 +202,5 @@ config IOMUX_LPSR config IOMUX_SHARE_CONF_REG bool + +endif diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index b311d176d64..5262dca4ffd 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -217,8 +217,8 @@ endif ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y) -quiet_cmd_imx9_check = CHECK $@ -cmd_imx9_check = $(srctree)/tools/imx9_image.sh $@ +quiet_cmd_cpp_cfg_imx9_check = CHECK $@ +cmd_cpp_cfg_imx9_check = $(CPP) $(cpp_flags) -D__ASSEMBLY__ -x c -o $@ $< && $(srctree)/tools/imx9_image.sh $@ SPL: spl/u-boot-spl.bin spl/u-boot-spl.cfgout u-boot-container.cfgout FORCE @@ -227,15 +227,13 @@ flash.bin: MKIMAGEOUTPUT = flash.log spl/u-boot-spl.cfgout: $(IMX_CONFIG) FORCE $(Q)mkdir -p $(dir $@) - $(call if_changed_dep,cpp_cfg) - $(call if_changed,imx9_check) + $(call if_changed_dep,cpp_cfg_imx9_check) spl/u-boot-spl-ddr.bin: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE u-boot-container.cfgout: $(IMX_CONTAINER_CFG) FORCE $(Q)mkdir -p $(dir $@) - $(call if_changed_dep,cpp_cfg) - $(call if_changed,imx9_check) + $(call if_changed_dep,cpp_cfg_imx9_check) flash.bin: spl/u-boot-spl-ddr.bin container.cfgout FORCE $(call if_changed,mkimage) diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index c13d9f0e00e..647daeb6562 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -624,6 +624,31 @@ static int do_ahab_return_lifecycle(struct cmd_tbl *cmdtp, int flag, int argc, c return CMD_RET_SUCCESS; } +static int do_ahab_derive(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong key; + size_t key_size; + char seed[] = "_ELE_AHAB_SEED_"; + + if (argc != 3) + return CMD_RET_USAGE; + + key = hextoul(argv[1], NULL); + key_size = simple_strtoul(argv[2], NULL, 10); + if (key_size != 16 && key_size != 32) { + printf("key size can only be 16 or 32\n"); + return CMD_RET_FAILURE; + } + + if (ele_derive_huk((u8 *)key, key_size, seed, sizeof(seed))) { + printf("Error in AHAB derive\n"); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + static int do_ahab_commit(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -680,6 +705,12 @@ U_BOOT_CMD(ahab_return_lifecycle, CONFIG_SYS_MAXARGS, 1, do_ahab_return_lifecycl "addr - Return lifecycle message block signed by OEM SRK\n" ); +U_BOOT_CMD(ahab_derive, CONFIG_SYS_MAXARGS, 3, do_ahab_derive, + "Derive the hardware unique key", + "addr [16|32]\n" + "Store at addr the derivation of the HUK on 16 or 32 bytes.\n" +); + U_BOOT_CMD(ahab_commit, CONFIG_SYS_MAXARGS, 1, do_ahab_commit, "commit into the fuses any new SRK revocation and FW version information\n" "that have been found into the NXP (ELE FW) and OEM containers", diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index e2388e3fef8..2afe9d38a06 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -205,7 +205,7 @@ static unsigned long get_boot_device_offset(void *dev, int dev_type) } else { u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); - if (part == 1 || part == 2) { + if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2) { if (is_imx8qxp() && is_soc_rev(CHIP_REV_B)) offset = CONTAINER_HDR_MMCSD_OFFSET; else @@ -294,15 +294,15 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc) int part; part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); - if (part == 1 || part == 2) { + if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2) { unsigned long sec_set_off = 0; bool sec_boot = false; sec_boot = check_secondary_cnt_set(&sec_set_off); if (sec_boot) - part = (part == 1) ? 2 : 1; - } else if (part == 7) { - part = 0; + part = (part == EMMC_BOOT_PART_BOOT1) ? EMMC_HWPART_BOOT2 : EMMC_HWPART_BOOT1; + } else if (part == EMMC_BOOT_PART_USER) { + part = EMMC_HWPART_DEFAULT; } return part; diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index de630e940c9..d7fd102c955 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -181,10 +181,19 @@ void dram_disable_bypass(void) } #endif -int intpll_configure(enum pll_clocks pll, ulong freq) +__weak int board_imx_intpll_override(enum pll_clocks pll, ulong *freq) +{ + return 0; +} + +static int intpll_configure(enum pll_clocks pll, ulong freq) { void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl; u32 pll_div_ctl_val, pll_clke_masks; + int ret = board_imx_intpll_override(pll, &freq); + + if (ret) + return ret; switch (pll) { case ANATOP_SYSTEM_PLL1: diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index be38ca52885..986687e9ce4 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -32,6 +32,7 @@ #include <imx_sip.h> #include <linux/bitops.h> #include <linux/bitfield.h> +#include <linux/sizes.h> DECLARE_GLOBAL_DATA_PTR; @@ -206,6 +207,14 @@ void enable_caches(void) int entry = imx8m_find_dram_entry_in_mem_map(); u64 attrs = imx8m_mem_map[entry].attrs; + /* Deactivate the data cache, possibly enabled in arch_cpu_init() */ + dcache_disable(); + /* + * Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr + * to update the TLB location udpated in board_f.c::reserve_mmu + */ + gd->arch.tlb_fillptr = 0; + while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx8m_mem_map)) { if (gd->bd->bi_dram[i].start == 0) @@ -587,12 +596,50 @@ static void imx8m_setup_csu_tzasc(void) } } +/* + * Place early TLB into the .data section so that it will not + * get cleared, use 16 kiB alignment. + */ +#define EARLY_TLB_SIZE SZ_64K +u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000); + +/* + * Initialize the MMU and activate cache in U-Boot pre-reloc stage + * MMU/TLB is updated in enable_caches() for U-Boot after relocation + */ +static void early_enable_caches(void) +{ + phys_size_t sdram_size; + int entry, ret; + + if (IS_ENABLED(CONFIG_SPL_BUILD)) + return; + + if (CONFIG_IS_ENABLED(SYS_ICACHE_OFF) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + return; + + /* Use maximum available DRAM size in first bank. */ + ret = board_phys_sdram_size(&sdram_size); + if (ret) + return; + + entry = imx8m_find_dram_entry_in_mem_map(); + imx8m_mem_map[entry].size = max(sdram_size, (phys_size_t)0xc0000000); + + gd->arch.tlb_size = EARLY_TLB_SIZE; + gd->arch.tlb_addr = (unsigned long)&early_tlb; + + /* Enable MMU (default configuration) */ + dcache_enable(); +} + int arch_cpu_init(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) icache_enable(); + early_enable_caches(); #endif /* @@ -735,6 +782,7 @@ int boot_mode_getprisec(void) #endif #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) +#ifdef SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION #define IMG_CNTN_SET1_OFFSET GENMASK(22, 19) unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect) @@ -769,6 +817,7 @@ unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, return raw_sect; } +#endif /* SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION */ #endif bool is_usb_boot(void) diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 32208220b20..f88e7a222dd 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -536,7 +536,7 @@ static int fixup_thermal_trips(void *blob, const char *name) temp = 0; if (!strcmp(type, "critical")) - temp = 1000 * (maxc - 5); + temp = 1000 * maxc; else if (!strcmp(type, "passive")) temp = 1000 * (maxc - 10); if (temp) { diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index bee9d5f4877..7a567672251 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -393,6 +393,7 @@ config TARGET_MX6SLEVK bool "mx6slevk" depends on MX6SL select SUPPORT_SPL + imply OF_UPSTREAM config TARGET_MX6SLLEVK bool "mx6sll evk" diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 3a3e01f3d0a..2c0c77e1a56 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -585,6 +585,10 @@ const struct boot_mode soc_boot_modes[] = { {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, + {"ecspi3:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0a)}, + {"ecspi3:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x1a)}, + {"ecspi3:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x2a)}, + {"ecspi3:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x3a)}, /* 4 bit bus width */ {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index 9a86f5c133f..3982f4cca18 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -33,8 +33,17 @@ ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf) ulong __weak spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev) { - return image_offset + - (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000); + u32 sector = 0; + + /* + * Some boards use this value even though MMC is not enabled in SPL, for + * example imx8mn_bsh_smm_s2 + */ +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR + sector = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; +#endif + + return image_offset + sector * 512 - 0x8000; } static int is_boot_from_stream_device(u32 boot) @@ -99,18 +108,13 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image, if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && image_get_magic(header) == FDT_MAGIC) { struct spl_load_info load; - memset(&load, 0, sizeof(load)); - spl_set_bl_len(&load, pagesize); - load.read = spl_romapi_read_seekable; + spl_load_init(&load, spl_romapi_read_seekable, NULL, pagesize); return spl_load_simple_fit(spl_image, &load, offset, header); } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && valid_container_hdr((void *)header)) { struct spl_load_info load; - memset(&load, 0, sizeof(load)); - spl_set_bl_len(&load, pagesize); - load.read = spl_romapi_read_seekable; - + spl_load_init(&load, spl_romapi_read_seekable, NULL, pagesize); ret = spl_load_imx_container(spl_image, &load, offset); } else { /* TODO */ @@ -332,10 +336,7 @@ static int spl_romapi_load_image_stream(struct spl_image_info *spl_image, ss.end = p; ss.pagesize = pagesize; - memset(&load, 0, sizeof(load)); - spl_set_bl_len(&load, 1); - load.read = spl_romapi_read_stream; - load.priv = &ss; + spl_load_init(&load, spl_romapi_read_stream, &ss, 1); return spl_load_simple_fit(spl_image, &load, (ulong)phdr, phdr); } diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c index 72a752d38e8..595fc391ac5 100644 --- a/arch/arm/mach-k3/am62x/am625_init.c +++ b/arch/arm/mach-k3/am62x/am625_init.c @@ -282,6 +282,15 @@ void board_init_f(ulong dummy) } spl_enable_cache(); + if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) && + spl_boot_device() == BOOT_DEVICE_ETHERNET) { + struct udevice *cpswdev; + + if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), + &cpswdev)) + printf("Failed to probe am65_cpsw_nuss driver\n"); + } + fixup_a53_cpu_freq_by_speed_grade(); } diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index eaa7d361767..df48ec8d479 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -104,7 +104,7 @@ int early_console_init(void) gd->cur_serial_dev = dev; gd->flags |= GD_FLG_SERIAL_READY; - gd->have_console = 1; + gd->flags |= GD_FLG_HAVE_CONSOLE; return 0; } diff --git a/arch/arm/mach-k3/r5/sysfw-loader.c b/arch/arm/mach-k3/r5/sysfw-loader.c index 94d051ba0fb..188731e673d 100644 --- a/arch/arm/mach-k3/r5/sysfw-loader.c +++ b/arch/arm/mach-k3/r5/sysfw-loader.c @@ -451,7 +451,7 @@ void k3_sysfw_loader(bool rom_loaded_sysfw, * the case when continuing to boot serially from the same * UART that the ROM loaded the initial bootloader from. */ - if (!gd->have_console) + if (!(gd->flags & GD_FLG_HAVE_CONSOLE)) early_console_init(); #endif ret = spl_ymodem_load_image(&spl_image, &bootdev); diff --git a/arch/arm/mach-octeontx/Kconfig b/arch/arm/mach-octeontx/Kconfig index 542f4804760..c2bef89b905 100644 --- a/arch/arm/mach-octeontx/Kconfig +++ b/arch/arm/mach-octeontx/Kconfig @@ -13,7 +13,6 @@ config TARGET_OCTEONTX_83XX endchoice config SYS_SOC - string default "octeontx" endif diff --git a/arch/arm/mach-octeontx2/Kconfig b/arch/arm/mach-octeontx2/Kconfig index f6158df9086..c6a477be7c0 100644 --- a/arch/arm/mach-octeontx2/Kconfig +++ b/arch/arm/mach-octeontx2/Kconfig @@ -13,7 +13,6 @@ config TARGET_OCTEONTX2_96XX endchoice config SYS_SOC - string default "octeontx2" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index c07bdaee4c3..3b13891ec24 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -8,9 +8,9 @@ # inaccessible/protected memory (and the bootrom-helper assumes that # the stack-pointer is valid before switching to the U-Boot stack). obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o -obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o +obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o spl_common.o obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o -obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o +obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o spl_common.o obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 8a57b8217ff..0fdf9365b41 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -25,7 +25,7 @@ #include <part.h> #include <ram.h> #include <syscon.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <u-boot/crc.h> #include <u-boot/sha256.h> #include <asm/cache.h> diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index 3ce7e792b5a..f4d29bbdd17 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -13,6 +13,7 @@ #include <ram.h> #include <spl.h> #include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/timer.h> #include <asm/global_data.h> #include <asm/io.h> #include <linux/bitops.h> @@ -79,33 +80,6 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) return MMCSD_MODE_RAW; } -#define TIMER_LOAD_COUNT_L 0x00 -#define TIMER_LOAD_COUNT_H 0x04 -#define TIMER_CONTROL_REG 0x10 -#define TIMER_EN 0x1 -#define TIMER_FMODE BIT(0) -#define TIMER_RMODE BIT(1) - -__weak void rockchip_stimer_init(void) -{ -#if defined(CONFIG_ROCKCHIP_STIMER_BASE) - /* If Timer already enabled, don't re-init it */ - u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - - if (reg & TIMER_EN) - return; -#ifndef CONFIG_ARM64 - asm volatile("mcr p15, 0, %0, c14, c0, 0" - : : "r"(CONFIG_COUNTER_FREQUENCY)); -#endif - writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); - writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + - TIMER_CONTROL_REG); -#endif -} - __weak int board_early_init_f(void) { return 0; diff --git a/arch/arm/mach-rockchip/spl_common.c b/arch/arm/mach-rockchip/spl_common.c new file mode 100644 index 00000000000..b29f33448ab --- /dev/null +++ b/arch/arm/mach-rockchip/spl_common.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include <asm/io.h> +#include <linux/bitops.h> + +#define TIMER_LOAD_COUNT_L 0x00 +#define TIMER_LOAD_COUNT_H 0x04 +#define TIMER_CONTROL_REG 0x10 +#define TIMER_EN 0x1 +#define TIMER_FMODE BIT(0) +#define TIMER_RMODE BIT(1) + +__weak void rockchip_stimer_init(void) +{ +#if defined(CONFIG_ROCKCHIP_STIMER_BASE) + /* If Timer already enabled, don't re-init it */ + u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + + if (reg & TIMER_EN) + return; + +#ifndef CONFIG_ARM64 + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(CONFIG_COUNTER_FREQUENCY)); +#endif + + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + + TIMER_CONTROL_REG); +#endif +} diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index 597a5caa84b..bbb9329e725 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -14,41 +14,13 @@ #include <version.h> #include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/timer.h> #include <linux/bitops.h> #if CONFIG_IS_ENABLED(BANNER_PRINT) #include <timestamp.h> #endif -#define TIMER_LOAD_COUNT_L 0x00 -#define TIMER_LOAD_COUNT_H 0x04 -#define TIMER_CONTROL_REG 0x10 -#define TIMER_EN 0x1 -#define TIMER_FMODE BIT(0) -#define TIMER_RMODE BIT(1) - -__weak void rockchip_stimer_init(void) -{ -#if defined(CONFIG_ROCKCHIP_STIMER_BASE) - /* If Timer already enabled, don't re-init it */ - u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - - if (reg & TIMER_EN) - return; - -#ifndef CONFIG_ARM64 - asm volatile("mcr p15, 0, %0, c14, c0, 0" - : : "r"(CONFIG_COUNTER_FREQUENCY)); -#endif - - writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); - writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + - TIMER_CONTROL_REG); -#endif -} - void board_init_f(ulong dummy) { struct udevice *dev; diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index b439a19ec7e..0af297470a6 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -18,6 +18,7 @@ #include <dm/read.h> #include <power/regulator.h> #include <env.h> +#include <fdt_support.h> #include <init.h> #include <linux/arm-smccc.h> #include <linux/bug.h> @@ -37,9 +38,18 @@ static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } }; struct mm_region *mem_map = rbx_mem_map; +static struct { + phys_addr_t start; + phys_size_t size; +} prevbl_ddr_banks[CONFIG_NR_DRAM_BANKS] __section(".data") = { 0 }; + int dram_init(void) { - return fdtdec_setup_mem_size_base(); + /* + * gd->ram_base / ram_size have been setup already + * in qcom_parse_memory(). + */ + return 0; } static int ddr_bank_cmp(const void *v1, const void *v2) @@ -57,21 +67,69 @@ static int ddr_bank_cmp(const void *v1, const void *v2) return (res1->start >> 24) - (res2->start >> 24); } +/* This has to be done post-relocation since gd->bd isn't preserved */ +static void qcom_configure_bi_dram(void) +{ + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = prevbl_ddr_banks[i].start; + gd->bd->bi_dram[i].size = prevbl_ddr_banks[i].size; + } +} + int dram_init_banksize(void) { - int ret; + qcom_configure_bi_dram(); - ret = fdtdec_setup_memory_banksize(); - if (ret < 0) - return ret; + return 0; +} - if (CONFIG_NR_DRAM_BANKS < 2) - return 0; +static void qcom_parse_memory(void) +{ + ofnode node; + const fdt64_t *memory; + int memsize; + phys_addr_t ram_end = 0; + int i, j, banks; + + node = ofnode_path("/memory"); + if (!ofnode_valid(node)) { + log_err("No memory node found in device tree!\n"); + return; + } + memory = ofnode_read_prop(node, "reg", &memsize); + if (!memory) { + log_err("No memory configuration was provided by the previous bootloader!\n"); + return; + } + + banks = min(memsize / (2 * sizeof(u64)), (ulong)CONFIG_NR_DRAM_BANKS); + + if (memsize / sizeof(u64) > CONFIG_NR_DRAM_BANKS * 2) + log_err("Provided more than the max of %d memory banks\n", CONFIG_NR_DRAM_BANKS); + + if (banks > CONFIG_NR_DRAM_BANKS) + log_err("Provided more memory banks than we can handle\n"); + + for (i = 0, j = 0; i < banks * 2; i += 2, j++) { + prevbl_ddr_banks[j].start = get_unaligned_be64(&memory[i]); + prevbl_ddr_banks[j].size = get_unaligned_be64(&memory[i + 1]); + /* SM8650 boards sometimes have empty regions! */ + if (!prevbl_ddr_banks[j].size) { + j--; + continue; + } + ram_end = max(ram_end, prevbl_ddr_banks[j].start + prevbl_ddr_banks[j].size); + } /* Sort our RAM banks -_- */ - qsort(gd->bd->bi_dram, CONFIG_NR_DRAM_BANKS, sizeof(gd->bd->bi_dram[0]), ddr_bank_cmp); + qsort(prevbl_ddr_banks, banks, sizeof(prevbl_ddr_banks[0]), ddr_bank_cmp); - return 0; + gd->ram_base = prevbl_ddr_banks[0].start; + gd->ram_size = ram_end - gd->ram_base; + debug("ram_base = %#011lx, ram_size = %#011llx, ram_end = %#011llx\n", + gd->ram_base, gd->ram_size, ram_end); } static void show_psci_version(void) @@ -85,26 +143,43 @@ static void show_psci_version(void) PSCI_VERSION_MINOR(res.a0)); } +/* We support booting U-Boot with an internal DT when running as a first-stage bootloader + * or for supporting quirky devices where it's easier to leave the downstream DT in place + * to improve ABL compatibility. Otherwise, we use the DT provided by ABL. + */ void *board_fdt_blob_setup(int *err) { - phys_addr_t fdt; - /* Return DTB pointer passed by ABL */ + struct fdt_header *fdt; + bool internal_valid, external_valid; + *err = 0; - fdt = get_prev_bl_fdt_addr(); + fdt = (struct fdt_header *)get_prev_bl_fdt_addr(); + external_valid = fdt && !fdt_check_header(fdt); + internal_valid = !fdt_check_header(gd->fdt_blob); /* - * If we bail then the board will simply not boot, instead let's - * try and use the FDT built into U-Boot if there is one... - * This avoids having a hard dependency on the previous stage bootloader + * There is no point returning an error here, U-Boot can't do anything useful in this situation. + * Bail out while we can still print a useful error message. */ + if (!internal_valid && !external_valid) + panic("Internal FDT is invalid and no external FDT was provided! (fdt=%#llx)\n", + (phys_addr_t)fdt); - if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K) || - fdt_check_header((void *)fdt))) { - debug("%s: Using built in FDT, bootloader gave us %#llx\n", __func__, fdt); - return (void *)gd->fdt_blob; + if (internal_valid) { + debug("Using built in FDT\n"); + } else { + debug("Using external FDT\n"); + /* So we can use it before returning */ + gd->fdt_blob = fdt; } - return (void *)fdt; + /* + * Parse the /memory node while we're here, + * this makes it easy to do other things early. + */ + qcom_parse_memory(); + + return (void *)gd->fdt_blob; } void reset_cpu(void) @@ -169,6 +244,66 @@ int board_init(void) return 0; } +/** + * out_len includes the trailing null space + */ +static int get_cmdline_option(const char *cmdline, const char *key, char *out, int out_len) +{ + const char *p, *p_end; + int len; + + p = strstr(cmdline, key); + if (!p) + return -ENOENT; + + p += strlen(key); + p_end = strstr(p, " "); + if (!p_end) + return -ENOENT; + + len = p_end - p; + if (len > out_len) + len = out_len; + + strncpy(out, p, len); + out[len] = '\0'; + + return 0; +} + +/* The bootargs are populated by the previous stage bootloader */ +static const char *get_cmdline(void) +{ + ofnode node; + static const char *cmdline = NULL; + + if (cmdline) + return cmdline; + + node = ofnode_path("/chosen"); + if (!ofnode_valid(node)) + return NULL; + + cmdline = ofnode_read_string(node, "bootargs"); + + return cmdline; +} + +void qcom_set_serialno(void) +{ + const char *cmdline = get_cmdline(); + char serial[32]; + + if (!cmdline) { + log_debug("Failed to get bootargs\n"); + return; + } + + get_cmdline_option(cmdline, "androidboot.serialno=", serial, sizeof(serial)); + if (serial[0] != '\0') + env_set("serial#", serial); +} + /* Sets up the "board", and "soc" environment variables as well as constructing the devicetree * path, with a few quirks to handle non-standard dtb filenames. This is not meant to be a * comprehensive solution to automatically picking the DTB, but aims to be correct for the @@ -267,6 +402,8 @@ static void configure_env(void) snprintf(dt_path, sizeof(dt_path), "qcom/%s-%s.dtb", env_get("soc"), env_get("board")); env_set("fdtfile", dt_path); + + qcom_set_serialno(); } void __weak qcom_late_init(void) @@ -274,29 +411,41 @@ void __weak qcom_late_init(void) } #define KERNEL_COMP_SIZE SZ_64M +#ifdef CONFIG_FASTBOOT_BUF_SIZE +#define FASTBOOT_BUF_SIZE CONFIG_FASTBOOT_BUF_SIZE +#else +#define FASTBOOT_BUF_SIZE 0 +#endif -#define addr_alloc(lmb, size) lmb_alloc(lmb, size, SZ_2M) +#define addr_alloc(size) lmb_alloc(size, SZ_2M) /* Stolen from arch/arm/mach-apple/board.c */ int board_late_init(void) { - struct lmb lmb; u32 status = 0; - - lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); + phys_addr_t addr; + struct fdt_header *fdt_blob = (struct fdt_header *)gd->fdt_blob; /* We need to be fairly conservative here as we support boards with just 1G of TOTAL RAM */ - status |= env_set_hex("kernel_addr_r", addr_alloc(&lmb, SZ_128M)); - status |= env_set_hex("ramdisk_addr_r", addr_alloc(&lmb, SZ_128M)); - status |= env_set_hex("kernel_comp_addr_r", addr_alloc(&lmb, KERNEL_COMP_SIZE)); + addr = addr_alloc(SZ_128M); + status |= env_set_hex("kernel_addr_r", addr); + status |= env_set_hex("loadaddr", addr); + status |= env_set_hex("ramdisk_addr_r", addr_alloc(SZ_128M)); + status |= env_set_hex("kernel_comp_addr_r", addr_alloc(KERNEL_COMP_SIZE)); status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE); - status |= env_set_hex("scriptaddr", addr_alloc(&lmb, SZ_4M)); - status |= env_set_hex("pxefile_addr_r", addr_alloc(&lmb, SZ_4M)); - status |= env_set_hex("fdt_addr_r", addr_alloc(&lmb, SZ_2M)); + if (IS_ENABLED(CONFIG_FASTBOOT)) + status |= env_set_hex("fastboot_addr_r", addr_alloc(FASTBOOT_BUF_SIZE)); + status |= env_set_hex("scriptaddr", addr_alloc(SZ_4M)); + status |= env_set_hex("pxefile_addr_r", addr_alloc(SZ_4M)); + addr = addr_alloc(SZ_2M); + status |= env_set_hex("fdt_addr_r", addr); if (status) log_warning("%s: Failed to set run time variables\n", __func__); + /* By default copy U-Boots FDT, it will be used as a fallback */ + memcpy((void *)addr, (void *)gd->fdt_blob, fdt32_to_cpu(fdt_blob->totalsize)); + configure_env(); qcom_late_init(); @@ -342,7 +491,7 @@ static void build_mem_map(void) u64 get_page_table_size(void) { - return SZ_64K; + return SZ_1M; } static int fdt_cmp_res(const void *v1, const void *v2) diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 6024959b97e..198785353f1 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -14,9 +14,26 @@ #include <ram.h> #include <asm/global_data.h> #include <asm/system.h> +#include <mach/stm32mp.h> DECLARE_GLOBAL_DATA_PTR; +int optee_get_reserved_memory(u32 *start, u32 *size) +{ + fdt_addr_t fdt_mem_size; + fdt_addr_t fdt_start; + ofnode node; + + node = ofnode_path("/reserved-memory/optee"); + if (!ofnode_valid(node)) + return -ENOENT; + + fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size); + *start = fdt_start; + *size = fdt_mem_size; + return (fdt_start < 0) ? fdt_start : 0; +} + int dram_init(void) { struct ram_info ram; @@ -45,9 +62,10 @@ int dram_init(void) phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { + int ret; phys_size_t size; phys_addr_t reg; - struct lmb lmb; + u32 optee_start, optee_size; if (!total_size) return gd->ram_top; @@ -57,17 +75,10 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) * if the effective available memory is bigger */ gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1); + size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE); - /* found enough not-reserved memory to relocated U-Boot */ - lmb_init(&lmb); - lmb_add(&lmb, gd->ram_base, gd->ram_top - gd->ram_base); - boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob); - /* add 8M for reserved memory for display, fdt, gd,... */ - size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE), - reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE); - - if (!reg) - reg = gd->ram_top - size; + ret = optee_get_reserved_memory(&optee_start, &optee_size); + reg = (!ret ? optee_start : gd->ram_top) - size; /* before relocation, mark the U-Boot memory as cacheable by default */ if (!(gd->flags & GD_FLG_RELOC)) diff --git a/arch/arm/mach-stm32mp/include/mach/stm32mp.h b/arch/arm/mach-stm32mp/include/mach/stm32mp.h new file mode 100644 index 00000000000..506a42559b8 --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/stm32mp.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2024, STMicroelectronics - All Rights Reserved + */ + +#ifndef __MACH_STM32MP_H_ +#define __MACH_STM32MP_H_ + +int optee_get_reserved_memory(u32 *start, u32 *size); + +#endif diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 478c3efae73..64480da9f8d 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -30,8 +30,6 @@ */ u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000); -struct lmb lmb; - u32 get_bootmode(void) { /* read bootmode from TAMP backup register */ @@ -80,7 +78,7 @@ void dram_bank_mmu_setup(int bank) i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); i++) { option = DCACHE_DEFAULT_OPTION; - if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP)) + if (use_lmb && lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP)) option = 0; /* INVALID ENTRY in TLB */ set_section_dcache(i, option); } @@ -143,9 +141,6 @@ int mach_cpu_init(void) void enable_caches(void) { - /* parse device tree when data cache is still activated */ - lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); - /* I-cache is already enabled in start.S: icache_enable() not needed */ /* deactivate the data cache, early enabled in arch_cpu_init() */ diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c index 6eae5c2f557..9c4fafbf478 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/spl.c +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c @@ -18,6 +18,7 @@ #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <mach/tzc.h> +#include <mach/stm32mp.h> #include <linux/libfdt.h> u32 spl_boot_device(void) @@ -110,22 +111,6 @@ uint32_t stm32mp_get_dram_size(void) return ram.size; } -static int optee_get_reserved_memory(uint32_t *start, uint32_t *size) -{ - fdt_addr_t fdt_mem_size; - fdt_addr_t fdt_start; - ofnode node; - - node = ofnode_path("/reserved-memory/optee"); - if (!ofnode_valid(node)) - return -ENOENT; - - fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size); - *start = fdt_start; - *size = fdt_mem_size; - return (fdt_start < 0) ? fdt_start : 0; -} - #define CFG_SHMEM_SIZE 0x200000 #define STM32_TZC_NSID_ALL 0xffff #define STM32_TZC_FILTER_ALL 3 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 046e9fbfc67..2b64ddc0dc7 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -399,7 +399,7 @@ static bool sunxi_valid_emmc_boot(struct mmc *mmc) return false; /* Partition 0 is the user data partition, bootpart must be 1 or 2. */ - if (bootpart != 1 && bootpart != 2) + if (bootpart != EMMC_BOOT_PART_BOOT1 && bootpart != EMMC_BOOT_PART_BOOT2) return false; /* Failure to switch to the boot partition is fatal. */ diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index d7abdc2e401..5f72e809952 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -390,8 +390,7 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found FIT image\n"); - spl_set_bl_len(&load, 1); - load.read = spi_load_read; + spl_load_init(&load, spi_load_read, NULL, 1); ret = spl_load_simple_fit(spl_image, &load, load_offset, header); } else { diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 479137e457c..7971e3b68d5 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -423,10 +423,6 @@ int dram_init_banksize(void) gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); -#ifdef CONFIG_PCI - gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; -#endif - #ifdef CONFIG_PHYS_64BIT if (gd->ram_size > SZ_2G) { gd->bd->bi_dram[1].start = 0x100000000; diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c index c12543d71ac..e2342b2aece 100644 --- a/arch/arm/mach-tegra/cboot.c +++ b/arch/arm/mach-tegra/cboot.c @@ -189,10 +189,6 @@ int cboot_dram_init_banksize(void) gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; } -#ifdef CONFIG_PCI - gd->pci_ram_top = ram_top; -#endif - return 0; } diff --git a/arch/m68k/cpu/mcf5445x/cpu.c b/arch/m68k/cpu/mcf5445x/cpu.c index b811ac355e4..3fbd6a58c7d 100644 --- a/arch/m68k/cpu/mcf5445x/cpu.c +++ b/arch/m68k/cpu/mcf5445x/cpu.c @@ -92,7 +92,7 @@ int print_cpuinfo(void) strmhz(buf3, gd->arch.flb_clk)); #ifdef CONFIG_PCI printf(" PCI CLK %s MHz INP CLK %s MHz VCO CLK %s MHz\n", - strmhz(buf1, gd->pci_clk), + strmhz(buf1, gd->arch.pci_clk), strmhz(buf2, gd->arch.inp_clk), strmhz(buf3, gd->arch.vco_clk)); #else diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h index 93efc722ba8..4ac886933c6 100644 --- a/arch/m68k/include/asm/global_data.h +++ b/arch/m68k/include/asm/global_data.h @@ -26,6 +26,8 @@ struct arch_global_data { #if defined(CONFIG_FSL_ESDHC) unsigned long sdhc_per_clk; #endif + /** @pci_clk: PCI clock rate in Hz */ + unsigned long pci_clk; }; #include <asm-generic/global_data.h> diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c index cf6ae5adddf..891e94bbd3f 100644 --- a/arch/m68k/lib/bdinfo.c +++ b/arch/m68k/lib/bdinfo.c @@ -22,7 +22,7 @@ int arch_setup_bdinfo(void) bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ if (IS_ENABLED(CONFIG_PCI)) - bd->bi_pcifreq = gd->pci_clk; + bd->bi_pcifreq = gd->arch.pci_clk; #if defined(CONFIG_EXTRA_CLOCK) bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ diff --git a/arch/m68k/lib/bootm.c b/arch/m68k/lib/bootm.c index f2d02e43765..3dcff8076e3 100644 --- a/arch/m68k/lib/bootm.c +++ b/arch/m68k/lib/bootm.c @@ -9,7 +9,6 @@ #include <command.h> #include <env.h> #include <image.h> -#include <lmb.h> #include <log.h> #include <asm/global_data.h> #include <u-boot/zlib.h> @@ -27,21 +26,14 @@ DECLARE_GLOBAL_DATA_PTR; #define LINUX_MAX_ENVS 256 #define LINUX_MAX_ARGS 256 -static ulong get_sp (void); static void set_clocks_in_mhz (struct bd_info *kbd); -void arch_lmb_reserve(struct lmb *lmb) -{ - arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 1024); -} - int do_bootm_linux(int flag, struct bootm_info *bmi) { struct bootm_headers *images = bmi->images; int ret; struct bd_info *kbd; void (*kernel) (struct bd_info *, ulong, ulong, ulong, ulong); - struct lmb *lmb = &images->lmb; /* * allow the PREP bootm subcommand, it is required for bootm to work @@ -53,7 +45,7 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) return 1; /* allocate space for kernel copy of board info */ - ret = boot_get_kbd (lmb, &kbd); + ret = boot_get_kbd(&kbd); if (ret) { puts("ERROR with allocation of kernel bd\n"); goto error; @@ -89,16 +81,6 @@ error: return 1; } -static ulong get_sp (void) -{ - ulong sp; - - asm("movel %%a7, %%d0\n" - "movel %%d0, %0\n": "=d"(sp): :"%d0"); - - return sp; -} - static void set_clocks_in_mhz (struct bd_info *kbd) { char *s; diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index cbe9d85aa91..4879a41aab3 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -15,7 +15,6 @@ #include <fdt_support.h> #include <hang.h> #include <image.h> -#include <lmb.h> #include <log.h> #include <asm/cache.h> #include <asm/global_data.h> @@ -24,19 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -static ulong get_sp(void) -{ - ulong ret; - - asm("addik %0, r1, 0" : "=r"(ret) : ); - return ret; -} - -void arch_lmb_reserve(struct lmb *lmb) -{ - arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); -} - static void boot_jump_linux(struct bootm_headers *images, int flag) { void (*thekernel)(char *cmdline, ulong rd, ulong dt); diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index adb6b6cc229..87195100023 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -9,7 +9,6 @@ #include <env.h> #include <image.h> #include <fdt_support.h> -#include <lmb.h> #include <log.h> #include <asm/addrspace.h> #include <asm/global_data.h> @@ -28,20 +27,6 @@ static char **linux_env; static char *linux_env_p; static int linux_env_idx; -static ulong arch_get_sp(void) -{ - ulong ret; - - __asm__ __volatile__("move %0, $sp" : "=r"(ret) : ); - - return ret; -} - -void arch_lmb_reserve(struct lmb *lmb) -{ - arch_lmb_reserve_generic(lmb, arch_get_sp(), gd->ram_top, 4096); -} - static void linux_cmdline_init(void) { linux_argc = 1; @@ -225,9 +210,8 @@ static int boot_reloc_fdt(struct bootm_headers *images) } #if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT) - boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr); - return boot_relocate_fdt(&images->lmb, &images->ft_addr, - &images->ft_len); + boot_fdt_add_mem_rsv_regions(images->ft_addr); + return boot_relocate_fdt(&images->ft_addr, &images->ft_len); #else return 0; #endif @@ -248,7 +232,7 @@ static int boot_setup_fdt(struct bootm_headers *images) images->initrd_start = virt_to_phys((void *)images->initrd_start); images->initrd_end = virt_to_phys((void *)images->initrd_end); - return image_setup_libfdt(images, images->ft_addr, &images->lmb); + return image_setup_libfdt(images, images->ft_addr, true); } static void boot_prep_linux(struct bootm_headers *images) diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c index bdaa6839a2b..231a21ca90f 100644 --- a/arch/mips/mach-ath79/ar934x/clk.c +++ b/arch/mips/mach-ath79/ar934x/clk.c @@ -327,8 +327,8 @@ int do_ar934x_showclk(struct cmd_tbl *cmdtp, int flag, int argc, { ar934x_update_clock(); printf("CPU: %8ld MHz\n", gd->cpu_clk / 1000000); - printf("Memory: %8ld MHz\n", gd->mem_clk / 1000000); - printf("AHB: %8ld MHz\n", gd->bus_clk / 1000000); + printf("Memory: %8d MHz\n", gd->mem_clk / 1000000); + printf("AHB: %8d MHz\n", gd->bus_clk / 1000000); return 0; } diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig index 624039df253..5d2186bba55 100644 --- a/arch/mips/mach-octeon/Kconfig +++ b/arch/mips/mach-octeon/Kconfig @@ -2,7 +2,6 @@ menu "Octeon platforms" depends on ARCH_OCTEON config SYS_SOC - string default "octeon" config OCTEON_CN7XXX diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c index c7744e84706..c771da61a68 100644 --- a/arch/mips/mach-octeon/cpu.c +++ b/arch/mips/mach-octeon/cpu.c @@ -67,7 +67,7 @@ static int get_clocks(void) gd->cpu_clk = ref_clock * FIELD_GET(RST_BOOT_C_MUL, val); gd->bus_clk = ref_clock * FIELD_GET(RST_BOOT_PNR_MUL, val); - debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk); + debug("%s: cpu: %lu, bus: %u\n", __func__, gd->cpu_clk, gd->bus_clk); return 0; } diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index ce939ff5e15..71319839ba2 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -64,16 +64,3 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) return 1; } - -static ulong get_sp(void) -{ - ulong ret; - - asm("mov %0, sp" : "=r"(ret) : ); - return ret; -} - -void arch_lmb_reserve(struct lmb *lmb) -{ - arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); -} diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c index 6f378c4e221..aef1123a2b7 100644 --- a/arch/powerpc/cpu/mpc83xx/pci.c +++ b/arch/powerpc/cpu/mpc83xx/pci.c @@ -45,7 +45,7 @@ void ft_pci_setup(void *blob, struct bd_info *bd) do_fixup_by_path(blob, path, "bus-range", &tmp, sizeof(tmp), 1); - tmp[0] = cpu_to_be32(gd->pci_clk); + tmp[0] = cpu_to_be32(gd->arch.pci_clk); do_fixup_by_path(blob, path, "clock-frequency", &tmp, sizeof(tmp[0]), 1); } @@ -60,7 +60,7 @@ void ft_pci_setup(void *blob, struct bd_info *bd) do_fixup_by_path(blob, path, "bus-range", &tmp, sizeof(tmp), 1); - tmp[0] = cpu_to_be32(gd->pci_clk); + tmp[0] = cpu_to_be32(gd->arch.pci_clk); do_fixup_by_path(blob, path, "clock-frequency", &tmp, sizeof(tmp[0]), 1); } diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 72464962613..0185ab50ad9 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -456,7 +456,7 @@ int get_clocks(void) #if defined(CONFIG_ARCH_MPC837X) gd->arch.sata_clk = sata_clk; #endif - gd->pci_clk = pci_sync_in; + gd->arch.pci_clk = pci_sync_in; gd->cpu_clk = gd->arch.core_clk; gd->bus_clk = gd->arch.csb_clk; return 0; diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index a7b805bc674..739d14f8002 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -940,22 +940,6 @@ int cpu_init_r(void) return 0; } -#ifdef CONFIG_ARCH_MISC_INIT -int arch_misc_init(void) -{ - if (IS_ENABLED(CONFIG_FSL_CAAM)) { - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); - if (ret) - printf("Failed to initialize caam_jr: %d\n", ret); - } - - return 0; -} -#endif - void arch_preboot_os(void) { u32 msr; diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 03f801ebbb7..bed465cb2cb 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -408,11 +408,11 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) } #endif -void cpu_mp_lmb_reserve(struct lmb *lmb) +void cpu_mp_lmb_reserve(void) { u32 bootpg = determine_mp_bootpg(NULL); - lmb_reserve(lmb, bootpg, 4096); + lmb_reserve(bootpg, 4096); } void setup_mp(void) diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index a9efbbdd3d4..cc2ce617350 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -87,6 +87,8 @@ struct arch_global_data { #if defined(CONFIG_LWMON5) unsigned long kbd_status; #endif + /** @pci_clk: PCI clock rate in Hz */ + unsigned long pci_clk; }; #include <asm-generic/global_data.h> diff --git a/arch/powerpc/include/asm/mp.h b/arch/powerpc/include/asm/mp.h index 8dacd2781d4..b3f59be8406 100644 --- a/arch/powerpc/include/asm/mp.h +++ b/arch/powerpc/include/asm/mp.h @@ -6,10 +6,8 @@ #ifndef _ASM_MP_H_ #define _ASM_MP_H_ -#include <lmb.h> - void setup_mp(void); -void cpu_mp_lmb_reserve(struct lmb *lmb); +void cpu_mp_lmb_reserve(void); u32 determine_mp_bootpg(unsigned int *pagesize); int is_core_disabled(int nr); diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index bb819dcbb6c..ecc2aba8f3c 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -39,6 +39,7 @@ obj-y += cache.o obj-y += extable.o obj-y += interrupts.o obj-$(CONFIG_CMD_KGDB) += kgdb.o +obj-y += misc.o obj-y += stack.o obj-y += time.o obj-y += traps.o diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 61e08728dd4..dc44bf3ab3a 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -12,7 +12,6 @@ #include <cpu_func.h> #include <env.h> #include <init.h> -#include <lmb.h> #include <log.h> #include <watchdog.h> #include <command.h> @@ -37,14 +36,9 @@ DECLARE_GLOBAL_DATA_PTR; -static ulong get_sp (void); extern void ft_fixup_num_cores(void *blob); static void set_clocks_in_mhz (struct bd_info *kbd); -#ifndef CFG_SYS_LINUX_LOWMEM_MAX_SIZE -#define CFG_SYS_LINUX_LOWMEM_MAX_SIZE (768*1024*1024) -#endif - static void boot_jump_linux(struct bootm_headers *images) { void (*kernel)(struct bd_info *, ulong r4, ulong r5, ulong r6, @@ -116,41 +110,6 @@ static void boot_jump_linux(struct bootm_headers *images) return; } -void arch_lmb_reserve(struct lmb *lmb) -{ - phys_size_t bootm_size; - ulong size, bootmap_base; - - bootmap_base = env_get_bootm_low(); - bootm_size = env_get_bootm_size(); - -#ifdef DEBUG - if (((u64)bootmap_base + bootm_size) > - (CFG_SYS_SDRAM_BASE + (u64)gd->ram_size)) - puts("WARNING: bootm_low + bootm_size exceed total memory\n"); - if ((bootmap_base + bootm_size) > get_effective_memsize()) - puts("WARNING: bootm_low + bootm_size exceed eff. memory\n"); -#endif - - size = min(bootm_size, get_effective_memsize()); - size = min(size, (ulong)CFG_SYS_LINUX_LOWMEM_MAX_SIZE); - - if (size < bootm_size) { - ulong base = bootmap_base + size; - printf("WARNING: adjusting available memory from 0x%lx to 0x%llx\n", - size, (unsigned long long)bootm_size); - lmb_reserve(lmb, base, bootm_size - size); - } - - arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); - -#ifdef CONFIG_MP - cpu_mp_lmb_reserve(lmb); -#endif - - return; -} - static void boot_prep_linux(struct bootm_headers *images) { #ifdef CONFIG_MP @@ -166,7 +125,6 @@ static void boot_prep_linux(struct bootm_headers *images) static int boot_cmdline_linux(struct bootm_headers *images) { ulong of_size = images->ft_len; - struct lmb *lmb = &images->lmb; ulong *cmd_start = &images->cmdline_start; ulong *cmd_end = &images->cmdline_end; @@ -174,7 +132,7 @@ static int boot_cmdline_linux(struct bootm_headers *images) if (!of_size) { /* allocate space and init command line */ - ret = boot_get_cmdline (lmb, cmd_start, cmd_end); + ret = boot_get_cmdline(cmd_start, cmd_end); if (ret) { puts("ERROR with allocation of cmdline\n"); return ret; @@ -187,14 +145,13 @@ static int boot_cmdline_linux(struct bootm_headers *images) static int boot_bd_t_linux(struct bootm_headers *images) { ulong of_size = images->ft_len; - struct lmb *lmb = &images->lmb; struct bd_info **kbd = &images->kbd; int ret = 0; if (!of_size) { /* allocate space for kernel copy of board info */ - ret = boot_get_kbd (lmb, kbd); + ret = boot_get_kbd(kbd); if (ret) { puts("ERROR with allocation of kernel bd\n"); return ret; @@ -252,14 +209,6 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) return 0; } -static ulong get_sp (void) -{ - ulong sp; - - asm( "mr %0,1": "=r"(sp) : ); - return sp; -} - static void set_clocks_in_mhz (struct bd_info *kbd) { char *s; diff --git a/arch/powerpc/lib/misc.c b/arch/powerpc/lib/misc.c new file mode 100644 index 00000000000..4cd23b3406d --- /dev/null +++ b/arch/powerpc/lib/misc.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2024 Linaro Ltd. + */ + +#include <image.h> +#include <init.h> +#include <lmb.h> + +#include <asm/mp.h> +#include <dm/device.h> +#include <dm/uclass.h> + +#ifndef CFG_SYS_LINUX_LOWMEM_MAX_SIZE +#define CFG_SYS_LINUX_LOWMEM_MAX_SIZE (768 * 1024 * 1024) +#endif + +int arch_misc_init(void) +{ + if (CONFIG_IS_ENABLED(CMD_BOOTM)) { + phys_size_t bootm_size; + ulong size, bootmap_base; + + bootmap_base = env_get_bootm_low(); + bootm_size = env_get_bootm_size(); + +#ifdef DEBUG + if (((u64)bootmap_base + bootm_size) > + (CFG_SYS_SDRAM_BASE + (u64)gd->ram_size)) + puts("WARNING: bootm_low + bootm_size exceed total memory\n"); + if ((bootmap_base + bootm_size) > get_effective_memsize()) + puts("WARNING: bootm_low + bootm_size exceed eff. memory\n"); +#endif + + size = min(bootm_size, get_effective_memsize()); + size = min(size, (ulong)CFG_SYS_LINUX_LOWMEM_MAX_SIZE); + + if (size < bootm_size) { + ulong base = bootmap_base + size; + + printf("WARNING: adjusting available memory from 0x%lx to 0x%llx\n", + size, (unsigned long long)bootm_size); + lmb_reserve(base, bootm_size - size); + } + +#ifdef CONFIG_MP + cpu_mp_lmb_reserve(); +#endif + } + + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize caam_jr: %d\n", ret); + } + + return 0; +} diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fa3b016c527..6b854cc0b65 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -46,6 +46,9 @@ config TARGET_TH1520_LPI4A config TARGET_XILINX_MBV bool "Support AMD/Xilinx MicroBlaze V" +config TARGET_ASPEED_AST2700_IBEX + bool "Support Ibex RISC-V cores on Aspeed AST2700 SoC" + endchoice config SYS_ICACHE_OFF @@ -81,6 +84,7 @@ config SPL_ZERO_MEM_BEFORE_USE # board-specific options below source "board/andestech/ae350/Kconfig" +source "board/aspeed/ibex_ast2700/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/openpiton/riscv64/Kconfig" @@ -97,6 +101,7 @@ source "arch/riscv/cpu/andes/Kconfig" source "arch/riscv/cpu/cv1800b/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" +source "arch/riscv/cpu/ast2700/Kconfig" source "arch/riscv/cpu/generic/Kconfig" source "arch/riscv/cpu/jh7110/Kconfig" @@ -308,7 +313,10 @@ config TPL_USE_ARCH_STRNCMP endmenu config RISCV_ISA_A - def_bool y + bool "Standard extension for Atomic Instructions" + default y + help + Adds "A" to the ISA string passed to the compiler. config DMA_ADDR_T_64BIT bool @@ -450,7 +458,7 @@ config RISCV_PRIV_1_9 memory is configured was also changed. config STACK_SIZE_SHIFT - int + int "Stack size shift" default 14 config OF_BOARD_FIXUP diff --git a/arch/riscv/cpu/ast2700/Kconfig b/arch/riscv/cpu/ast2700/Kconfig new file mode 100644 index 00000000000..b16f0fc7cad --- /dev/null +++ b/arch/riscv/cpu/ast2700/Kconfig @@ -0,0 +1,6 @@ +config RISCV_AST2700 + bool + imply CPU + imply CPU_RISCV + help + Run U-Boot on AST2700 with IBex RISC-V CPU integrated. diff --git a/arch/riscv/cpu/ast2700/Makefile b/arch/riscv/cpu/ast2700/Makefile new file mode 100644 index 00000000000..1f843c706ad --- /dev/null +++ b/arch/riscv/cpu/ast2700/Makefile @@ -0,0 +1 @@ +obj-y += cpu.o diff --git a/arch/riscv/cpu/ast2700/cpu.c b/arch/riscv/cpu/ast2700/cpu.c new file mode 100644 index 00000000000..c1540546a9a --- /dev/null +++ b/arch/riscv/cpu/ast2700/cpu.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + * Copyright (C) 2024, Aspeed Technology Inc. + */ + +#include <irq_func.h> +#include <asm/cache.h> + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + cache_flush(); + + return 0; +} diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds index d1113a59aa6..907094620bd 100644 --- a/arch/riscv/cpu/u-boot-spl.lds +++ b/arch/riscv/cpu/u-boot-spl.lds @@ -44,8 +44,6 @@ SECTIONS __binman_sym_end = .; } > .spl_mem - . = ALIGN(8); - _end = .; _image_binary_end = .; diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 17cda483e12..c4c44057bad 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -11,6 +11,7 @@ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb +dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb include $(srctree)/scripts/Makefile.dts diff --git a/arch/riscv/dts/ast2700-ibex.dts b/arch/riscv/dts/ast2700-ibex.dts new file mode 100644 index 00000000000..f7a05e5771b --- /dev/null +++ b/arch/riscv/dts/ast2700-ibex.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "ast2700.dtsi" + +/ { + chosen { + stdout-path = &uart12; + tick-timer = &ast_ibex_timer; + }; + + memory@0 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&uart12 { + status = "okay"; + clock-frequency = <1846153>; +}; diff --git a/arch/riscv/dts/ast2700-u-boot.dtsi b/arch/riscv/dts/ast2700-u-boot.dtsi new file mode 100644 index 00000000000..ddc08a4bcef --- /dev/null +++ b/arch/riscv/dts/ast2700-u-boot.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/ { + cpus { + bootph-all; + }; + + memory@80000000 { + bootph-all; + }; + + soc0: soc@12000000 { + bootph-all; + + sdrammc: sdrammc@12c00000 { + bootph-all; + }; + + syscon0: syscon@12c02000 { + bootph-all; + }; + }; + + soc1: soc@14000000 { + bootph-all; + + syscon1: syscon@14c02000 { + bootph-all; + }; + + uart12: serial@14c33b00 { + bootph-all; + }; + + ast_ibex_timer: timer { + bootph-all; + }; + }; + +}; diff --git a/arch/riscv/dts/ast2700.dtsi b/arch/riscv/dts/ast2700.dtsi new file mode 100644 index 00000000000..9b482dfdd84 --- /dev/null +++ b/arch/riscv/dts/ast2700.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/ { + model = "Aspeed AST2700 Ibex BootMCU"; + compatible = "aspeed,ast2700-ibex"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "lowrisc,ibex"; + device_type = "cpu"; + reg = <0>; + comptaible = "riscv"; + riscv,isa = "rv32imc"; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x80000000>; + }; + + soc0: soc@12000000 { + compatible = "aspeed,soc1","simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sdrammc: sdrammc@12c00000 { + compatible = "aspeed,ast2700-sdrammc"; + reg = <0x12c00000 0x3000>, <0x13000000 0x1000>; + aspeed,scu0 = <&syscon0>; + aspeed,scu1 = <&syscon1>; + }; + + syscon0: syscon@12c02000 { + compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd"; + reg = <0x12c02000 0x1000>; + ranges = <0 0x12c02000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + soc1: soc@14000000 { + compatible = "aspeed,soc1","simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon1: syscon@14c02000 { + compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd"; + reg = <0x14c02000 0x1000>; + ranges = <0 0x14c02000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + uart12: serial@14c33b00 { + compatible = "ns16550a"; + reg = <0x14c33b00 0x20>; + reg-shift = <2>; + no-loopback-test; + clock-frequency = <1846153>; + status = "disabled"; + }; + + ast_ibex_timer: timer { + compatible = "aspeed,ast2700-ibex-timer"; + clock-frequency = <200000000>; + }; + }; +}; diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi index 4b0143450e8..8a7386b76e6 100644 --- a/arch/riscv/dts/cv18xx.dtsi +++ b/arch/riscv/dts/cv18xx.dtsi @@ -5,6 +5,7 @@ */ #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/sophgo,cv1800.h> / { #address-cells = <1>; @@ -45,13 +46,6 @@ #clock-cells = <0>; }; - sdhci_clk: sdhci-clock { - compatible = "fixed-clock"; - clock-frequency = <375000000>; - clock-output-names = "sdhci_clk"; - #clock-cells = <0>; - }; - eth_csrclk: eth-csrclk { compatible = "fixed-clock"; clock-frequency = <250000000>; @@ -66,13 +60,6 @@ #clock-cells = <0x0>; }; - spif_clk: spi-flash-clock { - compatible = "fixed-clock"; - clock-frequency = <300000000>; - clock-output-names = "spif_clk"; - #clock-cells = <0>; - }; - soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -163,8 +150,8 @@ compatible = "sophgo,cv1800b-dwmac"; reg = <0x04070000 0x10000>; interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <ð_csrclk>, <ð_ptpclk>; - clock-names = "stmmaceth", "ptp_ref"; + clocks = <&clk CLK_ETH0_500M>, <&clk CLK_AXI4_ETH0>; + clock-names = "stmmaceth", "pclk"; status = "disabled"; }; @@ -172,7 +159,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x04140000 0x100>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -182,7 +170,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x04150000 0x100>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -192,7 +181,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x04160000 0x100>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -202,7 +192,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x04170000 0x100>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -212,7 +203,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x041c0000 0x100>; interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -222,8 +214,8 @@ compatible = "sophgo,cv1800b-dwcmshc"; reg = <0x4310000 0x1000>; interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sdhci_clk>; - clock-names = "core"; + clocks = <&clk CLK_AXI4_SD0>, <&clk CLK_SD0>; + clock-names = "core", "bus"; status = "disabled"; }; @@ -232,7 +224,7 @@ reg = <0x10000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; - clocks = <&spif_clk>; + clocks = <&clk CLK_AHB_SF>; interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; diff --git a/arch/riscv/include/asm/arch-ast2700/fmc_hdr.h b/arch/riscv/include/asm/arch-ast2700/fmc_hdr.h new file mode 100644 index 00000000000..fbbcdb25cca --- /dev/null +++ b/arch/riscv/include/asm/arch-ast2700/fmc_hdr.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#ifndef __ASM_AST2700_FMC_HDR_H__ +#define __ASM_AST2700_FMC_HDR_H__ + +#include <linux/types.h> + +#define HDR_MAGIC 0x48545341 /* ASTH */ +#define HDR_PB_MAX 30 + +enum prebuilt_type { + PBT_END_MARK = 0x0, + + PBT_DDR4_PMU_TRAIN_IMEM, + PBT_DDR4_PMU_TRAIN_DMEM, + PBT_DDR4_2D_PMU_TRAIN_IMEM, + PBT_DDR4_2D_PMU_TRAIN_DMEM, + PBT_DDR5_PMU_TRAIN_IMEM, + PBT_DDR5_PMU_TRAIN_DMEM, + PBT_DP_FW, + PBT_UEFI_X64_AST2700, + + PBT_NUM +}; + +struct fmc_hdr_preamble { + uint32_t magic; + uint32_t version; +}; + +struct fmc_hdr_body { + uint32_t fmc_size; + union { + struct { + uint32_t type; + uint32_t size; + } pbs[0]; + uint32_t raz[29]; + }; +}; + +struct fmc_hdr { + struct fmc_hdr_preamble preamble; + struct fmc_hdr_body body; +} __packed; + +int fmc_hdr_get_prebuilt(uint32_t type, uint32_t *ofst, uint32_t *size); + +#endif diff --git a/arch/riscv/include/asm/arch-ast2700/scu.h b/arch/riscv/include/asm/arch-ast2700/scu.h new file mode 100644 index 00000000000..1aa7d38bace --- /dev/null +++ b/arch/riscv/include/asm/arch-ast2700/scu.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef __ASM_AST2700_SCU_H__ +#define __ASM_AST2700_SCU_H__ + +/* SCU0: CPU-die SCU */ +#define SCU0_HWSTRAP 0x010 +#define SCU0_HWSTRAP_DIS_RVAS BIT(30) +#define SCU0_HWSTRAP_DIS_WDTFULL BIT(25) +#define SCU0_HWSTRAP_DISARMICE_TZ BIT(22) +#define SCU0_HWSTRAP_DISABLE_XHCI BIT(21) +#define SCU0_HWSTRAP_BOOTEMMCSPEED BIT(20) +#define SCU0_HWSTRAP_VGA_CC BIT(18) +#define SCU0_HWSTRAP_EN_OPROM BIT(17) +#define SCU0_HWSTRAP_DISARMICE BIT(16) +#define SCU0_HWSTRAP_TSPRSNTSEL BIT(9) +#define SCU0_HWSTRAP_DISDEBUG BIT(8) +#define SCU0_HWSTRAP_HCLKHPLL BIT(7) +#define SCU0_HWSTRAP_HCLKSEL GENMASK(6, 5) +#define SCU0_HWSTRAP_CPUHPLL BIT(4) +#define SCU0_HWSTRAP_HPLLFREQ GENMASK(3, 2) +#define SCU0_HWSTRAP_BOOTSPI BIT(1) +#define SCU0_HWSTRAP_HWSTRAP_DISCPU BIT(0) +#define SCU0_DBGCTL 0x0c8 +#define SCU0_DBGCTL_MASK GENMASK(14, 0) +#define SCU0_DBGCTL_UARTDBG BIT(1) +#define SCU0_RSTCTL1 0x200 +#define SCU0_RSTCTL1_EMMC BIT(17) +#define SCU0_RSTCTL1_HACE BIT(4) +#define SCU0_RSTCTL1_CLR 0x204 +#define SCU0_RSTCTL1_CLR_EMMC BIT(17) +#define SCU0_RSTCTL1_CLR_HACE BIT(4) +#define SCU0_CLKGATE1 0x240 +#define SCU0_CLKGATE1_EMMC BIT(27) +#define SCU0_CLKGATE1_HACE BIT(13) +#define SCU0_CLKGATE1_DDRPHY BIT(11) +#define SCU0_CLKGATE1_CLR 0x244 +#define SCU0_CLKGATE1_CLR_EMMC BIT(27) +#define SCU0_CLKGATE1_CLR_HACE BIT(13) +#define SCU0_CLKGATE1_CLR_DDRPHY BIT(11) +#define SCU0_VGA0_SCRATCH 0x900 +#define SCU0_VGA0_SCRATCH_DRAM_INIT BIT(6) +#define SCU0_PCI_MISC70 0xa70 +#define SCU0_PCI_MISC70_EN_PCIEXHCI0 BIT(3) +#define SCU0_PCI_MISC70_EN_PCIEEHCI0 BIT(2) +#define SCU0_PCI_MISC70_EN_PCIEVGA0 BIT(0) +#define SCU0_PCI_MISC80 0xa80 +#define SCU0_PCI_MISC80_EN_PCIEXHCI1 BIT(3) +#define SCU0_PCI_MISC80_EN_PCIEEHCI1 BIT(2) +#define SCU0_PCI_MISC80_EN_PCIEVGA1 BIT(0) +#define SCU0_PCI_MISCF0 0xaf0 +#define SCU0_PCI_MISCF0_EN_PCIEXHCI1 BIT(3) +#define SCU0_PCI_MISCF0_EN_PCIEEHCI1 BIT(2) +#define SCU0_PCI_MISCF0_EN_PCIEVGA1 BIT(0) +#define SCU0_WPROT1 0xe04 +#define SCU0_WPROT1_0C8 BIT(18) + +/* SCU1: IO-die SCU */ +#define SCU1_REVISION 0x000 +#define SCU1_REVISION_HWID GENMASK(23, 16) +#define SCU1_REVISION_CHIP_EFUSE GENMASK(15, 8) +#define SCU1_HWSTRAP1 0x010 +#define SCU1_HWSTRAP1_DIS_CPTRA BIT(30) +#define SCU1_HWSTRAP1_RECOVERY_USB_PORT GENMASK(29, 28) +#define SCU1_HWSTRAP1_RECOVERY_INTERFACE GENMASK(27, 26) +#define SCU1_HWSTRAP1_RECOVERY_I3C (BIT(26) | BIT(27)) +#define SCU1_HWSTRAP1_RECOVERY_I2C BIT(27) +#define SCU1_HWSTRAP1_RECOVERY_USB BIT(26) +#define SCU1_HWSTRAP1_SPI_FLASH_4_BYTE_MODE BIT(25) +#define SCU1_HWSTRAP1_SPI_FLASH_WAIT_READY BIT(24) +#define SCU1_HWSTRAP1_BOOT_UFS BIT(23) +#define SCU1_HWSTRAP1_DIS_ROM BIT(22) +#define SCU1_HWSTRAP1_DIS_CPTRAJTAG BIT(20) +#define SCU1_HWSTRAP1_UARTDBGSEL BIT(19) +#define SCU1_HWSTRAP1_DIS_UARTDBG BIT(18) +#define SCU1_HWSTRAP1_DIS_WDTFULL BIT(17) +#define SCU1_HWSTRAP1_DISDEBUG1 BIT(16) +#define SCU1_HWSTRAP1_LTPI0_IO_DRIVING GENMASK(15, 14) +#define SCU1_HWSTRAP1_ACPI_1 BIT(13) +#define SCU1_HWSTRAP1_ACPI_0 BIT(12) +#define SCU1_HWSTRAP1_BOOT_EMMC_UFS BIT(11) +#define SCU1_HWSTRAP1_DDR4 BIT(10) +#define SCU1_HWSTRAP1_LOW_SECURE BIT(8) +#define SCU1_HWSTRAP1_EN_EMCS BIT(7) +#define SCU1_HWSTRAP1_EN_GPIOPT BIT(6) +#define SCU1_HWSTRAP1_EN_SECBOOT BIT(5) +#define SCU1_HWSTRAP1_EN_RECOVERY_BOOT BIT(4) +#define SCU1_HWSTRAP1_LTPI0_EN BIT(3) +#define SCU1_HWSTRAP1_LTPI_IDX BIT(2) +#define SCU1_HWSTRAP1_LTPI1_EN BIT(1) +#define SCU1_HWSTRAP1_LTPI_MODE BIT(0) +#define SCU1_HWSTRAP2 0x030 +#define SCU1_HWSTRAP2_FMC_ABR_SINGLE_FLASH BIT(29) +#define SCU1_HWSTRAP2_FMC_ABR_CS_SWAP_DIS BIT(28) +#define SCU1_HWSTRAP2_SPI_TPM_PCR_EXT_EN BIT(27) +#define SCU1_HWSTRAP2_SPI_TPM_HASH_ALGO GENMASK(26, 25) +#define SCU1_HWSTRAP2_BOOT_SPI_FREQ GENMASK(24, 23) +#define SCU1_HWSTRAP2_RESERVED GENMASK(22, 19) +#define SCU1_HWSTRAP2_FWSPI_CRTM GENMASK(18, 17) +#define SCU1_HWSTRAP2_EN_FWSPIAUX BIT(16) +#define SCU1_HWSTRAP2_FWSPISIZE GENMASK(15, 13) +#define SCU1_HWSTRAP2_DIS_REC BIT(12) +#define SCU1_HWSTRAP2_EN_CPTRA_DBG BIT(11) +#define SCU1_HWSTRAP2_TPM_PCR_INDEX GENMASK(6, 2) +#define SCU1_HWSTRAP2_ROM_CLEAR_SRAM BIT(1) +#define SCU1_HWSTRAP2_ABR BIT(0) +#define SCU1_RSTLOG0 0x050 +#define SCU1_RSTLOG0_BMC_CPU BIT(12) +#define SCU1_RSTLOG0_ABR BIT(2) +#define SCU1_RSTLOG0_EXTRSTN BIT(1) +#define SCU1_RSTLOG0_SRST BIT(0) +#define SCU1_MISC1 0x0c0 +#define SCU1_MISC1_UARTDBG_ROUTE GENMASK(23, 22) +#define SCU1_MISC1_UART12_ROUTE GENMASK(21, 20) +#define SCU1_DBGCTL 0x0c8 +#define SCU1_DBGCTL_MASK GENMASK(7, 0) +#define SCU1_DBGCTL_UARTDBG BIT(6) +#define SCU1_RNG_DATA 0x0f4 +#define SCU1_RSTCTL1 0x200 +#define SCU1_RSTCTL1_I3C(x) (BIT(16) << (x)) +#define SCU1_RSTCTL1_CLR 0x204 +#define SCU1_RSTCTL1_CLR_I3C(x) (BIT(16) << (x)) +#define SCU1_RSTCTL2 0x220 +#define SCU1_RSTCTL2_LTPI1 BIT(22) +#define SCU1_RSTCTL2_LTPI0 BIT(20) +#define SCU1_RSTCTL2_I2C BIT(15) +#define SCU1_RSTCTL2_CPTRA BIT(9) +#define SCU1_RSTCTL2_CLR 0x224 +#define SCU1_RSTCTL2_CLR_I2C BIT(15) +#define SCU1_RSTCTL2_CLR_CPTRA BIT(9) +#define SCU1_CLKGATE1 0x240 +#define SCU1_CLKGATE1_I3C(x) (BIT(16) << (x)) +#define SCU1_CLKGATE1_I2C BIT(15) +#define SCU1_CLKGATE1_CLR 0x244 +#define SCU1_CLKGATE1_CLR_I3C(x) (BIT(16) << (x)) +#define SCU1_CLKGATE1_CLR_I2C BIT(15) +#define SCU1_CLKGATE2 0x260 +#define SCU1_CLKGATE2_LTPI1_TX BIT(19) +#define SCU1_CLKGATE2_LTPI_AHB BIT(10) +#define SCU1_CLKGATE2_LTPI0_TX BIT(9) +#define SCU1_CLKGATE2_CLR 0x264 + +#endif diff --git a/arch/riscv/include/asm/arch-ast2700/sdram.h b/arch/riscv/include/asm/arch-ast2700/sdram.h new file mode 100644 index 00000000000..daf48dd6ed1 --- /dev/null +++ b/arch/riscv/include/asm/arch-ast2700/sdram.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef __ASM_AST2700_SDRAM_H__ +#define __ASM_AST2700_SDRAM_H__ + +struct sdrammc_regs { + u32 prot_key; + u32 intr_status; + u32 intr_clear; + u32 intr_mask; + u32 mcfg; + u32 mctl; + u32 msts; + u32 error_status; + u32 actime1; + u32 actime2; + u32 actime3; + u32 actime4; + u32 actime5; + u32 actime6; + u32 actime7; + u32 dfi_timing; + u32 dcfg; + u32 dctl; + u32 mrctl; + u32 mrwr; + u32 mrrd; + u32 mr01; + u32 mr23; + u32 mr45; + u32 mr67; + u32 refctl; + u32 refmng_ctl; + u32 refsts; + u32 zqctl; + u32 ecc_addr_range; + u32 ecc_failure_status; + u32 ecc_failure_addr; + u32 ecc_test_control; + u32 ecc_test_status; + u32 arbctl; + u32 enccfg; + u32 protect_lock_set; + u32 protect_lock_status; + u32 protect_lock_reset; + u32 enc_min_addr; + u32 enc_max_addr; + u32 enc_key[4]; + u32 enc_iv[3]; + u32 bistcfg; + u32 bist_addr; + u32 bist_size; + u32 bist_patt; + u32 bist_res; + u32 bist_fail_addr; + u32 bist_fail_data[4]; + u32 reserved2[2]; + u32 debug_control; + u32 debug_status; + u32 phy_intf_status; + u32 testcfg; + u32 gfmcfg; + u32 gfm0ctl; + u32 gfm1ctl; + u32 reserved3[0xf8]; +}; + +#define DRAMC_UNLK_KEY 0x1688a8a8 + +/* offset 0x04 */ +#define DRAMC_IRQSTA_PWRCTL_ERR BIT(16) +#define DRAMC_IRQSTA_PHY_ERR BIT(15) +#define DRAMC_IRQSTA_LOWPOWER_DONE BIT(12) +#define DRAMC_IRQSTA_FREQ_CHG_DONE BIT(11) +#define DRAMC_IRQSTA_REF_DONE BIT(10) +#define DRAMC_IRQSTA_ZQ_DONE BIT(9) +#define DRAMC_IRQSTA_BIST_DONE BIT(8) +#define DRAMC_IRQSTA_ECC_RCVY_ERR BIT(5) +#define DRAMC_IRQSTA_ECC_ERR BIT(4) +#define DRAMC_IRQSTA_PROT_ERR BIT(3) +#define DRAMC_IRQSTA_OVERSZ_ERR BIT(2) +#define DRAMC_IRQSTA_MR_DONE BIT(1) +#define DRAMC_IRQSTA_PHY_INIT_DONE BIT(0) + +/* offset 0x14 */ +#define DRAMC_MCTL_WB_SOFT_RESET BIT(24) +#define DRAMC_MCTL_PHY_CLK_DIS BIT(18) +#define DRAMC_MCTL_PHY_RESET BIT(17) +#define DRAMC_MCTL_PHY_POWER_ON BIT(16) +#define DRAMC_MCTL_FREQ_CHG_START BIT(3) +#define DRAMC_MCTL_PHY_LOWPOWER_START BIT(2) +#define DRAMC_MCTL_SELF_REF_START BIT(1) +#define DRAMC_MCTL_PHY_INIT_START BIT(0) + +/* offset 0x40 */ +#define DRAMC_DFICFG_WD_POL BIT(18) +#define DRAMC_DFICFG_CKE_OUT BIT(17) +#define DRAMC_DFICFG_RESET BIT(16) + +/* offset 0x48 */ +#define DRAMC_MRCTL_ERR_STATUS BIT(31) +#define DRAMC_MRCTL_READY_STATUS BIT(30) +#define DRAMC_MRCTL_MR_ADDR BIT(8) +#define DRAMC_MRCTL_CMD_DLL_RST BIT(7) +#define DRAMC_MRCTL_CMD_DQ_SEL BIT(6) +#define DRAMC_MRCTL_CMD_TYPE BIT(2) +#define DRAMC_MRCTL_CMD_WR_CTL BIT(1) +#define DRAMC_MRCTL_CMD_START BIT(0) + +/* offset 0xC0 */ +#define DRAMC_BISTRES_RUNNING BIT(10) +#define DRAMC_BISTRES_FAIL BIT(9) +#define DRAMC_BISTRES_DONE BIT(8) +#define DRAMC_BISTCFG_INIT_MODE BIT(7) +#define DRAMC_BISTCFG_PMODE GENMASK(6, 4) +#define DRAMC_BISTCFG_BMODE GENMASK(3, 2) +#define DRAMC_BISTCFG_ENABLE BIT(1) +#define DRAMC_BISTCFG_START BIT(0) +#define BIST_PMODE_CRC (3) +#define BIST_BMODE_RW_SWITCH (3) + +/* DRAMC048 MR Control Register */ +#define MR_TYPE_SHIFT 2 +#define MR_RW (0 << MR_TYPE_SHIFT) +#define MR_MPC BIT(2) +#define MR_VREFCS (2 << MR_TYPE_SHIFT) +#define MR_VREFCA (3 << MR_TYPE_SHIFT) +#define MR_ADDRESS_SHIFT 8 +#define MR_ADDR(n) (((n) << MR_ADDRESS_SHIFT) | DRAMC_MRCTL_CMD_WR_CTL) +#define MR_NUM_SHIFT 4 +#define MR_NUM(n) ((n) << MR_NUM_SHIFT) +#define MR_DLL_RESET BIT(7) +#define MR_1T_MODE BIT(16) + +#endif diff --git a/arch/riscv/include/asm/arch-ast2700/sli.h b/arch/riscv/include/asm/arch-ast2700/sli.h new file mode 100644 index 00000000000..42f0f9ac93d --- /dev/null +++ b/arch/riscv/include/asm/arch-ast2700/sli.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef __ASM_AST2700_SLI_H__ +#define __ASM_AST2700_SLI_H__ + +#define SLI_CPU_ADRBASE 0x12c17000 +#define SLI_IOD_ADRBASE 0x14c1e000 +#define SLIM_CPU_BASE (SLI_CPU_ADRBASE + 0x000) +#define SLIH_CPU_BASE (SLI_CPU_ADRBASE + 0x200) +#define SLIV_CPU_BASE (SLI_CPU_ADRBASE + 0x400) +#define SLIM_IOD_BASE (SLI_IOD_ADRBASE + 0x000) +#define SLIH_IOD_BASE (SLI_IOD_ADRBASE + 0x200) +#define SLIV_IOD_BASE (SLI_IOD_ADRBASE + 0x400) + +#define SLI_CTRL_I 0x00 +#define SLIV_RAW_MODE BIT(15) +#define SLI_TX_MODE BIT(14) +#define SLI_RX_PHY_LAH_SEL_REV BIT(13) +#define SLI_RX_PHY_LAH_SEL_NEG BIT(12) +#define SLI_AUTO_SEND_TRN_OFF BIT(8) +#define SLI_CLEAR_BUS BIT(6) +#define SLI_TRANS_EN BIT(5) +#define SLI_CLEAR_RX BIT(2) +#define SLI_CLEAR_TX BIT(1) +#define SLI_RESET_TRIGGER BIT(0) +#define SLI_CTRL_II 0x04 +#define SLI_CTRL_III 0x08 +#define SLI_CLK_SEL GENMASK(31, 28) +#define SLI_CLK_500M 0x6 +#define SLI_CLK_200M 0x3 +#define SLI_PHYCLK_SEL GENMASK(27, 24) +#define SLI_PHYCLK_25M 0x0 +#define SLI_PHYCLK_800M 0x1 +#define SLI_PHYCLK_400M 0x2 +#define SLI_PHYCLK_200M 0x3 +#define SLI_PHYCLK_788M 0x5 +#define SLI_PHYCLK_500M 0x6 +#define SLI_PHYCLK_250M 0x7 +#define SLIH_PAD_DLY_TX1 GENMASK(23, 18) +#define SLIH_PAD_DLY_TX0 GENMASK(17, 12) +#define SLIH_PAD_DLY_RX1 GENMASK(11, 6) +#define SLIH_PAD_DLY_RX0 GENMASK(5, 0) +#define SLIM_PAD_DLY_RX3 GENMASK(23, 18) +#define SLIM_PAD_DLY_RX2 GENMASK(17, 12) +#define SLIM_PAD_DLY_RX1 GENMASK(11, 6) +#define SLIM_PAD_DLY_RX0 GENMASK(5, 0) +#define SLI_CTRL_IV 0x0c +#define SLIM_PAD_DLY_TX3 GENMASK(23, 18) +#define SLIM_PAD_DLY_TX2 GENMASK(17, 12) +#define SLIM_PAD_DLY_TX1 GENMASK(11, 6) +#define SLIM_PAD_DLY_TX0 GENMASK(5, 0) +#define SLI_INTR_EN 0x10 +#define SLI_INTR_STATUS 0x14 +#define SLI_INTR_RX_SYNC BIT(15) +#define SLI_INTR_RX_ERR BIT(13) +#define SLI_INTR_RX_NACK BIT(12) +#define SLI_INTR_RX_TRAIN_PKT BIT(10) +#define SLI_INTR_RX_DISCONN BIT(6) +#define SLI_INTR_TX_SUSPEND BIT(4) +#define SLI_INTR_TX_TRAIN BIT(3) +#define SLI_INTR_TX_IDLE BIT(2) +#define SLI_INTR_RX_SUSPEND BIT(1) +#define SLI_INTR_RX_IDLE BIT(0) +#define SLI_INTR_RX_ERRORS \ + (SLI_INTR_RX_ERR | SLI_INTR_RX_NACK | SLI_INTR_RX_DISCONN) + +#define SLIM_MARB_FUNC_I 0x60 +#define SLIM_SLI_MARB_RR BIT(0) + +#define SLI_TARGET_PHYCLK SLI_PHYCLK_400M +#define SLIH_DEFAULT_DELAY 11 +#if (SLI_TARGET_PHYCLK == SLI_PHYCLK_800M) || (SLI_TARGET_PHYCLK == SLI_PHYCLK_788M) +#define SLIM_DEFAULT_DELAY 5 +#define SLIM_LAH_CONFIG 1 +#else +#define SLIM_DEFAULT_DELAY 12 +#define SLIM_LAH_CONFIG 0 +#endif +#endif +int sli_init(void); diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 13cbaaba682..82502972eec 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -133,16 +133,3 @@ int do_bootm_vxworks(int flag, struct bootm_info *bmi) { return do_bootm_linux(flag, bmi); } - -static ulong get_sp(void) -{ - ulong ret; - - asm("mv %0, sp" : "=r"(ret) : ); - return ret; -} - -void arch_lmb_reserve(struct lmb *lmb) -{ - arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); -} diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index bcb1ca10a51..1c33a520c64 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -127,6 +127,15 @@ static int load_from_image(struct spl_image_info *spl_image, } SPL_LOAD_IMAGE_METHOD("sandbox_image", 7, BOOT_DEVICE_BOARD, load_from_image); +int dram_init_banksize(void) +{ + /* These are necessary so TFTP can use LMBs to check its load address */ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = get_effective_memsize(); + + return 0; +} + void spl_board_init(void) { struct sandbox_state *state = state_get_current(); @@ -134,10 +143,6 @@ void spl_board_init(void) if (!CONFIG_IS_ENABLED(UNIT_TEST)) return; - /* These are necessary so TFTP can use LMBs to check its load address */ - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); - if (state->run_unittests) { struct unit_test *tests = UNIT_TEST_ALL_START(); const int count = UNIT_TEST_ALL_COUNT(); @@ -221,9 +226,8 @@ int sandbox_spl_load_fit(char *fname, int maxlen, struct spl_image_info *image) int ret; int fd; - memset(&load, '\0', sizeof(load)); - spl_set_bl_len(&load, IS_ENABLED(CONFIG_SPL_LOAD_BLOCK) ? 512 : 1); - load.read = read_fit_image; + spl_load_init(&load, read_fit_image, &load_ctx, + IS_ENABLED(CONFIG_SPL_LOAD_BLOCK) ? 512 : 1); ret = sandbox_find_next_phase(fname, maxlen, true); if (ret) { diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index c93ce712894..8a115c503dc 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -231,23 +231,25 @@ }; pinctrl { + bootph-some-ram; compatible = "sandbox,pinctrl"; status = "okay"; pinctrl_i2c0: i2c0 { - groups = "i2c"; - function = "i2c"; + groups = "I2C_UART"; + function = "I2C"; bias-pull-up; }; pinctrl_serial0: uart0 { - groups = "serial_a"; - function = "serial"; + bootph-some-ram; + groups = "I2C_UART"; + function = "UART"; }; pinctrl_onewire0: onewire0 { - groups = "w1"; - function = "w1"; + pins = "P8"; + function = "ONEWIRE"; bias-pull-up; }; }; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 5fb5eac862e..8412506c17a 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -78,7 +78,7 @@ event_log: tcg_event_log { no-map; - reg = <(CFG_SYS_SDRAM_SIZE - 0x2000) 0x2000>; + reg = <(CFG_SYS_SDRAM_BASE + 0x100000) 0x2000>; }; }; diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 17159f8d674..0e8d19ce232 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -49,6 +49,10 @@ struct unit_test_state; #define PCI_EA_BAR2_MAGIC 0x72727272 #define PCI_EA_BAR4_MAGIC 0x74747474 +/* Used by the sandbox iommu driver */ +#define SANDBOX_IOMMU_DVA_ADDR 0x89abc000 +#define SANDBOX_IOMMU_PAGE_SIZE SZ_4K + enum { SANDBOX_IRQN_PEND = 1, /* Interrupt number for 'pending' test */ }; diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index e298d766b52..bb0f59e0aa2 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -101,16 +101,3 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) /* does not return */ return 1; } - -static ulong get_sp(void) -{ - ulong ret; - - asm("mov r15, %0" : "=r"(ret) : ); - return ret; -} - -void arch_lmb_reserve(struct lmb *lmb) -{ - arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); -} diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index db2727d7485..934e98ac582 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -412,12 +412,6 @@ int cpu_phys_address_size(void) return 32; } -/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */ -static void setup_pci_ram_top(void) -{ - gd_set_pci_ram_top(0x80000000U); -} - static void setup_mtrr(void) { u64 mtrr_cap; @@ -469,7 +463,6 @@ int x86_cpu_init_f(void) setup_cpu_features(); setup_identity(); setup_mtrr(); - setup_pci_ram_top(); /* Set up the i8254 timer if required */ if (IS_ENABLED(CONFIG_I8254_TIMER)) @@ -483,7 +476,6 @@ int x86_cpu_reinit_f(void) long addr; setup_identity(); - setup_pci_ram_top(); addr = locate_coreboot_table(); if (addr >= 0) { gd->arch.coreboot_table = addr; diff --git a/arch/x86/cpu/intel_common/cpu_from_spl.c b/arch/x86/cpu/intel_common/cpu_from_spl.c index 48b2ef253cb..5aad2ae7309 100644 --- a/arch/x86/cpu/intel_common/cpu_from_spl.c +++ b/arch/x86/cpu/intel_common/cpu_from_spl.c @@ -24,9 +24,7 @@ int arch_cpu_init(void) int ret; #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB) - struct spl_handoff *ho = gd->spl_handoff; - - gd->arch.hob_list = ho->arch.hob_list; + gd->arch.hob_list = handoff_get(); #endif ret = x86_cpu_reinit_f(); diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index d71ab0a6385..05691a38d2e 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -55,7 +55,6 @@ int arch_cpu_init(void) static int ivybridge_cpu_init(void) { - struct pci_controller *hose; struct udevice *bus, *dev; int ret; @@ -65,10 +64,6 @@ static int ivybridge_cpu_init(void) if (ret) return ret; post_code(0x72); - hose = dev_get_uclass_priv(bus); - - /* TODO(sjg@chromium.org): Get rid of gd->hose */ - gd->hose = hose; ret = uclass_first_device_err(UCLASS_LPC, &dev); if (ret) diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index aa1f47d7227..e2e1849c065 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -164,12 +164,12 @@ static inline void barrier_wait(atomic_t *b) { while (atomic_read(b) == 0) asm("pause"); - mfence(); + mb(); } static inline void release_barrier(atomic_t *b) { - mfence(); + mb(); atomic_set(b, 1); } @@ -631,7 +631,7 @@ static int run_ap_work(struct mp_callback *callback, struct udevice *bsp, if (cur_cpu != i) store_callback(&ap_callbacks[i], callback); } - mfence(); + mb(); /* Wait for all the APs to signal back that call has been accepted. */ start = get_timer(0); @@ -656,7 +656,7 @@ static int run_ap_work(struct mp_callback *callback, struct udevice *bsp, } while (cpus_accepted != num_aps); /* Make sure we can see any data written by the APs */ - mfence(); + mb(); return 0; } @@ -692,7 +692,7 @@ static int ap_wait_for_instruction(struct udevice *cpu, void *unused) /* Copy to local variable before using the value */ memcpy(&lcb, cb, sizeof(lcb)); - mfence(); + mb(); if (lcb.logical_cpu_number == MP_SELECT_ALL || lcb.logical_cpu_number == MP_SELECT_APS || dev_seq(cpu) == lcb.logical_cpu_number) diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 073f80b07f1..87e0c6f12b6 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -185,11 +185,6 @@ static inline int flag_is_changeable_p(uint32_t flag) } #endif -static inline void mfence(void) -{ - __asm__ __volatile__("mfence" : : : "memory"); -} - /** * cpu_enable_paging_pae() - Enable PAE-paging * diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index c6d90eb794a..1390193f09c 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -240,6 +240,7 @@ static inline void sync(void) * have some advantages to use them instead of the simple one here. */ #define dmb() __asm__ __volatile__ ("" : : : "memory") +#define mb() __asm__ __volatile__ ("mfence" : : : "memory") #define __iormb() dmb() #define __iowmb() dmb() diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 2c889bcd33c..55f581836df 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -253,21 +253,3 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) return boot_jump_linux(images); } - -static ulong get_sp(void) -{ - ulong ret; - -#if CONFIG_IS_ENABLED(X86_64) - asm("mov %%rsp, %0" : "=r"(ret) : ); -#else - asm("mov %%esp, %0" : "=r"(ret) : ); -#endif - - return ret; -} - -void arch_lmb_reserve(struct lmb *lmb) -{ - arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); -} diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index 5f7701265a9..ad25020086c 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -103,7 +103,6 @@ static int fsp_video_probe(struct udevice *dev) * For IGD, it seems to be always on BAR2. */ vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2); - gd->fb_base = vesa->phys_base_ptr; ret = vesa_setup_video_priv(vesa, vesa->phys_base_ptr, uc_priv, plat); if (ret) diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c index 83c6d7bcc93..a50dc985a3c 100644 --- a/arch/x86/lib/fsp2/fsp_dram.c +++ b/arch/x86/lib/fsp2/fsp_dram.c @@ -59,7 +59,7 @@ int dram_init(void) #endif } else { #if CONFIG_IS_ENABLED(HANDOFF) - struct spl_handoff *ho = gd->spl_handoff; + struct spl_handoff *ho = handoff_get(); if (!ho) { log_debug("No SPL handoff found\n"); @@ -82,7 +82,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return gd->ram_size; #if CONFIG_IS_ENABLED(HANDOFF) - struct spl_handoff *ho = gd->spl_handoff; + struct spl_handoff *ho = handoff_get(); log_debug("usable_ram_top = %lx\n", ho->arch.usable_ram_top); diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 70eebb4bd22..3876c3f7f98 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -2,7 +2,6 @@ menu "Xtensa architecture" depends on XTENSA config SYS_ARCH - string default "xtensa" config SYS_CPU diff --git a/arch/xtensa/lib/bootm.c b/arch/xtensa/lib/bootm.c index 1de06b7fb53..2958f207397 100644 --- a/arch/xtensa/lib/bootm.c +++ b/arch/xtensa/lib/bootm.c @@ -197,16 +197,3 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) return 1; } - -static ulong get_sp(void) -{ - ulong ret; - - asm("mov %0, a1" : "=r"(ret) : ); - return ret; -} - -void arch_lmb_reserve(struct lmb *lmb) -{ - arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); -} diff --git a/board/Marvell/octeon_ebb7304/Kconfig b/board/Marvell/octeon_ebb7304/Kconfig index b3244f751b1..c8dd0268f36 100644 --- a/board/Marvell/octeon_ebb7304/Kconfig +++ b/board/Marvell/octeon_ebb7304/Kconfig @@ -1,11 +1,9 @@ if TARGET_OCTEON_EBB7304 config SYS_BOARD - string default "octeon_ebb7304" config SYS_VENDOR - string default "Marvell" config SYS_CONFIG_NAME diff --git a/board/Marvell/octeon_nic23/Kconfig b/board/Marvell/octeon_nic23/Kconfig index 468bbb756e6..ad8d5083354 100644 --- a/board/Marvell/octeon_nic23/Kconfig +++ b/board/Marvell/octeon_nic23/Kconfig @@ -1,11 +1,9 @@ if TARGET_OCTEON_NIC23 config SYS_BOARD - string default "octeon_nic23" config SYS_VENDOR - string default "Marvell" config SYS_CONFIG_NAME diff --git a/board/Marvell/octeontx/Kconfig b/board/Marvell/octeontx/Kconfig index 45d115916c9..bdedd24b7a8 100644 --- a/board/Marvell/octeontx/Kconfig +++ b/board/Marvell/octeontx/Kconfig @@ -1,11 +1,9 @@ if TARGET_OCTEONTX_81XX || TARGET_OCTEONTX_83XX config SYS_VENDOR - string default "Marvell" config SYS_BOARD - string default "octeontx" config SYS_CONFIG_NAME diff --git a/board/Marvell/octeontx2/Kconfig b/board/Marvell/octeontx2/Kconfig index 99291d795b5..8664b3e3e50 100644 --- a/board/Marvell/octeontx2/Kconfig +++ b/board/Marvell/octeontx2/Kconfig @@ -1,11 +1,9 @@ if TARGET_OCTEONTX2_95XX || TARGET_OCTEONTX2_96XX config SYS_VENDOR - string default "Marvell" config SYS_BOARD - string default "octeontx2" config SYS_CONFIG_NAME diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c index cc3a6624155..b9f47006d61 100644 --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c @@ -189,7 +189,7 @@ int board_late_init(void) return 0; } -#ifdef CONFIG_SPL_MMC +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR #define UBOOT_RAW_SECTOR_OFFSET 0x40 unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sector) @@ -203,4 +203,4 @@ unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; } } -#endif /* CONFIG_SPL_MMC */ +#endif /* CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR */ diff --git a/board/aspeed/ibex_ast2700/Kconfig b/board/aspeed/ibex_ast2700/Kconfig new file mode 100644 index 00000000000..469cea58d12 --- /dev/null +++ b/board/aspeed/ibex_ast2700/Kconfig @@ -0,0 +1,21 @@ +if TARGET_ASPEED_AST2700_IBEX + +config SYS_BOARD + default "ibex_ast2700" + +config SYS_VENDOR + default "aspeed" + +config SYS_CPU + default "ast2700" + +config SYS_CONFIG_NAME + default "ibex_ast2700" + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select RISCV_AST2700 + select SUPPORT_SPL + imply SPL_DRIVERS_MISC + +endif diff --git a/board/aspeed/ibex_ast2700/MAINTAINERS b/board/aspeed/ibex_ast2700/MAINTAINERS new file mode 100644 index 00000000000..777f582a20d --- /dev/null +++ b/board/aspeed/ibex_ast2700/MAINTAINERS @@ -0,0 +1,7 @@ +AST2700 using Ibex RISC-V Core as the boot MCU +M: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> +S: Maintained +F: arch/riscv/include/asm/arch-ast2700/ +F: board/aspeed/ibex_ast2700/ +F: configs/ibex-ast2700_defconfig +F: include/configs/ibex_ast2700.h diff --git a/board/aspeed/ibex_ast2700/Makefile b/board/aspeed/ibex_ast2700/Makefile new file mode 100644 index 00000000000..3d8eea9166d --- /dev/null +++ b/board/aspeed/ibex_ast2700/Makefile @@ -0,0 +1,3 @@ +obj-y += ibex_ast2700.o +obj-y += fmc_hdr.o +obj-y += sli.o diff --git a/board/aspeed/ibex_ast2700/fmc_hdr.c b/board/aspeed/ibex_ast2700/fmc_hdr.c new file mode 100644 index 00000000000..2068a906f60 --- /dev/null +++ b/board/aspeed/ibex_ast2700/fmc_hdr.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) Aspeed Technology Inc. + */ + +#include <asm/arch/fmc_hdr.h> +#include <asm/io.h> +#include <asm/sections.h> +#include <errno.h> +#include <spl.h> +#include <string.h> + +int fmc_hdr_get_prebuilt(uint32_t type, uint32_t *ofst, uint32_t *size) +{ + struct fmc_hdr_preamble *preamble; + struct fmc_hdr_body *body; + struct fmc_hdr *hdr; + uint32_t t, s, o; + int i; + + if (type >= PBT_NUM) + return -EINVAL; + + if (!ofst || !size) + return -EINVAL; + + hdr = (struct fmc_hdr *)(_start - sizeof(*hdr)); + preamble = &hdr->preamble; + body = &hdr->body; + + if (preamble->magic != HDR_MAGIC) + return -EIO; + + for (i = 0, o = sizeof(*hdr) + body->fmc_size; i < HDR_PB_MAX; ++i) { + t = body->pbs[i].type; + s = body->pbs[i].size; + + /* skip if unrecognized, yet */ + if (t >= PBT_NUM) { + o += s; + continue; + } + + /* prebuilt end mark */ + if (t == 0 && s == 0) + break; + + /* return the prebuilt info if found */ + if (t == type) { + *ofst = o; + *size = s; + + goto found; + } + + /* update offset for next prebuilt */ + o += s; + } + + return -ENODATA; + +found: + return 0; +} diff --git a/board/aspeed/ibex_ast2700/ibex_ast2700.c b/board/aspeed/ibex_ast2700/ibex_ast2700.c new file mode 100644 index 00000000000..e697f9b8baa --- /dev/null +++ b/board/aspeed/ibex_ast2700/ibex_ast2700.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#include <asm/io.h> +#include <asm/arch/sli.h> +#include <dm.h> +#include <ram.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int ret; + struct udevice *dev; + struct ram_info ram; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("cannot get DRAM driver\n"); + return ret; + } + + ret = ram_get_info(dev, &ram); + if (ret) { + printf("cannot get DRAM information\n"); + return ret; + } + + gd->ram_size = ram.size; + + return 0; +} + +int spl_board_init_f(void) +{ + sli_init(); + + dram_init(); + + return 0; +} + +struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) +{ + return (struct legacy_img_hdr *)CONFIG_SYS_LOAD_ADDR; +} + +void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) +{ + return (void *)spl_get_load_buffer(sectors, bl_len); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_RAM; +} + +int board_init(void) +{ + struct udevice *dev; + int i = 0; + int ret; + + /* + * Loop over all MISC uclass drivers to call the comphy code + * and init all CP110 devices enabled in the DT + */ + while (1) { + /* Call the comphy code via the MISC uclass driver */ + ret = uclass_get_device(UCLASS_MISC, i++, &dev); + + /* We're done, once no further CP110 device is found */ + if (ret) + break; + } + + return 0; +} + +int board_late_init(void) +{ + return 0; +} diff --git a/board/aspeed/ibex_ast2700/sli.c b/board/aspeed/ibex_ast2700/sli.c new file mode 100644 index 00000000000..7868111d844 --- /dev/null +++ b/board/aspeed/ibex_ast2700/sli.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#include <asm/io.h> +#include <asm/arch/sli.h> +#include <asm/arch/scu.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> + +#define SLI_POLL_TIMEOUT_US 100 + +static void sli_clear_interrupt_status(uint32_t base) +{ + writel(-1, (void *)base + SLI_INTR_STATUS); +} + +static int sli_wait(uint32_t base, uint32_t mask) +{ + uint32_t value; + + sli_clear_interrupt_status(base); + + do { + value = readl((void *)base + SLI_INTR_STATUS); + if (value & SLI_INTR_RX_ERRORS) + return -1; + } while ((value & mask) != mask); + + return 0; +} + +static int sli_wait_suspend(uint32_t base) +{ + return sli_wait(base, SLI_INTR_TX_SUSPEND | SLI_INTR_RX_SUSPEND); +} + +/* + * CPU die --- downstream pads ---> I/O die + * CPU die <--- upstream pads ----- I/O die + * + * US/DS PAD[3:0] : SLIM[3:0] + * US/DS PAD[5:4] : SLIH[1:0] + * US/DS PAD[7:6] : SLIV[1:0] + */ +int sli_init(void) +{ + uint32_t value; + + /* The following training sequence is designed for AST2700A0 */ + value = FIELD_GET(SCU1_REVISION_HWID, readl(SCU1_REVISION)); + if (value) + return 0; + + /* Return if SLI had been calibrated */ + value = readl((void *)SLIH_IOD_BASE + SLI_CTRL_III); + value = FIELD_GET(SLI_CLK_SEL, value); + if (value) { + debug("SLI has been initialized\n"); + return 0; + } + + /* 25MHz PAD delay for AST2700A0 */ + value = SLI_RX_PHY_LAH_SEL_NEG | SLI_TRANS_EN | SLI_CLEAR_BUS; + writel(value, (void *)SLIH_IOD_BASE + SLI_CTRL_I); + writel(value, (void *)SLIM_IOD_BASE + SLI_CTRL_I); + writel(value | SLIV_RAW_MODE, (void *)SLIV_IOD_BASE + SLI_CTRL_I); + sli_wait_suspend(SLIH_IOD_BASE); + sli_wait_suspend(SLIH_CPU_BASE); + + return 0; +} diff --git a/board/cadence/xtfpga/Kconfig b/board/cadence/xtfpga/Kconfig index a64961e6d6a..9d3a7aa67ac 100644 --- a/board/cadence/xtfpga/Kconfig +++ b/board/cadence/xtfpga/Kconfig @@ -17,11 +17,9 @@ config XTFPGA_KC705 endchoice config SYS_BOARD - string default "xtfpga" config SYS_VENDOR - string default "cadence" config SYS_CONFIG_NAME diff --git a/board/cavium/thunderx/Kconfig b/board/cavium/thunderx/Kconfig index 3d4b260ea29..1add150b45d 100644 --- a/board/cavium/thunderx/Kconfig +++ b/board/cavium/thunderx/Kconfig @@ -1,15 +1,12 @@ if TARGET_THUNDERX_88XX config SYS_CPU - string default "armv8" config SYS_BOARD - string default "thunderx" config SYS_VENDOR - string default "cavium" config SYS_CONFIG_NAME diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c index 616842e62f4..f16f2f1184f 100644 --- a/board/cobra5272/flash.c +++ b/board/cobra5272/flash.c @@ -11,7 +11,7 @@ #include <irq_func.h> #include <stdio.h> #include <time.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <vsprintf.h> #include <linux/delay.h> #include <linux/string.h> diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c index c1935898533..f81b7274556 100644 --- a/board/data_modul/imx8mp_edm_sbc/spl.c +++ b/board/data_modul/imx8mp_edm_sbc/spl.c @@ -100,7 +100,10 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) if (boot_dev_spl == MMC3_BOOT) /* eMMC */ return BOOT_DEVICE_MMC2; - return BOOT_DEVICE_MMC1; /* SD */ + if (boot_dev_spl == SD2_BOOT) /* SD */ + return BOOT_DEVICE_MMC1; + + return BOOT_DEVICE_BOOTROM; /* USB SDPS */ } void board_boot_order(u32 *spl_boot_list) diff --git a/board/egnite/ethernut5/Kconfig b/board/egnite/ethernut5/Kconfig deleted file mode 100644 index 5a6c1c5de1f..00000000000 --- a/board/egnite/ethernut5/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ETHERNUT5 - -config SYS_BOARD - default "ethernut5" - -config SYS_VENDOR - default "egnite" - -config SYS_CONFIG_NAME - default "ethernut5" - -endif diff --git a/board/egnite/ethernut5/MAINTAINERS b/board/egnite/ethernut5/MAINTAINERS deleted file mode 100644 index a4ad913b630..00000000000 --- a/board/egnite/ethernut5/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ETHERNUT5 BOARD -M: egnite GmbH <info@egnite.de> -S: Maintained -F: board/egnite/ethernut5/ -F: include/configs/ethernut5.h -F: configs/ethernut5_defconfig diff --git a/board/egnite/ethernut5/Makefile b/board/egnite/ethernut5/Makefile deleted file mode 100644 index 580f440564e..00000000000 --- a/board/egnite/ethernut5/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2010 -# egnite GmbH - -obj-y += ethernut5.o -obj-y += ethernut5_pwrman.o diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c deleted file mode 100644 index 64e341c3779..00000000000 --- a/board/egnite/ethernut5/ethernut5.c +++ /dev/null @@ -1,198 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011 - * egnite GmbH <info@egnite.de> - * - * (C) Copyright 2010 - * Ole Reinhardt <ole.reinhardt@thermotemp.de> - */ - -/* - * Ethernut 5 general board support - * - * Ethernut is an open source hardware and software project for - * embedded Ethernet devices. Hardware layouts and CAD files are - * freely available under BSD-like license. - * - * Ethernut 5 is the first member of the Ethernut board family - * with U-Boot and Linux support. This implementation is based - * on the original work done by Ole Reinhardt, but heavily modified - * to support additional features and the latest board revision 5.0F. - * - * Main board components are by default: - * - * Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash - * 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM - * 512 MBytes Micron MT29F4G08ABADA NAND Flash - * 4 MBytes Atmel AT45DB321D DataFlash - * SMSC LAN8710 Ethernet PHY - * Atmel ATmega168 MCU used for power management - * Linear Technology LTC4411 PoE controller - * - * U-Boot relevant board interfaces are: - * - * 100 Mbit Ethernet with IEEE 802.3af PoE - * RS-232 serial port - * USB host and device - * MMC/SD-Card slot - * Expansion port with I2C, SPI and more... - * - * Typically the U-Boot image is loaded from serial DataFlash into - * SDRAM by the samboot boot loader, which is located in internal - * NOR Flash and provides all essential initializations like CPU - * and peripheral clocks and, of course, the SDRAM configuration. - * - * For testing purposes it is also possibly to directly transfer - * the image into SDRAM via JTAG. A tested configuration exists - * for the Turtelizer 2 hardware dongle and the OpenOCD software. - * In this case the latter will do the basic hardware configuration - * via its reset-init script. - * - * For additional information visit the project home page at - * http://www.ethernut.de/ - */ - -#include <config.h> -#include <init.h> -#include <net.h> -#include <netdev.h> -#include <miiphy.h> -#include <i2c.h> -#include <mmc.h> -#include <atmel_mci.h> -#include <asm/global_data.h> - -#include <asm/arch/at91sam9260.h> -#include <asm/arch/at91sam9260_matrix.h> -#include <asm/arch/at91sam9_smc.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/clk.h> -#include <asm/arch/gpio.h> -#include <asm/io.h> -#include <asm/gpio.h> - -#include "ethernut5_pwrman.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * This is called last during early initialization. Most of the basic - * hardware interfaces are up and running. - * - * The SDRAM hardware has been configured by the first stage boot loader. - * We only need to announce its size, using u-boot's memory check. - */ -int dram_init(void) -{ - gd->ram_size = get_ram_size( - (void *)CFG_SYS_SDRAM_BASE, - CFG_SYS_SDRAM_SIZE); - return 0; -} - -#ifdef CONFIG_CMD_NAND -static void ethernut5_nand_hw_init(void) -{ - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - unsigned long csa; - - /* Assign CS3 to NAND/SmartMedia Interface */ - csa = readl(&matrix->ebicsa); - csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; - writel(csa, &matrix->ebicsa); - - /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), - &smc->cs[3].setup); - writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | - AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), - &smc->cs[3].pulse); - writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), - &smc->cs[3].cycle); - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | - AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(2), - &smc->cs[3].mode); - -#ifdef CFG_SYS_NAND_READY_PIN - /* Ready pin is optional. */ - at91_set_pio_input(CFG_SYS_NAND_READY_PIN, 1); -#endif - gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1); -} -#endif - -/* - * This is called first during late initialization. - */ -int board_init(void) -{ - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - - /* Set adress of boot parameters. */ - gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; - /* Initialize UARTs and power management. */ - ethernut5_power_init(); -#ifdef CONFIG_CMD_NAND - ethernut5_nand_hw_init(); -#endif - return 0; -} - -#ifdef CONFIG_MACB -/* - * This is optionally called last during late initialization. - */ -int board_eth_init(struct bd_info *bis) -{ - const char *devname; - unsigned short mode; - - at91_periph_clk_enable(ATMEL_ID_EMAC0); - - /* Need to reset PHY via power management. */ - ethernut5_phy_reset(); - /* Set peripheral pins. */ - at91_macb_hw_init(); - /* Basic EMAC initialization. */ - if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CFG_PHY_ID)) - return -1; - /* - * Early board revisions have a pull-down at the PHY's MODE0 - * strap pin, which forces the PHY into power down. Here we - * switch to all-capable mode. - */ - devname = miiphy_get_current_dev(); - if (miiphy_read(devname, 0, 18, &mode) == 0) { - /* Set mode[2:0] to 0b111. */ - mode |= 0x00E0; - miiphy_write(devname, 0, 18, mode); - /* Soft reset overrides strap pins. */ - miiphy_write(devname, 0, MII_BMCR, BMCR_RESET); - } - /* Sync environment with network devices, needed for nfsroot. */ - return eth_init(); -} -#endif - -#ifdef CONFIG_GENERIC_ATMEL_MCI -int board_mmc_init(struct bd_info *bd) -{ - at91_periph_clk_enable(ATMEL_ID_MCI); - - /* Initialize MCI hardware. */ - at91_mci_hw_init(); - /* Register the device. */ - return atmel_mci_init((void *)ATMEL_BASE_MCI); -} - -int board_mmc_getcd(struct mmc *mmc) -{ - return !at91_get_pio_value(CFG_SYS_MMC_CD_PIN); -} -#endif diff --git a/board/egnite/ethernut5/ethernut5_pwrman.c b/board/egnite/ethernut5/ethernut5_pwrman.c deleted file mode 100644 index 42e1914a875..00000000000 --- a/board/egnite/ethernut5/ethernut5_pwrman.c +++ /dev/null @@ -1,323 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011 - * egnite GmbH <info@egnite.de> - */ - -/* - * Ethernut 5 power management support - * - * This board may be supplied via USB, IEEE 802.3af PoE or an - * auxiliary DC input. An on-board ATmega168 microcontroller, - * the so called power management controller or PMC, is used - * to select the supply source and to switch on and off certain - * energy consuming board components. This allows to reduce the - * total stand-by consumption to less than 70mW. - * - * The main CPU communicates with the PMC via I2C. When - * CONFIG_CMD_BSP is defined in the board configuration file, - * then the board specific command 'pwrman' becomes available, - * which allows to manually deal with the PMC. - * - * Two distinct registers are provided by the PMC for enabling - * and disabling specific features. This avoids the often seen - * read-modify-write cycle or shadow register requirement. - * Additional registers are available to query the board - * status and temperature, the auxiliary voltage and to control - * the green user LED that is integrated in the reset switch. - * - * Note, that the AVR firmware of the PMC is released under BSDL. - * - * For additional information visit the project home page at - * http://www.ethernut.de/ - */ -#include <command.h> -#include <vsprintf.h> -#include <asm/arch/at91sam9260.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/gpio.h> -#include <asm/io.h> -#include <i2c.h> -#include <linux/delay.h> - -#include "ethernut5_pwrman.h" - -/* PMC firmware version */ -static int pwrman_major; -static int pwrman_minor; - -/* - * Enable Ethernut 5 power management. - * - * This function must be called during board initialization. - * While we are using u-boot's I2C subsystem, it may be required - * to enable the serial port before calling this function, - * in particular when debugging is enabled. - * - * If board specific commands are not available, we will activate - * all board components. - */ -void ethernut5_power_init(void) -{ - pwrman_minor = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VERS); - pwrman_major = pwrman_minor >> 4; - pwrman_minor &= 15; - -#ifndef CONFIG_CMD_BSP - /* Do not modify anything, if we do not have a known version. */ - if (pwrman_major == 2) { - /* Without board specific commands we enable all features. */ - i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, ~PWRMAN_ETHRST); - i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST); - } -#endif -} - -/* - * Reset Ethernet PHY. - * - * This function allows the re-configure the PHY after - * changing its strap pins. - */ -void ethernut5_phy_reset(void) -{ - /* Do not modify anything, if we do not have a known version. */ - if (pwrman_major != 2) - return; - - /* - * Make sure that the Ethernet clock is enabled and the PHY reset - * is disabled for at least 100 us. - */ - i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHCLK); - i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST); - udelay(100); - - /* - * LAN8710 strap pins are - * PA14 => PHY MODE0 - * PA15 => PHY MODE1 - * PA17 => PHY MODE2 => 111b all capable - * PA18 => PHY ADDR0 => 0b - */ - at91_set_pio_input(AT91_PIO_PORTA, 14, 1); - at91_set_pio_input(AT91_PIO_PORTA, 15, 1); - at91_set_pio_input(AT91_PIO_PORTA, 17, 1); - at91_set_pio_input(AT91_PIO_PORTA, 18, 0); - - /* Activate PHY reset for 100 us. */ - i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHRST); - udelay(100); - i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST); - - at91_set_pio_input(AT91_PIO_PORTA, 14, 1); -} - -/* - * Output the firmware version we got during initialization. - */ -void ethernut5_print_version(void) -{ - printf("%u.%u\n", pwrman_major, pwrman_minor); -} - -/* - * All code below this point is optional and implements - * the 'pwrman' command. - */ -#ifdef CONFIG_CMD_BSP - -/* Human readable names of PMC features */ -char *pwrman_feat[8] = { - "board", "vbin", "vbout", "mmc", - "rs232", "ethclk", "ethrst", "wakeup" -}; - -/* - * Print all feature names, that have its related flags enabled. - */ -static void print_flagged_features(u8 flags) -{ - int i; - - for (i = 0; i < 8; i++) { - if (flags & (1 << i)) - printf("%s ", pwrman_feat[i]); - } -} - -/* - * Return flags of a given list of feature names. - * - * The function stops at the first unknown list entry and - * returns the number of detected names as a function result. - */ -static int feature_flags(char * const names[], int num, u8 *flags) -{ - int i, j; - - *flags = 0; - for (i = 0; i < num; i++) { - for (j = 0; j < 8; j++) { - if (strcmp(pwrman_feat[j], names[i]) == 0) { - *flags |= 1 << j; - break; - } - } - if (j > 7) - break; - } - return i; -} - -void ethernut5_print_power(void) -{ - u8 flags; - int i; - - flags = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA); - for (i = 0; i < 2; i++) { - if (flags) { - print_flagged_features(flags); - printf("%s\n", i ? "off" : "on"); - } - flags = ~flags; - } -} - -void ethernut5_print_celsius(void) -{ - int val; - - /* Read ADC value from LM50 and return Celsius degrees. */ - val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_TEMP); - val *= 5000; /* 100mV/degree with 5V reference */ - val += 128; /* 8 bit resolution */ - val /= 256; - val -= 450; /* Celsius offset, still x10 */ - /* Output full degrees. */ - printf("%d\n", (val + 5) / 10); -} - -void ethernut5_print_voltage(void) -{ - int val; - - /* Read ADC value from divider and return voltage. */ - val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VAUX); - /* Resistors are 100k and 12.1k */ - val += 5; - val *= 180948; - val /= 100000; - val++; - /* Calculation was done in 0.1V units. */ - printf("%d\n", (val + 5) / 10); -} - -/* - * Process the board specific 'pwrman' command. - */ -int do_pwrman(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - u8 val; - int i; - - if (argc == 1) { - ethernut5_print_power(); - } else if (argc == 2 && strcmp(argv[1], "reset") == 0) { - at91_set_pio_output(AT91_PIO_PORTB, 8, 1); - udelay(100); - at91_set_pio_output(AT91_PIO_PORTB, 8, 0); - udelay(100000); - } else if (argc == 2 && strcmp(argv[1], "temp") == 0) { - ethernut5_print_celsius(); - } else if (argc == 2 && strcmp(argv[1], "vaux") == 0) { - ethernut5_print_voltage(); - } else if (argc == 2 && strcmp(argv[1], "version") == 0) { - ethernut5_print_version(); - } else if (strcmp(argv[1], "led") == 0) { - /* Control the green status LED. Blink frequency unit - ** is 0.1s, very roughly. */ - if (argc == 2) { - /* No more arguments, output current settings. */ - val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL); - printf("led %u %u\n", val >> 4, val & 15); - } else { - /* First argument specifies the on-time. */ - val = (u8) simple_strtoul(argv[2], NULL, 0); - val <<= 4; - if (argc > 3) { - /* Second argument specifies the off-time. */ - val |= (u8) (simple_strtoul(argv[3], NULL, 0) - & 15); - } - /* Update the LED control register. */ - i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL, val); - } - } else { - /* We expect a list of features followed an optional status. */ - argc--; - i = feature_flags(&argv[1], argc, &val); - if (argc == i) { - /* We got a list only, print status. */ - val &= i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_STA); - if (val) { - if (i > 1) - print_flagged_features(val); - printf("active\n"); - } else { - printf("inactive\n"); - } - } else { - /* More arguments. */ - if (i == 0) { - /* No given feature, use despensibles. */ - val = PWRMAN_DISPENSIBLE; - } - if (strcmp(argv[i + 1], "on") == 0) { - /* Enable features. */ - i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, - val); - } else if (strcmp(argv[i + 1], "off") == 0) { - /* Disable features. */ - i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, - val); - } else { - printf("Bad parameter %s\n", argv[i + 1]); - return 1; - } - } - } - return 0; -} - -U_BOOT_CMD( - pwrman, CONFIG_SYS_MAXARGS, 1, do_pwrman, - "power management", - "- print settings\n" - "pwrman feature ...\n" - " - print status\n" - "pwrman [feature ...] on|off\n" - " - enable/disable specified or all dispensible features\n" - "pwrman led [on-time [off-time]]\n" - " - print or set led blink timer\n" - "pwrman temp\n" - " - print board temperature (Celsius)\n" - "pwrman vaux\n" - " - print auxiliary input voltage\n" - "pwrman reset\n" - " - reset power management controller\n" - "pwrman version\n" - " - print firmware version\n" - "\n" - " features, (*)=dispensible:\n" - " board - 1.8V and 3.3V supply\n" - " vbin - supply via USB device connector\n" - " vbout - USB host connector supply(*)\n" - " mmc - MMC slot supply(*)\n" - " rs232 - RS232 driver\n" - " ethclk - Ethernet PHY clock(*)\n" - " ethrst - Ethernet PHY reset\n" - " wakeup - RTC alarm" -); -#endif /* CONFIG_CMD_BSP */ diff --git a/board/egnite/ethernut5/ethernut5_pwrman.h b/board/egnite/ethernut5/ethernut5_pwrman.h deleted file mode 100644 index 103f5583289..00000000000 --- a/board/egnite/ethernut5/ethernut5_pwrman.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * egnite GmbH <info@egnite.de> - */ - -/* - * Ethernut 5 power management support - * - * For additional information visit the project home page at - * http://www.ethernut.de/ - */ - -/* I2C address of the PMC */ -#define PWRMAN_I2C_ADDR 0x22 - -/* PMC registers */ -#define PWRMAN_REG_VERS 0 /* Version register */ -#define PWRMAN_REG_STA 1 /* Feature status register */ -#define PWRMAN_REG_ENA 2 /* Feature enable register */ -#define PWRMAN_REG_DIS 3 /* Feature disable register */ -#define PWRMAN_REG_TEMP 4 /* Board temperature */ -#define PWRMAN_REG_VAUX 6 /* Auxiliary input voltage */ -#define PWRMAN_REG_LEDCTL 8 /* LED blinking timer. */ - -/* Feature flags used in status, enable and disable registers */ -#define PWRMAN_BOARD 0x01 /* 1.8V and 3.3V supply */ -#define PWRMAN_VBIN 0x02 /* VBUS input at device connector */ -#define PWRMAN_VBOUT 0x04 /* VBUS output at host connector */ -#define PWRMAN_MMC 0x08 /* Memory card supply */ -#define PWRMAN_RS232 0x10 /* RS-232 driver shutdown */ -#define PWRMAN_ETHCLK 0x20 /* Ethernet clock enable */ -#define PWRMAN_ETHRST 0x40 /* Ethernet PHY reset */ -#define PWRMAN_WAKEUP 0x80 /* RTC wake-up */ - -/* Features, which are not essential to keep u-boot alive */ -#define PWRMAN_DISPENSIBLE (PWRMAN_VBOUT | PWRMAN_MMC | PWRMAN_ETHCLK) - -/* Enable Ethernut 5 power management. */ -extern void ethernut5_power_init(void); - -/* Reset Ethernet PHY. */ -extern void ethernut5_phy_reset(void); - -extern void ethernut5_print_version(void); - -#ifdef CONFIG_CMD_BSP -extern void ethernut5_print_power(void); -extern void ethernut5_print_celsius(void); -extern void ethernut5_print_voltage(void); -#endif diff --git a/board/freescale/imxrt1020-evk/Kconfig b/board/freescale/imxrt1020-evk/Kconfig index 3cb8fb1e6e9..6618a9b3b57 100644 --- a/board/freescale/imxrt1020-evk/Kconfig +++ b/board/freescale/imxrt1020-evk/Kconfig @@ -1,15 +1,12 @@ if TARGET_IMXRT1020_EVK config SYS_BOARD - string default "imxrt1020-evk" config SYS_VENDOR - string default "freescale" config SYS_SOC - string default "imxrt1020" config SYS_CONFIG_NAME diff --git a/board/freescale/imxrt1050-evk/Kconfig b/board/freescale/imxrt1050-evk/Kconfig index 068130beca9..04ade6ec900 100644 --- a/board/freescale/imxrt1050-evk/Kconfig +++ b/board/freescale/imxrt1050-evk/Kconfig @@ -1,15 +1,12 @@ if TARGET_IMXRT1050_EVK config SYS_BOARD - string default "imxrt1050-evk" config SYS_VENDOR - string default "freescale" config SYS_SOC - string default "imxrt1050" config SYS_CONFIG_NAME diff --git a/board/freescale/imxrt1170-evk/Kconfig b/board/freescale/imxrt1170-evk/Kconfig index b433d6e5df0..ad7cd4aeb9c 100644 --- a/board/freescale/imxrt1170-evk/Kconfig +++ b/board/freescale/imxrt1170-evk/Kconfig @@ -1,15 +1,12 @@ if TARGET_IMXRT1170_EVK config SYS_BOARD - string default "imxrt1170-evk" config SYS_VENDOR - string default "freescale" config SYS_SOC - string default "imxrt1170" config SYS_CONFIG_NAME diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index 44d9782d729..7fc4fecf774 100644 --- a/board/freescale/ls2080ardb/eth_ls2080rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -12,7 +12,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_eth_init(struct bd_info *bis) { -#ifdef CONFIG_PHY_AQUANTIA +#if defined(CONFIG_PHY_AQUANTIA) && !defined(CONFIG_SPL_BUILD) /* * Export functions to be used by AQ firmware * upload application diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c index c8cbc5a15fa..b32dfc6b570 100644 --- a/board/friendlyarm/nanopi2/board.c +++ b/board/friendlyarm/nanopi2/board.c @@ -11,6 +11,7 @@ #ifdef CONFIG_PWM_NX #include <pwm.h> #endif +#include <video.h> #include <asm/global_data.h> #include <asm/io.h> @@ -492,12 +493,8 @@ int splash_screen_prepare(void) ARRAY_SIZE(splash_locations)); } - if (!err) { - char addr[64]; - - sprintf(addr, "0x%lx", gd->fb_base); - env_set("fb_addr", addr); - } + if (!err) + env_set_hex("fb_addr", video_get_fb()); return err; } diff --git a/board/gardena/smart-gateway-mt7688/board.c b/board/gardena/smart-gateway-mt7688/board.c index c6b14bed41f..eb7fcd630a1 100644 --- a/board/gardena/smart-gateway-mt7688/board.c +++ b/board/gardena/smart-gateway-mt7688/board.c @@ -16,7 +16,7 @@ #include <linux/delay.h> #include <linux/stringify.h> #include <u-boot/crc.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <linux/ctype.h> #include <linux/io.h> diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index e9cdede6214..002d7bbf864 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -366,8 +366,8 @@ unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long { if (!IS_SD(mmc)) { switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) { - case 1: - case 2: + case EMMC_BOOT_PART_BOOT1: + case EMMC_BOOT_PART_BOOT2: if (IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)) raw_sect -= 32 * 2; break; @@ -379,16 +379,24 @@ unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long const char *spl_board_loader_name(u32 boot_device) { + static char name[16]; + struct mmc *mmc; + switch (boot_device) { /* SDHC2 */ case BOOT_DEVICE_MMC1: - return "eMMC"; + mmc_init_device(0); + mmc = find_mmc_device(0); + mmc_init(mmc); + snprintf(name, sizeof(name), "eMMC %s", emmc_hwpart_names[EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)]); + return name; /* SDHC3 */ case BOOT_DEVICE_MMC2: - return "SD card"; - default: - return NULL; + sprintf(name, "SD card"); + return name; } + + return NULL; } void spl_board_init(void) diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index d4c22121497..98b33624f04 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -157,20 +157,20 @@ int board_late_init(void) int bootpart; switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) { - case 1: /* boot0 */ - bootpart = 1; + case EMMC_BOOT_PART_BOOT1: + bootpart = EMMC_HWPART_BOOT1; break; - case 2: /* boot1 */ - bootpart = 2; + case EMMC_BOOT_PART_BOOT2: + bootpart = EMMC_HWPART_BOOT2; break; - case 7: /* user */ + case EMMC_BOOT_PART_USER: default: - bootpart = 0; + bootpart = EMMC_HWPART_DEFAULT; break; } /* IMX8MP/IMX8MN BOOTROM v2 uses offset=0 for boot parts */ if ((IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)) && - (bootpart == 1 || bootpart == 2)) + (bootpart == EMMC_BOOT_PART_BOOT1 || bootpart == EMMC_BOOT_PART_BOOT2)) bootblk = 0; env_set_hex("bootpart", bootpart); env_set_hex("bootblk", bootblk); @@ -201,10 +201,10 @@ uint mmc_get_env_part(struct mmc *mmc) { if (!IS_SD(mmc)) { switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) { - case 1: - return 1; - case 2: - return 2; + case EMMC_BOOT_PART_BOOT1: + return EMMC_HWPART_BOOT1; + case EMMC_BOOT_PART_BOOT2: + return EMMC_HWPART_BOOT2; } } diff --git a/board/kontron/sl-mx6ul/Kconfig b/board/kontron/sl-mx6ul/Kconfig index 782e099cec2..7a4ffbed289 100644 --- a/board/kontron/sl-mx6ul/Kconfig +++ b/board/kontron/sl-mx6ul/Kconfig @@ -1,11 +1,9 @@ if TARGET_KONTRON_MX6UL config SYS_BOARD - string default "sl-mx6ul" config SYS_VENDOR - string default "kontron" config SYS_CONFIG_NAME diff --git a/board/kontron/sl-mx8mm/Kconfig b/board/kontron/sl-mx8mm/Kconfig index 1cfe9ee64bd..1597bcf894d 100644 --- a/board/kontron/sl-mx8mm/Kconfig +++ b/board/kontron/sl-mx8mm/Kconfig @@ -1,11 +1,9 @@ if TARGET_KONTRON_MX8MM config SYS_BOARD - string default "sl-mx8mm" config SYS_VENDOR - string default "kontron" config SYS_CONFIG_NAME diff --git a/board/phytec/phycore_am62x/MAINTAINERS b/board/phytec/phycore_am62x/MAINTAINERS index 42463ad054e..670c7473481 100644 --- a/board/phytec/phycore_am62x/MAINTAINERS +++ b/board/phytec/phycore_am62x/MAINTAINERS @@ -9,6 +9,7 @@ F: arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts F: board/phytec/phycore_am62x/ F: configs/phycore_am62x_a53_defconfig F: configs/phycore_am62x_r5_defconfig +F: configs/phycore_am62x_r5_usbdfu_defconfig F: include/configs/phycore_am62x.h F: doc/board/phytec/phycore-am62x.rst F: board/phytec/common/k3 diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index 046bbd22f25..711ca3040c4 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -1,5 +1,7 @@ #include <env/ti/k3_dfu.env> #include <env/phytec/k3_mmc.env> +#include <env/phytec/k3_net.env> +#include <env/phytec/k3_spi.env> fdtaddr=0x88000000 loadaddr=0x82000000 @@ -15,3 +17,9 @@ mmcroot=2 mmcpart=1 console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 + +get_cmd=tftp + +spi_fdt_addr=0x700000 +spi_image_addr=0x800000 +spi_ramdisk_addr=0x1e00000 diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env index 18f0fa5b4c3..3032b518e0b 100644 --- a/board/phytec/phycore_am64x/phycore_am64x.env +++ b/board/phytec/phycore_am64x/phycore_am64x.env @@ -1,4 +1,6 @@ #include <env/phytec/k3_mmc.env> +#include <env/phytec/k3_net.env> +#include <env/phytec/k3_spi.env> fdtaddr=0x88000000 loadaddr=0x82000000 @@ -14,3 +16,9 @@ mmcroot=2 mmcpart=1 console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 + +get_cmd=tftp + +spi_fdt_addr=0x700000 +spi_image_addr=0x800000 +spi_ramdisk_addr=0x1e00000 diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c index ef951361844..bf2d5ce01fa 100644 --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c @@ -10,10 +10,34 @@ #include <asm/mach-imx/boot_mode.h> #include <env.h> #include <init.h> +#include <fdt_support.h> +#include <jffs2/load_kernel.h> #include <miiphy.h> +#include <mtd_node.h> + +#include "../common/imx8m_som_detection.h" DECLARE_GLOBAL_DATA_PTR; +#define EEPROM_ADDR 0x51 +#define EEPROM_ADDR_FALLBACK 0x59 + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u8 spi = phytec_get_imx8m_spi(NULL); + /* Do nothing if no SPI is populated */ + if (!spi) + return 0; + + static const struct node_info nodes[] = { + { "jedec,spi-nor", MTD_DEV_TYPE_NOR, }, + }; + + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + + return 0; +} + static int setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = @@ -27,6 +51,11 @@ static int setup_fec(void) int board_init(void) { + int ret = phytec_eeprom_data_setup_fallback(NULL, 0, + EEPROM_ADDR, EEPROM_ADDR_FALLBACK); + if (ret) + printf("%s: EEPROM data init failed\n", __func__); + setup_fec(); return 0; @@ -39,6 +68,11 @@ int board_mmc_get_env_dev(int devno) int board_late_init(void) { + u8 spi = phytec_get_imx8m_spi(NULL); + + if (spi != 0 && spi != PHYTEC_EEPROM_INVAL) + env_set("spiprobe", "sf probe"); + switch (get_boot_device()) { case SD2_BOOT: env_set_ulong("mmcdev", 1); diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env b/board/phytec/phycore_imx8mp/phycore_imx8mp.env index f8f878e8f3a..2c12fc65432 100644 --- a/board/phytec/phycore_imx8mp/phycore_imx8mp.env +++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env @@ -7,6 +7,7 @@ bootcmd= fi; mmc dev ${mmcdev}; if mmc rescan; then + run spiprobe; if test ${doraucboot} = 1; then run raucinit; fi; @@ -27,10 +28,13 @@ fdt_addr_r=0x48000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image ip_dyn=yes +mtdparts=30bb0000.spi:3840k(u-boot),128k(env),128k(env_redund),-(none) +mtdids=nor0=30bb0000.spi +spiprobe=true loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} mmcargs= - setenv bootargs console=${console} + setenv bootargs ${mcore_clk} console=${console} root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw mmcautodetect=yes mmcboot= @@ -51,7 +55,7 @@ mmcdev=CONFIG_SYS_MMC_ENV_DEV mmcpart=1 mmcroot=2 netargs= - setenv bootargs console=${console} root=/dev/nfs ip=dhcp + setenv bootargs ${mcore_clk} console=${console} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp netboot= echo Booting from net ...; @@ -74,4 +78,5 @@ netboot= echo WARN: Cannot load the DT; fi; nfsroot=/srv/nfs +prepare_mcore=setenv mcore_clk clk-imx8mp.mcore_booted sd_dev=1 diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c index a3c421572af..8ca8792fa42 100644 --- a/board/purism/librem5/librem5.c +++ b/board/purism/librem5/librem5.c @@ -42,8 +42,8 @@ uint board_mmc_get_env_part(struct mmc *mmc) { uint part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); - if (part == 7) - part = 0; + if (part == EMMC_BOOT_PART_USER) + part = EMMC_HWPART_DEFAULT; return part; } #endif diff --git a/board/qualcomm/debug-sdm845.config b/board/qualcomm/debug-sdm845.config new file mode 100644 index 00000000000..31ad6d02a3a --- /dev/null +++ b/board/qualcomm/debug-sdm845.config @@ -0,0 +1,5 @@ +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_BASE=0xa84000 +CONFIG_DEBUG_UART_MSM_GENI=y +CONFIG_DEBUG_UART_CLOCK=7372800 diff --git a/board/qualcomm/debug-sm6115.config b/board/qualcomm/debug-sm6115.config new file mode 100644 index 00000000000..131c6e230de --- /dev/null +++ b/board/qualcomm/debug-sm6115.config @@ -0,0 +1,5 @@ +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_BASE=0x4a90000 +CONFIG_DEBUG_UART_MSM_GENI=y +CONFIG_DEBUG_UART_CLOCK=14745600 diff --git a/board/qualcomm/debug-sm8250.config b/board/qualcomm/debug-sm8250.config new file mode 100644 index 00000000000..4d3cc4cc97f --- /dev/null +++ b/board/qualcomm/debug-sm8250.config @@ -0,0 +1,5 @@ +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_BASE=0xa90000 +CONFIG_DEBUG_UART_MSM_GENI=y +CONFIG_DEBUG_UART_CLOCK=14745600 diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 1de1bd68701..8125f064cf1 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -9,6 +9,7 @@ #include <config.h> #include <init.h> +#include <video.h> #include <asm/global_data.h> #include <linux/sizes.h> #include <asm/io.h> @@ -110,11 +111,12 @@ int dram_init_banksize(void) #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard (void) { + ulong fb_base = video_get_fb(); char *ss; printf ("Board : Ronetix PM9263\n"); - switch (gd->fb_base) { + switch (fb_base) { case PHYS_PSRAM: ss = "(PSRAM)"; break; @@ -127,7 +129,7 @@ int checkboard (void) ss = ""; break; } - printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss ); + printf("Video memory : 0x%08lX %s\n", fb_base, ss); printf ("\n"); return 0; diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 802596569c6..d97945e58fc 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -32,34 +32,18 @@ gd_t *gd; #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) -/* GUIDs for capsule updatable firmware images */ -#define SANDBOX_UBOOT_IMAGE_GUID \ - EFI_GUID(0x09d7cf52, 0x0720, 0x4710, 0x91, 0xd1, \ - 0x08, 0x46, 0x9b, 0x7f, 0xe9, 0xc8) - -#define SANDBOX_UBOOT_ENV_IMAGE_GUID \ - EFI_GUID(0x5a7021f5, 0xfef2, 0x48b4, 0xaa, 0xba, \ - 0x83, 0x2e, 0x77, 0x74, 0x18, 0xc0) - -#define SANDBOX_FIT_IMAGE_GUID \ - EFI_GUID(0x3673b45d, 0x6a7c, 0x46f3, 0x9e, 0x60, \ - 0xad, 0xab, 0xb0, 0x3f, 0x79, 0x37) - struct efi_fw_image fw_images[] = { #if defined(CONFIG_EFI_CAPSULE_FIRMWARE_RAW) { - .image_type_id = SANDBOX_UBOOT_IMAGE_GUID, .fw_name = u"SANDBOX-UBOOT", .image_index = 1, }, { - .image_type_id = SANDBOX_UBOOT_ENV_IMAGE_GUID, .fw_name = u"SANDBOX-UBOOT-ENV", .image_index = 2, }, #elif defined(CONFIG_EFI_CAPSULE_FIRMWARE_FIT) { - .image_type_id = SANDBOX_FIT_IMAGE_GUID, .fw_name = u"SANDBOX-FIT", .image_index = 1, }, diff --git a/board/sielaff/imx6dl-sielaff/Kconfig b/board/sielaff/imx6dl-sielaff/Kconfig index 7876ab14c07..cad15ac30b5 100644 --- a/board/sielaff/imx6dl-sielaff/Kconfig +++ b/board/sielaff/imx6dl-sielaff/Kconfig @@ -1,11 +1,9 @@ if TARGET_MX6S_SIELAFF config SYS_BOARD - string default "imx6dl-sielaff" config SYS_VENDOR - string default "sielaff" config SYS_CONFIG_NAME diff --git a/board/siemens/common/board_am335x.c b/board/siemens/common/board_am335x.c index 2a727606bc3..e6537b0675a 100644 --- a/board/siemens/common/board_am335x.c +++ b/board/siemens/common/board_am335x.c @@ -36,7 +36,7 @@ void set_mux_conf_regs(void) /* enable early the console */ gd->baudrate = CONFIG_BAUDRATE; serial_init(); - gd->have_console = 1; + gd->flags |= GD_FLG_HAVE_CONSOLE; siemens_ee_setup(); if (draco_read_eeprom() < 0) diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 6e6e276cc74..5e5a45ee00d 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -15,7 +15,7 @@ #include <env.h> #include <init.h> #include <pci.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <asm/global_data.h> #include <asm/processor.h> #include <asm/immap_85xx.h> diff --git a/board/st/stih410-b2260/Kconfig b/board/st/stih410-b2260/Kconfig index 441a83cbaea..2dd7411b8b4 100644 --- a/board/st/stih410-b2260/Kconfig +++ b/board/st/stih410-b2260/Kconfig @@ -1,15 +1,12 @@ if TARGET_STIH410_B2260 config SYS_BOARD - string default "stih410-b2260" config SYS_VENDOR - string default "st" config SYS_SOC - string default "stih410" config SYS_CONFIG_NAME diff --git a/board/st/stm32f429-discovery/Kconfig b/board/st/stm32f429-discovery/Kconfig index 3c93df20afa..cde6900871a 100644 --- a/board/st/stm32f429-discovery/Kconfig +++ b/board/st/stm32f429-discovery/Kconfig @@ -1,15 +1,12 @@ if TARGET_STM32F429_DISCOVERY config SYS_BOARD - string default "stm32f429-discovery" config SYS_VENDOR - string default "st" config SYS_SOC - string default "stm32f4" config SYS_CONFIG_NAME diff --git a/board/st/stm32f429-evaluation/Kconfig b/board/st/stm32f429-evaluation/Kconfig index eaa40db8a74..b168bf8d5db 100644 --- a/board/st/stm32f429-evaluation/Kconfig +++ b/board/st/stm32f429-evaluation/Kconfig @@ -1,15 +1,12 @@ if TARGET_STM32F429_EVALUATION config SYS_BOARD - string default "stm32f429-evaluation" config SYS_VENDOR - string default "st" config SYS_SOC - string default "stm32f4" config SYS_CONFIG_NAME diff --git a/board/st/stm32f469-discovery/Kconfig b/board/st/stm32f469-discovery/Kconfig index 622a8d82d81..688523b52af 100644 --- a/board/st/stm32f469-discovery/Kconfig +++ b/board/st/stm32f469-discovery/Kconfig @@ -1,15 +1,12 @@ if TARGET_STM32F469_DISCOVERY config SYS_BOARD - string default "stm32f469-discovery" config SYS_VENDOR - string default "st" config SYS_SOC - string default "stm32f4" config SYS_CONFIG_NAME diff --git a/board/st/stm32f746-disco/Kconfig b/board/st/stm32f746-disco/Kconfig index 86ace17377c..382b86e5bc9 100644 --- a/board/st/stm32f746-disco/Kconfig +++ b/board/st/stm32f746-disco/Kconfig @@ -1,15 +1,12 @@ if TARGET_STM32F746_DISCO config SYS_BOARD - string default "stm32f746-disco" config SYS_VENDOR - string default "st" config SYS_SOC - string default "stm32f7" config SYS_CONFIG_NAME diff --git a/board/st/stm32h743-disco/Kconfig b/board/st/stm32h743-disco/Kconfig index bc116bcf32f..0f0f56e1a78 100644 --- a/board/st/stm32h743-disco/Kconfig +++ b/board/st/stm32h743-disco/Kconfig @@ -1,15 +1,12 @@ if TARGET_STM32H743_DISCO config SYS_BOARD - string default "stm32h743-disco" config SYS_VENDOR - string default "st" config SYS_SOC - string default "stm32h7" config SYS_CONFIG_NAME diff --git a/board/st/stm32h743-eval/Kconfig b/board/st/stm32h743-eval/Kconfig index ff86de25f7d..0fffa888e70 100644 --- a/board/st/stm32h743-eval/Kconfig +++ b/board/st/stm32h743-eval/Kconfig @@ -1,15 +1,12 @@ if TARGET_STM32H743_EVAL config SYS_BOARD - string default "stm32h743-eval" config SYS_VENDOR - string default "st" config SYS_SOC - string default "stm32h7" config SYS_CONFIG_NAME diff --git a/board/st/stm32h750-art-pi/Kconfig b/board/st/stm32h750-art-pi/Kconfig index ab2d0f227d7..6bd6a13d2a1 100644 --- a/board/st/stm32h750-art-pi/Kconfig +++ b/board/st/stm32h750-art-pi/Kconfig @@ -1,15 +1,12 @@ if TARGET_STM32H750_ART_PI config SYS_BOARD - string default "stm32h750-art-pi" config SYS_VENDOR - string default "st" config SYS_SOC - string default "stm32h7" config SYS_CONFIG_NAME diff --git a/board/storopack/smegw01/smegw01.c b/board/storopack/smegw01/smegw01.c index 910feeda31f..c9513ddbc68 100644 --- a/board/storopack/smegw01/smegw01.c +++ b/board/storopack/smegw01/smegw01.c @@ -105,8 +105,8 @@ uint mmc_get_env_part(struct mmc *mmc) { uint part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); - if (part == 7) - part = 0; + if (part == EMMC_BOOT_PART_USER) + part = EMMC_HWPART_DEFAULT; return part; } diff --git a/board/sysam/amcore/Kconfig b/board/sysam/amcore/Kconfig index e13ee8f6e90..b5c81dda237 100644 --- a/board/sysam/amcore/Kconfig +++ b/board/sysam/amcore/Kconfig @@ -1,15 +1,12 @@ if TARGET_AMCORE config SYS_CPU - string default "mcf530x" config SYS_BOARD - string default "amcore" config SYS_VENDOR - string default "sysam" config SYS_CONFIG_NAME diff --git a/board/ti/am62x/MAINTAINERS b/board/ti/am62x/MAINTAINERS index 562a5c67669..d7dfefffe75 100644 --- a/board/ti/am62x/MAINTAINERS +++ b/board/ti/am62x/MAINTAINERS @@ -6,5 +6,7 @@ F: board/ti/am62x/ F: include/configs/am62x_evm.h F: configs/am62x_evm_r5_defconfig F: configs/am62x_evm_a53_defconfig +F: configs/am62x_evm_r5_ethboot_defconfig +F: configs/am62x_evm_a53_ethboot_defconfig F: configs/am62x_lpsk_r5_defconfig F: configs/am62x_lpsk_a53_defconfig diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 72d67d90d41..570bf2a27d4 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -290,6 +290,14 @@ int board_init(void) return 0; } +void reset_cpu(void) +{ + sc_pm_reboot(-1, SC_PM_RESET_TYPE_COLD); + + do { + } while (1); +} + #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { diff --git a/board/tq/tqma6/tqma6.c b/board/tq/tqma6/tqma6.c index 445ce987b68..40369f03e72 100644 --- a/board/tq/tqma6/tqma6.c +++ b/board/tq/tqma6/tqma6.c @@ -19,33 +19,15 @@ #include <linux/errno.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/mach-imx/spi.h> -#include <fsl_esdhc_imx.h> #include <linux/libfdt.h> #include <mmc.h> #include <power/pfuze100_pmic.h> #include <power/pmic.h> -#include <spi_flash.h> #include "tqma6_bb.h" DECLARE_GLOBAL_DATA_PTR; -#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -55,114 +37,6 @@ int dram_init(void) static const uint16_t tqma6_emmc_dsr = 0x0100; -#ifndef CONFIG_DM_MMC -/* eMMC on USDHCI3 always present */ -static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = { - NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL), - /* eMMC reset */ - NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL), -}; - -/* - * According to board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 eMMC (SD3) on TQMa6 - * mmc1 .. n optional slots used on baseboard - */ -struct fsl_esdhc_cfg tqma6_usdhc_cfg = { - .esdhc_base = USDHC3_BASE_ADDR, - .max_bus_width = 8, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - if (cfg->esdhc_base == USDHC3_BASE_ADDR) - /* eMMC/uSDHC3 is always present */ - ret = 1; - else - ret = tqma6_bb_board_mmc_getcd(mmc); - - return ret; -} - -int board_mmc_getwp(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - if (cfg->esdhc_base == USDHC3_BASE_ADDR) - /* eMMC/uSDHC3 is always present */ - ret = 0; - else - ret = tqma6_bb_board_mmc_getwp(mmc); - - return ret; -} - -int board_mmc_init(struct bd_info *bis) -{ - imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads, - ARRAY_SIZE(tqma6_usdhc3_pads)); - tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) { - puts("Warning: failed to initialize eMMC dev\n"); - } else { - struct mmc *mmc = find_mmc_device(0); - if (mmc) - mmc_set_dsr(mmc, tqma6_emmc_dsr); - } - - tqma6_bb_board_mmc_init(bis); - - return 0; -} -#endif - -#ifndef CONFIG_DM_SPI -static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = { - /* SS1 */ - NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), -}; - -#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19) - -static unsigned const tqma6_ecspi1_cs[] = { - TQMA6_SF_CS_GPIO, -}; - -__weak void tqma6_iomuxc_spi(void) -{ - unsigned i; - - for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i) - gpio_direction_output(tqma6_ecspi1_cs[i], 1); - imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads, - ARRAY_SIZE(tqma6_ecspi1_pads)); -} - -#if defined(CONFIG_SF_DEFAULT_BUS) && defined(CONFIG_SF_DEFAULT_CS) -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return ((bus == CONFIG_SF_DEFAULT_BUS) && - (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1; -} -#endif -#endif int board_early_init_f(void) { diff --git a/board/tq/tqma6/tqma6_mba6.c b/board/tq/tqma6/tqma6_mba6.c index 877539e359e..b8f76591006 100644 --- a/board/tq/tqma6/tqma6_mba6.c +++ b/board/tq/tqma6/tqma6_mba6.c @@ -31,28 +31,6 @@ #include "tqma6_bb.h" -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - #if defined(CONFIG_TQMA6Q) #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790 @@ -89,17 +67,6 @@ static void mba6_setup_iomuxc_enet(void) (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII); } -static iomux_v3_cfg_t const mba6_uart2_pads[] = { - NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL), -}; - -static void mba6_setup_iomuxc_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads, - ARRAY_SIZE(mba6_uart2_pads)); -} - int board_mmc_get_env_dev(int devno) { /* @@ -159,8 +126,6 @@ int board_phy_config(struct phy_device *phydev) int tqma6_bb_board_early_init_f(void) { - mba6_setup_iomuxc_uart(); - return 0; } diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 0b43407b9e9..1c100d61589 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -12,7 +12,6 @@ #include <image.h> #include <init.h> #include <jffs2/load_kernel.h> -#include <lmb.h> #include <log.h> #include <asm/global_data.h> #include <asm/sections.h> @@ -31,7 +30,7 @@ #include <soc.h> #include <linux/ctype.h> #include <linux/kernel.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include "fru.h" @@ -665,38 +664,6 @@ int embedded_dtb_select(void) } #endif -#if defined(CONFIG_LMB) - -#ifndef MMU_SECTION_SIZE -#define MMU_SECTION_SIZE (1 * 1024 * 1024) -#endif - -phys_addr_t board_get_usable_ram_top(phys_size_t total_size) -{ - phys_size_t size; - phys_addr_t reg; - struct lmb lmb; - - if (!total_size) - return gd->ram_top; - - if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8)) - panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob); - - /* found enough not-reserved memory to relocated U-Boot */ - lmb_init(&lmb); - lmb_add(&lmb, gd->ram_base, gd->ram_size); - boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob); - size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE); - reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE); - - if (!reg) - reg = gd->ram_top - size; - - return reg + size; -} -#endif - #ifdef CONFIG_OF_BOARD_SETUP #define MAX_RAND_SIZE 8 int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/boot/Kconfig b/boot/Kconfig index 7ac34574079..925afe06a19 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -1,5 +1,7 @@ menu "Boot options" +source "lib/efi_loader/Kconfig" + menu "Boot images" config ANDROID_BOOT_IMAGE diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c index 7c7bba088c9..807f8dfb064 100644 --- a/boot/bootdev-uclass.c +++ b/boot/bootdev-uclass.c @@ -632,7 +632,7 @@ int bootdev_next_label(struct bootflow_iter *iter, struct udevice **devp, int bootdev_next_prio(struct bootflow_iter *iter, struct udevice **devp) { - struct udevice *dev = *devp, *last_dev = NULL; + struct udevice *dev = *devp; bool found; int ret; @@ -640,6 +640,7 @@ int bootdev_next_prio(struct bootflow_iter *iter, struct udevice **devp) *devp = NULL; log_debug("next prio %d: dev=%p/%s\n", iter->cur_prio, dev, dev ? dev->name : "none"); + found = false; do { /* * Don't probe devices here since they may not be of the @@ -682,23 +683,13 @@ int bootdev_next_prio(struct bootflow_iter *iter, struct udevice **devp) } } else { ret = device_probe(dev); - if (!ret) - last_dev = dev; - if (ret) { - log_warning("Device '%s' failed to probe\n", + if (ret) + log_debug("Device '%s' failed to probe\n", dev->name); - if (last_dev == dev) { - /* - * We have already tried this device - * and it failed to probe. Give up. - */ - return log_msg_ret("probe", ret); - } - last_dev = dev; - dev = NULL; - } + else + found = true; } - } while (!dev); + } while (!found); *devp = dev; diff --git a/boot/bootm.c b/boot/bootm.c index 480f8e6a0e6..a61bbcfb45c 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -239,30 +239,11 @@ static int boot_get_kernel(const char *addr_fit, struct bootm_headers *images, return 0; } -#ifdef CONFIG_LMB -static void boot_start_lmb(struct bootm_headers *images) -{ - phys_addr_t mem_start; - phys_size_t mem_size; - - mem_start = env_get_bootm_low(); - mem_size = env_get_bootm_size(); - - lmb_init_and_reserve_range(&images->lmb, mem_start, - mem_size, NULL); -} -#else -#define lmb_reserve(lmb, base, size) -static inline void boot_start_lmb(struct bootm_headers *images) { } -#endif - static int bootm_start(void) { memset((void *)&images, 0, sizeof(images)); images.verify = env_get_yesno("verify"); - boot_start_lmb(&images); - bootstage_mark_name(BOOTSTAGE_ID_BOOTM_START, "bootm_start"); images.state = BOOTM_STATE_START; @@ -640,7 +621,7 @@ static int bootm_load_os(struct bootm_headers *images, int boot_progress) if (os.type == IH_TYPE_KERNEL_NOLOAD && os.comp != IH_COMP_NONE) { ulong req_size = ALIGN(image_len * 4, SZ_1M); - load = lmb_alloc(&images->lmb, req_size, SZ_2M); + load = lmb_alloc(req_size, SZ_2M); if (!load) return 1; os.load = load; @@ -714,8 +695,9 @@ static int bootm_load_os(struct bootm_headers *images, int boot_progress) images->os.end = relocated_addr + image_size; } - lmb_reserve(&images->lmb, images->os.load, (load_end - - images->os.load)); + if (CONFIG_IS_ENABLED(LMB)) + lmb_reserve(images->os.load, (load_end - images->os.load)); + return 0; } @@ -1029,19 +1011,19 @@ int bootm_run_states(struct bootm_info *bmi, int states) if (!ret && (states & BOOTM_STATE_RAMDISK)) { ulong rd_len = images->rd_end - images->rd_start; - ret = boot_ramdisk_high(&images->lmb, images->rd_start, - rd_len, &images->initrd_start, &images->initrd_end); + ret = boot_ramdisk_high(images->rd_start, rd_len, + &images->initrd_start, + &images->initrd_end); if (!ret) { env_set_hex("initrd_start", images->initrd_start); env_set_hex("initrd_end", images->initrd_end); } } #endif -#if CONFIG_IS_ENABLED(OF_LIBFDT) && defined(CONFIG_LMB) +#if CONFIG_IS_ENABLED(OF_LIBFDT) && CONFIG_IS_ENABLED(LMB) if (!ret && (states & BOOTM_STATE_FDT)) { - boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr); - ret = boot_relocate_fdt(&images->lmb, &images->ft_addr, - &images->ft_len); + boot_fdt_add_mem_rsv_regions(images->ft_addr); + ret = boot_relocate_fdt(&images->ft_addr, &images->ft_len); } #endif diff --git a/boot/bootm_os.c b/boot/bootm_os.c index 6a6621706f7..e9522cd3299 100644 --- a/boot/bootm_os.c +++ b/boot/bootm_os.c @@ -260,12 +260,11 @@ static void do_bootvx_fdt(struct bootm_headers *images) char *bootline; ulong of_size = images->ft_len; char **of_flat_tree = &images->ft_addr; - struct lmb *lmb = &images->lmb; if (*of_flat_tree) { - boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree); + boot_fdt_add_mem_rsv_regions(*of_flat_tree); - ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size); + ret = boot_relocate_fdt(of_flat_tree, &of_size); if (ret) return; diff --git a/boot/image-android.c b/boot/image-android.c index 09c7a44e058..774565fd1fe 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -393,10 +393,9 @@ int android_image_get_ramdisk(const void *hdr, const void *vendor_boot_img, if (!android_image_get_data(hdr, vendor_boot_img, &img_data)) return -EINVAL; - if (!img_data.ramdisk_size) { - *rd_data = *rd_len = 0; - return -1; - } + if (!img_data.ramdisk_size) + return -ENOENT; + if (img_data.header_version > 2) { ramdisk_ptr = img_data.ramdisk_addr; memcpy((void *)(ramdisk_ptr), (void *)img_data.vendor_ramdisk_ptr, diff --git a/boot/image-board.c b/boot/image-board.c index f2124013046..1757e5816d8 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -427,7 +427,9 @@ static int select_ramdisk(struct bootm_headers *images, const char *select, u8 a unmap_sysmem(ptr); } - if (ret) + if (ret == -ENOENT) + return -ENOPKG; + else if (ret) return ret; done = true; } @@ -515,7 +517,6 @@ int boot_get_ramdisk(char const *select, struct bootm_headers *images, /** * boot_ramdisk_high - relocate init ramdisk - * @lmb: pointer to lmb handle, will be used for memory mgmt * @rd_data: ramdisk data start address * @rd_len: ramdisk data length * @initrd_start: pointer to a ulong variable, will hold final init ramdisk @@ -534,8 +535,8 @@ int boot_get_ramdisk(char const *select, struct bootm_headers *images, * 0 - success * -1 - failure */ -int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, - ulong *initrd_start, ulong *initrd_end) +int boot_ramdisk_high(ulong rd_data, ulong rd_len, ulong *initrd_start, + ulong *initrd_end) { char *s; phys_addr_t initrd_high; @@ -561,13 +562,14 @@ int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, debug(" in-place initrd\n"); *initrd_start = rd_data; *initrd_end = rd_data + rd_len; - lmb_reserve(lmb, rd_data, rd_len); + lmb_reserve(rd_data, rd_len); } else { if (initrd_high) - *initrd_start = (ulong)lmb_alloc_base(lmb, - rd_len, 0x1000, initrd_high); + *initrd_start = (ulong)lmb_alloc_base(rd_len, + 0x1000, + initrd_high); else - *initrd_start = (ulong)lmb_alloc(lmb, rd_len, + *initrd_start = (ulong)lmb_alloc(rd_len, 0x1000); if (*initrd_start == 0) { @@ -800,7 +802,6 @@ int boot_get_loadable(struct bootm_headers *images) /** * boot_get_cmdline - allocate and initialize kernel cmdline - * @lmb: pointer to lmb handle, will be used for memory mgmt * @cmd_start: pointer to a ulong variable, will hold cmdline start * @cmd_end: pointer to a ulong variable, will hold cmdline end * @@ -813,7 +814,7 @@ int boot_get_loadable(struct bootm_headers *images) * 0 - success * -1 - failure */ -int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end) +int boot_get_cmdline(ulong *cmd_start, ulong *cmd_end) { int barg; char *cmdline; @@ -827,7 +828,7 @@ int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end) return 0; barg = IF_ENABLED_INT(CONFIG_SYS_BOOT_GET_CMDLINE, CONFIG_SYS_BARGSIZE); - cmdline = (char *)(ulong)lmb_alloc_base(lmb, barg, 0xf, + cmdline = (char *)(ulong)lmb_alloc_base(barg, 0xf, env_get_bootm_mapsize() + env_get_bootm_low()); if (!cmdline) return -1; @@ -848,7 +849,6 @@ int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end) /** * boot_get_kbd - allocate and initialize kernel copy of board info - * @lmb: pointer to lmb handle, will be used for memory mgmt * @kbd: double pointer to board info data * * boot_get_kbd() allocates space for kernel copy of board info data below @@ -859,10 +859,9 @@ int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end) * 0 - success * -1 - failure */ -int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd) +int boot_get_kbd(struct bd_info **kbd) { - *kbd = (struct bd_info *)(ulong)lmb_alloc_base(lmb, - sizeof(struct bd_info), + *kbd = (struct bd_info *)(ulong)lmb_alloc_base(sizeof(struct bd_info), 0xf, env_get_bootm_mapsize() + env_get_bootm_low()); @@ -883,17 +882,16 @@ int image_setup_linux(struct bootm_headers *images) { ulong of_size = images->ft_len; char **of_flat_tree = &images->ft_addr; - struct lmb *lmb = images_lmb(images); int ret; /* This function cannot be called without lmb support */ - if (!IS_ENABLED(CONFIG_LMB)) + if (!CONFIG_IS_ENABLED(LMB)) return -EFAULT; if (CONFIG_IS_ENABLED(OF_LIBFDT)) - boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree); + boot_fdt_add_mem_rsv_regions(*of_flat_tree); if (IS_ENABLED(CONFIG_SYS_BOOT_GET_CMDLINE)) { - ret = boot_get_cmdline(lmb, &images->cmdline_start, + ret = boot_get_cmdline(&images->cmdline_start, &images->cmdline_end); if (ret) { puts("ERROR with allocation of cmdline\n"); @@ -902,13 +900,13 @@ int image_setup_linux(struct bootm_headers *images) } if (CONFIG_IS_ENABLED(OF_LIBFDT)) { - ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size); + ret = boot_relocate_fdt(of_flat_tree, &of_size); if (ret) return ret; } if (CONFIG_IS_ENABLED(OF_LIBFDT) && of_size) { - ret = image_setup_libfdt(images, *of_flat_tree, lmb); + ret = image_setup_libfdt(images, *of_flat_tree, true); if (ret) return ret; } diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 8332792b8e8..8eda521693d 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -68,12 +68,11 @@ static const struct legacy_img_hdr *image_get_fdt(ulong fdt_addr) } #endif -static void boot_fdt_reserve_region(struct lmb *lmb, uint64_t addr, - uint64_t size, enum lmb_flags flags) +static void boot_fdt_reserve_region(u64 addr, u64 size, enum lmb_flags flags) { long ret; - ret = lmb_reserve_flags(lmb, addr, size, flags); + ret = lmb_reserve_flags(addr, size, flags); if (ret >= 0) { debug(" reserving fdt memory region: addr=%llx size=%llx flags=%x\n", (unsigned long long)addr, @@ -89,14 +88,13 @@ static void boot_fdt_reserve_region(struct lmb *lmb, uint64_t addr, /** * boot_fdt_add_mem_rsv_regions - Mark the memreserve and reserved-memory * sections as unusable - * @lmb: pointer to lmb handle, will be used for memory mgmt * @fdt_blob: pointer to fdt blob base address * * Adds the and reserved-memorymemreserve regions in the dtb to the lmb block. * Adding the memreserve regions prevents u-boot from using them to store the * initrd or the fdt blob. */ -void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob) +void boot_fdt_add_mem_rsv_regions(void *fdt_blob) { uint64_t addr, size; int i, total, ret; @@ -112,7 +110,7 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob) for (i = 0; i < total; i++) { if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0) continue; - boot_fdt_reserve_region(lmb, addr, size, LMB_NONE); + boot_fdt_reserve_region(addr, size, LMB_NONE); } /* process reserved-memory */ @@ -130,7 +128,7 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob) flags = LMB_NOMAP; addr = res.start; size = res.end - res.start + 1; - boot_fdt_reserve_region(lmb, addr, size, flags); + boot_fdt_reserve_region(addr, size, flags); } subnode = fdt_next_subnode(fdt_blob, subnode); @@ -140,7 +138,6 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob) /** * boot_relocate_fdt - relocate flat device tree - * @lmb: pointer to lmb handle, will be used for memory mgmt * @of_flat_tree: pointer to a char* variable, will hold fdt start address * @of_size: pointer to a ulong variable, will hold fdt length * @@ -155,7 +152,7 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob) * 0 - success * 1 - failure */ -int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) +int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) { u64 start, size, usable, addr, low, mapsize; void *fdt_blob = *of_flat_tree; @@ -187,18 +184,17 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) if (desired_addr == ~0UL) { /* All ones means use fdt in place */ of_start = fdt_blob; - lmb_reserve(lmb, map_to_sysmem(of_start), of_len); + lmb_reserve(map_to_sysmem(of_start), of_len); disable_relocation = 1; } else if (desired_addr) { - addr = lmb_alloc_base(lmb, of_len, 0x1000, - desired_addr); + addr = lmb_alloc_base(of_len, 0x1000, desired_addr); of_start = map_sysmem(addr, of_len); if (of_start == NULL) { puts("Failed using fdt_high value for Device Tree"); goto error; } } else { - addr = lmb_alloc(lmb, of_len, 0x1000); + addr = lmb_alloc(of_len, 0x1000); of_start = map_sysmem(addr, of_len); } } else { @@ -220,7 +216,7 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) * for LMB allocation. */ usable = min(start + size, low + mapsize); - addr = lmb_alloc_base(lmb, of_len, 0x1000, usable); + addr = lmb_alloc_base(of_len, 0x1000, usable); of_start = map_sysmem(addr, of_len); /* Allocation succeeded, use this block. */ if (of_start != NULL) @@ -569,8 +565,7 @@ __weak int arch_fixup_fdt(void *blob) return 0; } -int image_setup_libfdt(struct bootm_headers *images, void *blob, - struct lmb *lmb) +int image_setup_libfdt(struct bootm_headers *images, void *blob, bool lmb) { ulong *initrd_start = &images->initrd_start; ulong *initrd_end = &images->initrd_end; @@ -670,8 +665,8 @@ int image_setup_libfdt(struct bootm_headers *images, void *blob, } /* Delete the old LMB reservation */ - if (lmb) - lmb_free(lmb, map_to_sysmem(blob), fdt_totalsize(blob)); + if (CONFIG_IS_ENABLED(LMB) && lmb) + lmb_free(map_to_sysmem(blob), fdt_totalsize(blob)); ret = fdt_shrink_to_minimum(blob, 0); if (ret < 0) @@ -679,8 +674,8 @@ int image_setup_libfdt(struct bootm_headers *images, void *blob, of_size = ret; /* Create a new LMB reservation */ - if (lmb) - lmb_reserve(lmb, map_to_sysmem(blob), of_size); + if (CONFIG_IS_ENABLED(LMB) && lmb) + lmb_reserve(map_to_sysmem(blob), of_size); #if defined(CONFIG_ARCH_KEYSTONE) if (IS_ENABLED(CONFIG_OF_BOARD_SETUP)) diff --git a/boot/scene.c b/boot/scene.c index ac976aa26bb..270c9c67233 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -79,13 +79,7 @@ int scene_title_set(struct scene *scn, uint id) int scene_obj_count(struct scene *scn) { - struct scene_obj *obj; - int count = 0; - - list_for_each_entry(obj, &scn->obj_head, sibling) - count++; - - return count; + return list_count_nodes(&scn->obj_head); } void *scene_obj_find(const struct scene *scn, uint id, enum scene_obj_t type) diff --git a/cmd/bcb.c b/cmd/bcb.c index fe6d6cb2c38..97a96c00964 100644 --- a/cmd/bcb.c +++ b/cmd/bcb.c @@ -172,8 +172,8 @@ static int __bcb_initialize(const char *iface, int devnum, const char *partp) return CMD_RET_SUCCESS; err_read_fail: - printf("Error: %d %d:%s read failed (%d)\n", block->uclass_id, - block->devnum, partition->name, ret); + printf("Error: %s %d:%s read failed (%d)\n", iface, devnum, + partition->name, ret); __bcb_reset(); return CMD_RET_FAILURE; } diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 437ac4e8630..f6e534dd5bb 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -154,18 +154,13 @@ static int bdinfo_print_all(struct bd_info *bd) if (IS_ENABLED(CONFIG_CMD_NET)) print_eth(); bdinfo_print_num_l("fdt_blob", (ulong)map_to_sysmem(gd->fdt_blob)); - bdinfo_print_num_l("new_fdt", (ulong)map_to_sysmem(gd->new_fdt)); - bdinfo_print_num_l("fdt_size", (ulong)gd->fdt_size); if (IS_ENABLED(CONFIG_VIDEO)) show_video_info(); #if CONFIG_IS_ENABLED(MULTI_DTB_FIT) bdinfo_print_num_l("multi_dtb_fit", (ulong)gd->multi_dtb_fit); #endif if (IS_ENABLED(CONFIG_LMB) && gd->fdt_blob) { - struct lmb lmb; - - lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); - lmb_dump_all_force(&lmb); + lmb_dump_all_force(); if (IS_ENABLED(CONFIG_OF_REAL)) printf("devicetree = %s\n", fdtdec_get_srcname()); } diff --git a/cmd/bind.c b/cmd/bind.c index 3a59eefd5c5..c0d31f5eb16 100644 --- a/cmd/bind.c +++ b/cmd/bind.c @@ -10,8 +10,8 @@ #include <dm/root.h> #include <dm/uclass-internal.h> -static int bind_by_class_index(const char *uclass, int index, - const char *drv_name) +static int bind_by_class_seq(const char *uclass, int seq, + const char *drv_name) { static enum uclass_id uclass_id; struct udevice *dev; @@ -31,9 +31,9 @@ static int bind_by_class_index(const char *uclass, int index, return -EINVAL; } - ret = uclass_find_device(uclass_id, index, &parent); + ret = uclass_find_device_by_seq(uclass_id, seq, &parent); if (!parent || ret) { - printf("Cannot find device %d of class %s\n", index, uclass); + printf("Cannot find device %d of class %s\n", seq, uclass); return ret; } @@ -47,7 +47,7 @@ static int bind_by_class_index(const char *uclass, int index, return 0; } -static int find_dev(const char *uclass, int index, struct udevice **devp) +static int find_dev(const char *uclass, int seq, struct udevice **devp) { static enum uclass_id uclass_id; int rc; @@ -58,21 +58,21 @@ static int find_dev(const char *uclass, int index, struct udevice **devp) return -EINVAL; } - rc = uclass_find_device(uclass_id, index, devp); + rc = uclass_find_device_by_seq(uclass_id, seq, devp); if (!*devp || rc) { - printf("Cannot find device %d of class %s\n", index, uclass); + printf("Cannot find device %d of class %s\n", seq, uclass); return rc; } return 0; } -static int unbind_by_class_index(const char *uclass, int index) +static int unbind_by_class_seq(const char *uclass, int seq) { int ret; struct udevice *dev; - ret = find_dev(uclass, index, &dev); + ret = find_dev(uclass, seq, &dev); if (ret) return ret; @@ -91,8 +91,8 @@ static int unbind_by_class_index(const char *uclass, int index) return 0; } -static int unbind_child_by_class_index(const char *uclass, int index, - const char *drv_name) +static int unbind_child_by_class_seq(const char *uclass, int seq, + const char *drv_name) { struct udevice *parent; int ret; @@ -104,7 +104,7 @@ static int unbind_child_by_class_index(const char *uclass, int index, return -ENOENT; } - ret = find_dev(uclass, index, &parent); + ret = find_dev(uclass, seq, &parent); if (ret) return ret; @@ -217,19 +217,19 @@ static int do_bind_unbind(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_USAGE; ret = unbind_by_node_path(argv[1]); } else if (!by_node && bind) { - int index = (argc > 2) ? dectoul(argv[2], NULL) : 0; + int seq = (argc > 2) ? dectoul(argv[2], NULL) : 0; if (argc != 4) return CMD_RET_USAGE; - ret = bind_by_class_index(argv[1], index, argv[3]); + ret = bind_by_class_seq(argv[1], seq, argv[3]); } else if (!by_node && !bind) { - int index = (argc > 2) ? dectoul(argv[2], NULL) : 0; + int seq = (argc > 2) ? dectoul(argv[2], NULL) : 0; if (argc == 3) - ret = unbind_by_class_index(argv[1], index); + ret = unbind_by_class_seq(argv[1], seq); else if (argc == 4) - ret = unbind_child_by_class_index(argv[1], index, - argv[3]); + ret = unbind_child_by_class_seq(argv[1], seq, + argv[3]); else return CMD_RET_USAGE; } @@ -244,17 +244,17 @@ U_BOOT_CMD( bind, 4, 0, do_bind_unbind, "Bind a device to a driver", "<node path> <driver>\n" - "bind <class> <index> <driver>\n" + "bind <class> <seq> <driver>\n" "Use 'dm tree' to list all devices registered in the driver model,\n" - "their path, class, index and current driver.\n" + "their path, class, sequence and current driver.\n" ); U_BOOT_CMD( unbind, 4, 0, do_bind_unbind, "Unbind a device from a driver", "<node path>\n" - "unbind <class> <index>\n" - "unbind <class> <index> <driver>\n" + "unbind <class> <seq>\n" + "unbind <class> <seq> <driver>\n" "Use 'dm tree' to list all devices registered in the driver model,\n" - "their path, class, index and current driver.\n" + "their path, class, sequence and current driver.\n" ); diff --git a/cmd/booti.c b/cmd/booti.c index 62b19e83436..6018cbacf0a 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -87,7 +87,7 @@ static int booti_start(struct bootm_info *bmi) images->os.start = relocated_addr; images->os.end = relocated_addr + image_size; - lmb_reserve(&images->lmb, images->ep, le32_to_cpu(image_size)); + lmb_reserve(images->ep, le32_to_cpu(image_size)); /* * Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not diff --git a/cmd/bootz.c b/cmd/bootz.c index 55837a7599b..787203f5bd7 100644 --- a/cmd/bootz.c +++ b/cmd/bootz.c @@ -56,7 +56,7 @@ static int bootz_start(struct cmd_tbl *cmdtp, int flag, int argc, if (ret != 0) return 1; - lmb_reserve(&images->lmb, images->ep, zi_end - zi_start); + lmb_reserve(images->ep, zi_end - zi_start); /* * Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not diff --git a/cmd/efi.c b/cmd/efi.c index 6bed2d743ba..687ccb52042 100644 --- a/cmd/efi.c +++ b/cmd/efi.c @@ -11,7 +11,7 @@ #include <log.h> #include <malloc.h> #include <sort.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/cmd/efi_common.c b/cmd/efi_common.c index c46764e6eea..d2f2b59e9e3 100644 --- a/cmd/efi_common.c +++ b/cmd/efi_common.c @@ -8,7 +8,7 @@ #include <efi.h> #include <efi_api.h> -#include <uuid.h> +#include <u-boot/uuid.h> void efi_show_tables(struct efi_system_table *systab) { diff --git a/cmd/elf.c b/cmd/elf.c index 673c6c30511..f07e344a596 100644 --- a/cmd/elf.c +++ b/cmd/elf.c @@ -70,7 +70,7 @@ int do_bootelf(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) fdt_set_totalsize((void *)fdt_addr, fdt_totalsize(fdt_addr) + CONFIG_SYS_FDT_PAD); - if (image_setup_libfdt(&img, (void *)fdt_addr, NULL)) + if (image_setup_libfdt(&img, (void *)fdt_addr, false)) return 1; } #endif diff --git a/cmd/flash.c b/cmd/flash.c index de0e04f09cf..fd660ec477c 100644 --- a/cmd/flash.c +++ b/cmd/flash.c @@ -10,7 +10,7 @@ #include <command.h> #include <log.h> #include <vsprintf.h> -#include <uuid.h> +#include <u-boot/uuid.h> #if defined(CONFIG_CMD_MTDPARTS) #include <jffs2/jffs2.h> diff --git a/cmd/gpt.c b/cmd/gpt.c index 86b7701886a..27aea2df197 100644 --- a/cmd/gpt.c +++ b/cmd/gpt.c @@ -19,7 +19,7 @@ #include <part_efi.h> #include <part.h> #include <exports.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <linux/ctype.h> #include <div64.h> #include <memalign.h> diff --git a/cmd/load.c b/cmd/load.c index d773a25d70c..20d802502ae 100644 --- a/cmd/load.c +++ b/cmd/load.c @@ -141,7 +141,6 @@ static int do_load_serial(struct cmd_tbl *cmdtp, int flag, int argc, static ulong load_serial(long offset) { - struct lmb lmb; char record[SREC_MAXRECLEN + 1]; /* buffer for one S-Record */ char binbuf[SREC_MAXBINLEN]; /* buffer for binary data */ int binlen; /* no. of data bytes in S-Rec. */ @@ -154,8 +153,6 @@ static ulong load_serial(long offset) int line_count = 0; long ret; - lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); - while (read_record(record, SREC_MAXRECLEN + 1) >= 0) { type = srec_decode(record, &binlen, &addr, binbuf); @@ -182,7 +179,7 @@ static ulong load_serial(long offset) { void *dst; - ret = lmb_reserve(&lmb, store_addr, binlen); + ret = lmb_reserve(store_addr, binlen); if (ret) { printf("\nCannot overwrite reserved area (%08lx..%08lx)\n", store_addr, store_addr + binlen); @@ -191,7 +188,7 @@ static ulong load_serial(long offset) dst = map_sysmem(store_addr, binlen); memcpy(dst, binbuf, binlen); unmap_sysmem(dst); - lmb_free(&lmb, store_addr, binlen); + lmb_free(store_addr, binlen); } if ((store_addr) < start_addr) start_addr = store_addr; diff --git a/cmd/mmc.c b/cmd/mmc.c index ff7b8e555ba..9a841c25d3d 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -14,6 +14,7 @@ #include <sparse_format.h> #include <image-sparse.h> #include <vsprintf.h> +#include <linux/ctype.h> static int curr_device = -1; @@ -918,8 +919,9 @@ static int mmc_partconf_print(struct mmc *mmc, const char *varname) printf("EXT_CSD[179], PARTITION_CONFIG:\n" "BOOT_ACK: 0x%x\n" - "BOOT_PARTITION_ENABLE: 0x%x\n" - "PARTITION_ACCESS: 0x%x\n", ack, part, access); + "BOOT_PARTITION_ENABLE: 0x%x (%s)\n" + "PARTITION_ACCESS: 0x%x (%s)\n", ack, part, emmc_boot_part_names[part], + access, emmc_hwpart_names[access]); return CMD_RET_SUCCESS; } @@ -948,9 +950,26 @@ static int do_mmc_partconf(struct cmd_tbl *cmdtp, int flag, if (argc == 2 || argc == 3) return mmc_partconf_print(mmc, cmd_arg2(argc, argv)); + /* BOOT_ACK */ ack = dectoul(argv[2], NULL); - part_num = dectoul(argv[3], NULL); - access = dectoul(argv[4], NULL); + /* BOOT_PARTITION_ENABLE */ + if (!isdigit(*argv[3])) { + for (part_num = ARRAY_SIZE(emmc_boot_part_names) - 1; part_num > 0; part_num--) { + if (!strcmp(argv[3], emmc_boot_part_names[part_num])) + break; + } + } else { + part_num = dectoul(argv[3], NULL); + } + /* PARTITION_ACCESS */ + if (!isdigit(*argv[4])) { + for (access = ARRAY_SIZE(emmc_hwpart_names) - 1; access > 0; access--) { + if (!strcmp(argv[4], emmc_hwpart_names[access])) + break; + } + } else { + access = dectoul(argv[4], NULL); + } /* acknowledge to be sent during boot operation */ ret = mmc_set_part_conf(mmc, ack, part_num, access); diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c index e3f21dd0d81..5e4ffc40d72 100644 --- a/cmd/mvebu/bubt.c +++ b/cmd/mvebu/bubt.c @@ -223,8 +223,8 @@ static int mmc_burn_image(size_t image_size) #endif part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); - if (part == 7) - part = 0; + if (part == EMMC_BOOT_PART_USER) + part = EMMC_HWPART_DEFAULT; #ifdef CONFIG_BLK err = blk_dselect_hwpart(blk_desc, part); diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c index 64ae2ad2ce2..32b7d049074 100644 --- a/cmd/nvedit_efi.c +++ b/cmd/nvedit_efi.c @@ -15,7 +15,7 @@ #include <malloc.h> #include <mapmem.h> #include <rtc.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <linux/kernel.h> /* @@ -14,8 +14,10 @@ static int do_sb_handoff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { #if CONFIG_IS_ENABLED(HANDOFF) - if (gd->spl_handoff) - printf("SPL handoff magic %lx\n", gd->spl_handoff->arch.magic); + struct spl_handoff *handoff = handoff_get(); + + if (handoff) + printf("SPL handoff magic %lx\n", handoff->arch.magic); else printf("SPL handoff info not received\n"); diff --git a/cmd/x86/hob.c b/cmd/x86/hob.c index 2dd30808bd1..d3713cef331 100644 --- a/cmd/x86/hob.c +++ b/cmd/x86/hob.c @@ -5,7 +5,7 @@ #include <command.h> #include <efi.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <asm/global_data.h> #include <asm/hob.h> #include <asm/fsp/fsp_hob.h> diff --git a/common/board_f.c b/common/board_f.c index 454426d921c..154675d0e40 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -305,17 +305,6 @@ static int setup_mon_len(void) return 0; } -static int setup_spl_handoff(void) -{ -#if CONFIG_IS_ENABLED(HANDOFF) - gd->spl_handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, - sizeof(struct spl_handoff)); - debug("Found SPL hand-off info %p\n", gd->spl_handoff); -#endif - - return 0; -} - __weak int arch_cpu_init(void) { return 0; @@ -351,7 +340,7 @@ __weak int arch_setup_dest_addr(void) static int setup_dest_addr(void) { - debug("Monitor len: %08lX\n", gd->mon_len); + debug("Monitor len: %08x\n", gd->mon_len); /* * Ram is setup, size stored in gd !! */ @@ -488,7 +477,7 @@ static int reserve_uboot(void) gd->relocaddr &= ~(65536 - 1); #endif - debug("Reserving %ldk for U-Boot at: %08lx\n", + debug("Reserving %dk for U-Boot at: %08lx\n", gd->mon_len >> 10, gd->relocaddr); } @@ -575,12 +564,15 @@ static int reserve_fdt(void) * section, then it will be relocated with other data. */ if (gd->fdt_blob) { - gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob), 32); + gd->boardf->fdt_size = + ALIGN(fdt_totalsize(gd->fdt_blob), 32); - gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size); - gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); + gd->start_addr_sp = reserve_stack_aligned( + gd->boardf->fdt_size); + gd->boardf->new_fdt = map_sysmem(gd->start_addr_sp, + gd->boardf->fdt_size); debug("Reserving %lu Bytes for FDT at: %08lx\n", - gd->fdt_size, gd->start_addr_sp); + gd->boardf->fdt_size, gd->start_addr_sp); } } @@ -593,7 +585,7 @@ static int reserve_bootstage(void) int size = bootstage_get_size(); gd->start_addr_sp = reserve_stack_aligned(size); - gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); + gd->boardf->new_bootstage = map_sysmem(gd->start_addr_sp, size); debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, gd->start_addr_sp); #endif @@ -624,8 +616,8 @@ static int reserve_bloblist(void) /* Align to a 4KB boundary for easier reading of addresses */ gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp - CONFIG_BLOBLIST_SIZE_RELOC, 0x1000); - gd->new_bloblist = map_sysmem(gd->start_addr_sp, - CONFIG_BLOBLIST_SIZE_RELOC); + gd->boardf->new_bloblist = map_sysmem(gd->start_addr_sp, + CONFIG_BLOBLIST_SIZE_RELOC); #endif return 0; @@ -668,10 +660,10 @@ static int init_post(void) static int reloc_fdt(void) { if (!IS_ENABLED(CONFIG_OF_EMBED)) { - if (gd->new_fdt) { - memcpy(gd->new_fdt, gd->fdt_blob, + if (gd->boardf->new_fdt) { + memcpy(gd->boardf->new_fdt, gd->fdt_blob, fdt_totalsize(gd->fdt_blob)); - gd->fdt_blob = gd->new_fdt; + gd->fdt_blob = gd->boardf->new_fdt; } } @@ -683,9 +675,8 @@ static int reloc_bootstage(void) #ifdef CONFIG_BOOTSTAGE if (gd->flags & GD_FLG_SKIP_RELOC) return 0; - if (gd->new_bootstage) { - bootstage_relocate(gd->new_bootstage); - } + if (gd->boardf->new_bootstage) + bootstage_relocate(gd->boardf->new_bootstage); #endif return 0; @@ -702,10 +693,11 @@ static int reloc_bloblist(void) debug("Not relocating bloblist\n"); return 0; } - if (gd->new_bloblist) { + if (gd->boardf->new_bloblist) { debug("Copying bloblist from %p to %p, size %x\n", - gd->bloblist, gd->new_bloblist, gd->bloblist->total_size); - return bloblist_reloc(gd->new_bloblist, + gd->bloblist, gd->boardf->new_bloblist, + gd->bloblist->total_size); + return bloblist_reloc(gd->boardf->new_bloblist, CONFIG_BLOBLIST_SIZE_RELOC); } #endif @@ -805,7 +797,7 @@ static int initf_bootstage(void) if (ret) return ret; if (from_spl) { - ret = bootstage_stash_default(); + ret = bootstage_unstash_default(); if (ret && ret != -ENOENT) { debug("Failed to unstash bootstage: err=%d\n", ret); return ret; @@ -888,7 +880,6 @@ static const init_fnc_t init_sequence_f[] = { initf_bootstage, /* uses its own timer, so does not need DM */ event_init, bloblist_maybe_init, - setup_spl_handoff, #if defined(CONFIG_CONSOLE_RECORD_INIT_F) console_record_init, #endif @@ -1021,8 +1012,11 @@ static const init_fnc_t init_sequence_f[] = { void board_init_f(ulong boot_flags) { + struct board_f boardf; + gd->flags = boot_flags; - gd->have_console = 0; + gd->flags &= ~GD_FLG_HAVE_CONSOLE; + gd->boardf = &boardf; if (initcall_run_list(init_sequence_f)) hang(); diff --git a/common/board_r.c b/common/board_r.c index f445803d7a4..4faaa202421 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -22,6 +22,7 @@ #include <hang.h> #include <image.h> #include <irq_func.h> +#include <lmb.h> #include <log.h> #include <net.h> #include <asm/cache.h> @@ -192,7 +193,7 @@ static int initr_malloc(void) ulong start; #if CONFIG_IS_ENABLED(SYS_MALLOC_F) - debug("Pre-reloc malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr, + debug("Pre-reloc malloc() used %#x bytes (%d KB)\n", gd->malloc_ptr, gd->malloc_ptr / 1024); #endif /* The malloc area is immediately below the monitor copy in DRAM */ @@ -510,6 +511,14 @@ int initr_mem(void) } #endif +static int initr_lmb(void) +{ + if (CONFIG_IS_ENABLED(LMB)) + return lmb_init(); + else + return 0; +} + static int dm_announce(void) { int device_count; @@ -612,6 +621,7 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_CLOCKS set_cpu_clk_info, /* Setup clock information */ #endif + initr_lmb, #ifdef CONFIG_EFI_LOADER efi_memory_init, #endif diff --git a/common/console.c b/common/console.c index 85f627297ed..52d6df8150f 100644 --- a/common/console.c +++ b/common/console.c @@ -189,6 +189,7 @@ static int console_setfile(int file, struct stdio_dev * dev) /* Assign the new device (leaving the existing one started) */ stdio_devices[file] = dev; +#ifndef CONFIG_SPL_BUILD /* * Update monitor functions * (to use the console stuff by other applications) @@ -206,7 +207,7 @@ static int console_setfile(int file, struct stdio_dev * dev) break; } break; - +#endif default: /* Invalid file ID */ error = -1; } @@ -586,7 +587,7 @@ int getchar(void) if (IS_ENABLED(CONFIG_DISABLE_CONSOLE) && (gd->flags & GD_FLG_DISABLE_CONSOLE)) return 0; - if (!gd->have_console) + if (!(gd->flags & GD_FLG_HAVE_CONSOLE)) return 0; ch = console_record_getc(); @@ -607,7 +608,7 @@ int tstc(void) if (IS_ENABLED(CONFIG_DISABLE_CONSOLE) && (gd->flags & GD_FLG_DISABLE_CONSOLE)) return 0; - if (!gd->have_console) + if (!(gd->flags & GD_FLG_HAVE_CONSOLE)) return 0; if (console_record_tstc()) @@ -715,7 +716,7 @@ void putc(const char c) if (IS_ENABLED(CONFIG_DISABLE_CONSOLE) && (gd->flags & GD_FLG_DISABLE_CONSOLE)) return; - if (!gd->have_console) + if (!(gd->flags & GD_FLG_HAVE_CONSOLE)) return pre_console_putc(c); if (gd->flags & GD_FLG_DEVINIT) { @@ -759,7 +760,7 @@ void puts(const char *s) if (IS_ENABLED(CONFIG_DISABLE_CONSOLE) && (gd->flags & GD_FLG_DISABLE_CONSOLE)) return; - if (!gd->have_console) + if (!(gd->flags & GD_FLG_HAVE_CONSOLE)) return pre_console_puts(s); if (gd->flags & GD_FLG_DEVINIT) { @@ -793,7 +794,7 @@ void flush(void) if (IS_ENABLED(CONFIG_DISABLE_CONSOLE) && (gd->flags & GD_FLG_DISABLE_CONSOLE)) return; - if (!gd->have_console) + if (!(gd->flags & GD_FLG_HAVE_CONSOLE)) return; if (gd->flags & GD_FLG_DEVINIT) { @@ -874,7 +875,7 @@ static int ctrlc_disabled = 0; /* see disable_ctrl() */ static int ctrlc_was_pressed = 0; int ctrlc(void) { - if (!ctrlc_disabled && gd->have_console) { + if (!ctrlc_disabled && (gd->flags & GD_FLG_HAVE_CONSOLE)) { if (tstc()) { switch (getchar()) { case 0x03: /* ^C - Control C */ @@ -1013,7 +1014,7 @@ int console_announce_r(void) /* Called before relocation - use serial functions */ int console_init_f(void) { - gd->have_console = 1; + gd->flags |= GD_FLG_HAVE_CONSOLE; console_update_silent(); diff --git a/common/flash.c b/common/flash.c index 24ddc8bee72..226646c6868 100644 --- a/common/flash.c +++ b/common/flash.c @@ -8,7 +8,7 @@ #include <flash.h> #include <log.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <linux/string.h> #include <mtd/cfi_flash.h> diff --git a/common/hwconfig.c b/common/hwconfig.c index afaa6cb37ab..25a8cd5bf5d 100644 --- a/common/hwconfig.c +++ b/common/hwconfig.c @@ -77,7 +77,13 @@ static const char *__hwconfig(const char *opt, size_t *arglen, /* if we are passed a buffer use it, otherwise try the environment */ if (!env_hwconfig) { - if (!(gd->flags & GD_FLG_ENV_READY) && gd->env_valid != ENV_VALID) { +#if CONFIG_IS_ENABLED(ENV_SUPPORT) + if (!(gd->flags & GD_FLG_ENV_READY) && + gd->env_valid != ENV_VALID) +#else + if (true) +#endif + { printf("WARNING: Calling __hwconfig without a buffer " "and before environment is ready\n"); return NULL; diff --git a/common/init/handoff.c b/common/init/handoff.c index a7cd065fb38..86c020ee0b9 100644 --- a/common/init/handoff.c +++ b/common/init/handoff.c @@ -5,6 +5,7 @@ * Copyright 2018 Google, Inc */ +#include <bloblist.h> #include <handoff.h> #include <asm/global_data.h> @@ -38,3 +39,14 @@ void handoff_load_dram_banks(struct spl_handoff *ho) bd->bi_dram[i].size = ho->ram_bank[i].size; } } + +struct spl_handoff *handoff_get(void) +{ + struct spl_handoff *handoff; + + handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, + sizeof(struct spl_handoff)); + debug("Found SPL hand-off info %p\n", handoff); + + return handoff; +} diff --git a/common/log_console.c b/common/log_console.c index c27101b8fe2..9376baad664 100644 --- a/common/log_console.c +++ b/common/log_console.c @@ -38,10 +38,10 @@ static int log_console_emit(struct log_device *ldev, struct log_rec *rec) printf("%d-", rec->line); if (fmt & BIT(LOGF_FUNC)) { if (CONFIG_IS_ENABLED(USE_TINY_PRINTF)) { - printf("%s()", rec->func); + printf("%s()", rec->func ?: "?"); } else { printf("%*s()", CONFIG_LOGF_FUNC_PAD, - rec->func); + rec->func ?: "?"); } } } diff --git a/common/log_syslog.c b/common/log_syslog.c index d01bb749c22..0dcb5f7cdea 100644 --- a/common/log_syslog.c +++ b/common/log_syslog.c @@ -88,7 +88,7 @@ static int log_syslog_emit(struct log_device *ldev, struct log_rec *rec) if (fmt & BIT(LOGF_LINE)) append(&ptr, msg_end, "%d-", rec->line); if (fmt & BIT(LOGF_FUNC)) - append(&ptr, msg_end, "%s()", rec->func); + append(&ptr, msg_end, "%s()", rec->func ?: "?"); if (fmt & BIT(LOGF_MSG)) append(&ptr, msg_end, "%s%s", fmt != BIT(LOGF_MSG) ? " " : "", rec->msg); diff --git a/common/malloc_simple.c b/common/malloc_simple.c index 4e6d7952b3c..5a8ec538f8f 100644 --- a/common/malloc_simple.c +++ b/common/malloc_simple.c @@ -23,7 +23,7 @@ static void *alloc_simple(size_t bytes, int align) addr = ALIGN(gd->malloc_base + gd->malloc_ptr, align); new_ptr = addr + bytes - gd->malloc_base; - log_debug("size=%lx, ptr=%lx, limit=%lx: ", (ulong)bytes, new_ptr, + log_debug("size=%lx, ptr=%lx, limit=%x: ", (ulong)bytes, new_ptr, gd->malloc_limit); if (new_ptr > gd->malloc_limit) { log_err("alloc space exhausted\n"); @@ -87,6 +87,6 @@ void free_simple(void *ptr) void malloc_simple_info(void) { - log_info("malloc_simple: %lx bytes used, %lx remain\n", gd->malloc_ptr, + log_info("malloc_simple: %x bytes used, %x remain\n", gd->malloc_ptr, CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_ptr); } diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 44a68abce60..3c44e329d62 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -492,24 +492,45 @@ config SPL_DISPLAY_PRINT the board. config SPL_SYS_MMCSD_RAW_MODE - bool - help - Support booting from an MMC without a filesystem. - -config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR - bool "MMC raw mode: by sector" + bool "Use raw reads to locate the next boot phase" + depends on SPL_DM_MMC || SPL_MMC default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \ ARCH_MX6 || ARCH_MX7 || \ ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \ ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ OMAP54XX || AM33XX || AM43XX || \ TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED - select SPL_LOAD_BLOCK if SPL_MMC - select SPL_SYS_MMCSD_RAW_MODE if SPL_MMC + help + Support booting from an MMC without a filesystem. + +if SPL_SYS_MMCSD_RAW_MODE + +choice + prompt "Method for locating next phase of boot (e.g. U-Boot)" + +config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR + bool "MMC raw mode: by sector" + select SPL_LOAD_BLOCK help Use sector number for specifying U-Boot location on MMC/SD in raw mode. +config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION + bool "MMC raw mode: by partition" + select SPL_LOAD_BLOCK + help + Use a partition for loading U-Boot when using MMC/SD in raw mode. + +config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE + bool "MMC raw mode: by partition type" + depends on DOS_PARTITION + help + Use partition type for specifying U-Boot partition on MMC/SD in + raw mode. U-Boot will be loaded from the first partition of this + type to be found. + +endchoice + config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR hex "Address on the MMC to load U-Boot from" depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR @@ -540,13 +561,6 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET If unsure, leave the default. -config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION - bool "MMC Raw mode: by partition" - select SPL_LOAD_BLOCK if SPL_MMC - select SPL_SYS_MMCSD_RAW_MODE if SPL_MMC - help - Use a partition for loading U-Boot when using MMC/SD in raw mode. - config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION hex "Partition to use to load U-Boot from" depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION @@ -555,14 +569,6 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION Partition on the MMC to load U-Boot from when the MMC is being used in raw mode -config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE - bool "MMC raw mode: by partition type" - depends on DOS_PARTITION && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION - help - Use partition type for specifying U-Boot partition on MMC/SD in - raw mode. U-Boot will be loaded from the first partition of this - type to be found. - config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE hex "Partition Type on the MMC to load U-Boot from" depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE @@ -570,6 +576,8 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE Partition Type on the MMC to load U-Boot from, when the MMC is being used in raw mode. +endif # SPL_SYS_MMCSD_RAW_MODE + config SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG bool "Override eMMC EXT_CSC_PART_CONFIG by user defined partition" depends on SUPPORT_EMMC_BOOT diff --git a/common/spl/spl.c b/common/spl/spl.c index d6a364de6ee..c13b2b8f714 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -245,7 +245,6 @@ __weak struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) return map_sysmem(CONFIG_TEXT_BASE + offset, 0); } -#ifdef CONFIG_SPL_RAW_IMAGE_SUPPORT void spl_set_header_raw_uboot(struct spl_image_info *spl_image) { ulong u_boot_pos = spl_get_image_pos(); @@ -273,7 +272,6 @@ void spl_set_header_raw_uboot(struct spl_image_info *spl_image) spl_image->os = IH_OS_U_BOOT; spl_image->name = "U-Boot"; } -#endif __weak int spl_parse_board_header(struct spl_image_info *spl_image, const struct spl_boot_device *bootdev, @@ -308,8 +306,10 @@ int spl_parse_image_header(struct spl_image_info *spl_image, ret = spl_parse_legacy_header(spl_image, header); if (ret) return ret; - } else { -#ifdef CONFIG_SPL_PANIC_ON_RAW_IMAGE + return 0; + } + + if (IS_ENABLED(CONFIG_SPL_PANIC_ON_RAW_IMAGE)) { /* * CONFIG_SPL_PANIC_ON_RAW_IMAGE is defined when the * code which loads images in SPL cannot guarantee that @@ -319,10 +319,9 @@ int spl_parse_image_header(struct spl_image_info *spl_image, * is bad, and thus should be skipped silently. */ panic("** no mkimage signature but raw image not supported"); -#endif + } -#if CONFIG_IS_ENABLED(OS_BOOT) -#if defined(CMD_BOOTI) + if (CONFIG_IS_ENABLED(OS_BOOT) && IS_ENABLED(CONFIG_CMD_BOOTI)) { ulong start, size; if (!booti_setup((ulong)header, &start, &size, 0)) { @@ -336,7 +335,7 @@ int spl_parse_image_header(struct spl_image_info *spl_image, spl_image->load_addr, spl_image->size); return 0; } -#elif defined(CMD_BOOTZ) + } else if (CONFIG_IS_ENABLED(OS_BOOT) && IS_ENABLED(CONFIG_CMD_BOOTZ)) { ulong start, end; if (!bootz_setup((ulong)header, &start, &end)) { @@ -350,22 +349,21 @@ int spl_parse_image_header(struct spl_image_info *spl_image, spl_image->load_addr, spl_image->size); return 0; } -#endif -#endif + } - if (!spl_parse_board_header(spl_image, bootdev, (const void *)header, sizeof(*header))) - return 0; + if (!spl_parse_board_header(spl_image, bootdev, (const void *)header, + sizeof(*header))) + return 0; -#ifdef CONFIG_SPL_RAW_IMAGE_SUPPORT + if (IS_ENABLED(CONFIG_SPL_RAW_IMAGE_SUPPORT)) { /* Signature not found - assume u-boot.bin */ debug("mkimage signature not found - ih_magic = %x\n", - header->ih_magic); + header->ih_magic); spl_set_header_raw_uboot(spl_image); -#else + } else { /* RAW image not supported, proceed to other boot methods. */ debug("Raw boot image support not enabled, proceeding to other boot methods\n"); return -EINVAL; -#endif } return 0; @@ -713,16 +711,16 @@ void board_init_r(gd_t *dummy1, ulong dummy2) if (CONFIG_IS_ENABLED(SOC_INIT)) spl_soc_init(); - if (CONFIG_IS_ENABLED(BOARD_INIT)) - spl_board_init(); - if (IS_ENABLED(CONFIG_SPL_WATCHDOG) && CONFIG_IS_ENABLED(WDT)) initr_watchdog(); if (IS_ENABLED(CONFIG_SPL_OS_BOOT) || CONFIG_IS_ENABLED(HANDOFF) || - IS_ENABLED(CONFIG_SPL_ATF)) + IS_ENABLED(CONFIG_SPL_ATF) || IS_ENABLED(CONFIG_SPL_NET)) dram_init_banksize(); + if (IS_ENABLED(CONFIG_SPL_LMB)) + lmb_init(); + if (CONFIG_IS_ENABLED(PCI) && !(gd->flags & GD_FLG_DM_DEAD)) { ret = pci_init(); if (ret) @@ -730,6 +728,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2) /* Don't fail. We still can try other boot methods. */ } + if (CONFIG_IS_ENABLED(BOARD_INIT)) + spl_board_init(); + bootcount_inc(); /* Dump driver model states to aid analysis */ @@ -784,7 +785,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) } if (CONFIG_IS_ENABLED(SYS_MALLOC_F) && !IS_ENABLED(CONFIG_SPL_SYS_MALLOC_SIZE)) - debug("SPL malloc() used 0x%lx bytes (%ld KB)\n", + debug("SPL malloc() used 0x%x bytes (%d KB)\n", gd_malloc_ptr(), gd_malloc_ptr() / 1024); bootstage_mark_name(get_bootstage_id(false), "end phase"); @@ -840,7 +841,7 @@ void preloader_console_init(void) serial_init(); /* serial communications setup */ - gd->have_console = 1; + gd->flags |= GD_FLG_HAVE_CONSOLE; #if CONFIG_IS_ENABLED(BANNER_PRINT) puts("\nU-Boot " SPL_TPL_NAME " " PLAIN_VERSION " (" U_BOOT_DATE " - " @@ -903,7 +904,7 @@ ulong spl_relocate_stack_gd(void) #if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_IS_ENABLED(SYS_MALLOC_F) if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) { - debug("SPL malloc() before relocation used 0x%lx bytes (%ld KB)\n", + debug("SPL malloc() before relocation used 0x%x bytes (%d KB)\n", gd->malloc_ptr, gd->malloc_ptr / 1024); ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN; gd->malloc_base = ptr; diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c index bc551c5c074..bbf90a9741e 100644 --- a/common/spl/spl_blk_fs.c +++ b/common/spl/spl_blk_fs.c @@ -80,11 +80,8 @@ int spl_blk_load_image(struct spl_image_info *spl_image, return ret; } - load.read = spl_fit_read; - if (IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN)) - spl_set_bl_len(&load, ARCH_DMA_MINALIGN); - else - spl_set_bl_len(&load, 1); - load.priv = &dev; + spl_load_init(&load, spl_fit_read, &dev, + IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN) ? + ARCH_DMA_MINALIGN : 1); return spl_load(spl_image, bootdev, &load, filesize, 0); } diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c index 76f49a5a8a6..c5478820a9b 100644 --- a/common/spl/spl_ext.c +++ b/common/spl/spl_ext.c @@ -51,8 +51,7 @@ int spl_load_image_ext(struct spl_image_info *spl_image, goto end; } - spl_set_bl_len(&load, 1); - load.read = spl_fit_read; + spl_load_init(&load, spl_fit_read, NULL, 1); err = spl_load(spl_image, bootdev, &load, filelen, 0); end: diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c index bd8aab253a9..fce451b7664 100644 --- a/common/spl/spl_fat.c +++ b/common/spl/spl_fat.c @@ -83,12 +83,10 @@ int spl_load_image_fat(struct spl_image_info *spl_image, size = 0; } - load.read = spl_fit_read; - if (IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN)) - spl_set_bl_len(&load, ARCH_DMA_MINALIGN); - else - spl_set_bl_len(&load, 1); - load.priv = (void *)filename; + spl_load_init(&load, spl_fit_read, (void *)filename, + IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN) ? + ARCH_DMA_MINALIGN : 1); + err = spl_load(spl_image, bootdev, &load, size, 0); end: diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index ccab0be4be2..1337596eca0 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -46,21 +46,17 @@ int mmc_load_image_raw_sector(struct spl_image_info *spl_image, struct blk_desc *bd = mmc_get_blk_desc(mmc); struct spl_load_info load; - load.priv = bd; - spl_set_bl_len(&load, bd->blksz); - load.read = h_spl_load_read; + spl_load_init(&load, h_spl_load_read, bd, bd->blksz); ret = spl_load(spl_image, bootdev, &load, 0, sector << bd->log2blksz); if (ret) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT puts("mmc_load_image_raw_sector: mmc block read error\n"); -#endif - return -1; + return ret; } return 0; } -static int spl_mmc_get_device_index(u32 boot_device) +static int spl_mmc_get_device_index(uint boot_device) { switch (boot_device) { case BOOT_DEVICE_MMC1: @@ -70,40 +66,30 @@ static int spl_mmc_get_device_index(u32 boot_device) return 1; } -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT printf("spl: unsupported mmc boot device.\n"); -#endif return -ENODEV; } -static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device) +static int spl_mmc_find_device(struct mmc **mmcp, int mmc_dev) { - int err, mmc_dev; - - mmc_dev = spl_mmc_get_device_index(boot_device); - if (mmc_dev < 0) - return mmc_dev; + int ret; #if CONFIG_IS_ENABLED(DM_MMC) - err = mmc_init_device(mmc_dev); + ret = mmc_init_device(mmc_dev); #else - err = mmc_initialize(NULL); + ret = mmc_initialize(NULL); #endif /* DM_MMC */ - if (err) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("spl: could not initialize mmc. error: %d\n", err); -#endif - return err; + if (ret) { + printf("spl: could not initialize mmc. error: %d\n", ret); + return ret; } *mmcp = find_mmc_device(mmc_dev); - err = *mmcp ? 0 : -ENODEV; - if (err) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + ret = *mmcp ? 0 : -ENODEV; + if (ret) { printf("spl: could not find mmc device %d. error: %d\n", - mmc_dev, err); -#endif - return err; + mmc_dev, ret); + return ret; } return 0; @@ -116,14 +102,14 @@ static int mmc_load_image_raw_partition(struct spl_image_info *spl_image, unsigned long sector) { struct disk_partition info; - int err; + int ret; #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE int type_part; /* Only support MBR so DOS_ENTRY_NUMBERS */ for (type_part = 1; type_part <= DOS_ENTRY_NUMBERS; type_part++) { - err = part_get_info(mmc_get_blk_desc(mmc), type_part, &info); - if (err) + ret = part_get_info(mmc_get_blk_desc(mmc), type_part, &info); + if (ret) continue; if (info.sys_ind == CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE) { @@ -133,12 +119,10 @@ static int mmc_load_image_raw_partition(struct spl_image_info *spl_image, } #endif - err = part_get_info(mmc_get_blk_desc(mmc), partition, &info); - if (err) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + ret = part_get_info(mmc_get_blk_desc(mmc), partition, &info); + if (ret) { puts("spl: partition error\n"); -#endif - return -1; + return ret; } #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR @@ -164,10 +148,8 @@ static int mmc_load_image_raw_os(struct spl_image_info *spl_image, CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS, (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR); if (count != CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT puts("mmc_load_image_raw_os: mmc block read error\n"); -#endif - return -1; + return -EIO; } #endif /* CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR */ @@ -205,7 +187,7 @@ static int spl_mmc_do_fs_boot(struct spl_image_info *spl_image, struct mmc *mmc, const char *filename) { - int err = -ENOSYS; + int ret = -ENOSYS; __maybe_unused int partition = CONFIG_SYS_MMCSD_FS_BOOT_PARTITION; @@ -214,8 +196,8 @@ static int spl_mmc_do_fs_boot(struct spl_image_info *spl_image, struct disk_partition info; debug("Checking for the first MBR bootable partition\n"); for (int type_part = 1; type_part <= DOS_ENTRY_NUMBERS; type_part++) { - err = part_get_info(mmc_get_blk_desc(mmc), type_part, &info); - if (err) + ret = part_get_info(mmc_get_blk_desc(mmc), type_part, &info); + if (ret) continue; debug("Partition %d is of type %d and bootable=%d\n", type_part, info.sys_ind, info.bootable); if (info.bootable != 0) { @@ -233,40 +215,40 @@ static int spl_mmc_do_fs_boot(struct spl_image_info *spl_image, #ifdef CONFIG_SPL_FS_FAT if (!spl_start_uboot()) { - err = spl_load_image_fat_os(spl_image, bootdev, mmc_get_blk_desc(mmc), - partition); - if (!err) - return err; + ret = spl_load_image_fat_os(spl_image, bootdev, mmc_get_blk_desc(mmc), + partition); + if (!ret) + return 0; } #ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME - err = spl_load_image_fat(spl_image, bootdev, mmc_get_blk_desc(mmc), + ret = spl_load_image_fat(spl_image, bootdev, mmc_get_blk_desc(mmc), partition, filename); - if (!err) - return err; + if (!ret) + return ret; #endif #endif #ifdef CONFIG_SPL_FS_EXT4 if (!spl_start_uboot()) { - err = spl_load_image_ext_os(spl_image, bootdev, mmc_get_blk_desc(mmc), - partition); - if (!err) - return err; + ret = spl_load_image_ext_os(spl_image, bootdev, mmc_get_blk_desc(mmc), + partition); + if (!ret) + return 0; } #ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME - err = spl_load_image_ext(spl_image, bootdev, mmc_get_blk_desc(mmc), + ret = spl_load_image_ext(spl_image, bootdev, mmc_get_blk_desc(mmc), partition, filename); - if (!err) - return err; + if (!ret) + return 0; #endif #endif #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) - err = -ENOENT; + ret = -ENOENT; #endif - return err; + return ret; } #endif @@ -318,8 +300,8 @@ int default_spl_mmc_emmc_boot_partition(struct mmc *mmc) * which is the first physical partition (0). */ part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); - if (part == 7) - part = 0; + if (part == EMMC_BOOT_PART_USER) + part = EMMC_HWPART_DEFAULT; #endif return part; } @@ -354,87 +336,82 @@ int spl_mmc_load(struct spl_image_info *spl_image, unsigned long raw_sect) { u32 boot_mode; - int err = 0; + int ret = 0; __maybe_unused int part = 0; int mmc_dev; /* Perform peripheral init only once for an mmc device */ mmc_dev = spl_mmc_get_device_index(bootdev->boot_device); if (!mmc || spl_mmc_get_mmc_devnum(mmc) != mmc_dev) { - err = spl_mmc_find_device(&mmc, bootdev->boot_device); - if (err) - return err; + ret = spl_mmc_find_device(&mmc, mmc_dev); + if (ret) + return ret; - err = mmc_init(mmc); - if (err) { + ret = mmc_init(mmc); + if (ret) { mmc = NULL; -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("spl: mmc init failed with error: %d\n", err); -#endif - return err; + printf("spl: mmc init failed with error: %d\n", ret); + return ret; } } boot_mode = spl_mmc_boot_mode(mmc, bootdev->boot_device); - err = -EINVAL; + ret = -EINVAL; switch (boot_mode) { case MMCSD_MODE_EMMCBOOT: part = spl_mmc_emmc_boot_partition(mmc); if (CONFIG_IS_ENABLED(MMC_TINY)) - err = mmc_switch_part(mmc, part); + ret = mmc_switch_part(mmc, part); else - err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part); + ret = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part); - if (err) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + if (ret) { puts("spl: mmc partition switch failed\n"); -#endif - return err; + return ret; } /* Fall through */ case MMCSD_MODE_RAW: debug("spl: mmc boot mode: raw\n"); if (!spl_start_uboot()) { - err = mmc_load_image_raw_os(spl_image, bootdev, mmc); - if (!err) - return err; + ret = mmc_load_image_raw_os(spl_image, bootdev, mmc); + if (!ret) + return 0; } raw_sect = spl_mmc_get_uboot_raw_sector(mmc, raw_sect); #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION - err = mmc_load_image_raw_partition(spl_image, bootdev, + ret = mmc_load_image_raw_partition(spl_image, bootdev, mmc, raw_part, raw_sect); - if (!err) - return err; + if (!ret) + return 0; #endif #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR - err = mmc_load_image_raw_sector(spl_image, bootdev, mmc, - raw_sect + spl_mmc_raw_uboot_offset(part)); - if (!err) - return err; + ret = mmc_load_image_raw_sector(spl_image, bootdev, mmc, + raw_sect + + spl_mmc_raw_uboot_offset(part)); + if (!ret) + return 0; #endif /* If RAW mode fails, try FS mode. */ #ifdef CONFIG_SYS_MMCSD_FS_BOOT case MMCSD_MODE_FS: debug("spl: mmc boot mode: fs\n"); - err = spl_mmc_do_fs_boot(spl_image, bootdev, mmc, filename); - if (!err) - return err; + ret = spl_mmc_do_fs_boot(spl_image, bootdev, mmc, filename); + if (!ret) + return 0; break; #endif -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT default: puts("spl: mmc: wrong boot mode\n"); -#endif } - return err; + return ret; } int spl_mmc_load_image(struct spl_image_info *spl_image, diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 5631fa6d563..22883f4e8b9 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -71,9 +71,7 @@ static int spl_nand_load_element(struct spl_image_info *spl_image, { struct spl_load_info load; - load.priv = &offset; - spl_set_bl_len(&load, 1); - load.read = spl_nand_read; + spl_load_init(&load, spl_nand_read, &offset, 1); return spl_load(spl_image, bootdev, &load, 0, offset); } diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c index be7278bb933..2be7b73ed35 100644 --- a/common/spl/spl_net.c +++ b/common/spl/spl_net.c @@ -47,8 +47,7 @@ static int spl_net_load_image(struct spl_image_info *spl_image, return rv; } - spl_set_bl_len(&load, 1); - load.read = spl_net_load_read; + spl_load_init(&load, spl_net_load_read, NULL, 1); return spl_load(spl_image, bootdev, &load, 0, 0); } #endif diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index ed76b5e1293..1021d933999 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -49,8 +49,7 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, int ret; debug("Found FIT\n"); - spl_set_bl_len(&load, 1); - load.read = spl_nor_load_read; + spl_load_init(&load, spl_nor_load_read, NULL, 1); ret = spl_load_simple_fit(spl_image, &load, CONFIG_SYS_OS_BASE, @@ -93,8 +92,7 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, * Load real U-Boot from its location in NOR flash to its * defined location in SDRAM */ - spl_set_bl_len(&load, 1); - load.read = spl_nor_load_read; + spl_load_init(&load, spl_nor_load_read, NULL, 1); return spl_load(spl_image, bootdev, &load, 0, spl_nor_get_uboot_base()); } SPL_LOAD_IMAGE_METHOD("NOR", 0, BOOT_DEVICE_NOR, spl_nor_load_image); diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c index 5a23841f698..71b7a8374bb 100644 --- a/common/spl/spl_ram.c +++ b/common/spl/spl_ram.c @@ -69,8 +69,7 @@ static int spl_ram_load_image(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found FIT\n"); - spl_set_bl_len(&load, 1); - load.read = spl_ram_load_read; + spl_load_init(&load, spl_ram_load_read, NULL, 1); ret = spl_load_simple_fit(spl_image, &load, 0, header); } else { ulong u_boot_pos = spl_get_image_pos(); diff --git a/common/spl/spl_semihosting.c b/common/spl/spl_semihosting.c index 2047248f39b..f36863fe48d 100644 --- a/common/spl/spl_semihosting.c +++ b/common/spl/spl_semihosting.c @@ -43,9 +43,7 @@ static int spl_smh_load_image(struct spl_image_info *spl_image, } len = ret; - load.read = smh_fit_read; - spl_set_bl_len(&load, 1); - load.priv = &fd; + spl_load_init(&load, smh_fit_read, &fd, 1); ret = spl_load(spl_image, bootdev, &load, len, 0); if (ret) log_debug("could not read %s: %d\n", filename, ret); diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index 8ab4803f7c4..691a431a926 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -77,9 +77,7 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, return -ENODEV; } - load.priv = flash; - spl_set_bl_len(&load, 1); - load.read = spl_spi_fit_read; + spl_load_init(&load, spl_spi_fit_read, flash, 1); #if CONFIG_IS_ENABLED(OS_BOOT) if (spl_start_uboot()) { diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c index 4c7222af612..2be957134c1 100644 --- a/common/spl/spl_ymodem.c +++ b/common/spl/spl_ymodem.c @@ -132,11 +132,9 @@ int spl_ymodem_load_image(struct spl_image_info *spl_image, struct ymodem_fit_info info; debug("Found FIT\n"); - load.priv = (void *)&info; - spl_set_bl_len(&load, 1); + spl_load_init(&load, ymodem_read_fit, (void *)&info, 1); info.buf = buf; info.image_read = BUF_SIZE; - load.read = ymodem_read_fit; ret = spl_load_simple_fit(spl_image, &load, 0, (void *)buf); size = info.image_read; diff --git a/configs/a3y17lte_defconfig b/configs/a3y17lte_defconfig index 5c15d51fdc3..b012b985a30 100644 --- a/configs/a3y17lte_defconfig +++ b/configs/a3y17lte_defconfig @@ -23,4 +23,3 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_DM_I2C_GPIO=y -CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/a5y17lte_defconfig b/configs/a5y17lte_defconfig index 7c9b6b25117..25a7d5bc984 100644 --- a/configs/a5y17lte_defconfig +++ b/configs/a5y17lte_defconfig @@ -23,4 +23,3 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_DM_I2C_GPIO=y -CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/a7y17lte_defconfig b/configs/a7y17lte_defconfig index c7297f7d75c..c87379ab391 100644 --- a/configs/a7y17lte_defconfig +++ b/configs/a7y17lte_defconfig @@ -23,4 +23,3 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_DM_I2C_GPIO=y -CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index 7c7041c23b0..6b36f6edee0 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -33,7 +33,7 @@ CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ETH=y CONFIG_SPL_I2C=y diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig index a0163f16f36..d9acc81e9d3 100644 --- a/configs/am335x_pdu001_defconfig +++ b/configs/am335x_pdu001_defconfig @@ -25,7 +25,7 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_I2C=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_POWER=y diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 4eb406673ff..4c1f664edec 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -19,7 +19,7 @@ CONFIG_SYS_PBSIZE=1054 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set CONFIG_SPL_MTD=y diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig index 4a351cd015a..b905ff74f2a 100644 --- a/configs/am62ax_evm_a53_defconfig +++ b/configs/am62ax_evm_a53_defconfig @@ -30,6 +30,7 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig index 44ccb6baa90..092d0830623 100644 --- a/configs/am62ax_evm_r5_defconfig +++ b/configs/am62ax_evm_r5_defconfig @@ -39,6 +39,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_DMA=y diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig index 87005d03dee..9635beb1b27 100644 --- a/configs/am62px_evm_a53_defconfig +++ b/configs/am62px_evm_a53_defconfig @@ -37,6 +37,7 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index ace55696737..4f7be44cfba 100644 --- a/configs/am62px_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -40,6 +40,7 @@ CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_DMA=y diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig index 79c82d1ff7a..af54f9670a7 100644 --- a/configs/am62x_beagleplay_a53_defconfig +++ b/configs/am62x_beagleplay_a53_defconfig @@ -40,6 +40,7 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig index d0cc4f5b405..ee4c43ff97f 100644 --- a/configs/am62x_beagleplay_r5_defconfig +++ b/configs/am62x_beagleplay_r5_defconfig @@ -45,6 +45,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_DM_MAILBOX=y diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index ca993b427bd..0b7ee942a0a 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -38,6 +38,7 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" diff --git a/configs/am62x_evm_a53_ethboot_defconfig b/configs/am62x_evm_a53_ethboot_defconfig new file mode 100644 index 00000000000..9d3c6b889f0 --- /dev/null +++ b/configs/am62x_evm_a53_ethboot_defconfig @@ -0,0 +1,17 @@ +#include <configs/am62x_evm_a53_defconfig> + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_AM625=y +CONFIG_TARGET_AM625_A53_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-sk" +CONFIG_SPL_STACK_R_ADDR=0x83000000 +CONFIG_SPL_SIZE_LIMIT=0x80000 +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_ETH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM62X U-Boot A53 SPL" +CONFIG_SPL_SYSCON=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index 4b2e57b13a0..78ed3f62d06 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -47,6 +47,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_DM_MAILBOX=y diff --git a/configs/am62x_evm_r5_ethboot_defconfig b/configs/am62x_evm_r5_ethboot_defconfig new file mode 100644 index 00000000000..0d823743907 --- /dev/null +++ b/configs/am62x_evm_r5_ethboot_defconfig @@ -0,0 +1,25 @@ +#include<configs/am62x_evm_r5_defconfig> + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_AM625=y +CONFIG_TARGET_AM625_R5_EVM=y +CONFIG_DEFAULT_DEVICEC_TREE="k3-am625-r5-sk" +CONFIG_SPL_GPIO=y +CONFIG_SPL_MMC=n +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 +CONFIG_SPL_BSS_MAX_SIZE=0X3100 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_ETH=y +CONFIG_SPL_I2C=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM62X U-Boot R5 SPL" +CONFIG_CMD_DHCP=y +CONFIG_SPL_SYSCON=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_DM_I2C=y +CONFIG_PHY_TI_DP83867=y +CONFIG_TI_AM65_CPSW_NUSS=y diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 5b01002dfc4..e6e3e018da6 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -43,6 +43,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800 CONFIG_SPL_DMA=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index 96475d4c1b8..1e83b7ff1fe 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -50,6 +50,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_DMA=y diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 925a88e2547..f22b9afdb3b 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 4fc9c39711c..1660bf93530 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -46,6 +46,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_DMA=y diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index e9fb4c75988..466147f3bf2 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis" CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 CONFIG_TARGET_APALIS_IMX8=y +CONFIG_IMX_BOOTAUX=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SYS_LOAD_ADDR=0x95400000 CONFIG_SYS_MEMTEST_START=0x88000000 diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig index 20d2cff93f7..dca6e0ca8ba 100644 --- a/configs/apple_m1_defconfig +++ b/configs/apple_m1_defconfig @@ -26,4 +26,3 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_NO_FB_CLEAR=y CONFIG_VIDEO_SIMPLE=y # CONFIG_SMBIOS is not set -CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig index 47b37bbc807..2f29cb3dc46 100644 --- a/configs/brppt2_defconfig +++ b/configs/brppt2_defconfig @@ -34,7 +34,7 @@ CONFIG_SYS_PBSIZE=532 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC=y -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_I2C=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig index dc868b72b21..a17afdee7ff 100644 --- a/configs/brsmarc1_defconfig +++ b/configs/brsmarc1_defconfig @@ -42,7 +42,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_I2C=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_DM_SPI_FLASH=y diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig index 24dfdae11e3..a9283ad49ea 100644 --- a/configs/cgtqmx8_defconfig +++ b/configs/cgtqmx8_defconfig @@ -43,6 +43,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000 CONFIG_SPL_SYS_MALLOC_SIZE=0x3000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=0 diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index e5d805d7da7..93bf4f5c592 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -38,7 +38,7 @@ CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_CMD_GPIO=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 9bc59539dc8..a1df1f830f0 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -37,7 +37,7 @@ CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_CMD_GPIO=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 26fa05e543b..03520b6af40 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -38,7 +38,7 @@ CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_CMD_GPIO=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 5deb09b28ec..607fd288197 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -38,7 +38,7 @@ CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_CMD_GPIO=y diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig index 39f33844e46..90574d2a157 100644 --- a/configs/ci20_mmc_defconfig +++ b/configs/ci20_mmc_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_SPL_MAX_SIZE=0x2e00 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set # CONFIG_SPL_BANNER_PRINT is not set +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1c CONFIG_SPL_MMC_TINY=y diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index e76373e499a..d7b1b76c21d 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -13,6 +13,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri" CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 CONFIG_TARGET_COLIBRI_IMX8X=y +CONFIG_IMX_SNVS_SEC_SC=y +CONFIG_IMX_BOOTAUX=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SYS_LOAD_ADDR=0x95c00000 CONFIG_SYS_MEMTEST_START=0x88000000 diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 30d1a93fec3..d10faa5b275 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -50,7 +50,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0f70000 CONFIG_SPL_SYS_MALLOC_SIZE=0x110000 -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 62cbd02b69a..7e59b6ff876 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -46,7 +46,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0f70000 CONFIG_SPL_SYS_MALLOC_SIZE=0x110000 -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y diff --git a/configs/deneb_defconfig b/configs/deneb_defconfig index 4b9b0734c5a..4731e84e388 100644 --- a/configs/deneb_defconfig +++ b/configs/deneb_defconfig @@ -55,6 +55,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000 CONFIG_SPL_SYS_MALLOC_SIZE=0x3000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_POWER_DOMAIN=y diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 1d3336b8c6a..7463f4f52b5 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -42,7 +42,7 @@ CONFIG_SYS_PBSIZE=2076 CONFIG_MISC_INIT_R=y CONFIG_SPL_BOOTCOUNT_LIMIT=y CONFIG_SPL_SYS_MALLOC=y -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SAVEENV=y diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 7c681f095c5..59d0c5d0370 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -39,7 +39,7 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2084 CONFIG_MISC_INIT_R=y CONFIG_SPL_SYS_MALLOC=y -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/draco-rastaban_defconfig b/configs/draco-rastaban_defconfig index 81a349b730c..ea6518e142e 100644 --- a/configs/draco-rastaban_defconfig +++ b/configs/draco-rastaban_defconfig @@ -33,7 +33,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000 -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y diff --git a/configs/draco-thuban_defconfig b/configs/draco-thuban_defconfig index 265c1138dfe..4672d4b2873 100644 --- a/configs/draco-thuban_defconfig +++ b/configs/draco-thuban_defconfig @@ -33,7 +33,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000 -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_I2C=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig deleted file mode 100644 index 004f1866162..00000000000 --- a/configs/ethernut5_defconfig +++ /dev/null @@ -1,87 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_AT91=y -CONFIG_TEXT_BASE=0x27000000 -CONFIG_SYS_MALLOC_LEN=0x121000 -CONFIG_TARGET_ETHERNUT5=y -CONFIG_AT91_EFLASH=y -CONFIG_EFLASH_PROTSECTORS=1 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x21000 -CONFIG_ENV_OFFSET=0x3DE000 -CONFIG_ENV_SECT_SIZE=0x21000 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="ethernut5" -CONFIG_SYS_LOAD_ADDR=0x020000000 -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x22000000 0xc6000 0x294000; bootm 0x22000000" -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=281 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="U-Boot> " -# CONFIG_CMD_BDI is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_UNZIP=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SPI=y -CONFIG_CMD_DHCP=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_RARP=y -CONFIG_SYS_DISABLE_AUTOLOAD=y -CONFIG_CMD_MII=y -# CONFIG_CMD_MDIO is not set -CONFIG_CMD_PING=y -CONFIG_CMD_CDP=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_DNS=y -CONFIG_CMD_BSP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=atmel_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:-(root)" -CONFIG_CMD_UBI=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RETRY_COUNT=20 -CONFIG_CLK=y -CONFIG_CLK_AT91=y -CONFIG_AT91_GPIO=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SLAVE=0 -CONFIG_GENERIC_ATMEL_MCI=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_SYS_MAX_FLASH_SECT=32 -CONFIG_MTD_RAW_NAND=y -# CONFIG_SYS_NAND_USE_FLASH_BBT is not set -CONFIG_NAND_ATMEL=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_SPI_FLASH_DATAFLASH=y -CONFIG_MACB=y -CONFIG_RMII=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_AT91=y -CONFIG_RTC_PCF8563=y -CONFIG_DM_SERIAL=y -CONFIG_ATMEL_USART=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_USB=y -CONFIG_JFFS2_NAND=y diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig index 3b9466c830f..42f116fac13 100644 --- a/configs/gardena-smart-gateway-at91sam_defconfig +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -46,7 +46,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_RAW_ONLY=y CONFIG_SPL_NAND_DRIVERS=y diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig index c7390d1d323..774ab647ccd 100644 --- a/configs/giedi_defconfig +++ b/configs/giedi_defconfig @@ -55,6 +55,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000 CONFIG_SPL_SYS_MALLOC_SIZE=0x3000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_POWER_DOMAIN=y diff --git a/configs/ibex-ast2700_defconfig b/configs/ibex-ast2700_defconfig new file mode 100644 index 00000000000..855615cc1ea --- /dev/null +++ b/configs/ibex-ast2700_defconfig @@ -0,0 +1,94 @@ +CONFIG_RISCV=y +CONFIG_SYS_DCACHE_OFF=y +# CONFIG_SPL_USE_ARCH_MEMCPY is not set +# CONFIG_SPL_USE_ARCH_MEMMOVE is not set +# CONFIG_SPL_USE_ARCH_MEMSET is not set +CONFIG_TEXT_BASE=0x80000000 +CONFIG_SYS_MALLOC_LEN=0xf00 +CONFIG_SYS_MALLOC_F_LEN=0xf00 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x14bd7800 +CONFIG_ENV_SIZE=0x20000 +CONFIG_DEFAULT_DEVICE_TREE="ast2700-ibex" +CONFIG_SPL_TEXT_BASE=0x14bc0080 +CONFIG_DM_RESET=y +CONFIG_SPL_BSS_START_ADDR=0x14bd7800 +CONFIG_SPL_BSS_MAX_SIZE=0x800 +CONFIG_SPL_SIZE_LIMIT=0x16000 +CONFIG_SPL=y +CONFIG_SYS_MEM_TOP_HIDE=0x10000000 +CONFIG_SYS_LOAD_ADDR=0x83000000 +CONFIG_BUILD_TARGET="" +CONFIG_TARGET_ASPEED_AST2700_IBEX=y +# CONFIG_RISCV_ISA_F is not set +# CONFIG_RISCV_ISA_A is not set +# CONFIG_SPL_SMP is not set +CONFIG_XIP=y +CONFIG_SPL_XIP=y +# CONFIG_AVAILABLE_HARTS is not set +CONFIG_STACK_SIZE_SHIFT=11 +CONFIG_ENV_VARS_UBOOT_CONFIG=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_STACK_SIZE=0x100000 +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x200c0000 +# CONFIG_BOOTSTD is not set +CONFIG_SYS_BOOTM_LEN=0x4000000 +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +# CONFIG_CONSOLE_FLUSH_SUPPORT is not set +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_STDIO_DEREGISTER=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x16000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_BOOTM_LINUX is not set +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DEVICE_TREE_INCLUDES="ast2700-u-boot.dtsi" +# CONFIG_OF_TAG_MIGRATE is not set +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_SYS_RX_ETH_BUFFER=2 +# CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_DM_SEQ_ALIAS is not set +# CONFIG_BLOCK_CACHE is not set +# CONFIG_CPU is not set +# CONFIG_GPIO is not set +# CONFIG_I2C is not set +CONFIG_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_SDHCI=y +# CONFIG_MTD is not set +# CONFIG_POWER is not set +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_ASPEED_RAM=y +# CONFIG_RAM_SIFIVE is not set +CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y +CONFIG_AST_IBEX_TIMER=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +# CONFIG_RSA is not set +# CONFIG_EFI_LOADER is not set diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig index 822a329187f..d1470014fd7 100644 --- a/configs/imx28_xea_defconfig +++ b/configs/imx28_xea_defconfig @@ -48,6 +48,7 @@ CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x0 CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y diff --git a/configs/imx28_xea_sb_defconfig b/configs/imx28_xea_sb_defconfig index 8d48d8c5078..aa1116aa4b0 100644 --- a/configs/imx28_xea_sb_defconfig +++ b/configs/imx28_xea_sb_defconfig @@ -29,6 +29,7 @@ CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0 CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index 7203583003c..b893da6c92a 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -30,7 +30,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SPL_RAW_IMAGE_SUPPORT=y CONFIG_SPL_SYS_MALLOC=y -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_DMA=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" CONFIG_SPL_I2C=y diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index f5bb50c5f39..0b7dd632b59 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index b36ad7c867c..9312e9f72a7 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -39,6 +39,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index d4e9d9f342d..f37297cdbf7 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_POWER=y diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index c85a14119e7..950246ecded 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_POWER=y diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index 5e6bbb3e508..8644177a769 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -52,6 +52,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig index 16ba7d4b4f1..6570c9fbcd6 100644 --- a/configs/imx8mm-phygate-tauri-l_defconfig +++ b/configs/imx8mm-phygate-tauri-l_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index e3dcbfe0452..7f0cb9a06bf 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig index 0aca853afd9..354a671bafb 100644 --- a/configs/imx8mm_beacon_fspi_defconfig +++ b/configs/imx8mm_beacon_fspi_defconfig @@ -41,6 +41,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index f26a8791cd0..34566d4b7ef 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -59,6 +59,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -105,6 +106,8 @@ CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CAT=y +CONFIG_CMD_XXD=y CONFIG_CMD_DHCP=y CONFIG_CMD_DHCP6=y CONFIG_CMD_TFTPPUT=y diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 788770bb364..3fd2d9ffd11 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig index a57dc47f26f..96c0a46bcec 100644 --- a/configs/imx8mm_evk_fspi_defconfig +++ b/configs/imx8mm_evk_fspi_defconfig @@ -39,6 +39,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mm_phg_defconfig b/configs/imx8mm_phg_defconfig index e14dcdf9a3d..2fd319b3a6c 100644 --- a/configs/imx8mm_phg_defconfig +++ b/configs/imx8mm_phg_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index f4d999bfcef..3633401a349 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -138,7 +139,6 @@ CONFIG_DM_PMIC_MP5416=y CONFIG_SPL_DM_PMIC_MP5416=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -# CONFIG_DM_RNG is not set CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index 1129d8070cc..7a1931510e8 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -48,6 +48,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index f4af99847d1..eebfb0d7a7d 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -47,6 +47,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig index cecde443367..6acbb8a0215 100644 --- a/configs/imx8mn_beacon_fspi_defconfig +++ b/configs/imx8mn_beacon_fspi_defconfig @@ -47,6 +47,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig index b4351a392ef..29d7cdab922 100644 --- a/configs/imx8mn_bsh_smm_s2_defconfig +++ b/configs/imx8mn_bsh_smm_s2_defconfig @@ -42,6 +42,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_DMA=y diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig index 0faa3376fd3..151a9a520ab 100644 --- a/configs/imx8mn_bsh_smm_s2pro_defconfig +++ b/configs/imx8mn_bsh_smm_s2pro_defconfig @@ -43,6 +43,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 82e3ce19480..93380a0ddde 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -41,6 +41,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index 679ca71ade0..5405f8f5265 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig index 218415fad57..0155cb2044e 100644 --- a/configs/imx8mn_var_som_defconfig +++ b/configs/imx8mn_var_som_defconfig @@ -46,6 +46,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index b65fef0a806..d2925f247e1 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -46,6 +46,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -133,7 +134,6 @@ CONFIG_SPL_DM_PMIC_MP5416=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -# CONFIG_DM_RNG is not set CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig index 05f68c7e2ae..497a908f7a7 100644 --- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig +++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig index 3c337d4bd25..ba676c95467 100644 --- a/configs/imx8mp_beacon_defconfig +++ b/configs/imx8mp_beacon_defconfig @@ -53,6 +53,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig index fe3e757eefd..0e910e2a2ea 100644 --- a/configs/imx8mp_data_modul_edm_sbc_defconfig +++ b/configs/imx8mp_data_modul_edm_sbc_defconfig @@ -66,6 +66,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -112,6 +113,8 @@ CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CAT=y +CONFIG_CMD_XXD=y CONFIG_CMD_DHCP=y CONFIG_CMD_DHCP6=y CONFIG_CMD_TFTPPUT=y diff --git a/configs/imx8mp_debix_model_a_defconfig b/configs/imx8mp_debix_model_a_defconfig index aa1de6d6909..c76ab232b12 100644 --- a/configs/imx8mp_debix_model_a_defconfig +++ b/configs/imx8mp_debix_model_a_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index 79b3e96c8e3..f807b0cfc37 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -64,6 +64,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 # CONFIG_SPL_FIT_IMAGE_TINY is not set diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig index 8ef8bf4db27..05895d6dd6f 100644 --- a/configs/imx8mp_dhcom_pdk3_defconfig +++ b/configs/imx8mp_dhcom_pdk3_defconfig @@ -66,6 +66,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 # CONFIG_SPL_FIT_IMAGE_TINY is not set diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index a2c07967f59..4b9ac30fed1 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -41,6 +41,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig index 54789365aa9..7a7f3907b06 100644 --- a/configs/imx8mp_rsb3720a1_4G_defconfig +++ b/configs/imx8mp_rsb3720a1_4G_defconfig @@ -53,6 +53,8 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig index 4b0b71d03d9..75d110f91d1 100644 --- a/configs/imx8mp_rsb3720a1_6G_defconfig +++ b/configs/imx8mp_rsb3720a1_6G_defconfig @@ -53,6 +53,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index df93774b307..09a88418143 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -48,6 +48,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y @@ -138,7 +139,6 @@ CONFIG_DM_PMIC_MP5416=y CONFIG_SPL_DM_PMIC_MP5416=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -# CONFIG_DM_RNG is not set CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig index 5eb96d3826a..ac45c3d669d 100644 --- a/configs/imx8mq_cm_defconfig +++ b/configs/imx8mq_cm_defconfig @@ -40,6 +40,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 3c1701a3768..2a51681c335 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -42,6 +42,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig index 3a3fb754fa4..4c36827b2ae 100644 --- a/configs/imx8mq_phanbell_defconfig +++ b/configs/imx8mq_phanbell_defconfig @@ -43,6 +43,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig index 1844e3c8b84..2a951f16de4 100644 --- a/configs/imx8mq_reform2_defconfig +++ b/configs/imx8mq_reform2_defconfig @@ -45,6 +45,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index bf02d3e4f67..a96fb310cdd 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -48,6 +48,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000 CONFIG_SPL_SYS_MALLOC_SIZE=0x3000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_POWER_DOMAIN=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index d6b79f53893..56cc8347926 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -49,6 +49,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000 CONFIG_SPL_SYS_MALLOC_SIZE=0x3000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_POWER_DOMAIN=y diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig index 0f0748b6792..c20b9048cf0 100644 --- a/configs/imx8ulp_evk_defconfig +++ b/configs/imx8ulp_evk_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x22040000 CONFIG_SPL_SYS_MALLOC_SIZE=0x8000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_WATCHDOG=y diff --git a/configs/imx93-phyboard-segin_defconfig b/configs/imx93-phyboard-segin_defconfig index e3eb0029fa4..6e9e9c5a19b 100644 --- a/configs/imx93-phyboard-segin_defconfig +++ b/configs/imx93-phyboard-segin_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_LOAD_IMX_CONTAINER=y CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg" # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 CONFIG_SPL_I2C=y diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 6f083e0cd8c..198d43ec9e0 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -42,6 +42,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 CONFIG_SPL_I2C=y diff --git a/configs/imx93_11x11_evk_ld_defconfig b/configs/imx93_11x11_evk_ld_defconfig index deed068550a..fd33fd54762 100644 --- a/configs/imx93_11x11_evk_ld_defconfig +++ b/configs/imx93_11x11_evk_ld_defconfig @@ -43,6 +43,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 CONFIG_SPL_I2C=y diff --git a/configs/imx93_var_som_defconfig b/configs/imx93_var_som_defconfig index 94ce213f93a..14f220e8a3c 100644 --- a/configs/imx93_var_som_defconfig +++ b/configs/imx93_var_som_defconfig @@ -45,6 +45,7 @@ CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_LOAD_IMX_CONTAINER=y CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg" # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 CONFIG_SPL_I2C=y diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig index 80c8769926e..72bbd720153 100644 --- a/configs/imxrt1020-evk_defconfig +++ b/configs/imxrt1020-evk_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 # CONFIG_BOOTM_NETBSD is not set diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index 086fc47ec27..fdbce8e6aa9 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 CONFIG_SPL_NOR_SUPPORT=y diff --git a/configs/imxrt1050-evk_fspi_defconfig b/configs/imxrt1050-evk_fspi_defconfig index 4b252cfa5d0..03543ed0a30 100644 --- a/configs/imxrt1050-evk_fspi_defconfig +++ b/configs/imxrt1050-evk_fspi_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 CONFIG_SPL_NOR_SUPPORT=y diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig index 83825da6de9..fe0058aa5ce 100644 --- a/configs/imxrt1170-evk_defconfig +++ b/configs/imxrt1170-evk_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 # CONFIG_BOOTM_NETBSD is not set diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig index 8654bf20865..2a7a958dec2 100644 --- a/configs/iot2050_defconfig +++ b/configs/iot2050_defconfig @@ -53,6 +53,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DM_MAILBOX=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index fcfa9265996..137ca3f0d02 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -45,6 +45,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800 CONFIG_SPL_DMA=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index e023af24674..774a9eff439 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_DMA=y diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig index 86c565a9211..ed75f7ee051 100644 --- a/configs/j721e_beagleboneai64_a72_defconfig +++ b/configs/j721e_beagleboneai64_a72_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y diff --git a/configs/j721e_beagleboneai64_r5_defconfig b/configs/j721e_beagleboneai64_r5_defconfig index 314161b8a62..ce96e4921b8 100644 --- a/configs/j721e_beagleboneai64_r5_defconfig +++ b/configs/j721e_beagleboneai64_r5_defconfig @@ -42,6 +42,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_DMA=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index f99315789c7..640c1be2b93 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index f1c9bbd3fa8..3b4a7c3c0ee 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -49,6 +49,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_DMA=y diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 5800e4be963..d78ebb5cfd4 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -43,6 +43,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index d0af664a6b7..b6adb6a77d7 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -50,6 +50,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_DMA=y diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig index 1675cedb25e..98620222a07 100644 --- a/configs/j722s_evm_a53_defconfig +++ b/configs/j722s_evm_a53_defconfig @@ -37,6 +37,7 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig index 8ba3916807d..e574be9e19d 100644 --- a/configs/j722s_evm_r5_defconfig +++ b/configs/j722s_evm_r5_defconfig @@ -40,6 +40,7 @@ CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_DMA=y diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index 520a53b12f6..f0220170bbf 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -38,6 +38,7 @@ CONFIG_LOGLEVEL=7 CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index 543b0a50d7a..a1168819497 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_DMA=y diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 1b7d22b43e1..d85a4335c63 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig index c2133470fc9..52238831229 100644 --- a/configs/kontron_pitx_imx8m_defconfig +++ b/configs/kontron_pitx_imx8m_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index a1d5f89b1ec..c4493e50a32 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -51,6 +51,7 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x900 CONFIG_SPL_MPC8XXX_INIT_DDR=y diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig index 6999a689e29..248fc1fdde4 100644 --- a/configs/librem5_defconfig +++ b/configs/librem5_defconfig @@ -46,6 +46,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index 2354f4113ae..981093a9fb5 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -49,6 +49,7 @@ CONFIG_SPL_FSL_PBL=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82080000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 136ca9a2670..4fc0e66e485 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -60,6 +60,7 @@ CONFIG_SPL_FSL_PBL=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80200000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index befb4ae442c..72632b87701 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -59,6 +59,7 @@ CONFIG_SPL_FSL_PBL=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x820c0000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index db06a03fe6b..78dce4dcbba 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -58,6 +58,7 @@ CONFIG_SPL_FSL_PBL=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x820c0000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index e5d8eeb8a2f..0853bfbd3a0 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -52,6 +52,7 @@ CONFIG_SPL_FSL_PBL=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82100000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index dc0e507263f..28434d8e191 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -60,6 +60,7 @@ CONFIG_SPL_FSL_PBL=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82104000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 9980d6106ec..b4348f12678 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -61,6 +61,7 @@ CONFIG_SPL_FSL_PBL=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82100000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index ed92e34dccf..8d2c391f0e8 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -62,6 +62,7 @@ CONFIG_SPL_FSL_PBL=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82100000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig index d350ec14eb1..1186763a73c 100644 --- a/configs/milkv_duo_defconfig +++ b/configs/milkv_duo_defconfig @@ -1,6 +1,6 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0x820000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82300000 @@ -26,6 +26,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK_SOPHGO_CV1800B=y CONFIG_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig index 2e1d112a3e7..47ed5cfb214 100644 --- a/configs/msc_sm2s_imx8mp_defconfig +++ b/configs/msc_sm2s_imx8mp_defconfig @@ -43,6 +43,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/mt7981_emmc_rfb_defconfig b/configs/mt7981_emmc_rfb_defconfig index 76ee2aa2d66..d3e833905f3 100644 --- a/configs/mt7981_emmc_rfb_defconfig +++ b/configs/mt7981_emmc_rfb_defconfig @@ -62,4 +62,3 @@ CONFIG_MTK_SERIAL=y CONFIG_FAT_WRITE=y CONFIG_HEXDUMP=y # CONFIG_EFI_LOADER is not set -CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/mt7981_rfb_defconfig b/configs/mt7981_rfb_defconfig index 3989c79d2b1..4bc2173f13d 100644 --- a/configs/mt7981_rfb_defconfig +++ b/configs/mt7981_rfb_defconfig @@ -65,4 +65,3 @@ CONFIG_DM_SPI=y CONFIG_MTK_SPIM=y CONFIG_HEXDUMP=y # CONFIG_EFI_LOADER is not set -CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/mt7981_sd_rfb_defconfig b/configs/mt7981_sd_rfb_defconfig index 9b332455279..8721b4074ac 100644 --- a/configs/mt7981_sd_rfb_defconfig +++ b/configs/mt7981_sd_rfb_defconfig @@ -62,4 +62,3 @@ CONFIG_MTK_SERIAL=y CONFIG_FAT_WRITE=y CONFIG_HEXDUMP=y # CONFIG_EFI_LOADER is not set -CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/mt7986_rfb_defconfig b/configs/mt7986_rfb_defconfig index 4d0cc85d0e5..15c31de236f 100644 --- a/configs/mt7986_rfb_defconfig +++ b/configs/mt7986_rfb_defconfig @@ -65,4 +65,3 @@ CONFIG_DM_SPI=y CONFIG_MTK_SPIM=y CONFIG_HEXDUMP=y # CONFIG_EFI_LOADER is not set -CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/mt7986a_bpir3_emmc_defconfig b/configs/mt7986a_bpir3_emmc_defconfig index 3c296ab803e..56921f36057 100644 --- a/configs/mt7986a_bpir3_emmc_defconfig +++ b/configs/mt7986a_bpir3_emmc_defconfig @@ -62,4 +62,3 @@ CONFIG_MTK_SERIAL=y CONFIG_FAT_WRITE=y CONFIG_HEXDUMP=y # CONFIG_EFI_LOADER is not set -CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/mt7986a_bpir3_sd_defconfig b/configs/mt7986a_bpir3_sd_defconfig index f644070f4e1..4ed06b72d52 100644 --- a/configs/mt7986a_bpir3_sd_defconfig +++ b/configs/mt7986a_bpir3_sd_defconfig @@ -62,4 +62,3 @@ CONFIG_MTK_SERIAL=y CONFIG_FAT_WRITE=y CONFIG_HEXDUMP=y # CONFIG_EFI_LOADER is not set -CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/mt7988_rfb_defconfig b/configs/mt7988_rfb_defconfig index d0ed2cc1c91..f7ceaceb303 100644 --- a/configs/mt7988_rfb_defconfig +++ b/configs/mt7988_rfb_defconfig @@ -81,4 +81,3 @@ CONFIG_MTK_SPIM=y CONFIG_LZO=y CONFIG_HEXDUMP=y # CONFIG_EFI_LOADER is not set -CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/mt7988_sd_rfb_defconfig b/configs/mt7988_sd_rfb_defconfig index 5631eaa338f..808c8b90116 100644 --- a/configs/mt7988_sd_rfb_defconfig +++ b/configs/mt7988_sd_rfb_defconfig @@ -69,4 +69,3 @@ CONFIG_MTK_SPIM=y CONFIG_LZO=y CONFIG_HEXDUMP=y # CONFIG_EFI_LOADER is not set -CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index 9beb045d7df..e927bb21658 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -9,7 +9,7 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_MX6SL=y CONFIG_TARGET_MX6SLEVK=y CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6sl-evk" # CONFIG_CMD_BMODE is not set CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y @@ -38,7 +38,6 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y @@ -63,9 +62,13 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_SYSRESET_WATCHDOG_AUTO=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig deleted file mode 100644 index 3491cbc5b10..00000000000 --- a/configs/mx6slevk_spinor_defconfig +++ /dev/null @@ -1,71 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_TEXT_BASE=0x87800000 -CONFIG_SYS_MALLOC_LEN=0x300000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MX6SL=y -CONFIG_TARGET_MX6SLEVK=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" -# CONFIG_CMD_BMODE is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SPI_BOOT=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" -CONFIG_SYS_PBSIZE=532 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MXC=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHYLIB=y -CONFIG_PHY_SMSC=y -CONFIG_FEC_MXC=y -CONFIG_MII=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX6=y -CONFIG_DM_PMIC=y -CONFIG_DM_PMIC_PFUZE100=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_PFUZE100=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_DM_SERIAL=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_MXC_SPI=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_THERMAL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig deleted file mode 100644 index 9c923609000..00000000000 --- a/configs/mx6slevk_spl_defconfig +++ /dev/null @@ -1,88 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_TEXT_BASE=0x87800000 -CONFIG_SYS_MALLOC_LEN=0x300000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x80000 -CONFIG_MX6SL=y -CONFIG_TARGET_MX6SLEVK=y -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" -CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SYS_MONITOR_LEN=409600 -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_SPL_LIBDISK_SUPPORT=y -# CONFIG_CMD_BMODE is not set -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" -CONFIG_SYS_PBSIZE=532 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" -CONFIG_SPL_I2C=y -CONFIG_SPL_WATCHDOG=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_BOUNCE_BUFFER=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_MXC=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHYLIB=y -CONFIG_PHY_SMSC=y -CONFIG_FEC_MXC=y -CONFIG_MII=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX6=y -CONFIG_DM_PMIC=y -CONFIG_DM_PMIC_PFUZE100=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_PFUZE100=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_DM_SERIAL=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_MXC_SPI=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_THERMAL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index 843b61dec4a..29aa01fb3d7 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -22,7 +22,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set CONFIG_SPL_MTD=y diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index bbd1b746cf9..4c60514dacf 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -23,7 +23,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set CONFIG_SPL_MTD=y diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index cc0b61af509..42c6aadea97 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -3,7 +3,7 @@ CONFIG_ARM=y # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_MALLOC_F_LEN=0x4000 -CONFIG_DEFAULT_DEVICE_TREE="omap3-evm" +CONFIG_DEFAULT_DEVICE_TREE="ti/omap/omap3-evm" CONFIG_TARGET_OMAP3_EVM=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL=y @@ -42,10 +42,9 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(spl),1920k(u-boot),128k(u-boot-env),128k(dtb),6m(kernel),-(rootfs)" CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_SPL_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FAT=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index ed04386cf95..e3791daf249 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -21,7 +21,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set CONFIG_SPL_MTD=y diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index c5d76d0d086..e9291d527dd 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -23,7 +23,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set CONFIG_SPL_MTD=y diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 6748e6fafbc..61a3ead9b15 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -40,6 +40,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 63f8a80ba99..b63a96fff14 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -6,8 +6,10 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_PHYTEC_SOM_DETECTION=y +CONFIG_SF_DEFAULT_SPEED=80000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 +CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-phyboard-pollux-rdk" @@ -24,12 +26,15 @@ CONFIG_SPL_BSS_START_ADDR=0x98fc00 CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3e0000 +CONFIG_IMX_BOOTAUX=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y +CONFIG_FDT_FIXUP_PARTITIONS=y CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 @@ -44,11 +49,14 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 # CONFIG_SPL_CRYPTO is not set CONFIG_SPL_I2C=y +CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_POWER=y +CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " @@ -64,6 +72,8 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y @@ -77,10 +87,12 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 @@ -113,6 +125,17 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_TI_DP83867=y CONFIG_DM_ETH_PHY=y @@ -134,6 +157,9 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_POWER_I2C=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 39161b722b1..67f89e03fbf 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -12,7 +12,7 @@ CONFIG_TARGET_PHYCORE_AM62X_A53=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000 CONFIG_SF_DEFAULT_SPEED=25000000 -CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x680000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-phyboard-lyra-rdk" @@ -40,13 +40,14 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="run mmcboot; bootflow scan -lb" +CONFIG_BOOTCOMMAND="run ${boot}boot; bootflow scan -lb" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_ENV_SUPPORT=y @@ -92,7 +93,7 @@ CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y -CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y @@ -151,7 +152,7 @@ CONFIG_SPL_USB_DWC3_AM62=y CONFIG_USB_DWC3_AM62=y CONFIG_USB_GADGET=y CONFIG_SPL_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Phytec" +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index b7d0273dd74..7fc3abf1262 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -48,6 +48,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_I2C=y diff --git a/configs/phycore_am62x_r5_usbdfu_defconfig b/configs/phycore_am62x_r5_usbdfu_defconfig new file mode 100644 index 00000000000..ff17a29e1a7 --- /dev/null +++ b/configs/phycore_am62x_r5_usbdfu_defconfig @@ -0,0 +1,9 @@ +#include <configs/phycore_am62x_r5_defconfig> +#include <configs/am62x_r5_usbdfu.config> + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_AM625=y +CONFIG_TARGET_PHYCORE_AM62X_R5=y + +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index 1af72e8bb32..3bfe8761309 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -37,7 +37,8 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y -CONFIG_BOOTCOMMAND="run mmcboot; bootflow scan -lb" +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run ${boot}boot; bootflow scan -lb" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x180000 @@ -45,6 +46,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y diff --git a/configs/phycore_am64x_r5_defconfig b/configs/phycore_am64x_r5_defconfig index a0d78241928..72d10f76647 100644 --- a/configs/phycore_am64x_r5_defconfig +++ b/configs/phycore_am64x_r5_defconfig @@ -49,6 +49,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_DMA=y diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig index cf91eb563b9..ef876abbd36 100644 --- a/configs/pico-imx8mq_defconfig +++ b/configs/pico-imx8mq_defconfig @@ -43,6 +43,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/qcm6490_defconfig b/configs/qcm6490_defconfig new file mode 100644 index 00000000000..5ddc5ab3ef8 --- /dev/null +++ b/configs/qcm6490_defconfig @@ -0,0 +1,21 @@ +# Configuration for building U-Boot to be flashed +# to the uefi partition of QCM6490 dev boards with +# the "Linux Embedded" partition layout (which have +# a dedicated "uefi" partition for edk2/U-Boot) + +#include "qcom_defconfig" + +# Otherwise buildman thinks this isn't an ARM platform +CONFIG_ARM=y + +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_BASE=0x994000 +CONFIG_DEBUG_UART_MSM_GENI=y +CONFIG_DEBUG_UART_CLOCK=14745600 + +# Address where U-Boot will be loaded +CONFIG_TEXT_BASE=0x9fc00000 +CONFIG_REMAKE_ELF=y + +CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs6490-rb3gen2" diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 8852e83a52b..2a2253f766d 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -3,6 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_POSITION_INDEPENDENT=y CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 CONFIG_ARCH_SNAPDRAGON=y +CONFIG_NR_DRAM_BANKS=24 CONFIG_DEFAULT_DEVICE_TREE="qcom/sdm845-db845c" CONFIG_SYS_LOAD_ADDR=0xA0000000 CONFIG_BUTTON_CMD=y @@ -44,6 +45,7 @@ CONFIG_CLK_QCOM_APQ8016=y CONFIG_CLK_QCOM_APQ8096=y CONFIG_CLK_QCOM_QCM2290=y CONFIG_CLK_QCOM_QCS404=y +CONFIG_CLK_QCOM_SC7280=y CONFIG_CLK_QCOM_SDM845=y CONFIG_CLK_QCOM_SM6115=y CONFIG_CLK_QCOM_SM8250=y @@ -117,4 +119,3 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_NO_FB_CLEAR=y CONFIG_VIDEO_SIMPLE=y CONFIG_HEXDUMP=y -CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index 89a5bcdfac8..25213af37c5 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -48,7 +48,7 @@ CONFIG_SPL_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 CONFIG_SPL_DISPLAY_PRINT=y -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_AT91_MCK_BYPASS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index a07044578a8..5502858fead 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -48,7 +48,7 @@ CONFIG_SPL_MAX_SIZE=0x10000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 CONFIG_SPL_DISPLAY_PRINT=y -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig index 6b9fa27de63..98b931c375d 100644 --- a/configs/sama5d2_icp_mmc_defconfig +++ b/configs/sama5d2_icp_mmc_defconfig @@ -49,7 +49,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 CONFIG_SPL_DISPLAY_PRINT=y -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_AT91_MCK_BYPASS=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 484f9e1bf8d..a50fbce8d06 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -40,6 +40,7 @@ CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_LOG=y CONFIG_LOG_MAX_LEVEL=9 CONFIG_LOG_DEFAULT_LEVEL=6 +CONFIG_LOGF_FUNC=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_STACKPROTECTOR=y CONFIG_CMD_CPU=y diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig index f37230151a0..eb0f064ad28 100644 --- a/configs/sandbox_noinst_defconfig +++ b/configs/sandbox_noinst_defconfig @@ -43,6 +43,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xa000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x4000000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x0 CONFIG_SPL_ENV_SUPPORT=y @@ -285,3 +286,4 @@ CONFIG_UNIT_TEST=y CONFIG_SPL_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y +CONFIG_SPL_LMB=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index f7b92dc8445..bc6a430fa35 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -1,4 +1,4 @@ -CONFIG_TEXT_BASE=0x200000 +CONFIG_TEXT_BASE=0x400000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -253,3 +253,4 @@ CONFIG_UNIT_TEST=y CONFIG_SPL_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y +CONFIG_SPL_LMB=y diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig index 06e9b2ae2fa..bc4ff0909c8 100644 --- a/configs/sniper_defconfig +++ b/configs/sniper_defconfig @@ -12,7 +12,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2 # CONFIG_SPL_FS_EXT4 is not set diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index b8d9c849bcd..a023e454947 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -42,7 +42,7 @@ CONFIG_SPL_PAD_TO=0x10000 CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE is not set CONFIG_SPL_MTD=y diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index caaabf39ef3..9aa3560c7e3 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -103,6 +103,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_ERRNO_STR=y -# CONFIG_LMB_USE_MAX_REGIONS is not set -CONFIG_LMB_MEMORY_REGIONS=2 -CONFIG_LMB_RESERVED_REGIONS=16 diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 2e22bf86000..806935f3892 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -190,6 +190,3 @@ CONFIG_WDT=y CONFIG_WDT_STM32MP=y # CONFIG_BINMAN_FDT is not set CONFIG_ERRNO_STR=y -# CONFIG_LMB_USE_MAX_REGIONS is not set -CONFIG_LMB_MEMORY_REGIONS=2 -CONFIG_LMB_RESERVED_REGIONS=16 diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index ffe7512650e..5f050ee0d05 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -166,6 +166,3 @@ CONFIG_WDT=y CONFIG_WDT_STM32MP=y # CONFIG_BINMAN_FDT is not set CONFIG_ERRNO_STR=y -# CONFIG_LMB_USE_MAX_REGIONS is not set -CONFIG_LMB_MEMORY_REGIONS=2 -CONFIG_LMB_RESERVED_REGIONS=16 diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 74deaaba2e4..3c591d74af3 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -166,6 +166,3 @@ CONFIG_WDT=y CONFIG_WDT_STM32MP=y # CONFIG_BINMAN_FDT is not set CONFIG_ERRNO_STR=y -# CONFIG_LMB_USE_MAX_REGIONS is not set -CONFIG_LMB_MEMORY_REGIONS=2 -CONFIG_LMB_RESERVED_REGIONS=16 diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig index 87038cc773a..f5623a19bb2 100644 --- a/configs/stm32mp25_defconfig +++ b/configs/stm32mp25_defconfig @@ -49,6 +49,3 @@ CONFIG_WDT_STM32MP=y CONFIG_WDT_ARM_SMC=y CONFIG_ERRNO_STR=y # CONFIG_EFI_LOADER is not set -# CONFIG_LMB_USE_MAX_REGIONS is not set -CONFIG_LMB_MEMORY_REGIONS=2 -CONFIG_LMB_RESERVED_REGIONS=32 diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig index 49ff92f6de3..db80e33870b 100644 --- a/configs/th1520_lpi4a_defconfig +++ b/configs/th1520_lpi4a_defconfig @@ -79,4 +79,3 @@ CONFIG_BZIP2=y CONFIG_ZSTD=y CONFIG_LIB_RATIONAL=y # CONFIG_EFI_LOADER is not set -# CONFIG_LMB_USE_MAX_REGIONS is not set diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig index 25f5f5e7ee5..c5652e9541c 100644 --- a/configs/verdin-am62_a53_defconfig +++ b/configs/verdin-am62_a53_defconfig @@ -51,6 +51,7 @@ CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig index e39ee2ac6fe..bd9ecd94922 100644 --- a/configs/verdin-am62_r5_defconfig +++ b/configs/verdin-am62_r5_defconfig @@ -41,6 +41,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index ef7f3b1bc10..a7e969d3cfc 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -29,6 +29,7 @@ CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=1 CONFIG_OF_SYSTEM_SETUP=y @@ -47,6 +48,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index fca91f7b1ee..15cfe2c48ac 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -38,6 +38,7 @@ CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=1 CONFIG_OF_SYSTEM_SETUP=y @@ -60,6 +61,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y diff --git a/disk/part_efi.c b/disk/part_efi.c index b1a03bd165e..580821a6ee9 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -15,7 +15,7 @@ #include <blk.h> #include <log.h> #include <part.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <asm/cache.h> #include <asm/global_data.h> #include <asm/unaligned.h> diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst index 5f8db126657..49675517246 100644 --- a/doc/arch/sandbox/sandbox.rst +++ b/doc/arch/sandbox/sandbox.rst @@ -662,7 +662,8 @@ Addr Config Usage b000 CONFIG_BLOBLIST_ADDR Blob list 10000 CFG_MALLOC_F_ADDR Early memory allocation f0000 CONFIG_PRE_CON_BUF_ADDR Pre-console buffer - 100000 CONFIG_TRACE_EARLY_ADDR Early trace buffer (if enabled). Also used + 100000 TCG Event log TCG Event Log + 200000 CONFIG_TRACE_EARLY_ADDR Early trace buffer (if enabled). Also used as the SPL load buffer in spl_test_load(). - 200000 CONFIG_TEXT_BASE Load buffer for U-Boot (sandbox_spl only) + 400000 CONFIG_TEXT_BASE Load buffer for U-Boot (sandbox_spl only) ======= ======================== =============================== diff --git a/doc/board/aspeed/ibex-ast2700.rst b/doc/board/aspeed/ibex-ast2700.rst new file mode 100644 index 00000000000..511bd081ba2 --- /dev/null +++ b/doc/board/aspeed/ibex-ast2700.rst @@ -0,0 +1,26 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +IBex AST2700 +============ + +AST2700 integrates an IBex RISC-V 32-bits CPU as the boot MCU to execute the +first stage bootlaoder, namely SPL. + +Build +----- + +1. Prepare the toolchains and make sure the $PATH to toolchains is correct. +2. Use `make ibex-ast2700_defconfig` in u-boot root to build the image + +Running U-Boot SPL +------------------ + +The U-Boot SPL will boot in M mode and load the FIT image which includes +the 2nd stage bootloaders executed by the main processor Cortex-A35. + + +Burn U-Boot to SPI Flash +------------------------ + +Use SPI flash programmer (e.g. SF100) to program the u-book-spl.bin with the +offset 0x80 bytes to the SPI flash beginning. diff --git a/doc/board/aspeed/index.rst b/doc/board/aspeed/index.rst new file mode 100644 index 00000000000..d784c88494f --- /dev/null +++ b/doc/board/aspeed/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Aspeed +====== + +.. toctree:: + :maxdepth: 2 + + ibex-ast2700 diff --git a/doc/board/atmel/at91ek.rst b/doc/board/atmel/at91ek.rst index 6185b1dfb28..a500b2f8950 100644 --- a/doc/board/atmel/at91ek.rst +++ b/doc/board/atmel/at91ek.rst @@ -6,8 +6,8 @@ AT91 Evaluation kits Board mapping & boot media -------------------------- -AT91SAM9260EK, AT91SAM9G20EK & AT91SAM9XEEK -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +AT91SAM9260EK & AT91SAM9G20EK +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Memory map:: diff --git a/doc/board/index.rst b/doc/board/index.rst index 417c128c7af..3fb7c84f10c 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -14,6 +14,7 @@ Board-specific doc anbernic/index apple/index armltd/index + aspeed/index asus/index atmel/index beacon/index diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst index 4955274a39b..8c7969987a9 100644 --- a/doc/board/qualcomm/index.rst +++ b/doc/board/qualcomm/index.rst @@ -7,5 +7,6 @@ Qualcomm :maxdepth: 2 dragonboard410c + rb3gen2 board debugging diff --git a/doc/board/qualcomm/rb3gen2.rst b/doc/board/qualcomm/rb3gen2.rst new file mode 100644 index 00000000000..4240606224f --- /dev/null +++ b/doc/board/qualcomm/rb3gen2.rst @@ -0,0 +1,53 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Caleb Connolly <caleb.connolly@linaro.org> + +Qualcomm Robotics RB3 Gen 2 +=========================== + +The RB3 Gen 2 is a development board based on the Qualcomm QCM6490 SoC (a derivative +of SC7280). More information can be found on `Qualcomm's product page`_. + +U-Boot can be used as a replacement for Qualcomm's original EDK2 bootloader by +flashing it directly to the uefi_a (or _b) partition. + +.. _Qualcomm's product page: https://www.qualcomm.com/developer/hardware/rb3-gen-2-development-kit + +Installation +------------ +First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``qcm6490``:: + + $ export CROSS_COMPILE=<aarch64 toolchain prefix> + $ make qcm6490_defconfig + $ make -j8 + +This will build ``u-boot.elf`` in the configured output directory. + +Although the RB3 Gen 2 does not have secure boot set up by default, +the firmware still expects firmware ELF images to be "signed". The signature +does not provide any security in this case, but it provides the firmware with +some required metadata. + +To "sign" ``u-boot.elf`` you can use e.g. `qtestsign`_:: + + $ qtestsign -v6 aboot -o u-boot.mbn u-boot.elf + +Then install the resulting ``u-boot.mbn`` to the ``uefi_a`` partition +on your device with ``fastboot flash uefi_a u-boot.mbn``. + +U-Boot should be running after a reboot (``fastboot reboot``). + +Note that fastboot is not yet supported in U-Boot on this board, as a result, +to flash back the original firmware, or new versoins of the U-Boot, EDL mode +must be used. This can be accessed by pressing the EDL mode button as described +in the Qualcomm Linux documentation. A tool like bkerler's `edl`_ can be used +for flashing with the firehose loader binary appropriate for the board. + +.. _qtestsign: https://github.com/msm8916-mainline/qtestsign +.. _edl: https://github.com/bkerler/edl + +Usage +----- + +The USB Type-A ports are connected via a PCIe USB hub, which is not supported yet. +However, the Type-C port can be used with a powered USB dock to connect peripherals +like a USB stick. diff --git a/doc/develop/commands.rst b/doc/develop/commands.rst index 6427844f143..77a7a4d9c02 100644 --- a/doc/develop/commands.rst +++ b/doc/develop/commands.rst @@ -197,7 +197,6 @@ Here is an example: ctx.current = buf; ut_assertok(acpi_fill_ssdt(&ctx)); - console_record_reset(); run_command("acpi items", 0); ut_assert_nextline("dev 'acpi-test', type 1, size 2"); ut_assert_nextline("dev 'acpi-test2', type 1, size 2"); @@ -205,13 +204,11 @@ Here is an example: ctx.current = buf; ut_assertok(acpi_inject_dsdt(&ctx)); - console_record_reset(); run_command("acpi items", 0); ut_assert_nextline("dev 'acpi-test', type 2, size 2"); ut_assert_nextline("dev 'acpi-test2', type 2, size 2"); ut_assert_console_end(); - console_record_reset(); run_command("acpi items -d", 0); ut_assert_nextline("dev 'acpi-test', type 2, size 2"); ut_assert_nextlines_are_dump(2); @@ -223,4 +220,8 @@ Here is an example: return 0; } - DM_TEST(dm_test_acpi_cmd_items, UTF_SCAN_PDATA | UTF_SCAN_FDT); + DM_TEST(dm_test_acpi_cmd_items, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE); + +Note that it is not necessary to call console_record_reset() unless you are +trying to drop some unchecked output. Consider using ut_check_skip_to_line() +instead. diff --git a/doc/develop/global_data.rst b/doc/develop/global_data.rst index d143f27eedd..2863154ea42 100644 --- a/doc/develop/global_data.rst +++ b/doc/develop/global_data.rst @@ -51,6 +51,31 @@ U-Boot. The value of gd has to be saved every time U-Boot is left and restored whenever U-Boot is reentered. This is also relevant for the implementation of function tracing. For setting the value of gd function set_gd() can be used. +Guidelines +---------- + +The global_data structure is placed in some memory which is available very early +after boot to allow for a minimum set of global variables during system +initialisation (until the memory controller is set up and RAM can be used). It +is the primary data structure passed from pre-relocation U-Boot to +post-relocation, i.e. ``from board_init_f()`` ``to board_init_r()``. + +The global_data struct exists for the lifetime of U-Boot. Since the struct is +used by all architectures, fields added should be useful for most architectures. +Fields which are only needed on one or two architectures can be placed in the +architecture-specific ``struct arch_global_data``. + +In any case the struct should be kept small, since it uses precious SRAM on +many boards. + +SPL also uses global data, as well as U-Boot proper, so take care to avoid +adding fields to SPL which are not actually used by SPL. You can create +access functions or macros in the header file to avoid filling the C code with +#ifdefs. + +A flags word is available, which provides a convenient means to track the state +of various initialisation phases within U-Boot. + Global data structure --------------------- diff --git a/doc/README.generic-board b/doc/develop/historical/generic_board.rst index bc35179fbfd..12550a140e0 100644 --- a/doc/README.generic-board +++ b/doc/develop/historical/generic_board.rst @@ -1,10 +1,9 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2014 Google, Inc -# Simon Glass <sjg@chromium.org> +.. SPDX-License-Identifier: GPL-2.0+ +.. (C) Copyright 2014 Google, Inc +.. sectionauthor:: Simon Glass <sjg@chromium.org> -Background ----------- +Generic board +------------- U-Boot traditionally had a board.c file for each architecture. This introduced quite a lot of duplication, with each architecture tending to do @@ -16,7 +15,7 @@ All boards and architectures have moved to this as of mid 2016. What has changed? ------------------ +~~~~~~~~~~~~~~~~~ The main change is that the arch/<arch>/lib/board.c file is removed in favour of common/board_f.c (for pre-relocation init) and common/board_r.c @@ -28,7 +27,7 @@ have been moved to separate structures. Further Background ------------------- +~~~~~~~~~~~~~~~~~~ The full text of the original generic board series is reproduced below. @@ -132,4 +131,6 @@ convenience. Simon Glass, sjg@chromium.org March 2014 + Updated after final removal, May 2016 + diff --git a/doc/develop/historical/index.rst b/doc/develop/historical/index.rst new file mode 100644 index 00000000000..e4462f5d2a7 --- /dev/null +++ b/doc/develop/historical/index.rst @@ -0,0 +1,12 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Historical Documents +==================== + +This section provides documentation about major changes in U-Boot over the +years. + +.. toctree:: + :maxdepth: 1 + + generic_board diff --git a/doc/develop/index.rst b/doc/develop/index.rst index c0107a783fc..0d0e60ab56c 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -99,3 +99,11 @@ Code quality :maxdepth: 1 python_cq + +Historical documentation +------------------------ + +.. toctree:: + :maxdepth: 2 + + historical/index diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 72863756a42..de1d3045b44 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -73,7 +73,7 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2024.10-rc3 was released on Mon 19 August 2024. -.. * U-Boot v2024.10-rc4 was released on Mon 02 September 2024. +* U-Boot v2024.10-rc4 was released on Mon 02 September 2024. .. * U-Boot v2024.10-rc5 was released on Mon 16 September 2024. diff --git a/doc/develop/tests_writing.rst b/doc/develop/tests_writing.rst index 404d158ec40..a328ebfef33 100644 --- a/doc/develop/tests_writing.rst +++ b/doc/develop/tests_writing.rst @@ -151,7 +151,6 @@ There is no exactly equivalent C test, but here is a similar one that tests 'ms' buf[0x31] = 0x12; buf[0xff] = 0x12; buf[0x100] = 0x12; - ut_assertok(console_record_reset_enable()); run_command("ms.b 1 ff 12", 0); ut_assert_nextline("00000030: 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................"); ut_assert_nextline("--"); diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index d450b12bf80..94482758573 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -449,6 +449,33 @@ practice. Getting this information from the firmware itself is more secure, assuming the firmware has been verified by a previous stage boot loader. +Dynamic Firmware Update GUIDs +***************************** + +The image_type_id contains a GUID value which is specific to the image +and board being updated, that is to say it should uniquely identify the +board model (and revision if relevant) and image pair. Traditionally, +these GUIDs are generated manually and hardcoded on a per-board basis, +however this scheme makes it difficult to scale up to support many +boards. + +To address this, v5 GUIDs can be used to generate board-specific GUIDs +at runtime, based on the board's devicetree root compatible +(e.g. "qcom,qrb5165-rb5"). + +These strings are combined with the fw_image name to generate GUIDs for +each image. Support for dynamic UUIDs can be enabled by generating a new +namespace UUID and setting EFI_CAPSULE_NAMESPACE_GUID to it. Dynamic GUID +generation is only enabled if the image_type_id property is unset for your +firmware images, this is to avoid breaking existing boards with hardcoded +GUIDs. + +The mkeficapsule tool can be used to determine the GUIDs for a particular +board and image. It can be found in the tools directory. + +Firmware update images +********************** + The firmware images structure defines the GUID values, image index values and the name of the images that are to be updated through the capsule update feature. These values are to be defined as part of diff --git a/doc/mkeficapsule.1 b/doc/mkeficapsule.1 index c3d0f21488a..a5545f7898a 100644 --- a/doc/mkeficapsule.1 +++ b/doc/mkeficapsule.1 @@ -10,6 +10,9 @@ mkeficapsule \- Generate EFI capsule file for U-Boot .B mkeficapsule .RI [ options ] " " [ image-blob ] " " capsule-file +.B mkeficapsule +.RI guidgen " " [ GUID ] " " DTB " " IMAGE_NAME... + .SH "DESCRIPTION" The .B mkeficapsule @@ -42,6 +45,10 @@ multiple binary blobs in a single capsule file. This type of image file can be generated by .BR mkimage . +mkeficapsule can also be used to simulate the dynamic GUID generation used to +identify firmware images in capsule updates by providing the namespace guid, dtb +for the board, and a list of firmware images. + .SH "OPTIONS" .TP @@ -117,6 +124,22 @@ at every firmware update. .B "-d\fR,\fB --dump_sig" Dump signature data into *.p7 file +.SH "GUIDGEN OPTIONS" + +.TP +.B "[GUID]" +The namespace/salt GUID, by default this is EFI_CAPSULE_NAMESPACE_GUID. +The format is: + xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx + +.TP +.B DTB +The device tree blob file for the board. + +.TP +.B IMAGE_NAME... +The names of the firmware images to generate GUIDs for. + .PP .SH FILES .TP diff --git a/doc/usage/cmd/bind.rst b/doc/usage/cmd/bind.rst index 23457783666..67a0405bab5 100644 --- a/doc/usage/cmd/bind.rst +++ b/doc/usage/cmd/bind.rst @@ -12,7 +12,7 @@ Synopsis :: bind <node path> <driver> - bind <class> <index> <driver> + bind <class> <seq> <driver> Description ----------- @@ -30,8 +30,8 @@ node path class device class name -index - index of the parent device in the device class +seq + sequence number of the parent device in the device class driver device driver name @@ -46,7 +46,7 @@ using the two alternative bind syntaxes. .. code-block:: => dm tree - Class Index Probed Driver Name + Class Seq Probed Driver Name ----------------------------------------------------------- root 0 [ + ] root_driver root_driver ... @@ -75,13 +75,13 @@ using the two alternative bind syntaxes. => date Cannot find RTC: err=-19 => dm tree - Class Index Probed Driver Name + Class Seq Probed Driver Name ----------------------------------------------------------- root 0 [ + ] root_driver root_driver ... => bind /pl031@9010000 rtc-pl031 => dm tree - Class Index Probed Driver Name + Class Seq Probed Driver Name ----------------------------------------------------------- root 0 [ + ] root_driver root_driver ... diff --git a/doc/usage/cmd/dm.rst b/doc/usage/cmd/dm.rst index 7651507937a..196b22d1376 100644 --- a/doc/usage/cmd/dm.rst +++ b/doc/usage/cmd/dm.rst @@ -112,9 +112,8 @@ This shows the full tree of devices including the following fields: uclass Shows the name of the uclass for the device -Index - Shows the index number of the device, within the uclass. This shows the - ordering within the uclass, but not the sequence number. +Seq + Shows the sequence number of the device, within the uclass. Probed Shows `+` if the device is active @@ -366,7 +365,7 @@ dm tree This example shows the abridged sandbox output:: => dm tree - Class Index Probed Driver Name + Class Seq Probed Driver Name ----------------------------------------------------------- root 0 [ + ] root_driver root_driver demo 0 [ ] demo_shape_drv |-- demo_shape_drv diff --git a/doc/usage/cmd/pwm.rst b/doc/usage/cmd/pwm.rst new file mode 100644 index 00000000000..522acb5afa3 --- /dev/null +++ b/doc/usage/cmd/pwm.rst @@ -0,0 +1,91 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +.. index:: + single: pwm (command) + +pwm command +=========== + +Synopsis +-------- + +:: + + pwm invert <pwm_dev_num> <channel> <polarity> + pwm config <pwm_dev_num> <channel> <period_ns> <duty_ns> + pwm enable <pwm_dev_num> <channel> + pwm disable <pwm_dev_num> <channel> + + +Description +----------- + +The ``pwm`` command is used to access and configure PWM (Pulse Width Modulation) +signals. + +pwm invert +---------- + +* If the value of ``polarity`` is 0, the default polarity is used. +* If the value of ``polarity`` is 1, the polarity is inverted. + +pwm config +---------- + +Configure the period and duty period in nanoseconds. + +pwm enable +---------- + +Enable output on the configured device and channel. + +pwm disable +----------- + +Disable output on the configured device and channel. + +pwm_dev_num + Device number of the pulse width modulation device + +channel + Output channel of the PWM device + +polarity + * 0 - Use normal polarity + * 1 - Use inverted polarity + +duty_ns + Duty period in ns + +period_ns + Period time in ns + +Examples +-------- + +Configure device 0, channel 0 to 20 µs period and 14 µs (that is, 70%) duty period:: + + => pwm config 0 0 20000 14000 + +Enable output on the configured device and channel:: + + => pwm enable 0 0 + +Disable output on the configured device and channel:: + + => pwm disable 0 0 + +Invert the signal on the configured device and channel:: + + => pwm invert 0 0 1 + +Configuration +------------- + +The ``pwm`` command is only available if CONFIG_CMD_PWM=y. + +Return value +------------ + +If the command succeeds, the return value ``$?`` is set to 0. If an error occurs, the +return value ``$?`` is set to 1. diff --git a/doc/usage/cmd/unbind.rst b/doc/usage/cmd/unbind.rst index 0309e90f6ea..1ae9c1b172c 100644 --- a/doc/usage/cmd/unbind.rst +++ b/doc/usage/cmd/unbind.rst @@ -12,8 +12,8 @@ Synopsis :: unbind <node path> - unbind <class> <index> - unbind <class> <index> <driver> + unbind <class> <seq> + unbind <class> <seq> <driver> Description ----------- @@ -27,8 +27,8 @@ node path class device class name -index - index of the device in the device class +seq + sequence number of the device in the device class driver device driver name @@ -43,7 +43,7 @@ using the three alternative unbind syntaxes. .. code-block:: => dm tree - Class Index Probed Driver Name + Class Seq Probed Driver Name ----------------------------------------------------------- root 0 [ + ] root_driver root_driver ... @@ -70,7 +70,7 @@ using the three alternative unbind syntaxes. } => unbind /pl031@9010000 => dm tree - Class Index Probed Driver Name + Class Seq Probed Driver Name ----------------------------------------------------------- root 0 [ + ] root_driver root_driver ... @@ -78,7 +78,7 @@ using the three alternative unbind syntaxes. Cannot find a device with path /pl031@9010000 => bind /pl031@9010000 rtc-pl031 => dm tree - Class Index Probed Driver Name + Class Seq Probed Driver Name ----------------------------------------------------------- root 0 [ + ] root_driver root_driver ... diff --git a/doc/usage/index.rst b/doc/usage/index.rst index b058c2254fb..70563374899 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -94,6 +94,7 @@ Shell commands cmd/pinmux cmd/printenv cmd/pstore + cmd/pwm cmd/qfw cmd/read cmd/reset diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index a29d641343e..203f98edffc 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -6,6 +6,7 @@ #include <ahci.h> #include <blk.h> +#include <bootdev.h> #include <cpu_func.h> #include <dm.h> #include <dwc_ahsata.h> @@ -897,7 +898,11 @@ int dwc_ahsata_scan(struct udevice *dev) ret = blk_probe_or_unbind(dev); if (ret < 0) /* TODO: undo create */ - return ret; + return log_msg_ret("pro", ret); + + ret = bootdev_setup_for_sibling_blk(blk, "sata_bootdev"); + if (ret) + return log_msg_ret("bd", ret); return 0; } diff --git a/drivers/ata/sata.c b/drivers/ata/sata.c index 84437d3d346..89cd516f3d6 100644 --- a/drivers/ata/sata.c +++ b/drivers/ata/sata.c @@ -9,9 +9,12 @@ * Dave Liu <daveliu@freescale.com> */ +#define LOG_CATEGORY UCLASS_AHCI + #include <ahci.h> #include <blk.h> #include <dm.h> +#include <log.h> #include <part.h> #include <sata.h> #include <dm/device-internal.h> @@ -49,38 +52,39 @@ int sata_scan(struct udevice *dev) int sata_rescan(bool verbose) { + struct uclass *uc; + struct udevice *dev; /* SATA controller */ int ret; - struct udevice *dev; if (verbose) - printf("Removing devices on SATA bus...\n"); - - blk_unbind_all(UCLASS_AHCI); - - ret = uclass_find_first_device(UCLASS_AHCI, &dev); - if (ret || !dev) { - printf("Cannot find SATA device (err=%d)\n", ret); - return -ENOENT; - } - - ret = device_remove(dev, DM_REMOVE_NORMAL); - if (ret) { - printf("Cannot remove SATA device '%s' (err=%d)\n", dev->name, ret); - return -ENOSYS; + printf("scanning bus for devices...\n"); + + ret = uclass_get(UCLASS_AHCI, &uc); + if (ret) + return ret; + + /* Remove all children of SATA devices (blk and bootdev) */ + uclass_foreach_dev(dev, uc) { + log_debug("unbind %s\n", dev->name); + ret = device_chld_remove(dev, NULL, DM_REMOVE_NORMAL); + if (!ret) + ret = device_chld_unbind(dev, NULL); + if (ret && verbose) { + log_err("Unbinding from %s failed (%dE)\n", + dev->name, ret); + } } if (verbose) printf("Rescanning SATA bus for devices...\n"); - ret = uclass_probe_all(UCLASS_AHCI); - - if (ret == -ENODEV) { - if (verbose) - printf("No SATA block device found\n"); - return 0; + uclass_foreach_dev_probe(UCLASS_AHCI, dev) { + ret = sata_scan(dev); + if (ret && verbose) + log_err("Scanning %s failed (%dE)\n", dev->name, ret); } - return ret; + return 0; } static unsigned long sata_bread(struct udevice *dev, lbaint_t start, diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 2105cea3d45..b6ab31a314a 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -13,7 +13,6 @@ if BOOTCOUNT_LIMIT choice prompt "Boot count device" default BOOTCOUNT_AM33XX if AM33XX || SOC_DA8XX - default BOOTCOUNT_AT91 if AT91SAM9XE default BOOTCOUNT_GENERIC config BOOTCOUNT_GENERIC diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 9acbc47fe8e..d9d518d7038 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -257,6 +257,7 @@ source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/renesas/Kconfig" +source "drivers/clk/sophgo/Kconfig" source "drivers/clk/sunxi/Kconfig" source "drivers/clk/sifive/Kconfig" source "drivers/clk/starfive/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 847b9b29110..f9b90a38b00 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_CLK_QCOM) += qcom/ obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o obj-$(CONFIG_CLK_SIFIVE) += sifive/ +obj-$(CONFIG_CLK_SOPHGO) += sophgo/ obj-$(CONFIG_CLK_SUNXI) += sunxi/ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c index a29ad0d7a68..a43fff2e7ed 100644 --- a/drivers/clk/mpc83xx_clk.c +++ b/drivers/clk/mpc83xx_clk.c @@ -358,7 +358,7 @@ static int mpc83xx_clk_probe(struct udevice *dev) gd->mem_clk = priv->speed[MPC83XX_CLK_MEM]; if (mpc83xx_has_pci(type)) - gd->pci_clk = priv->speed[MPC83XX_CLK_PCI]; + gd->arch.pci_clk = priv->speed[MPC83XX_CLK_PCI]; gd->cpu_clk = priv->speed[MPC83XX_CLK_CORE]; gd->bus_clk = priv->speed[MPC83XX_CLK_CSB]; diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 45d63c6d6db..0d2c0ac225c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -86,6 +86,14 @@ config CLK_QCOM_SM8650 on the Snapdragon SM8650 SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_SC7280 + bool "Qualcomm SC7280 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon SC7280 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + endmenu endif diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index dec20e4b594..e223c131ee4 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o +obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o obj-$(CONFIG_CLK_QCOM_SM8250) += clock-sm8250.o obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index f6445c8f566..7aa6ca59aad 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -11,6 +11,7 @@ #define CFG_CLK_SRC_GPLL0 (1 << 8) #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8) #define CFG_CLK_SRC_GPLL9 (2 << 8) +#define CFG_CLK_SRC_GPLL0_ODD (3 << 8) #define CFG_CLK_SRC_GPLL6 (4 << 8) #define CFG_CLK_SRC_GPLL7 (3 << 8) #define CFG_CLK_SRC_GPLL4 (5 << 8) diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c new file mode 100644 index 00000000000..5d343f12051 --- /dev/null +++ b/drivers/clk/qcom/clock-sc7280.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock drivers for Qualcomm sc7280 + * + * (C) Copyright 2024 Linaro Ltd. + */ + +#include <linux/types.h> +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,gcc-sc7280.h> + +#include "clock-qcom.h" + +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038 +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020 + +static ulong sc7280_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id < priv->data->num_clks) + debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate); + + switch (clk->id) { + case GCC_USB30_PRIM_MOCK_UTMI_CLK: + WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate); + clk_rcg_set_rate(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO); + return rate; + case GCC_USB30_PRIM_MASTER_CLK: + WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate); + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, + 1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8); + clk_rcg_set_rate(priv->base, 0xf064, 0, 0); + return rate; + default: + return 0; + } +} + +static const struct gate_clk sc7280_clks[] = { + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0xf07c, 1), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0xf010, 1), + GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0xf080, 1), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0xf018, 1), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1), + GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1), +}; + +static int sc7280_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %ld: %s\n", __func__, clk->id, sc7280_clks[clk->id].name); + + switch (clk->id) { + case GCC_AGGRE_USB3_PRIM_AXI_CLK: + qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK); + fallthrough; + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + break; + } + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map sc7280_gcc_resets[] = { + [GCC_PCIE_0_BCR] = { 0x6b000 }, + [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, + [GCC_PCIE_1_BCR] = { 0x8d000 }, + [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, + [GCC_SDCC1_BCR] = { 0x75000 }, + [GCC_SDCC2_BCR] = { 0x14000 }, + [GCC_SDCC4_BCR] = { 0x16000 }, + [GCC_UFS_PHY_BCR] = { 0x77000 }, + [GCC_USB30_PRIM_BCR] = { 0xf000 }, + [GCC_USB30_SEC_BCR] = { 0x9e000 }, + [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, + [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, + [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, +}; + +static const struct qcom_power_map sc7280_gdscs[] = { + [GCC_UFS_PHY_GDSC] = { 0x77004 }, + [GCC_USB30_PRIM_GDSC] = { 0xf004 }, +}; + +static struct msm_clk_data qcs404_gcc_data = { + .resets = sc7280_gcc_resets, + .num_resets = ARRAY_SIZE(sc7280_gcc_resets), + .clks = sc7280_clks, + .num_clks = ARRAY_SIZE(sc7280_clks), + + .power_domains = sc7280_gdscs, + .num_power_domains = ARRAY_SIZE(sc7280_gdscs), + + .enable = sc7280_enable, + .set_rate = sc7280_set_rate, +}; + +static const struct udevice_id gcc_sc7280_of_match[] = { + { + .compatible = "qcom,gcc-sc7280", + .data = (ulong)&qcs404_gcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_sc7280) = { + .name = "gcc_sc7280", + .id = UCLASS_NOP, + .of_match = gcc_sc7280_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 24cefebd1b2..89924041299 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -8,6 +8,7 @@ #include <dm.h> #include <dt-structs.h> #include <errno.h> +#include <handoff.h> #include <log.h> #include <malloc.h> #include <mapmem.h> @@ -1467,7 +1468,7 @@ static int rk3399_clk_probe(struct udevice *dev) init_clocks = true; #elif CONFIG_IS_ENABLED(HANDOFF) if (!(gd->flags & GD_FLG_RELOC)) { - if (!(gd->spl_handoff)) + if (!handoff_get()) init_clocks = true; } #endif diff --git a/drivers/clk/sophgo/Kconfig b/drivers/clk/sophgo/Kconfig new file mode 100644 index 00000000000..59b51608fe6 --- /dev/null +++ b/drivers/clk/sophgo/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + +config CLK_SOPHGO + bool + +config CLK_SOPHGO_CV1800B + bool "Sophgo CV1800B clock support" + depends on CLK + select CLK_CCF + select CLK_SOPHGO + help + This enables support clock driver for Sophgo CV1800B SoC. diff --git a/drivers/clk/sophgo/Makefile b/drivers/clk/sophgo/Makefile new file mode 100644 index 00000000000..caec76222be --- /dev/null +++ b/drivers/clk/sophgo/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + +obj-y += clk-ip.o clk-pll.o +obj-$(CONFIG_CLK_SOPHGO_CV1800B) += clk-cv1800b.o diff --git a/drivers/clk/sophgo/clk-common.h b/drivers/clk/sophgo/clk-common.h new file mode 100644 index 00000000000..95b82e968d0 --- /dev/null +++ b/drivers/clk/sophgo/clk-common.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + * + */ + +#ifndef __CLK_SOPHGO_COMMON_H__ +#define __CLK_SOPHGO_COMMON_H__ + +#include <linux/bitops.h> +#include <linux/io.h> + +#define CV1800B_CLK_OSC 1 +#define CV1800B_CLK_BYPASS 2 +#define CV1800B_CLK_ID_TRANSFORM(_id) ((_id) + 3) + +struct cv1800b_clk_regbit { + u32 offset; + u8 shift; +}; + +struct cv1800b_clk_regfield { + u32 offset; + u8 shift; + u8 width; +}; + +#define CV1800B_CLK_REGBIT(_offset, _shift) \ + { \ + .offset = _offset, \ + .shift = _shift, \ + } + +#define CV1800B_CLK_REGFIELD(_offset, _shift, _width) \ + { \ + .offset = _offset, \ + .shift = _shift, \ + .width = _width, \ + } + +static inline u32 cv1800b_clk_getbit(void *base, struct cv1800b_clk_regbit *bit) +{ + return readl(base + bit->offset) & (BIT(bit->shift)); +} + +static inline u32 cv1800b_clk_setbit(void *base, struct cv1800b_clk_regbit *bit) +{ + return setbits_le32(base + bit->offset, BIT(bit->shift)); +} + +static inline u32 cv1800b_clk_clrbit(void *base, struct cv1800b_clk_regbit *bit) +{ + return clrbits_le32(base + bit->offset, BIT(bit->shift)); +} + +static inline u32 cv1800b_clk_getfield(void *base, + struct cv1800b_clk_regfield *field) +{ + u32 mask = GENMASK(field->shift + field->width - 1, field->shift); + + return (readl(base + field->offset) & mask) >> field->shift; +} + +static inline void +cv1800b_clk_setfield(void *base, struct cv1800b_clk_regfield *field, u32 val) +{ + u32 mask = GENMASK(field->shift + field->width - 1, field->shift); + u32 new_val = (readl(base + field->offset) & ~mask) | + ((val << field->shift) & mask); + + return writel(new_val, base + field->offset); +} + +#endif /* __CLK_SOPHGO_COMMON_H__ */ diff --git a/drivers/clk/sophgo/clk-cv1800b.c b/drivers/clk/sophgo/clk-cv1800b.c new file mode 100644 index 00000000000..d946ea57a46 --- /dev/null +++ b/drivers/clk/sophgo/clk-cv1800b.c @@ -0,0 +1,754 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <linux/clk-provider.h> + +#include "clk-common.h" +#include "clk-cv1800b.h" +#include "clk-ip.h" +#include "clk-pll.h" + +static const char *const clk_cam_parents[] = { + "clk_cam0pll", + "clk_cam0pll_d2", + "clk_cam0pll_d3", + "clk_mipimpll_d3" +}; + +static const char *const clk_tpu_parents[] = { + "clk_tpll", + "clk_a0pll", + "clk_mipimpll", + "clk_fpll" +}; + +static const char *const clk_axi4_parents[] = { "clk_fpll", "clk_disppll" }; +static const char *const clk_aud_parents[] = { "clk_a0pll", "clk_a24m" }; +static const char *const clk_cam0_200_parents[] = { "osc", "clk_disppll" }; + +static const char *const clk_vip_sys_parents[] = { + "clk_mipimpll", + "clk_cam0pll", + "clk_disppll", + "clk_fpll" +}; + +static const char *const clk_axi_video_codec_parents[] = { + "clk_a0pll", + "clk_mipimpll", + "clk_cam1pll", + "clk_fpll" +}; + +static const char *const clk_vc_src0_parents[] = { + "clk_disppll", + "clk_mipimpll", + "clk_cam1pll", + "clk_fpll" +}; + +static const struct cv1800b_mmux_parent_info clk_c906_0_parents[] = { + { "clk_tpll", 0, 0 }, + { "clk_a0pll", 0, 1 }, + { "clk_mipimpll", 0, 2 }, + { "clk_mpll", 0, 3 }, + { "clk_fpll", 1, 0 }, +}; + +static const struct cv1800b_mmux_parent_info clk_c906_1_parents[] = { + { "clk_tpll", 0, 0 }, + { "clk_a0pll", 0, 1 }, + { "clk_disppll", 0, 2 }, + { "clk_mpll", 0, 3 }, + { "clk_fpll", 1, 0 }, +}; + +static const struct cv1800b_mmux_parent_info clk_a53_parents[] = { + { "clk_tpll", 0, 0 }, + { "clk_a0pll", 0, 1 }, + { "clk_mipimpll", 0, 2 }, + { "clk_mpll", 0, 3 }, + { "clk_fpll", 1, 0 }, +}; + +static struct cv1800b_clk_gate cv1800b_gate_info[] = { + CV1800B_GATE(CLK_XTAL_AP, "clk_xtal_ap", "osc", REG_CLK_EN_0, 3, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_RTC_25M, "clk_rtc_25m", "osc", REG_CLK_EN_0, 8, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_TEMPSEN, "clk_tempsen", "osc", REG_CLK_EN_0, 9, 0), + CV1800B_GATE(CLK_SARADC, "clk_saradc", "osc", REG_CLK_EN_0, 10, 0), + CV1800B_GATE(CLK_EFUSE, "clk_efuse", "osc", REG_CLK_EN_0, 11, 0), + CV1800B_GATE(CLK_APB_EFUSE, "clk_apb_efuse", "osc", REG_CLK_EN_0, 12, 0), + CV1800B_GATE(CLK_DEBUG, "clk_debug", "osc", REG_CLK_EN_0, 13, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_XTAL_MISC, "clk_xtal_misc", "osc", REG_CLK_EN_0, 14, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_APB_WDT, "clk_apb_wdt", "osc", REG_CLK_EN_1, 7, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_WGN, "clk_wgn", "osc", REG_CLK_EN_3, 22, 0), + CV1800B_GATE(CLK_WGN0, "clk_wgn0", "osc", REG_CLK_EN_3, 23, 0), + CV1800B_GATE(CLK_WGN1, "clk_wgn1", "osc", REG_CLK_EN_3, 24, 0), + CV1800B_GATE(CLK_WGN2, "clk_wgn2", "osc", REG_CLK_EN_3, 25, 0), + CV1800B_GATE(CLK_KEYSCAN, "clk_keyscan", "osc", REG_CLK_EN_3, 26, 0), + CV1800B_GATE(CLK_TPU_FAB, "clk_tpu_fab", "clk_mipimpll", REG_CLK_EN_0, 5, 0), + CV1800B_GATE(CLK_AHB_ROM, "clk_ahb_rom", "clk_axi4", REG_CLK_EN_0, 6, 0), + CV1800B_GATE(CLK_AXI4_EMMC, "clk_axi4_emmc", "clk_axi4", REG_CLK_EN_0, 15, 0), + CV1800B_GATE(CLK_AXI4_SD0, "clk_axi4_sd0", "clk_axi4", REG_CLK_EN_0, 18, 0), + CV1800B_GATE(CLK_AXI4_SD1, "clk_axi4_sd1", "clk_axi4", REG_CLK_EN_0, 21, 0), + CV1800B_GATE(CLK_AXI4_ETH0, "clk_axi4_eth0", "clk_axi4", REG_CLK_EN_0, 26, 0), + CV1800B_GATE(CLK_AXI4_ETH1, "clk_axi4_eth1", "clk_axi4", REG_CLK_EN_0, 28, 0), + CV1800B_GATE(CLK_AHB_SF, "clk_ahb_sf", "clk_axi4", REG_CLK_EN_1, 0, 0), + CV1800B_GATE(CLK_SDMA_AXI, "clk_sdma_axi", "clk_axi4", REG_CLK_EN_1, 1, 0), + CV1800B_GATE(CLK_APB_I2C, "clk_apb_i2c", "clk_axi4", REG_CLK_EN_1, 6, 0), + CV1800B_GATE(CLK_APB_SPI0, "clk_apb_spi0", "clk_axi4", REG_CLK_EN_1, 9, 0), + CV1800B_GATE(CLK_APB_SPI1, "clk_apb_spi1", "clk_axi4", REG_CLK_EN_1, 10, 0), + CV1800B_GATE(CLK_APB_SPI2, "clk_apb_spi2", "clk_axi4", REG_CLK_EN_1, 11, 0), + CV1800B_GATE(CLK_APB_SPI3, "clk_apb_spi3", "clk_axi4", REG_CLK_EN_1, 12, 0), + CV1800B_GATE(CLK_APB_UART0, "clk_apb_uart0", "clk_axi4", REG_CLK_EN_1, 15, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_APB_UART1, "clk_apb_uart1", "clk_axi4", REG_CLK_EN_1, 17, 0), + CV1800B_GATE(CLK_APB_UART2, "clk_apb_uart2", "clk_axi4", REG_CLK_EN_1, 19, 0), + CV1800B_GATE(CLK_APB_UART3, "clk_apb_uart3", "clk_axi4", REG_CLK_EN_1, 21, 0), + CV1800B_GATE(CLK_APB_UART4, "clk_apb_uart4", "clk_axi4", REG_CLK_EN_1, 23, 0), + CV1800B_GATE(CLK_APB_I2S0, "clk_apb_i2s0", "clk_axi4", REG_CLK_EN_1, 24, 0), + CV1800B_GATE(CLK_APB_I2S1, "clk_apb_i2s1", "clk_axi4", REG_CLK_EN_1, 25, 0), + CV1800B_GATE(CLK_APB_I2S2, "clk_apb_i2s2", "clk_axi4", REG_CLK_EN_1, 26, 0), + CV1800B_GATE(CLK_APB_I2S3, "clk_apb_i2s3", "clk_axi4", REG_CLK_EN_1, 27, 0), + CV1800B_GATE(CLK_AXI4_USB, "clk_axi4_usb", "clk_axi4", REG_CLK_EN_1, 28, 0), + CV1800B_GATE(CLK_APB_USB, "clk_apb_usb", "clk_axi4", REG_CLK_EN_1, 29, 0), + CV1800B_GATE(CLK_APB_I2C0, "clk_apb_i2c0", "clk_axi4", REG_CLK_EN_3, 17, 0), + CV1800B_GATE(CLK_APB_I2C1, "clk_apb_i2c1", "clk_axi4", REG_CLK_EN_3, 18, 0), + CV1800B_GATE(CLK_APB_I2C2, "clk_apb_i2c2", "clk_axi4", REG_CLK_EN_3, 19, 0), + CV1800B_GATE(CLK_APB_I2C3, "clk_apb_i2c3", "clk_axi4", REG_CLK_EN_3, 20, 0), + CV1800B_GATE(CLK_APB_I2C4, "clk_apb_i2c4", "clk_axi4", REG_CLK_EN_3, 21, 0), + CV1800B_GATE(CLK_AHB_SF1, "clk_ahb_sf1", "clk_axi4", REG_CLK_EN_3, 27, 0), + CV1800B_GATE(CLK_APB_AUDSRC, "clk_apb_audsrc", "clk_axi4", REG_CLK_EN_4, 2, 0), + CV1800B_GATE(CLK_DDR_AXI_REG, "clk_ddr_axi_reg", "clk_axi6", REG_CLK_EN_0, 7, + CLK_IS_CRITICAL), + CV1800B_GATE(CLK_APB_GPIO, "clk_apb_gpio", "clk_axi6", REG_CLK_EN_0, 29, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_APB_GPIO_INTR, "clk_apb_gpio_intr", "clk_axi6", REG_CLK_EN_0, 30, + CLK_IS_CRITICAL), + CV1800B_GATE(CLK_APB_JPEG, "clk_apb_jpeg", "clk_axi6", REG_CLK_EN_2, 13, CLK_IGNORE_UNUSED), + CV1800B_GATE(CLK_APB_H264C, "clk_apb_h264c", "clk_axi6", REG_CLK_EN_2, 14, 0), + CV1800B_GATE(CLK_APB_H265C, "clk_apb_h265c", "clk_axi6", REG_CLK_EN_2, 15, 0), + CV1800B_GATE(CLK_PM, "clk_pm", "clk_axi6", REG_CLK_EN_3, 8, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_CFG_REG_VIP, "clk_cfg_reg_vip", "clk_axi6", REG_CLK_EN_3, 31, 0), + CV1800B_GATE(CLK_CFG_REG_VC, "clk_cfg_reg_vc", "clk_axi6", REG_CLK_EN_4, 0, + CLK_IGNORE_UNUSED), + CV1800B_GATE(CLK_PWM, "clk_pwm", "clk_pwm_src", REG_CLK_EN_1, 8, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_UART0, "clk_uart0", "clk_cam0_200", REG_CLK_EN_1, 14, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_UART1, "clk_uart1", "clk_cam0_200", REG_CLK_EN_1, 16, 0), + CV1800B_GATE(CLK_UART2, "clk_uart2", "clk_cam0_200", REG_CLK_EN_1, 18, 0), + CV1800B_GATE(CLK_UART3, "clk_uart3", "clk_cam0_200", REG_CLK_EN_1, 20, 0), + CV1800B_GATE(CLK_UART4, "clk_uart4", "clk_cam0_200", REG_CLK_EN_1, 22, 0), + CV1800B_GATE(CLK_H264C, "clk_h264c", "clk_axi_video_codec", REG_CLK_EN_2, 10, 0), + CV1800B_GATE(CLK_H265C, "clk_h265c", "clk_axi_video_codec", REG_CLK_EN_2, 11, 0), + CV1800B_GATE(CLK_JPEG, "clk_jpeg", "clk_axi_video_codec", REG_CLK_EN_2, 12, + CLK_IGNORE_UNUSED), + CV1800B_GATE(CLK_CSI_MAC0_VIP, "clk_csi_mac0_vip", "clk_axi_vip", REG_CLK_EN_2, 18, 0), + CV1800B_GATE(CLK_CSI_MAC1_VIP, "clk_csi_mac1_vip", "clk_axi_vip", REG_CLK_EN_2, 19, 0), + CV1800B_GATE(CLK_ISP_TOP_VIP, "clk_isp_top_vip", "clk_axi_vip", REG_CLK_EN_2, 20, 0), + CV1800B_GATE(CLK_IMG_D_VIP, "clk_img_d_vip", "clk_axi_vip", REG_CLK_EN_2, 21, 0), + CV1800B_GATE(CLK_IMG_V_VIP, "clk_img_v_vip", "clk_axi_vip", REG_CLK_EN_2, 22, 0), + CV1800B_GATE(CLK_SC_TOP_VIP, "clk_sc_top_vip", "clk_axi_vip", REG_CLK_EN_2, 23, 0), + CV1800B_GATE(CLK_SC_D_VIP, "clk_sc_d_vip", "clk_axi_vip", REG_CLK_EN_2, 24, 0), + CV1800B_GATE(CLK_SC_V1_VIP, "clk_sc_v1_vip", "clk_axi_vip", REG_CLK_EN_2, 25, 0), + CV1800B_GATE(CLK_SC_V2_VIP, "clk_sc_v2_vip", "clk_axi_vip", REG_CLK_EN_2, 26, 0), + CV1800B_GATE(CLK_SC_V3_VIP, "clk_sc_v3_vip", "clk_axi_vip", REG_CLK_EN_2, 27, 0), + CV1800B_GATE(CLK_DWA_VIP, "clk_dwa_vip", "clk_axi_vip", REG_CLK_EN_2, 28, 0), + CV1800B_GATE(CLK_BT_VIP, "clk_bt_vip", "clk_axi_vip", REG_CLK_EN_2, 29, 0), + CV1800B_GATE(CLK_DISP_VIP, "clk_disp_vip", "clk_axi_vip", REG_CLK_EN_2, 30, 0), + CV1800B_GATE(CLK_DSI_MAC_VIP, "clk_dsi_mac_vip", "clk_axi_vip", REG_CLK_EN_2, 31, 0), + CV1800B_GATE(CLK_LVDS0_VIP, "clk_lvds0_vip", "clk_axi_vip", REG_CLK_EN_3, 0, 0), + CV1800B_GATE(CLK_LVDS1_VIP, "clk_lvds1_vip", "clk_axi_vip", REG_CLK_EN_3, 1, 0), + CV1800B_GATE(CLK_CSI0_RX_VIP, "clk_csi0_rx_vip", "clk_axi_vip", REG_CLK_EN_3, 2, 0), + CV1800B_GATE(CLK_CSI1_RX_VIP, "clk_csi1_rx_vip", "clk_axi_vip", REG_CLK_EN_3, 3, 0), + CV1800B_GATE(CLK_PAD_VI_VIP, "clk_pad_vi_vip", "clk_axi_vip", REG_CLK_EN_3, 4, 0), + CV1800B_GATE(CLK_PAD_VI1_VIP, "clk_pad_vi1_vip", "clk_axi_vip", REG_CLK_EN_3, 30, 0), + CV1800B_GATE(CLK_PAD_VI2_VIP, "clk_pad_vi2_vip", "clk_axi_vip", REG_CLK_EN_4, 7, 0), + CV1800B_GATE(CLK_CSI_BE_VIP, "clk_csi_be_vip", "clk_axi_vip", REG_CLK_EN_4, 8, 0), + CV1800B_GATE(CLK_VIP_IP0, "clk_vip_ip0", "clk_axi_vip", REG_CLK_EN_4, 9, 0), + CV1800B_GATE(CLK_VIP_IP1, "clk_vip_ip1", "clk_axi_vip", REG_CLK_EN_4, 10, 0), + CV1800B_GATE(CLK_VIP_IP2, "clk_vip_ip2", "clk_axi_vip", REG_CLK_EN_4, 11, 0), + CV1800B_GATE(CLK_VIP_IP3, "clk_vip_ip3", "clk_axi_vip", REG_CLK_EN_4, 12, 0), + CV1800B_GATE(CLK_IVE_VIP, "clk_ive_vip", "clk_axi_vip", REG_CLK_EN_4, 17, 0), + CV1800B_GATE(CLK_RAW_VIP, "clk_raw_vip", "clk_axi_vip", REG_CLK_EN_4, 18, 0), + CV1800B_GATE(CLK_OSDC_VIP, "clk_osdc_vip", "clk_axi_vip", REG_CLK_EN_4, 19, 0), + CV1800B_GATE(CLK_CSI_MAC2_VIP, "clk_csi_mac2_vip", "clk_axi_vip", REG_CLK_EN_4, 20, 0), + CV1800B_GATE(CLK_CAM0_VIP, "clk_cam0_vip", "clk_axi_vip", REG_CLK_EN_4, 21, 0), + CV1800B_GATE(CLK_TIMER0, "clk_timer0", "clk_xtal_misc", REG_CLK_EN_3, 9, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_TIMER1, "clk_timer1", "clk_xtal_misc", REG_CLK_EN_3, 10, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_TIMER2, "clk_timer2", "clk_xtal_misc", REG_CLK_EN_3, 11, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_TIMER3, "clk_timer3", "clk_xtal_misc", REG_CLK_EN_3, 12, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_TIMER4, "clk_timer4", "clk_xtal_misc", REG_CLK_EN_3, 13, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_TIMER5, "clk_timer5", "clk_xtal_misc", REG_CLK_EN_3, 14, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_TIMER6, "clk_timer6", "clk_xtal_misc", REG_CLK_EN_3, 15, CLK_IS_CRITICAL), + CV1800B_GATE(CLK_TIMER7, "clk_timer7", "clk_xtal_misc", REG_CLK_EN_3, 16, CLK_IS_CRITICAL), +}; + +struct cv1800b_clk_div cv1800b_div_info[] = { + CV1800B_DIV(CLK_1M, "clk_1m", "osc", REG_CLK_EN_3, 5, + REG_DIV_CLK_1M, 16, 6, 25, CLK_IS_CRITICAL), + CV1800B_DIV(CLK_EMMC_100K, "clk_emmc_100k", "clk_1m", REG_CLK_EN_0, 17, + REG_DIV_CLK_EMMC_100K, 16, 8, 10, 0), + CV1800B_DIV(CLK_SD0_100K, "clk_sd0_100k", "clk_1m", REG_CLK_EN_0, 20, + REG_DIV_CLK_SD0_100K, 16, 8, 10, 0), + CV1800B_DIV(CLK_SD1_100K, "clk_sd1_100k", "clk_1m", REG_CLK_EN_0, 23, + REG_DIV_CLK_SD1_100K, 16, 8, 10, 0), + CV1800B_DIV(CLK_GPIO_DB, "clk_gpio_db", "clk_1m", REG_CLK_EN_0, 31, + REG_DIV_CLK_GPIO_DB, 16, 16, 10, CLK_IS_CRITICAL) +}; + +struct cv1800b_clk_bypass_div cv1800b_bypass_div_info[] = { + CV1800B_BYPASS_DIV(CLK_AP_DEBUG, "clk_ap_debug", "clk_fpll", REG_CLK_EN_4, 5, + REG_DIV_CLK_AP_DEBUG, 16, 4, 5, REG_CLK_BYP_1, 4, CLK_IS_CRITICAL), + CV1800B_BYPASS_DIV(CLK_SRC_RTC_SYS_0, "clk_src_rtc_sys_0", "clk_fpll", REG_CLK_EN_4, 6, + REG_DIV_CLK_RTCSYS_SRC_0, 16, 4, 5, REG_CLK_BYP_1, 5, CLK_IS_CRITICAL), + CV1800B_BYPASS_DIV(CLK_CPU_GIC, "clk_cpu_gic", "clk_fpll", REG_CLK_EN_0, 2, + REG_DIV_CLK_CPU_GIC, 16, 4, 5, REG_CLK_BYP_0, 2, CLK_IS_CRITICAL), + CV1800B_BYPASS_DIV(CLK_ETH0_500M, "clk_eth0_500m", "clk_fpll", REG_CLK_EN_0, 25, + REG_DIV_CLK_GPIO_DB, 16, 4, 3, REG_CLK_BYP_0, 9, 0), + CV1800B_BYPASS_DIV(CLK_ETH1_500M, "clk_eth1_500m", "clk_fpll", REG_CLK_EN_0, 27, + REG_DIV_CLK_GPIO_DB, 16, 4, 3, REG_CLK_BYP_0, 10, 0), + CV1800B_BYPASS_DIV(CLK_AXI6, "clk_axi6", "clk_fpll", REG_CLK_EN_2, 2, REG_DIV_CLK_AXI6, 16, + 4, 15, REG_CLK_BYP_0, 20, CLK_IS_CRITICAL), + CV1800B_BYPASS_DIV(CLK_SPI, "clk_spi", "clk_fpll", REG_CLK_EN_3, 6, REG_DIV_CLK_SPI, 16, 6, + 8, REG_CLK_BYP_0, 30, 0), + CV1800B_BYPASS_DIV(CLK_DISP_SRC_VIP, "clk_disp_src_vip", "clk_disppll", REG_CLK_EN_2, 7, + REG_DIV_CLK_DISP_SRC_VIP, 16, 4, 8, REG_CLK_BYP_0, 25, 0), + CV1800B_BYPASS_DIV(CLK_CPU_AXI0, "clk_cpu_axi0", "clk_axi4", REG_CLK_EN_0, 1, + REG_DIV_CLK_CPU_AXI0, 16, 4, 3, REG_CLK_BYP_0, 1, CLK_IS_CRITICAL), + CV1800B_BYPASS_DIV(CLK_DSI_ESC, "clk_dsi_esc", "clk_axi6", REG_CLK_EN_2, 3, + REG_DIV_CLK_DSI_ESC, 16, 4, 5, REG_CLK_BYP_0, 21, 0), + CV1800B_BYPASS_DIV(CLK_I2C, "clk_i2c", "clk_axi6", REG_CLK_EN_3, 7, REG_DIV_CLK_I2C, 16, 4, + 1, REG_CLK_BYP_0, 31, 0), +}; + +struct cv1800b_clk_fixed_div cv1800b_fixed_div_info[] = { + CV1800B_FIXED_DIV(CLK_CAM0PLL_D2, "clk_cam0pll_d2", "clk_cam0pll", + REG_CAM0PLL_CLK_CSR, 1, 2, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), + CV1800B_FIXED_DIV(CLK_CAM0PLL_D3, "clk_cam0pll_d3", "clk_cam0pll", + REG_CAM0PLL_CLK_CSR, 2, 3, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), + CV1800B_FIXED_DIV(CLK_MIPIMPLL_D3, "clk_mipimpll_d3", "clk_mipimpll", + REG_MIPIMPLL_CLK_CSR, 2, 3, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), + CV1800B_FIXED_DIV(CLK_USB_33K, "clk_usb_33k", "clk_1m", + REG_CLK_EN_1, 31, 3, + 0), +}; + +struct cv1800b_clk_bypass_fixed_div cv1800b_bypass_fixed_div_info[] = { + CV1800B_BYPASS_FIXED_DIV(CLK_USB_125M, "clk_usb_125m", "clk_fpll", + REG_CLK_EN_1, 30, 12, + REG_CLK_BYP_0, 17, + CLK_SET_RATE_PARENT), + CV1800B_BYPASS_FIXED_DIV(CLK_USB_12M, "clk_usb_12m", "clk_fpll", + REG_CLK_EN_2, 0, 125, + REG_CLK_BYP_0, 18, + CLK_SET_RATE_PARENT), + CV1800B_BYPASS_FIXED_DIV(CLK_VC_SRC1, "clk_vc_src1", "clk_fpll", + REG_CLK_EN_3, 28, 2, + REG_CLK_BYP_1, 0, + CLK_SET_RATE_PARENT), + CV1800B_BYPASS_FIXED_DIV(CLK_VC_SRC2, "clk_vc_src2", "clk_fpll", + REG_CLK_EN_4, 3, 3, + REG_CLK_BYP_1, 3, + CLK_SET_RATE_PARENT), +}; + +struct cv1800b_clk_mux cv1800b_mux_info[] = { + CV1800B_MUX(CLK_CAM0, "clk_cam0", clk_cam_parents, + REG_CLK_EN_2, 16, + REG_CLK_CAM0_SRC_DIV, 16, 6, 0, + REG_CLK_CAM0_SRC_DIV, 8, 2, + CLK_IGNORE_UNUSED), + CV1800B_MUX(CLK_CAM1, "clk_cam1", clk_cam_parents, + REG_CLK_EN_2, 17, + REG_CLK_CAM1_SRC_DIV, 16, 6, 0, + REG_CLK_CAM1_SRC_DIV, 8, 2, + CLK_IGNORE_UNUSED), +}; + +struct cv1800b_clk_bypass_mux cv1800b_bypass_mux_info[] = { + CV1800B_BYPASS_MUX(CLK_TPU, "clk_tpu", clk_tpu_parents, + REG_CLK_EN_0, 4, + REG_DIV_CLK_TPU, 16, 4, 3, + REG_DIV_CLK_TPU, 8, 2, + REG_CLK_BYP_0, 3, + 0), + CV1800B_BYPASS_MUX(CLK_EMMC, "clk_emmc", clk_axi4_parents, + REG_CLK_EN_0, 16, + REG_DIV_CLK_EMMC, 16, 5, 15, + REG_DIV_CLK_EMMC, 8, 2, + REG_CLK_BYP_0, 5, + 0), + CV1800B_BYPASS_MUX(CLK_SD0, "clk_sd0", clk_axi4_parents, + REG_CLK_EN_0, 19, + REG_DIV_CLK_SD0, 16, 5, 15, + REG_DIV_CLK_SD0, 8, 2, + REG_CLK_BYP_0, 6, + 0), + CV1800B_BYPASS_MUX(CLK_SD1, "clk_sd1", clk_axi4_parents, + REG_CLK_EN_0, 22, + REG_DIV_CLK_SD1, 16, 5, 15, + REG_DIV_CLK_SD1, 8, 2, + REG_CLK_BYP_0, 7, + 0), + CV1800B_BYPASS_MUX(CLK_SPI_NAND, "clk_spi_nand", clk_axi4_parents, + REG_CLK_EN_0, 24, + REG_DIV_CLK_SPI_NAND, 16, 5, 8, + REG_DIV_CLK_SPI_NAND, 8, 2, + REG_CLK_BYP_0, 8, + 0), + CV1800B_BYPASS_MUX(CLK_AXI4, "clk_axi4", clk_axi4_parents, + REG_CLK_EN_2, 1, + REG_DIV_CLK_AXI4, 16, 4, 5, + REG_DIV_CLK_AXI4, 8, 2, + REG_CLK_BYP_0, 19, + CLK_IS_CRITICAL), + CV1800B_BYPASS_MUX(CLK_PWM_SRC, "clk_pwm_src", clk_axi4_parents, + REG_CLK_EN_4, 4, + REG_DIV_CLK_PWM_SRC_0, 16, 6, 10, + REG_DIV_CLK_PWM_SRC_0, 8, 2, + REG_CLK_BYP_0, 15, + CLK_IS_CRITICAL), + CV1800B_BYPASS_MUX(CLK_AUDSRC, "clk_audsrc", clk_aud_parents, + REG_CLK_EN_4, 1, + REG_DIV_CLK_AUDSRC, 16, 8, 18, + REG_DIV_CLK_AUDSRC, 8, 2, + REG_CLK_BYP_1, 2, + 0), + CV1800B_BYPASS_MUX(CLK_SDMA_AUD0, "clk_sdma_aud0", clk_aud_parents, + REG_CLK_EN_1, 2, + REG_DIV_CLK_SDMA_AUD0, 16, 8, 18, + REG_DIV_CLK_SDMA_AUD0, 8, 2, + REG_CLK_BYP_0, 11, + 0), + CV1800B_BYPASS_MUX(CLK_SDMA_AUD1, "clk_sdma_aud1", clk_aud_parents, + REG_CLK_EN_1, 3, + REG_DIV_CLK_SDMA_AUD1, 16, 8, 18, + REG_DIV_CLK_SDMA_AUD1, 8, 2, + REG_CLK_BYP_0, 12, + 0), + CV1800B_BYPASS_MUX(CLK_SDMA_AUD2, "clk_sdma_aud2", clk_aud_parents, + REG_CLK_EN_1, 3, + REG_DIV_CLK_SDMA_AUD2, 16, 8, 18, + REG_DIV_CLK_SDMA_AUD2, 8, 2, + REG_CLK_BYP_0, 13, + 0), + CV1800B_BYPASS_MUX(CLK_SDMA_AUD3, "clk_sdma_aud3", clk_aud_parents, + REG_CLK_EN_1, 3, + REG_DIV_CLK_SDMA_AUD3, 16, 8, 18, + REG_DIV_CLK_SDMA_AUD3, 8, 2, + REG_CLK_BYP_0, 14, + 0), + CV1800B_BYPASS_MUX(CLK_CAM0_200, "clk_cam0_200", clk_cam0_200_parents, + REG_CLK_EN_1, 13, + REG_DIV_CLK_CAM0_200, 16, 4, 1, + REG_DIV_CLK_CAM0_200, 8, 2, + REG_CLK_BYP_0, 16, + CLK_IS_CRITICAL), + CV1800B_BYPASS_MUX(CLK_AXI_VIP, "clk_axi_vip", clk_vip_sys_parents, + REG_CLK_EN_2, 4, + REG_DIV_CLK_AXI_VIP, 16, 4, 3, + REG_DIV_CLK_AXI_VIP, 8, 2, + REG_CLK_BYP_0, 22, + 0), + CV1800B_BYPASS_MUX(CLK_SRC_VIP_SYS_0, "clk_src_vip_sys_0", clk_vip_sys_parents, + REG_CLK_EN_2, 5, + REG_DIV_CLK_SRC_VIP_SYS_0, 16, 4, 6, + REG_DIV_CLK_SRC_VIP_SYS_0, 8, 2, + REG_CLK_BYP_0, 23, + 0), + CV1800B_BYPASS_MUX(CLK_SRC_VIP_SYS_1, "clk_src_vip_sys_1", clk_vip_sys_parents, + REG_CLK_EN_2, 6, + REG_DIV_CLK_SRC_VIP_SYS_1, 16, 4, 6, + REG_DIV_CLK_SRC_VIP_SYS_1, 8, 2, + REG_CLK_BYP_0, 24, + 0), + CV1800B_BYPASS_MUX(CLK_SRC_VIP_SYS_2, "clk_src_vip_sys_2", clk_vip_sys_parents, + REG_CLK_EN_3, 29, + REG_DIV_CLK_SRC_VIP_SYS_2, 16, 4, 2, + REG_DIV_CLK_SRC_VIP_SYS_2, 8, 2, + REG_CLK_BYP_1, 1, + 0), + CV1800B_BYPASS_MUX(CLK_SRC_VIP_SYS_3, "clk_src_vip_sys_3", clk_vip_sys_parents, + REG_CLK_EN_4, 15, + REG_DIV_CLK_SRC_VIP_SYS_3, 16, 4, 2, + REG_DIV_CLK_SRC_VIP_SYS_3, 8, 2, + REG_CLK_BYP_1, 8, + 0), + CV1800B_BYPASS_MUX(CLK_SRC_VIP_SYS_4, "clk_src_vip_sys_4", clk_vip_sys_parents, + REG_CLK_EN_4, 16, + REG_DIV_CLK_SRC_VIP_SYS_4, 16, 4, 3, + REG_DIV_CLK_SRC_VIP_SYS_4, 8, 2, + REG_CLK_BYP_1, 9, + 0), + CV1800B_BYPASS_MUX(CLK_AXI_VIDEO_CODEC, "clk_axi_video_codec", clk_axi_video_codec_parents, + REG_CLK_EN_2, 8, + REG_DIV_CLK_AXI_VIDEO_CODEC, 16, 4, 2, + REG_DIV_CLK_AXI_VIDEO_CODEC, 8, 2, + REG_CLK_BYP_0, 26, + 0), + CV1800B_BYPASS_MUX(CLK_VC_SRC0, "clk_vc_src0", clk_vc_src0_parents, + REG_CLK_EN_2, 9, + REG_DIV_CLK_VC_SRC0, 16, 4, 2, + REG_DIV_CLK_VC_SRC0, 8, 2, + REG_CLK_BYP_0, 27, + 0), +}; + +struct cv1800b_clk_mmux cv1800b_mmux_info[] = { + CV1800B_MMUX(CLK_C906_0, "clk_c906_0", clk_c906_0_parents, + REG_CLK_EN_4, 13, + REG_DIV_CLK_C906_0_0, 16, 4, 1, + REG_DIV_CLK_C906_0_1, 16, 4, 2, + REG_DIV_CLK_C906_0_0, 8, 2, + REG_DIV_CLK_C906_0_1, 8, 2, + REG_CLK_BYP_1, 6, + REG_CLK_SEL_0, 23, + CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE), + CV1800B_MMUX(CLK_C906_1, "clk_c906_1", clk_c906_1_parents, + REG_CLK_EN_4, 14, + REG_DIV_CLK_C906_1_0, 16, 4, 2, + REG_DIV_CLK_C906_1_1, 16, 4, 3, + REG_DIV_CLK_C906_1_0, 8, 2, + REG_DIV_CLK_C906_1_1, 8, 2, + REG_CLK_BYP_1, 7, + REG_CLK_SEL_0, 24, + CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE), + CV1800B_MMUX(CLK_A53, "clk_a53", clk_a53_parents, + REG_CLK_EN_0, 0, + REG_DIV_CLK_A53_0, 16, 4, 1, + REG_DIV_CLK_A53_1, 16, 4, 2, + REG_DIV_CLK_A53_0, 8, 2, + REG_DIV_CLK_A53_1, 8, 2, + REG_CLK_BYP_0, 0, + REG_CLK_SEL_0, 0, + CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE), +}; + +static struct cv1800b_clk_audio cv1800b_audio_info[] = { + CV1800B_AUDIO(CLK_A24M, "clk_a24m", "clk_mipimpll", + REG_APLL_FRAC_DIV_CTRL, 0, + REG_APLL_FRAC_DIV_CTRL, 3, + REG_APLL_FRAC_DIV_CTRL, 1, + REG_APLL_FRAC_DIV_CTRL, 2, + REG_APLL_FRAC_DIV_M, 0, 22, + REG_APLL_FRAC_DIV_N, 0, 22, + 0), +}; + +static struct cv1800b_clk_ipll cv1800b_ipll_info[] = { + CV1800B_IPLL(CLK_FPLL, "clk_fpll", "osc", REG_FPLL_CSR, + REG_PLL_G6_CTRL, 8, + REG_PLL_G6_STATUS, 2, + CLK_IS_CRITICAL), + CV1800B_IPLL(CLK_MIPIMPLL, "clk_mipimpll", "osc", REG_MIPIMPLL_CSR, + REG_PLL_G2_CTRL, 0, + REG_PLL_G2_STATUS, 0, + CLK_IS_CRITICAL), +}; + +static struct cv1800b_clk_fpll cv1800b_fpll_info[] = { + CV1800B_FPLL(CLK_MPLL, "clk_mpll", "osc", REG_MPLL_CSR, + REG_PLL_G6_CTRL, 0, + REG_PLL_G6_STATUS, 0, + REG_PLL_G6_SSC_SYN_CTRL, 2, + REG_PLL_G6_SSC_SYN_CTRL, 0, + REG_MPLL_SSC_SYN_CTRL, REG_MPLL_SSC_SYN_SET, + CLK_IS_CRITICAL), + CV1800B_FPLL(CLK_TPLL, "clk_tpll", "osc", REG_TPLL_CSR, + REG_PLL_G6_CTRL, 4, + REG_PLL_G6_STATUS, 1, + REG_PLL_G6_SSC_SYN_CTRL, 3, + REG_PLL_G6_SSC_SYN_CTRL, 0, + REG_TPLL_SSC_SYN_CTRL, REG_TPLL_SSC_SYN_SET, + CLK_IS_CRITICAL), + CV1800B_FPLL(CLK_A0PLL, "clk_a0pll", "clk_mipimpll", REG_A0PLL_CSR, + REG_PLL_G2_CTRL, 4, + REG_PLL_G2_STATUS, 1, + REG_PLL_G2_SSC_SYN_CTRL, 2, + REG_PLL_G2_SSC_SYN_CTRL, 0, + REG_A0PLL_SSC_SYN_CTRL, REG_A0PLL_SSC_SYN_SET, + CLK_IS_CRITICAL), + CV1800B_FPLL(CLK_DISPPLL, "clk_disppll", "clk_mipimpll", REG_DISPPLL_CSR, + REG_PLL_G2_CTRL, 8, + REG_PLL_G2_STATUS, 2, + REG_PLL_G2_SSC_SYN_CTRL, 3, + REG_PLL_G2_SSC_SYN_CTRL, 0, + REG_DISPPLL_SSC_SYN_CTRL, REG_DISPPLL_SSC_SYN_SET, + CLK_IS_CRITICAL), + CV1800B_FPLL(CLK_CAM0PLL, "clk_cam0pll", "clk_mipimpll", REG_CAM0PLL_CSR, + REG_PLL_G2_CTRL, 12, + REG_PLL_G2_STATUS, 3, + REG_PLL_G2_SSC_SYN_CTRL, 4, + REG_PLL_G2_SSC_SYN_CTRL, 0, + REG_CAM0PLL_SSC_SYN_CTRL, REG_CAM0PLL_SSC_SYN_SET, + CLK_IGNORE_UNUSED), + CV1800B_FPLL(CLK_CAM1PLL, "clk_cam1pll", "clk_mipimpll", REG_CAM1PLL_CSR, + REG_PLL_G2_CTRL, 16, + REG_PLL_G2_STATUS, 4, + REG_PLL_G2_SSC_SYN_CTRL, 5, + REG_PLL_G2_SSC_SYN_CTRL, 0, + REG_CAM1PLL_SSC_SYN_CTRL, REG_CAM1PLL_SSC_SYN_SET, + CLK_IS_CRITICAL), +}; + +static int cv1800b_register_clk(struct udevice *dev) +{ + struct clk osc; + ulong osc_rate; + void *base = devfdt_get_addr_ptr(dev); + int i, ret; + + ret = clk_get_by_index(dev, 0, &osc); + if (ret) { + pr_err("Failed to get clock\n"); + return ret; + } + + osc_rate = clk_get_rate(&osc); + clk_dm(CV1800B_CLK_OSC, clk_register_fixed_rate(NULL, "osc", osc_rate)); + clk_dm(CV1800B_CLK_BYPASS, clk_register_fixed_rate(NULL, "bypass", osc_rate)); + + for (i = 0; i < ARRAY_SIZE(cv1800b_ipll_info); i++) { + struct cv1800b_clk_ipll *ipll = &cv1800b_ipll_info[i]; + + ipll->base = base; + ret = clk_register(&ipll->clk, "cv1800b_clk_ipll", ipll->name, + ipll->parent_name); + if (ret) { + pr_err("Failed to register ipll %s\n", ipll->name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_fpll_info); i++) { + struct cv1800b_clk_fpll *fpll = &cv1800b_fpll_info[i]; + + fpll->ipll.base = base; + ret = clk_register(&fpll->ipll.clk, "cv1800b_clk_fpll", + fpll->ipll.name, fpll->ipll.parent_name); + if (ret) { + pr_err("Failed to register fpll %s\n", fpll->ipll.name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_div_info); i++) { + struct cv1800b_clk_div *div = &cv1800b_div_info[i]; + + div->base = base; + ret = clk_register(&div->clk, "cv1800b_clk_div", div->name, + div->parent_name); + if (ret) { + pr_err("Failed to register div %s\n", div->name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_fixed_div_info); i++) { + struct cv1800b_clk_fixed_div *fixed_div = + &cv1800b_fixed_div_info[i]; + + fixed_div->base = base; + ret = clk_register(&fixed_div->clk, "cv1800b_clk_fixed_div", + fixed_div->name, fixed_div->parent_name); + if (ret) { + pr_err("Failed to register fixed div %s\n", + fixed_div->name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_bypass_fixed_div_info); i++) { + struct cv1800b_clk_bypass_fixed_div *bypass_fixed_div = + &cv1800b_bypass_fixed_div_info[i]; + + bypass_fixed_div->div.base = base; + ret = clk_register(&bypass_fixed_div->div.clk, + "cv1800b_clk_bypass_fixed_div", + bypass_fixed_div->div.name, + bypass_fixed_div->div.parent_name); + if (ret) { + pr_err("Failed to register bypass fixed div %s\n", + bypass_fixed_div->div.name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_mux_info); i++) { + struct cv1800b_clk_mux *mux = &cv1800b_mux_info[i]; + int parent; + + mux->base = base; + parent = cv1800b_clk_getfield(base, &mux->mux); + ret = clk_register(&mux->clk, "cv1800b_clk_mux", mux->name, + mux->parent_names[parent]); + if (ret) { + pr_err("Failed to register mux %s\n", mux->name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_mmux_info); i++) { + struct cv1800b_clk_mmux *mmux = &cv1800b_mmux_info[i]; + int clk_sel, parent, idx; + + mmux->base = base; + clk_sel = cv1800b_clk_getbit(base, &mmux->clk_sel) ? 0 : 1; + parent = cv1800b_clk_getfield(base, &mmux->mux[clk_sel]); + for (idx = 0; idx < mmux->num_parents; idx++) { + if (clk_sel == mmux->parent_infos[idx].clk_sel && + parent == mmux->parent_infos[idx].index) + break; + } + ret = clk_register(&mmux->clk, "cv1800b_clk_mmux", mmux->name, + mmux->parent_infos[idx].name); + if (ret) { + pr_err("Failed to register mmux %s\n", mmux->name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_audio_info); i++) { + struct cv1800b_clk_audio *audio = &cv1800b_audio_info[i]; + + audio->base = base; + ret = clk_register(&audio->clk, "cv1800b_clk_audio", + audio->name, audio->parent_name); + if (ret) { + pr_err("Failed to register audio %s\n", audio->name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_bypass_mux_info); i++) { + struct cv1800b_clk_bypass_mux *bypass_mux = + &cv1800b_bypass_mux_info[i]; + int parent; + + bypass_mux->mux.base = base; + parent = cv1800b_clk_getfield(base, &bypass_mux->mux.mux); + ret = clk_register(&bypass_mux->mux.clk, + "cv1800b_clk_bypass_mux", + bypass_mux->mux.name, + bypass_mux->mux.parent_names[parent]); + if (ret) { + pr_err("Failed to register bypass mux %s\n", + bypass_mux->mux.name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_bypass_div_info); i++) { + struct cv1800b_clk_bypass_div *bypass_div = + &cv1800b_bypass_div_info[i]; + + bypass_div->div.base = base; + ret = clk_register(&bypass_div->div.clk, + "cv1800b_clk_bypass_div", + bypass_div->div.name, + bypass_div->div.parent_name); + if (ret) { + pr_err("Failed to register bypass div %s\n", + bypass_div->div.name); + return ret; + } + } + + for (i = 0; i < ARRAY_SIZE(cv1800b_gate_info); i++) { + struct cv1800b_clk_gate *gate = &cv1800b_gate_info[i]; + + gate->base = base; + ret = clk_register(&gate->clk, "cv1800b_clk_gate", gate->name, + gate->parent_name); + if (ret) { + pr_err("Failed to register gate %s\n", gate->name); + return ret; + } + } + return 0; +} + +static int cv1800b_clk_probe(struct udevice *dev) +{ + return cv1800b_register_clk(dev); +} + +static int cv1800b_clk_enable(struct clk *clk) +{ + struct clk *c; + int err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(clk->id), &c); + + if (err) + return err; + return clk_enable(c); +} + +static int cv1800b_clk_disable(struct clk *clk) +{ + struct clk *c; + int err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(clk->id), &c); + + if (err) + return err; + return clk_disable(c); +} + +static ulong cv1800b_clk_get_rate(struct clk *clk) +{ + struct clk *c; + int err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(clk->id), &c); + + if (err) + return err; + return clk_get_rate(c); +} + +static ulong cv1800b_clk_set_rate(struct clk *clk, ulong rate) +{ + struct clk *c; + int err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(clk->id), &c); + + if (err) + return err; + return clk_set_rate(c, rate); +} + +static int cv1800b_clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct clk *c, *p; + int err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(clk->id), &c); + + if (err) + return err; + err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(parent->id), &p); + if (err) + return err; + return clk_set_parent(c, p); +} + +const struct clk_ops cv1800b_clk_ops = { + .enable = cv1800b_clk_enable, + .disable = cv1800b_clk_disable, + .get_rate = cv1800b_clk_get_rate, + .set_rate = cv1800b_clk_set_rate, + .set_parent = cv1800b_clk_set_parent, +}; + +static const struct udevice_id cv1800b_clk_of_match[] = { + { .compatible = "sophgo,cv1800-clk" }, + { }, +}; + +U_BOOT_DRIVER(sophgo_clk) = { + .name = "cv1800b_clk", + .id = UCLASS_CLK, + .of_match = cv1800b_clk_of_match, + .probe = cv1800b_clk_probe, + .ops = &cv1800b_clk_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/sophgo/clk-cv1800b.h b/drivers/clk/sophgo/clk-cv1800b.h new file mode 100644 index 00000000000..1e7107b5d05 --- /dev/null +++ b/drivers/clk/sophgo/clk-cv1800b.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> + */ + +#ifndef _CLK_SOPHGO_CV1800_H_ +#define _CLK_SOPHGO_CV1800_H_ + +#include <dt-bindings/clock/sophgo,cv1800.h> + +#define CV1800_CLK_MAX (CLK_XTAL_AP + 1) +#define CV1810_CLK_MAX (CLK_DISP_SRC_VIP + 1) + +#define REG_PLL_G2_CTRL 0x800 +#define REG_PLL_G2_STATUS 0x804 +#define REG_MIPIMPLL_CSR 0x808 +#define REG_A0PLL_CSR 0x80C +#define REG_DISPPLL_CSR 0x810 +#define REG_CAM0PLL_CSR 0x814 +#define REG_CAM1PLL_CSR 0x818 +#define REG_PLL_G2_SSC_SYN_CTRL 0x840 +#define REG_A0PLL_SSC_SYN_CTRL 0x850 +#define REG_A0PLL_SSC_SYN_SET 0x854 +#define REG_A0PLL_SSC_SYN_SPAN 0x858 +#define REG_A0PLL_SSC_SYN_STEP 0x85C +#define REG_DISPPLL_SSC_SYN_CTRL 0x860 +#define REG_DISPPLL_SSC_SYN_SET 0x864 +#define REG_DISPPLL_SSC_SYN_SPAN 0x868 +#define REG_DISPPLL_SSC_SYN_STEP 0x86C +#define REG_CAM0PLL_SSC_SYN_CTRL 0x870 +#define REG_CAM0PLL_SSC_SYN_SET 0x874 +#define REG_CAM0PLL_SSC_SYN_SPAN 0x878 +#define REG_CAM0PLL_SSC_SYN_STEP 0x87C +#define REG_CAM1PLL_SSC_SYN_CTRL 0x880 +#define REG_CAM1PLL_SSC_SYN_SET 0x884 +#define REG_CAM1PLL_SSC_SYN_SPAN 0x888 +#define REG_CAM1PLL_SSC_SYN_STEP 0x88C +#define REG_APLL_FRAC_DIV_CTRL 0x890 +#define REG_APLL_FRAC_DIV_M 0x894 +#define REG_APLL_FRAC_DIV_N 0x898 +#define REG_MIPIMPLL_CLK_CSR 0x8A0 +#define REG_A0PLL_CLK_CSR 0x8A4 +#define REG_DISPPLL_CLK_CSR 0x8A8 +#define REG_CAM0PLL_CLK_CSR 0x8AC +#define REG_CAM1PLL_CLK_CSR 0x8B0 +#define REG_CLK_CAM0_SRC_DIV 0x8C0 +#define REG_CLK_CAM1_SRC_DIV 0x8C4 + +/* top_pll_g6 */ +#define REG_PLL_G6_CTRL 0x900 +#define REG_PLL_G6_STATUS 0x904 +#define REG_MPLL_CSR 0x908 +#define REG_TPLL_CSR 0x90C +#define REG_FPLL_CSR 0x910 +#define REG_PLL_G6_SSC_SYN_CTRL 0x940 +#define REG_DPLL_SSC_SYN_CTRL 0x950 +#define REG_DPLL_SSC_SYN_SET 0x954 +#define REG_DPLL_SSC_SYN_SPAN 0x958 +#define REG_DPLL_SSC_SYN_STEP 0x95C +#define REG_MPLL_SSC_SYN_CTRL 0x960 +#define REG_MPLL_SSC_SYN_SET 0x964 +#define REG_MPLL_SSC_SYN_SPAN 0x968 +#define REG_MPLL_SSC_SYN_STEP 0x96C +#define REG_TPLL_SSC_SYN_CTRL 0x970 +#define REG_TPLL_SSC_SYN_SET 0x974 +#define REG_TPLL_SSC_SYN_SPAN 0x978 +#define REG_TPLL_SSC_SYN_STEP 0x97C + +/* clkgen */ +#define REG_CLK_EN_0 0x000 +#define REG_CLK_EN_1 0x004 +#define REG_CLK_EN_2 0x008 +#define REG_CLK_EN_3 0x00C +#define REG_CLK_EN_4 0x010 +#define REG_CLK_SEL_0 0x020 +#define REG_CLK_BYP_0 0x030 +#define REG_CLK_BYP_1 0x034 + +#define REG_DIV_CLK_A53_0 0x040 +#define REG_DIV_CLK_A53_1 0x044 +#define REG_DIV_CLK_CPU_AXI0 0x048 +#define REG_DIV_CLK_CPU_GIC 0x050 +#define REG_DIV_CLK_TPU 0x054 +#define REG_DIV_CLK_EMMC 0x064 +#define REG_DIV_CLK_EMMC_100K 0x06C +#define REG_DIV_CLK_SD0 0x070 +#define REG_DIV_CLK_SD0_100K 0x078 +#define REG_DIV_CLK_SD1 0x07C +#define REG_DIV_CLK_SD1_100K 0x084 +#define REG_DIV_CLK_SPI_NAND 0x088 +#define REG_DIV_CLK_ETH0_500M 0x08C +#define REG_DIV_CLK_ETH1_500M 0x090 +#define REG_DIV_CLK_GPIO_DB 0x094 +#define REG_DIV_CLK_SDMA_AUD0 0x098 +#define REG_DIV_CLK_SDMA_AUD1 0x09C +#define REG_DIV_CLK_SDMA_AUD2 0x0A0 +#define REG_DIV_CLK_SDMA_AUD3 0x0A4 +#define REG_DIV_CLK_CAM0_200 0x0A8 +#define REG_DIV_CLK_AXI4 0x0B8 +#define REG_DIV_CLK_AXI6 0x0BC +#define REG_DIV_CLK_DSI_ESC 0x0C4 +#define REG_DIV_CLK_AXI_VIP 0x0C8 +#define REG_DIV_CLK_SRC_VIP_SYS_0 0x0D0 +#define REG_DIV_CLK_SRC_VIP_SYS_1 0x0D8 +#define REG_DIV_CLK_DISP_SRC_VIP 0x0E0 +#define REG_DIV_CLK_AXI_VIDEO_CODEC 0x0E4 +#define REG_DIV_CLK_VC_SRC0 0x0EC +#define REG_DIV_CLK_1M 0x0FC +#define REG_DIV_CLK_SPI 0x100 +#define REG_DIV_CLK_I2C 0x104 +#define REG_DIV_CLK_SRC_VIP_SYS_2 0x110 +#define REG_DIV_CLK_AUDSRC 0x118 +#define REG_DIV_CLK_PWM_SRC_0 0x120 +#define REG_DIV_CLK_AP_DEBUG 0x128 +#define REG_DIV_CLK_RTCSYS_SRC_0 0x12C +#define REG_DIV_CLK_C906_0_0 0x130 +#define REG_DIV_CLK_C906_0_1 0x134 +#define REG_DIV_CLK_C906_1_0 0x138 +#define REG_DIV_CLK_C906_1_1 0x13C +#define REG_DIV_CLK_SRC_VIP_SYS_3 0x140 +#define REG_DIV_CLK_SRC_VIP_SYS_4 0x144 + +#endif /* _CLK_SOPHGO_CV1800_H_ */ diff --git a/drivers/clk/sophgo/clk-ip.c b/drivers/clk/sophgo/clk-ip.c new file mode 100644 index 00000000000..d571fa671b0 --- /dev/null +++ b/drivers/clk/sophgo/clk-ip.c @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> + */ + +#include <dm.h> +#include <div64.h> +#include <linux/clk-provider.h> +#include <linux/io.h> + +#include "clk-common.h" +#include "clk-ip.h" + +static int get_parent_index(struct clk *clk, const char *const *parent_name, + u8 num_parents) +{ + const char *name = clk_hw_get_name(clk); + int i; + + for (i = 0; i < num_parents; i++) { + if (!strcmp(name, parent_name[i])) + return i; + } + + return -1; +} + +/* GATE */ +#define to_cv1800b_clk_gate(_clk) \ + container_of(_clk, struct cv1800b_clk_gate, clk) + +static int gate_enable(struct clk *clk) +{ + struct cv1800b_clk_gate *gate = to_cv1800b_clk_gate(clk); + + return cv1800b_clk_setbit(gate->base, &gate->gate); +} + +static int gate_disable(struct clk *clk) +{ + struct cv1800b_clk_gate *gate = to_cv1800b_clk_gate(clk); + + return cv1800b_clk_clrbit(gate->base, &gate->gate); +} + +static ulong gate_get_rate(struct clk *clk) +{ + return clk_get_parent_rate(clk); +} + +const struct clk_ops cv1800b_clk_gate_ops = { + .disable = gate_disable, + .enable = gate_enable, + .get_rate = gate_get_rate, +}; + +U_BOOT_DRIVER(cv1800b_clk_gate) = { + .name = "cv1800b_clk_gate", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* DIV */ +#define CLK_DIV_EN_FACTOR BIT(3) + +#define to_cv1800b_clk_div(_clk) container_of(_clk, struct cv1800b_clk_div, clk) + +static int div_enable(struct clk *clk) +{ + struct cv1800b_clk_div *div = to_cv1800b_clk_div(clk); + + return cv1800b_clk_setbit(div->base, &div->gate); +} + +static int div_disable(struct clk *clk) +{ + struct cv1800b_clk_div *div = to_cv1800b_clk_div(clk); + + return cv1800b_clk_clrbit(div->base, &div->gate); +} + +static ulong div_get_rate(struct clk *clk) +{ + struct cv1800b_clk_div *div = to_cv1800b_clk_div(clk); + ulong val; + + if (div->div_init == 0 || + readl(div->base + div->div.offset) & CLK_DIV_EN_FACTOR) + val = cv1800b_clk_getfield(div->base, &div->div); + else + val = div->div_init; + + return DIV_ROUND_UP_ULL(clk_get_parent_rate(clk), val); +} + +static ulong div_set_rate(struct clk *clk, ulong rate) +{ + struct cv1800b_clk_div *div = to_cv1800b_clk_div(clk); + ulong parent_rate = clk_get_parent_rate(clk); + u32 val; + + val = DIV_ROUND_UP_ULL(parent_rate, rate); + val = min_t(u32, val, clk_div_mask(div->div.width)); + + cv1800b_clk_setfield(div->base, &div->div, val); + if (div->div_init > 0) + setbits_le32(div->base + div->div.offset, CLK_DIV_EN_FACTOR); + + return DIV_ROUND_UP_ULL(parent_rate, val); +} + +const struct clk_ops cv1800b_clk_div_ops = { + .disable = div_disable, + .enable = div_enable, + .get_rate = div_get_rate, + .set_rate = div_set_rate, +}; + +U_BOOT_DRIVER(cv1800b_clk_div) = { + .name = "cv1800b_clk_div", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_div_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#define to_cv1800b_clk_bypass_div(_clk) \ + container_of(_clk, struct cv1800b_clk_bypass_div, div.clk) + +static ulong bypass_div_get_rate(struct clk *clk) +{ + struct cv1800b_clk_bypass_div *div = to_cv1800b_clk_bypass_div(clk); + + if (cv1800b_clk_getbit(div->div.base, &div->bypass)) + return 0; + + return div_get_rate(clk); +} + +static ulong bypass_div_set_rate(struct clk *clk, ulong rate) +{ + struct cv1800b_clk_bypass_div *div = to_cv1800b_clk_bypass_div(clk); + + if (cv1800b_clk_getbit(div->div.base, &div->bypass)) + return 0; + + return div_set_rate(clk, rate); +} + +static int bypass_div_set_parent(struct clk *clk, struct clk *pclk) +{ + struct cv1800b_clk_bypass_div *div = to_cv1800b_clk_bypass_div(clk); + + if (pclk->id == CV1800B_CLK_BYPASS) { + cv1800b_clk_setbit(div->div.base, &div->bypass); + return 0; + } + + if (strcmp(clk_hw_get_name(pclk), div->div.parent_name)) + return -EINVAL; + + cv1800b_clk_clrbit(div->div.base, &div->bypass); + return 0; +} + +const struct clk_ops cv1800b_clk_bypass_div_ops = { + .disable = div_disable, + .enable = div_enable, + .get_rate = bypass_div_get_rate, + .set_rate = bypass_div_set_rate, + .set_parent = bypass_div_set_parent, +}; + +U_BOOT_DRIVER(cv1800b_clk_bypass_div) = { + .name = "cv1800b_clk_bypass_div", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_bypass_div_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* FIXED DIV */ +#define to_cv1800b_clk_fixed_div(_clk) \ + container_of(_clk, struct cv1800b_clk_fixed_div, clk) + +static int fixed_div_enable(struct clk *clk) +{ + struct cv1800b_clk_fixed_div *div = to_cv1800b_clk_fixed_div(clk); + + return cv1800b_clk_setbit(div->base, &div->gate); +} + +static int fixed_div_disable(struct clk *clk) +{ + struct cv1800b_clk_fixed_div *div = to_cv1800b_clk_fixed_div(clk); + + return cv1800b_clk_clrbit(div->base, &div->gate); +} + +static ulong fixed_div_get_rate(struct clk *clk) +{ + struct cv1800b_clk_fixed_div *div = to_cv1800b_clk_fixed_div(clk); + + return DIV_ROUND_UP_ULL(clk_get_parent_rate(clk), div->div); +} + +const struct clk_ops cv1800b_clk_fixed_div_ops = { + .disable = fixed_div_disable, + .enable = fixed_div_enable, + .get_rate = fixed_div_get_rate, +}; + +U_BOOT_DRIVER(cv1800b_clk_fixed_div) = { + .name = "cv1800b_clk_fixed_div", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_fixed_div_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#define to_cv1800b_clk_bypass_fixed_div(_clk) \ + container_of(_clk, struct cv1800b_clk_bypass_fixed_div, div.clk) + +static ulong bypass_fixed_div_get_rate(struct clk *clk) +{ + struct cv1800b_clk_bypass_fixed_div *div = + to_cv1800b_clk_bypass_fixed_div(clk); + + if (cv1800b_clk_getbit(div->div.base, &div->bypass)) + return 0; + + return fixed_div_get_rate(clk); +} + +static int bypass_fixed_div_set_parent(struct clk *clk, struct clk *pclk) +{ + struct cv1800b_clk_bypass_fixed_div *div = + to_cv1800b_clk_bypass_fixed_div(clk); + + if (pclk->id == CV1800B_CLK_BYPASS) { + cv1800b_clk_setbit(div->div.base, &div->bypass); + return 0; + } + + if (strcmp(clk_hw_get_name(pclk), div->div.parent_name)) + return -EINVAL; + + cv1800b_clk_clrbit(div->div.base, &div->bypass); + return 0; +} + +const struct clk_ops cv1800b_clk_bypass_fixed_div_ops = { + .disable = fixed_div_disable, + .enable = fixed_div_enable, + .get_rate = bypass_fixed_div_get_rate, + .set_parent = bypass_fixed_div_set_parent, +}; + +U_BOOT_DRIVER(cv1800b_clk_bypass_fixed_div) = { + .name = "cv1800b_clk_bypass_fixed_div", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_bypass_fixed_div_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* MUX */ +#define to_cv1800b_clk_mux(_clk) container_of(_clk, struct cv1800b_clk_mux, clk) + +static int mux_enable(struct clk *clk) +{ + struct cv1800b_clk_mux *mux = to_cv1800b_clk_mux(clk); + + return cv1800b_clk_setbit(mux->base, &mux->gate); +} + +static int mux_disable(struct clk *clk) +{ + struct cv1800b_clk_mux *mux = to_cv1800b_clk_mux(clk); + + return cv1800b_clk_clrbit(mux->base, &mux->gate); +} + +static ulong mux_get_rate(struct clk *clk) +{ + struct cv1800b_clk_mux *mux = to_cv1800b_clk_mux(clk); + ulong val; + + if (mux->div_init == 0 || + readl(mux->base + mux->div.offset) & CLK_DIV_EN_FACTOR) + val = cv1800b_clk_getfield(mux->base, &mux->div); + else + val = mux->div_init; + + return DIV_ROUND_UP_ULL(clk_get_parent_rate(clk), val); +} + +static ulong mux_set_rate(struct clk *clk, ulong rate) +{ + struct cv1800b_clk_mux *mux = to_cv1800b_clk_mux(clk); + ulong parent_rate = clk_get_parent_rate(clk); + ulong val; + + val = DIV_ROUND_UP_ULL(parent_rate, rate); + val = min_t(u32, val, clk_div_mask(mux->div.width)); + + cv1800b_clk_setfield(mux->base, &mux->div, val); + if (mux->div_init > 0) + setbits_le32(mux->base + mux->div.offset, CLK_DIV_EN_FACTOR); + + return DIV_ROUND_UP_ULL(parent_rate, val); +} + +static int mux_set_parent(struct clk *clk, struct clk *pclk) +{ + struct cv1800b_clk_mux *mux = to_cv1800b_clk_mux(clk); + int index = get_parent_index(pclk, mux->parent_names, mux->num_parents); + + if (index < 0) + return -EINVAL; + + cv1800b_clk_setfield(mux->base, &mux->mux, index); + return 0; +} + +const struct clk_ops cv1800b_clk_mux_ops = { + .disable = mux_disable, + .enable = mux_enable, + .get_rate = mux_get_rate, + .set_rate = mux_set_rate, + .set_parent = mux_set_parent, +}; + +U_BOOT_DRIVER(cv1800b_clk_mux) = { + .name = "cv1800b_clk_mux", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_mux_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#define to_cv1800b_clk_bypass_mux(_clk) \ + container_of(_clk, struct cv1800b_clk_bypass_mux, mux.clk) + +static ulong bypass_mux_get_rate(struct clk *clk) +{ + struct cv1800b_clk_bypass_mux *mux = to_cv1800b_clk_bypass_mux(clk); + + if (cv1800b_clk_getbit(mux->mux.base, &mux->bypass)) + return 0; + + return mux_get_rate(clk); +} + +static ulong bypass_mux_set_rate(struct clk *clk, ulong rate) +{ + struct cv1800b_clk_bypass_mux *mux = to_cv1800b_clk_bypass_mux(clk); + + if (cv1800b_clk_getbit(mux->mux.base, &mux->bypass)) + return 0; + + return mux_set_rate(clk, rate); +} + +static int bypass_mux_set_parent(struct clk *clk, struct clk *pclk) +{ + struct cv1800b_clk_bypass_mux *mux = to_cv1800b_clk_bypass_mux(clk); + int index; + + if (pclk->id == CV1800B_CLK_BYPASS) { + cv1800b_clk_setbit(mux->mux.base, &mux->bypass); + return 0; + } + + index = get_parent_index(pclk, mux->mux.parent_names, + mux->mux.num_parents); + if (index < 0) + return -EINVAL; + + cv1800b_clk_clrbit(mux->mux.base, &mux->bypass); + cv1800b_clk_setfield(mux->mux.base, &mux->mux.mux, index); + return 0; +} + +const struct clk_ops cv1800b_clk_bypass_mux_ops = { + .disable = mux_disable, + .enable = mux_enable, + .get_rate = bypass_mux_get_rate, + .set_rate = bypass_mux_set_rate, + .set_parent = bypass_mux_set_parent, +}; + +U_BOOT_DRIVER(cv1800b_clk_bypass_mux) = { + .name = "cv1800b_clk_bypass_mux", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_bypass_mux_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* MMUX */ +#define to_cv1800b_clk_mmux(_clk) \ + container_of(_clk, struct cv1800b_clk_mmux, clk) + +static int mmux_enable(struct clk *clk) +{ + struct cv1800b_clk_mmux *mmux = to_cv1800b_clk_mmux(clk); + + return cv1800b_clk_setbit(mmux->base, &mmux->gate); +} + +static int mmux_disable(struct clk *clk) +{ + struct cv1800b_clk_mmux *mmux = to_cv1800b_clk_mmux(clk); + + return cv1800b_clk_clrbit(mmux->base, &mmux->gate); +} + +static ulong mmux_get_rate(struct clk *clk) +{ + struct cv1800b_clk_mmux *mmux = to_cv1800b_clk_mmux(clk); + int clk_sel = 1; + ulong reg, val; + + if (cv1800b_clk_getbit(mmux->base, &mmux->bypass)) + return 0; + + if (cv1800b_clk_getbit(mmux->base, &mmux->clk_sel)) + clk_sel = 0; + + reg = readl(mmux->base + mmux->div[clk_sel].offset); + + if (mmux->div_init[clk_sel] == 0 || reg & CLK_DIV_EN_FACTOR) + val = cv1800b_clk_getfield(mmux->base, &mmux->div[clk_sel]); + else + val = mmux->div_init[clk_sel]; + + return DIV_ROUND_UP_ULL(clk_get_parent_rate(clk), val); +} + +static ulong mmux_set_rate(struct clk *clk, ulong rate) +{ + struct cv1800b_clk_mmux *mmux = to_cv1800b_clk_mmux(clk); + int clk_sel = 1; + ulong parent_rate = clk_get_parent_rate(clk); + ulong val; + + if (cv1800b_clk_getbit(mmux->base, &mmux->bypass)) + return 0; + + if (cv1800b_clk_getbit(mmux->base, &mmux->clk_sel)) + clk_sel = 0; + + val = DIV_ROUND_UP_ULL(parent_rate, rate); + val = min_t(u32, val, clk_div_mask(mmux->div[clk_sel].width)); + + cv1800b_clk_setfield(mmux->base, &mmux->div[clk_sel], val); + if (mmux->div_init[clk_sel] > 0) + setbits_le32(mmux->base + mmux->div[clk_sel].offset, + CLK_DIV_EN_FACTOR); + + return DIV_ROUND_UP_ULL(parent_rate, val); +} + +static int mmux_set_parent(struct clk *clk, struct clk *pclk) +{ + struct cv1800b_clk_mmux *mmux = to_cv1800b_clk_mmux(clk); + const char *pname = clk_hw_get_name(pclk); + int i; + u8 clk_sel, index; + + if (pclk->id == CV1800B_CLK_BYPASS) { + cv1800b_clk_setbit(mmux->base, &mmux->bypass); + return 0; + } + + for (i = 0; i < mmux->num_parents; i++) { + if (!strcmp(pname, mmux->parent_infos[i].name)) + break; + } + + if (i == mmux->num_parents) + return -EINVAL; + + clk_sel = mmux->parent_infos[i].clk_sel; + index = mmux->parent_infos[i].index; + cv1800b_clk_clrbit(mmux->base, &mmux->bypass); + if (clk_sel) + cv1800b_clk_clrbit(mmux->base, &mmux->clk_sel); + else + cv1800b_clk_setbit(mmux->base, &mmux->clk_sel); + + cv1800b_clk_setfield(mmux->base, &mmux->mux[clk_sel], index); + return 0; +} + +const struct clk_ops cv1800b_clk_mmux_ops = { + .disable = mmux_disable, + .enable = mmux_enable, + .get_rate = mmux_get_rate, + .set_rate = mmux_set_rate, + .set_parent = mmux_set_parent, +}; + +U_BOOT_DRIVER(cv1800b_clk_mmux) = { + .name = "cv1800b_clk_mmux", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_mmux_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* AUDIO CLK */ +#define to_cv1800b_clk_audio(_clk) \ + container_of(_clk, struct cv1800b_clk_audio, clk) + +static int aclk_enable(struct clk *clk) +{ + struct cv1800b_clk_audio *aclk = to_cv1800b_clk_audio(clk); + + cv1800b_clk_setbit(aclk->base, &aclk->src_en); + cv1800b_clk_setbit(aclk->base, &aclk->output_en); + return 0; +} + +static int aclk_disable(struct clk *clk) +{ + struct cv1800b_clk_audio *aclk = to_cv1800b_clk_audio(clk); + + cv1800b_clk_clrbit(aclk->base, &aclk->src_en); + cv1800b_clk_clrbit(aclk->base, &aclk->output_en); + return 0; +} + +static ulong aclk_get_rate(struct clk *clk) +{ + struct cv1800b_clk_audio *aclk = to_cv1800b_clk_audio(clk); + u64 parent_rate = clk_get_parent_rate(clk); + u32 m, n; + + if (!cv1800b_clk_getbit(aclk->base, &aclk->div_en)) + return 0; + + m = cv1800b_clk_getfield(aclk->base, &aclk->m); + n = cv1800b_clk_getfield(aclk->base, &aclk->n); + + return DIV_ROUND_UP_ULL(n * parent_rate, m * 2); +} + +static u32 gcd(u32 a, u32 b) +{ + u32 t; + + while (b != 0) { + t = a % b; + a = b; + b = t; + } + return a; +} + +static void aclk_determine_mn(ulong parent_rate, ulong rate, u32 *m, u32 *n) +{ + u32 tm = parent_rate / 2; + u32 tn = rate; + u32 tcommon = gcd(tm, tn); + *m = tm / tcommon; + *n = tn / tcommon; +} + +static ulong aclk_set_rate(struct clk *clk, ulong rate) +{ + struct cv1800b_clk_audio *aclk = to_cv1800b_clk_audio(clk); + ulong parent_rate = clk_get_parent_rate(clk); + u32 m, n; + + aclk_determine_mn(parent_rate, rate, &m, &n); + + cv1800b_clk_setfield(aclk->base, &aclk->m, m); + cv1800b_clk_setfield(aclk->base, &aclk->n, n); + + cv1800b_clk_setbit(aclk->base, &aclk->div_en); + cv1800b_clk_setbit(aclk->base, &aclk->div_up); + + return DIV_ROUND_UP_ULL(parent_rate * n, m * 2); +} + +const struct clk_ops cv1800b_clk_audio_ops = { + .disable = aclk_disable, + .enable = aclk_enable, + .get_rate = aclk_get_rate, + .set_rate = aclk_set_rate, +}; + +U_BOOT_DRIVER(cv1800b_clk_audio) = { + .name = "cv1800b_clk_audio", + .id = UCLASS_CLK, + .ops = &cv1800b_clk_audio_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/sophgo/clk-ip.h b/drivers/clk/sophgo/clk-ip.h new file mode 100644 index 00000000000..09d15d86dc9 --- /dev/null +++ b/drivers/clk/sophgo/clk-ip.h @@ -0,0 +1,288 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + * + */ + +#ifndef __CLK_SOPHGO_IP_H__ +#define __CLK_SOPHGO_IP_H__ + +#include <clk.h> + +#include "clk-common.h" + +struct cv1800b_mmux_parent_info { + const char *name; + u8 clk_sel; + u8 index; +}; + +struct cv1800b_clk_gate { + struct clk clk; + const char *name; + const char *parent_name; + void __iomem *base; + struct cv1800b_clk_regbit gate; +}; + +struct cv1800b_clk_div { + struct clk clk; + const char *name; + const char *parent_name; + void __iomem *base; + struct cv1800b_clk_regbit gate; + struct cv1800b_clk_regfield div; + int div_init; +}; + +struct cv1800b_clk_bypass_div { + struct cv1800b_clk_div div; + struct cv1800b_clk_regbit bypass; +}; + +struct cv1800b_clk_fixed_div { + struct clk clk; + const char *name; + const char *parent_name; + void __iomem *base; + struct cv1800b_clk_regbit gate; + int div; +}; + +struct cv1800b_clk_bypass_fixed_div { + struct cv1800b_clk_fixed_div div; + struct cv1800b_clk_regbit bypass; +}; + +struct cv1800b_clk_mux { + struct clk clk; + const char *name; + const char * const *parent_names; + u8 num_parents; + void __iomem *base; + struct cv1800b_clk_regbit gate; + struct cv1800b_clk_regfield div; + int div_init; + struct cv1800b_clk_regfield mux; +}; + +struct cv1800b_clk_bypass_mux { + struct cv1800b_clk_mux mux; + struct cv1800b_clk_regbit bypass; +}; + +struct cv1800b_clk_mmux { + struct clk clk; + const char *name; + const struct cv1800b_mmux_parent_info *parent_infos; + u8 num_parents; + void __iomem *base; + struct cv1800b_clk_regbit gate; + struct cv1800b_clk_regfield div[2]; + int div_init[2]; + struct cv1800b_clk_regfield mux[2]; + struct cv1800b_clk_regbit bypass; + struct cv1800b_clk_regbit clk_sel; +}; + +struct cv1800b_clk_audio { + struct clk clk; + const char *name; + const char *parent_name; + void __iomem *base; + struct cv1800b_clk_regbit src_en; + struct cv1800b_clk_regbit output_en; + struct cv1800b_clk_regbit div_en; + struct cv1800b_clk_regbit div_up; + struct cv1800b_clk_regfield m; + struct cv1800b_clk_regfield n; +}; + +#define CV1800B_GATE(_id, _name, _parent, \ + _gate_offset, _gate_shift, \ + _flags) \ + { \ + .clk = { \ + .id = CV1800B_CLK_ID_TRANSFORM(_id), \ + .flags = _flags, \ + }, \ + .name = _name, \ + .parent_name = _parent, \ + .gate = CV1800B_CLK_REGBIT(_gate_offset, _gate_shift), \ + } + +#define CV1800B_DIV(_id, _name, _parent, \ + _gate_offset, _gate_shift, \ + _div_offset, _div_shift, _div_width, \ + _div_init, _flags) \ + { \ + .clk = { \ + .id = CV1800B_CLK_ID_TRANSFORM(_id), \ + .flags = _flags, \ + }, \ + .name = _name, \ + .parent_name = _parent, \ + .gate = CV1800B_CLK_REGBIT(_gate_offset, _gate_shift), \ + .div = CV1800B_CLK_REGFIELD(_div_offset, _div_shift, \ + _div_width), \ + .div_init = _div_init, \ + } + +#define CV1800B_BYPASS_DIV(_id, _name, _parent, \ + _gate_offset, _gate_shift, \ + _div_offset, _div_shift, \ + _div_width, _div_init, \ + _bypass_offset, _bypass_shift, \ + _flags) \ + { \ + .div = CV1800B_DIV(_id, _name, _parent, \ + _gate_offset, _gate_shift, \ + _div_offset, _div_shift, _div_width, \ + _div_init, _flags), \ + .bypass = CV1800B_CLK_REGBIT(_bypass_offset, \ + _bypass_shift), \ + } + +#define CV1800B_FIXED_DIV(_id, _name, _parent, \ + _gate_offset, _gate_shift, \ + _div, _flags) \ + { \ + .clk = { \ + .id = CV1800B_CLK_ID_TRANSFORM(_id), \ + .flags = _flags, \ + }, \ + .name = _name, \ + .parent_name = _parent, \ + .gate = CV1800B_CLK_REGBIT(_gate_offset, _gate_shift), \ + .div = _div, \ + } + +#define CV1800B_BYPASS_FIXED_DIV(_id, _name, _parent, \ + _gate_offset, _gate_shift, \ + _div, \ + _bypass_offset, _bypass_shift, \ + _flags) \ + { \ + .div = CV1800B_FIXED_DIV(_id, _name, _parent, \ + _gate_offset, _gate_shift, \ + _div, _flags), \ + .bypass = CV1800B_CLK_REGBIT(_bypass_offset, \ + _bypass_shift) \ + } + +#define CV1800B_MUX(_id, _name, _parents, \ + _gate_offset, _gate_shift, \ + _div_offset, _div_shift, _div_width, _div_init, \ + _mux_offset, _mux_shift, _mux_width, \ + _flags) \ + { \ + .clk = { \ + .id = CV1800B_CLK_ID_TRANSFORM(_id), \ + .flags = _flags, \ + }, \ + .name = _name, \ + .parent_names = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .gate = CV1800B_CLK_REGBIT(_gate_offset, _gate_shift), \ + .div = CV1800B_CLK_REGFIELD(_div_offset, _div_shift, \ + _div_width), \ + .div_init = _div_init, \ + .mux = CV1800B_CLK_REGFIELD(_mux_offset, _mux_shift, \ + _mux_width), \ + } + +#define CV1800B_BYPASS_MUX(_id, _name, _parents, \ + _gate_offset, _gate_shift, \ + _div_offset, _div_shift, \ + _div_width, _div_init, \ + _mux_offset, _mux_shift, _mux_width, \ + _bypass_offset, _bypass_shift, \ + _flags) \ + { \ + .mux = CV1800B_MUX(_id, _name, _parents, \ + _gate_offset, _gate_shift, \ + _div_offset, _div_shift, \ + _div_width, _div_init, \ + _mux_offset, _mux_shift, _mux_width, \ + _flags), \ + .bypass = CV1800B_CLK_REGBIT(_bypass_offset, \ + _bypass_shift), \ + } + +#define CV1800B_MMUX(_id, _name, _parents, \ + _gate_offset, _gate_shift, \ + _div0_offset, _div0_shift, _div0_width, _div0_init,\ + _div1_offset, _div1_shift, _div1_width, _div1_init,\ + _mux0_offset, _mux0_shift, _mux0_width, \ + _mux1_offset, _mux1_shift, _mux1_width, \ + _bypass_offset, _bypass_shift, \ + _clk_sel_offset, _clk_sel_shift, \ + _flags) \ + { \ + .clk = { \ + .id = CV1800B_CLK_ID_TRANSFORM(_id), \ + .flags = _flags, \ + }, \ + .name = _name, \ + .parent_infos = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .gate = CV1800B_CLK_REGBIT(_gate_offset, _gate_shift), \ + .div = { \ + CV1800B_CLK_REGFIELD(_div0_offset, _div0_shift, \ + _div0_width), \ + CV1800B_CLK_REGFIELD(_div1_offset, _div1_shift, \ + _div1_width), \ + }, \ + .div_init = { _div0_init, _div1_init }, \ + .mux = { \ + CV1800B_CLK_REGFIELD(_mux0_offset, _mux0_shift, \ + _mux0_width), \ + CV1800B_CLK_REGFIELD(_mux1_offset, _mux1_shift, \ + _mux1_width), \ + }, \ + .bypass = CV1800B_CLK_REGBIT(_bypass_offset, \ + _bypass_shift), \ + .clk_sel = CV1800B_CLK_REGBIT(_clk_sel_offset, \ + _clk_sel_shift), \ + } + +#define CV1800B_AUDIO(_id, _name, _parent, \ + _src_en_offset, _src_en_shift, \ + _output_en_offset, _output_en_shift, \ + _div_en_offset, _div_en_shift, \ + _div_up_offset, _div_up_shift, \ + _m_offset, _m_shift, _m_width, \ + _n_offset, _n_shift, _n_width, \ + _flags) \ + { \ + .clk = { \ + .id = CV1800B_CLK_ID_TRANSFORM(_id), \ + .flags = _flags, \ + }, \ + .name = _name, \ + .parent_name = _parent, \ + .src_en = CV1800B_CLK_REGBIT(_src_en_offset, \ + _src_en_shift), \ + .output_en = CV1800B_CLK_REGBIT(_output_en_offset, \ + _output_en_shift), \ + .div_en = CV1800B_CLK_REGBIT(_div_en_offset, \ + _div_en_shift), \ + .div_up = CV1800B_CLK_REGBIT(_div_up_offset, \ + _div_up_shift), \ + .m = CV1800B_CLK_REGFIELD(_m_offset, _m_shift, \ + _m_width), \ + .n = CV1800B_CLK_REGFIELD(_n_offset, _n_shift, \ + _n_width), \ + } + +extern const struct clk_ops cv1800b_clk_gate_ops; +extern const struct clk_ops cv1800b_clk_div_ops; +extern const struct clk_ops cv1800b_clk_bypass_div_ops; +extern const struct clk_ops cv1800b_clk_fixed_div_ops; +extern const struct clk_ops cv1800b_clk_bypass_fixed_div_ops; +extern const struct clk_ops cv1800b_clk_mux_ops; +extern const struct clk_ops cv1800b_clk_bypass_mux_ops; +extern const struct clk_ops cv1800b_clk_mmux_ops; +extern const struct clk_ops cv1800b_clk_audio_ops; + +#endif /* __CLK_SOPHGO_IP_H__ */ diff --git a/drivers/clk/sophgo/clk-pll.c b/drivers/clk/sophgo/clk-pll.c new file mode 100644 index 00000000000..c99aa0b4e44 --- /dev/null +++ b/drivers/clk/sophgo/clk-pll.c @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <div64.h> +#include <linux/bitfield.h> +#include <linux/clk-provider.h> +#include <linux/kernel.h> + +#include "clk-common.h" +#include "clk-pll.h" + +#define PLL_PRE_DIV_MIN 1 +#define PLL_PRE_DIV_MAX 127 +#define PLL_POST_DIV_MIN 1 +#define PLL_POST_DIV_MAX 127 +#define PLL_DIV_MIN 6 +#define PLL_DIV_MAX 127 +#define PLL_ICTRL_MIN 0 +#define PLL_ICTRL_MAX 7 +#define PLL_MODE_MIN 0 +#define PLL_MODE_MAX 3 +#define FOR_RANGE(x, RANGE) for (x = RANGE##_MIN; x <= RANGE##_MAX; x++) + +#define PLL_ICTRL GENMASK(26, 24) +#define PLL_DIV_SEL GENMASK(23, 17) +#define PLL_SEL_MODE GENMASK(16, 15) +#define PLL_POST_DIV_SEL GENMASK(14, 8) +#define PLL_PRE_DIV_SEL GENMASK(6, 0) +#define PLL_MASK_ALL (PLL_ICTRL | PLL_DIV_SEL | PLL_SEL_MODE | PLL_POST_DIV_SEL | PLL_PRE_DIV_SEL) + +/* IPLL */ +#define to_clk_ipll(dev) container_of(dev, struct cv1800b_clk_ipll, clk) + +static int cv1800b_ipll_enable(struct clk *clk) +{ + struct cv1800b_clk_ipll *pll = to_clk_ipll(clk); + + cv1800b_clk_clrbit(pll->base, &pll->pll_pwd); + return 0; +} + +static int cv1800b_ipll_disable(struct clk *clk) +{ + struct cv1800b_clk_ipll *pll = to_clk_ipll(clk); + + cv1800b_clk_setbit(pll->base, &pll->pll_pwd); + return 0; +} + +static ulong cv1800b_ipll_get_rate(struct clk *clk) +{ + struct cv1800b_clk_ipll *pll = to_clk_ipll(clk); + + ulong parent_rate = clk_get_parent_rate(clk); + u32 reg = readl(pll->base + pll->pll_reg); + u32 pre_div = FIELD_GET(PLL_PRE_DIV_SEL, reg); + u32 post_div = FIELD_GET(PLL_POST_DIV_SEL, reg); + u32 div = FIELD_GET(PLL_DIV_SEL, reg); + + return DIV_ROUND_DOWN_ULL(parent_rate * div, pre_div * post_div); +} + +static ulong cv1800b_ipll_set_rate(struct clk *clk, ulong rate) +{ + struct cv1800b_clk_ipll *pll = to_clk_ipll(clk); + ulong parent_rate = clk_get_parent_rate(clk); + u32 pre_div, post_div, div; + u32 pre_div_sel, post_div_sel, div_sel; + ulong new_rate, best_rate = 0; + u32 mode, ictrl; + u32 test, val; + + FOR_RANGE(pre_div, PLL_PRE_DIV) + { + FOR_RANGE(post_div, PLL_POST_DIV) + { + FOR_RANGE(div, PLL_DIV) + { + new_rate = + DIV_ROUND_DOWN_ULL(parent_rate * div, pre_div * post_div); + if (rate - new_rate < rate - best_rate) { + best_rate = new_rate; + pre_div_sel = pre_div; + post_div_sel = post_div; + div_sel = div; + } + } + } + } + + FOR_RANGE(mode, PLL_MODE) + { + FOR_RANGE(ictrl, PLL_ICTRL) + { + test = 184 * (1 + mode) * (1 + ictrl) / 2; + if (test > 20 * div_sel && test < 35 * div_sel) { + val = FIELD_PREP(PLL_PRE_DIV_SEL, pre_div_sel) | + FIELD_PREP(PLL_POST_DIV_SEL, post_div_sel) | + FIELD_PREP(PLL_DIV_SEL, div_sel) | + FIELD_PREP(PLL_ICTRL, ictrl) | + FIELD_PREP(PLL_SEL_MODE, mode); + clrsetbits_le32(pll->base + pll->pll_reg, PLL_MASK_ALL, val); + return best_rate; + } + } + } + + return -EINVAL; +} + +const struct clk_ops cv1800b_ipll_ops = { + .enable = cv1800b_ipll_enable, + .disable = cv1800b_ipll_disable, + .get_rate = cv1800b_ipll_get_rate, + .set_rate = cv1800b_ipll_set_rate, +}; + +U_BOOT_DRIVER(cv1800b_clk_ipll) = { + .name = "cv1800b_clk_ipll", + .id = UCLASS_CLK, + .ops = &cv1800b_ipll_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* FPLL */ +#define to_clk_fpll(dev) container_of(dev, struct cv1800b_clk_fpll, ipll.clk) + +static ulong cv1800b_fpll_get_rate(struct clk *clk) +{ + struct cv1800b_clk_fpll *pll = to_clk_fpll(clk); + u32 val, syn_set; + u32 pre_div, post_div, div; + u8 mult = 1; + ulong divisor, remainder, rate; + + if (!cv1800b_clk_getbit(pll->ipll.base, &pll->syn.en)) + return cv1800b_ipll_get_rate(clk); + + syn_set = readl(pll->ipll.base + pll->syn.set); + if (syn_set == 0) + return 0; + + val = readl(pll->ipll.base + pll->ipll.pll_reg); + pre_div = FIELD_GET(PLL_PRE_DIV_SEL, val); + post_div = FIELD_GET(PLL_POST_DIV_SEL, val); + div = FIELD_GET(PLL_DIV_SEL, val); + + if (cv1800b_clk_getbit(pll->ipll.base, &pll->syn.clk_half)) + mult = 2; + + divisor = (ulong)pre_div * post_div * syn_set; + rate = (clk_get_parent_rate(clk) * div) << 25; + remainder = rate % divisor; + rate /= divisor; + return rate * mult + DIV_ROUND_CLOSEST_ULL(remainder * mult, divisor); +} + +static ulong cv1800b_find_syn(ulong rate, ulong parent_rate, ulong pre_div, ulong post_div, + ulong div, u32 *syn) +{ + u32 syn_min = (4 << 26) + 1; + u32 syn_max = U32_MAX; + u32 mid; + ulong new_rate; + u32 mult = 1; + ulong divisor, remainder; + + while (syn_min < syn_max) { + mid = ((ulong)syn_min + syn_max) / 2; + divisor = pre_div * post_div * mid; + new_rate = (parent_rate * div) << 25; + remainder = do_div(new_rate, divisor); + new_rate = new_rate * mult + DIV_ROUND_CLOSEST_ULL(remainder * mult, divisor); + if (new_rate > rate) { + syn_max = mid + 1; + } else if (new_rate < rate) { + syn_min = mid - 1; + } else { + syn_min = mid; + break; + } + } + *syn = syn_min; + return new_rate; +} + +static ulong cv1800b_fpll_set_rate(struct clk *clk, ulong rate) +{ + struct cv1800b_clk_fpll *pll = to_clk_fpll(clk); + ulong parent_rate = clk_get_parent_rate(clk); + u32 pre_div, post_div, div; + u32 pre_div_sel, post_div_sel, div_sel; + u32 syn, syn_sel; + ulong new_rate, best_rate = 0; + u32 mult = 1; + u32 mode, ictrl; + + if (!cv1800b_clk_getbit(pll->ipll.base, &pll->syn.en)) + return cv1800b_ipll_set_rate(clk, rate); + + if (cv1800b_clk_getbit(pll->ipll.base, &pll->syn.clk_half)) + mult = 2; + + FOR_RANGE(pre_div, PLL_PRE_DIV) + { + FOR_RANGE(post_div, PLL_POST_DIV) + { + FOR_RANGE(div, PLL_DIV) + { + new_rate = cv1800b_find_syn(rate, parent_rate, pre_div, post_div, + div, &syn); + if (rate - new_rate < rate - best_rate) { + best_rate = new_rate; + pre_div_sel = pre_div; + post_div_sel = post_div; + div_sel = div; + syn_sel = syn; + } + } + } + } + + FOR_RANGE(mode, PLL_MODE) + { + FOR_RANGE(ictrl, PLL_ICTRL) + { + u32 test = 184 * (1 + mode) * (1 + ictrl) / 2; + + if (test > 10 * div_sel && test <= 24 * div_sel) { + u32 val = FIELD_PREP(PLL_PRE_DIV_SEL, pre_div_sel) | + FIELD_PREP(PLL_POST_DIV_SEL, post_div_sel) | + FIELD_PREP(PLL_DIV_SEL, div_sel) | + FIELD_PREP(PLL_ICTRL, ictrl) | + FIELD_PREP(PLL_SEL_MODE, mode); + clrsetbits_le32(pll->ipll.base + pll->ipll.pll_reg, PLL_MASK_ALL, + val); + writel(syn_sel, pll->ipll.base + pll->syn.set); + return best_rate; + } + } + } + + return -EINVAL; +} + +static int cv1800b_fpll_set_parent(struct clk *clk, struct clk *parent) +{ + struct cv1800b_clk_fpll *pll = to_clk_fpll(clk); + + if (parent->id == CV1800B_CLK_BYPASS) + cv1800b_clk_setbit(pll->ipll.base, &pll->syn.en); + else + cv1800b_clk_clrbit(pll->ipll.base, &pll->syn.en); + + return 0; +} + +const struct clk_ops cv1800b_fpll_ops = { + .enable = cv1800b_ipll_enable, + .disable = cv1800b_ipll_disable, + .get_rate = cv1800b_fpll_get_rate, + .set_rate = cv1800b_fpll_set_rate, + .set_parent = cv1800b_fpll_set_parent, +}; + +U_BOOT_DRIVER(cv1800b_clk_fpll) = { + .name = "cv1800b_clk_fpll", + .id = UCLASS_CLK, + .ops = &cv1800b_fpll_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/sophgo/clk-pll.h b/drivers/clk/sophgo/clk-pll.h new file mode 100644 index 00000000000..bea9bd8a437 --- /dev/null +++ b/drivers/clk/sophgo/clk-pll.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + * + */ + +#ifndef __clk_SOPHGO_PLL_H__ +#define __clk_SOPHGO_PLL_H__ + +#include <clk.h> + +#include "clk-common.h" + +struct cv1800b_clk_synthesizer { + struct cv1800b_clk_regbit en; + struct cv1800b_clk_regbit clk_half; + u32 ctrl; + u32 set; +}; + +struct cv1800b_clk_ipll { + struct clk clk; + const char *name; + const char *parent_name; + void __iomem *base; + u32 pll_reg; + struct cv1800b_clk_regbit pll_pwd; + struct cv1800b_clk_regbit pll_status; +}; + +struct cv1800b_clk_fpll { + struct cv1800b_clk_ipll ipll; + struct cv1800b_clk_synthesizer syn; +}; + +#define CV1800B_IPLL(_id, _name, _parent_name, _pll_reg, _pll_pwd_offset, \ + _pll_pwd_shift, _pll_status_offset, _pll_status_shift, \ + _flags) \ + { \ + .clk = { \ + .id = CV1800B_CLK_ID_TRANSFORM(_id), \ + .flags = _flags, \ + }, \ + .name = _name, \ + .parent_name = _parent_name, \ + .pll_reg = _pll_reg, \ + .pll_pwd = CV1800B_CLK_REGBIT(_pll_pwd_offset, _pll_pwd_shift), \ + .pll_status = CV1800B_CLK_REGBIT(_pll_status_offset, \ + _pll_status_shift), \ + } + +#define CV1800B_FPLL(_id, _name, _parent_name, _pll_reg, _pll_pwd_offset, \ + _pll_pwd_shift, _pll_status_offset, _pll_status_shift, \ + _syn_en_offset, _syn_en_shift, _syn_clk_half_offset, \ + _syn_clk_half_shift, _syn_ctrl_offset, _syn_set_offset, \ + _flags) \ + { \ + .ipll = CV1800B_IPLL(_id, _name, _parent_name, _pll_reg, \ + _pll_pwd_offset, _pll_pwd_shift, \ + _pll_status_offset, _pll_status_shift, \ + _flags), \ + .syn = { \ + .en = CV1800B_CLK_REGBIT(_syn_en_offset, _syn_en_shift),\ + .clk_half = CV1800B_CLK_REGBIT(_syn_clk_half_offset, \ + _syn_clk_half_shift), \ + .ctrl = _syn_ctrl_offset, \ + .set = _syn_set_offset, \ + }, \ + } + +extern const struct clk_ops cv1800b_ipll_ops; +extern const struct clk_ops cv1800b_fpll_ops; + +#endif /* __clk_SOPHGO_PLL_H__ */ diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 1a7be4d9b4d..c39abe3bc94 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -146,6 +146,7 @@ config DM_SEQ_ALIAS config SPL_DM_SEQ_ALIAS bool "Support numbered aliases in device tree in SPL" depends on SPL_DM + select SPL_STRTO help Most boards will have a '/aliases' node containing the path to numbered devices (e.g. serial0 = &serial0). This feature can be diff --git a/drivers/core/dump.c b/drivers/core/dump.c index 5ec30d5b3c1..5cbaa97fa31 100644 --- a/drivers/core/dump.c +++ b/drivers/core/dump.c @@ -40,7 +40,7 @@ static void show_devices(struct udevice *dev, int depth, int last_flag, /* print the first 20 characters to not break the tree-format. */ printf(CONFIG_IS_ENABLED(USE_TINY_PRINTF) ? " %s %d [ %c ] %s " : " %-10.10s %3d [ %c ] %-20.20s ", dev->uclass->uc_drv->name, - dev_get_uclass_index(dev, NULL), + dev->seq_, flags & DM_FLAG_ACTIVATED ? '+' : ' ', dev->driver->name); for (i = depth; i >= 0; i--) { @@ -129,7 +129,7 @@ void dm_dump_tree(char *dev_name, bool extended, bool sort) { struct udevice *root; - printf(" Class Index Probed Driver Name\n"); + printf(" Class Seq Probed Driver Name\n"); printf("-----------------------------------------------------------\n"); root = dm_root(); diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c index 9e59968df01..2aa58b006f1 100644 --- a/drivers/core/fdtaddr.c +++ b/drivers/core/fdtaddr.c @@ -19,11 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; -fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index) +#if CONFIG_IS_ENABLED(OF_REAL) || CONFIG_IS_ENABLED(OF_CONTROL) +fdt_addr_t devfdt_get_addr_index_parent(const struct udevice *dev, int index, + int offset, int parent) { -#if CONFIG_IS_ENABLED(OF_REAL) - int offset = dev_of_offset(dev); - int parent = fdt_parent_offset(gd->fdt_blob, offset); fdt_addr_t addr; if (CONFIG_IS_ENABLED(OF_TRANSLATE)) { @@ -89,6 +88,15 @@ fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index) #endif return addr; +} +#endif + +fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index) +{ +#if CONFIG_IS_ENABLED(OF_REAL) + int offset = dev_of_offset(dev); + int parent = fdt_parent_offset(gd->fdt_blob, offset); + return devfdt_get_addr_index_parent(dev, index, offset, parent); #else return FDT_ADDR_T_NONE; #endif @@ -113,14 +121,16 @@ fdt_addr_t devfdt_get_addr_size_index(const struct udevice *dev, int index, * next call to the exisiting dev_get_xxx function which handles * all config options. */ - fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev_of_offset(dev), - "reg", index, size, false); + int offset = dev_of_offset(dev); + int parent = fdt_parent_offset(gd->fdt_blob, offset); + fdtdec_get_addr_size_auto_parent(gd->fdt_blob, parent, offset, + "reg", index, size, false); /* * Get the base address via the existing function which handles * all Kconfig cases */ - return devfdt_get_addr_index(dev, index); + return devfdt_get_addr_index_parent(dev, index, offset, parent); #else return FDT_ADDR_T_NONE; #endif diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 4d563b47a5a..7e3b3719d18 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -762,8 +762,9 @@ static fdt_addr_t __ofnode_get_addr_size_index(ofnode node, int index, return of_read_number(prop_val, na); } } else { - na = ofnode_read_simple_addr_cells(ofnode_get_parent(node)); - ns = ofnode_read_simple_size_cells(ofnode_get_parent(node)); + ofnode parent = ofnode_get_parent(node); + na = ofnode_read_simple_addr_cells(parent); + ns = ofnode_read_simple_size_cells(parent); return fdtdec_get_addr_size_fixed(ofnode_to_fdt(node), ofnode_to_offset(node), "reg", index, na, ns, size, diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index 304d5b02bcd..5cb5fa27343 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -168,18 +168,21 @@ static int init_range(ofnode node, struct regmap_range *range, int addr_len, int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index) { + ofnode parent; struct regmap *map; int addr_len, size_len; int ret; - addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node)); + parent = ofnode_get_parent(node); + + addr_len = ofnode_read_simple_addr_cells(parent); if (addr_len < 0) { dm_warn("%s: Error while reading the addr length (ret = %d)\n", ofnode_get_name(node), addr_len); return addr_len; } - size_len = ofnode_read_simple_size_cells(ofnode_get_parent(node)); + size_len = ofnode_read_simple_size_cells(parent); if (size_len < 0) { dm_warn("%s: Error while reading the size length: (ret = %d)\n", ofnode_get_name(node), size_len); @@ -241,6 +244,7 @@ int regmap_init_mem_range(ofnode node, ulong r_start, ulong r_size, int regmap_init_mem(ofnode node, struct regmap **mapp) { + ofnode parent; struct regmap_range *range; struct regmap *map; int count; @@ -249,14 +253,16 @@ int regmap_init_mem(ofnode node, struct regmap **mapp) int index; int ret; - addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node)); + parent = ofnode_get_parent(node); + + addr_len = ofnode_read_simple_addr_cells(parent); if (addr_len < 0) { dm_warn("%s: Error while reading the addr length (ret = %d)\n", ofnode_get_name(node), addr_len); return addr_len; } - size_len = ofnode_read_simple_size_cells(ofnode_get_parent(node)); + size_len = ofnode_read_simple_size_cells(parent); if (size_len < 0) { dm_warn("%s: Error while reading the size length: (ret = %d)\n", ofnode_get_name(node), size_len); diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index b7e674f2186..e23d09e6b81 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -2118,6 +2118,9 @@ static int bcdma_tisci_tx_channel_config(struct udma_chan *uc) if (ret) dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret); + if (IS_ENABLED(CONFIG_K3_DM_FW)) + udma_alloc_tchan_raw(uc); + return ret; } @@ -2166,6 +2169,9 @@ static int pktdma_tisci_rx_channel_config(struct udma_chan *uc) dev_err(ud->dev, "flow%d config failed: %d\n", uc->rflow->id, ret); + if (IS_ENABLED(CONFIG_K3_DM_FW)) + udma_alloc_rchan_raw(uc); + return ret; } diff --git a/drivers/firmware/arm-ffa/arm-ffa-uclass.c b/drivers/firmware/arm-ffa/arm-ffa-uclass.c index e0767fc7551..96c64964bb7 100644 --- a/drivers/firmware/arm-ffa/arm-ffa-uclass.c +++ b/drivers/firmware/arm-ffa/arm-ffa-uclass.c @@ -11,7 +11,7 @@ #include <log.h> #include <malloc.h> #include <string.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <asm/global_data.h> #include <dm/device-internal.h> #include <dm/devres.h> diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index e591333ba38..719cfa771b4 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -2450,6 +2450,12 @@ fail: return ret; } +static int ti_sci_cmd_rm_udmap_rx_flow_cfg_noop(const struct ti_sci_handle *handle, + const struct ti_sci_msg_rm_udmap_flow_cfg *params) +{ + return 0; +} + /** * ti_sci_cmd_set_fwl_region() - Request for configuring a firewall region * @handle: pointer to TI SCI handle @@ -2895,7 +2901,7 @@ static __maybe_unused int ti_sci_dm_probe(struct udevice *dev) udmap_ops = &ops->rm_udmap_ops; udmap_ops->tx_ch_cfg = ti_sci_cmd_rm_udmap_tx_ch_cfg; udmap_ops->rx_ch_cfg = ti_sci_cmd_rm_udmap_rx_ch_cfg; - udmap_ops->rx_flow_cfg = ti_sci_cmd_rm_udmap_rx_flow_cfg; + udmap_ops->rx_flow_cfg = ti_sci_cmd_rm_udmap_rx_flow_cfg_noop; return ret; } diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index fcca6941ebf..3996333fe8d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -157,6 +157,13 @@ config ASPEED_GPIO is found in the AST2400, AST2500 and AST2600 BMC SoCs and provides access to over 200 GPIOs on each chip. +config ASPEED_G7_GPIO + bool "Aspeed G7 GPIO Driver" + help + Say yes here to support the Aspeed G7 GPIO driver. The controller + is found in the AST2700 BMC SoCs and provides access to over 200 + GPIOs on each chip. + config DA8XX_GPIO bool "DA8xx GPIO Driver" help @@ -301,6 +308,15 @@ config NPCM_GPIO Support GPIO controllers on Nuvovon NPCM SoCs. NPCM7xx/NPCM8xx contain 8 GPIO banks, each bank contains 32 pins. +config NPCM_SGPIO + bool "Nuvoton NPCM SGPIO driver" + depends on DM_GPIO + help + Support Nuvoton BMC NPCM7xx/NPCM8xx sgpio driver support. + Nuvoton NPCM SGPIO module is combine serial to parallel IC (HC595) + and parallel to serial IC (HC165). + BMC can use this driver to increase 64 GPI pins and 64 GPO pins to use. + config OMAP_GPIO bool "TI OMAP GPIO driver" depends on ARCH_OMAP2PLUS diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 4a293154350..da0faf05246 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_$(SPL_TPL_)DM_GPIO) += gpio-uclass.o obj-$(CONFIG_$(SPL_)DM_PCA953X) += pca953x_gpio.o obj-$(CONFIG_ASPEED_GPIO) += gpio-aspeed.o +obj-$(CONFIG_ASPEED_G7_GPIO) += gpio-aspeed-g7.o obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o @@ -27,6 +28,7 @@ obj-$(CONFIG_$(SPL_TPL_)MCP230XX_GPIO) += mcp230xx_gpio.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o obj-$(CONFIG_NPCM_GPIO) += npcm_gpio.o +obj-$(CONFIG_NPCM_SGPIO) += npcm_sgpio.o obj-$(CONFIG_PCA953X) += pca953x.o obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o diff --git a/drivers/gpio/gpio-aspeed-g7.c b/drivers/gpio/gpio-aspeed-g7.c new file mode 100644 index 00000000000..4c6ab86203c --- /dev/null +++ b/drivers/gpio/gpio-aspeed-g7.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + * Billy Tsai <billy_tsai@aspeedtech.com> + */ +#include <asm/io.h> +#include <asm/gpio.h> + +#include <config.h> +#include <clk.h> +#include <dm.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/sizes.h> + +struct aspeed_gpio_priv { + void *regs; +}; + +#define GPIO_G7_IRQ_STS_BASE 0x100 +#define GPIO_G7_IRQ_STS_OFFSET(x) (GPIO_G7_IRQ_STS_BASE + (x) * 0x4) +#define GPIO_G7_CTRL_REG_BASE 0x180 +#define GPIO_G7_CTRL_REG_OFFSET(x) (GPIO_G7_CTRL_REG_BASE + (x) * 0x4) +#define GPIO_G7_OUT_DATA BIT(0) +#define GPIO_G7_DIR BIT(1) +#define GPIO_G7_IRQ_EN BIT(2) +#define GPIO_G7_IRQ_TYPE0 BIT(3) +#define GPIO_G7_IRQ_TYPE1 BIT(4) +#define GPIO_G7_IRQ_TYPE2 BIT(5) +#define GPIO_G7_RST_TOLERANCE BIT(6) +#define GPIO_G7_DEBOUNCE_SEL GENMASK(8, 7) +#define GPIO_G7_INPUT_MASK BIT(9) +#define GPIO_G7_IRQ_STS BIT(12) +#define GPIO_G7_IN_DATA BIT(13) +/* + * The configuration of the following registers should be determined + * outside of the GPIO driver. + */ +#define GPIO_G7_PRIVILEGE_W_REG_BASE 0x810 +#define GPIO_G7_PRIVILEGE_W_REG_OFFSET(x) (GPIO_G7_PRIVILEGE_W_REG_BASE + ((x) >> 2) * 0x4) +#define GPIO_G7_PRIVILEGE_R_REG_BASE 0x910 +#define GPIO_G7_PRIVILEGE_R_REG_OFFSET(x) (GPIO_G7_PRIVILEGE_R_REG_BASE + ((x) >> 2) * 0x4) +#define GPIO_G7_IRQ_TARGET_REG_BASE 0xA10 +#define GPIO_G7_IRQ_TARGET_REG_OFFSET(x) (GPIO_G7_IRQ_TARGET_REG_BASE + ((x) >> 2) * 0x4) +#define GPIO_G7_IRQ_TO_INTC2_18 BIT(0) +#define GPIO_G7_IRQ_TO_INTC2_19 BIT(1) +#define GPIO_G7_IRQ_TO_INTC2_20 BIT(2) +#define GPIO_G7_IRQ_TO_SIO BIT(3) +#define GPIO_G7_IRQ_TARGET_RESET_TOLERANCE BIT(6) +#define GPIO_G7_IRQ_TARGET_W_PROTECT BIT(7) + +static int +aspeed_gpio_direction_input(struct udevice *dev, unsigned int offset) +{ + struct aspeed_gpio_priv *priv = dev_get_priv(dev); + void __iomem *addr = priv->regs + GPIO_G7_CTRL_REG_OFFSET(offset); + u32 dir = readl(addr); + + dir &= ~GPIO_G7_DIR; + writel(dir, addr); + + return 0; +} + +static int aspeed_gpio_direction_output(struct udevice *dev, unsigned int offset, + int value) +{ + struct aspeed_gpio_priv *priv = dev_get_priv(dev); + void __iomem *addr = priv->regs + GPIO_G7_CTRL_REG_OFFSET(offset); + u32 data = readl(addr); + + if (value) + data |= GPIO_G7_OUT_DATA; + else + data &= ~GPIO_G7_OUT_DATA; + writel(data, addr); + data |= GPIO_G7_DIR; + writel(data, addr); + + return 0; +} + +static int aspeed_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct aspeed_gpio_priv *priv = dev_get_priv(dev); + void __iomem *addr = priv->regs + GPIO_G7_CTRL_REG_OFFSET(offset); + + return !!(readl(addr) & GPIO_G7_IN_DATA); +} + +static int +aspeed_gpio_set_value(struct udevice *dev, unsigned int offset, int value) +{ + struct aspeed_gpio_priv *priv = dev_get_priv(dev); + void __iomem *addr = priv->regs + GPIO_G7_CTRL_REG_OFFSET(offset); + u32 data = readl(addr); + + if (value) + data |= GPIO_G7_OUT_DATA; + else + data &= ~GPIO_G7_OUT_DATA; + + writel(data, addr); + + return 0; +} + +static int aspeed_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct aspeed_gpio_priv *priv = dev_get_priv(dev); + void __iomem *addr = priv->regs + GPIO_G7_CTRL_REG_OFFSET(offset); + + if (readl(addr) & GPIO_G7_DIR) + return GPIOF_OUTPUT; + + return GPIOF_INPUT; +} + +static const struct dm_gpio_ops aspeed_gpio_ops = { + .direction_input = aspeed_gpio_direction_input, + .direction_output = aspeed_gpio_direction_output, + .get_value = aspeed_gpio_get_value, + .set_value = aspeed_gpio_set_value, + .get_function = aspeed_gpio_get_function, +}; + +static int aspeed_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct aspeed_gpio_priv *priv = dev_get_priv(dev); + + uc_priv->bank_name = dev->name; + ofnode_read_u32(dev_ofnode(dev), "ngpios", &uc_priv->gpio_count); + priv->regs = devfdt_get_addr_ptr(dev); + + return 0; +} + +static const struct udevice_id aspeed_gpio_ids[] = { + { .compatible = "aspeed,ast2700-gpio", }, + { } +}; + +U_BOOT_DRIVER(gpio_aspeed) = { + .name = "gpio-aspeed", + .id = UCLASS_GPIO, + .of_match = aspeed_gpio_ids, + .ops = &aspeed_gpio_ops, + .probe = aspeed_gpio_probe, + .priv_auto = sizeof(struct aspeed_gpio_priv), +}; diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index cac6b32b279..28176e15b7d 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -133,7 +133,10 @@ int gpio_get_value(unsigned gpio) regs = (struct gpio_regs *)gpio_ports[port]; - val = (readl(®s->gpio_psr) >> gpio) & 0x01; + if ((readl(®s->gpio_dir) >> gpio) & 0x01) + val = (readl(®s->gpio_dr) >> gpio) & 0x01; + else + val = (readl(®s->gpio_psr) >> gpio) & 0x01; return val; } @@ -210,7 +213,10 @@ static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset, static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset) { - return (readl(®s->gpio_psr) >> offset) & 0x01; + if ((readl(®s->gpio_dir) >> offset) & 0x01) + return (readl(®s->gpio_dr) >> offset) & 0x01; + else + return (readl(®s->gpio_psr) >> offset) & 0x01; } /* set GPIO pin 'gpio' as an input */ diff --git a/drivers/gpio/npcm_sgpio.c b/drivers/gpio/npcm_sgpio.c new file mode 100644 index 00000000000..6d73287c0a2 --- /dev/null +++ b/drivers/gpio/npcm_sgpio.c @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 Nuvoton Technology Corp. + */ + +#include <dm.h> +#include <asm/gpio.h> +#include <linux/io.h> + +#define MAX_NR_HW_SGPIO 64 +#define NPCM_CLK_MHZ 8000000 + +#define NPCM_IOXCFG1 0x2A + +#define NPCM_IOXCTS 0x28 +#define NPCM_IOXCTS_IOXIF_EN BIT(7) +#define NPCM_IOXCTS_RD_MODE GENMASK(2, 1) +#define NPCM_IOXCTS_RD_MODE_PERIODIC BIT(2) + +#define NPCM_IOXCFG2 0x2B +#define NPCM_IOXCFG2_PORT GENMASK(3, 0) + +#define GPIO_BANK(x) ((x) / 8) +#define GPIO_BIT(x) ((x) % 8) + +struct npcm_sgpio_priv { + void __iomem *base; + u32 nin_sgpio; + u32 nout_sgpio; + u32 in_port; + u32 out_port; +}; + +struct npcm_sgpio_bank { + u8 rdata_reg; + u8 wdata_reg; + u8 event_config; + u8 event_status; +}; + +enum npcm_sgpio_reg { + READ_DATA, + WRITE_DATA, + EVENT_CFG, + EVENT_STS, +}; + +static const struct npcm_sgpio_bank npcm_sgpio_banks[] = { + { + .wdata_reg = 0x00, + .rdata_reg = 0x08, + .event_config = 0x10, + .event_status = 0x20, + }, + { + .wdata_reg = 0x01, + .rdata_reg = 0x09, + .event_config = 0x12, + .event_status = 0x21, + }, + { + .wdata_reg = 0x02, + .rdata_reg = 0x0a, + .event_config = 0x14, + .event_status = 0x22, + }, + { + .wdata_reg = 0x03, + .rdata_reg = 0x0b, + .event_config = 0x16, + .event_status = 0x23, + }, + { + .wdata_reg = 0x04, + .rdata_reg = 0x0c, + .event_config = 0x18, + .event_status = 0x24, + }, + { + .wdata_reg = 0x05, + .rdata_reg = 0x0d, + .event_config = 0x1a, + .event_status = 0x25, + }, + { + .wdata_reg = 0x06, + .rdata_reg = 0x0e, + .event_config = 0x1c, + .event_status = 0x26, + }, + { + .wdata_reg = 0x07, + .rdata_reg = 0x0f, + .event_config = 0x1e, + .event_status = 0x27, + }, +}; + +static void __iomem *bank_reg(struct npcm_sgpio_priv *gpio, + const struct npcm_sgpio_bank *bank, + const enum npcm_sgpio_reg reg) +{ + switch (reg) { + case READ_DATA: + return gpio->base + bank->rdata_reg; + case WRITE_DATA: + return gpio->base + bank->wdata_reg; + case EVENT_CFG: + return gpio->base + bank->event_config; + case EVENT_STS: + return gpio->base + bank->event_status; + default: + /* actually if code runs to here, it's an error case */ + printf("Getting here is an error condition\n"); + return NULL; + } +} + +static const struct npcm_sgpio_bank *offset_to_bank(unsigned int offset) +{ + unsigned int bank = GPIO_BANK(offset); + + return &npcm_sgpio_banks[bank]; +} + +static int npcm_sgpio_direction_input(struct udevice *dev, unsigned int offset) +{ + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + + if (offset < priv->nout_sgpio) { + printf("Error: Offset %d is a output pin\n", offset); + return -EINVAL; + } + + return 0; +} + +static int npcm_sgpio_direction_output(struct udevice *dev, unsigned int offset, + int value) +{ + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + const struct npcm_sgpio_bank *bank = offset_to_bank(offset); + void __iomem *addr; + u8 reg = 0; + + if (offset >= priv->nout_sgpio) { + printf("Error: Offset %d is a input pin\n", offset); + return -EINVAL; + } + + addr = bank_reg(priv, bank, WRITE_DATA); + reg = ioread8(addr); + + if (value) + reg |= BIT(GPIO_BIT(offset)); + else + reg &= ~BIT(GPIO_BIT(offset)); + + iowrite8(reg, addr); + + return 0; +} + +static int npcm_sgpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + const struct npcm_sgpio_bank *bank; + void __iomem *addr; + u8 reg; + + if (offset < priv->nout_sgpio) { + bank = offset_to_bank(offset); + addr = bank_reg(priv, bank, WRITE_DATA); + } else { + offset -= priv->nout_sgpio; + bank = offset_to_bank(offset); + addr = bank_reg(priv, bank, READ_DATA); + } + + reg = ioread8(addr); + + return !!(reg & BIT(GPIO_BIT(offset))); +} + +static int npcm_sgpio_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + return npcm_sgpio_direction_output(dev, offset, value); +} + +static int npcm_sgpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + + if (offset < priv->nout_sgpio) + return GPIOF_OUTPUT; + + return GPIOF_INPUT; +} + +static void npcm_sgpio_setup_enable(struct npcm_sgpio_priv *gpio, bool enable) +{ + u8 reg; + + reg = ioread8(gpio->base + NPCM_IOXCTS); + reg = (reg & ~NPCM_IOXCTS_RD_MODE) | NPCM_IOXCTS_RD_MODE_PERIODIC; + + if (enable) + reg |= NPCM_IOXCTS_IOXIF_EN; + else + reg &= ~NPCM_IOXCTS_IOXIF_EN; + + iowrite8(reg, gpio->base + NPCM_IOXCTS); +} + +static int npcm_sgpio_init_port(struct udevice *dev) +{ + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + u8 in_port, out_port, set_port, reg, set_clk; + + npcm_sgpio_setup_enable(priv, false); + + in_port = GPIO_BANK(priv->nin_sgpio); + if (GPIO_BIT(priv->nin_sgpio) > 0) + in_port += 1; + + out_port = GPIO_BANK(priv->nout_sgpio); + if (GPIO_BIT(priv->nout_sgpio) > 0) + out_port += 1; + + priv->in_port = in_port; + priv->out_port = out_port; + + set_port = (out_port & NPCM_IOXCFG2_PORT) << 4 | (in_port & NPCM_IOXCFG2_PORT); + set_clk = 0x07; + + iowrite8(set_port, priv->base + NPCM_IOXCFG2); + iowrite8(set_clk, priv->base + NPCM_IOXCFG1); + + reg = ioread8(priv->base + NPCM_IOXCFG2); + + return reg == set_port ? 0 : -EINVAL; +} + +static const struct dm_gpio_ops npcm_sgpio_ops = { + .direction_input = npcm_sgpio_direction_input, + .direction_output = npcm_sgpio_direction_output, + .get_value = npcm_sgpio_get_value, + .set_value = npcm_sgpio_set_value, + .get_function = npcm_sgpio_get_function, +}; + +static int npcm_sgpio_probe(struct udevice *dev) +{ + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + int rc; + + priv->base = dev_read_addr_ptr(dev); + ofnode_read_u32(dev_ofnode(dev), "nuvoton,input-ngpios", &priv->nin_sgpio); + ofnode_read_u32(dev_ofnode(dev), "nuvoton,output-ngpios", &priv->nout_sgpio); + + if (priv->nin_sgpio > MAX_NR_HW_SGPIO || priv->nout_sgpio > MAX_NR_HW_SGPIO) + return -EINVAL; + + rc = npcm_sgpio_init_port(dev); + if (rc < 0) + return rc; + + uc_priv->gpio_count = priv->nin_sgpio + priv->nout_sgpio; + uc_priv->bank_name = dev->name; + + npcm_sgpio_setup_enable(priv, true); + + return 0; +} + +static const struct udevice_id npcm_sgpio_match[] = { + { .compatible = "nuvoton,npcm845-sgpio" }, + { .compatible = "nuvoton,npcm750-sgpio" }, + { } +}; + +U_BOOT_DRIVER(npcm_sgpio) = { + .name = "npcm_sgpio", + .id = UCLASS_GPIO, + .of_match = npcm_sgpio_match, + .probe = npcm_sgpio_probe, + .priv_auto = sizeof(struct npcm_sgpio_priv), + .ops = &npcm_sgpio_ops, +}; diff --git a/drivers/iommu/apple_dart.c b/drivers/iommu/apple_dart.c index 9327dea1e3b..611ac7cd6de 100644 --- a/drivers/iommu/apple_dart.c +++ b/drivers/iommu/apple_dart.c @@ -70,7 +70,6 @@ struct apple_dart_priv { void *base; - struct lmb lmb; u64 *l1, *l2; int bypass, shift; @@ -124,7 +123,7 @@ static dma_addr_t apple_dart_map(struct udevice *dev, void *addr, size_t size) off = (phys_addr_t)addr - paddr; psize = ALIGN(size + off, DART_PAGE_SIZE); - dva = lmb_alloc(&priv->lmb, psize, DART_PAGE_SIZE); + dva = lmb_alloc(psize, DART_PAGE_SIZE); idx = dva / DART_PAGE_SIZE; for (i = 0; i < psize / DART_PAGE_SIZE; i++) { @@ -160,7 +159,7 @@ static void apple_dart_unmap(struct udevice *dev, dma_addr_t addr, size_t size) (unsigned long)&priv->l2[idx + i]); priv->flush_tlb(priv); - lmb_free(&priv->lmb, dva, psize); + lmb_free(dva, psize); } static struct iommu_ops apple_dart_ops = { @@ -213,8 +212,7 @@ static int apple_dart_probe(struct udevice *dev) priv->dvabase = DART_PAGE_SIZE; priv->dvaend = SZ_4G - DART_PAGE_SIZE; - lmb_init(&priv->lmb); - lmb_add(&priv->lmb, priv->dvabase, priv->dvaend - priv->dvabase); + lmb_add(priv->dvabase, priv->dvaend - priv->dvabase); /* Disable translations. */ for (sid = 0; sid < priv->nsid; sid++) diff --git a/drivers/iommu/qcom-hyp-smmu.c b/drivers/iommu/qcom-hyp-smmu.c index 7b646d840dd..1b5a09bb7b3 100644 --- a/drivers/iommu/qcom-hyp-smmu.c +++ b/drivers/iommu/qcom-hyp-smmu.c @@ -381,6 +381,7 @@ static struct iommu_ops qcom_smmu_ops = { static const struct udevice_id qcom_smmu500_ids[] = { { .compatible = "qcom,sdm845-smmu-500" }, + { .compatible = "qcom,sc7280-smmu-500" }, { .compatible = "qcom,smmu-500", }, { /* sentinel */ } }; diff --git a/drivers/iommu/sandbox_iommu.c b/drivers/iommu/sandbox_iommu.c index e37976f86f0..c5eefec2185 100644 --- a/drivers/iommu/sandbox_iommu.c +++ b/drivers/iommu/sandbox_iommu.c @@ -5,28 +5,20 @@ #include <dm.h> #include <iommu.h> -#include <lmb.h> #include <asm/io.h> +#include <asm/test.h> #include <linux/sizes.h> -#define IOMMU_PAGE_SIZE SZ_4K - -struct sandbox_iommu_priv { - struct lmb lmb; -}; - static dma_addr_t sandbox_iommu_map(struct udevice *dev, void *addr, size_t size) { - struct sandbox_iommu_priv *priv = dev_get_priv(dev); phys_addr_t paddr, dva; phys_size_t psize, off; - paddr = ALIGN_DOWN(virt_to_phys(addr), IOMMU_PAGE_SIZE); + paddr = ALIGN_DOWN(virt_to_phys(addr), SANDBOX_IOMMU_PAGE_SIZE); off = virt_to_phys(addr) - paddr; - psize = ALIGN(size + off, IOMMU_PAGE_SIZE); - - dva = lmb_alloc(&priv->lmb, psize, IOMMU_PAGE_SIZE); + psize = ALIGN(size + off, SANDBOX_IOMMU_PAGE_SIZE); + dva = (phys_addr_t)SANDBOX_IOMMU_DVA_ADDR; return dva + off; } @@ -34,15 +26,12 @@ static dma_addr_t sandbox_iommu_map(struct udevice *dev, void *addr, static void sandbox_iommu_unmap(struct udevice *dev, dma_addr_t addr, size_t size) { - struct sandbox_iommu_priv *priv = dev_get_priv(dev); phys_addr_t dva; phys_size_t psize; - dva = ALIGN_DOWN(addr, IOMMU_PAGE_SIZE); + dva = ALIGN_DOWN(addr, SANDBOX_IOMMU_PAGE_SIZE); psize = size + (addr - dva); - psize = ALIGN(psize, IOMMU_PAGE_SIZE); - - lmb_free(&priv->lmb, dva, psize); + psize = ALIGN(psize, SANDBOX_IOMMU_PAGE_SIZE); } static struct iommu_ops sandbox_iommu_ops = { @@ -50,16 +39,6 @@ static struct iommu_ops sandbox_iommu_ops = { .unmap = sandbox_iommu_unmap, }; -static int sandbox_iommu_probe(struct udevice *dev) -{ - struct sandbox_iommu_priv *priv = dev_get_priv(dev); - - lmb_init(&priv->lmb); - lmb_add(&priv->lmb, 0x89abc000, SZ_16K); - - return 0; -} - static const struct udevice_id sandbox_iommu_ids[] = { { .compatible = "sandbox,iommu" }, { /* sentinel */ } @@ -69,7 +48,5 @@ U_BOOT_DRIVER(sandbox_iommu) = { .name = "sandbox_iommu", .id = UCLASS_IOMMU, .of_match = sandbox_iommu_ids, - .priv_auto = sizeof(struct sandbox_iommu_priv), .ops = &sandbox_iommu_ops, - .probe = sandbox_iommu_probe, }; diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index 3745504637b..b753419f01b 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -1,11 +1,13 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright 2020, 2023 NXP + * Copyright 2024 Mathieu Othacehe <othacehe@gnu.org> * */ #include <hang.h> #include <malloc.h> +#include <memalign.h> #include <asm/io.h> #include <dm.h> #include <asm/mach-imx/ele_api.h> @@ -527,6 +529,81 @@ int ele_start_rng(void) return ret; } +int ele_derive_huk(u8 *key, size_t key_size, u8 *seed, size_t seed_size) +{ + struct udevice *dev = gd->arch.ele_dev; + struct ele_msg msg; + int msg_size = sizeof(struct ele_msg); + u8 *seed_aligned, *key_aligned; + int ret, size; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + if (key_size != 16 && key_size != 32) { + printf("key size can only be 16 or 32\n"); + return -EINVAL; + } + + if (seed_size >= (1U << 16) - 1) { + printf("seed size is too large\n"); + return -EINVAL; + } + + seed_aligned = memalign(ARCH_DMA_MINALIGN, seed_size); + if (!seed_aligned) { + printf("failed to alloc memory\n"); + return -EINVAL; + } + memcpy(seed_aligned, seed, seed_size); + + key_aligned = memalign(ARCH_DMA_MINALIGN, key_size); + if (!key_aligned) { + printf("failed to alloc memory\n"); + ret = -EINVAL; + goto ret_seed; + } + + size = ALIGN(seed_size, ARCH_DMA_MINALIGN); + flush_dcache_range((ulong)seed_aligned, + (ulong)seed_aligned + size); + + size = ALIGN(key_size, ARCH_DMA_MINALIGN); + invalidate_dcache_range((ulong)key_aligned, + (ulong)key_aligned + size); + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 7; + msg.command = ELE_CMD_DERIVE_KEY; + msg.data[0] = upper_32_bits((ulong)key_aligned); + msg.data[1] = lower_32_bits((ulong)key_aligned); + msg.data[2] = upper_32_bits((ulong)seed_aligned); + msg.data[3] = lower_32_bits((ulong)seed_aligned); + msg.data[4] = seed_size << 16 | key_size; + msg.data[5] = compute_crc(&msg); + + ret = misc_call(dev, false, &msg, msg_size, &msg, msg_size); + if (ret) { + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + goto ret_key; + } + + invalidate_dcache_range((ulong)key_aligned, + (ulong)key_aligned + size); + memcpy(key, key_aligned, key_size); + +ret_key: + free(key_aligned); +ret_seed: + free(seed_aligned); + + return ret; +} + int ele_commit(u16 fuse_id, u32 *response, u32 *info_type) { struct udevice *dev = gd->arch.ele_dev; diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 72c3fb66ce0..235c477c2e0 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -60,6 +60,7 @@ obj-$(CONFIG_MMC_SDHCI_ATMEL) += atmel_sdhci.o obj-$(CONFIG_MMC_SDHCI_BCM2835) += bcm2835_sdhci.o obj-$(CONFIG_MMC_SDHCI_BCMSTB) += bcmstb_sdhci.o obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o +obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence6.o obj-$(CONFIG_MMC_SDHCI_CV1800B) += cv1800b_sdhci.o obj-$(CONFIG_MMC_SDHCI_AM654) += am654_sdhci.o obj-$(CONFIG_MMC_SDHCI_IPROC) += iproc_sdhci.o diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index cf8277cbed8..7e702c3ae85 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -30,6 +30,41 @@ #define DEFAULT_CMD6_TIMEOUT_MS 500 +/** + * names of emmc BOOT_PARTITION_ENABLE values + * + * Boot Area Partitions - name consistent with Linux + */ +const char *emmc_boot_part_names[] = { + "default", /* EMMC_BOOT_PART_DEFAULT */ + "boot0", /* EMMC_BOOT_PART_BOOT1 */ + "boot1", /* EMMC_BOOT_PART_BOOT2 */ + "", + "", + "", + "", + "user", /* EMMC_BOOT_PART_USER */ +}; + +/** + * names of emmc 'hardware partitions' consistent with: + * - value used in mmc_switch() + * - value used by PARTITION_CONFIG PARTITION_ACCESS field + * + * Boot Area Partitions - name consistent with Linux + * General Perpose Partitions - name consistent with 'mmc hwpartition' usage + */ +const char *emmc_hwpart_names[] = { + "user", /* EMMC_HWPART_DEFAULT */ + "boot0", /* EMMC_HWPART_BOOT1 */ + "boot1", /* EMMC_HWPART_BOOT2 */ + "rpmb", /* EMMC_HWPART_RPMB */ + "gp1", /* EMMC_HWPART_GP1 */ + "gp2", /* EMMC_HWPART_GP2 */ + "gp3", /* EMMC_HWPART_GP3 */ + "gp4", /* EMMC_HWPART_GP4 */ +}; + static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage); #if !CONFIG_IS_ENABLED(DM_MMC) @@ -294,7 +329,7 @@ int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms) if (status & MMC_STATUS_MASK) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - pr_err("Status Error: 0x%08x\n", status); + log_err("Status Error: %#08x\n", status); #endif return -ECOMM; } @@ -307,7 +342,7 @@ int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms) if (timeout_ms <= 0) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - pr_err("Timeout waiting card ready\n"); + log_err("Timeout waiting card ready\n"); #endif return -ETIMEDOUT; } @@ -449,7 +484,7 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, if (blkcnt > 1) { if (mmc_send_stop_transmission(mmc, false)) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - pr_err("mmc fail to send stop cmd\n"); + log_err("mmc fail to send stop cmd\n"); #endif return 0; } @@ -500,8 +535,8 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, if ((start + blkcnt) > block_dev->lba) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", - start + blkcnt, block_dev->lba); + log_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", + start + blkcnt, block_dev->lba); #endif return 0; } @@ -962,8 +997,8 @@ static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode, * Extended CSD. Reconfigure the controller to run at HS mode. */ if (hsdowngrade) { - mmc_select_mode(mmc, MMC_HS); - mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false); + mmc_select_mode(mmc, MMC_HS_52); + mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS_52), false); } #endif @@ -996,7 +1031,7 @@ static int mmc_get_capabilities(struct mmc *mmc) return 0; if (!ext_csd) { - pr_err("No ext_csd found!\n"); /* this should enver happen */ + log_err("No ext_csd found!\n"); /* this should never happen */ return -ENOTSUPP; } @@ -1108,17 +1143,17 @@ int mmc_hwpart_config(struct mmc *mmc, return -EINVAL; if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { - pr_err("eMMC >= 4.4 required for enhanced user data area\n"); + log_err("eMMC >= 4.4 required for enhanced user data area\n"); return -EMEDIUMTYPE; } if (!(mmc->part_support & PART_SUPPORT)) { - pr_err("Card does not support partitioning\n"); + log_err("Card does not support partitioning\n"); return -EMEDIUMTYPE; } if (!mmc->hc_wp_grp_size) { - pr_err("Card does not define HC WP group size\n"); + log_err("Card does not define HC WP group size\n"); return -EMEDIUMTYPE; } @@ -1126,8 +1161,7 @@ int mmc_hwpart_config(struct mmc *mmc, if (conf->user.enh_size) { if (conf->user.enh_size % mmc->hc_wp_grp_size || conf->user.enh_start % mmc->hc_wp_grp_size) { - pr_err("User data enhanced area not HC WP group " - "size aligned\n"); + log_err("User data enhanced area not HC WP group size aligned\n"); return -EINVAL; } part_attrs |= EXT_CSD_ENH_USR; @@ -1145,8 +1179,8 @@ int mmc_hwpart_config(struct mmc *mmc, for (pidx = 0; pidx < 4; pidx++) { if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { - pr_err("GP%i partition not HC WP group size " - "aligned\n", pidx+1); + log_err("GP%i partition not HC WP group-size aligned\n", + pidx + 1); return -EINVAL; } gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; @@ -1157,7 +1191,7 @@ int mmc_hwpart_config(struct mmc *mmc, } if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { - pr_err("Card does not support enhanced attribute\n"); + log_err("Card does not support enhanced attribute\n"); return -EMEDIUMTYPE; } @@ -1170,8 +1204,8 @@ int mmc_hwpart_config(struct mmc *mmc, (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; if (tot_enh_size_mult > max_enh_size_mult) { - pr_err("Total enhanced size exceeds maximum (%u > %u)\n", - tot_enh_size_mult, max_enh_size_mult); + log_err("Total enhanced size exceeds maximum (%#x > %#x)\n", + tot_enh_size_mult, max_enh_size_mult); return -EMEDIUMTYPE; } @@ -1204,7 +1238,7 @@ int mmc_hwpart_config(struct mmc *mmc, if (ext_csd[EXT_CSD_PARTITION_SETTING] & EXT_CSD_PARTITION_SETTING_COMPLETED) { - pr_err("Card already partitioned\n"); + log_err("Card already partitioned\n"); return -EPERM; } @@ -1875,7 +1909,7 @@ error: } } - pr_err("unable to select a mode\n"); + log_err("unable to select a mode\n"); return -ENOTSUPP; } @@ -2043,7 +2077,7 @@ static int mmc_select_hs400(struct mmc *mmc) } /* Set back to HS */ - mmc_set_card_speed(mmc, MMC_HS, true); + mmc_set_card_speed(mmc, MMC_HS_52, true); err = mmc_hs400_prepare_ddr(mmc); if (err) @@ -2253,7 +2287,7 @@ error: } } - pr_err("unable to select a mode : %d\n", err); + log_err("unable to select a mode: %d\n", err); return -ENOTSUPP; } @@ -2921,7 +2955,8 @@ retry: if (err) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) if (!quiet) - pr_err("Card did not respond to voltage select! : %d\n", err); + log_err("Card did not respond to voltage select! : %d\n", + err); #endif return -EOPNOTSUPP; } @@ -2954,7 +2989,7 @@ int mmc_start_init(struct mmc *mmc) | MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT); } else { - pr_err("bus_mode requested is not supported\n"); + log_err("bus_mode requested is not supported\n"); return -EINVAL; } } @@ -2974,7 +3009,7 @@ int mmc_start_init(struct mmc *mmc) if (no_card) { mmc->has_init = 0; #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - pr_err("MMC: no card present\n"); + log_err("MMC: no card present\n"); #endif return -ENOMEDIUM; } @@ -3103,7 +3138,7 @@ static int mmc_probe(struct bd_info *bis) uclass_foreach_dev(dev, uc) { ret = device_probe(dev); if (ret) - pr_err("%s - probe failed: %d\n", dev->name, ret); + log_err("%s - probe failed: %d\n", dev->name, ret); } return 0; diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index f5e9930c799..4e5c932c071 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -32,6 +32,8 @@ #define SDCC_MCI_STATUS2_MCI_ACT 0x1 #define SDCC_MCI_HC_MODE 0x78 +#define CORE_VENDOR_SPEC_POR_VAL 0xa9c + struct msm_sdhc_plat { struct mmc_config cfg; struct mmc mmc; @@ -46,6 +48,7 @@ struct msm_sdhc { struct msm_sdhc_variant_info { bool mci_removed; + u32 core_vendor_spec; u32 core_vendor_spec_capabilities0; }; @@ -54,11 +57,14 @@ DECLARE_GLOBAL_DATA_PTR; static int msm_sdc_clk_init(struct udevice *dev) { struct msm_sdhc *prv = dev_get_priv(dev); + const struct msm_sdhc_variant_info *var_info; ofnode node = dev_ofnode(dev); ulong clk_rate; int ret, i = 0, n_clks; const char *clk_name; + var_info = (void *)dev_get_driver_data(dev); + ret = ofnode_read_u32(node, "clock-frequency", (uint *)(&clk_rate)); if (ret) clk_rate = 201500000; @@ -105,6 +111,9 @@ static int msm_sdc_clk_init(struct udevice *dev) return -EINVAL; } + writel_relaxed(CORE_VENDOR_SPEC_POR_VAL, + prv->host.ioaddr + var_info->core_vendor_spec); + return 0; } @@ -254,12 +263,14 @@ static int msm_sdc_bind(struct udevice *dev) static const struct msm_sdhc_variant_info msm_sdhc_mci_var = { .mci_removed = false, + .core_vendor_spec = 0x10c, .core_vendor_spec_capabilities0 = 0x11c, }; static const struct msm_sdhc_variant_info msm_sdhc_v5_var = { .mci_removed = true, + .core_vendor_spec = 0x20c, .core_vendor_spec_capabilities0 = 0x21c, }; diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index 07ec35a0463..7d169efa476 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -16,56 +16,7 @@ #include <linux/libfdt.h> #include <mmc.h> #include <sdhci.h> - -/* HRS - Host Register Set (specific to Cadence) */ -#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */ -#define SDHCI_CDNS_HRS04_ACK BIT(26) -#define SDHCI_CDNS_HRS04_RD BIT(25) -#define SDHCI_CDNS_HRS04_WR BIT(24) -#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16) -#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8) -#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0) - -#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */ -#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) -#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8) -#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0) -#define SDHCI_CDNS_HRS06_MODE_SD 0x0 -#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2 -#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3 -#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4 -#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 -#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6 - -/* SRS - Slot Register Set (SDHCI-compatible) */ -#define SDHCI_CDNS_SRS_BASE 0x200 - -/* PHY */ -#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00 -#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01 -#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02 -#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03 -#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04 -#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05 -#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06 -#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07 -#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08 -#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b -#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c -#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d - -/* - * The tuned val register is 6 bit-wide, but not the whole of the range is - * available. The range 0-42 seems to be available (then 43 wraps around to 0) - * but I am not quite sure if it is official. Use only 0 to 39 for safety. - */ -#define SDHCI_CDNS_MAX_TUNING_LOOP 40 - -struct sdhci_cdns_plat { - struct mmc_config cfg; - struct mmc mmc; - void __iomem *hrs_addr; -}; +#include "sdhci-cadence.h" struct sdhci_cdns_phy_cfg { const char *property; @@ -162,6 +113,9 @@ static void sdhci_cdns_set_control_reg(struct sdhci_host *host) tmp &= ~SDHCI_CDNS_HRS06_MODE; tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06); + + if (device_is_compatible(mmc->dev, "cdns,sd6hc")) + sdhci_cdns6_phy_adj(mmc->dev, plat, mode); } static const struct sdhci_ops sdhci_cdns_ops = { @@ -175,6 +129,9 @@ static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat, u32 tmp; int i, ret; + if (device_is_compatible(plat->mmc.dev, "cdns,sd6hc")) + return sdhci_cdns6_set_tune_val(plat, val); + if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val))) return -EINVAL; @@ -281,7 +238,10 @@ static int sdhci_cdns_probe(struct udevice *dev) if (ret) return ret; - ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev)); + if (device_is_compatible(dev, "cdns,sd6hc")) + ret = sdhci_cdns6_phy_init(dev, plat); + else + ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev)); if (ret) return ret; @@ -300,6 +260,7 @@ static int sdhci_cdns_probe(struct udevice *dev) static const struct udevice_id sdhci_cdns_match[] = { { .compatible = "socionext,uniphier-sd4hc" }, { .compatible = "cdns,sd4hc" }, + { .compatible = "cdns,sd6hc" }, { /* sentinel */ } }; diff --git a/drivers/mmc/sdhci-cadence.h b/drivers/mmc/sdhci-cadence.h new file mode 100644 index 00000000000..7101f00b75b --- /dev/null +++ b/drivers/mmc/sdhci-cadence.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + */ + +#ifndef SDHCI_CADENCE_H_ +#define SDHCI_CADENCE_H_ + +/* HRS - Host Register Set (specific to Cadence) */ +/* PHY access port */ +#define SDHCI_CDNS_HRS04 0x10 +/* Cadence V4 HRS04 Description*/ +#define SDHCI_CDNS_HRS04_ACK BIT(26) +#define SDHCI_CDNS_HRS04_RD BIT(25) +#define SDHCI_CDNS_HRS04_WR BIT(24) +#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16) +#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8) +#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0) + +#define SDHCI_CDNS_HRS05 0x14 + +/* eMMC control */ +#define SDHCI_CDNS_HRS06 0x18 +#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) +#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8) +#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0) +#define SDHCI_CDNS_HRS06_MODE_SD 0x0 +#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2 +#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6 + +/* SRS - Slot Register Set (SDHCI-compatible) */ +#define SDHCI_CDNS_SRS_BASE 0x200 + +/* Cadence V4 PHY Setting*/ +#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00 +#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01 +#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02 +#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03 +#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04 +#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05 +#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06 +#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07 +#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08 +#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b +#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c +#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d + +/* + * The tuned val register is 6 bit-wide, but not the whole of the range is + * available. The range 0-42 seems to be available (then 43 wraps around to 0) + * but I am not quite sure if it is official. Use only 0 to 39 for safety. + */ +#define SDHCI_CDNS_MAX_TUNING_LOOP 40 + +struct sdhci_cdns_plat { + struct mmc_config cfg; + struct mmc mmc; + void __iomem *hrs_addr; +}; + +int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 mode); +int sdhci_cdns6_phy_init(struct udevice *dev, struct sdhci_cdns_plat *plat); +int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val); + +#endif diff --git a/drivers/mmc/sdhci-cadence6.c b/drivers/mmc/sdhci-cadence6.c new file mode 100644 index 00000000000..a5ed87321ab --- /dev/null +++ b/drivers/mmc/sdhci-cadence6.c @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: GPL-2.0-or-platform_driver +/* + * Copyright (C) 2023 Starfive. + * Author: Kuan Lim Lee <kuanlim.lee@starfivetech.com> + */ + +#include <dm.h> +#include <asm/global_data.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/bug.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/sizes.h> +#include <linux/libfdt.h> +#include <mmc.h> +#include <sdhci.h> +#include "sdhci-cadence.h" + +/* IO Delay Information */ +#define SDHCI_CDNS_HRS07 0X1C +#define SDHCI_CDNS_HRS07_RW_COMPENSATE GENMASK(20, 16) +#define SDHCI_CDNS_HRS07_IDELAY_VAL GENMASK(4, 0) + +/* PHY Control and Status */ +#define SDHCI_CDNS_HRS09 0x24 +#define SDHCI_CDNS_HRS09_RDDATA_EN BIT(16) +#define SDHCI_CDNS_HRS09_RDCMD_EN BIT(15) +#define SDHCI_CDNS_HRS09_EXTENDED_WR_MODE BIT(3) +#define SDHCI_CDNS_HRS09_EXTENDED_RD_MODE BIT(2) +#define SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE BIT(1) +#define SDHCI_CDNS_HRS09_PHY_SW_RESET BIT(0) + +/* SDCLK adjustment */ +#define SDHCI_CDNS_HRS10 0x28 +#define SDHCI_CDNS_HRS10_HCSDCLKADJ GENMASK(19, 16) + +/* CMD/DAT output delay */ +#define SDHCI_CDNS_HRS16 0x40 + +/* PHY Special Function Registers */ +/* register to control the DQ related timing */ +#define PHY_DQ_TIMING_REG_ADDR 0x2000 + +/* register to control the DQS related timing */ +#define PHY_DQS_TIMING_REG_ADDR 0x2004 + +/* register to control the gate and loopback control related timing */ +#define PHY_GATE_LPBK_CTRL_REG_ADDR 0x2008 + +/* register to control the Master DLL logic */ +#define PHY_DLL_MASTER_CTRL_REG_ADDR 0x200C + +/* register to control the Slave DLL logic */ +#define PHY_DLL_SLAVE_CTRL_REG_ADDR 0x2010 +#define PHY_DLL_SLAVE_CTRL_REG_READ_DQS_CMD_DELAY GENMASK(31, 24) +#define PHY_DLL_SLAVE_CTRL_REG_READ_DQS_DELAY GENMASK(7, 0) + +#define SDHCI_CDNS6_PHY_CFG_NUM 4 +#define SDHCI_CDNS6_CTRL_CFG_NUM 4 + +struct sdhci_cdns6_phy_cfg { + const char *property; + u32 val; +}; + +struct sdhci_cdns6_ctrl_cfg { + const char *property; + u32 val; +}; + +static struct sdhci_cdns6_phy_cfg sd_ds_phy_cfgs[] = { + { "cdns,phy-dqs-timing-delay-sd-ds", 0x00380004, }, + { "cdns,phy-gate-lpbk_ctrl-delay-sd-ds", 0x01A00040, }, + { "cdns,phy-dll-slave-ctrl-sd-ds", 0x00000000, }, + { "cdns,phy-dq-timing-delay-sd-ds", 0x00000001, }, +}; + +static struct sdhci_cdns6_phy_cfg emmc_sdr_phy_cfgs[] = { + { "cdns,phy-dqs-timing-delay-semmc-sdr", 0x00380004, }, + { "cdns,phy-gate-lpbk_ctrl-delay-emmc-sdr", 0x01A00040, }, + { "cdns,phy-dll-slave-ctrl-emmc-sdr", 0x00000000, }, + { "cdns,phy-dq-timing-delay-emmc-sdr", 0x00000001, }, +}; + +static struct sdhci_cdns6_phy_cfg emmc_ddr_phy_cfgs[] = { + { "cdns,phy-dqs-timing-delay-emmc-ddr", 0x00380004, }, + { "cdns,phy-gate-lpbk_ctrl-delay-emmc-ddr", 0x01A00040, }, + { "cdns,phy-dll-slave-ctrl-emmc-ddr", 0x00000000, }, + { "cdns,phy-dq-timing-delay-emmc-ddr", 0x10000001, }, +}; + +static struct sdhci_cdns6_phy_cfg emmc_hs200_phy_cfgs[] = { + { "cdns,phy-dqs-timing-delay-emmc-hs200", 0x00380004, }, + { "cdns,phy-gate-lpbk_ctrl-delay-emmc-hs200", 0x01A00040, }, + { "cdns,phy-dll-slave-ctrl-emmc-hs200", 0x00DADA00, }, + { "cdns,phy-dq-timing-delay-emmc-hs200", 0x00000001, }, +}; + +static struct sdhci_cdns6_phy_cfg emmc_hs400_phy_cfgs[] = { + { "cdns,phy-dqs-timing-delay-emmc-hs400", 0x00280004, }, + { "cdns,phy-gate-lpbk_ctrl-delay-emmc-hs400", 0x01A00040, }, + { "cdns,phy-dll-slave-ctrl-emmc-hs400", 0x00DAD800, }, + { "cdns,phy-dq-timing-delay-emmc-hs400", 0x00000001, }, +}; + +static struct sdhci_cdns6_ctrl_cfg sd_ds_ctrl_cfgs[] = { + { "cdns,ctrl-hrs09-timing-delay-sd-ds", 0x0001800C, }, + { "cdns,ctrl-hrs10-lpbk_ctrl-delay-sd-ds", 0x00020000, }, + { "cdns,ctrl-hrs16-slave-ctrl-sd-ds", 0x00000000, }, + { "cdns,ctrl-hrs07-timing-delay-sd-ds", 0x00080000, }, +}; + +static struct sdhci_cdns6_ctrl_cfg emmc_sdr_ctrl_cfgs[] = { + { "cdns,ctrl-hrs09-timing-delay-emmc-sdr", 0x0001800C, }, + { "cdns,ctrl-hrs10-lpbk_ctrl-delay-emmc-sdr", 0x00030000, }, + { "cdns,ctrl-hrs16-slave-ctrl-emmc-sdr", 0x00000000, }, + { "cdns,ctrl-hrs07-timing-delay-emmc-sdr", 0x00080000, }, +}; + +static struct sdhci_cdns6_ctrl_cfg emmc_ddr_ctrl_cfgs[] = { + { "cdns,ctrl-hrs09-timing-delay-emmc-ddr", 0x0001800C, }, + { "cdns,ctrl-hrs10-lpbk_ctrl-delay-emmc-ddr", 0x00020000, }, + { "cdns,ctrl-hrs16-slave-ctrl-emmc-ddr", 0x11000001, }, + { "cdns,ctrl-hrs07-timing-delay-emmc-ddr", 0x00090001, }, +}; + +static struct sdhci_cdns6_ctrl_cfg emmc_hs200_ctrl_cfgs[] = { + { "cdns,ctrl-hrs09-timing-delay-emmc-hs200", 0x00018000, }, + { "cdns,ctrl-hrs10-lpbk_ctrl-delay-emmc-hs200", 0x00080000, }, + { "cdns,ctrl-hrs16-slave-ctrl-emmc-hs200", 0x00000000, }, + { "cdns,ctrl-hrs07-timing-delay-emmc-hs200", 0x00090000, }, +}; + +static struct sdhci_cdns6_ctrl_cfg emmc_hs400_ctrl_cfgs[] = { + { "cdns,ctrl-hrs09-timing-delay-emmc-hs400", 0x00018000, }, + { "cdns,ctrl-hrs10-lpbk_ctrl-delay-emmc-hs400", 0x00080000, }, + { "cdns,ctrl-hrs16-slave-ctrl-emmc-hs400", 0x11000000, }, + { "cdns,ctrl-hrs07-timing-delay-emmc-hs400", 0x00080000, }, +}; + +static u32 sdhci_cdns6_read_phy_reg(struct sdhci_cdns_plat *plat, u32 addr) +{ + writel(addr, plat->hrs_addr + SDHCI_CDNS_HRS04); + return readl(plat->hrs_addr + SDHCI_CDNS_HRS05); +} + +static void sdhci_cdns6_write_phy_reg(struct sdhci_cdns_plat *plat, u32 addr, u32 val) +{ + writel(addr, plat->hrs_addr + SDHCI_CDNS_HRS04); + writel(val, plat->hrs_addr + SDHCI_CDNS_HRS05); +} + +static int sdhci_cdns6_reset_phy_dll(struct sdhci_cdns_plat *plat, bool reset) +{ + void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS09; + u32 tmp; + int ret; + + tmp = readl(reg); + tmp &= ~SDHCI_CDNS_HRS09_PHY_SW_RESET; + + /* Switch On DLL Reset */ + if (reset) + tmp |= FIELD_PREP(SDHCI_CDNS_HRS09_PHY_SW_RESET, 0); + else + tmp |= FIELD_PREP(SDHCI_CDNS_HRS09_PHY_SW_RESET, 1); + + writel(tmp, reg); + + /* After reset, wait until HRS09.PHY_INIT_COMPLETE is set to 1 within 3000us*/ + if (!reset) { + ret = readl_poll_timeout(reg, tmp, (tmp & SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE), + 3000); + } + + return ret; +} + +int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 mode) +{ + DECLARE_GLOBAL_DATA_PTR; + struct sdhci_cdns6_phy_cfg *sdhci_cdns6_phy_cfgs; + struct sdhci_cdns6_ctrl_cfg *sdhci_cdns6_ctrl_cfgs; + const fdt32_t *prop; + u32 tmp; + int i, ret; + + switch (mode) { + case SDHCI_CDNS_HRS06_MODE_SD: + sdhci_cdns6_phy_cfgs = sd_ds_phy_cfgs; + sdhci_cdns6_ctrl_cfgs = sd_ds_ctrl_cfgs; + break; + + case SDHCI_CDNS_HRS06_MODE_MMC_SDR: + sdhci_cdns6_phy_cfgs = emmc_sdr_phy_cfgs; + sdhci_cdns6_ctrl_cfgs = emmc_sdr_ctrl_cfgs; + break; + + case SDHCI_CDNS_HRS06_MODE_MMC_DDR: + sdhci_cdns6_phy_cfgs = emmc_ddr_phy_cfgs; + sdhci_cdns6_ctrl_cfgs = emmc_ddr_ctrl_cfgs; + break; + + case SDHCI_CDNS_HRS06_MODE_MMC_HS200: + sdhci_cdns6_phy_cfgs = emmc_hs200_phy_cfgs; + sdhci_cdns6_ctrl_cfgs = emmc_hs200_ctrl_cfgs; + break; + + case SDHCI_CDNS_HRS06_MODE_MMC_HS400: + sdhci_cdns6_phy_cfgs = emmc_hs400_phy_cfgs; + sdhci_cdns6_ctrl_cfgs = emmc_hs400_ctrl_cfgs; + break; + default: + return -EINVAL; + } + + for (i = 0; i < SDHCI_CDNS6_PHY_CFG_NUM; i++) { + prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), + sdhci_cdns6_phy_cfgs[i].property, NULL); + if (prop) + sdhci_cdns6_phy_cfgs[i].val = *prop; + } + + for (i = 0; i < SDHCI_CDNS6_CTRL_CFG_NUM; i++) { + prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), + sdhci_cdns6_ctrl_cfgs[i].property, NULL); + if (prop) + sdhci_cdns6_ctrl_cfgs[i].val = *prop; + } + + /* Switch On the DLL Reset */ + sdhci_cdns6_reset_phy_dll(plat, true); + + sdhci_cdns6_write_phy_reg(plat, PHY_DQS_TIMING_REG_ADDR, sdhci_cdns6_phy_cfgs[0].val); + sdhci_cdns6_write_phy_reg(plat, PHY_GATE_LPBK_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[1].val); + sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[2].val); + + /* Switch Off the DLL Reset */ + ret = sdhci_cdns6_reset_phy_dll(plat, false); + if (ret) { + printf("sdhci_cdns6_reset_phy is not completed\n"); + return ret; + } + + /* Set PHY DQ TIMING control register */ + sdhci_cdns6_write_phy_reg(plat, PHY_DQ_TIMING_REG_ADDR, sdhci_cdns6_phy_cfgs[3].val); + + /* Set HRS09 register */ + tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS09); + tmp &= ~(SDHCI_CDNS_HRS09_EXTENDED_WR_MODE | + SDHCI_CDNS_HRS09_EXTENDED_RD_MODE | + SDHCI_CDNS_HRS09_RDDATA_EN | + SDHCI_CDNS_HRS09_RDCMD_EN); + tmp |= sdhci_cdns6_ctrl_cfgs[0].val; + writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS09); + + /* Set HRS10 register */ + tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS10); + tmp &= ~SDHCI_CDNS_HRS10_HCSDCLKADJ; + tmp |= sdhci_cdns6_ctrl_cfgs[1].val; + writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS10); + + /* Set HRS16 register */ + writel(sdhci_cdns6_ctrl_cfgs[2].val, plat->hrs_addr + SDHCI_CDNS_HRS16); + + /* Set HRS07 register */ + writel(sdhci_cdns6_ctrl_cfgs[3].val, plat->hrs_addr + SDHCI_CDNS_HRS07); + + return 0; +} + +int sdhci_cdns6_phy_init(struct udevice *dev, struct sdhci_cdns_plat *plat) +{ + return sdhci_cdns6_phy_adj(dev, plat, SDHCI_CDNS_HRS06_MODE_SD); +} + +int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val) +{ + u32 tmp, tuneval; + + tuneval = (val * 256) / SDHCI_CDNS_MAX_TUNING_LOOP; + + tmp = sdhci_cdns6_read_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR); + tmp &= ~(PHY_DLL_SLAVE_CTRL_REG_READ_DQS_CMD_DELAY | + PHY_DLL_SLAVE_CTRL_REG_READ_DQS_DELAY); + tmp |= FIELD_PREP(PHY_DLL_SLAVE_CTRL_REG_READ_DQS_CMD_DELAY, tuneval) | + FIELD_PREP(PHY_DLL_SLAVE_CTRL_REG_READ_DQS_DELAY, tuneval); + sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, tmp); + + return 0; +} diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 560b7e889c7..4833b5158c7 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -32,8 +32,7 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask) sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { if (timeout == 0) { - printf("%s: Reset 0x%x never completed.\n", - __func__, (int)mask); + log_warning("Reset %#x never completed\n", mask); return; } timeout--; @@ -139,8 +138,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data) do { stat = sdhci_readl(host, SDHCI_INT_STATUS); if (stat & SDHCI_INT_ERROR) { - pr_debug("%s: Error detected in status(0x%X)!\n", - __func__, stat); + log_debug("Error detected in status(%#x)!\n", stat); return -EIO; } if (!transfer_done && (stat & rdy)) { @@ -173,7 +171,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data) if (timeout-- > 0) udelay(10); else { - printf("%s: Transfer data timeout\n", __func__); + log_err("Transfer data timeout\n"); return -ETIMEDOUT; } } while (!(stat & SDHCI_INT_DATA_END)); @@ -232,13 +230,13 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { if (time >= cmd_timeout) { - printf("%s: MMC: %d busy ", __func__, mmc_dev); + log_warning("mmc%d busy ", mmc_dev); if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) { cmd_timeout += cmd_timeout; - printf("timeout increasing to: %u ms.\n", - cmd_timeout); + log_warning("timeout increasing to: %u ms\n", + cmd_timeout); } else { - puts("timeout.\n"); + log_warning("timeout\n"); return -ECOMM; } } @@ -316,8 +314,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, } if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { - printf("%s: Timeout for status update: %08x %08x\n", - __func__, stat, mask); + log_warning("Timeout for status update: %08x %08x\n", + stat, mask); return -ETIMEDOUT; } } while ((stat & mask) != mask); @@ -358,7 +356,7 @@ static int sdhci_execute_tuning(struct udevice *dev, uint opcode) struct mmc *mmc = mmc_get_mmc_dev(dev); struct sdhci_host *host = mmc->priv; - debug("%s\n", __func__); + log_debug("sdhci tuning\n"); if (host->ops && host->ops->platform_execute_tuning) { err = host->ops->platform_execute_tuning(mmc, opcode); @@ -380,8 +378,7 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int clock) while (sdhci_readl(host, SDHCI_PRESENT_STATE) & (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { if (timeout == 0) { - printf("%s: Timeout to wait cmd & data inhibit\n", - __func__); + log_err("Timeout waiting for cmd & data inhibit\n"); return -EBUSY; } @@ -397,7 +394,7 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int clock) if (host->ops && host->ops->set_delay) { ret = host->ops->set_delay(host); if (ret) { - printf("%s: Error while setting tap delay\n", __func__); + log_err("Error while setting tap delay\n"); return ret; } } @@ -405,7 +402,7 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int clock) if (host->ops && host->ops->config_dll) { ret = host->ops->config_dll(host, clock, false); if (ret) { - printf("%s: Error while configuring dll\n", __func__); + log_err("Error configuring dll\n"); return ret; } } @@ -456,7 +453,7 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int clock) if (host->ops && host->ops->config_dll) { ret = host->ops->config_dll(host, clock, true); if (ret) { - printf("%s: Error while configuring dll\n", __func__); + log_err("Error while configuring dll\n"); return ret; } } @@ -472,8 +469,7 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int clock) while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) & SDHCI_CLOCK_INT_STABLE)) { if (timeout == 0) { - printf("%s: Internal clock never stabilised.\n", - __func__); + log_err("Internal clock never stabilised.\n"); return -EBUSY; } timeout--; @@ -738,8 +734,7 @@ static int sdhci_init(struct mmc *mmc) if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) { host->align_buffer = memalign(8, 512 * 1024); if (!host->align_buffer) { - printf("%s: Aligned buffer alloc failed!!!\n", - __func__); + log_err("Aligned buffer alloc failed\n"); return -ENOMEM; } } @@ -881,20 +876,18 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, #else caps = sdhci_readl(host, SDHCI_CAPABILITIES); #endif - debug("%s, caps: 0x%x\n", __func__, caps); + log_debug("caps: %#x\n", caps); #if CONFIG_IS_ENABLED(MMC_SDHCI_SDMA) if ((caps & SDHCI_CAN_DO_SDMA)) { host->flags |= USE_SDMA; } else { - debug("%s: Your controller doesn't support SDMA!!\n", - __func__); + log_debug("Controller doesn't support SDMA\n"); } #endif #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA) if (!(caps & SDHCI_CAN_DO_ADMA2)) { - printf("%s: Your controller doesn't support ADMA!!\n", - __func__); + log_err("Controller doesn't support ADMA\n"); return -EINVAL; } if (!host->adma_desc_table) { @@ -927,7 +920,7 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, #else caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); #endif - debug("%s, caps_1: 0x%x\n", __func__, caps_1); + log_debug("caps_1: %#x\n", caps_1); host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; @@ -953,8 +946,7 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, host->max_clk *= host->clk_mul; } if (host->max_clk == 0) { - printf("%s: Hardware doesn't specify base clock frequency\n", - __func__); + log_err("Hardware doesn't specify base clock frequency\n"); return -EINVAL; } if (f_max && (f_max < host->max_clk)) @@ -1047,7 +1039,7 @@ int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min) host->mmc = mmc_create(&host->cfg, host); if (host->mmc == NULL) { - printf("%s: mmc create fail!\n", __func__); + log_err("mmc create fail\n"); return -ENOMEM; } diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c index f30331e51f7..47ab5654bd6 100644 --- a/drivers/mmc/snps_dw_mmc.c +++ b/drivers/mmc/snps_dw_mmc.c @@ -12,6 +12,7 @@ #include <dwmmc.h> #include <errno.h> #include <fdtdec.h> +#include <asm/gpio.h> #include <dm/device_compat.h> #include <linux/libfdt.h> #include <linux/err.h> @@ -29,6 +30,7 @@ struct snps_dwmci_plat { struct snps_dwmci_priv_data { struct dwmci_host host; u32 f_max; + struct gpio_desc cd_gpio; }; static int snps_dwmmc_clk_setup(struct udevice *dev) @@ -104,6 +106,10 @@ static int snps_dwmmc_of_to_plat(struct udevice *dev) if (!ret && priv->f_max < CLOCK_MIN) return -EINVAL; + if (CONFIG_IS_ENABLED(DM_GPIO)) + gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, + GPIOD_IS_IN); + host->fifo_mode = dev_read_bool(dev, "fifo-mode"); host->name = dev->name; host->dev_index = 0; @@ -117,6 +123,9 @@ int snps_dwmmc_getcd(struct udevice *dev) struct snps_dwmci_priv_data *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; + if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&priv->cd_gpio)) + return dm_gpio_get_value(&priv->cd_gpio); + return !(dwmci_readl(host, DWMCI_CDETECT) & 1); } diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c index 12499a79478..28c851f103b 100644 --- a/drivers/mtd/nand/raw/meson_nand.c +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -39,6 +39,7 @@ #define NFC_CMD_RB BIT(20) #define NFC_CMD_SCRAMBLER_ENABLE BIT(19) #define NFC_CMD_SCRAMBLER_DISABLE 0 +#define NFC_CMD_SHORTMODE_ENABLE 1 #define NFC_CMD_SHORTMODE_DISABLE 0 #define NFC_CMD_RB_INT BIT(14) #define NFC_CMD_RB_INT_NO_PIN ((0xb << 10) | BIT(18) | BIT(16)) @@ -77,6 +78,8 @@ #define DMA_DIR(dir) ((dir) ? NFC_CMD_N2M : NFC_CMD_M2N) +#define NFC_SHORT_MODE_ECC_SZ 384 + #define ECC_CHECK_RETURN_FF -1 #define NAND_CE0 (0xe << 10) @@ -140,6 +143,8 @@ struct meson_nfc_nand_chip { struct list_head node; struct nand_chip nand; + u32 boot_pages; + u32 boot_page_step; u32 bch_mode; u8 *data_buf; @@ -228,28 +233,49 @@ static void meson_nfc_cmd_seed(const struct meson_nfc *nfc, u32 seed) nfc->reg_base + NFC_REG_CMD); } -static void meson_nfc_cmd_access(struct nand_chip *nand, bool raw, bool dir, - int scrambler) +static int meson_nfc_is_boot_page(struct nand_chip *nand, int page) +{ + const struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); + + return (nand->options & NAND_IS_BOOT_MEDIUM) && + !(page % meson_chip->boot_page_step) && + (page < meson_chip->boot_pages); +} + +static void meson_nfc_cmd_access(struct nand_chip *nand, bool raw, bool dir, int page) { + const struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); struct mtd_info *mtd = nand_to_mtd(nand); const struct meson_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd)); - const struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); - u32 bch = meson_chip->bch_mode, cmd; int len = mtd->writesize, pagesize, pages; + unsigned int scrambler; + u32 cmd; - pagesize = nand->ecc.size; + if (nand->options & NAND_NEED_SCRAMBLING) + scrambler = NFC_CMD_SCRAMBLER_ENABLE; + else + scrambler = NFC_CMD_SCRAMBLER_DISABLE; if (raw) { len = mtd->writesize + mtd->oobsize; cmd = len | scrambler | DMA_DIR(dir); - writel(cmd, nfc->reg_base + NFC_REG_CMD); - return; - } + } else if (meson_nfc_is_boot_page(nand, page)) { + pagesize = NFC_SHORT_MODE_ECC_SZ >> 3; + pages = mtd->writesize / 512; + + scrambler = NFC_CMD_SCRAMBLER_ENABLE; + cmd = CMDRWGEN(DMA_DIR(dir), scrambler, NFC_ECC_BCH8_1K, + NFC_CMD_SHORTMODE_ENABLE, pagesize, pages); + } else { + pagesize = nand->ecc.size >> 3; + pages = len / nand->ecc.size; - pages = len / nand->ecc.size; + cmd = CMDRWGEN(DMA_DIR(dir), scrambler, meson_chip->bch_mode, + NFC_CMD_SHORTMODE_DISABLE, pagesize, pages); + } - cmd = CMDRWGEN(DMA_DIR(dir), scrambler, bch, - NFC_CMD_SHORTMODE_DISABLE, pagesize, pages); + if (scrambler == NFC_CMD_SCRAMBLER_ENABLE) + meson_nfc_cmd_seed(nfc, page); writel(cmd, nfc->reg_base + NFC_REG_CMD); } @@ -565,14 +591,7 @@ static int meson_nfc_write_page_sub(struct nand_chip *nand, return ret; } - if (nand->options & NAND_NEED_SCRAMBLING) { - meson_nfc_cmd_seed(nfc, page); - meson_nfc_cmd_access(nand, raw, DIRWRITE, - NFC_CMD_SCRAMBLER_ENABLE); - } else { - meson_nfc_cmd_access(nand, raw, DIRWRITE, - NFC_CMD_SCRAMBLER_DISABLE); - } + meson_nfc_cmd_access(nand, raw, DIRWRITE, page); cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_PAGEPROG; writel(cmd, nfc->reg_base + NFC_REG_CMD); @@ -643,14 +662,7 @@ static int meson_nfc_read_page_sub(struct nand_chip *nand, if (ret) return ret; - if (nand->options & NAND_NEED_SCRAMBLING) { - meson_nfc_cmd_seed(nfc, page); - meson_nfc_cmd_access(nand, raw, DIRREAD, - NFC_CMD_SCRAMBLER_ENABLE); - } else { - meson_nfc_cmd_access(nand, raw, DIRREAD, - NFC_CMD_SCRAMBLER_DISABLE); - } + meson_nfc_cmd_access(nand, raw, DIRREAD, page); meson_nfc_wait_dma_finish(nfc); meson_nfc_check_ecc_pages_valid(nfc, nand, raw); @@ -1137,6 +1149,24 @@ static int meson_nfc_nand_chip_init(struct udevice *dev, struct meson_nfc *nfc, goto err_chip_buf_free; } + if (nand->options & NAND_IS_BOOT_MEDIUM) { + ret = ofnode_read_u32(node, "amlogic,boot-pages", + &meson_chip->boot_pages); + if (ret) { + dev_err(dev, "could not retrieve 'amlogic,boot-pages' property: %d", + ret); + goto err_chip_buf_free; + } + + ret = ofnode_read_u32(node, "amlogic,boot-page-step", + &meson_chip->boot_page_step); + if (ret) { + dev_err(dev, "could not retrieve 'amlogic,boot-page-step' property: %d", + ret); + goto err_chip_buf_free; + } + } + ret = nand_register(0, mtd); if (ret) { dev_err(dev, "'nand_register()' failed: %d\n", ret); diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 4401bdcdb90..0545c23e268 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4454,6 +4454,9 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode nod if (ret == 16) chip->options |= NAND_BUSWIDTH_16; + if (ofnode_read_bool(node, "nand-is-boot-medium")) + chip->options |= NAND_IS_BOOT_MEDIUM; + if (ofnode_read_bool(node, "nand-on-flash-bbt")) chip->bbt_options |= NAND_BBT_USE_FLASH; diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 92a92ad63a0..a36e2a148cc 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -1188,7 +1188,10 @@ static int gpmc_nand_probe(struct udevice *dev) return ret; base = devm_ioremap(dev, res.start, resource_size(&res)); - gpmc_nand_init(nand, base); + ret = gpmc_nand_init(nand, base); + if (ret) + return ret; + mtd->dev = dev; nand_set_flash_node(nand, dev_ofnode(dev)); diff --git a/drivers/mtd/ubi/fastmap.c b/drivers/mtd/ubi/fastmap.c index 21750e1817b..9c6b15b8cb5 100644 --- a/drivers/mtd/ubi/fastmap.c +++ b/drivers/mtd/ubi/fastmap.c @@ -581,13 +581,11 @@ static int count_fastmap_pebs(struct ubi_attach_info *ai) struct ubi_ainf_peb *aeb; struct ubi_ainf_volume *av; struct rb_node *rb1, *rb2; - int n = 0; + int n; - list_for_each_entry(aeb, &ai->erase, u.list) - n++; + n = list_count_nodes(&ai->erase); - list_for_each_entry(aeb, &ai->free, u.list) - n++; + n += list_count_nodes(&ai->free); ubi_rb_for_each_entry(rb1, av, &ai->volumes, rb) ubi_rb_for_each_entry(rb2, aeb, &av->root, u.rb) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 69ae7c07508..6ed325517c0 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -243,6 +243,13 @@ config DWC_ETH_QOS_IMX The Synopsys Designware Ethernet QOS IP block with the specific configuration used in IMX soc. +config DWC_ETH_QOS_INTEL + bool "Synopsys DWC Ethernet QOS device support for Intel" + depends on DWC_ETH_QOS + help + The Synopsys Designware Ethernet QOS IP block with the specific + configuration used in the Intel Elkhart-Lake soc. + config DWC_ETH_QOS_ROCKCHIP bool "Synopsys DWC Ethernet QOS device support for Rockchip SoCs" depends on DWC_ETH_QOS diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 425dd721f9d..4946a63f80f 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o +obj-$(CONFIG_DWC_ETH_QOS_INTEL) += dwc_eth_qos_intel.o obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o obj-$(CONFIG_DWC_ETH_XGMAC) += dwc_eth_xgmac.o diff --git a/drivers/net/aspeed_mdio.c b/drivers/net/aspeed_mdio.c index f2e4392aa9a..2e1f3cdf11a 100644 --- a/drivers/net/aspeed_mdio.c +++ b/drivers/net/aspeed_mdio.c @@ -113,6 +113,7 @@ static int aspeed_mdio_probe(struct udevice *dev) static const struct udevice_id aspeed_mdio_ids[] = { { .compatible = "aspeed,ast2600-mdio" }, + { .compatible = "aspeed,ast2700-mdio" }, { } }; diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 43f0ec7637d..3415c418a93 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -32,6 +32,7 @@ #include <clk.h> #include <cpu_func.h> #include <dm.h> +#include <dm/device_compat.h> #include <errno.h> #include <eth_phy.h> #include <log.h> @@ -1301,6 +1302,13 @@ static int eqos_probe_resources_tegra186(struct udevice *dev) debug("%s(dev=%p):\n", __func__, dev); + ret = eqos_get_base_addr_dt(dev); + if (ret) { + pr_err("eqos_get_base_addr_dt failed: %d\n", ret); + return ret; + } + eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE); + ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl); if (ret) { pr_err("reset_get_by_name(rst) failed: %d\n", ret); @@ -1375,6 +1383,69 @@ static int eqos_remove_resources_tegra186(struct udevice *dev) return 0; } +static int eqos_bind(struct udevice *dev) +{ + static int dev_num; + const size_t name_sz = 16; + char name[name_sz]; + + /* Device name defaults to DT node name. */ + if (ofnode_valid(dev_ofnode(dev))) + return 0; + + /* Assign unique names in case there is no DT node. */ + snprintf(name, name_sz, "eth_eqos#%d", dev_num++); + return device_set_name(dev, name); +} + +/* + * Get driver data based on the device tree. Boards not using a device tree can + * overwrite this function. + */ +__weak void *eqos_get_driver_data(struct udevice *dev) +{ + return (void *)dev_get_driver_data(dev); +} + +static fdt_addr_t eqos_get_base_addr_common(struct udevice *dev, fdt_addr_t addr) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + if (addr == FDT_ADDR_T_NONE) { +#if CONFIG_IS_ENABLED(FDT_64BIT) + dev_err(dev, "addr=0x%llx is invalid.\n", addr); +#else + dev_err(dev, "addr=0x%x is invalid.\n", addr); +#endif + return -EINVAL; + } + + eqos->regs = addr; + eqos->mac_regs = (void *)(addr + EQOS_MAC_REGS_BASE); + eqos->mtl_regs = (void *)(addr + EQOS_MTL_REGS_BASE); + eqos->dma_regs = (void *)(addr + EQOS_DMA_REGS_BASE); + + return 0; +} + +int eqos_get_base_addr_dt(struct udevice *dev) +{ + fdt_addr_t addr = dev_read_addr(dev); + return eqos_get_base_addr_common(dev, addr); +} + +int eqos_get_base_addr_pci(struct udevice *dev) +{ + fdt_addr_t addr; + void *paddr; + + paddr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, + PCI_REGION_MEM); + addr = paddr ? (fdt_addr_t)paddr : FDT_ADDR_T_NONE; + + return eqos_get_base_addr_common(dev, addr); +} + static int eqos_probe(struct udevice *dev) { struct eqos_priv *eqos = dev_get_priv(dev); @@ -1383,17 +1454,12 @@ static int eqos_probe(struct udevice *dev) debug("%s(dev=%p):\n", __func__, dev); eqos->dev = dev; - eqos->config = (void *)dev_get_driver_data(dev); - eqos->regs = dev_read_addr(dev); - if (eqos->regs == FDT_ADDR_T_NONE) { - pr_err("dev_read_addr() failed\n"); + eqos->config = eqos_get_driver_data(dev); + if (!eqos->config) { + pr_err("Failed to get driver data.\n"); return -ENODEV; } - eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE); - eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE); - eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE); - eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE); eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0); @@ -1574,6 +1640,7 @@ U_BOOT_DRIVER(eth_eqos) = { .name = "eth_eqos", .id = UCLASS_ETH, .of_match = of_match_ptr(eqos_ids), + .bind = eqos_bind, .probe = eqos_probe, .remove = eqos_remove, .ops = &eqos_ops, diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index a06390a6982..ce57e22a81f 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -3,8 +3,11 @@ * Copyright 2022 NXP */ -#include <phy_interface.h> +#include <asm/gpio.h> +#include <clk.h> #include <linux/bitops.h> +#include <phy_interface.h> +#include <reset.h> /* Core registers */ @@ -286,7 +289,10 @@ void eqos_inval_desc_generic(void *desc); void eqos_flush_desc_generic(void *desc); void eqos_inval_buffer_generic(void *buf, size_t size); void eqos_flush_buffer_generic(void *buf, size_t size); +int eqos_get_base_addr_dt(struct udevice *dev); +int eqos_get_base_addr_pci(struct udevice *dev); int eqos_null_ops(struct udevice *dev); +void *eqos_get_driver_data(struct udevice *dev); extern struct eqos_config eqos_imx_config; extern struct eqos_config eqos_rockchip_config; diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c index d6bed278ca7..642432834f5 100644 --- a/drivers/net/dwc_eth_qos_imx.c +++ b/drivers/net/dwc_eth_qos_imx.c @@ -47,6 +47,12 @@ static int eqos_probe_resources_imx(struct udevice *dev) debug("%s(dev=%p):\n", __func__, dev); + ret = eqos_get_base_addr_dt(dev); + if (ret) { + dev_dbg(dev, "eqos_get_base_addr_dt failed: %d", ret); + goto err_probe; + } + interface = eqos->config->interface(dev); if (interface == PHY_INTERFACE_MODE_NA) { diff --git a/drivers/net/dwc_eth_qos_intel.c b/drivers/net/dwc_eth_qos_intel.c new file mode 100644 index 00000000000..a2c68257329 --- /dev/null +++ b/drivers/net/dwc_eth_qos_intel.c @@ -0,0 +1,449 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023-2024 DENX Software Engineering GmbH + * Philip Oberfichtner <pro@denx.de> + * + * Based on linux v6.6.39, especially drivers/net/ethernet/stmicro/stmmac + */ + +#include <asm/io.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <miiphy.h> +#include <net.h> +#include <pci.h> + +#include "dwc_eth_qos.h" +#include "dwc_eth_qos_intel.h" + +static struct pci_device_id intel_pci_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_RGMII1G) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_SGMII1) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_SGMII2G5) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5) }, + {} +}; + +static int pci_config(struct udevice *dev) +{ + u32 val; + + /* Try to enable I/O accesses and bus-mastering */ + dm_pci_read_config32(dev, PCI_COMMAND, &val); + val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + dm_pci_write_config32(dev, PCI_COMMAND, val); + + /* Make sure it worked */ + dm_pci_read_config32(dev, PCI_COMMAND, &val); + if (!(val & PCI_COMMAND_MEMORY)) { + dev_err(dev, "%s: Can't enable I/O memory\n", __func__); + return -ENOSPC; + } + + if (!(val & PCI_COMMAND_MASTER)) { + dev_err(dev, "%s: Can't enable bus-mastering\n", __func__); + return -EPERM; + } + + return 0; +} + +static void limit_fifo_size(struct udevice *dev) +{ + /* + * As described in Intel Erratum EHL22, Document Number: 636674-2.1, + * the PSE GbE Controllers advertise a wrong RX and TX fifo size. + * Software should limit this value to 64KB. + */ + struct eqos_priv *eqos = dev_get_priv(dev); + + eqos->tx_fifo_sz = 0x8000; + eqos->rx_fifo_sz = 0x8000; +} + +static int serdes_status_poll(struct udevice *dev, + unsigned char phyaddr, unsigned char phyreg, + unsigned short mask, unsigned short val) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + unsigned int retries = 10; + unsigned short val_rd; + + do { + miiphy_read(eqos->mii->name, phyaddr, phyreg, &val_rd); + if ((val_rd & mask) == (val & mask)) + return 0; + udelay(POLL_DELAY_US); + } while (--retries); + + return -ETIMEDOUT; +} + + /* Returns -ve if MAC is unknown and 0 on success */ +static int mac_check_pse(const struct udevice *dev, bool *is_pse) +{ + struct pci_child_plat *plat = dev_get_parent_plat(dev); + + if (!plat || plat->vendor != PCI_VENDOR_ID_INTEL) + return -ENXIO; + + switch (plat->device) { + case PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5: + *is_pse = 1; + return 0; + + case PCI_DEVICE_ID_INTEL_EHL_RGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_SGMII1: + case PCI_DEVICE_ID_INTEL_EHL_SGMII2G5: + *is_pse = 0; + return 0; + }; + + return -ENXIO; +} + +/* Check if we're in 2G5 mode */ +static bool serdes_link_mode_2500(struct udevice *dev) +{ + const unsigned char phyad = INTEL_MGBE_ADHOC_ADDR; + struct eqos_priv *eqos = dev_get_priv(dev); + unsigned short data; + + miiphy_read(eqos->mii->name, phyad, SERDES_GCR, &data); + if (FIELD_GET(SERDES_LINK_MODE_MASK, data) == SERDES_LINK_MODE_2G5) + return true; + + return false; +} + +static int serdes_powerup(struct udevice *dev) +{ + /* Based on linux/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c */ + + const unsigned char phyad = INTEL_MGBE_ADHOC_ADDR; + struct eqos_priv *eqos = dev_get_priv(dev); + unsigned short data; + int ret; + bool is_pse; + + /* Set the serdes rate and the PCLK rate */ + miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data); + + data &= ~SERDES_RATE_MASK; + data &= ~SERDES_PCLK_MASK; + + if (serdes_link_mode_2500(dev)) + data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT | + SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT; + else + data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT | + SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT; + + miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data); + + /* assert clk_req */ + miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data); + data |= SERDES_PLL_CLK; + miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data); + + /* check for clk_ack assertion */ + ret = serdes_status_poll(dev, phyad, SERDES_GSR0, + SERDES_PLL_CLK, SERDES_PLL_CLK); + + if (ret) { + dev_err(dev, "Serdes PLL clk request timeout\n"); + return ret; + } + + /* assert lane reset*/ + miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data); + data |= SERDES_RST; + miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data); + + /* check for assert lane reset reflection */ + ret = serdes_status_poll(dev, phyad, SERDES_GSR0, + SERDES_RST, SERDES_RST); + + if (ret) { + dev_err(dev, "Serdes assert lane reset timeout\n"); + return ret; + } + + /* move power state to P0 */ + miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data); + data &= ~SERDES_PWR_ST_MASK; + data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT; + miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data); + + /* Check for P0 state */ + ret = serdes_status_poll(dev, phyad, SERDES_GSR0, + SERDES_PWR_ST_MASK, + SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT); + + if (ret) { + dev_err(dev, "Serdes power state P0 timeout.\n"); + return ret; + } + + /* PSE only - ungate SGMII PHY Rx Clock*/ + ret = mac_check_pse(dev, &is_pse); + if (ret) { + dev_err(dev, "Failed to determine MAC type.\n"); + return ret; + } + + if (is_pse) { + miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data); + data |= SERDES_PHY_RX_CLK; + miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data); + } + + return 0; +} + +static int xpcs_access(struct udevice *dev, int reg, int v) +{ + /* + * Common read/write helper function + * + * It may seem a bit odd at a first glance that we use bus->read() + * directly insetad of one of the wrapper functions. But: + * + * (1) phy_read() can't be used because we do not access an acutal PHY, + * but a MAC-internal submodule. + * + * (2) miiphy_read() can't be used because it assumes MDIO_DEVAD_NONE. + */ + + int port = INTEL_MGBE_XPCS_ADDR; + int devad = 0x1f; + u16 val; + struct eqos_priv *eqos; + struct mii_dev *bus; + + eqos = dev_get_priv(dev); + bus = eqos->mii; + + if (v < 0) + return bus->read(bus, port, devad, reg); + + val = v; + return bus->write(bus, port, devad, reg, val); +} + +static int xpcs_read(struct udevice *dev, int reg) +{ + return xpcs_access(dev, reg, -1); +} + +static int xpcs_write(struct udevice *dev, int reg, u16 val) +{ + return xpcs_access(dev, reg, val); +} + +static int xpcs_clr_bits(struct udevice *dev, int reg, u16 bits) +{ + int ret; + + ret = xpcs_read(dev, reg); + if (ret < 0) + return ret; + + ret &= ~bits; + + return xpcs_write(dev, reg, ret); +} + +static int xpcs_set_bits(struct udevice *dev, int reg, u16 bits) +{ + int ret; + + ret = xpcs_read(dev, reg); + if (ret < 0) + return ret; + + ret |= bits; + + return xpcs_write(dev, reg, ret); +} + +static int xpcs_init(struct udevice *dev) +{ + /* Based on linux/drivers/net/pcs/pcs-xpcs.c */ + struct eqos_priv *eqos = dev_get_priv(dev); + phy_interface_t interface = eqos->config->interface(dev); + + if (interface != PHY_INTERFACE_MODE_SGMII) + return 0; + + if (xpcs_clr_bits(dev, VR_MII_MMD_CTRL, XPCS_AN_CL37_EN) || + xpcs_set_bits(dev, VR_MII_AN_CTRL, XPCS_MODE_SGMII) || + xpcs_set_bits(dev, VR_MII_DIG_CTRL1, XPCS_MAC_AUTO_SW) || + xpcs_set_bits(dev, VR_MII_MMD_CTRL, XPCS_AN_CL37_EN)) + return -EIO; + + return 0; +} + +static int eqos_probe_ressources_intel(struct udevice *dev) +{ + int ret; + + ret = eqos_get_base_addr_pci(dev); + if (ret) { + dev_err(dev, "eqos_get_base_addr_pci failed: %d\n", ret); + return ret; + } + + limit_fifo_size(dev); + + ret = pci_config(dev); + if (ret) { + dev_err(dev, "pci_config failed: %d\n", ret); + return ret; + } + + return 0; +} + +struct eqos_config eqos_intel_config; + +/* + * overwrite __weak function from eqos_intel.c + * + * For PCI devices the devcie tree is optional. Choose driver data based on PCI + * IDs instead. + */ +void *eqos_get_driver_data(struct udevice *dev) +{ + const struct pci_device_id *id; + const struct pci_child_plat *plat; + + plat = dev_get_parent_plat(dev); + + if (!plat) + return NULL; + + /* last intel_pci_ids element is zero initialized */ + for (id = intel_pci_ids; id->vendor != 0; id++) { + if (id->vendor == plat->vendor && id->device == plat->device) + return &eqos_intel_config; + } + + return NULL; +} + +static int eqos_start_resets_intel(struct udevice *dev) +{ + int ret; + + ret = xpcs_init(dev); + if (ret) { + dev_err(dev, "xpcs init failed.\n"); + return ret; + } + + ret = serdes_powerup(dev); + if (ret) { + dev_err(dev, "Failed to power up serdes.\n"); + return ret; + } + + return 0; +} + +static ulong eqos_get_tick_clk_rate_intel(struct udevice *dev) +{ + return 0; +} + +static int eqos_get_enetaddr_intel(struct udevice *dev) +{ + /* Assume MAC address is programmed by previous boot stage */ + struct eth_pdata *plat = dev_get_plat(dev); + struct eqos_priv *eqos = dev_get_priv(dev); + u8 *lo = (u8 *)&eqos->mac_regs->address0_low; + u8 *hi = (u8 *)&eqos->mac_regs->address0_high; + + plat->enetaddr[0] = lo[0]; + plat->enetaddr[1] = lo[1]; + plat->enetaddr[2] = lo[2]; + plat->enetaddr[3] = lo[3]; + plat->enetaddr[4] = hi[0]; + plat->enetaddr[5] = hi[1]; + + return 0; +} + +static phy_interface_t eqos_get_interface_intel(const struct udevice *dev) +{ + struct pci_child_plat *plat = dev_get_parent_plat(dev); + + if (!plat || plat->vendor != PCI_VENDOR_ID_INTEL) + return PHY_INTERFACE_MODE_NA; + + switch (plat->device) { + /* The GbE Host Controller has no RGMII interface */ + case PCI_DEVICE_ID_INTEL_EHL_RGMII1G: + return PHY_INTERFACE_MODE_NA; + + case PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G: + return PHY_INTERFACE_MODE_RGMII; + + /* Host SGMII and Host SGMII2G5 share the same device id */ + case PCI_DEVICE_ID_INTEL_EHL_SGMII1: + case PCI_DEVICE_ID_INTEL_EHL_SGMII2G5: + case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5: + case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G: + case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5: + return PHY_INTERFACE_MODE_SGMII; + }; + + return PHY_INTERFACE_MODE_NA; +} + +static struct eqos_ops eqos_intel_ops = { + .eqos_inval_desc = eqos_inval_desc_generic, + .eqos_flush_desc = eqos_flush_desc_generic, + .eqos_inval_buffer = eqos_inval_buffer_generic, + .eqos_flush_buffer = eqos_flush_buffer_generic, + .eqos_probe_resources = eqos_probe_ressources_intel, + .eqos_remove_resources = eqos_null_ops, + .eqos_stop_resets = eqos_null_ops, + .eqos_start_resets = eqos_start_resets_intel, + .eqos_stop_clks = eqos_null_ops, + .eqos_start_clks = eqos_null_ops, + .eqos_calibrate_pads = eqos_null_ops, + .eqos_disable_calibration = eqos_null_ops, + .eqos_set_tx_clk_speed = eqos_null_ops, + .eqos_get_enetaddr = eqos_get_enetaddr_intel, + .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_intel, +}; + +struct eqos_config eqos_intel_config = { + .reg_access_always_ok = false, + .mdio_wait = 10, + .swr_wait = 50, + .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, + .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, + .axi_bus_width = EQOS_AXI_WIDTH_64, + .interface = eqos_get_interface_intel, + .ops = &eqos_intel_ops +}; + +extern U_BOOT_DRIVER(eth_eqos); +U_BOOT_PCI_DEVICE(eth_eqos, intel_pci_ids); diff --git a/drivers/net/dwc_eth_qos_intel.h b/drivers/net/dwc_eth_qos_intel.h new file mode 100644 index 00000000000..847c75ede54 --- /dev/null +++ b/drivers/net/dwc_eth_qos_intel.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2023-2024 DENX Software Engineering GmbH + * Philip Oberfichtner <pro@denx.de> + * + * This header is based on linux v6.6.39, + * + * drivers/net/pcs/pcs-xpcs.h + * drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h, + * + * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates + * Copyright (c) 2020 Intel Corporation + */ + +#ifndef __DWMAC_INTEL_H__ +#define __DWMAC_INTEL_H__ + +#define POLL_DELAY_US 8 + +/* SERDES Register */ +#define SERDES_GCR 0x0 /* Global Conguration */ +#define SERDES_GSR0 0x5 /* Global Status Reg0 */ +#define SERDES_GCR0 0xb /* Global Configuration Reg0 */ + +/* SERDES defines */ +#define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */ +#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */ +#define SERDES_RST BIT(2) /* Serdes Reset */ +#define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/ +#define SERDES_RATE_MASK GENMASK(9, 8) +#define SERDES_PCLK_MASK GENMASK(14, 12) /* PCLK rate to PHY */ +#define SERDES_LINK_MODE_MASK GENMASK(2, 1) +#define SERDES_PWR_ST_SHIFT 4 +#define SERDES_PWR_ST_P0 0x0 +#define SERDES_PWR_ST_P3 0x3 +#define SERDES_LINK_MODE_2G5 0x3 +#define SERSED_LINK_MODE_1G 0x2 +#define SERDES_PCLK_37p5MHZ 0x0 +#define SERDES_PCLK_70MHZ 0x1 +#define SERDES_RATE_PCIE_GEN1 0x0 +#define SERDES_RATE_PCIE_GEN2 0x1 +#define SERDES_RATE_PCIE_SHIFT 8 +#define SERDES_PCLK_SHIFT 12 + +#define INTEL_MGBE_ADHOC_ADDR 0x15 +#define INTEL_MGBE_XPCS_ADDR 0x16 + +/* XPCS defines */ +#define XPCS_MODE_SGMII BIT(2) +#define XPCS_MAC_AUTO_SW BIT(9) +#define XPCS_AN_CL37_EN BIT(12) + +#define VR_MII_MMD_CTRL 0x0000 +#define VR_MII_DIG_CTRL1 0x8000 +#define VR_MII_AN_CTRL 0x8001 + +#endif /* __DWMAC_INTEL_H__ */ diff --git a/drivers/net/dwc_eth_qos_qcom.c b/drivers/net/dwc_eth_qos_qcom.c index 77d626393d5..de0ae090c5d 100644 --- a/drivers/net/dwc_eth_qos_qcom.c +++ b/drivers/net/dwc_eth_qos_qcom.c @@ -522,6 +522,12 @@ static int eqos_probe_resources_qcom(struct udevice *dev) debug("%s(dev=%p):\n", __func__, dev); + ret = eqos_get_base_addr_dt(dev); + if (ret) { + pr_err("eqos_get_base_addr_dt failed: %d\n", ret); + return ret; + } + interface = eqos->config->interface(dev); if (interface == PHY_INTERFACE_MODE_NA) { diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index c4557e57988..9fc8c686b88 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -311,6 +311,12 @@ static int eqos_probe_resources_rk(struct udevice *dev) int reset_flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE; int ret; + ret = eqos_get_base_addr_dt(dev); + if (ret) { + dev_err(dev, "eqos_get_base_addr_dt failed: %d\n", ret); + return ret; + } + data = calloc(1, sizeof(struct rockchip_platform_data)); if (!data) return -ENOMEM; diff --git a/drivers/net/dwc_eth_qos_starfive.c b/drivers/net/dwc_eth_qos_starfive.c index 09e714ce76a..d9ace435ee2 100644 --- a/drivers/net/dwc_eth_qos_starfive.c +++ b/drivers/net/dwc_eth_qos_starfive.c @@ -183,6 +183,12 @@ static int eqos_probe_resources_jh7110(struct udevice *dev) struct starfive_platform_data *data; int ret; + ret = eqos_get_base_addr_dt(dev); + if (ret) { + pr_err("eqos_get_base_addr_dt failed: %d\n", ret); + return ret; + } + data = calloc(1, sizeof(struct starfive_platform_data)); if (!data) return -ENOMEM; diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index cffaa10b705..f3a973f3774 100644 --- a/drivers/net/dwc_eth_qos_stm32.c +++ b/drivers/net/dwc_eth_qos_stm32.c @@ -234,6 +234,12 @@ static int eqos_probe_resources_stm32(struct udevice *dev) interface = eqos->config->interface(dev); + ret = eqos_get_base_addr_dt(dev); + if (ret) { + dev_err(dev, "eqos_get_base_addr_dt failed: %d\n", ret); + return ret; + } + if (interface == PHY_INTERFACE_MODE_NA) { dev_err(dev, "Invalid PHY interface\n"); return -EINVAL; diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 8781e50a48d..f5ea2e72d1b 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -26,6 +26,7 @@ #include <linux/io.h> #include <linux/iopoll.h> #include <linux/printk.h> +#include <linux/bitfield.h> #include "ftgmac100.h" @@ -57,6 +58,15 @@ enum ftgmac100_model { FTGMAC100_MODEL_FARADAY, FTGMAC100_MODEL_ASPEED, + FTGMAC100_MODEL_ASPEED_AST2700, +}; + +union ftgmac100_dma_addr { + dma_addr_t addr; + struct { + u32 lo; + u32 hi; + }; }; /** @@ -96,6 +106,8 @@ struct ftgmac100_data { /* End of RX/TX ring buffer bits. Depend on model */ u32 rxdes0_edorr_mask; u32 txdes0_edotr_mask; + + bool is_ast2700; }; /* @@ -222,7 +234,7 @@ static int ftgmac100_phy_init(struct udevice *dev) struct phy_device *phydev; int ret; - if (IS_ENABLED(CONFIG_DM_MDIO)) + if (IS_ENABLED(CONFIG_DM_MDIO) && priv->phy_mode != PHY_INTERFACE_MODE_NCSI) phydev = dm_eth_phy_connect(dev); else phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode); @@ -320,8 +332,9 @@ static int ftgmac100_start(struct udevice *dev) struct eth_pdata *plat = dev_get_plat(dev); struct ftgmac100_data *priv = dev_get_priv(dev); struct ftgmac100 *ftgmac100 = priv->iobase; + union ftgmac100_dma_addr dma_addr = {.hi = 0, .lo = 0}; struct phy_device *phydev = priv->phydev; - unsigned int maccr; + unsigned int maccr, dblac, desc_size; ulong start, end; int ret; int i; @@ -341,6 +354,7 @@ static int ftgmac100_start(struct udevice *dev) priv->rx_index = 0; for (i = 0; i < PKTBUFSTX; i++) { + priv->txdes[i].txdes2 = 0; priv->txdes[i].txdes3 = 0; priv->txdes[i].txdes0 = 0; } @@ -351,7 +365,14 @@ static int ftgmac100_start(struct udevice *dev) flush_dcache_range(start, end); for (i = 0; i < PKTBUFSRX; i++) { - priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i]; + unsigned int ip_align = 0; + + dma_addr.addr = (dma_addr_t)net_rx_packets[i]; + priv->rxdes[i].rxdes2 = FIELD_PREP(FTGMAC100_RXDES2_RXBUF_BADR_HI, dma_addr.hi); + /* For IP alignment */ + if ((dma_addr.lo & (PKTALIGN - 1)) == 0) + ip_align = 2; + priv->rxdes[i].rxdes3 = dma_addr.lo + ip_align; priv->rxdes[i].rxdes0 = 0; } priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask; @@ -361,10 +382,25 @@ static int ftgmac100_start(struct udevice *dev) flush_dcache_range(start, end); /* transmit ring */ - writel((u32)priv->txdes, &ftgmac100->txr_badr); + dma_addr.addr = (dma_addr_t)priv->txdes; + writel(dma_addr.lo, &ftgmac100->txr_badr); + writel(dma_addr.hi, &ftgmac100->txr_badr_hi); /* receive ring */ - writel((u32)priv->rxdes, &ftgmac100->rxr_badr); + dma_addr.addr = (dma_addr_t)priv->rxdes; + writel(dma_addr.lo, &ftgmac100->rxr_badr); + writel(dma_addr.hi, &ftgmac100->rxr_badr_hi); + + /* Configure TX/RX decsriptor size + * This size is calculated based on cache line. + */ + desc_size = ARCH_DMA_MINALIGN / FTGMAC100_DESC_UNIT; + /* The descriptor size is at least 2 descriptor units. */ + if (desc_size < 2) + desc_size = 2; + dblac = readl(&ftgmac100->dblac) & ~GENMASK(19, 12); + dblac |= FTGMAC100_DBLAC_RXDES_SIZE(desc_size) | FTGMAC100_DBLAC_TXDES_SIZE(desc_size); + writel(dblac, &ftgmac100->dblac); /* poll receive descriptor automatically */ writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc); @@ -382,6 +418,10 @@ static int ftgmac100_start(struct udevice *dev) FTGMAC100_MACCR_RX_RUNT | FTGMAC100_MACCR_RX_BROADPKT; + if (priv->is_ast2700 && (priv->phydev->interface == PHY_INTERFACE_MODE_RMII || + priv->phydev->interface == PHY_INTERFACE_MODE_NCSI)) + maccr |= FTGMAC100_MACCR_RMII_ENABLE; + writel(maccr, &ftgmac100->maccr); ret = phy_startup(phydev); @@ -410,6 +450,14 @@ static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length) ulong des_end = des_start + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); + /* + * Make sure there are no stale data in write-back over this area, which + * might get written into the memory while the ftgmac100 also writes + * into the same memory area. + */ + flush_dcache_range((ulong)net_rx_packets[priv->rx_index], + (ulong)net_rx_packets[priv->rx_index] + PKTSIZE_ALIGN); + /* Release buffer to DMA and flush descriptor */ curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; flush_dcache_range(des_start, des_end); @@ -431,9 +479,11 @@ static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp) ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1); ulong des_end = des_start + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); - ulong data_start = curr_des->rxdes3; + union ftgmac100_dma_addr data_start = { .lo = 0, .hi = 0 }; ulong data_end; + data_start.hi = FIELD_GET(FTGMAC100_RXDES2_RXBUF_BADR_HI, curr_des->rxdes2); + data_start.lo = curr_des->rxdes3; invalidate_dcache_range(des_start, des_end); if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY)) @@ -453,9 +503,9 @@ static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp) __func__, priv->rx_index, rxlen); /* Invalidate received data */ - data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN); - invalidate_dcache_range(data_start, data_end); - *packetp = (uchar *)data_start; + data_end = data_start.addr + roundup(rxlen, ARCH_DMA_MINALIGN); + invalidate_dcache_range(data_start.addr, data_end); + *packetp = (uchar *)data_start.addr; return rxlen; } @@ -481,6 +531,7 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length) struct ftgmac100_data *priv = dev_get_priv(dev); struct ftgmac100 *ftgmac100 = priv->iobase; struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index]; + union ftgmac100_dma_addr dma_addr; ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1); ulong des_end = des_start + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); @@ -499,10 +550,12 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length) length = (length < ETH_ZLEN) ? ETH_ZLEN : length; - curr_des->txdes3 = (unsigned int)packet; + dma_addr.addr = (dma_addr_t)packet; + curr_des->txdes2 = FIELD_PREP(FTGMAC100_TXDES2_TXBUF_BADR_HI, dma_addr.hi); + curr_des->txdes3 = dma_addr.lo; /* Flush data to be sent */ - data_start = curr_des->txdes3; + data_start = (ulong)dma_addr.addr; data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); flush_dcache_range(data_start, data_end); @@ -565,6 +618,11 @@ static int ftgmac100_of_to_plat(struct udevice *dev) if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) { priv->rxdes0_edorr_mask = BIT(30); priv->txdes0_edotr_mask = BIT(30); + priv->is_ast2700 = false; + } else if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED_AST2700) { + priv->rxdes0_edorr_mask = BIT(30); + priv->txdes0_edotr_mask = BIT(30); + priv->is_ast2700 = true; } else { priv->rxdes0_edorr_mask = BIT(15); priv->txdes0_edotr_mask = BIT(15); @@ -655,10 +713,11 @@ static const struct eth_ops ftgmac100_ops = { }; static const struct udevice_id ftgmac100_ids[] = { - { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY }, - { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED }, - { .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED }, - { } + { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY }, + { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED }, + { .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED }, + { .compatible = "aspeed,ast2700-mac", .data = FTGMAC100_MODEL_ASPEED_AST2700 }, + {} }; U_BOOT_DRIVER(ftgmac100) = { diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h index f7874ae68b6..c38b57c9541 100644 --- a/drivers/net/ftgmac100.h +++ b/drivers/net/ftgmac100.h @@ -66,6 +66,13 @@ struct ftgmac100 { unsigned int rx_runt; /* 0xc0 */ unsigned int rx_crcer_ftl; /* 0xc4 */ unsigned int rx_col_lost; /* 0xc8 */ + unsigned int reserved[43]; /* 0xcc - 0x174 */ + unsigned int txr_badr_lo; /* 0x178, defined in ast2700 */ + unsigned int txr_badr_hi; /* 0x17c, defined in ast2700 */ + unsigned int hptxr_badr_lo; /* 0x180, defined in ast2700 */ + unsigned int hptxr_badr_hi; /* 0x184, defined in ast2700 */ + unsigned int rxr_badr_lo; /* 0x188, defined in ast2700 */ + unsigned int rxr_badr_hi; /* 0x18c, defined in ast2700 */ }; /* @@ -111,6 +118,7 @@ struct ftgmac100 { #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) #define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) #define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) +#define FTGMAC100_DESC_UNIT 8 #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) #define FTGMAC100_DBLAC_IFG_INC BIT(23) @@ -157,6 +165,7 @@ struct ftgmac100 { #define FTGMAC100_MACCR_RX_BROADPKT BIT(17) #define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18) #define FTGMAC100_MACCR_FAST_MODE BIT(19) +#define FTGMAC100_MACCR_RMII_ENABLE BIT(20) /* defined in ast2700 */ #define FTGMAC100_MACCR_SW_RST BIT(31) /* @@ -183,7 +192,7 @@ struct ftgmac100_txdes { unsigned int txdes1; unsigned int txdes2; /* not used by HW */ unsigned int txdes3; /* TXBUF_BADR */ -} __aligned(16); +} __aligned(ARCH_DMA_MINALIGN); #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) #define FTGMAC100_TXDES0_EDOTR BIT(15) @@ -201,6 +210,8 @@ struct ftgmac100_txdes { #define FTGMAC100_TXDES1_TX2FIC BIT(30) #define FTGMAC100_TXDES1_TXIC BIT(31) +#define FTGMAC100_TXDES2_TXBUF_BADR_HI GENMASK(18, 16) + /* * Receive descriptor, aligned to 16 bytes */ @@ -209,7 +220,7 @@ struct ftgmac100_rxdes { unsigned int rxdes1; unsigned int rxdes2; /* not used by HW */ unsigned int rxdes3; /* RXBUF_BADR */ -} __aligned(16); +} __aligned(ARCH_DMA_MINALIGN); #define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) #define FTGMAC100_RXDES0_EDORR BIT(15) @@ -240,4 +251,6 @@ struct ftgmac100_rxdes { #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26) #define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27) +#define FTGMAC100_RXDES2_RXBUF_BADR_HI GENMASK(18, 16) + #endif /* __FTGMAC100_H */ diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c index 04d8cc29afd..d88d850924c 100644 --- a/drivers/pci/pcie_mediatek.c +++ b/drivers/pci/pcie_mediatek.c @@ -524,7 +524,7 @@ exit: mtk_pcie_port_free(port); } -static int mtk_pcie_parse_port(struct udevice *dev, u32 slot) +static int mtk_pcie_parse_port(struct udevice *dev, u32 slot, int index) { struct mtk_pcie *pcie = dev_get_priv(dev); struct mtk_pcie_port *port; @@ -545,11 +545,11 @@ static int mtk_pcie_parse_port(struct udevice *dev, u32 slot) if (err) return err; - err = reset_get_by_index(dev, slot, &port->reset); + err = reset_get_by_index(dev, index, &port->reset); if (err) return err; - err = generic_phy_get_by_index(dev, slot, &port->phy); + err = generic_phy_get_by_index(dev, index, &port->phy); if (err) return err; @@ -631,18 +631,58 @@ static int mtk_pcie_parse_port_v2(struct udevice *dev, u32 slot) return 0; } +static int mtk_pcie_subsys_get(struct udevice *dev) +{ + struct mtk_pcie *pcie = dev_get_priv(dev); + ofnode cfg_node; + fdt_addr_t addr; + + cfg_node = ofnode_by_compatible(ofnode_null(), + "mediatek,generic-pciecfg"); + if (!ofnode_valid(cfg_node)) + return -ENOENT; + + addr = ofnode_get_addr(cfg_node); + if (addr == FDT_ADDR_T_NONE) + return -ENODEV; + + pcie->base = map_physmem(addr, 0, MAP_NOCACHE); + if (!pcie->base) + return -ENOENT; + + return 0; +} + static int mtk_pcie_probe(struct udevice *dev) { struct mtk_pcie *pcie = dev_get_priv(dev); struct mtk_pcie_port *port, *tmp; + bool split_pcie_node = false; ofnode subnode; + unsigned int slot; int err; INIT_LIST_HEAD(&pcie->ports); - pcie->base = dev_remap_addr_name(dev, "subsys"); - if (!pcie->base) - return -ENOENT; + /* Check if upstream implementation is used */ + err = mtk_pcie_subsys_get(dev); + if (!err) { + /* + * Assume split port node implementation with "mediatek,generic-pciecfg" + * found. We check reg-names and check if the node is for port0 or port1. + */ + split_pcie_node = true; + if (!strcmp(dev_read_string(dev, "reg-names"), "port0")) + slot = 0; + else if (!strcmp(dev_read_string(dev, "reg-names"), "port1")) + slot = 1; + else + return -EINVAL; + } else { + pcie->base = dev_remap_addr_name(dev, "subsys"); + if (!pcie->base) + return -ENOENT; + } err = clk_get_by_name(dev, "free_ck", &pcie->free_ck); if (err) @@ -653,20 +693,27 @@ static int mtk_pcie_probe(struct udevice *dev) if (err) return err; - dev_for_each_subnode(subnode, dev) { - struct fdt_pci_addr addr; - u32 slot = 0; + if (!split_pcie_node) { + dev_for_each_subnode(subnode, dev) { + struct fdt_pci_addr addr; - if (!ofnode_is_enabled(subnode)) - continue; + slot = 0; - err = ofnode_read_pci_addr(subnode, 0, "reg", &addr, NULL); - if (err) - return err; + if (!ofnode_is_enabled(subnode)) + continue; - slot = PCI_DEV(addr.phys_hi); + err = ofnode_read_pci_addr(subnode, 0, "reg", &addr, NULL); + if (err) + return err; - err = mtk_pcie_parse_port(dev, slot); + slot = PCI_DEV(addr.phys_hi); + + err = mtk_pcie_parse_port(dev, slot, slot); + if (err) + return err; + } + } else { + err = mtk_pcie_parse_port(dev, slot, 0); if (err) return err; } @@ -682,28 +729,54 @@ static int mtk_pcie_probe_v2(struct udevice *dev) { struct mtk_pcie *pcie = dev_get_priv(dev); struct mtk_pcie_port *port, *tmp; - struct fdt_pci_addr addr; + bool split_pcie_node = false; ofnode subnode; unsigned int slot; int err; INIT_LIST_HEAD(&pcie->ports); - pcie->base = dev_remap_addr_name(dev, "subsys"); - if (!pcie->base) - return -ENOENT; + /* Check if upstream implementation is used */ + err = mtk_pcie_subsys_get(dev); + if (!err) { + /* + * Assume split port node implementation with "mediatek,generic-pciecfg" + * found. We check reg-names and check if the node is for port0 or port1. + */ + split_pcie_node = true; + if (!strcmp(dev_read_string(dev, "reg-names"), "port0")) + slot = 0; + else if (!strcmp(dev_read_string(dev, "reg-names"), "port1")) + slot = 1; + else + return -EINVAL; + } else { + pcie->base = dev_remap_addr_name(dev, "subsys"); + if (!pcie->base) + return -ENOENT; + } pcie->priv = dev; - dev_for_each_subnode(subnode, dev) { - if (!ofnode_is_enabled(subnode)) - continue; + if (!split_pcie_node) { + dev_for_each_subnode(subnode, dev) { + struct fdt_pci_addr addr; - err = ofnode_read_pci_addr(subnode, 0, "reg", &addr, NULL); - if (err) - return err; + slot = 0; - slot = PCI_DEV(addr.phys_hi); + if (!ofnode_is_enabled(subnode)) + continue; + + err = ofnode_read_pci_addr(subnode, 0, "reg", &addr, NULL); + if (err) + return err; + + slot = PCI_DEV(addr.phys_hi); + err = mtk_pcie_parse_port_v2(dev, slot); + if (err) + return err; + } + } else { err = mtk_pcie_parse_port_v2(dev, slot); if (err) return err; diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c index 7c292cae0e2..b278f995f37 100644 --- a/drivers/phy/phy-rcar-gen3.c +++ b/drivers/phy/phy-rcar-gen3.c @@ -8,6 +8,7 @@ #include <clk.h> #include <div64.h> #include <dm.h> +#include <dm/device_compat.h> #include <fdtdec.h> #include <generic-phy.h> #include <malloc.h> @@ -31,8 +32,13 @@ #define USB2_LINECTRL1 0x610 #define USB2_ADPCTRL 0x630 +/* INT_ENABLE */ +#define USB2_INT_ENABLE_UCOM_INTEN BIT(3) +#define USB2_INT_ENABLE_USBH_INTB_EN BIT(2) +#define USB2_INT_ENABLE_USBH_INTA_EN BIT(1) + /* USBCTR */ -#define USB2_USBCTR_PLL_RST BIT(1) +#define USB2_USBCTR_PLL_RST BIT(1) /* SPD_RSM_TIMSET */ #define USB2_SPD_RSM_TIMSET_INIT 0x014e029b @@ -43,11 +49,23 @@ /* COMMCTRL */ #define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */ +/* OBINTSTA and OBINTEN */ +#define USB2_OBINT_SESSVLDCHG BIT(12) +#define USB2_OBINT_IDDIGCHG BIT(11) + +/* VBCTRL */ +#define USB2_VBCTRL_DRVVBUSSEL BIT(8) + /* LINECTRL1 */ +#define USB2_LINECTRL1_DPRPD_EN BIT(19) #define USB2_LINECTRL1_DP_RPD BIT(18) +#define USB2_LINECTRL1_DMRPD_EN BIT(17) #define USB2_LINECTRL1_DM_RPD BIT(16) /* ADPCTRL */ +#define USB2_ADPCTRL_OTGSESSVLD BIT(20) +#define USB2_ADPCTRL_IDDIG BIT(19) +#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */ #define USB2_ADPCTRL_DRVVBUS BIT(4) struct rcar_gen3_phy { @@ -65,12 +83,14 @@ static int rcar_gen3_phy_phy_init(struct phy *phy) writel(USB2_SPD_RSM_TIMSET_INIT, priv->regs + USB2_SPD_RSM_TIMSET); writel(USB2_OC_TIMSET_INIT, priv->regs + USB2_OC_TIMSET); - setbits_le32(priv->regs + USB2_LINECTRL1, - USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD); + return 0; +} - clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI); +static int rcar_gen3_phy_phy_exit(struct phy *phy) +{ + struct rcar_gen3_phy *priv = dev_get_priv(phy->dev); - setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS); + writel(0, priv->regs + USB2_INT_ENABLE); return 0; } @@ -102,10 +122,70 @@ static int rcar_gen3_phy_phy_power_off(struct phy *phy) return regulator_set_enable(priv->vbus_supply, false); } +static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + const u32 adpdevmask = USB2_ADPCTRL_IDDIG | USB2_ADPCTRL_OTGSESSVLD; + struct rcar_gen3_phy *priv = dev_get_priv(phy->dev); + u32 adpctrl; + + if (mode == PHY_MODE_USB_OTG) { + if (submode) { + /* OTG submode is used as initialization indicator */ + writel(USB2_INT_ENABLE_UCOM_INTEN | + USB2_INT_ENABLE_USBH_INTB_EN | + USB2_INT_ENABLE_USBH_INTA_EN, + priv->regs + USB2_INT_ENABLE); + setbits_le32(priv->regs + USB2_VBCTRL, + USB2_VBCTRL_DRVVBUSSEL); + writel(USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG, + priv->regs + USB2_OBINTSTA); + setbits_le32(priv->regs + USB2_OBINTEN, + USB2_OBINT_SESSVLDCHG | + USB2_OBINT_IDDIGCHG); + setbits_le32(priv->regs + USB2_ADPCTRL, + USB2_ADPCTRL_IDPULLUP); + clrsetbits_le32(priv->regs + USB2_LINECTRL1, + USB2_LINECTRL1_DP_RPD | + USB2_LINECTRL1_DM_RPD | + USB2_LINECTRL1_DPRPD_EN | + USB2_LINECTRL1_DMRPD_EN, + USB2_LINECTRL1_DPRPD_EN | + USB2_LINECTRL1_DMRPD_EN); + } + + adpctrl = readl(priv->regs + USB2_ADPCTRL); + if ((adpctrl & adpdevmask) == adpdevmask) + mode = PHY_MODE_USB_DEVICE; + else + mode = PHY_MODE_USB_HOST; + } + + if (mode == PHY_MODE_USB_HOST) { + clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI); + setbits_le32(priv->regs + USB2_LINECTRL1, + USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD); + setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS); + } else if (mode == PHY_MODE_USB_DEVICE) { + setbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI); + clrsetbits_le32(priv->regs + USB2_LINECTRL1, + USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD, + USB2_LINECTRL1_DM_RPD); + clrbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS); + } else { + dev_err(phy->dev, "Unknown mode %d\n", mode); + return -EINVAL; + } + + return 0; +} + static const struct phy_ops rcar_gen3_phy_phy_ops = { .init = rcar_gen3_phy_phy_init, + .exit = rcar_gen3_phy_phy_exit, .power_on = rcar_gen3_phy_phy_power_on, .power_off = rcar_gen3_phy_phy_power_off, + .set_mode = rcar_gen3_phy_phy_set_mode, }; static int rcar_gen3_phy_probe(struct udevice *dev) diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c index acdcda15b5b..777d952b041 100644 --- a/drivers/phy/phy-uclass.c +++ b/drivers/phy/phy-uclass.c @@ -508,7 +508,8 @@ int generic_phy_power_off_bulk(struct phy_bulk *bulk) return ret; } -int generic_setup_phy(struct udevice *dev, struct phy *phy, int index) +int generic_setup_phy(struct udevice *dev, struct phy *phy, int index, + enum phy_mode mode, int submode) { int ret; @@ -520,10 +521,18 @@ int generic_setup_phy(struct udevice *dev, struct phy *phy, int index) if (ret) return ret; + ret = generic_phy_set_mode(phy, mode, submode); + if (ret) + goto phys_mode_err; + ret = generic_phy_power_on(phy); if (ret) - generic_phy_exit(phy); + goto phys_mode_err; + + return 0; +phys_mode_err: + generic_phy_exit(phy); return ret; } diff --git a/drivers/phy/sandbox-phy.c b/drivers/phy/sandbox-phy.c index b159147a765..e70d20432e0 100644 --- a/drivers/phy/sandbox-phy.c +++ b/drivers/phy/sandbox-phy.c @@ -72,6 +72,18 @@ static int sandbox_phy_exit(struct phy *phy) return 0; } +static int +sandbox_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + if (submode) + return -EOPNOTSUPP; + + if (mode != PHY_MODE_USB_HOST) + return -EINVAL; + + return 0; +} + static int sandbox_phy_bind(struct udevice *dev) { if (dev_get_driver_data(dev) != DRIVER_DATA) @@ -96,6 +108,7 @@ static struct phy_ops sandbox_phy_ops = { .power_off = sandbox_phy_power_off, .init = sandbox_phy_init, .exit = sandbox_phy_exit, + .set_mode = sandbox_phy_set_mode, }; static const struct udevice_id sandbox_phy_ids[] = { diff --git a/drivers/pinctrl/pinctrl-sandbox.c b/drivers/pinctrl/pinctrl-sandbox.c index a5d056643a0..f6921b56ceb 100644 --- a/drivers/pinctrl/pinctrl-sandbox.c +++ b/drivers/pinctrl/pinctrl-sandbox.c @@ -42,7 +42,7 @@ static const char * const sandbox_pins_muxing[][2] = { { "GPIO0", "SPI CS0" }, { "GPIO1", "SPI CS1" }, { "GPIO2", "PWM0" }, - { "GPIO3", "PWM1" }, + { "GPIO3", "ONEWIRE" }, }; #define SANDBOX_GROUP_I2C_UART 0 @@ -63,6 +63,7 @@ static const char * const sandbox_functions[] = { FUNC(GPIO), FUNC(CS), FUNC(PWM), + FUNC(ONEWIRE), #undef FUNC }; @@ -166,6 +167,7 @@ static int sandbox_pinmux_set(struct udevice *dev, unsigned pin_selector, break; case SANDBOX_PINMUX_CS: case SANDBOX_PINMUX_PWM: + case SANDBOX_PINMUX_ONEWIRE: mux = BIT(pin_selector); break; default: diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index bc061c20d75..958f337c7e7 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -383,6 +383,15 @@ config DM_REGULATOR_TPS80031 features for TPS80031/TPS80032 PMICs. The driver implements get/set api for: value and enable. +config DM_REGULATOR_TPS6287X + bool "Enable driver for TPS6287x Power Regulator" + depends on DM_REGULATOR + help + The TPS6287X is a step down converter with a fast transient + response. This driver supports all four variants of the chip + (TPS62870, TPS62871, TPS62872, TPS62873). It implements the + get/set api for value only, as the power line is always on. + config DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators" depends on DM_REGULATOR && PMIC_STPMIC1 @@ -402,6 +411,15 @@ config DM_REGULATOR_ANATOP regulators. It is recommended that this option be enabled on i.MX6 platform. +config SPL_DM_REGULATOR_TPS6287X + bool "Enable driver for TPS6287x Power Regulator" + depends on SPL_DM_REGULATOR + help + The TPS6287X is a step down converter with a fast transient + response. This driver supports all four variants of the chip + (TPS62870, TPS62871, TPS62872, TPS62873). It implements the + get/set api for value only, as the power line is always on. + config SPL_DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators in SPL" depends on SPL_DM_REGULATOR && PMIC_STPMIC1 diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 56a527612b7..54db0885657 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS65911) += tps65911_regulator.o obj-$(CONFIG_DM_REGULATOR_TPS62360) += tps62360_regulator.o +obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS6287X) += tps6287x_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS80031) += tps80031_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMIC1) += stpmic1.o obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c index 98c89bf2aff..996da41546a 100644 --- a/drivers/power/regulator/fixed.c +++ b/drivers/power/regulator/fixed.c @@ -17,7 +17,7 @@ #include "regulator_common.h" -struct fixed_clock_regulator_plat { +struct fixed_clock_regulator_priv { struct clk *enable_clock; unsigned int clk_enable_counter; }; @@ -83,14 +83,14 @@ static int fixed_regulator_set_enable(struct udevice *dev, bool enable) static int fixed_clock_regulator_get_enable(struct udevice *dev) { - struct fixed_clock_regulator_plat *priv = dev_get_priv(dev); + struct fixed_clock_regulator_priv *priv = dev_get_priv(dev); return priv->clk_enable_counter > 0; } static int fixed_clock_regulator_set_enable(struct udevice *dev, bool enable) { - struct fixed_clock_regulator_plat *priv = dev_get_priv(dev); + struct fixed_clock_regulator_priv *priv = dev_get_priv(dev); struct regulator_common_plat *plat = dev_get_plat(dev); int ret = 0; @@ -113,6 +113,17 @@ static int fixed_clock_regulator_set_enable(struct udevice *dev, bool enable) return ret; } +static int fixed_clock_regulator_probe(struct udevice *dev) +{ + struct fixed_clock_regulator_priv *priv = dev_get_priv(dev); + + priv->enable_clock = devm_clk_get(dev, NULL); + if (IS_ERR(priv->enable_clock)) + return PTR_ERR(priv->enable_clock); + + return 0; +} + static const struct dm_regulator_ops fixed_regulator_ops = { .get_value = fixed_regulator_get_value, .get_current = fixed_regulator_get_current, @@ -149,6 +160,8 @@ U_BOOT_DRIVER(regulator_fixed_clock) = { .id = UCLASS_REGULATOR, .ops = &fixed_clock_regulator_ops, .of_match = fixed_clock_regulator_ids, + .probe = fixed_clock_regulator_probe, .of_to_plat = fixed_regulator_of_to_plat, - .plat_auto = sizeof(struct fixed_clock_regulator_plat), + .plat_auto = sizeof(struct regulator_common_plat), + .priv_auto = sizeof(struct fixed_clock_regulator_priv), }; diff --git a/drivers/power/regulator/qcom-rpmh-regulator.c b/drivers/power/regulator/qcom-rpmh-regulator.c index 06fd3f31956..2dc261d83e3 100644 --- a/drivers/power/regulator/qcom-rpmh-regulator.c +++ b/drivers/power/regulator/qcom-rpmh-regulator.c @@ -357,6 +357,69 @@ static const struct dm_regulator_ops rpmh_regulator_vrm_drms_ops = { .get_mode = rpmh_regulator_vrm_get_mode, }; +static struct dm_regulator_mode pmic_mode_map_pmic5_bob[] = { + { + .id = REGULATOR_MODE_LPM, + .register_value = PMIC5_BOB_MODE_PFM, + .name = "PMIC5_BOB_MODE_PFM" + }, { + .id = REGULATOR_MODE_AUTO, + .register_value = PMIC5_BOB_MODE_AUTO, + .name = "PMIC5_BOB_MODE_AUTO" + }, { + .id = REGULATOR_MODE_HPM, + .register_value = PMIC5_BOB_MODE_PWM, + .name = "PMIC5_BOB_MODE_PWM" + }, +}; + +static struct dm_regulator_mode pmic_mode_map_pmic5_smps[] = { + { + .id = REGULATOR_MODE_RETENTION, + .register_value = PMIC5_SMPS_MODE_RETENTION, + .name = "PMIC5_SMPS_MODE_RETENTION" + }, { + .id = REGULATOR_MODE_LPM, + .register_value = PMIC5_SMPS_MODE_PFM, + .name = "PMIC5_SMPS_MODE_PFM" + }, { + .id = REGULATOR_MODE_AUTO, + .register_value = PMIC5_SMPS_MODE_AUTO, + .name = "PMIC5_SMPS_MODE_AUTO" + }, { + .id = REGULATOR_MODE_HPM, + .register_value = PMIC5_SMPS_MODE_PWM, + .name = "PMIC5_SMPS_MODE_PWM" + }, +}; + +static const struct rpmh_vreg_hw_data pmic5_bob = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_range = REGULATOR_LINEAR_RANGE(3000000, 0, 31, 32000), + .n_voltages = 32, + .pmic_mode_map = pmic_mode_map_pmic5_bob, + .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_bob), +}; + +static const struct rpmh_vreg_hw_data pmic5_ftsmps525_lv = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_range = REGULATOR_LINEAR_RANGE(300000, 0, 267, 4000), + .n_voltages = 268, + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_smps), +}; + +static const struct rpmh_vreg_hw_data pmic5_ftsmps525_mv = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_range = REGULATOR_LINEAR_RANGE(600000, 0, 267, 8000), + .n_voltages = 268, + .pmic_mode_map = pmic_mode_map_pmic5_smps, + .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_smps), +}; + static struct dm_regulator_mode pmic_mode_map_pmic5_ldo[] = { { .id = REGULATOR_MODE_RETENTION, @@ -393,6 +456,16 @@ static const struct rpmh_vreg_hw_data pmic5_pldo_lv = { .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_ldo), }; +static const struct rpmh_vreg_hw_data pmic5_nldo515 = { + .regulator_type = VRM, + .ops = &rpmh_regulator_vrm_drms_ops, + .voltage_range = REGULATOR_LINEAR_RANGE(320000, 0, 210, 8000), + .n_voltages = 211, + .hpm_min_load_uA = 30000, + .pmic_mode_map = pmic_mode_map_pmic5_ldo, + .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_ldo), +}; + #define RPMH_VREG(_name, _resource_name, _hw_data, _supply_name) \ { \ .name = _name, \ @@ -412,6 +485,57 @@ static const struct rpmh_vreg_init_data pm8150l_vreg_data[] = { {} }; +static const struct rpmh_vreg_init_data pm8550_vreg_data[] = { + RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1-l4-l10"), + RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, "vdd-l2-l13-l14"), + RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"), + RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo515, "vdd-l1-l4-l10"), + RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l16"), + RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l6-l7"), + RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l6-l7"), + RPMH_VREG("ldo8", "ldo%s8", &pmic5_pldo, "vdd-l8-l9"), + RPMH_VREG("ldo9", "ldo%s9", &pmic5_pldo, "vdd-l8-l9"), + RPMH_VREG("ldo10", "ldo%s10", &pmic5_nldo515, "vdd-l1-l4-l10"), + RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo515, "vdd-l11"), + RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo515, "vdd-l12"), + RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l2-l13-l14"), + RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo, "vdd-l2-l13-l14"), + RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo515, "vdd-l15"), + RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l5-l16"), + RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l17"), + RPMH_VREG("bob1", "bob%s1", &pmic5_bob, "vdd-bob1"), + RPMH_VREG("bob2", "bob%s2", &pmic5_bob, "vdd-bob2"), + {} +}; + +static const struct rpmh_vreg_init_data pm8550vs_vreg_data[] = { + RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525_lv, "vdd-s1"), + RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525_lv, "vdd-s2"), + RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525_lv, "vdd-s3"), + RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525_lv, "vdd-s4"), + RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525_lv, "vdd-s5"), + RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525_mv, "vdd-s6"), + RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"), + RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"), + RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"), + {} +}; + +static const struct rpmh_vreg_init_data pm8550ve_vreg_data[] = { + RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525_lv, "vdd-s1"), + RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525_lv, "vdd-s2"), + RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525_lv, "vdd-s3"), + RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525_mv, "vdd-s4"), + RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525_lv, "vdd-s5"), + RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525_lv, "vdd-s6"), + RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps525_lv, "vdd-s7"), + RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps525_lv, "vdd-s8"), + RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"), + RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"), + RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"), + {} +}; + /* probe an individual regulator */ static int rpmh_regulator_probe(struct udevice *dev) { @@ -526,6 +650,18 @@ static const struct udevice_id rpmh_regulator_ids[] = { .compatible = "qcom,pm8150l-rpmh-regulators", .data = (ulong)pm8150l_vreg_data, }, + { + .compatible = "qcom,pm8550-rpmh-regulators", + .data = (ulong)pm8550_vreg_data, + }, + { + .compatible = "qcom,pm8550ve-rpmh-regulators", + .data = (ulong)pm8550ve_vreg_data, + }, + { + .compatible = "qcom,pm8550vs-rpmh-regulators", + .data = (ulong)pm8550vs_vreg_data, + }, { /* sentinal */ }, }; diff --git a/drivers/power/regulator/tps6287x_regulator.c b/drivers/power/regulator/tps6287x_regulator.c new file mode 100644 index 00000000000..6d185719199 --- /dev/null +++ b/drivers/power/regulator/tps6287x_regulator.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + * Keerthy <j-keerthy@ti.com> + */ + +#include <dm.h> +#include <i2c.h> +#include <dm/device_compat.h> +#include <power/regulator.h> + +#define TPS6287X_REG_VSET 0x0 +#define TPS6287X_REG_CONTROL1 0x1 +#define TPS6287X_REG_CONTROL2 0x2 +#define TPS6287X_REG_CONTROL3 0x3 +#define TPS6287X_REG_STATUS 0x4 +#define TPS6287X_REG_VSET_VSET_MASK 0xff +#define TPS6287X_REG_CONTROL2_VRANGE_MASK 0xc + +struct tps6287x_regulator_config { + u32 vmin; + u32 vmax; +}; + +struct tps6287x_regulator_pdata { + u8 vsel_offset; + struct udevice *i2c; + struct tps6287x_regulator_config *config; +}; + +static struct tps6287x_regulator_config tps6287x_data = { + .vmin = 400000, + .vmax = 3350000, +}; + +static int tps6287x_regulator_set_value(struct udevice *dev, int uV) +{ + struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev); + u8 regval, vset; + int ret; + + if (uV < pdata->config->vmin || uV > pdata->config->vmax) + return -EINVAL; + /* + * Based on the value of VRANGE bit field of CONTROL2 reg the range + * varies. + */ + ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_CONTROL2, ®val, 1); + if (ret) { + dev_err(dev, "CTRL2 reg read failed: %d\n", ret); + return ret; + } + + regval &= TPS6287X_REG_CONTROL2_VRANGE_MASK; + regval >>= ffs(TPS6287X_REG_CONTROL2_VRANGE_MASK) - 1; + + /* + * VRANGE = 0. Increment step 1250 uV starting with 0 --> 400000 uV + * VRANGE = 1. Increment step 2500 uV starting with 0 --> 400000 uV + * VRANGE = 2. Increment step 5000 uV starting with 0 --> 400000 uV + * VRANGE = 3. Increment step 10000 uV starting with 0 --> 800000 uV + */ + switch (regval) { + case 0: + vset = (uV - 400000) / 1250; + break; + case 1: + vset = (uV - 400000) / 2500; + break; + case 2: + vset = (uV - 400000) / 5000; + break; + case 3: + vset = (uV - 800000) / 10000; + break; + default: + pr_err("%s: invalid regval %d\n", dev->name, regval); + return -EINVAL; + } + + return dm_i2c_write(pdata->i2c, TPS6287X_REG_VSET, &vset, 1); +} + +static int tps6287x_regulator_get_value(struct udevice *dev) +{ + u8 regval, vset; + int uV; + int ret; + struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev); + + /* + * Based on the value of VRANGE bit field of CONTROL2 reg the range + * varies. + */ + ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_CONTROL2, ®val, 1); + if (ret) { + dev_err(dev, "i2c read failed: %d\n", ret); + return ret; + } + + regval &= TPS6287X_REG_CONTROL2_VRANGE_MASK; + regval >>= ffs(TPS6287X_REG_CONTROL2_VRANGE_MASK) - 1; + + ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_VSET, &vset, 1); + if (ret) { + dev_err(dev, "i2c VSET read failed: %d\n", ret); + return ret; + } + + /* + * VRANGE = 0. Increment step 1250 uV starting with 0 --> 400000 uV + * VRANGE = 1. Increment step 2500 uV starting with 0 --> 400000 uV + * VRANGE = 2. Increment step 5000 uV starting with 0 --> 400000 uV + * VRANGE = 3. Increment step 10000 uV starting with 0 --> 800000 uV + */ + switch (regval) { + case 0: + uV = 400000 + vset * 1250; + break; + case 1: + uV = 400000 + vset * 2500; + break; + case 2: + uV = 400000 + vset * 5000; + break; + case 3: + uV = 800000 + vset * 10000; + break; + default: + pr_err("%s: invalid regval %d\n", dev->name, regval); + return -EINVAL; + } + + return uV; +} + +static int tps6287x_regulator_probe(struct udevice *dev) +{ + struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev); + int ret, slave_id; + + pdata->config = (void *)dev_get_driver_data(dev); + + slave_id = devfdt_get_addr_index(dev, 0); + + ret = i2c_get_chip(dev->parent, slave_id, 1, &pdata->i2c); + if (ret) { + dev_err(dev, "i2c dev get failed.\n"); + return ret; + } + + return 0; +} + +static const struct dm_regulator_ops tps6287x_regulator_ops = { + .get_value = tps6287x_regulator_get_value, + .set_value = tps6287x_regulator_set_value, +}; + +static const struct udevice_id tps6287x_regulator_ids[] = { + { .compatible = "ti,tps62873", .data = (ulong)&tps6287x_data }, + { }, +}; + +U_BOOT_DRIVER(tps6287x_regulator) = { + .name = "tps6287x_regulator", + .id = UCLASS_REGULATOR, + .ops = &tps6287x_regulator_ops, + .of_match = tps6287x_regulator_ids, + .plat_auto = sizeof(struct tps6287x_regulator_pdata), + .probe = tps6287x_regulator_probe, +}; diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index 320ea7c4239..bb37b39fa0e 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -20,10 +20,11 @@ int pwm_config_internal(struct pwm_regs *pwm, unsigned long period_cycles, u32 cr; writel(0, &pwm->ir); - cr = PWMCR_PRESCALER(prescale) | + + cr = readl(&pwm->cr) & PWMCR_EN; + cr |= PWMCR_PRESCALER(prescale) | PWMCR_DOZEEN | PWMCR_WAITEN | PWMCR_DBGEN | PWMCR_CLKSRC_IPG_HIGH; - writel(cr, &pwm->cr); /* set duty cycles */ writel(duty_cycles, &pwm->sar); diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index c9c46cc17a8..fdb2e78ec9e 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ -obj-$(CONFIG_ARCH_ASPEED) += aspeed/ +obj-$(CONFIG_ASPEED_RAM) += aspeed/ obj-$(CONFIG_K3_DDRSS) += k3-ddrss/ obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig index 0deab8649b6..e4918460de6 100644 --- a/drivers/ram/aspeed/Kconfig +++ b/drivers/ram/aspeed/Kconfig @@ -1,6 +1,7 @@ menuconfig ASPEED_RAM bool "ASPEED SDRAM configuration" - depends on RAM && ARCH_ASPEED + depends on RAM + depends on ARCH_ASPEED || TARGET_ASPEED_AST2700_IBEX default ARCH_ASPEED help Configuration options for DDR SDRAM on ASPEED systems. @@ -8,8 +9,6 @@ menuconfig ASPEED_RAM RAM initialisation is always built in for the platform. This menu allows customisation of the configuration used. -if ASPEED_RAM - config ASPEED_DDR4_DUALX8 bool "Enable Dual X8 DDR4 die" depends on ASPEED_RAM @@ -74,4 +73,24 @@ config ASPEED_DDR4_1600 select DDR4 target data rate at 1600M endchoice -endif # End of ASPEED_RAM +choice + prompt "AST2700 DDR target date rate" + default ASPEED_DDR_3200 + depends on ASPEED_RAM + depends on TARGET_ASPEED_AST2700_IBEX + +config ASPEED_DDR_1600 + bool "1600 Mbps" + help + select DDR target data rate at 1600M + +config ASPEED_DDR_2400 + bool "2400 Mbps" + help + select DDR target data rate at 2400M + +config ASPEED_DDR_3200 + bool "3200 Mbps" + help + select DDR target data rate at 3200M +endchoice diff --git a/drivers/ram/aspeed/Makefile b/drivers/ram/aspeed/Makefile index 7ac10af1c22..1f0b22c8e9f 100644 --- a/drivers/ram/aspeed/Makefile +++ b/drivers/ram/aspeed/Makefile @@ -2,3 +2,4 @@ # obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o obj-$(CONFIG_ASPEED_AST2600) += sdram_ast2600.o +obj-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += sdram_ast2700.o diff --git a/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr4-3200-nodimm-train2D.c b/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr4-3200-nodimm-train2D.c new file mode 100644 index 00000000000..de593c17fad --- /dev/null +++ b/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr4-3200-nodimm-train2D.c @@ -0,0 +1,2700 @@ +// SPDX-License-Identifier: GPL-2.0+ +// [dwc_ddrphy_phyinit_main] Start of dwc_ddrphy_phyinit_main() +// [dwc_ddrphy_phyinit_sequence] Start of dwc_ddrphy_phyinit_sequence() +// [dwc_ddrphy_phyinit_initStruct] Start of dwc_ddrphy_phyinit_initStruct() +// [dwc_ddrphy_phyinit_initStruct] End of dwc_ddrphy_phyinit_initStruct() +// [dwc_ddrphy_phyinit_setDefault] Start of dwc_ddrphy_phyinit_setDefault() +// [dwc_ddrphy_phyinit_setDefault] End of dwc_ddrphy_phyinit_setDefault() + +////############################################################## +// +//// dwc_ddrphy_phyinit_userCustom_overrideUserInput is a user-editable function. User can edit this function according to their needs. +//// +//// The purpose of dwc_ddrphy_phyinit_userCustom_overrideUserInput() is to override any +//// any field in Phyinit data structure set by dwc_ddrphy_phyinit_setDefault() +//// User should only override values in userInputBasic and userInputAdvanced. +//// IMPORTANT: in this function, user shall not override any values in the +//// messageblock directly on the data structue as the might be overwritten by +//// dwc_ddrphy_phyinit_calcMb(). Use dwc_ddrphy_phyinit_setMb() to set +//// messageblock parameters for override values to remain pervasive if +//// desired +// +////############################################################## + +dwc_ddrphy_phyinit_userCustom_overrideUserInput(); +// +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramType' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DimmType' to 0x4 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumDbyte' to 0x2 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumActiveDbyteDfi0' to 0x2 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumAnib' to 0xa +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumRank_dfi0' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[0]' to 0x10 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[1]' to 0x10 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[2]' to 0x10 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[3]' to 0x10 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumPStates' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Frequency[0]' to 0x640 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PllBypass[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DfiFreqRatio[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Dfi1Exists' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'D4RxPreambleLength[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'D4TxPreambleLength[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'ExtCalResVal' to 0xf0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Is2Ttiming[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'ODTImpedance[0]' to 0x78 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxImpedance[0]' to 0x3c +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'MemAlertEn' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'MtestPUImp' to 0xf0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DisDynAdrTri[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrTrainInterval[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrMaxReqToAck[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrCtrlMode[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'WDQSExt' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'CalInterval' to 0x9 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'CalOnce' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'RxEnBackOff' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TrainSequenceCtrl' to 0x31f +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'SnpsUmctlOpt' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'SnpsUmctlF0RC5x[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseDQ[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallDQ[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseAC' to 0x45 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallAC' to 0xa +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'IsHighVDD' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseCK' to 0x52 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallCK' to 0x12 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DisablePmuEcc' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnableMAlertAsync' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Apb32BitMode' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tDQS2DQ' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tDQSCK' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_override' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][1]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][2]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][3]' to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MsgMisc to 0x7 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].Pstate to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].PllBypassEn to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].DRAMFreq to 0xc80 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].PhyVref to 0x40 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].DramType to 0x2 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].DisabledDbyte to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].EnabledDQs to 0x10 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].CsPresent to 0x1 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].CsPresentD0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].CsPresentD1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AddrMirror to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].PhyCfg to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].SequenceCtrl to 0x31f +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].HdtCtrl to 0xc8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].PhyConfigOverride to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].DFIMRLMargin to 0x2 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR0 to 0x2150 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR1 to 0x101 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR2 to 0x228 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR3 to 0x400 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR4 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR5 to 0x500 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR6 to 0x104f +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].X16Present to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].CsSetupGDDec to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl4 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl5 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl6 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl7 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib0 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib1 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib2 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib3 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib4 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib5 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib6 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib7 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib8 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib9 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib10 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib11 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib12 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib13 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib14 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib15 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib16 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib17 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib18 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib19 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib0 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib1 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib2 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib3 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib4 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib5 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib6 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib7 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib8 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib9 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib10 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib11 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib12 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib13 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib14 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib15 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib16 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib17 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib18 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib19 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib0 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib1 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib2 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib3 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib4 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib5 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib6 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib7 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib8 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib9 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib10 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib11 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib12 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib13 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib14 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib15 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib16 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib17 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib18 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib19 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib0 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib1 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib2 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib3 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib4 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib5 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib6 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib7 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib8 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib9 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib10 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib11 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib12 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib13 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib14 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib15 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib16 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib17 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib18 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib19 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].ALT_CAS_L to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].ALT_WCAS_L to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].D4Misc to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].ExtTrainOpt to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].NVDIMM to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MsgMisc to 0x7 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].Pstate to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].PllBypassEn to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].DRAMFreq to 0xc80 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].PhyVref to 0x40 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].DramType to 0x2 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].DisabledDbyte to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].EnabledDQs to 0x10 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].CsPresent to 0x1 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].CsPresentD0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].CsPresentD1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AddrMirror to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].PhyCfg to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].SequenceCtrl to 0x31f +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].HdtCtrl to 0xc8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].PhyConfigOverride to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].DFIMRLMargin to 0x2 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR0 to 0x2150 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR1 to 0x101 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR2 to 0x228 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR3 to 0x400 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR4 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR5 to 0x500 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR6 to 0x104f +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].X16Present to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].CsSetupGDDec to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl4 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl5 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl6 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl7 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib0 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib1 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib2 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib3 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib4 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib5 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib6 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib7 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib8 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib9 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib10 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib11 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib12 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib13 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib14 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib15 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib16 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib17 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib18 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib19 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib0 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib1 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib2 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib3 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib4 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib5 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib6 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib7 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib8 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib9 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib10 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib11 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib12 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib13 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib14 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib15 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib16 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib17 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib18 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib19 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib0 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib1 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib2 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib3 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib4 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib5 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib6 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib7 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib8 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib9 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib10 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib11 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib12 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib13 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib14 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib15 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib16 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib17 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib18 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib19 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib0 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib1 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib2 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib3 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib4 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib5 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib6 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib7 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib8 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib9 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib10 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib11 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib12 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib13 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib14 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib15 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib16 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib17 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib18 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib19 to 0xf +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].ALT_CAS_L to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].ALT_WCAS_L to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].D4Misc to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].ExtTrainOpt to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].NVDIMM to 0x0 +// [dwc_ddrphy_phyinit_userCustom_overrideUserInput] End of dwc_ddrphy_phyinit_userCustom_overrideUserInput() +//[dwc_ddrphy_phyinit_calcMb] Start of dwc_ddrphy_phyinit_calcMb() +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].DramType override to 0x2 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].Pstate override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].DRAMFreq override to 0xc80 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].PllBypassEn override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].EnabledDQs override to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].PhyCfg override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].DisabledDbyte override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].X16Present override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].DramType to 0x2 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].Pstate to 0x1 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].DRAMFreq to 0x856 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].PllBypassEn to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].EnabledDQs to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].PhyCfg to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].DisabledDbyte to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].X16Present to 0x1 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].DramType to 0x2 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].Pstate to 0x2 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].DRAMFreq to 0x74a +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].PllBypassEn to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].EnabledDQs to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].PhyCfg to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].DisabledDbyte to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].X16Present to 0x1 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].DramType to 0x2 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].Pstate to 0x3 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].DRAMFreq to 0x640 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].PllBypassEn to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].EnabledDQs to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].PhyCfg to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].DisabledDbyte to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].X16Present to 0x1 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].DramType override to 0x2 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].Pstate override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].DRAMFreq override to 0xc80 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].PllBypassEn override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].EnabledDQs override to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].PhyCfg override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].DisabledDbyte override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].X16Present override to 0x0 +////[dwc_ddrphy_phyinit_calcMb] TG_active[0] = 1 +////[dwc_ddrphy_phyinit_calcMb] TG_active[1] = 0 +////[dwc_ddrphy_phyinit_calcMb] TG_active[2] = 0 +////[dwc_ddrphy_phyinit_calcMb] TG_active[3] = 0 +////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=0] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=0] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=0] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=1] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=1] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=1] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=2] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=2] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=2] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=3] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=3] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=3] = 0 ps +//[dwc_ddrphy_phyinit_calcMb] End of dwc_ddrphy_phyinit_calcMb() +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // Printing values in user input structure +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] pUserInputBasic->Frequency[0] = 1600 +//// [phyinit_print_dat] pUserInputBasic->Frequency[1] = 1067 +//// [phyinit_print_dat] pUserInputBasic->Frequency[2] = 933 +//// [phyinit_print_dat] pUserInputBasic->Frequency[3] = 800 +//// [phyinit_print_dat] pUserInputBasic->NumAnib = 10 +//// [phyinit_print_dat] pUserInputBasic->DramType = 0 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitValOvr = 0 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[0] = 3 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[1] = 3 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[2] = 3 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[3] = 3 +//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[0] = 1 +//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[1] = 1 +//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[2] = 1 +//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[3] = 1 +//// [phyinit_print_dat] pUserInputBasic->NumActiveDbyteDfi0 = 2 +//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[0] = 0 +//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[1] = 0 +//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[2] = 0 +//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[3] = 0 +//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[0] = 16 +//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[1] = 16 +//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[2] = 16 +//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[3] = 16 +//// [phyinit_print_dat] pUserInputBasic->PllBypass[0] = 0 +//// [phyinit_print_dat] pUserInputBasic->PllBypass[1] = 0 +//// [phyinit_print_dat] pUserInputBasic->PllBypass[2] = 0 +//// [phyinit_print_dat] pUserInputBasic->PllBypass[3] = 0 +//// [phyinit_print_dat] pUserInputBasic->Dfi1Exists = 0 +//// [phyinit_print_dat] pUserInputBasic->Train2D = 0 +//// [phyinit_print_dat] pUserInputBasic->NumRank_dfi0 = 1 +//// [phyinit_print_dat] pUserInputBasic->DimmType = 4 +//// [phyinit_print_dat] pUserInputBasic->NumPStates = 1 +//// [phyinit_print_dat] pUserInputBasic->NumDbyte = 2 +//// [phyinit_print_dat] pUserInputAdvanced->DisablePmuEcc = 1 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[1] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[2] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[3] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[4] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[5] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[6] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[7] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlOpt = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[0] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[1] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[2] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[3] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallAC = 10 +//// [phyinit_print_dat] pUserInputAdvanced->CalOnce = 0 +//// [phyinit_print_dat] pUserInputAdvanced->ExtCalResVal = 240 +//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[2] = 11 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[3] = 11 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[4] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[5] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[6] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[7] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->CalInterval = 9 +//// [phyinit_print_dat] pUserInputAdvanced->IsHighVDD = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseAC = 69 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseCK = 82 +//// [phyinit_print_dat] pUserInputAdvanced->RedundantCs_en = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TrainSequenceCtrl = 799 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->MtestPUImp = 240 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[1] = 3 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[2] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[3] = 3 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[4] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[5] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[6] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[7] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AlertRecoveryEnable = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->VREGCtrl_LP2_PwrSavings_En = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[1] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[2] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[3] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallCK = 18 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[0] = 60 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[1] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[2] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[3] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->en_16LogicalRanks_3DS = 0 +//// [phyinit_print_dat] pUserInputAdvanced->RstRxTrkState = 0 +//// [phyinit_print_dat] pUserInputAdvanced->Is2Ttiming[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->Is2Ttiming[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->Is2Ttiming[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->Is2Ttiming[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->MemAlertEn = 0 +//// [phyinit_print_dat] pUserInputAdvanced->rtt_term_en = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->WDQSExt = 0 +//// [phyinit_print_dat] pUserInputAdvanced->en_3DS = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[0] = 120 +//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[1] = 60 +//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[2] = 60 +//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[3] = 60 +//// [phyinit_print_dat] pUserInputAdvanced->EnableMAlertAsync = 0 +//// [phyinit_print_dat] pUserInputAdvanced->Apb32BitMode = 1 +//// [phyinit_print_dat] pUserInputAdvanced->Nibble_ECC = 15 +//// [phyinit_print_dat] pUserInputAdvanced->RxEnBackOff = 1 +//// [phyinit_print_dat] pUserInputAdvanced->ATxImpedance = 53247 +//// [phyinit_print_dat] pUserInputSim->tDQS2DQ = 0 +//// [phyinit_print_dat] pUserInputSim->tDQSCK = 0 +//// [phyinit_print_dat] pUserInputSim->tSTAOFF[0] = 0 +//// [phyinit_print_dat] pUserInputSim->tSTAOFF[1] = 0 +//// [phyinit_print_dat] pUserInputSim->tSTAOFF[2] = 0 +//// [phyinit_print_dat] pUserInputSim->tSTAOFF[3] = 0 +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // Printing values of 1D message block input/inout fields, PState=0 +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] mb_DDR4U_1D[0].AdvTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MsgMisc = 0x7 +//// [phyinit_print_dat] mb_DDR4U_1D[0].Pstate = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].PllBypassEn = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DRAMFreq = 0xc80 +//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyVref = 0x40 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DramType = 0x2 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DisabledDbyte = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].EnabledDQs = 0x10 +//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresent = 0x1 +//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresentD0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresentD1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AddrMirror = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyCfg = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].SequenceCtrl = 0x31f +//// [phyinit_print_dat] mb_DDR4U_1D[0].HdtCtrl = 0xc8 +//// [phyinit_print_dat] mb_DDR4U_1D[0].Rx2D_CmdSpacing = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MREP_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DWL_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyConfigOverride = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DFIMRLMargin = 0x2 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DDR4_RXEN_OFFSET = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR0 = 0x2150 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR1 = 0x101 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR2 = 0x228 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR3 = 0x400 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR5 = 0x500 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR6 = 0x104f +//// [phyinit_print_dat] mb_DDR4U_1D[0].X16Present = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].CsSetupGDDec = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK2 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK3 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK5 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK6 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK7 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl2 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl3 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl5 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl6 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl7 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].ALT_CAS_L = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].ALT_WCAS_L = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].D4Misc = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].ExtTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].NVDIMM = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AdvTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MsgMisc = 0x7 +//// [phyinit_print_dat] mb_DDR4U_1D[0].Pstate = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].PllBypassEn = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DRAMFreq = 0xc80 +//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyVref = 0x40 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DramType = 0x2 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DisabledDbyte = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].EnabledDQs = 0x10 +//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresent = 0x1 +//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresentD0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresentD1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AddrMirror = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyCfg = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].SequenceCtrl = 0x31f +//// [phyinit_print_dat] mb_DDR4U_1D[0].HdtCtrl = 0xc8 +//// [phyinit_print_dat] mb_DDR4U_1D[0].Rx2D_CmdSpacing = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MREP_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DWL_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyConfigOverride = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DFIMRLMargin = 0x2 +//// [phyinit_print_dat] mb_DDR4U_1D[0].DDR4_RXEN_OFFSET = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR0 = 0x2150 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR1 = 0x101 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR2 = 0x228 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR3 = 0x400 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR5 = 0x500 +//// [phyinit_print_dat] mb_DDR4U_1D[0].MR6 = 0x104f +//// [phyinit_print_dat] mb_DDR4U_1D[0].X16Present = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].CsSetupGDDec = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK2 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK3 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK5 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK6 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK7 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl2 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl3 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl5 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl6 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl7 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_1D[0].ALT_CAS_L = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].ALT_WCAS_L = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].D4Misc = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].ExtTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_1D[0].NVDIMM = 0x0 +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // Printing values of 2D message block input/inout fields, PState=0 +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] mb_DDR4U_2D[0].AdvTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MsgMisc = 0x7 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Pstate = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].PllBypassEn = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DRAMFreq = 0xc80 +//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyVref = 0x40 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DramType = 0x2 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DisabledDbyte = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].EnabledDQs = 0x10 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresent = 0x1 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresentD0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresentD1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AddrMirror = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyCfg = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].SequenceCtrl = 0x31f +//// [phyinit_print_dat] mb_DDR4U_2D[0].HdtCtrl = 0xc8 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RX2D_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].TX2D_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Share2DVrefResult = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Delay_Weight2D = 0x20 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Voltage_Weight2D = 0x80 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Rx2D_CmdSpacing = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MREP_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DWL_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyConfigOverride = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DFIMRLMargin = 0x2 +//// [phyinit_print_dat] mb_DDR4U_2D[0].VoltageRange2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR1_EQU_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].advSearch_rd2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].advSearch_wr2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].moreDebug2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR6_EQU_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].TX2D_DB_DFE_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsWriteNoise = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AdvTrainOpt2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Misc2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR0 = 0x2150 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR1 = 0x101 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR2 = 0x228 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR3 = 0x400 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR5 = 0x500 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR6 = 0x104f +//// [phyinit_print_dat] mb_DDR4U_2D[0].X16Present = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsSetupGDDec = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK2 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK3 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK5 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK6 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK7 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl2 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl3 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl5 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl6 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl7 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].ALT_CAS_L = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].ALT_WCAS_L = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].D4Misc = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].ExtTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].NVDIMM = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AdvTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MsgMisc = 0x7 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Pstate = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].PllBypassEn = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DRAMFreq = 0xc80 +//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyVref = 0x40 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DramType = 0x2 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DisabledDbyte = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].EnabledDQs = 0x10 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresent = 0x1 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresentD0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresentD1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AddrMirror = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyCfg = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].SequenceCtrl = 0x31f +//// [phyinit_print_dat] mb_DDR4U_2D[0].HdtCtrl = 0xc8 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RX2D_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].TX2D_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Share2DVrefResult = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Delay_Weight2D = 0x20 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Voltage_Weight2D = 0x80 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Rx2D_CmdSpacing = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MREP_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DWL_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyConfigOverride = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].DFIMRLMargin = 0x2 +//// [phyinit_print_dat] mb_DDR4U_2D[0].VoltageRange2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR1_EQU_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].advSearch_rd2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].advSearch_wr2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].moreDebug2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR6_EQU_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].TX2D_DB_DFE_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsWriteNoise = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AdvTrainOpt2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].Misc2D = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR0 = 0x2150 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR1 = 0x101 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR2 = 0x228 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR3 = 0x400 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR5 = 0x500 +//// [phyinit_print_dat] mb_DDR4U_2D[0].MR6 = 0x104f +//// [phyinit_print_dat] mb_DDR4U_2D[0].X16Present = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].CsSetupGDDec = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK2 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK3 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK5 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK6 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK7 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl0 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl1 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl2 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl3 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl4 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl5 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl6 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl7 = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib0 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib1 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib2 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib3 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib4 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib5 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib6 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib7 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib8 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib9 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib10 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib11 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib12 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib13 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib14 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib15 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib16 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib17 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib18 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib19 = 0xf +//// [phyinit_print_dat] mb_DDR4U_2D[0].ALT_CAS_L = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].ALT_WCAS_L = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].D4Misc = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].ExtTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR4U_2D[0].NVDIMM = 0x0 + +////############################################################## +//// +//// Step (A) : Bring up VDD, VDDQ, and VAA +//// +//// The power supplies can come up and stabilize in any order. +//// While the power supplies are coming up, all outputs will be unknown and +//// the values of the inputs are don't cares. +//// +////############################################################## + +dwc_ddrphy_phyinit_userCustom_A_bringupPower(); + +//[dwc_ddrphy_phyinit_userCustom_A_bringupPower] End of dwc_ddrphy_phyinit_userCustom_A_bringupPower() +// +// +////############################################################## +//// +//// 4.3.2(B) Start Clocks and Reset the PHY +//// +//// Following is one possbile sequence to reset the PHY. Other sequences are also possible. +//// See section 5.2.2 of the PUB for other possible reset sequences. +//// +//// 1. Drive PwrOkIn to 0. Note: Reset, DfiClk, and APBCLK can be X. +//// 2. Start DfiClk and APBCLK +//// 3. Drive Reset to 1 and PRESETn_APB to 0. +//// Note: The combination of PwrOkIn=0 and Reset=1 signals a cold reset to the PHY. +//// 4. Wait a minimum of 8 cycles. +//// 5. Drive PwrOkIn to 1. Once the PwrOkIn is asserted (and Reset is still asserted), +//// DfiClk synchronously switches to any legal input frequency. +//// 6. Wait a minimum of 64 cycles. Note: This is the reset period for the PHY. +//// 7. Drive Reset to 0. Note: All DFI and APB inputs must be driven at valid reset states before the deassertion of Reset. +//// 8. Wait a minimum of 1 Cycle. +//// 9. Drive PRESETn_APB to 1 to de-assert reset on the ABP bus. +////10. The PHY is now in the reset state and is ready to accept APB transactions. +//// +////############################################################## +// +// +dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(sdrammc); + +//// [dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy] End of dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy() +// + +////############################################################## +//// +//// Step (C) Initialize PHY Configuration +//// +//// Load the required PHY configuration registers for the appropriate mode and memory configuration +//// +////############################################################## +// + +//// [phyinit_C_initPhyConfig] Start of dwc_ddrphy_phyinit_C_initPhyConfig() +//// [phyinit_C_initPhyConfig] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x1 +dwc_ddrphy_apb_wr(0x200a6, 0x2); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for MASTER +dwc_ddrphy_apb_wr(0x20066, 0x0); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all DBYTEs +dwc_ddrphy_apb_wr(0x10066, 0x0); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x11066, 0x0); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all ANIBs +dwc_ddrphy_apb_wr(0x66, 0x0); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x1066, 0x0); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x2066, 0x0); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x3066, 0x0); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x4066, 0x0); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x5066, 0x0); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x6066, 0x0); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x7066, 0x0); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x8066, 0x0); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x9066, 0x0); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x31 for MASTER +dwc_ddrphy_apb_wr(0x20029, 0xc4); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl1_p0 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x31 for all DBYTEs +dwc_ddrphy_apb_wr(0x10029, 0xc4); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x11029, 0xc4); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl1_p0 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x31 for all ANIBs +dwc_ddrphy_apb_wr(0x29, 0xc4); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x1029, 0xc4); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x2029, 0xc4); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x3029, 0xc4); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x4029, 0xc4); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x5029, 0xc4); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x6029, 0xc4); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x7029, 0xc4); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x8029, 0xc4); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x9029, 0xc4); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate::CsrTxSrc to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate::TxPreDrvMode to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate to 0x0 +//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::CsrTxSrc are technology specific. +//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings + +dwc_ddrphy_apb_wr(0x1005f, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxSlewRate_b0_p0 +dwc_ddrphy_apb_wr(0x1015f, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxSlewRate_b1_p0 +dwc_ddrphy_apb_wr(0x1105f, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxSlewRate_b0_p0 +dwc_ddrphy_apb_wr(0x1115f, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxSlewRate_b1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::ATxPreDrvMode to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 0 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 0 to 0x11e +dwc_ddrphy_apb_wr(0x55, 0x11e); // DWC_DDRPHYA_ANIB0_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 1 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 1 to 0x11e +dwc_ddrphy_apb_wr(0x1055, 0x11e); // DWC_DDRPHYA_ANIB1_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 2 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 2 to 0x11e +dwc_ddrphy_apb_wr(0x2055, 0x11e); // DWC_DDRPHYA_ANIB2_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 3 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 3 to 0x11e +dwc_ddrphy_apb_wr(0x3055, 0x11e); // DWC_DDRPHYA_ANIB3_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 4 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 4 to 0x11e +dwc_ddrphy_apb_wr(0x4055, 0x11e); // DWC_DDRPHYA_ANIB4_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 5 to 0x15a +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 5 to 0x15a +dwc_ddrphy_apb_wr(0x5055, 0x15a); // DWC_DDRPHYA_ANIB5_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 6 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 6 to 0x11e +dwc_ddrphy_apb_wr(0x6055, 0x11e); // DWC_DDRPHYA_ANIB6_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 7 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 7 to 0x11e +dwc_ddrphy_apb_wr(0x7055, 0x11e); // DWC_DDRPHYA_ANIB7_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 8 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 8 to 0x11e +dwc_ddrphy_apb_wr(0x8055, 0x11e); // DWC_DDRPHYA_ANIB8_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 9 to 0x11e +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 9 to 0x11e +dwc_ddrphy_apb_wr(0x9055, 0x11e); // DWC_DDRPHYA_ANIB9_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::CsrATxSrc are technology specific. +//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings + +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::CsrTxOvSrc to 0x172 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::TxCalBaseN to 0x1 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::TxCalBaseP to 0x1 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride to 0x372 +//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for CalPreDriverOverride::CsrTxOvSrc are technology specific. +//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings + +dwc_ddrphy_apb_wr(0x2008c, 0x372); // DWC_DDRPHYA_MASTER0_base0_CalPreDriverOverride +//// [phyinit_C_initPhyConfig] PUB revision is 0x0350. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl2::PllFreqSel to 0x19 based on DfiClk frequency = 800. +dwc_ddrphy_apb_wr(0x200c5, 0x19); // DWC_DDRPHYA_MASTER0_base0_PllCtrl2_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1::PllCpPropCtrl to 0x3 based on DfiClk frequency = 800. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1::PllCpIntCtrl to 0x1 based on DfiClk frequency = 800. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1 to 0x61 based on DfiClk frequency = 800. +dwc_ddrphy_apb_wr(0x200c7, 0x61); // DWC_DDRPHYA_MASTER0_base0_PllCtrl1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllTestMode to 0x400f based on DfiClk frequency = 800. +dwc_ddrphy_apb_wr(0x200ca, 0x400f); // DWC_DDRPHYA_MASTER0_base0_PllTestMode_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4::PllCpPropGsCtrl to 0x6 based on DfiClk frequency = 800. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4::PllCpIntGsCtrl to 0x12 based on DfiClk frequency = 800. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4 to 0xd2 based on DfiClk frequency = 800. +dwc_ddrphy_apb_wr(0x200cc, 0xd2); // DWC_DDRPHYA_MASTER0_base0_PllCtrl4_p0 +//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for PllCtrl1 and PllTestMode are technology specific. +//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult technology specific PHY Databook for recommended settings + +// +////############################################################## +//// +//// Program ARdPtrInitVal based on Frequency and PLL Bypass inputs +//// The values programmed here assume ideal properties of DfiClk +//// and Pclk including: +//// - DfiClk skew +//// - DfiClk jitter +//// - DfiClk PVT variations +//// - Pclk skew +//// - Pclk jitter +//// +//// PLL Bypassed mode: +//// For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 2-5 +//// For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-5 +//// +//// PLL Enabled mode: +//// For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-5 +//// For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 0-5 +//// +////############################################################## +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ARdPtrInitVal to 0x1 +dwc_ddrphy_apb_wr(0x2002e, 0x1); // DWC_DDRPHYA_MASTER0_base0_ARdPtrInitVal_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DisPtrInitClrTxTracking to 0x0 +dwc_ddrphy_apb_wr(0x20051, 0x0); // DWC_DDRPHYA_MASTER0_base0_PtrInitTrackingModeCntrl_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::DDR5RxPreamble to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::DDR5RxPostamble to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl to 0x8 +dwc_ddrphy_apb_wr(0x20024, 0x8); // DWC_DDRPHYA_MASTER0_base0_DqsPreambleControl_p0 +//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl::DllRxPreambleMode to 0x1 +//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl::DllRxBurstLengthMode to 0x0 +//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl to 0x2 +dwc_ddrphy_apb_wr(0x2003a, 0x2); // DWC_DDRPHYA_MASTER0_base0_DbyteDllModeCntrl +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxOdtDrvStren::TxOdtStrenPu to 0x4 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxOdtDrvStren::TxOdtStrenPd to 0x0 +dwc_ddrphy_apb_wr(0x1004d, 0x4); // DWC_DDRPHYA_DBYTE0_base0_TxOdtDrvStren_b0_p0 +dwc_ddrphy_apb_wr(0x1014d, 0x4); // DWC_DDRPHYA_DBYTE0_base0_TxOdtDrvStren_b1_p0 +dwc_ddrphy_apb_wr(0x1104d, 0x4); // DWC_DDRPHYA_DBYTE1_base0_TxOdtDrvStren_b0_p0 +dwc_ddrphy_apb_wr(0x1114d, 0x4); // DWC_DDRPHYA_DBYTE1_base0_TxOdtDrvStren_b1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ADrvStrenP to 0x3f +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ADrvStrenN to 0x3f +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxReserved13x12 to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxCalBaseN to 0x1 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxCalBaseP to 0x1 +dwc_ddrphy_apb_wr(0x43, 0xcfff); // DWC_DDRPHYA_ANIB0_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x1043, 0xcfff); // DWC_DDRPHYA_ANIB1_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x2043, 0xcfff); // DWC_DDRPHYA_ANIB2_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x3043, 0xcfff); // DWC_DDRPHYA_ANIB3_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x4043, 0xcfff); // DWC_DDRPHYA_ANIB4_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x5043, 0xcfff); // DWC_DDRPHYA_ANIB5_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x6043, 0xcfff); // DWC_DDRPHYA_ANIB6_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x7043, 0xcfff); // DWC_DDRPHYA_ANIB7_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x8043, 0xcfff); // DWC_DDRPHYA_ANIB8_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x9043, 0xcfff); // DWC_DDRPHYA_ANIB9_base0_ATxImpedance +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl0::TxStrenEqHiPu to 0xc +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl0::TxStrenEqLoPd to 0xc +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl1::TxStrenPu to 0x3f +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl1::TxStrenPd to 0x3f +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl2::TxStrenEqLoPu to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl2::TxStrenEqHiPd to 0x0 +dwc_ddrphy_apb_wr(0x10041, 0x30c); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl0_b0_p0 +dwc_ddrphy_apb_wr(0x10049, 0xfff); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl1_b0_p0 +dwc_ddrphy_apb_wr(0x1004b, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl2_b0_p0 +dwc_ddrphy_apb_wr(0x10141, 0x30c); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl0_b1_p0 +dwc_ddrphy_apb_wr(0x10149, 0xfff); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl1_b1_p0 +dwc_ddrphy_apb_wr(0x1014b, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl2_b1_p0 +dwc_ddrphy_apb_wr(0x11041, 0x30c); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl0_b0_p0 +dwc_ddrphy_apb_wr(0x11049, 0xfff); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl1_b0_p0 +dwc_ddrphy_apb_wr(0x1104b, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl2_b0_p0 +dwc_ddrphy_apb_wr(0x11141, 0x30c); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl0_b1_p0 +dwc_ddrphy_apb_wr(0x11149, 0xfff); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl1_b1_p0 +dwc_ddrphy_apb_wr(0x1114b, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl2_b1_p0 +//// [phyinit_C_initPhyConfig] Programming DfiMode to 0x1 +dwc_ddrphy_apb_wr(0x20018, 0x1); // DWC_DDRPHYA_MASTER0_base0_DfiMode +//// [phyinit_C_initPhyConfig] Programming DfiCAMode to 0x2 +dwc_ddrphy_apb_wr(0x20075, 0x2); // DWC_DDRPHYA_MASTER0_base0_DfiCAMode +//// [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPd50 to 0x2 +//// [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPu50 to 0x2 +dwc_ddrphy_apb_wr(0x20050, 0x82); // DWC_DDRPHYA_MASTER0_base0_CalDrvStr0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x320 +dwc_ddrphy_apb_wr(0x20008, 0x320); // DWC_DDRPHYA_MASTER0_base0_CalUclkInfo_p0 +//// [phyinit_C_initPhyConfig] Programming CalRate::CalInterval to 0x9 +//// [phyinit_C_initPhyConfig] Programming CalRate::CalOnce to 0x0 +dwc_ddrphy_apb_wr(0x20088, 0x9); // DWC_DDRPHYA_MASTER0_base0_CalRate +//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInSel to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInDAC to 0x1f +//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal to 0xf8 +dwc_ddrphy_apb_wr(0x200b2, 0xf8); // DWC_DDRPHYA_MASTER0_base0_VrefInGlobal_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=0, Upper/Lower=0) to 0x2500 +dwc_ddrphy_apb_wr(0x10043, 0x2500); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl_b0_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=0, Upper/Lower=1) to 0x2500 +dwc_ddrphy_apb_wr(0x10143, 0x2500); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl_b1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=1, Upper/Lower=0) to 0x2500 +dwc_ddrphy_apb_wr(0x11043, 0x2500); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl_b0_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=1, Upper/Lower=1) to 0x2500 +dwc_ddrphy_apb_wr(0x11143, 0x2500); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl_b1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl2 to 0x1c +dwc_ddrphy_apb_wr(0x1004c, 0x1c); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl2_p0 +dwc_ddrphy_apb_wr(0x1104c, 0x1c); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl2_p0 +//// [phyinit_C_initPhyConfig] Programming ATxOdtDrvStren of ANIB_0 to 0x0 +dwc_ddrphy_apb_wr(0x42, 0x0); // DWC_DDRPHYA_ANIB0_base0_ATxOdtDrvStren +//// [phyinit_C_initPhyConfig] Programming ATxOdtDrvStren of ANIB_0 to 0x0 +dwc_ddrphy_apb_wr(0x42, 0x0); // DWC_DDRPHYA_ANIB0_base0_ATxOdtDrvStren +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TristateModeCA::DisDynAdrTri_p0 to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TristateModeCA::DDR2TMode_p0 to 0x0 +dwc_ddrphy_apb_wr(0x20019, 0x5); // DWC_DDRPHYA_MASTER0_base0_TristateModeCA_p0 +//// [phyinit_C_initPhyConfig] Programming DfiFreqXlat* +dwc_ddrphy_apb_wr(0x200f0, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat0 +dwc_ddrphy_apb_wr(0x200f1, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat1 +dwc_ddrphy_apb_wr(0x200f2, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat2 +dwc_ddrphy_apb_wr(0x200f3, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat3 +dwc_ddrphy_apb_wr(0x200f4, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat4 +dwc_ddrphy_apb_wr(0x200f5, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat5 +dwc_ddrphy_apb_wr(0x200f6, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat6 +dwc_ddrphy_apb_wr(0x200f7, 0xf000); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat7 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY0 to 0x64 +dwc_ddrphy_apb_wr(0x2000b, 0x64); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY0_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY1 to 0xc8 +dwc_ddrphy_apb_wr(0x2000c, 0xc8); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY2 to 0x2bc +dwc_ddrphy_apb_wr(0x2000d, 0x2bc); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY2_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY3 to 0x2c +dwc_ddrphy_apb_wr(0x2000e, 0x2c); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY3_p0 +//// [phyinit_C_initPhyConfig] Disabling DBYTE 0 Lane 8 (DBI) Receiver to save power. +dwc_ddrphy_apb_wr(0x1004a, 0x500); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl1 +//// [phyinit_C_initPhyConfig] Disabling DBYTE 1 Lane 8 (DBI) Receiver to save power. +dwc_ddrphy_apb_wr(0x1104a, 0x500); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl1 +//// [phyinit_C_initPhyConfig] Programming MasterX4Config::X4TG to 0x0 +dwc_ddrphy_apb_wr(0x20025, 0x0); // DWC_DDRPHYA_MASTER0_base0_MasterX4Config +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming GPR7(csrAlertRecovery) to 0x0 +dwc_ddrphy_apb_wr(0x90307, 0x0); // DWC_DDRPHYA_INITENG0_base0_Seq0BGPR7_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DMIPinPresent::RdDbiEnabled to 0x0 +dwc_ddrphy_apb_wr(0x2002d, 0x0); // DWC_DDRPHYA_MASTER0_base0_DMIPinPresent_p0 +// [phyinit_C_initPhyConfig] Programming TimingModeCntrl::Dly64Prec to 0x0 +dwc_ddrphy_apb_wr(0x20040, 0x0); // DWC_DDRPHYA_MASTER0_base0_TimingModeCntrl +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for MASTER +dwc_ddrphy_apb_wr(0x20066, 0x1); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for all DBYTEs +dwc_ddrphy_apb_wr(0x10066, 0x1); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x11066, 0x1); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for all ANIBs +dwc_ddrphy_apb_wr(0x66, 0x1); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x1066, 0x1); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x2066, 0x1); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x3066, 0x1); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x4066, 0x1); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x5066, 0x1); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x6066, 0x1); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x7066, 0x1); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x8066, 0x1); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x9066, 0x1); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming AcClkDLLControl to 0x1080 +dwc_ddrphy_apb_wr(0x200ea, 0x1080); // DWC_DDRPHYA_MASTER0_base0_AcClkDLLControl_p0 +// [phyinit_C_initPhyConfig] Programming ArcPmuEccCtl to 0x1 +dwc_ddrphy_apb_wr(0xc0086, 0x1); // DWC_DDRPHYA_DRTUB0_ArcPmuEccCtl +// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x9820 for MASTER +dwc_ddrphy_apb_wr(0x2002b, 0x9820); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl2 +// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x8020 for all DBYTEs +dwc_ddrphy_apb_wr(0x1002b, 0x8020); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x1102b, 0x8020); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl2 +// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x8020 for all ANIBs +dwc_ddrphy_apb_wr(0x2b, 0x8020); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x102b, 0x8020); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x202b, 0x8020); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x302b, 0x8020); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x402b, 0x8020); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x502b, 0x8020); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x602b, 0x8020); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x702b, 0x8020); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x802b, 0x8020); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x902b, 0x8020); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl2 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for MASTER +dwc_ddrphy_apb_wr(0x20066, 0x0); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all DBYTEs +dwc_ddrphy_apb_wr(0x10066, 0x0); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x11066, 0x0); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all ANIBs +dwc_ddrphy_apb_wr(0x66, 0x0); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x1066, 0x0); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x2066, 0x0); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x3066, 0x0); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x4066, 0x0); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x5066, 0x0); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x6066, 0x0); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x7066, 0x0); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x8066, 0x0); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x9066, 0x0); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Programming VrefDAC0 to 0x3f for all DBYTEs and lanes +// [phyinit_C_initPhyConfig] Programming VrefDAC1 to 0x3f for all DBYTEs and lanes +// [phyinit_C_initPhyConfig] Programming VrefDAC2 to 0x3f for all DBYTEs and lanes +// [phyinit_C_initPhyConfig] Programming VrefDAC3 to 0x3f for all DBYTEs and lanes +dwc_ddrphy_apb_wr(0x10040, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r0_p0 +dwc_ddrphy_apb_wr(0x10030, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r0 +dwc_ddrphy_apb_wr(0x10050, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r0 +dwc_ddrphy_apb_wr(0x10060, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r0 +dwc_ddrphy_apb_wr(0x10140, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r1_p0 +dwc_ddrphy_apb_wr(0x10130, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r1 +dwc_ddrphy_apb_wr(0x10150, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r1 +dwc_ddrphy_apb_wr(0x10160, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r1 +dwc_ddrphy_apb_wr(0x10240, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r2_p0 +dwc_ddrphy_apb_wr(0x10230, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r2 +dwc_ddrphy_apb_wr(0x10250, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r2 +dwc_ddrphy_apb_wr(0x10260, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r2 +dwc_ddrphy_apb_wr(0x10340, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r3_p0 +dwc_ddrphy_apb_wr(0x10330, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r3 +dwc_ddrphy_apb_wr(0x10350, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r3 +dwc_ddrphy_apb_wr(0x10360, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r3 +dwc_ddrphy_apb_wr(0x10440, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r4_p0 +dwc_ddrphy_apb_wr(0x10430, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r4 +dwc_ddrphy_apb_wr(0x10450, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r4 +dwc_ddrphy_apb_wr(0x10460, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r4 +dwc_ddrphy_apb_wr(0x10540, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r5_p0 +dwc_ddrphy_apb_wr(0x10530, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r5 +dwc_ddrphy_apb_wr(0x10550, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r5 +dwc_ddrphy_apb_wr(0x10560, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r5 +dwc_ddrphy_apb_wr(0x10640, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r6_p0 +dwc_ddrphy_apb_wr(0x10630, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r6 +dwc_ddrphy_apb_wr(0x10650, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r6 +dwc_ddrphy_apb_wr(0x10660, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r6 +dwc_ddrphy_apb_wr(0x10740, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r7_p0 +dwc_ddrphy_apb_wr(0x10730, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r7 +dwc_ddrphy_apb_wr(0x10750, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r7 +dwc_ddrphy_apb_wr(0x10760, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r7 +dwc_ddrphy_apb_wr(0x10840, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r8_p0 +dwc_ddrphy_apb_wr(0x10830, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r8 +dwc_ddrphy_apb_wr(0x10850, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r8 +dwc_ddrphy_apb_wr(0x10860, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r8 +dwc_ddrphy_apb_wr(0x11040, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r0_p0 +dwc_ddrphy_apb_wr(0x11030, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r0 +dwc_ddrphy_apb_wr(0x11050, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r0 +dwc_ddrphy_apb_wr(0x11060, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r0 +dwc_ddrphy_apb_wr(0x11140, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r1_p0 +dwc_ddrphy_apb_wr(0x11130, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r1 +dwc_ddrphy_apb_wr(0x11150, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r1 +dwc_ddrphy_apb_wr(0x11160, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r1 +dwc_ddrphy_apb_wr(0x11240, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r2_p0 +dwc_ddrphy_apb_wr(0x11230, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r2 +dwc_ddrphy_apb_wr(0x11250, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r2 +dwc_ddrphy_apb_wr(0x11260, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r2 +dwc_ddrphy_apb_wr(0x11340, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r3_p0 +dwc_ddrphy_apb_wr(0x11330, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r3 +dwc_ddrphy_apb_wr(0x11350, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r3 +dwc_ddrphy_apb_wr(0x11360, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r3 +dwc_ddrphy_apb_wr(0x11440, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r4_p0 +dwc_ddrphy_apb_wr(0x11430, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r4 +dwc_ddrphy_apb_wr(0x11450, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r4 +dwc_ddrphy_apb_wr(0x11460, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r4 +dwc_ddrphy_apb_wr(0x11540, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r5_p0 +dwc_ddrphy_apb_wr(0x11530, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r5 +dwc_ddrphy_apb_wr(0x11550, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r5 +dwc_ddrphy_apb_wr(0x11560, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r5 +dwc_ddrphy_apb_wr(0x11640, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r6_p0 +dwc_ddrphy_apb_wr(0x11630, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r6 +dwc_ddrphy_apb_wr(0x11650, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r6 +dwc_ddrphy_apb_wr(0x11660, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r6 +dwc_ddrphy_apb_wr(0x11740, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r7_p0 +dwc_ddrphy_apb_wr(0x11730, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r7 +dwc_ddrphy_apb_wr(0x11750, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r7 +dwc_ddrphy_apb_wr(0x11760, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r7 +dwc_ddrphy_apb_wr(0x11840, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r8_p0 +dwc_ddrphy_apb_wr(0x11830, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r8 +dwc_ddrphy_apb_wr(0x11850, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r8 +dwc_ddrphy_apb_wr(0x11860, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r8 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DfiFreqRatio_p0 to 0x1 +dwc_ddrphy_apb_wr(0x200fa, 0x1); // DWC_DDRPHYA_MASTER0_base0_DfiFreqRatio_p0 +//// [phyinit_C_initPhyConfig] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x0 +dwc_ddrphy_apb_wr(0x200a6, 0x0); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables +//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=0) to 0xc +dwc_ddrphy_apb_wr(0x28, 0xc); // DWC_DDRPHYA_ANIB0_base0_AForceTriCont +//// [phyinit_C_initPhyConfig] End of dwc_ddrphy_phyinit_C_initPhyConfig() +// +// +////############################################################## +//// +//// dwc_ddrphy_phyinit_userCustom_customPreTrain is a user-editable function. +//// +//// The purpose of dwc_ddrphy_phyinit_userCustom_customPreTrain() is to override any +//// any message block fields calculated by Phyinit in dwc_ddrphy_phyinit_calcMb() or to +//// override any CSR values programmed by Phyinit in dwc_ddrphy_phyinit_C_initPhyConfig(). +//// This function is executed before training and thus any override here might affect +//// training result. +//// +//// IMPORTANT: in this function, user shall not override any values in userInputBasic and +//// userInputAdvanced data structures. Use dwc_ddrphy_phyinit_userCustom_overrideUserInput() +//// to modify values in those data structures. +//// +////############################################################## +// +//// [phyinit_userCustom_customPreTrain] Start of dwc_ddrphy_phyinit_userCustom_customPreTrain() +//// [phyinit_userCustom_customPreTrain] End of dwc_ddrphy_phyinit_userCustom_customPreTrain() +//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=0) +// +// +////############################################################## +//// +//// (D) Load the 1D IMEM image +//// +//// This function loads the training firmware IMEM image into the SRAM. +//// See PhyInit App Note for detailed description and function usage +//// +////############################################################## +// +// +//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Programming MemResetL to 0x2 +dwc_ddrphy_apb_wr(0x20060, 0x2); // DWC_DDRPHYA_MASTER0_base0_MemResetL +// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-16-52-55/firmware/Latest/training/ddr4/ddr4_pmu_train_imem.incv + +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +//// This allows the memory controller unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x50000 size 0x8000 +//#ifdef TRAIN_LOADBIN +dwc_ddrphy_phyinit_userCustom_D_loadIMEM(sdrammc, 0); +//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000 +//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +//// This allows the firmware unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] End of dwc_ddrphy_phyinit_D_loadIMEM() +// +// +////############################################################## +//// +//// 4.3.5(E) Set the PHY input clocks to the desired frequency for pstate 0 +//// +//// Set the PHY input Dfi Clk to the desired operating frequency associated with the given Pstate. Before proceeding to the next step, +//// the clock should be stable at the new frequency. For more information on clocking requirements, see "Clocks" on page <XXX>. +//// +////############################################################## +// +dwc_ddrphy_phyinit_userCustom_E_setDfiClk(sdrammc); + +// +//// [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() +//// [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=0) +// +// +////############################################################## +//// +//// 4.3.5(F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware +//// +//// The procedure is as follows: +//// +////############################################################## +// +// +// +//// 1. Load the firmware DMEM segment to initialize the data structures. +// +//// 2. Write the Firmware Message Block with the required contents detailing the training parameters. +// +// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-16-52-55/firmware/Latest/training/ddr4/ddr4_pmu_train_dmem.incv + +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +//// This allows the memory controller unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x58000 size 0x8000 +//#ifdef TRAIN_LOADBIN +dwc_ddrphy_phyinit_userCustom_F_loadDMEM(sdrammc, 0, 0); + +dwc_ddrphy_apb_wr_32b(0x58000, 0x100); +dwc_ddrphy_apb_wr_32b(0x58002, 0xc800000); +dwc_ddrphy_apb_wr_32b(0x58004, 0x0); +dwc_ddrphy_apb_wr_32b(0x58006, 0x10000240); +dwc_ddrphy_apb_wr_32b(0x58008, 0x1); +dwc_ddrphy_apb_wr_32b(0x5800a, 0x31f0000); +dwc_ddrphy_apb_wr_32b(0x5800c, 0xc8); +dwc_ddrphy_apb_wr_32b(0x5800e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58010, 0x0); +dwc_ddrphy_apb_wr_32b(0x58012, 0x2); +dwc_ddrphy_apb_wr_32b(0x58014, 0x0); +dwc_ddrphy_apb_wr_32b(0x58016, 0x0); +dwc_ddrphy_apb_wr_32b(0x58018, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58020, 0x0); +dwc_ddrphy_apb_wr_32b(0x58022, 0x0); +dwc_ddrphy_apb_wr_32b(0x58024, 0x0); +dwc_ddrphy_apb_wr_32b(0x58026, 0x0); +dwc_ddrphy_apb_wr_32b(0x58028, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802e, 0x21500000); +dwc_ddrphy_apb_wr_32b(0x58030, 0x2280101); +dwc_ddrphy_apb_wr_32b(0x58032, 0x400); +dwc_ddrphy_apb_wr_32b(0x58034, 0x104f0500); +dwc_ddrphy_apb_wr_32b(0x58036, 0x0); +dwc_ddrphy_apb_wr_32b(0x58038, 0x0); +dwc_ddrphy_apb_wr_32b(0x5803a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5803c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5803e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58040, 0x0); +dwc_ddrphy_apb_wr_32b(0x58042, 0xf0f0000); +dwc_ddrphy_apb_wr_32b(0x58044, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58046, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58048, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5804a, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5804c, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5804e, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58050, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58052, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58054, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58056, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58058, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5805a, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5805c, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5805e, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58060, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58062, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58064, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58066, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58068, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5806a, 0xf0f); +dwc_ddrphy_apb_wr_32b(0x5806c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5806e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58070, 0x0); +dwc_ddrphy_apb_wr_32b(0x58072, 0x0); +dwc_ddrphy_apb_wr_32b(0x58074, 0x0); +dwc_ddrphy_apb_wr_32b(0x58076, 0x0); +dwc_ddrphy_apb_wr_32b(0x58078, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58080, 0x0); +dwc_ddrphy_apb_wr_32b(0x58082, 0x0); +dwc_ddrphy_apb_wr_32b(0x58084, 0x0); +dwc_ddrphy_apb_wr_32b(0x58086, 0x0); +dwc_ddrphy_apb_wr_32b(0x58088, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58090, 0x0); +dwc_ddrphy_apb_wr_32b(0x58092, 0x0); +dwc_ddrphy_apb_wr_32b(0x58094, 0x0); +dwc_ddrphy_apb_wr_32b(0x58096, 0x0); +dwc_ddrphy_apb_wr_32b(0x58098, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809e, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580aa, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ac, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ae, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ba, 0x0); +dwc_ddrphy_apb_wr_32b(0x580bc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580be, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ca, 0x0); +dwc_ddrphy_apb_wr_32b(0x580cc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ce, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580da, 0x0); +dwc_ddrphy_apb_wr_32b(0x580dc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580de, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ea, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ec, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ee, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fa, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fe, 0x0); +dwc_ddrphy_apb_wr_32b(0x58100, 0x0); +dwc_ddrphy_apb_wr_32b(0x58102, 0x0); +dwc_ddrphy_apb_wr_32b(0x58104, 0x0); +dwc_ddrphy_apb_wr_32b(0x58106, 0x0); +dwc_ddrphy_apb_wr_32b(0x58108, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58110, 0x0); +dwc_ddrphy_apb_wr_32b(0x58112, 0x0); +dwc_ddrphy_apb_wr_32b(0x58114, 0x0); +dwc_ddrphy_apb_wr_32b(0x58116, 0x0); +dwc_ddrphy_apb_wr_32b(0x58118, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58120, 0x0); +dwc_ddrphy_apb_wr_32b(0x58122, 0x0); +dwc_ddrphy_apb_wr_32b(0x58124, 0x0); +dwc_ddrphy_apb_wr_32b(0x58126, 0x0); +dwc_ddrphy_apb_wr_32b(0x58128, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58130, 0x0); +dwc_ddrphy_apb_wr_32b(0x58132, 0x0); +dwc_ddrphy_apb_wr_32b(0x58134, 0x0); +dwc_ddrphy_apb_wr_32b(0x58136, 0x0); +dwc_ddrphy_apb_wr_32b(0x58138, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58140, 0x0); +dwc_ddrphy_apb_wr_32b(0x58142, 0x0); +dwc_ddrphy_apb_wr_32b(0x58144, 0x0); +dwc_ddrphy_apb_wr_32b(0x58146, 0x0); +dwc_ddrphy_apb_wr_32b(0x58148, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58150, 0x0); +dwc_ddrphy_apb_wr_32b(0x58152, 0x0); +dwc_ddrphy_apb_wr_32b(0x58154, 0x0); +dwc_ddrphy_apb_wr_32b(0x58156, 0x0); +dwc_ddrphy_apb_wr_32b(0x58158, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58160, 0x0); +dwc_ddrphy_apb_wr_32b(0x58162, 0x0); +dwc_ddrphy_apb_wr_32b(0x58164, 0x0); +dwc_ddrphy_apb_wr_32b(0x58166, 0x0); +dwc_ddrphy_apb_wr_32b(0x58168, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58170, 0x0); +dwc_ddrphy_apb_wr_32b(0x58172, 0x0); +dwc_ddrphy_apb_wr_32b(0x58174, 0x0); +dwc_ddrphy_apb_wr_32b(0x58176, 0x0); +dwc_ddrphy_apb_wr_32b(0x58178, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58180, 0x0); +dwc_ddrphy_apb_wr_32b(0x58182, 0x0); +dwc_ddrphy_apb_wr_32b(0x58184, 0x0); +dwc_ddrphy_apb_wr_32b(0x58186, 0x0); +dwc_ddrphy_apb_wr_32b(0x58188, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58190, 0x0); +dwc_ddrphy_apb_wr_32b(0x58192, 0x0); +dwc_ddrphy_apb_wr_32b(0x58194, 0x0); +dwc_ddrphy_apb_wr_32b(0x58196, 0x0); +dwc_ddrphy_apb_wr_32b(0x58198, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819e, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581aa, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ac, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ae, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ba, 0x0); +dwc_ddrphy_apb_wr_32b(0x581bc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581be, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ca, 0x0); +dwc_ddrphy_apb_wr_32b(0x581cc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ce, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581da, 0x0); +dwc_ddrphy_apb_wr_32b(0x581dc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581de, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ea, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ec, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ee, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fa, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fe, 0x0); +//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000 +//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +//// This allows the firmware unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() +// +// +////############################################################## +//// +//// 4.3.7(G) Execute the Training Firmware +//// +//// The training firmware is executed with the following procedure: +//// +////############################################################## +// +// +//// 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and +//// ResetToMicro fields to 1 (all other fields should be zero). +//// Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +dwc_ddrphy_apb_wr(0xd0099, 0x9); // DWC_DDRPHYA_APBONLY0_MicroReset +dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset +// +//// 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. +dwc_ddrphy_apb_wr(0xd0099, 0x0); // DWC_DDRPHYA_APBONLY0_MicroReset +// +//// 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" +//// 4.3.7 3. Wait for the training firmware to complete. Implement timeout function or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. +dwc_ddrphy_phyinit_userCustom_G_waitFwDone(sdrammc); + +//// [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() +//// 4. Halt the microcontroller." +dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset +dwc_ddrphy_apb_wr(0x20089, 0x0); // DWC_DDRPHYA_MASTER0_base0_CalZap +//// [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW() +// +// +////############################################################## +//// +//// 4.3.8(H) Read the Message Block results +//// +//// The procedure is as follows: +//// +////############################################################## +// +// +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +// +//2. Read the Firmware Message Block to obtain the results from the training. +//This can be accomplished by issuing APB read commands to the DMEM addresses. +//Example: +//if (Train2D) +//{ +// _read_2d_message_block_outputs_ +//} +//else +//{ +// _read_1d_message_block_outputs_ +//} +//This can be accomplished by issuing APB read commands to the DMEM addresses. +dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(sdrammc, 0); + +//[dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock() +//// 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// 4. If training is required at another frequency, repeat the operations starting at step (E). +//// [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() +// +// +////############################################################## +//// +//// 4.3.5(E) Set the PHY input clocks to the desired frequency for pstate 0 +//// +//// Set the PHY input Dfi Clk to the desired operating frequency associated with the given Pstate. Before proceeding to the next step, +//// the clock should be stable at the new frequency. For more information on clocking requirements, see "Clocks" on page <XXX>. +//// +////############################################################## +// +dwc_ddrphy_phyinit_userCustom_E_setDfiClk(sdrammc); + +// +//// [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() +//// [dwc_ddrphy_phyinit_D_loadIMEM, 2D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=1) +// +// +////############################################################## +//// +//// (D) Load the 2D IMEM image +//// +//// This function loads the training firmware IMEM image into the SRAM. +//// See PhyInit App Note for detailed description and function usage +//// +////############################################################## +// +// +// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-16-52-55/firmware/Latest/training/ddr4_2d/ddr4_2d_pmu_train_imem.incv + +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +//// This allows the memory controller unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x50000 size 0x8000 +dwc_ddrphy_phyinit_userCustom_D_loadIMEM(sdrammc, 1); +//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000 +//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +//// This allows the firmware unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_D_loadIMEM, 2D] End of dwc_ddrphy_phyinit_D_loadIMEM() +//// [phyinit_F_loadDMEM, 2D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=1) +// +// +////############################################################## +//// +//// 4.3.5(F) Load the 2D DMEM image and write the 2D Message Block parameters for the training firmware +//// +//// The procedure is as follows: +//// +////############################################################## +// +// +// +//// 1. Load the firmware DMEM segment to initialize the data structures. +// +//// 2. Write the Firmware Message Block with the required contents detailing the training parameters. +// +// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-16-52-55/firmware/Latest/training/ddr4_2d/ddr4_2d_pmu_train_dmem.incv + +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +//// This allows the memory controller unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x58000 size 0x8000 +dwc_ddrphy_phyinit_userCustom_F_loadDMEM(sdrammc, 0, 1); +dwc_ddrphy_apb_wr_32b(0x58000, 0x100); +dwc_ddrphy_apb_wr_32b(0x58002, 0xc800000); +dwc_ddrphy_apb_wr_32b(0x58004, 0x0); +dwc_ddrphy_apb_wr_32b(0x58006, 0x10000240); +dwc_ddrphy_apb_wr_32b(0x58008, 0x1); +//printf("- <DWC_DDRPHY/TRAIN>: Override 2D DMEM image for SequenceCtrl, RX2D_TrainOpt, TX2D_TrainOpt, Delay_Weight2D, and Voltage_Weight2D\n"); +// uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5800b, Direction=In + // SequenceCtrl[0] = Run DevInit - Device/PHY initialization. Should always be set + // SequenceCtrl[5] = Run rd2D - 2d read dqs training + // SequenceCtrl[6] = Run wr2D - 2d write dq training +dwc_ddrphy_apb_wr_32b(0x5800a, 0x0610000); + +// Redmine 1392: To speed up data collection, set the voltage and delay step size in Rx2D_TrainOpt and Tx2D_TrainOpt to its maximum value. +// uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5800c, Direction=In + // 0x04 = Maximal debug messages (e.g., Eye contours) + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only +// uint8_t RX2D_TrainOpt; // Byte offset 0x19, CSR Addr 0x5800c, Direction=In +// uint8_t TX2D_TrainOpt; // Byte offset 0x1a, CSR Addr 0x5800d, Direction=In + #ifdef DWC_DEBUG +//dwc_ddrphy_apb_wr_32b(0x5800c, 0x001e1e0a); + #else +//dwc_ddrphy_apb_wr_32b(0x5800c, 0x001e1ec8); +dwc_ddrphy_apb_wr_32b(0x5800c, 0x000000c8); + #endif +// uint8_t Delay_Weight2D; // Byte offset 0x1c, CSR Addr 0x5800e, Direction=In +// uint8_t Voltage_Weight2D; // Byte offset 0x1d, CSR Addr 0x5800e, Direction=In +dwc_ddrphy_apb_wr_32b(0x5800e, 0x8020); + +dwc_ddrphy_apb_wr_32b(0x58010, 0x0); +dwc_ddrphy_apb_wr_32b(0x58012, 0x2); +dwc_ddrphy_apb_wr_32b(0x58014, 0x0); +dwc_ddrphy_apb_wr_32b(0x58016, 0x0); +dwc_ddrphy_apb_wr_32b(0x58018, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58020, 0x0); +dwc_ddrphy_apb_wr_32b(0x58022, 0x0); +dwc_ddrphy_apb_wr_32b(0x58024, 0x0); +dwc_ddrphy_apb_wr_32b(0x58026, 0x0); +dwc_ddrphy_apb_wr_32b(0x58028, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802e, 0x21500000); +dwc_ddrphy_apb_wr_32b(0x58030, 0x2280101); +dwc_ddrphy_apb_wr_32b(0x58032, 0x400); +dwc_ddrphy_apb_wr_32b(0x58034, 0x104f0500); +dwc_ddrphy_apb_wr_32b(0x58036, 0x0); +dwc_ddrphy_apb_wr_32b(0x58038, 0x0); +dwc_ddrphy_apb_wr_32b(0x5803a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5803c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5803e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58040, 0x0); +dwc_ddrphy_apb_wr_32b(0x58042, 0xf0f0000); +dwc_ddrphy_apb_wr_32b(0x58044, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58046, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58048, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5804a, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5804c, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5804e, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58050, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58052, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58054, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58056, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58058, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5805a, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5805c, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5805e, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58060, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58062, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58064, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58066, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x58068, 0xf0f0f0f); +dwc_ddrphy_apb_wr_32b(0x5806a, 0xf0f); +dwc_ddrphy_apb_wr_32b(0x5806c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5806e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58070, 0x0); +dwc_ddrphy_apb_wr_32b(0x58072, 0x0); +dwc_ddrphy_apb_wr_32b(0x58074, 0x0); +dwc_ddrphy_apb_wr_32b(0x58076, 0x0); +dwc_ddrphy_apb_wr_32b(0x58078, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58080, 0x0); +dwc_ddrphy_apb_wr_32b(0x58082, 0x0); +dwc_ddrphy_apb_wr_32b(0x58084, 0x0); +dwc_ddrphy_apb_wr_32b(0x58086, 0x0); +dwc_ddrphy_apb_wr_32b(0x58088, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58090, 0x0); +dwc_ddrphy_apb_wr_32b(0x58092, 0x0); +dwc_ddrphy_apb_wr_32b(0x58094, 0x0); +dwc_ddrphy_apb_wr_32b(0x58096, 0x0); +dwc_ddrphy_apb_wr_32b(0x58098, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809e, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580aa, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ac, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ae, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ba, 0x0); +dwc_ddrphy_apb_wr_32b(0x580bc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580be, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ca, 0x0); +dwc_ddrphy_apb_wr_32b(0x580cc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ce, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580d8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580da, 0x0); +dwc_ddrphy_apb_wr_32b(0x580dc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580de, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580e8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ea, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ec, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ee, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fa, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fe, 0x0); +dwc_ddrphy_apb_wr_32b(0x58100, 0x0); +dwc_ddrphy_apb_wr_32b(0x58102, 0x0); +dwc_ddrphy_apb_wr_32b(0x58104, 0x0); +dwc_ddrphy_apb_wr_32b(0x58106, 0x0); +dwc_ddrphy_apb_wr_32b(0x58108, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58110, 0x0); +dwc_ddrphy_apb_wr_32b(0x58112, 0x0); +dwc_ddrphy_apb_wr_32b(0x58114, 0x0); +dwc_ddrphy_apb_wr_32b(0x58116, 0x0); +dwc_ddrphy_apb_wr_32b(0x58118, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58120, 0x0); +dwc_ddrphy_apb_wr_32b(0x58122, 0x0); +dwc_ddrphy_apb_wr_32b(0x58124, 0x0); +dwc_ddrphy_apb_wr_32b(0x58126, 0x0); +dwc_ddrphy_apb_wr_32b(0x58128, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58130, 0x0); +dwc_ddrphy_apb_wr_32b(0x58132, 0x0); +dwc_ddrphy_apb_wr_32b(0x58134, 0x0); +dwc_ddrphy_apb_wr_32b(0x58136, 0x0); +dwc_ddrphy_apb_wr_32b(0x58138, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58140, 0x0); +dwc_ddrphy_apb_wr_32b(0x58142, 0x0); +dwc_ddrphy_apb_wr_32b(0x58144, 0x0); +dwc_ddrphy_apb_wr_32b(0x58146, 0x0); +dwc_ddrphy_apb_wr_32b(0x58148, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58150, 0x0); +dwc_ddrphy_apb_wr_32b(0x58152, 0x0); +dwc_ddrphy_apb_wr_32b(0x58154, 0x0); +dwc_ddrphy_apb_wr_32b(0x58156, 0x0); +dwc_ddrphy_apb_wr_32b(0x58158, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58160, 0x0); +dwc_ddrphy_apb_wr_32b(0x58162, 0x0); +dwc_ddrphy_apb_wr_32b(0x58164, 0x0); +dwc_ddrphy_apb_wr_32b(0x58166, 0x0); +dwc_ddrphy_apb_wr_32b(0x58168, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58170, 0x0); +dwc_ddrphy_apb_wr_32b(0x58172, 0x0); +dwc_ddrphy_apb_wr_32b(0x58174, 0x0); +dwc_ddrphy_apb_wr_32b(0x58176, 0x0); +dwc_ddrphy_apb_wr_32b(0x58178, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58180, 0x0); +dwc_ddrphy_apb_wr_32b(0x58182, 0x0); +dwc_ddrphy_apb_wr_32b(0x58184, 0x0); +dwc_ddrphy_apb_wr_32b(0x58186, 0x0); +dwc_ddrphy_apb_wr_32b(0x58188, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58190, 0x0); +dwc_ddrphy_apb_wr_32b(0x58192, 0x0); +dwc_ddrphy_apb_wr_32b(0x58194, 0x0); +dwc_ddrphy_apb_wr_32b(0x58196, 0x0); +dwc_ddrphy_apb_wr_32b(0x58198, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819e, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581aa, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ac, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ae, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ba, 0x0); +dwc_ddrphy_apb_wr_32b(0x581bc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581be, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ca, 0x0); +dwc_ddrphy_apb_wr_32b(0x581cc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ce, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581da, 0x0); +dwc_ddrphy_apb_wr_32b(0x581dc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581de, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ea, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ec, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ee, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fa, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fe, 0x0); +//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000 +//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +//// This allows the firmware unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [phyinit_F_loadDMEM, 2D] End of dwc_ddrphy_phyinit_F_loadDMEM() +// +// +////############################################################## +//// +//// 4.3.7(G) Execute the Training Firmware +//// +//// The training firmware is executed with the following procedure: +//// +////############################################################## +// +// +//// 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and +//// ResetToMicro fields to 1 (all other fields should be zero). +//// Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +dwc_ddrphy_apb_wr(0xd0099, 0x9); // DWC_DDRPHYA_APBONLY0_MicroReset +dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset +// +//// 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. +dwc_ddrphy_apb_wr(0xd0099, 0x0); // DWC_DDRPHYA_APBONLY0_MicroReset +// +//// 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" +//// 4.3.7 3. Wait for the training firmware to complete. Implement timeout function or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. +dwc_ddrphy_phyinit_userCustom_G_waitFwDone(sdrammc); + +//// [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() +//// 4. Halt the microcontroller." +dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset +dwc_ddrphy_apb_wr(0x20089, 0x0); // DWC_DDRPHYA_MASTER0_base0_CalZap +//// [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW() +// +// +////############################################################## +//// +//// 4.3.8(H) Read the Message Block results +//// +//// The procedure is as follows: +//// +////############################################################## +// +// +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +// +//2. Read the Firmware Message Block to obtain the results from the training. +//This can be accomplished by issuing APB read commands to the DMEM addresses. +//Example: +//if (Train2D) +//{ +// _read_2d_message_block_outputs_ +//} +//else +//{ +// _read_1d_message_block_outputs_ +//} +//This can be accomplished by issuing APB read commands to the DMEM addresses. +dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(sdrammc, 1); + +//[dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock() +//// 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// 4. If training is required at another frequency, repeat the operations starting at step (E). +//// [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() +//// [initRuntimeConfigEnableBits] Start of initRuntimeConfigEnableBits() +//// [initRuntimeConfigEnableBits] enableBits[0] = 0x00000009 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A0 = 0x000000ff, rtt_required = 0x0000000f +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A1 = 0x000000ff, rtt_required = 0x0000000f +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A2 = 0x000000ff, rtt_required = 0x0000000f +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A3 = 0x000000ff, rtt_required = 0x0000000f +//// [initRuntimeConfigEnableBits] enableBits[1] = 0x00000000 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B0 = 0x000000ff, rtt_required = 0x0000000f +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B1 = 0x000000ff, rtt_required = 0x0000000f +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B2 = 0x000000ff, rtt_required = 0x0000000f +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B3 = 0x000000ff, rtt_required = 0x0000000f +//// [initRuntimeConfigEnableBits] enableBits[2] = 0x00000000 +//// [initRuntimeConfigEnableBits] End of initRuntimeConfigEnableBits() +//// [phyinit_I_loadPIEImage] Start of dwc_ddrphy_phyinit_I_loadPIEImage() +// +// +////############################################################## +//// +//// 4.3.9(I) Load PHY Init Engine Image +//// +//// Load the PHY Initialization Engine memory with the provided initialization sequence. +//// +////############################################################## +// +// +//// Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +//// This allows the memory controller unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [phyinit_I_loadPIEImage] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x1 +dwc_ddrphy_apb_wr(0x200a6, 0x2); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables +//// [phyinit_I_loadPIEImage] Programming PIE Production Code +//// [phyinit_LoadPIECodeSections] Start of dwc_ddrphy_phyinit_LoadPIECodeSections() +//// [phyinit_LoadPIECodeSections] Moving start address from 0 to 90000 +dwc_ddrphy_apb_wr(0x90000, 0x10); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s0 +dwc_ddrphy_apb_wr(0x90001, 0x400); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s1 +dwc_ddrphy_apb_wr(0x90002, 0x10e); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s2 +dwc_ddrphy_apb_wr(0x90003, 0x0); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s0 +dwc_ddrphy_apb_wr(0x90004, 0x0); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s1 +dwc_ddrphy_apb_wr(0x90005, 0x8); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s2 +//// [phyinit_LoadPIECodeSections] Moving start address from 90006 to 90029 +dwc_ddrphy_apb_wr(0x90029, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s0 +dwc_ddrphy_apb_wr(0x9002a, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s1 +dwc_ddrphy_apb_wr(0x9002b, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s2 +dwc_ddrphy_apb_wr(0x9002c, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s0 +dwc_ddrphy_apb_wr(0x9002d, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s1 +dwc_ddrphy_apb_wr(0x9002e, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s2 +dwc_ddrphy_apb_wr(0x9002f, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s0 +dwc_ddrphy_apb_wr(0x90030, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s1 +dwc_ddrphy_apb_wr(0x90031, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s2 +dwc_ddrphy_apb_wr(0x90032, 0xb); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s0 +dwc_ddrphy_apb_wr(0x90033, 0x480); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s1 +dwc_ddrphy_apb_wr(0x90034, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s2 +dwc_ddrphy_apb_wr(0x90035, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s0 +dwc_ddrphy_apb_wr(0x90036, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s1 +dwc_ddrphy_apb_wr(0x90037, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s2 +dwc_ddrphy_apb_wr(0x90038, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s0 +dwc_ddrphy_apb_wr(0x90039, 0x478); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s1 +dwc_ddrphy_apb_wr(0x9003a, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s2 +dwc_ddrphy_apb_wr(0x9003b, 0x2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s0 +dwc_ddrphy_apb_wr(0x9003c, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s1 +dwc_ddrphy_apb_wr(0x9003d, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s2 +dwc_ddrphy_apb_wr(0x9003e, 0xf); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s0 +dwc_ddrphy_apb_wr(0x9003f, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s1 +dwc_ddrphy_apb_wr(0x90040, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s2 +dwc_ddrphy_apb_wr(0x90041, 0x107); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s0 +dwc_ddrphy_apb_wr(0x90042, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s1 +dwc_ddrphy_apb_wr(0x90043, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s2 +dwc_ddrphy_apb_wr(0x90044, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s0 +dwc_ddrphy_apb_wr(0x90045, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s1 +dwc_ddrphy_apb_wr(0x90046, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s2 +dwc_ddrphy_apb_wr(0x90047, 0x147); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s0 +dwc_ddrphy_apb_wr(0x90048, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s1 +dwc_ddrphy_apb_wr(0x90049, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s2 +dwc_ddrphy_apb_wr(0x9004a, 0x14f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s0 +dwc_ddrphy_apb_wr(0x9004b, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s1 +dwc_ddrphy_apb_wr(0x9004c, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s2 +dwc_ddrphy_apb_wr(0x9004d, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s0 +dwc_ddrphy_apb_wr(0x9004e, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s1 +dwc_ddrphy_apb_wr(0x9004f, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s2 +dwc_ddrphy_apb_wr(0x90050, 0x47); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s0 +dwc_ddrphy_apb_wr(0x90051, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s1 +dwc_ddrphy_apb_wr(0x90052, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s2 +dwc_ddrphy_apb_wr(0x90053, 0x4f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s0 +dwc_ddrphy_apb_wr(0x90054, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s1 +dwc_ddrphy_apb_wr(0x90055, 0x179); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s2 +dwc_ddrphy_apb_wr(0x90056, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s0 +dwc_ddrphy_apb_wr(0x90057, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s1 +dwc_ddrphy_apb_wr(0x90058, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s2 +dwc_ddrphy_apb_wr(0x90059, 0x11); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s0 +dwc_ddrphy_apb_wr(0x9005a, 0x530); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s1 +dwc_ddrphy_apb_wr(0x9005b, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s2 +dwc_ddrphy_apb_wr(0x9005c, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s0 +dwc_ddrphy_apb_wr(0x9005d, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s1 +dwc_ddrphy_apb_wr(0x9005e, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s2 +dwc_ddrphy_apb_wr(0x9005f, 0x14f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s0 +dwc_ddrphy_apb_wr(0x90060, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s1 +dwc_ddrphy_apb_wr(0x90061, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s2 +dwc_ddrphy_apb_wr(0x90062, 0x2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s0 +dwc_ddrphy_apb_wr(0x90063, 0x45a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s1 +dwc_ddrphy_apb_wr(0x90064, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s2 +dwc_ddrphy_apb_wr(0x90065, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s0 +dwc_ddrphy_apb_wr(0x90066, 0x530); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s1 +dwc_ddrphy_apb_wr(0x90067, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s2 +dwc_ddrphy_apb_wr(0x90068, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s0 +dwc_ddrphy_apb_wr(0x90069, 0x65a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s1 +dwc_ddrphy_apb_wr(0x9006a, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s2 +dwc_ddrphy_apb_wr(0x9006b, 0x41); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s0 +dwc_ddrphy_apb_wr(0x9006c, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s1 +dwc_ddrphy_apb_wr(0x9006d, 0x179); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s2 +dwc_ddrphy_apb_wr(0x9006e, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s0 +dwc_ddrphy_apb_wr(0x9006f, 0x618); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s1 +dwc_ddrphy_apb_wr(0x90070, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s2 +dwc_ddrphy_apb_wr(0x90071, 0x40c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s0 +dwc_ddrphy_apb_wr(0x90072, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s1 +dwc_ddrphy_apb_wr(0x90073, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s2 +dwc_ddrphy_apb_wr(0x90074, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s0 +dwc_ddrphy_apb_wr(0x90075, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s1 +dwc_ddrphy_apb_wr(0x90076, 0x48); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s2 +dwc_ddrphy_apb_wr(0x90077, 0x4040); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s0 +dwc_ddrphy_apb_wr(0x90078, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s1 +dwc_ddrphy_apb_wr(0x90079, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s2 +dwc_ddrphy_apb_wr(0x9007a, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s0 +dwc_ddrphy_apb_wr(0x9007b, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s1 +dwc_ddrphy_apb_wr(0x9007c, 0x48); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s2 +dwc_ddrphy_apb_wr(0x9007d, 0x40); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s0 +dwc_ddrphy_apb_wr(0x9007e, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s1 +dwc_ddrphy_apb_wr(0x9007f, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s2 +dwc_ddrphy_apb_wr(0x90080, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s0 +dwc_ddrphy_apb_wr(0x90081, 0x658); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s1 +dwc_ddrphy_apb_wr(0x90082, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s2 +dwc_ddrphy_apb_wr(0x90083, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s0 +dwc_ddrphy_apb_wr(0x90084, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s1 +dwc_ddrphy_apb_wr(0x90085, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s2 +dwc_ddrphy_apb_wr(0x90086, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s0 +dwc_ddrphy_apb_wr(0x90087, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s1 +dwc_ddrphy_apb_wr(0x90088, 0x78); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s2 +dwc_ddrphy_apb_wr(0x90089, 0x549); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s0 +dwc_ddrphy_apb_wr(0x9008a, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s1 +dwc_ddrphy_apb_wr(0x9008b, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s2 +dwc_ddrphy_apb_wr(0x9008c, 0xd49); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s0 +dwc_ddrphy_apb_wr(0x9008d, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s1 +dwc_ddrphy_apb_wr(0x9008e, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s2 +dwc_ddrphy_apb_wr(0x9008f, 0x94c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s0 +dwc_ddrphy_apb_wr(0x90090, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s1 +dwc_ddrphy_apb_wr(0x90091, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s2 +dwc_ddrphy_apb_wr(0x90092, 0x94c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s0 +dwc_ddrphy_apb_wr(0x90093, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s1 +dwc_ddrphy_apb_wr(0x90094, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s2 +dwc_ddrphy_apb_wr(0x90095, 0x442); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s0 +dwc_ddrphy_apb_wr(0x90096, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s1 +dwc_ddrphy_apb_wr(0x90097, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s2 +dwc_ddrphy_apb_wr(0x90098, 0x42); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s0 +dwc_ddrphy_apb_wr(0x90099, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s1 +dwc_ddrphy_apb_wr(0x9009a, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s2 +dwc_ddrphy_apb_wr(0x9009b, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s0 +dwc_ddrphy_apb_wr(0x9009c, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s1 +dwc_ddrphy_apb_wr(0x9009d, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s2 +dwc_ddrphy_apb_wr(0x9009e, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s0 +dwc_ddrphy_apb_wr(0x9009f, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s1 +dwc_ddrphy_apb_wr(0x900a0, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s2 +dwc_ddrphy_apb_wr(0x900a1, 0xa); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s0 +dwc_ddrphy_apb_wr(0x900a2, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s1 +dwc_ddrphy_apb_wr(0x900a3, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s2 +dwc_ddrphy_apb_wr(0x900a4, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s0 +dwc_ddrphy_apb_wr(0x900a5, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s1 +dwc_ddrphy_apb_wr(0x900a6, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s2 +dwc_ddrphy_apb_wr(0x900a7, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s0 +dwc_ddrphy_apb_wr(0x900a8, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s1 +dwc_ddrphy_apb_wr(0x900a9, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s2 +dwc_ddrphy_apb_wr(0x900aa, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s0 +dwc_ddrphy_apb_wr(0x900ab, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s1 +dwc_ddrphy_apb_wr(0x900ac, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s2 +dwc_ddrphy_apb_wr(0x900ad, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s0 +dwc_ddrphy_apb_wr(0x900ae, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s1 +dwc_ddrphy_apb_wr(0x900af, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s2 +dwc_ddrphy_apb_wr(0x900b0, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s0 +dwc_ddrphy_apb_wr(0x900b1, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s1 +dwc_ddrphy_apb_wr(0x900b2, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s2 +dwc_ddrphy_apb_wr(0x900b3, 0xc); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s0 +dwc_ddrphy_apb_wr(0x900b4, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s1 +dwc_ddrphy_apb_wr(0x900b5, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s2 +dwc_ddrphy_apb_wr(0x900b6, 0x3); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s0 +dwc_ddrphy_apb_wr(0x900b7, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s1 +dwc_ddrphy_apb_wr(0x900b8, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s2 +dwc_ddrphy_apb_wr(0x900b9, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s0 +dwc_ddrphy_apb_wr(0x900ba, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s1 +dwc_ddrphy_apb_wr(0x900bb, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s2 +//// [phyinit_LoadPIECodeSections] Matched ANY enable_bits = 8, type = 0 +dwc_ddrphy_apb_wr(0x900bc, 0x3a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s0 +dwc_ddrphy_apb_wr(0x900bd, 0x1e2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s1 +dwc_ddrphy_apb_wr(0x900be, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s2 +dwc_ddrphy_apb_wr(0x900bf, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s0 +dwc_ddrphy_apb_wr(0x900c0, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s1 +dwc_ddrphy_apb_wr(0x900c1, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s2 +dwc_ddrphy_apb_wr(0x900c2, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s0 +dwc_ddrphy_apb_wr(0x900c3, 0x8140); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s1 +dwc_ddrphy_apb_wr(0x900c4, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s2 +dwc_ddrphy_apb_wr(0x900c5, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s0 +dwc_ddrphy_apb_wr(0x900c6, 0x8138); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s1 +dwc_ddrphy_apb_wr(0x900c7, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s2 +//// [phyinit_LoadPIECodeSections] Matched ANY enable_bits = 1, type = 0 +dwc_ddrphy_apb_wr(0x900c8, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s0 +dwc_ddrphy_apb_wr(0x900c9, 0x400); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s1 +dwc_ddrphy_apb_wr(0x900ca, 0x10e); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s2 +dwc_ddrphy_apb_wr(0x900cb, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s0 +dwc_ddrphy_apb_wr(0x900cc, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s1 +dwc_ddrphy_apb_wr(0x900cd, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s2 +dwc_ddrphy_apb_wr(0x900ce, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s0 +dwc_ddrphy_apb_wr(0x900cf, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s1 +dwc_ddrphy_apb_wr(0x900d0, 0x101); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s2 +dwc_ddrphy_apb_wr(0x900d1, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s0 +dwc_ddrphy_apb_wr(0x900d2, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s1 +dwc_ddrphy_apb_wr(0x900d3, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s2 +dwc_ddrphy_apb_wr(0x900d4, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s0 +dwc_ddrphy_apb_wr(0x900d5, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s1 +dwc_ddrphy_apb_wr(0x900d6, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s2 +dwc_ddrphy_apb_wr(0x900d7, 0xf); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s0 +dwc_ddrphy_apb_wr(0x900d8, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s1 +dwc_ddrphy_apb_wr(0x900d9, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s2 +dwc_ddrphy_apb_wr(0x900da, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s0 +dwc_ddrphy_apb_wr(0x900db, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s1 +dwc_ddrphy_apb_wr(0x900dc, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s2 +dwc_ddrphy_apb_wr(0x900dd, 0x47); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s0 +dwc_ddrphy_apb_wr(0x900de, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s1 +dwc_ddrphy_apb_wr(0x900df, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s2 +dwc_ddrphy_apb_wr(0x900e0, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s0 +dwc_ddrphy_apb_wr(0x900e1, 0x618); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s1 +dwc_ddrphy_apb_wr(0x900e2, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s2 +dwc_ddrphy_apb_wr(0x900e3, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s0 +dwc_ddrphy_apb_wr(0x900e4, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s1 +dwc_ddrphy_apb_wr(0x900e5, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s2 +dwc_ddrphy_apb_wr(0x900e6, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s0 +dwc_ddrphy_apb_wr(0x900e7, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s1 +dwc_ddrphy_apb_wr(0x900e8, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s2 +dwc_ddrphy_apb_wr(0x900e9, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s0 +dwc_ddrphy_apb_wr(0x900ea, 0x8140); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s1 +dwc_ddrphy_apb_wr(0x900eb, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s2 +dwc_ddrphy_apb_wr(0x900ec, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s0 +dwc_ddrphy_apb_wr(0x900ed, 0x478); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s1 +dwc_ddrphy_apb_wr(0x900ee, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s2 +dwc_ddrphy_apb_wr(0x900ef, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s0 +dwc_ddrphy_apb_wr(0x900f0, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s1 +dwc_ddrphy_apb_wr(0x900f1, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s2 +dwc_ddrphy_apb_wr(0x900f2, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s0 +dwc_ddrphy_apb_wr(0x900f3, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s1 +dwc_ddrphy_apb_wr(0x900f4, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s2 +dwc_ddrphy_apb_wr(0x900f5, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s0 +dwc_ddrphy_apb_wr(0x900f6, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s1 +dwc_ddrphy_apb_wr(0x900f7, 0x101); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s2 +//// [phyinit_LoadPIECodeSections] Moving start address from 900f8 to 90006 +dwc_ddrphy_apb_wr(0x90006, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s0 +dwc_ddrphy_apb_wr(0x90007, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s1 +dwc_ddrphy_apb_wr(0x90008, 0x8); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s2 +dwc_ddrphy_apb_wr(0x90009, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s0 +dwc_ddrphy_apb_wr(0x9000a, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s1 +dwc_ddrphy_apb_wr(0x9000b, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s2 +//// [phyinit_LoadPIECodeSections] Moving start address from 9000c to d00e7 +dwc_ddrphy_apb_wr(0xd00e7, 0x400); // DWC_DDRPHYA_APBONLY0_SequencerOverride +//// [phyinit_LoadPIECodeSections] End of dwc_ddrphy_phyinit_LoadPIECodeSections() +//seq0b_LoadPstateSeqProductionCode(): --------------------------------------------------------------------------------------------------- +//seq0b_LoadPstateSeqProductionCode(): Programming the 0B sequencer 0b0000 start vector registers with 0. +//seq0b_LoadPstateSeqProductionCode(): Programming the 0B sequencer 0b1111 start vector register with 56. +//seq0b_LoadPstateSeqProductionCode(): --------------------------------------------------------------------------------------------------- +dwc_ddrphy_apb_wr(0x90017, 0x0); // DWC_DDRPHYA_INITENG0_base0_StartVector0b0 +dwc_ddrphy_apb_wr(0x90026, 0x38); // DWC_DDRPHYA_INITENG0_base0_StartVector0b15 +dwc_ddrphy_apb_wr(0x9000c, 0x0); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag0 +dwc_ddrphy_apb_wr(0x9000d, 0x173); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag1 +dwc_ddrphy_apb_wr(0x9000e, 0x60); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag2 +dwc_ddrphy_apb_wr(0x9000f, 0x6110); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag3 +dwc_ddrphy_apb_wr(0x90010, 0x2152); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag4 +dwc_ddrphy_apb_wr(0x90011, 0xdfbd); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag5 +dwc_ddrphy_apb_wr(0x90012, 0xffff); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag6 +dwc_ddrphy_apb_wr(0x90013, 0x6152); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag7 +//// [phyinit_I_loadPIEImage] Programming D4PowerControl::D4CATxDllLP to 0x1 +//// [phyinit_I_loadPIEImage] Programming AcLcdlMasDis to 0xfff +dwc_ddrphy_apb_wr(0x2006d, 0x1); // DWC_DDRPHYA_MASTER0_base0_D4PowerControl +dwc_ddrphy_apb_wr(0x200e8, 0xfff); // DWC_DDRPHYA_MASTER0_base0_AcLcdlMasDis +//// [phyinit_I_loadPIEImage] Turn on calibration and hold idle until dfi_init_start is asserted sequence is triggered. +//// [phyinit_I_loadPIEImage] Programming CalZap to 0x1 +//// [phyinit_I_loadPIEImage] Programming CalRate::CalRun to 0x1 +//// [phyinit_I_loadPIEImage] Programming CalRate to 0x19 +dwc_ddrphy_apb_wr(0x20089, 0x1); // DWC_DDRPHYA_MASTER0_base0_CalZap +dwc_ddrphy_apb_wr(0x20088, 0x19); // DWC_DDRPHYA_MASTER0_base0_CalRate +//// [phyinit_I_loadPIEImage] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x0 +dwc_ddrphy_apb_wr(0x200a6, 0x0); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables +//// Disabling Ucclk (PMU) and Hclk (training hardware) +dwc_ddrphy_apb_wr(0xc0080, 0x0); // DWC_DDRPHYA_DRTUB0_UcclkHclkEnables +//// Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [phyinit_I_loadPIEImage] End of dwc_ddrphy_phyinit_I_loadPIEImage() +// +// +////############################################################## +//// +//// dwc_ddrphy_phyinit_userCustom_customPostTrain is a user-editable function. +//// +//// The purpose of dwc_ddrphy_phyinit_userCustom_customPostTrain() is to override any +//// CSR values programmed by the training firmware or dwc_ddrphy_phyinit_progCsrSkipTrain() +//// This function is executed after training +//// +//// IMPORTANT: in this function, user shall not override any values in userInputBasic and +//// userInputAdvanced data structures. Only CSR programming should be done in this function. +//// +//// Sequence of Events in this function are: +//// 1. Enable APB access. +//// 2. Issue register writes +//// 3. Isolate APB access. +// +////############################################################## +// +dwc_ddrphy_phyinit_userCustom_customPostTrain(); + +//// [dwc_ddrphy_phyinit_userCustom_customPostTrain] End of dwc_ddrphy_phyinit_userCustom_customPostTrain() +//// [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] Start of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() +// +// +////############################################################## +//// +//// 4.3.10(J) Initialize the PHY to Mission Mode through DFI Initialization +//// +//// Initialize the PHY to mission mode as follows: +//// +//// 1. Set the PHY input clocks to the desired frequency. +//// 2. Initialize the PHY to mission mode by performing DFI Initialization. +//// Please see the DFI specification for more information. See the DFI frequency bus encoding in section <XXX>. +//// Note: The PHY training firmware initializes the DRAM state. if skip +//// training is used, the DRAM state is not initialized. +//// +////############################################################## +// +dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(sdrammc); + +// +//// [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] End of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() +// [dwc_ddrphy_phyinit_sequence] End of dwc_ddrphy_phyinit_sequence() +// [dwc_ddrphy_phyinit_main] End of dwc_ddrphy_phyinit_main() diff --git a/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr5-3200-nodimm-train2D.c b/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr5-3200-nodimm-train2D.c new file mode 100644 index 00000000000..d21bcda6fb8 --- /dev/null +++ b/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr5-3200-nodimm-train2D.c @@ -0,0 +1,6930 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + */ +// [dwc_ddrphy_phyinit_main] Start of dwc_ddrphy_phyinit_main() +// [dwc_ddrphy_phyinit_sequence] Start of dwc_ddrphy_phyinit_sequence() +// [dwc_ddrphy_phyinit_initStruct] Start of dwc_ddrphy_phyinit_initStruct() +// [dwc_ddrphy_phyinit_initStruct] End of dwc_ddrphy_phyinit_initStruct() +// [dwc_ddrphy_phyinit_setDefault] Start of dwc_ddrphy_phyinit_setDefault() +// [dwc_ddrphy_phyinit_setDefault] End of dwc_ddrphy_phyinit_setDefault() + +////############################################################## +// +//// dwc_ddrphy_phyinit_userCustom_overrideUserInput is a user-editable function. User can edit this function according to their needs. +//// +//// The purpose of dwc_ddrphy_phyinit_userCustom_overrideUserInput() is to override any +//// any field in Phyinit data structure set by dwc_ddrphy_phyinit_setDefault() +//// User should only override values in userInputBasic and userInputAdvanced. +//// IMPORTANT: in this function, user shall not override any values in the +//// messageblock directly on the data structue as the might be overwritten by +//// dwc_ddrphy_phyinit_calcMb(). Use dwc_ddrphy_phyinit_setMb() to set +//// messageblock parameters for override values to remain pervasive if +//// desired +// +////############################################################## + +dwc_ddrphy_phyinit_userCustom_overrideUserInput(); +// +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramType' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DimmType' to 0x4 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumDbyte' to 0x2 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumActiveDbyteDfi0' to 0x2 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumActiveDbyteDfi1' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumAnib' to 0xa +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumRank_dfi0' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumRank_dfi1' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[0]' to 0x10 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[1]' to 0x10 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[2]' to 0x10 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[3]' to 0x10 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumPStates' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Frequency[0]' to 0x640 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PllBypass[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DfiFreqRatio[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Dfi1Exists' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'ExtCalResVal' to 0xf0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'ODTImpedance[0]' to 0x78 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxImpedance[0]' to 0x3c +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'MemAlertEn' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'MtestPUImp' to 0xf0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DisDynAdrTri[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrTrainInterval[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrMaxReqToAck[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrCtrlMode[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'WDQSExt' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'CalInterval' to 0x9 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'CalOnce' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'RxEnBackOff' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TrainSequenceCtrl' to 0x837f +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'SnpsUmctlOpt' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'SnpsUmctlF0RC5x[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseDQ[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallDQ[0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseAC' to 0x66 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallAC' to 0x26 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'IsHighVDD' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseCK' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallCK' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnTdqs2dqTrackingTg0[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnTdqs2dqTrackingTg1[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnTdqs2dqTrackingTg2[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnTdqs2dqTrackingTg3[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DqsOscRunTimeSel[0]' to 0x100 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnRxDqsTracking[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'D5TxDqPreambleCtrl[0]' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'D5DisableRetraining' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DisablePmuEcc' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnableMAlertAsync' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Apb32BitMode' to 0x1 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tDQS2DQ' to 0x2ee +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tDQSCK' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_override' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][0]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][1]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][2]' to 0x0 +//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][3]' to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MsgMisc to 0x7 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].Pstate to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].PllBypassEn to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].DRAMFreq to 0xc80 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].PhyVref to 0x40 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].D5Misc to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].WL_ADJ to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].SequenceCtrl to 0x837f +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].HdtCtrl to 0xc8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].PhyCfg to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].DFIMRLMargin to 0x2 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].X16Present to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].UseBroadcastMR to 0x1 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].DisabledDbyte to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].CATrainOpt to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].PhyConfigOverride to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].EnabledDQsChA to 0x10 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].CsPresentChA to 0x1 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_A0 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_A0 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_A0 to 0x20 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_A0 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_A0 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_A0 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_A0 to 0xd6 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_A0 to 0x3 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_A0 to 0x11 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_A0 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_A0 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_A0 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_A0 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_A0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_A1 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_A1 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_A1 to 0x20 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_A1 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_A1 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_A1 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_A1 to 0xd6 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_A1 to 0x3 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_A1 to 0x11 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_A1 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_A1 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_A1 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_A1 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_A1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_A2 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_A2 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_A2 to 0x20 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_A2 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_A2 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_A2 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_A2 to 0xd6 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_A2 to 0x3 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_A2 to 0x11 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_A2 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_A2 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_A2 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_A2 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_A2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_A3 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_A3 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_A3 to 0x20 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_A3 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_A3 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_A3 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_A3 to 0xd6 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_A3 to 0x3 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_A3 to 0x11 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_A3 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_A3 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_A3 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_A3 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_A3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].EnabledDQsChB to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].CsPresentChB to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_B0 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_B0 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_B0 to 0x20 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_B0 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_B0 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_B0 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_B0 to 0xd6 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_B0 to 0x3 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_B0 to 0x11 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_B0 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_B0 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_B0 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_B0 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_B0 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_B1 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_B1 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_B1 to 0x20 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_B1 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_B1 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_B1 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_B1 to 0xd6 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_B1 to 0x3 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_B1 to 0x11 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_B1 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_B1 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_B1 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_B1 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_B1 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_B2 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_B2 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_B2 to 0x20 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_B2 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_B2 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_B2 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_B2 to 0xd6 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_B2 to 0x3 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_B2 to 0x11 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_B2 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_B2 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_B2 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_B2 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_B2 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_B3 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_B3 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_B3 to 0x20 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_B3 to 0x8 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_B3 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_B3 to 0x2d +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_B3 to 0xd6 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_B3 to 0x3 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_B3 to 0x11 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_B3 to 0x4 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_B3 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_B3 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_B3 to 0x2c +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_B3 to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].WL_ADJ_START to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].WL_ADJ_END to 0x0 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].RCW00_ChA_D0 to 0x1 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].RCW00_ChA_D1 to 0x1 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].RCW00_ChB_D0 to 0x1 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].RCW00_ChB_D1 to 0x1 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib0 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib1 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib2 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib3 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib4 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib5 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib6 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib7 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib8 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib9 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib10 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib11 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib12 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib13 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib14 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib15 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib16 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib17 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib18 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib19 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib0 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib1 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib2 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib3 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib4 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib5 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib6 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib7 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib8 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib9 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib10 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib11 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib12 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib13 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib14 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib15 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib16 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib17 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib18 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib19 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib0 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib1 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib2 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib3 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib4 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib5 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib6 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib7 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib8 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib9 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib10 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib11 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib12 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib13 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib14 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib15 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib16 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib17 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib18 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib19 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib0 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib1 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib2 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib3 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib4 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib5 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib6 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib7 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib8 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib9 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib10 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib11 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib12 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib13 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib14 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib15 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib16 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib17 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib18 to 0x17 +// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib19 to 0x17 +// [dwc_ddrphy_phyinit_userCustom_overrideUserInput] End of dwc_ddrphy_phyinit_userCustom_overrideUserInput() +//[dwc_ddrphy_phyinit_calcMb] Start of dwc_ddrphy_phyinit_calcMb() +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].Pstate override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].DRAMFreq override to 0xc80 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].PllBypassEn override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].X16Present override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].EnabledDQsChA override to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].EnabledDQsChB override to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].Pstate to 0x1 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].DRAMFreq to 0x856 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].PllBypassEn to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].X16Present to 0x1 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].EnabledDQsChA to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].EnabledDQsChB to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].Pstate to 0x2 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].DRAMFreq to 0x74a +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].PllBypassEn to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].X16Present to 0x1 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].EnabledDQsChA to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].EnabledDQsChB to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].Pstate to 0x3 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].DRAMFreq to 0x640 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].PllBypassEn to 0x0 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].X16Present to 0x1 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].EnabledDQsChA to 0x10 +//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].EnabledDQsChB to 0x0 +////[dwc_ddrphy_phyinit_calcMb] TG_active[0] = 1 +////[dwc_ddrphy_phyinit_calcMb] TG_active[1] = 0 +////[dwc_ddrphy_phyinit_calcMb] TG_active[2] = 0 +////[dwc_ddrphy_phyinit_calcMb] TG_active[3] = 0 +////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=0] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=0] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=0] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=1] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=1] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=1] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=2] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=2] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=2] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=3] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=3] = 0 ps +////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=3] = 0 ps +//[dwc_ddrphy_phyinit_calcMb] End of dwc_ddrphy_phyinit_calcMb() +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // Printing values in user input structure +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[0] = 16 +//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[1] = 16 +//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[2] = 16 +//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[3] = 16 +//// [phyinit_print_dat] pUserInputBasic->NumActiveDbyteDfi1 = 0 +//// [phyinit_print_dat] pUserInputBasic->DramType = 1 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitValOvr = 0 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[0] = 3 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[1] = 3 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[2] = 3 +//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[3] = 3 +//// [phyinit_print_dat] pUserInputBasic->Dfi1Exists = 0 +//// [phyinit_print_dat] pUserInputBasic->Frequency[0] = 1600 +//// [phyinit_print_dat] pUserInputBasic->Frequency[1] = 1067 +//// [phyinit_print_dat] pUserInputBasic->Frequency[2] = 933 +//// [phyinit_print_dat] pUserInputBasic->Frequency[3] = 800 +//// [phyinit_print_dat] pUserInputBasic->NumActiveDbyteDfi0 = 2 +//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[0] = 0 +//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[1] = 0 +//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[2] = 0 +//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[3] = 0 +//// [phyinit_print_dat] pUserInputBasic->NumRank_dfi0 = 1 +//// [phyinit_print_dat] pUserInputBasic->NumPStates = 1 +//// [phyinit_print_dat] pUserInputBasic->PllBypass[0] = 0 +//// [phyinit_print_dat] pUserInputBasic->PllBypass[1] = 0 +//// [phyinit_print_dat] pUserInputBasic->PllBypass[2] = 0 +//// [phyinit_print_dat] pUserInputBasic->PllBypass[3] = 0 +//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[0] = 1 +//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[1] = 1 +//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[2] = 1 +//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[3] = 1 +//// [phyinit_print_dat] pUserInputBasic->NumAnib = 10 +//// [phyinit_print_dat] pUserInputBasic->DimmType = 4 +//// [phyinit_print_dat] pUserInputBasic->NumRank_dfi1 = 0 +//// [phyinit_print_dat] pUserInputBasic->NumDbyte = 2 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg1[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg1[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg1[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg1[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg0[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg0[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg0[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg0[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->IsHighVDD = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->ExtCalResVal = 240 +//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->RxEnBackOff = 1 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[4] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[5] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[6] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[7] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->CalOnce = 0 +//// [phyinit_print_dat] pUserInputAdvanced->Apb32BitMode = 1 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseCK = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallAC = 38 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallCK = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DisablePmuEcc = 1 +//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlOpt = 0 +//// [phyinit_print_dat] pUserInputAdvanced->WDQSExt = 0 +//// [phyinit_print_dat] pUserInputAdvanced->VREGCtrl_LP2_PwrSavings_En = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseAC = 102 +//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[4] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[5] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[6] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[7] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg3[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg3[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg3[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg3[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->rtt_term_en = 0 +//// [phyinit_print_dat] pUserInputAdvanced->AlertRecoveryEnable = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->en_16LogicalRanks_3DS = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[1] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[2] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[3] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[4] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[5] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[6] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[7] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[0] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[1] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[2] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[3] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->Nibble_ECC = 15 +//// [phyinit_print_dat] pUserInputAdvanced->D5DisableRetraining = 0 +//// [phyinit_print_dat] pUserInputAdvanced->DqsOscRunTimeSel[0] = 256 +//// [phyinit_print_dat] pUserInputAdvanced->DqsOscRunTimeSel[1] = 256 +//// [phyinit_print_dat] pUserInputAdvanced->DqsOscRunTimeSel[2] = 256 +//// [phyinit_print_dat] pUserInputAdvanced->DqsOscRunTimeSel[3] = 256 +//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[0] = 120 +//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[1] = 60 +//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[2] = 60 +//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[3] = 60 +//// [phyinit_print_dat] pUserInputAdvanced->MtestPUImp = 240 +//// [phyinit_print_dat] pUserInputAdvanced->EnableMAlertAsync = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[0] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->RedundantCs_en = 0 +//// [phyinit_print_dat] pUserInputAdvanced->CalInterval = 9 +//// [phyinit_print_dat] pUserInputAdvanced->D5TxDqPreambleCtrl[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->D5TxDqPreambleCtrl[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D5TxDqPreambleCtrl[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->D5TxDqPreambleCtrl[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->MemAlertEn = 0 +//// [phyinit_print_dat] pUserInputAdvanced->ATxImpedance = 53247 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg2[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg2[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg2[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg2[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->en_3DS = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnRxDqsTracking[0] = 1 +//// [phyinit_print_dat] pUserInputAdvanced->EnRxDqsTracking[1] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnRxDqsTracking[2] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->EnRxDqsTracking[3] = 0 +//// [phyinit_print_dat] pUserInputAdvanced->RstRxTrkState = 0 +//// [phyinit_print_dat] pUserInputAdvanced->TrainSequenceCtrl = 33663 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[0] = 60 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[1] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[2] = 25 +//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[3] = 25 +//// [phyinit_print_dat] pUserInputSim->tDQS2DQ = 750 +//// [phyinit_print_dat] pUserInputSim->tDQSCK = 0 +//// [phyinit_print_dat] pUserInputSim->tSTAOFF[0] = 0 +//// [phyinit_print_dat] pUserInputSim->tSTAOFF[1] = 0 +//// [phyinit_print_dat] pUserInputSim->tSTAOFF[2] = 0 +//// [phyinit_print_dat] pUserInputSim->tSTAOFF[3] = 0 +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // Printing values of 1D message block input/inout fields, PState=0 +//// [phyinit_print_dat] // +//// [phyinit_print_dat] // #################################################### +//// [phyinit_print_dat] mb_DDR5U_1D[0].AdvTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MsgMisc = 0x7 +//// [phyinit_print_dat] mb_DDR5U_1D[0].Pstate = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].PllBypassEn = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DRAMFreq = 0xc80 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RXEN_ADJ = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RX2D_DFE_Misc = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyVref = 0x40 +//// [phyinit_print_dat] mb_DDR5U_1D[0].D5Misc = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].SequenceCtrl = 0x837f +//// [phyinit_print_dat] mb_DDR5U_1D[0].HdtCtrl = 0xc8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyCfg = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFIMRLMargin = 0x2 +//// [phyinit_print_dat] mb_DDR5U_1D[0].X16Present = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].UseBroadcastMR = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].D5Quickboot = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDbyte = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].CATrainOpt = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].TX2D_DFE_Misc = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RX2D_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].TX2D_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].Share2DVrefResult = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MRE_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DWL_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyConfigOverride = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].EnabledDQsChA = 0x10 +//// [phyinit_print_dat] mb_DDR5U_1D[0].CsPresentChA = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A0 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A0 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A0 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A0 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A0 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A0 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A0 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A0 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A0 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A0 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A1 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A1 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A1 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A1 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A1 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A1 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A1 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A1 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A1 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A1 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A2 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A2 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A2 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A2 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A2 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A2 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A2 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A2 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A2 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A2 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A3 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A3 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A3 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A3 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A3 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A3 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A3 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A3 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A3 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A3 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].EnabledDQsChB = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].CsPresentChB = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B0 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B0 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B0 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B0 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B0 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B0 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B0 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B0 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B0 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B0 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B1 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B1 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B1 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B1 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B1 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B1 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B1 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B1 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B1 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B1 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B2 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B2 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B2 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B2 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B2 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B2 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B2 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B2 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B2 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B2 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B3 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B3 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B3 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B3 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B3 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B3 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B3 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B3 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B3 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B3 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ_START = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ_END = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChA_D0 = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChA_D1 = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChB_D0 = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChB_D1 = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib0 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib1 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib2 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib3 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib4 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib5 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib6 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib7 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib8 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib9 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib10 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib11 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib12 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib13 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib14 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib15 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib16 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib17 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib18 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib19 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib0 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib1 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib2 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib3 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib4 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib5 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib6 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib7 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib8 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib9 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib10 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib11 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib12 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib13 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib14 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib15 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib16 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib17 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib18 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib19 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib0 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib1 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib2 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib3 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib4 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib5 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib6 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib7 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib8 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib9 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib10 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib11 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib12 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib13 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib14 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib15 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib16 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib17 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib18 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib19 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib0 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib1 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib2 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib3 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib4 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib5 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib6 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib7 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib8 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib9 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib10 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib11 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib12 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib13 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib14 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib15 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib16 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib17 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib18 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib19 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].AdvTrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MsgMisc = 0x7 +//// [phyinit_print_dat] mb_DDR5U_1D[0].Pstate = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].PllBypassEn = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DRAMFreq = 0xc80 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RXEN_ADJ = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RX2D_DFE_Misc = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyVref = 0x40 +//// [phyinit_print_dat] mb_DDR5U_1D[0].D5Misc = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].SequenceCtrl = 0x837f +//// [phyinit_print_dat] mb_DDR5U_1D[0].HdtCtrl = 0xc8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyCfg = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFIMRLMargin = 0x2 +//// [phyinit_print_dat] mb_DDR5U_1D[0].X16Present = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].UseBroadcastMR = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].D5Quickboot = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDbyte = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].CATrainOpt = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].TX2D_DFE_Misc = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RX2D_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].TX2D_TrainOpt = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].Share2DVrefResult = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MRE_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DWL_MIN_PULSE = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyConfigOverride = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].EnabledDQsChA = 0x10 +//// [phyinit_print_dat] mb_DDR5U_1D[0].CsPresentChA = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A0 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A0 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A0 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A0 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A0 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A0 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A0 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A0 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A0 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A0 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A1 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A1 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A1 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A1 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A1 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A1 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A1 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A1 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A1 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A1 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A2 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A2 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A2 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A2 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A2 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A2 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A2 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A2 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A2 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A2 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A3 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A3 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A3 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A3 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A3 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A3 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A3 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A3 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A3 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A3 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].EnabledDQsChB = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].CsPresentChB = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B0 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B0 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B0 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B0 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B0 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B0 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B0 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B0 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B0 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B0 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B0 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B0_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B1 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B1 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B1 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B1 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B1 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B1 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B1 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B1 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B1 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B1 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B1 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B1_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B2 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B2 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B2 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B2 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B2 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B2 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B2 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B2 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B2 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B2 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B2 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B2_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B3 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B3 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B3 = 0x20 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B3 = 0x8 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B3 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B3 = 0x2d +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B3 = 0xd6 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B3 = 0x3 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B3 = 0x11 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B3 = 0x4 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B3 = 0x2c +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B3_next = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ_START = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ_END = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChA_D0 = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChA_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChA_D1 = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChA_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChB_D0 = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChB_D0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChB_D1 = 0x1 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChB_D1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib0 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib1 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib2 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib3 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib4 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib5 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib6 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib7 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib8 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib9 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib10 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib11 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib12 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib13 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib14 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib15 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib16 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib17 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib18 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib19 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib0 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib1 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib2 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib3 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib4 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib5 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib6 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib7 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib8 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib9 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib10 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib11 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib12 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib13 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib14 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib15 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib16 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib17 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib18 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib19 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib0 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib1 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib2 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib3 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib4 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib5 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib6 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib7 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib8 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib9 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib10 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib11 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib12 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib13 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib14 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib15 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib16 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib17 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib18 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib19 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib0 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib1 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib2 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib3 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib4 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib5 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib6 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib7 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib8 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib9 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib10 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib11 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib12 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib13 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib14 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib15 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib16 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib17 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib18 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib19 = 0x17 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib4 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib5 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib6 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib7 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib8 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib9 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib10 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib11 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib12 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib13 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib14 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib15 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib16 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib17 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib18 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib19 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR0 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR1 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR2 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR3 = 0x0 +//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR3 = 0x0 + +////############################################################## +//// +//// Step (A) : Bring up VDD, VDDQ, and VAA +//// +//// The power supplies can come up and stabilize in any order. +//// While the power supplies are coming up, all outputs will be unknown and +//// the values of the inputs are don't cares. +//// +////############################################################## + +dwc_ddrphy_phyinit_userCustom_A_bringupPower(); + +//[dwc_ddrphy_phyinit_userCustom_A_bringupPower] End of dwc_ddrphy_phyinit_userCustom_A_bringupPower() +// +// +////############################################################## +//// +//// 4.3.2(B) Start Clocks and Reset the PHY +//// +//// Following is one possbile sequence to reset the PHY. Other sequences are also possible. +//// See section 5.2.2 of the PUB for other possible reset sequences. +//// +//// 1. Drive PwrOkIn to 0. Note: Reset, DfiClk, and APBCLK can be X. +//// 2. Start DfiClk and APBCLK +//// 3. Drive Reset to 1 and PRESETn_APB to 0. +//// Note: The combination of PwrOkIn=0 and Reset=1 signals a cold reset to the PHY. +//// 4. Wait a minimum of 8 cycles. +//// 5. Drive PwrOkIn to 1. Once the PwrOkIn is asserted (and Reset is still asserted), +//// DfiClk synchronously switches to any legal input frequency. +//// 6. Wait a minimum of 64 cycles. Note: This is the reset period for the PHY. +//// 7. Drive Reset to 0. Note: All DFI and APB inputs must be driven at valid reset states before the deassertion of Reset. +//// 8. Wait a minimum of 1 Cycle. +//// 9. Drive PRESETn_APB to 1 to de-assert reset on the ABP bus. +////10. The PHY is now in the reset state and is ready to accept APB transactions. +//// +////############################################################## +// +// +dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(sdrammc); + +//// [dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy] End of dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy() +// + +////############################################################## +//// +//// Step (C) Initialize PHY Configuration +//// +//// Load the required PHY configuration registers for the appropriate mode and memory configuration +//// +////############################################################## +// + +//// [phyinit_C_initPhyConfig] Start of dwc_ddrphy_phyinit_C_initPhyConfig() +//// [phyinit_C_initPhyConfig] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x1 +dwc_ddrphy_apb_wr(0x200a6, 0x2); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for MASTER +dwc_ddrphy_apb_wr(0x20066, 0x0); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all DBYTEs +dwc_ddrphy_apb_wr(0x10066, 0x0); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x11066, 0x0); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all ANIBs +dwc_ddrphy_apb_wr(0x66, 0x0); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x1066, 0x0); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x2066, 0x0); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x3066, 0x0); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x4066, 0x0); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x5066, 0x0); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x6066, 0x0); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x7066, 0x0); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x8066, 0x0); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x9066, 0x0); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x16 for MASTER +dwc_ddrphy_apb_wr(0x20029, 0x58); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl1_p0 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x16 for all DBYTEs +dwc_ddrphy_apb_wr(0x10029, 0x58); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x11029, 0x58); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl1_p0 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x16 for all ANIBs +dwc_ddrphy_apb_wr(0x29, 0x58); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x1029, 0x58); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x2029, 0x58); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x3029, 0x58); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x4029, 0x58); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x5029, 0x58); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x6029, 0x58); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x7029, 0x58); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x8029, 0x58); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x9029, 0x58); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl1_p0 +dwc_ddrphy_apb_wr(0x90301, 0x59); // DWC_DDRPHYA_INITENG0_base0_Seq0BGPR1_p0 +dwc_ddrphy_apb_wr(0x90302, 0x58); // DWC_DDRPHYA_INITENG0_base0_Seq0BGPR2_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate::CsrTxSrc to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate::TxPreDrvMode to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate to 0x0 +//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::CsrTxSrc are technology specific. +//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings + +dwc_ddrphy_apb_wr(0x1005f, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxSlewRate_b0_p0 +dwc_ddrphy_apb_wr(0x1015f, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxSlewRate_b1_p0 +dwc_ddrphy_apb_wr(0x1105f, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxSlewRate_b0_p0 +dwc_ddrphy_apb_wr(0x1115f, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxSlewRate_b1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::ATxPreDrvMode to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 0 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 0 to 0x1be +dwc_ddrphy_apb_wr(0x55, 0x1be); // DWC_DDRPHYA_ANIB0_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 1 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 1 to 0x1be +dwc_ddrphy_apb_wr(0x1055, 0x1be); // DWC_DDRPHYA_ANIB1_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 2 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 2 to 0x1be +dwc_ddrphy_apb_wr(0x2055, 0x1be); // DWC_DDRPHYA_ANIB2_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 3 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 3 to 0x1be +dwc_ddrphy_apb_wr(0x3055, 0x1be); // DWC_DDRPHYA_ANIB3_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 4 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 4 to 0x1be +dwc_ddrphy_apb_wr(0x4055, 0x1be); // DWC_DDRPHYA_ANIB4_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 5 to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 5 to 0x0 +dwc_ddrphy_apb_wr(0x5055, 0x0); // DWC_DDRPHYA_ANIB5_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 6 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 6 to 0x1be +dwc_ddrphy_apb_wr(0x6055, 0x1be); // DWC_DDRPHYA_ANIB6_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 7 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 7 to 0x1be +dwc_ddrphy_apb_wr(0x7055, 0x1be); // DWC_DDRPHYA_ANIB7_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 8 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 8 to 0x1be +dwc_ddrphy_apb_wr(0x8055, 0x1be); // DWC_DDRPHYA_ANIB8_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 9 to 0x1be +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 9 to 0x1be +dwc_ddrphy_apb_wr(0x9055, 0x1be); // DWC_DDRPHYA_ANIB9_base0_ATxSlewRate_p0 +//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::CsrATxSrc are technology specific. +//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings + +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::CsrTxOvSrc to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::TxCalBaseN to 0x1 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::TxCalBaseP to 0x1 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride to 0x300 +//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for CalPreDriverOverride::CsrTxOvSrc are technology specific. +//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings + +dwc_ddrphy_apb_wr(0x2008c, 0x300); // DWC_DDRPHYA_MASTER0_base0_CalPreDriverOverride +//// [phyinit_C_initPhyConfig] PUB revision is 0x0350. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl2::PllFreqSel to 0x19 based on DfiClk frequency = 800. +dwc_ddrphy_apb_wr(0x200c5, 0x19); // DWC_DDRPHYA_MASTER0_base0_PllCtrl2_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1::PllCpPropCtrl to 0x3 based on DfiClk frequency = 800. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1::PllCpIntCtrl to 0x1 based on DfiClk frequency = 800. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1 to 0x61 based on DfiClk frequency = 800. +dwc_ddrphy_apb_wr(0x200c7, 0x21); // DWC_DDRPHYA_MASTER0_base0_PllCtrl1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllTestMode to 0x400f based on DfiClk frequency = 800. +dwc_ddrphy_apb_wr(0x200ca, 0x402f); // DWC_DDRPHYA_MASTER0_base0_PllTestMode_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4::PllCpPropGsCtrl to 0x6 based on DfiClk frequency = 800. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4::PllCpIntGsCtrl to 0x12 based on DfiClk frequency = 800. +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4 to 0xd2 based on DfiClk frequency = 800. +dwc_ddrphy_apb_wr(0x200cc, 0x17f); // DWC_DDRPHYA_MASTER0_base0_PllCtrl4_p0 +//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for PllCtrl1 and PllTestMode are technology specific. +//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult technology specific PHY Databook for recommended settings + +// +////############################################################## +//// +//// Program ARdPtrInitVal based on Frequency and PLL Bypass inputs +//// The values programmed here assume ideal properties of DfiClk +//// and Pclk including: +//// - DfiClk skew +//// - DfiClk jitter +//// - DfiClk PVT variations +//// - Pclk skew +//// - Pclk jitter +//// +//// PLL Bypassed mode: +//// For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 2-5 +//// For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-5 +//// +//// PLL Enabled mode: +//// For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-5 +//// For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 0-5 +//// +////############################################################## +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ARdPtrInitVal to 0x1 +dwc_ddrphy_apb_wr(0x2002e, 0x1); // DWC_DDRPHYA_MASTER0_base0_ARdPtrInitVal_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DisPtrInitClrTxTracking to 0x0 +dwc_ddrphy_apb_wr(0x20051, 0x0); // DWC_DDRPHYA_MASTER0_base0_PtrInitTrackingModeCntrl_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::DDR5RxPreamble to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::DDR5RxPostamble to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl to 0x88 +dwc_ddrphy_apb_wr(0x20024, 0x88); // DWC_DDRPHYA_MASTER0_base0_DqsPreambleControl_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreamblePattern::EnTxDqsPreamblePattern to 0x7 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreamblePattern::TxDqsPreamblePattern to 0x1 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreamblePattern to 0x701 +dwc_ddrphy_apb_wr(0x200a1, 0x701); // DWC_DDRPHYA_MASTER0_base0_DqsPreamblePattern_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPostamblePattern::EnTxDqsPostamblePattern to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPostamblePattern::TxDqsPostamblePattern to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPostamblePattern to 0x0 +dwc_ddrphy_apb_wr(0x200a2, 0x0); // DWC_DDRPHYA_MASTER0_base0_DqsPostamblePattern_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DmPreamblePattern::EnTxDmPreamblePattern to 0xf +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DmPreamblePattern::TxDmPreamblePattern to 0xf +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DmPreamblePattern to 0xf5 +dwc_ddrphy_apb_wr(0x200fe, 0xf5); // DWC_DDRPHYA_MASTER0_base0_DmPreamblePattern_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU0::EnTxDqPreamblePatternU0 to 0xf +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU0::TxDqPreamblePatternU0 to 0xf +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU0 to 0xf5 +dwc_ddrphy_apb_wr(0x200fc, 0xf5); // DWC_DDRPHYA_MASTER0_base0_DqPreamblePatternU0_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU1::EnTxDqPreamblePatternU1 to 0xf +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU1::TxDqPreamblePatternU1 to 0xf +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU1 to 0xf5 +dwc_ddrphy_apb_wr(0x200fd, 0xf5); // DWC_DDRPHYA_MASTER0_base0_DqPreamblePatternU1_p0 +//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl::DllRxPreambleMode to 0x1 +//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl::DllRxBurstLengthMode to 0x0 +//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl to 0x2 +dwc_ddrphy_apb_wr(0x2003a, 0x2); // DWC_DDRPHYA_MASTER0_base0_DbyteDllModeCntrl +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxOdtDrvStren::TxOdtStrenPu to 0x4 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxOdtDrvStren::TxOdtStrenPd to 0x0 +dwc_ddrphy_apb_wr(0x1004d, 0x104); // DWC_DDRPHYA_DBYTE0_base0_TxOdtDrvStren_b0_p0 +dwc_ddrphy_apb_wr(0x1014d, 0x104); // DWC_DDRPHYA_DBYTE0_base0_TxOdtDrvStren_b1_p0 +dwc_ddrphy_apb_wr(0x1104d, 0x104); // DWC_DDRPHYA_DBYTE1_base0_TxOdtDrvStren_b0_p0 +dwc_ddrphy_apb_wr(0x1114d, 0x104); // DWC_DDRPHYA_DBYTE1_base0_TxOdtDrvStren_b1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ADrvStrenP to 0x3f +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ADrvStrenN to 0x3f +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxReserved13x12 to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxCalBaseN to 0x1 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxCalBaseP to 0x1 +dwc_ddrphy_apb_wr(0x43, 0xcfff); // DWC_DDRPHYA_ANIB0_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x1043, 0xcfff); // DWC_DDRPHYA_ANIB1_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x2043, 0xcfff); // DWC_DDRPHYA_ANIB2_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x3043, 0xcfff); // DWC_DDRPHYA_ANIB3_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x4043, 0xcfff); // DWC_DDRPHYA_ANIB4_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x5043, 0xcfff); // DWC_DDRPHYA_ANIB5_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x6043, 0xcfff); // DWC_DDRPHYA_ANIB6_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x7043, 0xcfff); // DWC_DDRPHYA_ANIB7_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x8043, 0xcfff); // DWC_DDRPHYA_ANIB8_base0_ATxImpedance +dwc_ddrphy_apb_wr(0x9043, 0xcfff); // DWC_DDRPHYA_ANIB9_base0_ATxImpedance +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl0::TxStrenEqHiPu to 0xc +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl0::TxStrenEqLoPd to 0xc +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl1::TxStrenPu to 0x3f +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl1::TxStrenPd to 0x3f +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl2::TxStrenEqLoPu to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl2::TxStrenEqHiPd to 0x0 +dwc_ddrphy_apb_wr(0x10041, 0x30c); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl0_b0_p0 +dwc_ddrphy_apb_wr(0x10049, 0x79e); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl1_b0_p0 +dwc_ddrphy_apb_wr(0x1004b, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl2_b0_p0 +dwc_ddrphy_apb_wr(0x10141, 0x30c); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl0_b1_p0 +dwc_ddrphy_apb_wr(0x10149, 0x79e); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl1_b1_p0 +dwc_ddrphy_apb_wr(0x1014b, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl2_b1_p0 +dwc_ddrphy_apb_wr(0x11041, 0x30c); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl0_b0_p0 +dwc_ddrphy_apb_wr(0x11049, 0x79e); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl1_b0_p0 +dwc_ddrphy_apb_wr(0x1104b, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl2_b0_p0 +dwc_ddrphy_apb_wr(0x11141, 0x30c); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl0_b1_p0 +dwc_ddrphy_apb_wr(0x11149, 0x79e); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl1_b1_p0 +dwc_ddrphy_apb_wr(0x1114b, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl2_b1_p0 +//// [phyinit_C_initPhyConfig] Programming DfiMode to 0x1 +dwc_ddrphy_apb_wr(0x20018, 0x1); // DWC_DDRPHYA_MASTER0_base0_DfiMode +//// [phyinit_C_initPhyConfig] Programming DfiCAMode to 0x10 +dwc_ddrphy_apb_wr(0x20075, 0x10); // DWC_DDRPHYA_MASTER0_base0_DfiCAMode +//// [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPd50 to 0x2 +//// [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPu50 to 0x2 +dwc_ddrphy_apb_wr(0x20050, 0x82); // DWC_DDRPHYA_MASTER0_base0_CalDrvStr0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x320 +dwc_ddrphy_apb_wr(0x20008, 0x320); // DWC_DDRPHYA_MASTER0_base0_CalUclkInfo_p0 +//// [phyinit_C_initPhyConfig] Programming CalRate::CalInterval to 0x9 +//// [phyinit_C_initPhyConfig] Programming CalRate::CalOnce to 0x0 +dwc_ddrphy_apb_wr(0x20088, 0x9); // DWC_DDRPHYA_MASTER0_base0_CalRate +//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInSel to 0x0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInDAC to 0x1f +//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal to 0xf8 +dwc_ddrphy_apb_wr(0x200b2, 0xf8); // DWC_DDRPHYA_MASTER0_base0_VrefInGlobal_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=0, Upper/Lower=0) to 0x2900 +dwc_ddrphy_apb_wr(0x10043, 0x2900); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl_b0_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=0, Upper/Lower=1) to 0x2900 +dwc_ddrphy_apb_wr(0x10143, 0x2900); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl_b1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=1, Upper/Lower=0) to 0x2900 +dwc_ddrphy_apb_wr(0x11043, 0x2900); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl_b0_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=1, Upper/Lower=1) to 0x2900 +dwc_ddrphy_apb_wr(0x11143, 0x2900); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl_b1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl2 to 0x1c +dwc_ddrphy_apb_wr(0x1004c, 0x1c); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl2_p0 +dwc_ddrphy_apb_wr(0x1104c, 0x1c); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl2_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TristateModeCA::DisDynAdrTri_p0 to 0x1 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TristateModeCA::DDR2TMode_p0 to 0x0 +dwc_ddrphy_apb_wr(0x20019, 0x5); // DWC_DDRPHYA_MASTER0_base0_TristateModeCA_p0 +//// [phyinit_C_initPhyConfig] Programming DfiFreqXlat* +dwc_ddrphy_apb_wr(0x200f0, 0x0); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat0 +dwc_ddrphy_apb_wr(0x200f1, 0x0); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat1 +dwc_ddrphy_apb_wr(0x200f2, 0x4444); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat2 +dwc_ddrphy_apb_wr(0x200f3, 0x8888); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat3 +dwc_ddrphy_apb_wr(0x200f4, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat4 +dwc_ddrphy_apb_wr(0x200f5, 0x0); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat5 +dwc_ddrphy_apb_wr(0x200f6, 0x0); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat6 +dwc_ddrphy_apb_wr(0x200f7, 0xf000); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat7 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY0 to 0x64 +dwc_ddrphy_apb_wr(0x2000b, 0x64); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY0_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY1 to 0xc8 +dwc_ddrphy_apb_wr(0x2000c, 0xc8); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY1_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY2 to 0x2bc +dwc_ddrphy_apb_wr(0x2000d, 0x2bc); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY2_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY3 to 0x2c +dwc_ddrphy_apb_wr(0x2000e, 0x2c); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY3_p0 +//// [phyinit_C_initPhyConfig] Disabling DBYTE 0 Lane 8 (DBI) Receiver to save power. +dwc_ddrphy_apb_wr(0x1004a, 0x500); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl1 +//// [phyinit_C_initPhyConfig] Disabling DBYTE 1 Lane 8 (DBI) Receiver to save power. +dwc_ddrphy_apb_wr(0x1104a, 0x500); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl1 +//// [phyinit_C_initPhyConfig] Programming MasterX4Config::X4TG to 0x0 +dwc_ddrphy_apb_wr(0x20025, 0x0); // DWC_DDRPHYA_MASTER0_base0_MasterX4Config +// [phyinit_C_initPhyConfig] Programming DfiDataEnLatency::WLm13 and RLm13 +dwc_ddrphy_apb_wr(0x2019a, 0x18); // DWC_DDRPHYA_MASTER0_base0_DfiDataEnLatency +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, rd_Crc = 0 cwl= 24 , cl = 26 mr_cl =2 MR0_A0 = 0x8 +dwc_ddrphy_apb_wr(0x400f5, 0x1200); // DWC_DDRPHYA_ACSM0_base0_AcsmCtrl5_p0 +dwc_ddrphy_apb_wr(0x400f6, 0x10); // DWC_DDRPHYA_ACSM0_base0_AcsmCtrl6_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0RxEnPulse to 2062 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0RxValPulse to 2062 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0RdcsPulse to 2062 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0TxEnPulse to 2060 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0WrcsPulse to 2060 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0SnoopPulse to 2062 +dwc_ddrphy_apb_wr(0x20120, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0RxEnPulse_p0 +dwc_ddrphy_apb_wr(0x20121, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0RxValPulse_p0 +dwc_ddrphy_apb_wr(0x20124, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0RdcsPulse_p0 +dwc_ddrphy_apb_wr(0x20122, 0x80c); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0TxEnPulse_p0 +dwc_ddrphy_apb_wr(0x20123, 0x80c); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0WrcsPulse_p0 +dwc_ddrphy_apb_wr(0x20125, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0SnoopPulse_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0SnoopVal to 801 +dwc_ddrphy_apb_wr(0x2012e, 0x321); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0SnoopVal +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1RxEnPulse to 2062 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1RxValPulse to 2062 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1RdcsPulse to 2062 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1TxEnPulse to 2060 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1WrcsPulse to 2060 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1SnoopPulse to 2062 +dwc_ddrphy_apb_wr(0x20140, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1RxEnPulse_p0 +dwc_ddrphy_apb_wr(0x20141, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1RxValPulse_p0 +dwc_ddrphy_apb_wr(0x20144, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1RdcsPulse_p0 +dwc_ddrphy_apb_wr(0x20142, 0x80c); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1TxEnPulse_p0 +dwc_ddrphy_apb_wr(0x20143, 0x80c); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1WrcsPulse_p0 +dwc_ddrphy_apb_wr(0x20145, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1SnoopPulse_p0 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1SnoopVal to 801 +dwc_ddrphy_apb_wr(0x2014e, 0x321); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1SnoopVal +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming GPR7(csrAlertRecovery) to 0x0 +dwc_ddrphy_apb_wr(0x90307, 0x0); // DWC_DDRPHYA_INITENG0_base0_Seq0BGPR7_p0 +// [phyinit_C_initPhyConfig] Programming TimingModeCntrl::Dly64Prec to 0x1 +dwc_ddrphy_apb_wr(0x20040, 0x1); // DWC_DDRPHYA_MASTER0_base0_TimingModeCntrl +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for MASTER +dwc_ddrphy_apb_wr(0x20066, 0x1); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for all DBYTEs +dwc_ddrphy_apb_wr(0x10066, 0x1); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x11066, 0x1); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for all ANIBs +dwc_ddrphy_apb_wr(0x66, 0x1); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x1066, 0x1); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x2066, 0x1); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x3066, 0x1); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x4066, 0x1); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x5066, 0x1); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x6066, 0x1); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x7066, 0x1); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x8066, 0x1); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x9066, 0x1); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming AcClkDLLControl to 0x1080 +dwc_ddrphy_apb_wr(0x200ea, 0x1080); // DWC_DDRPHYA_MASTER0_base0_AcClkDLLControl_p0 +// [phyinit_C_initPhyConfig] Programming ArcPmuEccCtl to 0x1 +dwc_ddrphy_apb_wr(0xc0086, 0x1); // DWC_DDRPHYA_DRTUB0_ArcPmuEccCtl +// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x9820 for MASTER +dwc_ddrphy_apb_wr(0x2002b, 0x9820); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl2 +// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x8020 for all DBYTEs +dwc_ddrphy_apb_wr(0x1002b, 0x8020); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x1102b, 0x8020); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl2 +// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x8020 for all ANIBs +dwc_ddrphy_apb_wr(0x2b, 0x8020); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x102b, 0x8020); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x202b, 0x8020); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x302b, 0x8020); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x402b, 0x8020); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x502b, 0x8020); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x602b, 0x8020); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x702b, 0x8020); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x802b, 0x8020); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl2 +dwc_ddrphy_apb_wr(0x902b, 0x8020); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl2 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for MASTER +dwc_ddrphy_apb_wr(0x20066, 0x0); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all DBYTEs +dwc_ddrphy_apb_wr(0x10066, 0x0); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x11066, 0x0); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all ANIBs +dwc_ddrphy_apb_wr(0x66, 0x0); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x1066, 0x0); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x2066, 0x0); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x3066, 0x0); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x4066, 0x0); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x5066, 0x0); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x6066, 0x0); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x7066, 0x0); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x8066, 0x0); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3 +dwc_ddrphy_apb_wr(0x9066, 0x0); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3 +// [phyinit_C_initPhyConfig] Programming VrefDAC0 to 0x3f for all DBYTEs and lanes +// [phyinit_C_initPhyConfig] Programming VrefDAC1 to 0x3f for all DBYTEs and lanes +// [phyinit_C_initPhyConfig] Programming VrefDAC2 to 0x3f for all DBYTEs and lanes +// [phyinit_C_initPhyConfig] Programming VrefDAC3 to 0x3f for all DBYTEs and lanes +dwc_ddrphy_apb_wr(0x10040, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r0_p0 +dwc_ddrphy_apb_wr(0x10030, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r0 +dwc_ddrphy_apb_wr(0x10050, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r0 +dwc_ddrphy_apb_wr(0x10060, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r0 +dwc_ddrphy_apb_wr(0x10140, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r1_p0 +dwc_ddrphy_apb_wr(0x10130, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r1 +dwc_ddrphy_apb_wr(0x10150, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r1 +dwc_ddrphy_apb_wr(0x10160, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r1 +dwc_ddrphy_apb_wr(0x10240, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r2_p0 +dwc_ddrphy_apb_wr(0x10230, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r2 +dwc_ddrphy_apb_wr(0x10250, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r2 +dwc_ddrphy_apb_wr(0x10260, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r2 +dwc_ddrphy_apb_wr(0x10340, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r3_p0 +dwc_ddrphy_apb_wr(0x10330, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r3 +dwc_ddrphy_apb_wr(0x10350, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r3 +dwc_ddrphy_apb_wr(0x10360, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r3 +dwc_ddrphy_apb_wr(0x10440, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r4_p0 +dwc_ddrphy_apb_wr(0x10430, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r4 +dwc_ddrphy_apb_wr(0x10450, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r4 +dwc_ddrphy_apb_wr(0x10460, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r4 +dwc_ddrphy_apb_wr(0x10540, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r5_p0 +dwc_ddrphy_apb_wr(0x10530, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r5 +dwc_ddrphy_apb_wr(0x10550, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r5 +dwc_ddrphy_apb_wr(0x10560, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r5 +dwc_ddrphy_apb_wr(0x10640, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r6_p0 +dwc_ddrphy_apb_wr(0x10630, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r6 +dwc_ddrphy_apb_wr(0x10650, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r6 +dwc_ddrphy_apb_wr(0x10660, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r6 +dwc_ddrphy_apb_wr(0x10740, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r7_p0 +dwc_ddrphy_apb_wr(0x10730, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r7 +dwc_ddrphy_apb_wr(0x10750, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r7 +dwc_ddrphy_apb_wr(0x10760, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r7 +dwc_ddrphy_apb_wr(0x10840, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r8_p0 +dwc_ddrphy_apb_wr(0x10830, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r8 +dwc_ddrphy_apb_wr(0x10850, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r8 +dwc_ddrphy_apb_wr(0x10860, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r8 +dwc_ddrphy_apb_wr(0x11040, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r0_p0 +dwc_ddrphy_apb_wr(0x11030, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r0 +dwc_ddrphy_apb_wr(0x11050, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r0 +dwc_ddrphy_apb_wr(0x11060, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r0 +dwc_ddrphy_apb_wr(0x11140, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r1_p0 +dwc_ddrphy_apb_wr(0x11130, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r1 +dwc_ddrphy_apb_wr(0x11150, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r1 +dwc_ddrphy_apb_wr(0x11160, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r1 +dwc_ddrphy_apb_wr(0x11240, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r2_p0 +dwc_ddrphy_apb_wr(0x11230, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r2 +dwc_ddrphy_apb_wr(0x11250, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r2 +dwc_ddrphy_apb_wr(0x11260, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r2 +dwc_ddrphy_apb_wr(0x11340, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r3_p0 +dwc_ddrphy_apb_wr(0x11330, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r3 +dwc_ddrphy_apb_wr(0x11350, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r3 +dwc_ddrphy_apb_wr(0x11360, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r3 +dwc_ddrphy_apb_wr(0x11440, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r4_p0 +dwc_ddrphy_apb_wr(0x11430, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r4 +dwc_ddrphy_apb_wr(0x11450, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r4 +dwc_ddrphy_apb_wr(0x11460, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r4 +dwc_ddrphy_apb_wr(0x11540, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r5_p0 +dwc_ddrphy_apb_wr(0x11530, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r5 +dwc_ddrphy_apb_wr(0x11550, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r5 +dwc_ddrphy_apb_wr(0x11560, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r5 +dwc_ddrphy_apb_wr(0x11640, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r6_p0 +dwc_ddrphy_apb_wr(0x11630, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r6 +dwc_ddrphy_apb_wr(0x11650, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r6 +dwc_ddrphy_apb_wr(0x11660, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r6 +dwc_ddrphy_apb_wr(0x11740, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r7_p0 +dwc_ddrphy_apb_wr(0x11730, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r7 +dwc_ddrphy_apb_wr(0x11750, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r7 +dwc_ddrphy_apb_wr(0x11760, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r7 +dwc_ddrphy_apb_wr(0x11840, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r8_p0 +dwc_ddrphy_apb_wr(0x11830, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r8 +dwc_ddrphy_apb_wr(0x11850, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r8 +dwc_ddrphy_apb_wr(0x11860, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r8 +//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DfiFreqRatio_p0 to 0x1 +dwc_ddrphy_apb_wr(0x200fa, 0x1); // DWC_DDRPHYA_MASTER0_base0_DfiFreqRatio_p0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg0 (dbyte=0) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg1 (dbyte=0) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg2 (dbyte=0) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg3 (dbyte=0) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg0 (dbyte=0) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg1 (dbyte=0) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg2 (dbyte=0) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg3 (dbyte=0) to 0x0 +dwc_ddrphy_apb_wr(0x100aa, 0x0); // DWC_DDRPHYA_DBYTE0_base0_PptCtlStatic +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg0 (dbyte=1) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg1 (dbyte=1) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg2 (dbyte=1) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg3 (dbyte=1) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg0 (dbyte=1) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg1 (dbyte=1) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg2 (dbyte=1) to 0x0 +//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg3 (dbyte=1) to 0x0 +dwc_ddrphy_apb_wr(0x110aa, 0x0); // DWC_DDRPHYA_DBYTE1_base0_PptCtlStatic +//// [phyinit_C_initPhyConfig] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x0 +dwc_ddrphy_apb_wr(0x200a6, 0x0); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables +//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=0) to 0xc +//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=4) to 0x8 +//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=6) to 0xf +//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=7) to 0xf +//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=8) to 0xf +//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=9) to 0xf +dwc_ddrphy_apb_wr(0x28, 0xc); // DWC_DDRPHYA_ANIB0_base0_AForceTriCont +dwc_ddrphy_apb_wr(0x4028, 0x8); // DWC_DDRPHYA_ANIB4_base0_AForceTriCont +dwc_ddrphy_apb_wr(0x6028, 0xf); // DWC_DDRPHYA_ANIB6_base0_AForceTriCont +dwc_ddrphy_apb_wr(0x7028, 0xf); // DWC_DDRPHYA_ANIB7_base0_AForceTriCont +dwc_ddrphy_apb_wr(0x8028, 0xf); // DWC_DDRPHYA_ANIB8_base0_AForceTriCont +dwc_ddrphy_apb_wr(0x9028, 0xf); // DWC_DDRPHYA_ANIB9_base0_AForceTriCont +//// [phyinit_C_initPhyConfig] End of dwc_ddrphy_phyinit_C_initPhyConfig() +// +// +////############################################################## +//// +//// dwc_ddrphy_phyinit_userCustom_customPreTrain is a user-editable function. +//// +//// The purpose of dwc_ddrphy_phyinit_userCustom_customPreTrain() is to override any +//// any message block fields calculated by Phyinit in dwc_ddrphy_phyinit_calcMb() or to +//// override any CSR values programmed by Phyinit in dwc_ddrphy_phyinit_C_initPhyConfig(). +//// This function is executed before training and thus any override here might affect +//// training result. +//// +//// IMPORTANT: in this function, user shall not override any values in userInputBasic and +//// userInputAdvanced data structures. Use dwc_ddrphy_phyinit_userCustom_overrideUserInput() +//// to modify values in those data structures. +//// +////############################################################## +// +//// [phyinit_userCustom_customPreTrain] Start of dwc_ddrphy_phyinit_userCustom_customPreTrain() +//// [phyinit_userCustom_customPreTrain] End of dwc_ddrphy_phyinit_userCustom_customPreTrain() +//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=0) +// +// +////############################################################## +//// +//// (D) Load the 1D IMEM image +//// +//// This function loads the training firmware IMEM image into the SRAM. +//// See PhyInit App Note for detailed description and function usage +//// +////############################################################## +// +// +//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Programming MemResetL to 0x2 +dwc_ddrphy_apb_wr(0x20060, 0x2); // DWC_DDRPHYA_MASTER0_base0_MemResetL +// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-17-01-49/firmware/Latest/training/ddr5/ddr5_pmu_train_imem.incv + +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +//// This allows the memory controller unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x50000 size 0x8000 +dwc_ddrphy_phyinit_userCustom_D_loadIMEM(sdrammc, 0); + +//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000 +//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +//// This allows the firmware unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] End of dwc_ddrphy_phyinit_D_loadIMEM() +// +// +////############################################################## +//// +//// 4.3.5(E) Set the PHY input clocks to the desired frequency for pstate 0 +//// +//// Set the PHY input Dfi Clk to the desired operating frequency associated with the given Pstate. Before proceeding to the next step, +//// the clock should be stable at the new frequency. For more information on clocking requirements, see "Clocks" on page <XXX>. +//// +////############################################################## +// +dwc_ddrphy_phyinit_userCustom_E_setDfiClk(sdrammc); + +// +//// [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk() +//// [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=0) +// +// +////############################################################## +//// +//// 4.3.5(F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware +//// +//// The procedure is as follows: +//// +////############################################################## +// +// +// +//// 1. Load the firmware DMEM segment to initialize the data structures. +// +//// 2. Write the Firmware Message Block with the required contents detailing the training parameters. +// +// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-17-01-49/firmware/Latest/training/ddr5/ddr5_pmu_train_dmem.incv + +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +//// This allows the memory controller unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x58000 size 0x8000 + +dwc_ddrphy_phyinit_userCustom_F_loadDMEM(sdrammc, 0, 0); + +dwc_ddrphy_apb_wr_32b(0x58000, 0x100); +dwc_ddrphy_apb_wr_32b(0x58002, 0xc800000); +dwc_ddrphy_apb_wr_32b(0x58004, 0x0); +dwc_ddrphy_apb_wr_32b(0x58006, 0x40); +if (IS_ENABLED(CONFIG_ASPEED_PHY_TRAINING_MESSAGE)) + dwc_ddrphy_apb_wr_32b(0x58008, 0x04827f); +else + dwc_ddrphy_apb_wr_32b(0x58008, 0xc8827f); +// Redmine 1392: Set X16Present=1 by Synopsys's comment +// 0x5800b[7:0]=DFIMRLMargin, 0x5800b[15:8]=X16Present +dwc_ddrphy_apb_wr_32b(0x5800a, 0x01020000); +// Redmine 1456: Skip_CA13_during_CAtraining during DDR5 +dwc_ddrphy_apb_wr_32b(0x5800c, 0x10000001); +// Redmine 1392: To speed up data collection, set the voltage and delay step size in Rx2D_TrainOpt and Tx2D_TrainOpt to its maximum value. +// uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5800e, Direction=In +// uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5800f, Direction=In +//dwc_ddrphy_apb_wr_32b(0x5800e, 0x001e1e00); +//#elif defined(TRAIN_1D) +//printf("- <DWC_DDRPHY TRAIN>: Enable RdDQS1D, WrDQ1D for 1D training"); +// #ifdef DWC_DEBUG +//printf("- <DWC_DDRPHY TRAIN>: Debug level = 0x05: Detailed debug messages (e.g. Eye delays)"); +//dwc_ddrphy_apb_wr_32b(0x58008, 0x05821f); +// #else +//printf("- <DWC_DDRPHY TRAIN>: Debug level = 0xC8: Stage completion"); +//dwc_ddrphy_apb_wr_32b(0x58008, 0xc8821f); +// #endif +//// Redmine 1392: Set X16Present=1 by Synopsys's comment +//dwc_ddrphy_apb_wr_32b(0x5800a, 0x01020000); +//// Redmine 1456: Skip_CA13_during_CAtraining during DDR5 +//dwc_ddrphy_apb_wr_32b(0x5800c, 0x18000001); +//// Redmine 1392: To speed up data collection, set the voltage and delay step size in Rx2D_TrainOpt and Tx2D_TrainOpt to its maximum value. +//// uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5800e, Direction=In +//// uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5800f, Direction=In +//dwc_ddrphy_apb_wr_32b(0x5800e, 0x001e1e00); +//#else +//dwc_ddrphy_apb_wr_32b(0x58008, 0xc8837f); +//dwc_ddrphy_apb_wr_32b(0x5800a, 0x20000); +//dwc_ddrphy_apb_wr_32b(0x5800c, 0x8000001); +//dwc_ddrphy_apb_wr_32b(0x5800e, 0x0); +//#endif +dwc_ddrphy_apb_wr_32b(0x58010, 0x0); +dwc_ddrphy_apb_wr_32b(0x58012, 0x110); +dwc_ddrphy_apb_wr_32b(0x58014, 0x0); +dwc_ddrphy_apb_wr_32b(0x58016, 0x0); +dwc_ddrphy_apb_wr_32b(0x58018, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5801e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58020, 0x0); +dwc_ddrphy_apb_wr_32b(0x58022, 0x0); +dwc_ddrphy_apb_wr_32b(0x58024, 0x0); +dwc_ddrphy_apb_wr_32b(0x58026, 0x0); +dwc_ddrphy_apb_wr_32b(0x58028, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5802e, 0x84080000); //MR0 0x5802f=0x8(CL=26), MR2 0x5802f=0x84(OP[2]=1 2N mode, OP[7]=enable internal WL training) +dwc_ddrphy_apb_wr_32b(0x58030, 0x200000); //MR5 0x58031=0x20(OP[5]=1 DM enable, OP[2:1]=0 pu 34ohm, 1=40ohm, 2=48ohm, OP7:6]=pd) +dwc_ddrphy_apb_wr_32b(0x58032, 0x2d000800); //MR8 0x58032=0x08(OP[4:3]=1 Write preamble 2 tCK) MR10 0x58033=0x2d(Vref 75%) +dwc_ddrphy_apb_wr_32b(0x58034, 0xd62d); +dwc_ddrphy_apb_wr_32b(0x58036, 0x04240003); //MR32 0x58037=0x24(OP[2:0]=4 CK ODT 80, OP[5:3]=4 CS ODT 80ohm), MR33 0x58037=0x4(OP[2:0]=4 CA ODTt 80ohm) +dwc_ddrphy_apb_wr_32b(0x58038, 0x2c000499); //MR34 0x58038(OP[5:3]=3 RTT_WR 80) +dwc_ddrphy_apb_wr_32b(0x5803a, 0x2c2c); +dwc_ddrphy_apb_wr_32b(0x5803c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5803e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58040, 0x0); +dwc_ddrphy_apb_wr_32b(0x58042, 0x408); +dwc_ddrphy_apb_wr_32b(0x58044, 0x8000020); +dwc_ddrphy_apb_wr_32b(0x58046, 0xd62d2d00); +dwc_ddrphy_apb_wr_32b(0x58048, 0x30000); +dwc_ddrphy_apb_wr_32b(0x5804a, 0x4110000); +dwc_ddrphy_apb_wr_32b(0x5804c, 0x2c2c2c00); +dwc_ddrphy_apb_wr_32b(0x5804e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58050, 0x0); +dwc_ddrphy_apb_wr_32b(0x58052, 0x0); +dwc_ddrphy_apb_wr_32b(0x58054, 0x4080000); +dwc_ddrphy_apb_wr_32b(0x58056, 0x200000); +dwc_ddrphy_apb_wr_32b(0x58058, 0x2d000800); +dwc_ddrphy_apb_wr_32b(0x5805a, 0xd62d); +dwc_ddrphy_apb_wr_32b(0x5805c, 0x3); +dwc_ddrphy_apb_wr_32b(0x5805e, 0x2c000411); +dwc_ddrphy_apb_wr_32b(0x58060, 0x2c2c); +dwc_ddrphy_apb_wr_32b(0x58062, 0x0); +dwc_ddrphy_apb_wr_32b(0x58064, 0x0); +dwc_ddrphy_apb_wr_32b(0x58066, 0x0); +dwc_ddrphy_apb_wr_32b(0x58068, 0x408); +dwc_ddrphy_apb_wr_32b(0x5806a, 0x8000020); +dwc_ddrphy_apb_wr_32b(0x5806c, 0xd62d2d00); +dwc_ddrphy_apb_wr_32b(0x5806e, 0x30000); +dwc_ddrphy_apb_wr_32b(0x58070, 0x4110000); +dwc_ddrphy_apb_wr_32b(0x58072, 0x2c2c2c00); +dwc_ddrphy_apb_wr_32b(0x58074, 0x0); +dwc_ddrphy_apb_wr_32b(0x58076, 0x0); +dwc_ddrphy_apb_wr_32b(0x58078, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5807e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58080, 0x0); +dwc_ddrphy_apb_wr_32b(0x58082, 0x0); +dwc_ddrphy_apb_wr_32b(0x58084, 0x0); +dwc_ddrphy_apb_wr_32b(0x58086, 0x0); +dwc_ddrphy_apb_wr_32b(0x58088, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5808e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58090, 0x0); +dwc_ddrphy_apb_wr_32b(0x58092, 0x0); +dwc_ddrphy_apb_wr_32b(0x58094, 0x0); +dwc_ddrphy_apb_wr_32b(0x58096, 0x0); +dwc_ddrphy_apb_wr_32b(0x58098, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5809e, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580a4, 0x4080000); +dwc_ddrphy_apb_wr_32b(0x580a6, 0x200000); +dwc_ddrphy_apb_wr_32b(0x580a8, 0x2d000800); +dwc_ddrphy_apb_wr_32b(0x580aa, 0xd62d); +dwc_ddrphy_apb_wr_32b(0x580ac, 0x3); +dwc_ddrphy_apb_wr_32b(0x580ae, 0x2c000411); +dwc_ddrphy_apb_wr_32b(0x580b0, 0x2c2c); +dwc_ddrphy_apb_wr_32b(0x580b2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580b8, 0x408); +dwc_ddrphy_apb_wr_32b(0x580ba, 0x8000020); +dwc_ddrphy_apb_wr_32b(0x580bc, 0xd62d2d00); +dwc_ddrphy_apb_wr_32b(0x580be, 0x30000); +dwc_ddrphy_apb_wr_32b(0x580c0, 0x4110000); +dwc_ddrphy_apb_wr_32b(0x580c2, 0x2c2c2c00); +dwc_ddrphy_apb_wr_32b(0x580c4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580c8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ca, 0x4080000); +dwc_ddrphy_apb_wr_32b(0x580cc, 0x200000); +dwc_ddrphy_apb_wr_32b(0x580ce, 0x2d000800); +dwc_ddrphy_apb_wr_32b(0x580d0, 0xd62d); +dwc_ddrphy_apb_wr_32b(0x580d2, 0x3); +dwc_ddrphy_apb_wr_32b(0x580d4, 0x2c000411); +dwc_ddrphy_apb_wr_32b(0x580d6, 0x2c2c); +dwc_ddrphy_apb_wr_32b(0x580d8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580da, 0x0); +dwc_ddrphy_apb_wr_32b(0x580dc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580de, 0x408); +dwc_ddrphy_apb_wr_32b(0x580e0, 0x8000020); +dwc_ddrphy_apb_wr_32b(0x580e2, 0xd62d2d00); +dwc_ddrphy_apb_wr_32b(0x580e4, 0x30000); +dwc_ddrphy_apb_wr_32b(0x580e6, 0x4110000); +dwc_ddrphy_apb_wr_32b(0x580e8, 0x2c2c2c00); +dwc_ddrphy_apb_wr_32b(0x580ea, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ec, 0x0); +dwc_ddrphy_apb_wr_32b(0x580ee, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f0, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f2, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f4, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f6, 0x0); +dwc_ddrphy_apb_wr_32b(0x580f8, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fa, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fc, 0x0); +dwc_ddrphy_apb_wr_32b(0x580fe, 0xa00060); // WL_ADJ_START, WL_ADJ_END +dwc_ddrphy_apb_wr_32b(0x58100, 0x1); +dwc_ddrphy_apb_wr_32b(0x58102, 0x0); +dwc_ddrphy_apb_wr_32b(0x58104, 0x0); +dwc_ddrphy_apb_wr_32b(0x58106, 0x0); +dwc_ddrphy_apb_wr_32b(0x58108, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5810e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58110, 0x0); +dwc_ddrphy_apb_wr_32b(0x58112, 0x0); +dwc_ddrphy_apb_wr_32b(0x58114, 0x0); +dwc_ddrphy_apb_wr_32b(0x58116, 0x0); +dwc_ddrphy_apb_wr_32b(0x58118, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5811e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58120, 0x0); +dwc_ddrphy_apb_wr_32b(0x58122, 0x0); +dwc_ddrphy_apb_wr_32b(0x58124, 0x0); +dwc_ddrphy_apb_wr_32b(0x58126, 0x0); +dwc_ddrphy_apb_wr_32b(0x58128, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5812e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58130, 0x0); +dwc_ddrphy_apb_wr_32b(0x58132, 0x0); +dwc_ddrphy_apb_wr_32b(0x58134, 0x0); +dwc_ddrphy_apb_wr_32b(0x58136, 0x0); +dwc_ddrphy_apb_wr_32b(0x58138, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5813e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58140, 0x0); +dwc_ddrphy_apb_wr_32b(0x58142, 0x0); +dwc_ddrphy_apb_wr_32b(0x58144, 0x0); +dwc_ddrphy_apb_wr_32b(0x58146, 0x0); +dwc_ddrphy_apb_wr_32b(0x58148, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5814e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58150, 0x0); +dwc_ddrphy_apb_wr_32b(0x58152, 0x0); +dwc_ddrphy_apb_wr_32b(0x58154, 0x0); +dwc_ddrphy_apb_wr_32b(0x58156, 0x0); +dwc_ddrphy_apb_wr_32b(0x58158, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5815e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58160, 0x0); +dwc_ddrphy_apb_wr_32b(0x58162, 0x0); +dwc_ddrphy_apb_wr_32b(0x58164, 0x0); +dwc_ddrphy_apb_wr_32b(0x58166, 0x0); +dwc_ddrphy_apb_wr_32b(0x58168, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5816e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58170, 0x0); +dwc_ddrphy_apb_wr_32b(0x58172, 0x0); +dwc_ddrphy_apb_wr_32b(0x58174, 0x0); +dwc_ddrphy_apb_wr_32b(0x58176, 0x0); +dwc_ddrphy_apb_wr_32b(0x58178, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5817e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58180, 0x1); +dwc_ddrphy_apb_wr_32b(0x58182, 0x0); +dwc_ddrphy_apb_wr_32b(0x58184, 0x0); +dwc_ddrphy_apb_wr_32b(0x58186, 0x0); +dwc_ddrphy_apb_wr_32b(0x58188, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5818e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58190, 0x0); +dwc_ddrphy_apb_wr_32b(0x58192, 0x0); +dwc_ddrphy_apb_wr_32b(0x58194, 0x0); +dwc_ddrphy_apb_wr_32b(0x58196, 0x0); +dwc_ddrphy_apb_wr_32b(0x58198, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5819e, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581a8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581aa, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ac, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ae, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581b8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ba, 0x0); +dwc_ddrphy_apb_wr_32b(0x581bc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581be, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581c8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ca, 0x0); +dwc_ddrphy_apb_wr_32b(0x581cc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ce, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581d8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581da, 0x0); +dwc_ddrphy_apb_wr_32b(0x581dc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581de, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581e8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ea, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ec, 0x0); +dwc_ddrphy_apb_wr_32b(0x581ee, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f0, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f2, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f4, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f6, 0x0); +dwc_ddrphy_apb_wr_32b(0x581f8, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fa, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fc, 0x0); +dwc_ddrphy_apb_wr_32b(0x581fe, 0x0); +dwc_ddrphy_apb_wr_32b(0x58200, 0x1); +dwc_ddrphy_apb_wr_32b(0x58202, 0x0); +dwc_ddrphy_apb_wr_32b(0x58204, 0x0); +dwc_ddrphy_apb_wr_32b(0x58206, 0x0); +dwc_ddrphy_apb_wr_32b(0x58208, 0x0); +dwc_ddrphy_apb_wr_32b(0x5820a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5820c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5820e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58210, 0x0); +dwc_ddrphy_apb_wr_32b(0x58212, 0x0); +dwc_ddrphy_apb_wr_32b(0x58214, 0x0); +dwc_ddrphy_apb_wr_32b(0x58216, 0x0); +dwc_ddrphy_apb_wr_32b(0x58218, 0x0); +dwc_ddrphy_apb_wr_32b(0x5821a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5821c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5821e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58220, 0x0); +dwc_ddrphy_apb_wr_32b(0x58222, 0x0); +dwc_ddrphy_apb_wr_32b(0x58224, 0x0); +dwc_ddrphy_apb_wr_32b(0x58226, 0x0); +dwc_ddrphy_apb_wr_32b(0x58228, 0x0); +dwc_ddrphy_apb_wr_32b(0x5822a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5822c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5822e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58230, 0x0); +dwc_ddrphy_apb_wr_32b(0x58232, 0x0); +dwc_ddrphy_apb_wr_32b(0x58234, 0x0); +dwc_ddrphy_apb_wr_32b(0x58236, 0x0); +dwc_ddrphy_apb_wr_32b(0x58238, 0x0); +dwc_ddrphy_apb_wr_32b(0x5823a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5823c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5823e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58240, 0x0); +dwc_ddrphy_apb_wr_32b(0x58242, 0x0); +dwc_ddrphy_apb_wr_32b(0x58244, 0x0); +dwc_ddrphy_apb_wr_32b(0x58246, 0x0); +dwc_ddrphy_apb_wr_32b(0x58248, 0x0); +dwc_ddrphy_apb_wr_32b(0x5824a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5824c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5824e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58250, 0x0); +dwc_ddrphy_apb_wr_32b(0x58252, 0x0); +dwc_ddrphy_apb_wr_32b(0x58254, 0x0); +dwc_ddrphy_apb_wr_32b(0x58256, 0x0); +dwc_ddrphy_apb_wr_32b(0x58258, 0x0); +dwc_ddrphy_apb_wr_32b(0x5825a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5825c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5825e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58260, 0x0); +dwc_ddrphy_apb_wr_32b(0x58262, 0x0); +dwc_ddrphy_apb_wr_32b(0x58264, 0x0); +dwc_ddrphy_apb_wr_32b(0x58266, 0x0); +dwc_ddrphy_apb_wr_32b(0x58268, 0x0); +dwc_ddrphy_apb_wr_32b(0x5826a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5826c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5826e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58270, 0x0); +dwc_ddrphy_apb_wr_32b(0x58272, 0x0); +dwc_ddrphy_apb_wr_32b(0x58274, 0x0); +dwc_ddrphy_apb_wr_32b(0x58276, 0x0); +dwc_ddrphy_apb_wr_32b(0x58278, 0x0); +dwc_ddrphy_apb_wr_32b(0x5827a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5827c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5827e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58280, 0x1); +dwc_ddrphy_apb_wr_32b(0x58282, 0x0); +dwc_ddrphy_apb_wr_32b(0x58284, 0x0); +dwc_ddrphy_apb_wr_32b(0x58286, 0x0); +dwc_ddrphy_apb_wr_32b(0x58288, 0x0); +dwc_ddrphy_apb_wr_32b(0x5828a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5828c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5828e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58290, 0x0); +dwc_ddrphy_apb_wr_32b(0x58292, 0x0); +dwc_ddrphy_apb_wr_32b(0x58294, 0x0); +dwc_ddrphy_apb_wr_32b(0x58296, 0x0); +dwc_ddrphy_apb_wr_32b(0x58298, 0x0); +dwc_ddrphy_apb_wr_32b(0x5829a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5829c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5829e, 0x0); +dwc_ddrphy_apb_wr_32b(0x582a0, 0x0); +dwc_ddrphy_apb_wr_32b(0x582a2, 0x0); +dwc_ddrphy_apb_wr_32b(0x582a4, 0x0); +dwc_ddrphy_apb_wr_32b(0x582a6, 0x0); +dwc_ddrphy_apb_wr_32b(0x582a8, 0x0); +dwc_ddrphy_apb_wr_32b(0x582aa, 0x0); +dwc_ddrphy_apb_wr_32b(0x582ac, 0x0); +dwc_ddrphy_apb_wr_32b(0x582ae, 0x0); +dwc_ddrphy_apb_wr_32b(0x582b0, 0x0); +dwc_ddrphy_apb_wr_32b(0x582b2, 0x0); +dwc_ddrphy_apb_wr_32b(0x582b4, 0x0); +dwc_ddrphy_apb_wr_32b(0x582b6, 0x0); +dwc_ddrphy_apb_wr_32b(0x582b8, 0x0); +dwc_ddrphy_apb_wr_32b(0x582ba, 0x0); +dwc_ddrphy_apb_wr_32b(0x582bc, 0x0); +dwc_ddrphy_apb_wr_32b(0x582be, 0x0); +dwc_ddrphy_apb_wr_32b(0x582c0, 0x0); +dwc_ddrphy_apb_wr_32b(0x582c2, 0x0); +dwc_ddrphy_apb_wr_32b(0x582c4, 0x0); +dwc_ddrphy_apb_wr_32b(0x582c6, 0x0); +dwc_ddrphy_apb_wr_32b(0x582c8, 0x0); +dwc_ddrphy_apb_wr_32b(0x582ca, 0x0); +dwc_ddrphy_apb_wr_32b(0x582cc, 0x0); +dwc_ddrphy_apb_wr_32b(0x582ce, 0x0); +dwc_ddrphy_apb_wr_32b(0x582d0, 0x0); +dwc_ddrphy_apb_wr_32b(0x582d2, 0x0); +dwc_ddrphy_apb_wr_32b(0x582d4, 0x0); +dwc_ddrphy_apb_wr_32b(0x582d6, 0x0); +dwc_ddrphy_apb_wr_32b(0x582d8, 0x0); +dwc_ddrphy_apb_wr_32b(0x582da, 0x0); +dwc_ddrphy_apb_wr_32b(0x582dc, 0x0); +dwc_ddrphy_apb_wr_32b(0x582de, 0x0); +dwc_ddrphy_apb_wr_32b(0x582e0, 0x0); +dwc_ddrphy_apb_wr_32b(0x582e2, 0x0); +dwc_ddrphy_apb_wr_32b(0x582e4, 0x0); +dwc_ddrphy_apb_wr_32b(0x582e6, 0x0); +dwc_ddrphy_apb_wr_32b(0x582e8, 0x0); +dwc_ddrphy_apb_wr_32b(0x582ea, 0x0); +dwc_ddrphy_apb_wr_32b(0x582ec, 0x0); +dwc_ddrphy_apb_wr_32b(0x582ee, 0x0); +dwc_ddrphy_apb_wr_32b(0x582f0, 0x0); +dwc_ddrphy_apb_wr_32b(0x582f2, 0x0); +dwc_ddrphy_apb_wr_32b(0x582f4, 0x0); +dwc_ddrphy_apb_wr_32b(0x582f6, 0x0); +dwc_ddrphy_apb_wr_32b(0x582f8, 0x0); +dwc_ddrphy_apb_wr_32b(0x582fa, 0x0); +dwc_ddrphy_apb_wr_32b(0x582fc, 0x0); +dwc_ddrphy_apb_wr_32b(0x582fe, 0x0); +dwc_ddrphy_apb_wr_32b(0x58300, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58302, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58304, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58306, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58308, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x5830a, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x5830c, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x5830e, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58310, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58312, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58314, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58316, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58318, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x5831a, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x5831c, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x5831e, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58320, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58322, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58324, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58326, 0x17171717); +dwc_ddrphy_apb_wr_32b(0x58328, 0x0); +dwc_ddrphy_apb_wr_32b(0x5832a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5832c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5832e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58330, 0x0); +dwc_ddrphy_apb_wr_32b(0x58332, 0x0); +dwc_ddrphy_apb_wr_32b(0x58334, 0x0); +dwc_ddrphy_apb_wr_32b(0x58336, 0x0); +dwc_ddrphy_apb_wr_32b(0x58338, 0x0); +dwc_ddrphy_apb_wr_32b(0x5833a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5833c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5833e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58340, 0x0); +dwc_ddrphy_apb_wr_32b(0x58342, 0x0); +dwc_ddrphy_apb_wr_32b(0x58344, 0x0); +dwc_ddrphy_apb_wr_32b(0x58346, 0x0); +dwc_ddrphy_apb_wr_32b(0x58348, 0x0); +dwc_ddrphy_apb_wr_32b(0x5834a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5834c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5834e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58350, 0x0); +dwc_ddrphy_apb_wr_32b(0x58352, 0x0); +dwc_ddrphy_apb_wr_32b(0x58354, 0x0); +dwc_ddrphy_apb_wr_32b(0x58356, 0x0); +dwc_ddrphy_apb_wr_32b(0x58358, 0x0); +dwc_ddrphy_apb_wr_32b(0x5835a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5835c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5835e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58360, 0x0); +dwc_ddrphy_apb_wr_32b(0x58362, 0x0); +dwc_ddrphy_apb_wr_32b(0x58364, 0x0); +dwc_ddrphy_apb_wr_32b(0x58366, 0x0); +dwc_ddrphy_apb_wr_32b(0x58368, 0x0); +dwc_ddrphy_apb_wr_32b(0x5836a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5836c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5836e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58370, 0x0); +dwc_ddrphy_apb_wr_32b(0x58372, 0x0); +dwc_ddrphy_apb_wr_32b(0x58374, 0x0); +dwc_ddrphy_apb_wr_32b(0x58376, 0x0); +dwc_ddrphy_apb_wr_32b(0x58378, 0x0); +dwc_ddrphy_apb_wr_32b(0x5837a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5837c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5837e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58380, 0x0); +dwc_ddrphy_apb_wr_32b(0x58382, 0x0); +dwc_ddrphy_apb_wr_32b(0x58384, 0x0); +dwc_ddrphy_apb_wr_32b(0x58386, 0x0); +dwc_ddrphy_apb_wr_32b(0x58388, 0x0); +dwc_ddrphy_apb_wr_32b(0x5838a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5838c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5838e, 0x0); +dwc_ddrphy_apb_wr_32b(0x58390, 0x0); +dwc_ddrphy_apb_wr_32b(0x58392, 0x0); +dwc_ddrphy_apb_wr_32b(0x58394, 0x0); +dwc_ddrphy_apb_wr_32b(0x58396, 0x0); +dwc_ddrphy_apb_wr_32b(0x58398, 0x0); +dwc_ddrphy_apb_wr_32b(0x5839a, 0x0); +dwc_ddrphy_apb_wr_32b(0x5839c, 0x0); +dwc_ddrphy_apb_wr_32b(0x5839e, 0x0); +dwc_ddrphy_apb_wr_32b(0x583a0, 0x0); +dwc_ddrphy_apb_wr_32b(0x583a2, 0x0); +dwc_ddrphy_apb_wr_32b(0x583a4, 0x0); +dwc_ddrphy_apb_wr_32b(0x583a6, 0x0); +dwc_ddrphy_apb_wr_32b(0x583a8, 0x0); +dwc_ddrphy_apb_wr_32b(0x583aa, 0x0); +dwc_ddrphy_apb_wr_32b(0x583ac, 0x0); +dwc_ddrphy_apb_wr_32b(0x583ae, 0x0); +dwc_ddrphy_apb_wr_32b(0x583b0, 0x0); +dwc_ddrphy_apb_wr_32b(0x583b2, 0x0); +dwc_ddrphy_apb_wr_32b(0x583b4, 0x0); +dwc_ddrphy_apb_wr_32b(0x583b6, 0x0); +dwc_ddrphy_apb_wr_32b(0x583b8, 0x0); +dwc_ddrphy_apb_wr_32b(0x583ba, 0x0); +dwc_ddrphy_apb_wr_32b(0x583bc, 0x0); +dwc_ddrphy_apb_wr_32b(0x583be, 0x0); +dwc_ddrphy_apb_wr_32b(0x583c0, 0x0); +dwc_ddrphy_apb_wr_32b(0x583c2, 0x0); +dwc_ddrphy_apb_wr_32b(0x583c4, 0x0); +dwc_ddrphy_apb_wr_32b(0x583c6, 0x0); +dwc_ddrphy_apb_wr_32b(0x583c8, 0x0); +dwc_ddrphy_apb_wr_32b(0x583ca, 0x0); +dwc_ddrphy_apb_wr_32b(0x583cc, 0x0); +dwc_ddrphy_apb_wr_32b(0x583ce, 0x0); +dwc_ddrphy_apb_wr_32b(0x583d0, 0x0); +dwc_ddrphy_apb_wr_32b(0x583d2, 0x0); +dwc_ddrphy_apb_wr_32b(0x583d4, 0x0); +dwc_ddrphy_apb_wr_32b(0x583d6, 0x0); +dwc_ddrphy_apb_wr_32b(0x583d8, 0x0); +dwc_ddrphy_apb_wr_32b(0x583da, 0x0); +dwc_ddrphy_apb_wr_32b(0x583dc, 0x0); +dwc_ddrphy_apb_wr_32b(0x583de, 0x0); +dwc_ddrphy_apb_wr_32b(0x583e0, 0x0); +dwc_ddrphy_apb_wr_32b(0x583e2, 0x0); +dwc_ddrphy_apb_wr_32b(0x583e4, 0x0); +dwc_ddrphy_apb_wr_32b(0x583e6, 0x0); +dwc_ddrphy_apb_wr_32b(0x583e8, 0x0); +dwc_ddrphy_apb_wr_32b(0x583ea, 0x0); +dwc_ddrphy_apb_wr_32b(0x583ec, 0x0); +dwc_ddrphy_apb_wr_32b(0x583ee, 0x0); +dwc_ddrphy_apb_wr_32b(0x583f0, 0x0); +dwc_ddrphy_apb_wr_32b(0x583f2, 0x0); +dwc_ddrphy_apb_wr_32b(0x583f4, 0x0); +dwc_ddrphy_apb_wr_32b(0x583f6, 0x0); +dwc_ddrphy_apb_wr_32b(0x583f8, 0x0); +dwc_ddrphy_apb_wr_32b(0x583fa, 0x0); +dwc_ddrphy_apb_wr_32b(0x583fc, 0x0); +dwc_ddrphy_apb_wr_32b(0x583fe, 0x0); +//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000 +//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +//// This allows the firmware unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM() +// +// +////############################################################## +//// +//// 4.3.7(G) Execute the Training Firmware +//// +//// The training firmware is executed with the following procedure: +//// +////############################################################## +// +// +//// 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and +//// ResetToMicro fields to 1 (all other fields should be zero). +//// Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero). +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +dwc_ddrphy_apb_wr(0xd0099, 0x9); // DWC_DDRPHYA_APBONLY0_MicroReset +dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset +// +//// 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000. +dwc_ddrphy_apb_wr(0xd0099, 0x0); // DWC_DDRPHYA_APBONLY0_MicroReset +// +//// 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging" +//// 4.3.7 3. Wait for the training firmware to complete. Implement timeout function or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message. +dwc_ddrphy_phyinit_userCustom_G_waitFwDone(sdrammc); + +//// [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone() +//// 4. Halt the microcontroller." +dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset +dwc_ddrphy_apb_wr(0x20089, 0x0); // DWC_DDRPHYA_MASTER0_base0_CalZap +//// [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW() +// +// +////############################################################## +//// +//// 4.3.8(H) Read the Message Block results +//// +//// The procedure is as follows: +//// +////############################################################## +// +// +//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +// +//2. Read the Firmware Message Block to obtain the results from the training. +//This can be accomplished by issuing APB read commands to the DMEM addresses. +//Example: +//if (Train2D) +//{ +// _read_2d_message_block_outputs_ +//} +//else +//{ +// _read_1d_message_block_outputs_ +//} +//This can be accomplished by issuing APB read commands to the DMEM addresses. +dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(sdrammc, 0); + +//[dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock() +//// 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// 4. If training is required at another frequency, repeat the operations starting at step (E). +//// [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock() +//// [initRuntimeConfigEnableBits] Start of initRuntimeConfigEnableBits() +//// [initRuntimeConfigEnableBits] enableBits[0] = 0x00000009 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A0 = 0x00000000, rtt_required = 0x00000001 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A1 = 0x00000000, rtt_required = 0x00000002 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A2 = 0x00000000, rtt_required = 0x00000004 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A3 = 0x00000000, rtt_required = 0x00000008 +//// [initRuntimeConfigEnableBits] enableBits[1] = 0x00000000 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B0 = 0x00000000, rtt_required = 0x00000001 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B1 = 0x00000000, rtt_required = 0x00000002 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B2 = 0x00000000, rtt_required = 0x00000004 +//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B3 = 0x00000000, rtt_required = 0x00000008 +//// [initRuntimeConfigEnableBits] enableBits[2] = 0x00000000 +//// [initRuntimeConfigEnableBits] End of initRuntimeConfigEnableBits() +//// [phyinit_I_loadPIEImage] Start of dwc_ddrphy_phyinit_I_loadPIEImage() +// +// +////############################################################## +//// +//// 4.3.9(I) Load PHY Init Engine Image +//// +//// Load the PHY Initialization Engine memory with the provided initialization sequence. +//// +////############################################################## +// +// +//// Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. +//// This allows the memory controller unrestricted access to the configuration CSRs. +dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [phyinit_I_loadPIEImage] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x1 +dwc_ddrphy_apb_wr(0x200a6, 0x2); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables +//// [phyinit_I_loadPIEImage] Programming PIE Production Code +//// [phyinit_LoadPIECodeSections] Start of dwc_ddrphy_phyinit_LoadPIECodeSections() +//// [phyinit_LoadPIECodeSections] Moving start address from 0 to 90000 +dwc_ddrphy_apb_wr(0x90000, 0x10); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s0 +dwc_ddrphy_apb_wr(0x90001, 0x400); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s1 +dwc_ddrphy_apb_wr(0x90002, 0x10e); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s2 +dwc_ddrphy_apb_wr(0x90003, 0x0); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s0 +dwc_ddrphy_apb_wr(0x90004, 0x0); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s1 +dwc_ddrphy_apb_wr(0x90005, 0x8); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s2 +//// [phyinit_LoadPIECodeSections] Moving start address from 90006 to 41000 +dwc_ddrphy_apb_wr(0x41000, 0x3fff); +dwc_ddrphy_apb_wr(0x41001, 0xff00); +dwc_ddrphy_apb_wr(0x41002, 0x3f); +dwc_ddrphy_apb_wr(0x41003, 0x2c1); +dwc_ddrphy_apb_wr(0x41004, 0x3fff); +dwc_ddrphy_apb_wr(0x41005, 0xff00); +dwc_ddrphy_apb_wr(0x41006, 0x3f); +dwc_ddrphy_apb_wr(0x41007, 0xa01); +dwc_ddrphy_apb_wr(0x41008, 0x3fff); +dwc_ddrphy_apb_wr(0x41009, 0xff00); +dwc_ddrphy_apb_wr(0x4100a, 0x3f); +dwc_ddrphy_apb_wr(0x4100b, 0x1); +dwc_ddrphy_apb_wr(0x4100c, 0xffff); +dwc_ddrphy_apb_wr(0x4100d, 0xff03); +dwc_ddrphy_apb_wr(0x4100e, 0x3ff); +dwc_ddrphy_apb_wr(0x4100f, 0x0); +dwc_ddrphy_apb_wr(0x41010, 0xffff); +dwc_ddrphy_apb_wr(0x41011, 0xff03); +dwc_ddrphy_apb_wr(0x41012, 0x3ff); +dwc_ddrphy_apb_wr(0x41013, 0x1c1); +dwc_ddrphy_apb_wr(0x41014, 0xffff); +dwc_ddrphy_apb_wr(0x41015, 0xff03); +dwc_ddrphy_apb_wr(0x41016, 0x3ff); +dwc_ddrphy_apb_wr(0x41017, 0x1); +dwc_ddrphy_apb_wr(0x41018, 0xffff); +dwc_ddrphy_apb_wr(0x41019, 0xff03); +dwc_ddrphy_apb_wr(0x4101a, 0x3ff); +dwc_ddrphy_apb_wr(0x4101b, 0x2c1); +dwc_ddrphy_apb_wr(0x4101c, 0xffff); +dwc_ddrphy_apb_wr(0x4101d, 0xff03); +dwc_ddrphy_apb_wr(0x4101e, 0x3ff); +dwc_ddrphy_apb_wr(0x4101f, 0x101); +dwc_ddrphy_apb_wr(0x41020, 0x3fff); +dwc_ddrphy_apb_wr(0x41021, 0xff00); +dwc_ddrphy_apb_wr(0x41022, 0x3f); +dwc_ddrphy_apb_wr(0x41023, 0x1); +dwc_ddrphy_apb_wr(0x41024, 0x3fff); +dwc_ddrphy_apb_wr(0x41025, 0xff00); +dwc_ddrphy_apb_wr(0x41026, 0x3ff); +dwc_ddrphy_apb_wr(0x41027, 0x1); +dwc_ddrphy_apb_wr(0x41028, 0xffff); +dwc_ddrphy_apb_wr(0x41029, 0xff03); +dwc_ddrphy_apb_wr(0x4102a, 0x3ff); +dwc_ddrphy_apb_wr(0x4102b, 0x2c1); +dwc_ddrphy_apb_wr(0x4102c, 0xffff); +dwc_ddrphy_apb_wr(0x4102d, 0xff03); +dwc_ddrphy_apb_wr(0x4102e, 0x3ff); +dwc_ddrphy_apb_wr(0x4102f, 0xf901); +dwc_ddrphy_apb_wr(0x41030, 0xffff); +dwc_ddrphy_apb_wr(0x41031, 0xff03); +dwc_ddrphy_apb_wr(0x41032, 0x3ff); +dwc_ddrphy_apb_wr(0x41033, 0x2c1); +dwc_ddrphy_apb_wr(0x41034, 0xffff); +dwc_ddrphy_apb_wr(0x41035, 0xff03); +dwc_ddrphy_apb_wr(0x41036, 0x3ff); +dwc_ddrphy_apb_wr(0x41037, 0x5901); +dwc_ddrphy_apb_wr(0x41038, 0x5a5); +dwc_ddrphy_apb_wr(0x41039, 0x4000); +dwc_ddrphy_apb_wr(0x4103a, 0x3c0); +dwc_ddrphy_apb_wr(0x4103b, 0x1); +dwc_ddrphy_apb_wr(0x4103c, 0xc000); +dwc_ddrphy_apb_wr(0x4103d, 0x3); +dwc_ddrphy_apb_wr(0x4103e, 0x3c0); +dwc_ddrphy_apb_wr(0x4103f, 0x0); +dwc_ddrphy_apb_wr(0x41040, 0xc000); +dwc_ddrphy_apb_wr(0x41041, 0x3); +dwc_ddrphy_apb_wr(0x41042, 0x3c0); +dwc_ddrphy_apb_wr(0x41043, 0x2c1); +dwc_ddrphy_apb_wr(0x41044, 0xc000); +dwc_ddrphy_apb_wr(0x41045, 0x3); +dwc_ddrphy_apb_wr(0x41046, 0x3c0); +dwc_ddrphy_apb_wr(0x41047, 0xa01); +dwc_ddrphy_apb_wr(0x41048, 0xef); +dwc_ddrphy_apb_wr(0x41049, 0xef00); +dwc_ddrphy_apb_wr(0x4104a, 0x3c0); +dwc_ddrphy_apb_wr(0x4104b, 0x1); +dwc_ddrphy_apb_wr(0x4104c, 0xc000); +dwc_ddrphy_apb_wr(0x4104d, 0x3); +dwc_ddrphy_apb_wr(0x4104e, 0x3c0); +dwc_ddrphy_apb_wr(0x4104f, 0x0); +dwc_ddrphy_apb_wr(0x41050, 0xc000); +dwc_ddrphy_apb_wr(0x41051, 0x3); +dwc_ddrphy_apb_wr(0x41052, 0x3c0); +dwc_ddrphy_apb_wr(0x41053, 0x2c1); +dwc_ddrphy_apb_wr(0x41054, 0xc000); +dwc_ddrphy_apb_wr(0x41055, 0x3); +dwc_ddrphy_apb_wr(0x41056, 0x3c0); +dwc_ddrphy_apb_wr(0x41057, 0xff01); +dwc_ddrphy_apb_wr(0x41058, 0xc000); +dwc_ddrphy_apb_wr(0x41059, 0x3); +dwc_ddrphy_apb_wr(0x4105a, 0x3c0); +dwc_ddrphy_apb_wr(0x4105b, 0x2c1); +dwc_ddrphy_apb_wr(0x4105c, 0xc000); +dwc_ddrphy_apb_wr(0x4105d, 0x3); +dwc_ddrphy_apb_wr(0x4105e, 0x3c0); +dwc_ddrphy_apb_wr(0x4105f, 0xff01); +dwc_ddrphy_apb_wr(0x41060, 0xc000); +dwc_ddrphy_apb_wr(0x41061, 0x3); +dwc_ddrphy_apb_wr(0x41062, 0x3c0); +dwc_ddrphy_apb_wr(0x41063, 0x2c1); +dwc_ddrphy_apb_wr(0x41064, 0xc000); +dwc_ddrphy_apb_wr(0x41065, 0x3); +dwc_ddrphy_apb_wr(0x41066, 0x3c0); +dwc_ddrphy_apb_wr(0x41067, 0xa01); +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 0 +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 4, type = 0 +dwc_ddrphy_apb_wr(0x41068, 0x85d5); +dwc_ddrphy_apb_wr(0x41069, 0x63); +dwc_ddrphy_apb_wr(0x4106a, 0x3c0); +dwc_ddrphy_apb_wr(0x4106b, 0x400); +dwc_ddrphy_apb_wr(0x4106c, 0xc000); +dwc_ddrphy_apb_wr(0x4106d, 0x3); +dwc_ddrphy_apb_wr(0x4106e, 0x3c0); +dwc_ddrphy_apb_wr(0x4106f, 0x0); +dwc_ddrphy_apb_wr(0x41070, 0xc000); +dwc_ddrphy_apb_wr(0x41071, 0x3); +dwc_ddrphy_apb_wr(0x41072, 0x3c0); +dwc_ddrphy_apb_wr(0x41073, 0x2c1); +dwc_ddrphy_apb_wr(0x41074, 0xc000); +dwc_ddrphy_apb_wr(0x41075, 0x3); +dwc_ddrphy_apb_wr(0x41076, 0x3c0); +dwc_ddrphy_apb_wr(0x41077, 0x1001); +dwc_ddrphy_apb_wr(0x41078, 0x85f5); +dwc_ddrphy_apb_wr(0x41079, 0x63); +dwc_ddrphy_apb_wr(0x4107a, 0x3c0); +dwc_ddrphy_apb_wr(0x4107b, 0x800); +dwc_ddrphy_apb_wr(0x4107c, 0xc000); +dwc_ddrphy_apb_wr(0x4107d, 0x3); +dwc_ddrphy_apb_wr(0x4107e, 0x3c0); +dwc_ddrphy_apb_wr(0x4107f, 0x0); +dwc_ddrphy_apb_wr(0x41080, 0xc000); +dwc_ddrphy_apb_wr(0x41081, 0x3); +dwc_ddrphy_apb_wr(0x41082, 0x3c0); +dwc_ddrphy_apb_wr(0x41083, 0x2c1); +dwc_ddrphy_apb_wr(0x41084, 0xc000); +dwc_ddrphy_apb_wr(0x41085, 0x3); +dwc_ddrphy_apb_wr(0x41086, 0x3c0); +dwc_ddrphy_apb_wr(0x41087, 0x1001); +dwc_ddrphy_apb_wr(0x41088, 0x45d5); +dwc_ddrphy_apb_wr(0x41089, 0x63); +dwc_ddrphy_apb_wr(0x4108a, 0x3c0); +dwc_ddrphy_apb_wr(0x4108b, 0x401); +dwc_ddrphy_apb_wr(0x4108c, 0xc000); +dwc_ddrphy_apb_wr(0x4108d, 0x3); +dwc_ddrphy_apb_wr(0x4108e, 0x3c0); +dwc_ddrphy_apb_wr(0x4108f, 0x1); +dwc_ddrphy_apb_wr(0x41090, 0xc000); +dwc_ddrphy_apb_wr(0x41091, 0x3); +dwc_ddrphy_apb_wr(0x41092, 0x3c0); +dwc_ddrphy_apb_wr(0x41093, 0x2c1); +dwc_ddrphy_apb_wr(0x41094, 0xc000); +dwc_ddrphy_apb_wr(0x41095, 0x3); +dwc_ddrphy_apb_wr(0x41096, 0x3c0); +dwc_ddrphy_apb_wr(0x41097, 0x1001); +dwc_ddrphy_apb_wr(0x41098, 0x45f5); +dwc_ddrphy_apb_wr(0x41099, 0x63); +dwc_ddrphy_apb_wr(0x4109a, 0x3c0); +dwc_ddrphy_apb_wr(0x4109b, 0x801); +dwc_ddrphy_apb_wr(0x4109c, 0xc000); +dwc_ddrphy_apb_wr(0x4109d, 0x3); +dwc_ddrphy_apb_wr(0x4109e, 0x3c0); +dwc_ddrphy_apb_wr(0x4109f, 0x1); +dwc_ddrphy_apb_wr(0x410a0, 0xc000); +dwc_ddrphy_apb_wr(0x410a1, 0x3); +dwc_ddrphy_apb_wr(0x410a2, 0x3c0); +dwc_ddrphy_apb_wr(0x410a3, 0x2c1); +dwc_ddrphy_apb_wr(0x410a4, 0xc000); +dwc_ddrphy_apb_wr(0x410a5, 0x3); +dwc_ddrphy_apb_wr(0x410a6, 0x3c0); +dwc_ddrphy_apb_wr(0x410a7, 0x1001); +dwc_ddrphy_apb_wr(0x410a8, 0xc5d5); +dwc_ddrphy_apb_wr(0x410a9, 0x62); +dwc_ddrphy_apb_wr(0x410aa, 0x3c0); +dwc_ddrphy_apb_wr(0x410ab, 0x402); +dwc_ddrphy_apb_wr(0x410ac, 0xc000); +dwc_ddrphy_apb_wr(0x410ad, 0x3); +dwc_ddrphy_apb_wr(0x410ae, 0x3c0); +dwc_ddrphy_apb_wr(0x410af, 0x2); +dwc_ddrphy_apb_wr(0x410b0, 0xc000); +dwc_ddrphy_apb_wr(0x410b1, 0x3); +dwc_ddrphy_apb_wr(0x410b2, 0x3c0); +dwc_ddrphy_apb_wr(0x410b3, 0x2c1); +dwc_ddrphy_apb_wr(0x410b4, 0xc000); +dwc_ddrphy_apb_wr(0x410b5, 0x3); +dwc_ddrphy_apb_wr(0x410b6, 0x3c0); +dwc_ddrphy_apb_wr(0x410b7, 0x1001); +dwc_ddrphy_apb_wr(0x410b8, 0xc5f5); +dwc_ddrphy_apb_wr(0x410b9, 0x62); +dwc_ddrphy_apb_wr(0x410ba, 0x3c0); +dwc_ddrphy_apb_wr(0x410bb, 0x802); +dwc_ddrphy_apb_wr(0x410bc, 0xc000); +dwc_ddrphy_apb_wr(0x410bd, 0x3); +dwc_ddrphy_apb_wr(0x410be, 0x3c0); +dwc_ddrphy_apb_wr(0x410bf, 0x2); +dwc_ddrphy_apb_wr(0x410c0, 0xc000); +dwc_ddrphy_apb_wr(0x410c1, 0x3); +dwc_ddrphy_apb_wr(0x410c2, 0x3c0); +dwc_ddrphy_apb_wr(0x410c3, 0x2c1); +dwc_ddrphy_apb_wr(0x410c4, 0xc000); +dwc_ddrphy_apb_wr(0x410c5, 0x3); +dwc_ddrphy_apb_wr(0x410c6, 0x3c0); +dwc_ddrphy_apb_wr(0x410c7, 0x1001); +dwc_ddrphy_apb_wr(0x410c8, 0xc5d5); +dwc_ddrphy_apb_wr(0x410c9, 0x61); +dwc_ddrphy_apb_wr(0x410ca, 0x3c0); +dwc_ddrphy_apb_wr(0x410cb, 0x403); +dwc_ddrphy_apb_wr(0x410cc, 0xc000); +dwc_ddrphy_apb_wr(0x410cd, 0x3); +dwc_ddrphy_apb_wr(0x410ce, 0x3c0); +dwc_ddrphy_apb_wr(0x410cf, 0x3); +dwc_ddrphy_apb_wr(0x410d0, 0xc000); +dwc_ddrphy_apb_wr(0x410d1, 0x3); +dwc_ddrphy_apb_wr(0x410d2, 0x3c0); +dwc_ddrphy_apb_wr(0x410d3, 0x2c1); +dwc_ddrphy_apb_wr(0x410d4, 0xc000); +dwc_ddrphy_apb_wr(0x410d5, 0x3); +dwc_ddrphy_apb_wr(0x410d6, 0x3c0); +dwc_ddrphy_apb_wr(0x410d7, 0x1001); +dwc_ddrphy_apb_wr(0x410d8, 0xc5f5); +dwc_ddrphy_apb_wr(0x410d9, 0x61); +dwc_ddrphy_apb_wr(0x410da, 0x3c0); +dwc_ddrphy_apb_wr(0x410db, 0x803); +dwc_ddrphy_apb_wr(0x410dc, 0xc000); +dwc_ddrphy_apb_wr(0x410dd, 0x3); +dwc_ddrphy_apb_wr(0x410de, 0x3c0); +dwc_ddrphy_apb_wr(0x410df, 0x3); +dwc_ddrphy_apb_wr(0x410e0, 0xc000); +dwc_ddrphy_apb_wr(0x410e1, 0x3); +dwc_ddrphy_apb_wr(0x410e2, 0x3c0); +dwc_ddrphy_apb_wr(0x410e3, 0x2c1); +dwc_ddrphy_apb_wr(0x410e4, 0xc000); +dwc_ddrphy_apb_wr(0x410e5, 0x3); +dwc_ddrphy_apb_wr(0x410e6, 0x3c0); +dwc_ddrphy_apb_wr(0x410e7, 0x1d01); +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 2, type = 0 +dwc_ddrphy_apb_wr(0x410e8, 0x213); +dwc_ddrphy_apb_wr(0x410e9, 0x0); +dwc_ddrphy_apb_wr(0x410ea, 0x3c0); +dwc_ddrphy_apb_wr(0x410eb, 0x1); +dwc_ddrphy_apb_wr(0x410ec, 0xc000); +dwc_ddrphy_apb_wr(0x410ed, 0x3); +dwc_ddrphy_apb_wr(0x410ee, 0x3c0); +dwc_ddrphy_apb_wr(0x410ef, 0x0); +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 0 +dwc_ddrphy_apb_wr(0x410f0, 0xc000); +dwc_ddrphy_apb_wr(0x410f1, 0x3); +dwc_ddrphy_apb_wr(0x410f2, 0x3c0); +dwc_ddrphy_apb_wr(0x410f3, 0x2c1); +dwc_ddrphy_apb_wr(0x410f4, 0xc000); +dwc_ddrphy_apb_wr(0x410f5, 0x3); +dwc_ddrphy_apb_wr(0x410f6, 0x3c0); +dwc_ddrphy_apb_wr(0x410f7, 0xef00); +dwc_ddrphy_apb_wr(0x410f8, 0xc000); +dwc_ddrphy_apb_wr(0x410f9, 0x3); +dwc_ddrphy_apb_wr(0x410fa, 0x3c0); +dwc_ddrphy_apb_wr(0x410fb, 0x2c1); +dwc_ddrphy_apb_wr(0x410fc, 0xc000); +dwc_ddrphy_apb_wr(0x410fd, 0x3); +dwc_ddrphy_apb_wr(0x410fe, 0x3c0); +dwc_ddrphy_apb_wr(0x410ff, 0x5900); +dwc_ddrphy_apb_wr(0x41100, 0x217); +dwc_ddrphy_apb_wr(0x41101, 0x1700); +dwc_ddrphy_apb_wr(0x41102, 0x3c2); +dwc_ddrphy_apb_wr(0x41103, 0x1); +dwc_ddrphy_apb_wr(0x41104, 0xc000); +dwc_ddrphy_apb_wr(0x41105, 0x3); +dwc_ddrphy_apb_wr(0x41106, 0x3c0); +dwc_ddrphy_apb_wr(0x41107, 0x0); +dwc_ddrphy_apb_wr(0x41108, 0xc000); +dwc_ddrphy_apb_wr(0x41109, 0x3); +dwc_ddrphy_apb_wr(0x4110a, 0x3c0); +dwc_ddrphy_apb_wr(0x4110b, 0x2c1); +dwc_ddrphy_apb_wr(0x4110c, 0xc000); +dwc_ddrphy_apb_wr(0x4110d, 0x3); +dwc_ddrphy_apb_wr(0x4110e, 0x3c0); +dwc_ddrphy_apb_wr(0x4110f, 0x400); +dwc_ddrphy_apb_wr(0x41110, 0x3fff); +dwc_ddrphy_apb_wr(0x41111, 0xff00); +dwc_ddrphy_apb_wr(0x41112, 0x3f); +dwc_ddrphy_apb_wr(0x41113, 0x2e1); +dwc_ddrphy_apb_wr(0x41114, 0x3fff); +dwc_ddrphy_apb_wr(0x41115, 0xff00); +dwc_ddrphy_apb_wr(0x41116, 0x3f); +dwc_ddrphy_apb_wr(0x41117, 0xa21); +dwc_ddrphy_apb_wr(0x41118, 0x3fff); +dwc_ddrphy_apb_wr(0x41119, 0xff00); +dwc_ddrphy_apb_wr(0x4111a, 0x3f); +dwc_ddrphy_apb_wr(0x4111b, 0x21); +dwc_ddrphy_apb_wr(0x4111c, 0xffff); +dwc_ddrphy_apb_wr(0x4111d, 0xff03); +dwc_ddrphy_apb_wr(0x4111e, 0x3ff); +dwc_ddrphy_apb_wr(0x4111f, 0x20); +dwc_ddrphy_apb_wr(0x41120, 0xffff); +dwc_ddrphy_apb_wr(0x41121, 0xff03); +dwc_ddrphy_apb_wr(0x41122, 0x3ff); +dwc_ddrphy_apb_wr(0x41123, 0x1e1); +dwc_ddrphy_apb_wr(0x41124, 0xffff); +dwc_ddrphy_apb_wr(0x41125, 0xff03); +dwc_ddrphy_apb_wr(0x41126, 0x3ff); +dwc_ddrphy_apb_wr(0x41127, 0x21); +dwc_ddrphy_apb_wr(0x41128, 0xffff); +dwc_ddrphy_apb_wr(0x41129, 0xff03); +dwc_ddrphy_apb_wr(0x4112a, 0x3ff); +dwc_ddrphy_apb_wr(0x4112b, 0x2e1); +dwc_ddrphy_apb_wr(0x4112c, 0xffff); +dwc_ddrphy_apb_wr(0x4112d, 0xff03); +dwc_ddrphy_apb_wr(0x4112e, 0x3ff); +dwc_ddrphy_apb_wr(0x4112f, 0x121); +dwc_ddrphy_apb_wr(0x41130, 0x3fff); +dwc_ddrphy_apb_wr(0x41131, 0xff00); +dwc_ddrphy_apb_wr(0x41132, 0x3ff); +dwc_ddrphy_apb_wr(0x41133, 0x21); +dwc_ddrphy_apb_wr(0x41134, 0x3fff); +dwc_ddrphy_apb_wr(0x41135, 0xff00); +dwc_ddrphy_apb_wr(0x41136, 0x3ff); +dwc_ddrphy_apb_wr(0x41137, 0x21); +dwc_ddrphy_apb_wr(0x41138, 0x3fff); +dwc_ddrphy_apb_wr(0x41139, 0xff00); +dwc_ddrphy_apb_wr(0x4113a, 0x3ff); +dwc_ddrphy_apb_wr(0x4113b, 0x21); +dwc_ddrphy_apb_wr(0x4113c, 0xffff); +dwc_ddrphy_apb_wr(0x4113d, 0xff03); +dwc_ddrphy_apb_wr(0x4113e, 0x3ff); +dwc_ddrphy_apb_wr(0x4113f, 0x21); +dwc_ddrphy_apb_wr(0x41140, 0xffff); +dwc_ddrphy_apb_wr(0x41141, 0xff03); +dwc_ddrphy_apb_wr(0x41142, 0x3ff); +dwc_ddrphy_apb_wr(0x41143, 0x2e1); +dwc_ddrphy_apb_wr(0x41144, 0xffff); +dwc_ddrphy_apb_wr(0x41145, 0xff03); +dwc_ddrphy_apb_wr(0x41146, 0x3ff); +dwc_ddrphy_apb_wr(0x41147, 0xf921); +dwc_ddrphy_apb_wr(0x41148, 0xffff); +dwc_ddrphy_apb_wr(0x41149, 0xff03); +dwc_ddrphy_apb_wr(0x4114a, 0x3ff); +dwc_ddrphy_apb_wr(0x4114b, 0x2e1); +dwc_ddrphy_apb_wr(0x4114c, 0xffff); +dwc_ddrphy_apb_wr(0x4114d, 0xff03); +dwc_ddrphy_apb_wr(0x4114e, 0x3ff); +dwc_ddrphy_apb_wr(0x4114f, 0x5921); +dwc_ddrphy_apb_wr(0x41150, 0x5a5); +dwc_ddrphy_apb_wr(0x41151, 0xa500); +dwc_ddrphy_apb_wr(0x41152, 0x3c5); +dwc_ddrphy_apb_wr(0x41153, 0x21); +dwc_ddrphy_apb_wr(0x41154, 0xc040); +dwc_ddrphy_apb_wr(0x41155, 0x4003); +dwc_ddrphy_apb_wr(0x41156, 0x3c0); +dwc_ddrphy_apb_wr(0x41157, 0x20); +dwc_ddrphy_apb_wr(0x41158, 0xc000); +dwc_ddrphy_apb_wr(0x41159, 0x3); +dwc_ddrphy_apb_wr(0x4115a, 0x3c0); +dwc_ddrphy_apb_wr(0x4115b, 0x2e1); +dwc_ddrphy_apb_wr(0x4115c, 0xc000); +dwc_ddrphy_apb_wr(0x4115d, 0x3); +dwc_ddrphy_apb_wr(0x4115e, 0x3c0); +dwc_ddrphy_apb_wr(0x4115f, 0xa21); +dwc_ddrphy_apb_wr(0x41160, 0xef); +dwc_ddrphy_apb_wr(0x41161, 0xef00); +dwc_ddrphy_apb_wr(0x41162, 0x3c0); +dwc_ddrphy_apb_wr(0x41163, 0x21); +dwc_ddrphy_apb_wr(0x41164, 0xc000); +dwc_ddrphy_apb_wr(0x41165, 0x3); +dwc_ddrphy_apb_wr(0x41166, 0x3c0); +dwc_ddrphy_apb_wr(0x41167, 0x20); +dwc_ddrphy_apb_wr(0x41168, 0xc000); +dwc_ddrphy_apb_wr(0x41169, 0x3); +dwc_ddrphy_apb_wr(0x4116a, 0x3c0); +dwc_ddrphy_apb_wr(0x4116b, 0x2e1); +dwc_ddrphy_apb_wr(0x4116c, 0xc000); +dwc_ddrphy_apb_wr(0x4116d, 0x3); +dwc_ddrphy_apb_wr(0x4116e, 0x3c0); +dwc_ddrphy_apb_wr(0x4116f, 0xff21); +dwc_ddrphy_apb_wr(0x41170, 0xc000); +dwc_ddrphy_apb_wr(0x41171, 0x3); +dwc_ddrphy_apb_wr(0x41172, 0x3c0); +dwc_ddrphy_apb_wr(0x41173, 0x2e1); +dwc_ddrphy_apb_wr(0x41174, 0xc000); +dwc_ddrphy_apb_wr(0x41175, 0x3); +dwc_ddrphy_apb_wr(0x41176, 0x3c0); +dwc_ddrphy_apb_wr(0x41177, 0xff21); +dwc_ddrphy_apb_wr(0x41178, 0xc000); +dwc_ddrphy_apb_wr(0x41179, 0x3); +dwc_ddrphy_apb_wr(0x4117a, 0x3c0); +dwc_ddrphy_apb_wr(0x4117b, 0x2e1); +dwc_ddrphy_apb_wr(0x4117c, 0xc000); +dwc_ddrphy_apb_wr(0x4117d, 0x3); +dwc_ddrphy_apb_wr(0x4117e, 0x3c0); +dwc_ddrphy_apb_wr(0x4117f, 0xa21); +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000000, type = 1 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 0 +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 4, type = 0 +dwc_ddrphy_apb_wr(0x41180, 0x85d5); +dwc_ddrphy_apb_wr(0x41181, 0xd563); +dwc_ddrphy_apb_wr(0x41182, 0x3c5); +dwc_ddrphy_apb_wr(0x41183, 0x420); +dwc_ddrphy_apb_wr(0x41184, 0xc000); +dwc_ddrphy_apb_wr(0x41185, 0x3); +dwc_ddrphy_apb_wr(0x41186, 0x3c0); +dwc_ddrphy_apb_wr(0x41187, 0x20); +dwc_ddrphy_apb_wr(0x41188, 0xc000); +dwc_ddrphy_apb_wr(0x41189, 0x3); +dwc_ddrphy_apb_wr(0x4118a, 0x3c0); +dwc_ddrphy_apb_wr(0x4118b, 0x2c1); +dwc_ddrphy_apb_wr(0x4118c, 0xc000); +dwc_ddrphy_apb_wr(0x4118d, 0x3); +dwc_ddrphy_apb_wr(0x4118e, 0x3c0); +dwc_ddrphy_apb_wr(0x4118f, 0x1001); +dwc_ddrphy_apb_wr(0x41190, 0x85f5); +dwc_ddrphy_apb_wr(0x41191, 0xf563); +dwc_ddrphy_apb_wr(0x41192, 0x3c5); +dwc_ddrphy_apb_wr(0x41193, 0x820); +dwc_ddrphy_apb_wr(0x41194, 0xc000); +dwc_ddrphy_apb_wr(0x41195, 0x3); +dwc_ddrphy_apb_wr(0x41196, 0x3c0); +dwc_ddrphy_apb_wr(0x41197, 0x20); +dwc_ddrphy_apb_wr(0x41198, 0xc000); +dwc_ddrphy_apb_wr(0x41199, 0x3); +dwc_ddrphy_apb_wr(0x4119a, 0x3c0); +dwc_ddrphy_apb_wr(0x4119b, 0x2c1); +dwc_ddrphy_apb_wr(0x4119c, 0xc000); +dwc_ddrphy_apb_wr(0x4119d, 0x3); +dwc_ddrphy_apb_wr(0x4119e, 0x3c0); +dwc_ddrphy_apb_wr(0x4119f, 0x1001); +dwc_ddrphy_apb_wr(0x411a0, 0x45d5); +dwc_ddrphy_apb_wr(0x411a1, 0xd563); +dwc_ddrphy_apb_wr(0x411a2, 0x3c5); +dwc_ddrphy_apb_wr(0x411a3, 0x421); +dwc_ddrphy_apb_wr(0x411a4, 0xc000); +dwc_ddrphy_apb_wr(0x411a5, 0x3); +dwc_ddrphy_apb_wr(0x411a6, 0x3c0); +dwc_ddrphy_apb_wr(0x411a7, 0x21); +dwc_ddrphy_apb_wr(0x411a8, 0xc000); +dwc_ddrphy_apb_wr(0x411a9, 0x3); +dwc_ddrphy_apb_wr(0x411aa, 0x3c0); +dwc_ddrphy_apb_wr(0x411ab, 0x2c1); +dwc_ddrphy_apb_wr(0x411ac, 0xc000); +dwc_ddrphy_apb_wr(0x411ad, 0x3); +dwc_ddrphy_apb_wr(0x411ae, 0x3c0); +dwc_ddrphy_apb_wr(0x411af, 0x1001); +dwc_ddrphy_apb_wr(0x411b0, 0x45f5); +dwc_ddrphy_apb_wr(0x411b1, 0xf563); +dwc_ddrphy_apb_wr(0x411b2, 0x3c5); +dwc_ddrphy_apb_wr(0x411b3, 0x821); +dwc_ddrphy_apb_wr(0x411b4, 0xc000); +dwc_ddrphy_apb_wr(0x411b5, 0x3); +dwc_ddrphy_apb_wr(0x411b6, 0x3c0); +dwc_ddrphy_apb_wr(0x411b7, 0x21); +dwc_ddrphy_apb_wr(0x411b8, 0xc000); +dwc_ddrphy_apb_wr(0x411b9, 0x3); +dwc_ddrphy_apb_wr(0x411ba, 0x3c0); +dwc_ddrphy_apb_wr(0x411bb, 0x2c1); +dwc_ddrphy_apb_wr(0x411bc, 0xc000); +dwc_ddrphy_apb_wr(0x411bd, 0x3); +dwc_ddrphy_apb_wr(0x411be, 0x3c0); +dwc_ddrphy_apb_wr(0x411bf, 0x1001); +dwc_ddrphy_apb_wr(0x411c0, 0xc5d5); +dwc_ddrphy_apb_wr(0x411c1, 0xd562); +dwc_ddrphy_apb_wr(0x411c2, 0x3c5); +dwc_ddrphy_apb_wr(0x411c3, 0x422); +dwc_ddrphy_apb_wr(0x411c4, 0xc000); +dwc_ddrphy_apb_wr(0x411c5, 0x3); +dwc_ddrphy_apb_wr(0x411c6, 0x3c0); +dwc_ddrphy_apb_wr(0x411c7, 0x22); +dwc_ddrphy_apb_wr(0x411c8, 0xc000); +dwc_ddrphy_apb_wr(0x411c9, 0x3); +dwc_ddrphy_apb_wr(0x411ca, 0x3c0); +dwc_ddrphy_apb_wr(0x411cb, 0x2c1); +dwc_ddrphy_apb_wr(0x411cc, 0xc000); +dwc_ddrphy_apb_wr(0x411cd, 0x3); +dwc_ddrphy_apb_wr(0x411ce, 0x3c0); +dwc_ddrphy_apb_wr(0x411cf, 0x1001); +dwc_ddrphy_apb_wr(0x411d0, 0xc5f5); +dwc_ddrphy_apb_wr(0x411d1, 0xf562); +dwc_ddrphy_apb_wr(0x411d2, 0x3c5); +dwc_ddrphy_apb_wr(0x411d3, 0x822); +dwc_ddrphy_apb_wr(0x411d4, 0xc000); +dwc_ddrphy_apb_wr(0x411d5, 0x3); +dwc_ddrphy_apb_wr(0x411d6, 0x3c0); +dwc_ddrphy_apb_wr(0x411d7, 0x22); +dwc_ddrphy_apb_wr(0x411d8, 0xc000); +dwc_ddrphy_apb_wr(0x411d9, 0x3); +dwc_ddrphy_apb_wr(0x411da, 0x3c0); +dwc_ddrphy_apb_wr(0x411db, 0x2c1); +dwc_ddrphy_apb_wr(0x411dc, 0xc000); +dwc_ddrphy_apb_wr(0x411dd, 0x3); +dwc_ddrphy_apb_wr(0x411de, 0x3c0); +dwc_ddrphy_apb_wr(0x411df, 0x1001); +dwc_ddrphy_apb_wr(0x411e0, 0xc5d5); +dwc_ddrphy_apb_wr(0x411e1, 0xd561); +dwc_ddrphy_apb_wr(0x411e2, 0x3c5); +dwc_ddrphy_apb_wr(0x411e3, 0x423); +dwc_ddrphy_apb_wr(0x411e4, 0xc000); +dwc_ddrphy_apb_wr(0x411e5, 0x3); +dwc_ddrphy_apb_wr(0x411e6, 0x3c0); +dwc_ddrphy_apb_wr(0x411e7, 0x23); +dwc_ddrphy_apb_wr(0x411e8, 0xc000); +dwc_ddrphy_apb_wr(0x411e9, 0x3); +dwc_ddrphy_apb_wr(0x411ea, 0x3c0); +dwc_ddrphy_apb_wr(0x411eb, 0x2c1); +dwc_ddrphy_apb_wr(0x411ec, 0xc000); +dwc_ddrphy_apb_wr(0x411ed, 0x3); +dwc_ddrphy_apb_wr(0x411ee, 0x3c0); +dwc_ddrphy_apb_wr(0x411ef, 0x1001); +dwc_ddrphy_apb_wr(0x411f0, 0xc5f5); +dwc_ddrphy_apb_wr(0x411f1, 0xf561); +dwc_ddrphy_apb_wr(0x411f2, 0x3c5); +dwc_ddrphy_apb_wr(0x411f3, 0x823); +dwc_ddrphy_apb_wr(0x411f4, 0xc000); +dwc_ddrphy_apb_wr(0x411f5, 0x3); +dwc_ddrphy_apb_wr(0x411f6, 0x3c0); +dwc_ddrphy_apb_wr(0x411f7, 0x23); +dwc_ddrphy_apb_wr(0x411f8, 0xc000); +dwc_ddrphy_apb_wr(0x411f9, 0x3); +dwc_ddrphy_apb_wr(0x411fa, 0x3c0); +dwc_ddrphy_apb_wr(0x411fb, 0x2c1); +dwc_ddrphy_apb_wr(0x411fc, 0xc000); +dwc_ddrphy_apb_wr(0x411fd, 0x3); +dwc_ddrphy_apb_wr(0x411fe, 0x3c0); +dwc_ddrphy_apb_wr(0x411ff, 0x1d01); +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 2, type = 0 +dwc_ddrphy_apb_wr(0x41200, 0x213); +dwc_ddrphy_apb_wr(0x41201, 0x1300); +dwc_ddrphy_apb_wr(0x41202, 0x3c2); +dwc_ddrphy_apb_wr(0x41203, 0x21); +dwc_ddrphy_apb_wr(0x41204, 0xc000); +dwc_ddrphy_apb_wr(0x41205, 0x3); +dwc_ddrphy_apb_wr(0x41206, 0x3c0); +dwc_ddrphy_apb_wr(0x41207, 0x20); +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 0 +dwc_ddrphy_apb_wr(0x41208, 0xc000); +dwc_ddrphy_apb_wr(0x41209, 0x3); +dwc_ddrphy_apb_wr(0x4120a, 0x3c0); +dwc_ddrphy_apb_wr(0x4120b, 0x2e1); +dwc_ddrphy_apb_wr(0x4120c, 0xc000); +dwc_ddrphy_apb_wr(0x4120d, 0x3); +dwc_ddrphy_apb_wr(0x4120e, 0x3c0); +dwc_ddrphy_apb_wr(0x4120f, 0xef20); +dwc_ddrphy_apb_wr(0x41210, 0xc000); +dwc_ddrphy_apb_wr(0x41211, 0x3); +dwc_ddrphy_apb_wr(0x41212, 0x3c0); +dwc_ddrphy_apb_wr(0x41213, 0x2e1); +dwc_ddrphy_apb_wr(0x41214, 0xc000); +dwc_ddrphy_apb_wr(0x41215, 0x3); +dwc_ddrphy_apb_wr(0x41216, 0x3c0); +dwc_ddrphy_apb_wr(0x41217, 0x5920); +dwc_ddrphy_apb_wr(0x41218, 0x217); +dwc_ddrphy_apb_wr(0x41219, 0x1700); +dwc_ddrphy_apb_wr(0x4121a, 0x3c2); +dwc_ddrphy_apb_wr(0x4121b, 0x21); +dwc_ddrphy_apb_wr(0x4121c, 0xc000); +dwc_ddrphy_apb_wr(0x4121d, 0x3); +dwc_ddrphy_apb_wr(0x4121e, 0x3c0); +dwc_ddrphy_apb_wr(0x4121f, 0x20); +dwc_ddrphy_apb_wr(0x41220, 0xc000); +dwc_ddrphy_apb_wr(0x41221, 0x3); +dwc_ddrphy_apb_wr(0x41222, 0x3c0); +dwc_ddrphy_apb_wr(0x41223, 0x2e1); +dwc_ddrphy_apb_wr(0x41224, 0xc000); +dwc_ddrphy_apb_wr(0x41225, 0x3); +dwc_ddrphy_apb_wr(0x41226, 0x3c0); +dwc_ddrphy_apb_wr(0x41227, 0x420); +//// [phyinit_LoadPIECodeSections] Moving start address from 41228 to 42000 +dwc_ddrphy_apb_wr(0x42000, 0x3fff); +dwc_ddrphy_apb_wr(0x42001, 0xff00); +dwc_ddrphy_apb_wr(0x42002, 0x3f); +dwc_ddrphy_apb_wr(0x42003, 0x2c1); +dwc_ddrphy_apb_wr(0x42004, 0x3fff); +dwc_ddrphy_apb_wr(0x42005, 0xff00); +dwc_ddrphy_apb_wr(0x42006, 0x3f); +dwc_ddrphy_apb_wr(0x42007, 0xa01); +dwc_ddrphy_apb_wr(0x42008, 0x3fff); +dwc_ddrphy_apb_wr(0x42009, 0xff00); +dwc_ddrphy_apb_wr(0x4200a, 0x3f); +dwc_ddrphy_apb_wr(0x4200b, 0x1); +dwc_ddrphy_apb_wr(0x4200c, 0xffff); +dwc_ddrphy_apb_wr(0x4200d, 0xff03); +dwc_ddrphy_apb_wr(0x4200e, 0x3ff); +dwc_ddrphy_apb_wr(0x4200f, 0x0); +dwc_ddrphy_apb_wr(0x42010, 0xffff); +dwc_ddrphy_apb_wr(0x42011, 0xff03); +dwc_ddrphy_apb_wr(0x42012, 0x3ff); +dwc_ddrphy_apb_wr(0x42013, 0x1c1); +dwc_ddrphy_apb_wr(0x42014, 0xffff); +dwc_ddrphy_apb_wr(0x42015, 0xff03); +dwc_ddrphy_apb_wr(0x42016, 0x3ff); +dwc_ddrphy_apb_wr(0x42017, 0x1); +dwc_ddrphy_apb_wr(0x42018, 0xffff); +dwc_ddrphy_apb_wr(0x42019, 0xff03); +dwc_ddrphy_apb_wr(0x4201a, 0x3ff); +dwc_ddrphy_apb_wr(0x4201b, 0x2c1); +dwc_ddrphy_apb_wr(0x4201c, 0xffff); +dwc_ddrphy_apb_wr(0x4201d, 0xff03); +dwc_ddrphy_apb_wr(0x4201e, 0x3ff); +dwc_ddrphy_apb_wr(0x4201f, 0x101); +dwc_ddrphy_apb_wr(0x42020, 0x3fff); +dwc_ddrphy_apb_wr(0x42021, 0xff00); +dwc_ddrphy_apb_wr(0x42022, 0x3f); +dwc_ddrphy_apb_wr(0x42023, 0x1); +dwc_ddrphy_apb_wr(0x42024, 0x3fff); +dwc_ddrphy_apb_wr(0x42025, 0xff00); +dwc_ddrphy_apb_wr(0x42026, 0x3ff); +dwc_ddrphy_apb_wr(0x42027, 0x1); +dwc_ddrphy_apb_wr(0x42028, 0xffff); +dwc_ddrphy_apb_wr(0x42029, 0xff03); +dwc_ddrphy_apb_wr(0x4202a, 0x3ff); +dwc_ddrphy_apb_wr(0x4202b, 0x2c1); +dwc_ddrphy_apb_wr(0x4202c, 0xffff); +dwc_ddrphy_apb_wr(0x4202d, 0xff03); +dwc_ddrphy_apb_wr(0x4202e, 0x3ff); +dwc_ddrphy_apb_wr(0x4202f, 0xf901); +dwc_ddrphy_apb_wr(0x42030, 0xffff); +dwc_ddrphy_apb_wr(0x42031, 0xff03); +dwc_ddrphy_apb_wr(0x42032, 0x3ff); +dwc_ddrphy_apb_wr(0x42033, 0x2c1); +dwc_ddrphy_apb_wr(0x42034, 0xffff); +dwc_ddrphy_apb_wr(0x42035, 0xff03); +dwc_ddrphy_apb_wr(0x42036, 0x3ff); +dwc_ddrphy_apb_wr(0x42037, 0x5901); +dwc_ddrphy_apb_wr(0x42038, 0x5a5); +dwc_ddrphy_apb_wr(0x42039, 0x4000); +dwc_ddrphy_apb_wr(0x4203a, 0x3c0); +dwc_ddrphy_apb_wr(0x4203b, 0x1); +dwc_ddrphy_apb_wr(0x4203c, 0xc000); +dwc_ddrphy_apb_wr(0x4203d, 0x3); +dwc_ddrphy_apb_wr(0x4203e, 0x3c0); +dwc_ddrphy_apb_wr(0x4203f, 0x0); +dwc_ddrphy_apb_wr(0x42040, 0xc000); +dwc_ddrphy_apb_wr(0x42041, 0x3); +dwc_ddrphy_apb_wr(0x42042, 0x3c0); +dwc_ddrphy_apb_wr(0x42043, 0x2c1); +dwc_ddrphy_apb_wr(0x42044, 0xc000); +dwc_ddrphy_apb_wr(0x42045, 0x3); +dwc_ddrphy_apb_wr(0x42046, 0x3c0); +dwc_ddrphy_apb_wr(0x42047, 0xa01); +dwc_ddrphy_apb_wr(0x42048, 0xef); +dwc_ddrphy_apb_wr(0x42049, 0xef00); +dwc_ddrphy_apb_wr(0x4204a, 0x3c0); +dwc_ddrphy_apb_wr(0x4204b, 0x1); +dwc_ddrphy_apb_wr(0x4204c, 0xc000); +dwc_ddrphy_apb_wr(0x4204d, 0x3); +dwc_ddrphy_apb_wr(0x4204e, 0x3c0); +dwc_ddrphy_apb_wr(0x4204f, 0x0); +dwc_ddrphy_apb_wr(0x42050, 0xc000); +dwc_ddrphy_apb_wr(0x42051, 0x3); +dwc_ddrphy_apb_wr(0x42052, 0x3c0); +dwc_ddrphy_apb_wr(0x42053, 0x2c1); +dwc_ddrphy_apb_wr(0x42054, 0xc000); +dwc_ddrphy_apb_wr(0x42055, 0x3); +dwc_ddrphy_apb_wr(0x42056, 0x3c0); +dwc_ddrphy_apb_wr(0x42057, 0xff01); +dwc_ddrphy_apb_wr(0x42058, 0xc000); +dwc_ddrphy_apb_wr(0x42059, 0x3); +dwc_ddrphy_apb_wr(0x4205a, 0x3c0); +dwc_ddrphy_apb_wr(0x4205b, 0x2c1); +dwc_ddrphy_apb_wr(0x4205c, 0xc000); +dwc_ddrphy_apb_wr(0x4205d, 0x3); +dwc_ddrphy_apb_wr(0x4205e, 0x3c0); +dwc_ddrphy_apb_wr(0x4205f, 0xff01); +dwc_ddrphy_apb_wr(0x42060, 0xc000); +dwc_ddrphy_apb_wr(0x42061, 0x3); +dwc_ddrphy_apb_wr(0x42062, 0x3c0); +dwc_ddrphy_apb_wr(0x42063, 0x2c1); +dwc_ddrphy_apb_wr(0x42064, 0xc000); +dwc_ddrphy_apb_wr(0x42065, 0x3); +dwc_ddrphy_apb_wr(0x42066, 0x3c0); +dwc_ddrphy_apb_wr(0x42067, 0xa01); +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 0 +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 4, type = 0 +dwc_ddrphy_apb_wr(0x42068, 0x85d5); +dwc_ddrphy_apb_wr(0x42069, 0x63); +dwc_ddrphy_apb_wr(0x4206a, 0x3c0); +dwc_ddrphy_apb_wr(0x4206b, 0x400); +dwc_ddrphy_apb_wr(0x4206c, 0xc000); +dwc_ddrphy_apb_wr(0x4206d, 0x3); +dwc_ddrphy_apb_wr(0x4206e, 0x3c0); +dwc_ddrphy_apb_wr(0x4206f, 0x0); +dwc_ddrphy_apb_wr(0x42070, 0xc000); +dwc_ddrphy_apb_wr(0x42071, 0x3); +dwc_ddrphy_apb_wr(0x42072, 0x3c0); +dwc_ddrphy_apb_wr(0x42073, 0x2c1); +dwc_ddrphy_apb_wr(0x42074, 0xc000); +dwc_ddrphy_apb_wr(0x42075, 0x3); +dwc_ddrphy_apb_wr(0x42076, 0x3c0); +dwc_ddrphy_apb_wr(0x42077, 0x1001); +dwc_ddrphy_apb_wr(0x42078, 0x85f5); +dwc_ddrphy_apb_wr(0x42079, 0x63); +dwc_ddrphy_apb_wr(0x4207a, 0x3c0); +dwc_ddrphy_apb_wr(0x4207b, 0x800); +dwc_ddrphy_apb_wr(0x4207c, 0xc000); +dwc_ddrphy_apb_wr(0x4207d, 0x3); +dwc_ddrphy_apb_wr(0x4207e, 0x3c0); +dwc_ddrphy_apb_wr(0x4207f, 0x0); +dwc_ddrphy_apb_wr(0x42080, 0xc000); +dwc_ddrphy_apb_wr(0x42081, 0x3); +dwc_ddrphy_apb_wr(0x42082, 0x3c0); +dwc_ddrphy_apb_wr(0x42083, 0x2c1); +dwc_ddrphy_apb_wr(0x42084, 0xc000); +dwc_ddrphy_apb_wr(0x42085, 0x3); +dwc_ddrphy_apb_wr(0x42086, 0x3c0); +dwc_ddrphy_apb_wr(0x42087, 0x1001); +dwc_ddrphy_apb_wr(0x42088, 0x45d5); +dwc_ddrphy_apb_wr(0x42089, 0x63); +dwc_ddrphy_apb_wr(0x4208a, 0x3c0); +dwc_ddrphy_apb_wr(0x4208b, 0x401); +dwc_ddrphy_apb_wr(0x4208c, 0xc000); +dwc_ddrphy_apb_wr(0x4208d, 0x3); +dwc_ddrphy_apb_wr(0x4208e, 0x3c0); +dwc_ddrphy_apb_wr(0x4208f, 0x1); +dwc_ddrphy_apb_wr(0x42090, 0xc000); +dwc_ddrphy_apb_wr(0x42091, 0x3); +dwc_ddrphy_apb_wr(0x42092, 0x3c0); +dwc_ddrphy_apb_wr(0x42093, 0x2c1); +dwc_ddrphy_apb_wr(0x42094, 0xc000); +dwc_ddrphy_apb_wr(0x42095, 0x3); +dwc_ddrphy_apb_wr(0x42096, 0x3c0); +dwc_ddrphy_apb_wr(0x42097, 0x1001); +dwc_ddrphy_apb_wr(0x42098, 0x45f5); +dwc_ddrphy_apb_wr(0x42099, 0x63); +dwc_ddrphy_apb_wr(0x4209a, 0x3c0); +dwc_ddrphy_apb_wr(0x4209b, 0x801); +dwc_ddrphy_apb_wr(0x4209c, 0xc000); +dwc_ddrphy_apb_wr(0x4209d, 0x3); +dwc_ddrphy_apb_wr(0x4209e, 0x3c0); +dwc_ddrphy_apb_wr(0x4209f, 0x1); +dwc_ddrphy_apb_wr(0x420a0, 0xc000); +dwc_ddrphy_apb_wr(0x420a1, 0x3); +dwc_ddrphy_apb_wr(0x420a2, 0x3c0); +dwc_ddrphy_apb_wr(0x420a3, 0x2c1); +dwc_ddrphy_apb_wr(0x420a4, 0xc000); +dwc_ddrphy_apb_wr(0x420a5, 0x3); +dwc_ddrphy_apb_wr(0x420a6, 0x3c0); +dwc_ddrphy_apb_wr(0x420a7, 0x1001); +dwc_ddrphy_apb_wr(0x420a8, 0xc5d5); +dwc_ddrphy_apb_wr(0x420a9, 0x62); +dwc_ddrphy_apb_wr(0x420aa, 0x3c0); +dwc_ddrphy_apb_wr(0x420ab, 0x402); +dwc_ddrphy_apb_wr(0x420ac, 0xc000); +dwc_ddrphy_apb_wr(0x420ad, 0x3); +dwc_ddrphy_apb_wr(0x420ae, 0x3c0); +dwc_ddrphy_apb_wr(0x420af, 0x2); +dwc_ddrphy_apb_wr(0x420b0, 0xc000); +dwc_ddrphy_apb_wr(0x420b1, 0x3); +dwc_ddrphy_apb_wr(0x420b2, 0x3c0); +dwc_ddrphy_apb_wr(0x420b3, 0x2c1); +dwc_ddrphy_apb_wr(0x420b4, 0xc000); +dwc_ddrphy_apb_wr(0x420b5, 0x3); +dwc_ddrphy_apb_wr(0x420b6, 0x3c0); +dwc_ddrphy_apb_wr(0x420b7, 0x1001); +dwc_ddrphy_apb_wr(0x420b8, 0xc5f5); +dwc_ddrphy_apb_wr(0x420b9, 0x62); +dwc_ddrphy_apb_wr(0x420ba, 0x3c0); +dwc_ddrphy_apb_wr(0x420bb, 0x802); +dwc_ddrphy_apb_wr(0x420bc, 0xc000); +dwc_ddrphy_apb_wr(0x420bd, 0x3); +dwc_ddrphy_apb_wr(0x420be, 0x3c0); +dwc_ddrphy_apb_wr(0x420bf, 0x2); +dwc_ddrphy_apb_wr(0x420c0, 0xc000); +dwc_ddrphy_apb_wr(0x420c1, 0x3); +dwc_ddrphy_apb_wr(0x420c2, 0x3c0); +dwc_ddrphy_apb_wr(0x420c3, 0x2c1); +dwc_ddrphy_apb_wr(0x420c4, 0xc000); +dwc_ddrphy_apb_wr(0x420c5, 0x3); +dwc_ddrphy_apb_wr(0x420c6, 0x3c0); +dwc_ddrphy_apb_wr(0x420c7, 0x1001); +dwc_ddrphy_apb_wr(0x420c8, 0xc5d5); +dwc_ddrphy_apb_wr(0x420c9, 0x61); +dwc_ddrphy_apb_wr(0x420ca, 0x3c0); +dwc_ddrphy_apb_wr(0x420cb, 0x403); +dwc_ddrphy_apb_wr(0x420cc, 0xc000); +dwc_ddrphy_apb_wr(0x420cd, 0x3); +dwc_ddrphy_apb_wr(0x420ce, 0x3c0); +dwc_ddrphy_apb_wr(0x420cf, 0x3); +dwc_ddrphy_apb_wr(0x420d0, 0xc000); +dwc_ddrphy_apb_wr(0x420d1, 0x3); +dwc_ddrphy_apb_wr(0x420d2, 0x3c0); +dwc_ddrphy_apb_wr(0x420d3, 0x2c1); +dwc_ddrphy_apb_wr(0x420d4, 0xc000); +dwc_ddrphy_apb_wr(0x420d5, 0x3); +dwc_ddrphy_apb_wr(0x420d6, 0x3c0); +dwc_ddrphy_apb_wr(0x420d7, 0x1001); +dwc_ddrphy_apb_wr(0x420d8, 0xc5f5); +dwc_ddrphy_apb_wr(0x420d9, 0x61); +dwc_ddrphy_apb_wr(0x420da, 0x3c0); +dwc_ddrphy_apb_wr(0x420db, 0x803); +dwc_ddrphy_apb_wr(0x420dc, 0xc000); +dwc_ddrphy_apb_wr(0x420dd, 0x3); +dwc_ddrphy_apb_wr(0x420de, 0x3c0); +dwc_ddrphy_apb_wr(0x420df, 0x3); +dwc_ddrphy_apb_wr(0x420e0, 0xc000); +dwc_ddrphy_apb_wr(0x420e1, 0x3); +dwc_ddrphy_apb_wr(0x420e2, 0x3c0); +dwc_ddrphy_apb_wr(0x420e3, 0x2c1); +dwc_ddrphy_apb_wr(0x420e4, 0xc000); +dwc_ddrphy_apb_wr(0x420e5, 0x3); +dwc_ddrphy_apb_wr(0x420e6, 0x3c0); +dwc_ddrphy_apb_wr(0x420e7, 0x1d01); +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 2, type = 0 +dwc_ddrphy_apb_wr(0x420e8, 0x213); +dwc_ddrphy_apb_wr(0x420e9, 0x0); +dwc_ddrphy_apb_wr(0x420ea, 0x3c0); +dwc_ddrphy_apb_wr(0x420eb, 0x1); +dwc_ddrphy_apb_wr(0x420ec, 0xc000); +dwc_ddrphy_apb_wr(0x420ed, 0x3); +dwc_ddrphy_apb_wr(0x420ee, 0x3c0); +dwc_ddrphy_apb_wr(0x420ef, 0x0); +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 0 +dwc_ddrphy_apb_wr(0x420f0, 0xc000); +dwc_ddrphy_apb_wr(0x420f1, 0x3); +dwc_ddrphy_apb_wr(0x420f2, 0x3c0); +dwc_ddrphy_apb_wr(0x420f3, 0x2c1); +dwc_ddrphy_apb_wr(0x420f4, 0xc000); +dwc_ddrphy_apb_wr(0x420f5, 0x3); +dwc_ddrphy_apb_wr(0x420f6, 0x3c0); +dwc_ddrphy_apb_wr(0x420f7, 0xef00); +dwc_ddrphy_apb_wr(0x420f8, 0xc000); +dwc_ddrphy_apb_wr(0x420f9, 0x3); +dwc_ddrphy_apb_wr(0x420fa, 0x3c0); +dwc_ddrphy_apb_wr(0x420fb, 0x2c1); +dwc_ddrphy_apb_wr(0x420fc, 0xc000); +dwc_ddrphy_apb_wr(0x420fd, 0x3); +dwc_ddrphy_apb_wr(0x420fe, 0x3c0); +dwc_ddrphy_apb_wr(0x420ff, 0x5900); +dwc_ddrphy_apb_wr(0x42100, 0x217); +dwc_ddrphy_apb_wr(0x42101, 0x1700); +dwc_ddrphy_apb_wr(0x42102, 0x3c2); +dwc_ddrphy_apb_wr(0x42103, 0x1); +dwc_ddrphy_apb_wr(0x42104, 0xc000); +dwc_ddrphy_apb_wr(0x42105, 0x3); +dwc_ddrphy_apb_wr(0x42106, 0x3c0); +dwc_ddrphy_apb_wr(0x42107, 0x0); +dwc_ddrphy_apb_wr(0x42108, 0xc000); +dwc_ddrphy_apb_wr(0x42109, 0x3); +dwc_ddrphy_apb_wr(0x4210a, 0x3c0); +dwc_ddrphy_apb_wr(0x4210b, 0x2c1); +dwc_ddrphy_apb_wr(0x4210c, 0xc000); +dwc_ddrphy_apb_wr(0x4210d, 0x3); +dwc_ddrphy_apb_wr(0x4210e, 0x3c0); +dwc_ddrphy_apb_wr(0x4210f, 0x400); +dwc_ddrphy_apb_wr(0x42110, 0x3fff); +dwc_ddrphy_apb_wr(0x42111, 0xff00); +dwc_ddrphy_apb_wr(0x42112, 0x3f); +dwc_ddrphy_apb_wr(0x42113, 0x2e1); +dwc_ddrphy_apb_wr(0x42114, 0x3fff); +dwc_ddrphy_apb_wr(0x42115, 0xff00); +dwc_ddrphy_apb_wr(0x42116, 0x3f); +dwc_ddrphy_apb_wr(0x42117, 0xa21); +dwc_ddrphy_apb_wr(0x42118, 0x3fff); +dwc_ddrphy_apb_wr(0x42119, 0xff00); +dwc_ddrphy_apb_wr(0x4211a, 0x3f); +dwc_ddrphy_apb_wr(0x4211b, 0x21); +dwc_ddrphy_apb_wr(0x4211c, 0xffff); +dwc_ddrphy_apb_wr(0x4211d, 0xff03); +dwc_ddrphy_apb_wr(0x4211e, 0x3ff); +dwc_ddrphy_apb_wr(0x4211f, 0x20); +dwc_ddrphy_apb_wr(0x42120, 0xffff); +dwc_ddrphy_apb_wr(0x42121, 0xff03); +dwc_ddrphy_apb_wr(0x42122, 0x3ff); +dwc_ddrphy_apb_wr(0x42123, 0x1e1); +dwc_ddrphy_apb_wr(0x42124, 0xffff); +dwc_ddrphy_apb_wr(0x42125, 0xff03); +dwc_ddrphy_apb_wr(0x42126, 0x3ff); +dwc_ddrphy_apb_wr(0x42127, 0x21); +dwc_ddrphy_apb_wr(0x42128, 0xffff); +dwc_ddrphy_apb_wr(0x42129, 0xff03); +dwc_ddrphy_apb_wr(0x4212a, 0x3ff); +dwc_ddrphy_apb_wr(0x4212b, 0x2e1); +dwc_ddrphy_apb_wr(0x4212c, 0xffff); +dwc_ddrphy_apb_wr(0x4212d, 0xff03); +dwc_ddrphy_apb_wr(0x4212e, 0x3ff); +dwc_ddrphy_apb_wr(0x4212f, 0x121); +dwc_ddrphy_apb_wr(0x42130, 0x3fff); +dwc_ddrphy_apb_wr(0x42131, 0xff00); +dwc_ddrphy_apb_wr(0x42132, 0x3ff); +dwc_ddrphy_apb_wr(0x42133, 0x21); +dwc_ddrphy_apb_wr(0x42134, 0x3fff); +dwc_ddrphy_apb_wr(0x42135, 0xff00); +dwc_ddrphy_apb_wr(0x42136, 0x3ff); +dwc_ddrphy_apb_wr(0x42137, 0x21); +dwc_ddrphy_apb_wr(0x42138, 0x3fff); +dwc_ddrphy_apb_wr(0x42139, 0xff00); +dwc_ddrphy_apb_wr(0x4213a, 0x3ff); +dwc_ddrphy_apb_wr(0x4213b, 0x21); +dwc_ddrphy_apb_wr(0x4213c, 0xffff); +dwc_ddrphy_apb_wr(0x4213d, 0xff03); +dwc_ddrphy_apb_wr(0x4213e, 0x3ff); +dwc_ddrphy_apb_wr(0x4213f, 0x21); +dwc_ddrphy_apb_wr(0x42140, 0xffff); +dwc_ddrphy_apb_wr(0x42141, 0xff03); +dwc_ddrphy_apb_wr(0x42142, 0x3ff); +dwc_ddrphy_apb_wr(0x42143, 0x2e1); +dwc_ddrphy_apb_wr(0x42144, 0xffff); +dwc_ddrphy_apb_wr(0x42145, 0xff03); +dwc_ddrphy_apb_wr(0x42146, 0x3ff); +dwc_ddrphy_apb_wr(0x42147, 0xf921); +dwc_ddrphy_apb_wr(0x42148, 0xffff); +dwc_ddrphy_apb_wr(0x42149, 0xff03); +dwc_ddrphy_apb_wr(0x4214a, 0x3ff); +dwc_ddrphy_apb_wr(0x4214b, 0x2e1); +dwc_ddrphy_apb_wr(0x4214c, 0xffff); +dwc_ddrphy_apb_wr(0x4214d, 0xff03); +dwc_ddrphy_apb_wr(0x4214e, 0x3ff); +dwc_ddrphy_apb_wr(0x4214f, 0x5921); +dwc_ddrphy_apb_wr(0x42150, 0x5a5); +dwc_ddrphy_apb_wr(0x42151, 0xa500); +dwc_ddrphy_apb_wr(0x42152, 0x3c5); +dwc_ddrphy_apb_wr(0x42153, 0x21); +dwc_ddrphy_apb_wr(0x42154, 0xc040); +dwc_ddrphy_apb_wr(0x42155, 0x4003); +dwc_ddrphy_apb_wr(0x42156, 0x3c0); +dwc_ddrphy_apb_wr(0x42157, 0x20); +dwc_ddrphy_apb_wr(0x42158, 0xc000); +dwc_ddrphy_apb_wr(0x42159, 0x3); +dwc_ddrphy_apb_wr(0x4215a, 0x3c0); +dwc_ddrphy_apb_wr(0x4215b, 0x2e1); +dwc_ddrphy_apb_wr(0x4215c, 0xc000); +dwc_ddrphy_apb_wr(0x4215d, 0x3); +dwc_ddrphy_apb_wr(0x4215e, 0x3c0); +dwc_ddrphy_apb_wr(0x4215f, 0xa21); +dwc_ddrphy_apb_wr(0x42160, 0xef); +dwc_ddrphy_apb_wr(0x42161, 0xef00); +dwc_ddrphy_apb_wr(0x42162, 0x3c0); +dwc_ddrphy_apb_wr(0x42163, 0x21); +dwc_ddrphy_apb_wr(0x42164, 0xc000); +dwc_ddrphy_apb_wr(0x42165, 0x3); +dwc_ddrphy_apb_wr(0x42166, 0x3c0); +dwc_ddrphy_apb_wr(0x42167, 0x20); +dwc_ddrphy_apb_wr(0x42168, 0xc000); +dwc_ddrphy_apb_wr(0x42169, 0x3); +dwc_ddrphy_apb_wr(0x4216a, 0x3c0); +dwc_ddrphy_apb_wr(0x4216b, 0x2e1); +dwc_ddrphy_apb_wr(0x4216c, 0xc000); +dwc_ddrphy_apb_wr(0x4216d, 0x3); +dwc_ddrphy_apb_wr(0x4216e, 0x3c0); +dwc_ddrphy_apb_wr(0x4216f, 0xff21); +dwc_ddrphy_apb_wr(0x42170, 0xc000); +dwc_ddrphy_apb_wr(0x42171, 0x3); +dwc_ddrphy_apb_wr(0x42172, 0x3c0); +dwc_ddrphy_apb_wr(0x42173, 0x2e1); +dwc_ddrphy_apb_wr(0x42174, 0xc000); +dwc_ddrphy_apb_wr(0x42175, 0x3); +dwc_ddrphy_apb_wr(0x42176, 0x3c0); +dwc_ddrphy_apb_wr(0x42177, 0xff21); +dwc_ddrphy_apb_wr(0x42178, 0xc000); +dwc_ddrphy_apb_wr(0x42179, 0x3); +dwc_ddrphy_apb_wr(0x4217a, 0x3c0); +dwc_ddrphy_apb_wr(0x4217b, 0x2e1); +dwc_ddrphy_apb_wr(0x4217c, 0xc000); +dwc_ddrphy_apb_wr(0x4217d, 0x3); +dwc_ddrphy_apb_wr(0x4217e, 0x3c0); +dwc_ddrphy_apb_wr(0x4217f, 0xa21); +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000000, type = 2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 0 +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 4, type = 0 +dwc_ddrphy_apb_wr(0x42180, 0x85d5); +dwc_ddrphy_apb_wr(0x42181, 0xd563); +dwc_ddrphy_apb_wr(0x42182, 0x3c5); +dwc_ddrphy_apb_wr(0x42183, 0x420); +dwc_ddrphy_apb_wr(0x42184, 0xc000); +dwc_ddrphy_apb_wr(0x42185, 0x3); +dwc_ddrphy_apb_wr(0x42186, 0x3c0); +dwc_ddrphy_apb_wr(0x42187, 0x20); +dwc_ddrphy_apb_wr(0x42188, 0xc000); +dwc_ddrphy_apb_wr(0x42189, 0x3); +dwc_ddrphy_apb_wr(0x4218a, 0x3c0); +dwc_ddrphy_apb_wr(0x4218b, 0x2c1); +dwc_ddrphy_apb_wr(0x4218c, 0xc000); +dwc_ddrphy_apb_wr(0x4218d, 0x3); +dwc_ddrphy_apb_wr(0x4218e, 0x3c0); +dwc_ddrphy_apb_wr(0x4218f, 0x1001); +dwc_ddrphy_apb_wr(0x42190, 0x85f5); +dwc_ddrphy_apb_wr(0x42191, 0xf563); +dwc_ddrphy_apb_wr(0x42192, 0x3c5); +dwc_ddrphy_apb_wr(0x42193, 0x820); +dwc_ddrphy_apb_wr(0x42194, 0xc000); +dwc_ddrphy_apb_wr(0x42195, 0x3); +dwc_ddrphy_apb_wr(0x42196, 0x3c0); +dwc_ddrphy_apb_wr(0x42197, 0x20); +dwc_ddrphy_apb_wr(0x42198, 0xc000); +dwc_ddrphy_apb_wr(0x42199, 0x3); +dwc_ddrphy_apb_wr(0x4219a, 0x3c0); +dwc_ddrphy_apb_wr(0x4219b, 0x2c1); +dwc_ddrphy_apb_wr(0x4219c, 0xc000); +dwc_ddrphy_apb_wr(0x4219d, 0x3); +dwc_ddrphy_apb_wr(0x4219e, 0x3c0); +dwc_ddrphy_apb_wr(0x4219f, 0x1001); +dwc_ddrphy_apb_wr(0x421a0, 0x45d5); +dwc_ddrphy_apb_wr(0x421a1, 0xd563); +dwc_ddrphy_apb_wr(0x421a2, 0x3c5); +dwc_ddrphy_apb_wr(0x421a3, 0x421); +dwc_ddrphy_apb_wr(0x421a4, 0xc000); +dwc_ddrphy_apb_wr(0x421a5, 0x3); +dwc_ddrphy_apb_wr(0x421a6, 0x3c0); +dwc_ddrphy_apb_wr(0x421a7, 0x21); +dwc_ddrphy_apb_wr(0x421a8, 0xc000); +dwc_ddrphy_apb_wr(0x421a9, 0x3); +dwc_ddrphy_apb_wr(0x421aa, 0x3c0); +dwc_ddrphy_apb_wr(0x421ab, 0x2c1); +dwc_ddrphy_apb_wr(0x421ac, 0xc000); +dwc_ddrphy_apb_wr(0x421ad, 0x3); +dwc_ddrphy_apb_wr(0x421ae, 0x3c0); +dwc_ddrphy_apb_wr(0x421af, 0x1001); +dwc_ddrphy_apb_wr(0x421b0, 0x45f5); +dwc_ddrphy_apb_wr(0x421b1, 0xf563); +dwc_ddrphy_apb_wr(0x421b2, 0x3c5); +dwc_ddrphy_apb_wr(0x421b3, 0x821); +dwc_ddrphy_apb_wr(0x421b4, 0xc000); +dwc_ddrphy_apb_wr(0x421b5, 0x3); +dwc_ddrphy_apb_wr(0x421b6, 0x3c0); +dwc_ddrphy_apb_wr(0x421b7, 0x21); +dwc_ddrphy_apb_wr(0x421b8, 0xc000); +dwc_ddrphy_apb_wr(0x421b9, 0x3); +dwc_ddrphy_apb_wr(0x421ba, 0x3c0); +dwc_ddrphy_apb_wr(0x421bb, 0x2c1); +dwc_ddrphy_apb_wr(0x421bc, 0xc000); +dwc_ddrphy_apb_wr(0x421bd, 0x3); +dwc_ddrphy_apb_wr(0x421be, 0x3c0); +dwc_ddrphy_apb_wr(0x421bf, 0x1001); +dwc_ddrphy_apb_wr(0x421c0, 0xc5d5); +dwc_ddrphy_apb_wr(0x421c1, 0xd562); +dwc_ddrphy_apb_wr(0x421c2, 0x3c5); +dwc_ddrphy_apb_wr(0x421c3, 0x422); +dwc_ddrphy_apb_wr(0x421c4, 0xc000); +dwc_ddrphy_apb_wr(0x421c5, 0x3); +dwc_ddrphy_apb_wr(0x421c6, 0x3c0); +dwc_ddrphy_apb_wr(0x421c7, 0x22); +dwc_ddrphy_apb_wr(0x421c8, 0xc000); +dwc_ddrphy_apb_wr(0x421c9, 0x3); +dwc_ddrphy_apb_wr(0x421ca, 0x3c0); +dwc_ddrphy_apb_wr(0x421cb, 0x2c1); +dwc_ddrphy_apb_wr(0x421cc, 0xc000); +dwc_ddrphy_apb_wr(0x421cd, 0x3); +dwc_ddrphy_apb_wr(0x421ce, 0x3c0); +dwc_ddrphy_apb_wr(0x421cf, 0x1001); +dwc_ddrphy_apb_wr(0x421d0, 0xc5f5); +dwc_ddrphy_apb_wr(0x421d1, 0xf562); +dwc_ddrphy_apb_wr(0x421d2, 0x3c5); +dwc_ddrphy_apb_wr(0x421d3, 0x822); +dwc_ddrphy_apb_wr(0x421d4, 0xc000); +dwc_ddrphy_apb_wr(0x421d5, 0x3); +dwc_ddrphy_apb_wr(0x421d6, 0x3c0); +dwc_ddrphy_apb_wr(0x421d7, 0x22); +dwc_ddrphy_apb_wr(0x421d8, 0xc000); +dwc_ddrphy_apb_wr(0x421d9, 0x3); +dwc_ddrphy_apb_wr(0x421da, 0x3c0); +dwc_ddrphy_apb_wr(0x421db, 0x2c1); +dwc_ddrphy_apb_wr(0x421dc, 0xc000); +dwc_ddrphy_apb_wr(0x421dd, 0x3); +dwc_ddrphy_apb_wr(0x421de, 0x3c0); +dwc_ddrphy_apb_wr(0x421df, 0x1001); +dwc_ddrphy_apb_wr(0x421e0, 0xc5d5); +dwc_ddrphy_apb_wr(0x421e1, 0xd561); +dwc_ddrphy_apb_wr(0x421e2, 0x3c5); +dwc_ddrphy_apb_wr(0x421e3, 0x423); +dwc_ddrphy_apb_wr(0x421e4, 0xc000); +dwc_ddrphy_apb_wr(0x421e5, 0x3); +dwc_ddrphy_apb_wr(0x421e6, 0x3c0); +dwc_ddrphy_apb_wr(0x421e7, 0x23); +dwc_ddrphy_apb_wr(0x421e8, 0xc000); +dwc_ddrphy_apb_wr(0x421e9, 0x3); +dwc_ddrphy_apb_wr(0x421ea, 0x3c0); +dwc_ddrphy_apb_wr(0x421eb, 0x2c1); +dwc_ddrphy_apb_wr(0x421ec, 0xc000); +dwc_ddrphy_apb_wr(0x421ed, 0x3); +dwc_ddrphy_apb_wr(0x421ee, 0x3c0); +dwc_ddrphy_apb_wr(0x421ef, 0x1001); +dwc_ddrphy_apb_wr(0x421f0, 0xc5f5); +dwc_ddrphy_apb_wr(0x421f1, 0xf561); +dwc_ddrphy_apb_wr(0x421f2, 0x3c5); +dwc_ddrphy_apb_wr(0x421f3, 0x823); +dwc_ddrphy_apb_wr(0x421f4, 0xc000); +dwc_ddrphy_apb_wr(0x421f5, 0x3); +dwc_ddrphy_apb_wr(0x421f6, 0x3c0); +dwc_ddrphy_apb_wr(0x421f7, 0x23); +dwc_ddrphy_apb_wr(0x421f8, 0xc000); +dwc_ddrphy_apb_wr(0x421f9, 0x3); +dwc_ddrphy_apb_wr(0x421fa, 0x3c0); +dwc_ddrphy_apb_wr(0x421fb, 0x2c1); +dwc_ddrphy_apb_wr(0x421fc, 0xc000); +dwc_ddrphy_apb_wr(0x421fd, 0x3); +dwc_ddrphy_apb_wr(0x421fe, 0x3c0); +dwc_ddrphy_apb_wr(0x421ff, 0x1d01); +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 2, type = 0 +dwc_ddrphy_apb_wr(0x42200, 0x213); +dwc_ddrphy_apb_wr(0x42201, 0x1300); +dwc_ddrphy_apb_wr(0x42202, 0x3c2); +dwc_ddrphy_apb_wr(0x42203, 0x21); +dwc_ddrphy_apb_wr(0x42204, 0xc000); +dwc_ddrphy_apb_wr(0x42205, 0x3); +dwc_ddrphy_apb_wr(0x42206, 0x3c0); +dwc_ddrphy_apb_wr(0x42207, 0x20); +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 0 +dwc_ddrphy_apb_wr(0x42208, 0xc000); +dwc_ddrphy_apb_wr(0x42209, 0x3); +dwc_ddrphy_apb_wr(0x4220a, 0x3c0); +dwc_ddrphy_apb_wr(0x4220b, 0x2e1); +dwc_ddrphy_apb_wr(0x4220c, 0xc000); +dwc_ddrphy_apb_wr(0x4220d, 0x3); +dwc_ddrphy_apb_wr(0x4220e, 0x3c0); +dwc_ddrphy_apb_wr(0x4220f, 0xef20); +dwc_ddrphy_apb_wr(0x42210, 0xc000); +dwc_ddrphy_apb_wr(0x42211, 0x3); +dwc_ddrphy_apb_wr(0x42212, 0x3c0); +dwc_ddrphy_apb_wr(0x42213, 0x2e1); +dwc_ddrphy_apb_wr(0x42214, 0xc000); +dwc_ddrphy_apb_wr(0x42215, 0x3); +dwc_ddrphy_apb_wr(0x42216, 0x3c0); +dwc_ddrphy_apb_wr(0x42217, 0x5920); +dwc_ddrphy_apb_wr(0x42218, 0x217); +dwc_ddrphy_apb_wr(0x42219, 0x1700); +dwc_ddrphy_apb_wr(0x4221a, 0x3c2); +dwc_ddrphy_apb_wr(0x4221b, 0x21); +dwc_ddrphy_apb_wr(0x4221c, 0xc000); +dwc_ddrphy_apb_wr(0x4221d, 0x3); +dwc_ddrphy_apb_wr(0x4221e, 0x3c0); +dwc_ddrphy_apb_wr(0x4221f, 0x20); +dwc_ddrphy_apb_wr(0x42220, 0xc000); +dwc_ddrphy_apb_wr(0x42221, 0x3); +dwc_ddrphy_apb_wr(0x42222, 0x3c0); +dwc_ddrphy_apb_wr(0x42223, 0x2e1); +dwc_ddrphy_apb_wr(0x42224, 0xc000); +dwc_ddrphy_apb_wr(0x42225, 0x3); +dwc_ddrphy_apb_wr(0x42226, 0x3c0); +dwc_ddrphy_apb_wr(0x42227, 0x420); +//// [phyinit_LoadPIECodeSections] Moving start address from 42228 to 90029 +dwc_ddrphy_apb_wr(0x90029, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s0 +dwc_ddrphy_apb_wr(0x9002a, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s1 +dwc_ddrphy_apb_wr(0x9002b, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s2 +dwc_ddrphy_apb_wr(0x9002c, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s0 +dwc_ddrphy_apb_wr(0x9002d, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s1 +dwc_ddrphy_apb_wr(0x9002e, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s2 +dwc_ddrphy_apb_wr(0x9002f, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s0 +dwc_ddrphy_apb_wr(0x90030, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s1 +dwc_ddrphy_apb_wr(0x90031, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s2 +dwc_ddrphy_apb_wr(0x90032, 0xb); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s0 +dwc_ddrphy_apb_wr(0x90033, 0x480); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s1 +dwc_ddrphy_apb_wr(0x90034, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s2 +dwc_ddrphy_apb_wr(0x90035, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s0 +dwc_ddrphy_apb_wr(0x90036, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s1 +dwc_ddrphy_apb_wr(0x90037, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s2 +dwc_ddrphy_apb_wr(0x90038, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s0 +dwc_ddrphy_apb_wr(0x90039, 0x478); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s1 +dwc_ddrphy_apb_wr(0x9003a, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s2 +dwc_ddrphy_apb_wr(0x9003b, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s0 +dwc_ddrphy_apb_wr(0x9003c, 0xe8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s1 +dwc_ddrphy_apb_wr(0x9003d, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s2 +dwc_ddrphy_apb_wr(0x9003e, 0x2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s0 +dwc_ddrphy_apb_wr(0x9003f, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s1 +dwc_ddrphy_apb_wr(0x90040, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s2 +dwc_ddrphy_apb_wr(0x90041, 0xf); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s0 +dwc_ddrphy_apb_wr(0x90042, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s1 +dwc_ddrphy_apb_wr(0x90043, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s2 +dwc_ddrphy_apb_wr(0x90044, 0x107); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s0 +dwc_ddrphy_apb_wr(0x90045, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s1 +dwc_ddrphy_apb_wr(0x90046, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s2 +dwc_ddrphy_apb_wr(0x90047, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s0 +dwc_ddrphy_apb_wr(0x90048, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s1 +dwc_ddrphy_apb_wr(0x90049, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s2 +dwc_ddrphy_apb_wr(0x9004a, 0x147); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s0 +dwc_ddrphy_apb_wr(0x9004b, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s1 +dwc_ddrphy_apb_wr(0x9004c, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s2 +dwc_ddrphy_apb_wr(0x9004d, 0x14f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s0 +dwc_ddrphy_apb_wr(0x9004e, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s1 +dwc_ddrphy_apb_wr(0x9004f, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s2 +dwc_ddrphy_apb_wr(0x90050, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s0 +dwc_ddrphy_apb_wr(0x90051, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s1 +dwc_ddrphy_apb_wr(0x90052, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s2 +dwc_ddrphy_apb_wr(0x90053, 0x47); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s0 +dwc_ddrphy_apb_wr(0x90054, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s1 +dwc_ddrphy_apb_wr(0x90055, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s2 +dwc_ddrphy_apb_wr(0x90056, 0x4f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s0 +dwc_ddrphy_apb_wr(0x90057, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s1 +dwc_ddrphy_apb_wr(0x90058, 0x179); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s2 +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 800, type = 0 +dwc_ddrphy_apb_wr(0x90059, 0x100); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s0 +dwc_ddrphy_apb_wr(0x9005a, 0x15c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s1 +dwc_ddrphy_apb_wr(0x9005b, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 0 +dwc_ddrphy_apb_wr(0x9005c, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s0 +dwc_ddrphy_apb_wr(0x9005d, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s1 +dwc_ddrphy_apb_wr(0x9005e, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s2 +dwc_ddrphy_apb_wr(0x9005f, 0x11); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s0 +dwc_ddrphy_apb_wr(0x90060, 0x530); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s1 +dwc_ddrphy_apb_wr(0x90061, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s2 +dwc_ddrphy_apb_wr(0x90062, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s0 +dwc_ddrphy_apb_wr(0x90063, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s1 +dwc_ddrphy_apb_wr(0x90064, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s2 +dwc_ddrphy_apb_wr(0x90065, 0x14f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s0 +dwc_ddrphy_apb_wr(0x90066, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s1 +dwc_ddrphy_apb_wr(0x90067, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s2 +dwc_ddrphy_apb_wr(0x90068, 0x2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s0 +dwc_ddrphy_apb_wr(0x90069, 0x45a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s1 +dwc_ddrphy_apb_wr(0x9006a, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s2 +dwc_ddrphy_apb_wr(0x9006b, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s0 +dwc_ddrphy_apb_wr(0x9006c, 0x530); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s1 +dwc_ddrphy_apb_wr(0x9006d, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 0 +dwc_ddrphy_apb_wr(0x9006e, 0xc100); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s0 +dwc_ddrphy_apb_wr(0x9006f, 0x15c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s1 +dwc_ddrphy_apb_wr(0x90070, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s2 +dwc_ddrphy_apb_wr(0x90071, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s0 +dwc_ddrphy_apb_wr(0x90072, 0x65a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s1 +dwc_ddrphy_apb_wr(0x90073, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s2 +dwc_ddrphy_apb_wr(0x90074, 0x41); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s0 +dwc_ddrphy_apb_wr(0x90075, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s1 +dwc_ddrphy_apb_wr(0x90076, 0x179); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s2 +dwc_ddrphy_apb_wr(0x90077, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s0 +dwc_ddrphy_apb_wr(0x90078, 0x618); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s1 +dwc_ddrphy_apb_wr(0x90079, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s2 +dwc_ddrphy_apb_wr(0x9007a, 0x40c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s0 +dwc_ddrphy_apb_wr(0x9007b, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s1 +dwc_ddrphy_apb_wr(0x9007c, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s2 +dwc_ddrphy_apb_wr(0x9007d, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s0 +dwc_ddrphy_apb_wr(0x9007e, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s1 +dwc_ddrphy_apb_wr(0x9007f, 0x48); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s2 +dwc_ddrphy_apb_wr(0x90080, 0x4040); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s0 +dwc_ddrphy_apb_wr(0x90081, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s1 +dwc_ddrphy_apb_wr(0x90082, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s2 +dwc_ddrphy_apb_wr(0x90083, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s0 +dwc_ddrphy_apb_wr(0x90084, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s1 +dwc_ddrphy_apb_wr(0x90085, 0x48); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s2 +dwc_ddrphy_apb_wr(0x90086, 0x40); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s0 +dwc_ddrphy_apb_wr(0x90087, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s1 +dwc_ddrphy_apb_wr(0x90088, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s2 +dwc_ddrphy_apb_wr(0x90089, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s0 +dwc_ddrphy_apb_wr(0x9008a, 0x658); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s1 +dwc_ddrphy_apb_wr(0x9008b, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s2 +dwc_ddrphy_apb_wr(0x9008c, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s0 +dwc_ddrphy_apb_wr(0x9008d, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s1 +dwc_ddrphy_apb_wr(0x9008e, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s2 +dwc_ddrphy_apb_wr(0x9008f, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s0 +dwc_ddrphy_apb_wr(0x90090, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s1 +dwc_ddrphy_apb_wr(0x90091, 0x78); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s2 +dwc_ddrphy_apb_wr(0x90092, 0x549); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s0 +dwc_ddrphy_apb_wr(0x90093, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s1 +dwc_ddrphy_apb_wr(0x90094, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s2 +dwc_ddrphy_apb_wr(0x90095, 0xd49); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s0 +dwc_ddrphy_apb_wr(0x90096, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s1 +dwc_ddrphy_apb_wr(0x90097, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s2 +dwc_ddrphy_apb_wr(0x90098, 0x94c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s0 +dwc_ddrphy_apb_wr(0x90099, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s1 +dwc_ddrphy_apb_wr(0x9009a, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s2 +dwc_ddrphy_apb_wr(0x9009b, 0x94c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s0 +dwc_ddrphy_apb_wr(0x9009c, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s1 +dwc_ddrphy_apb_wr(0x9009d, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s2 +dwc_ddrphy_apb_wr(0x9009e, 0x442); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s0 +dwc_ddrphy_apb_wr(0x9009f, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s1 +dwc_ddrphy_apb_wr(0x900a0, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s2 +dwc_ddrphy_apb_wr(0x900a1, 0x42); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s0 +dwc_ddrphy_apb_wr(0x900a2, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s1 +dwc_ddrphy_apb_wr(0x900a3, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s2 +dwc_ddrphy_apb_wr(0x900a4, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s0 +dwc_ddrphy_apb_wr(0x900a5, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s1 +dwc_ddrphy_apb_wr(0x900a6, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s2 +dwc_ddrphy_apb_wr(0x900a7, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s0 +dwc_ddrphy_apb_wr(0x900a8, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s1 +dwc_ddrphy_apb_wr(0x900a9, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s2 +dwc_ddrphy_apb_wr(0x900aa, 0xa); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s0 +dwc_ddrphy_apb_wr(0x900ab, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s1 +dwc_ddrphy_apb_wr(0x900ac, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s2 +dwc_ddrphy_apb_wr(0x900ad, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s0 +dwc_ddrphy_apb_wr(0x900ae, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s1 +dwc_ddrphy_apb_wr(0x900af, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s2 +dwc_ddrphy_apb_wr(0x900b0, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s0 +dwc_ddrphy_apb_wr(0x900b1, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s1 +dwc_ddrphy_apb_wr(0x900b2, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s2 +dwc_ddrphy_apb_wr(0x900b3, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s0 +dwc_ddrphy_apb_wr(0x900b4, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s1 +dwc_ddrphy_apb_wr(0x900b5, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s2 +dwc_ddrphy_apb_wr(0x900b6, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s0 +dwc_ddrphy_apb_wr(0x900b7, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s1 +dwc_ddrphy_apb_wr(0x900b8, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s2 +dwc_ddrphy_apb_wr(0x900b9, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s0 +dwc_ddrphy_apb_wr(0x900ba, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s1 +dwc_ddrphy_apb_wr(0x900bb, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s2 +dwc_ddrphy_apb_wr(0x900bc, 0xc); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s0 +dwc_ddrphy_apb_wr(0x900bd, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s1 +dwc_ddrphy_apb_wr(0x900be, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s2 +dwc_ddrphy_apb_wr(0x900bf, 0x3); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s0 +dwc_ddrphy_apb_wr(0x900c0, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s1 +dwc_ddrphy_apb_wr(0x900c1, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s2 +dwc_ddrphy_apb_wr(0x900c2, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s0 +dwc_ddrphy_apb_wr(0x900c3, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s1 +dwc_ddrphy_apb_wr(0x900c4, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s2 +//// [phyinit_LoadPIECodeSections] Matched ANY enable_bits = 8, type = 0 +dwc_ddrphy_apb_wr(0x900c5, 0x3a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s0 +dwc_ddrphy_apb_wr(0x900c6, 0x1e2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s1 +dwc_ddrphy_apb_wr(0x900c7, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s2 +dwc_ddrphy_apb_wr(0x900c8, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s0 +dwc_ddrphy_apb_wr(0x900c9, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s1 +dwc_ddrphy_apb_wr(0x900ca, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s2 +dwc_ddrphy_apb_wr(0x900cb, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s0 +dwc_ddrphy_apb_wr(0x900cc, 0x400); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s1 +dwc_ddrphy_apb_wr(0x900cd, 0x16e); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s2 +dwc_ddrphy_apb_wr(0x900ce, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s0 +dwc_ddrphy_apb_wr(0x900cf, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s1 +dwc_ddrphy_apb_wr(0x900d0, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s2 +dwc_ddrphy_apb_wr(0x900d1, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s0 +dwc_ddrphy_apb_wr(0x900d2, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s1 +dwc_ddrphy_apb_wr(0x900d3, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s2 +dwc_ddrphy_apb_wr(0x900d4, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s0 +dwc_ddrphy_apb_wr(0x900d5, 0x978); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s1 +dwc_ddrphy_apb_wr(0x900d6, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s2 +dwc_ddrphy_apb_wr(0x900d7, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s0 +dwc_ddrphy_apb_wr(0x900d8, 0xa78); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s1 +dwc_ddrphy_apb_wr(0x900d9, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s2 +dwc_ddrphy_apb_wr(0x900da, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s0 +dwc_ddrphy_apb_wr(0x900db, 0x980); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s1 +dwc_ddrphy_apb_wr(0x900dc, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s2 +dwc_ddrphy_apb_wr(0x900dd, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s0 +dwc_ddrphy_apb_wr(0x900de, 0xa80); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s1 +dwc_ddrphy_apb_wr(0x900df, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s2 +dwc_ddrphy_apb_wr(0x900e0, 0x32); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s0 +dwc_ddrphy_apb_wr(0x900e1, 0x952); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s1 +dwc_ddrphy_apb_wr(0x900e2, 0x69); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s2 +dwc_ddrphy_apb_wr(0x900e3, 0x32); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s0 +dwc_ddrphy_apb_wr(0x900e4, 0xa52); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s1 +dwc_ddrphy_apb_wr(0x900e5, 0x69); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s2 +dwc_ddrphy_apb_wr(0x900e6, 0x2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s0 +dwc_ddrphy_apb_wr(0x900e7, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s1 +dwc_ddrphy_apb_wr(0x900e8, 0x68); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s2 +dwc_ddrphy_apb_wr(0x900e9, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s0 +dwc_ddrphy_apb_wr(0x900ea, 0x370); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s1 +dwc_ddrphy_apb_wr(0x900eb, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s2 +dwc_ddrphy_apb_wr(0x900ec, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s0 +dwc_ddrphy_apb_wr(0x900ed, 0x1400); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s1 +dwc_ddrphy_apb_wr(0x900ee, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s2 +dwc_ddrphy_apb_wr(0x900ef, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s0 +dwc_ddrphy_apb_wr(0x900f0, 0x8e8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s1 +dwc_ddrphy_apb_wr(0x900f1, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s2 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 0 +//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 0 +//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 2, type = 0 +dwc_ddrphy_apb_wr(0x900f2, 0x2cd); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s0 +dwc_ddrphy_apb_wr(0x900f3, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s1 +dwc_ddrphy_apb_wr(0x900f4, 0x68); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s2 +dwc_ddrphy_apb_wr(0x900f5, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s0 +dwc_ddrphy_apb_wr(0x900f6, 0x8e8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s1 +dwc_ddrphy_apb_wr(0x900f7, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s2 +dwc_ddrphy_apb_wr(0x900f8, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b69s0 +dwc_ddrphy_apb_wr(0x900f9, 0x3c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b69s1 +dwc_ddrphy_apb_wr(0x900fa, 0x1e9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b69s2 +dwc_ddrphy_apb_wr(0x900fb, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b70s0 +dwc_ddrphy_apb_wr(0x900fc, 0x370); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b70s1 +dwc_ddrphy_apb_wr(0x900fd, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b70s2 +dwc_ddrphy_apb_wr(0x900fe, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b71s0 +dwc_ddrphy_apb_wr(0x900ff, 0xe8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b71s1 +dwc_ddrphy_apb_wr(0x90100, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b71s2 +dwc_ddrphy_apb_wr(0x90101, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b72s0 +dwc_ddrphy_apb_wr(0x90102, 0x8140); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b72s1 +dwc_ddrphy_apb_wr(0x90103, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b72s2 +dwc_ddrphy_apb_wr(0x90104, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b73s0 +dwc_ddrphy_apb_wr(0x90105, 0x8138); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b73s1 +dwc_ddrphy_apb_wr(0x90106, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b73s2 +//// [phyinit_LoadPIECodeSections] Matched ANY enable_bits = 1, type = 0 +dwc_ddrphy_apb_wr(0x90107, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b74s0 +dwc_ddrphy_apb_wr(0x90108, 0x400); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b74s1 +dwc_ddrphy_apb_wr(0x90109, 0x10e); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b74s2 +dwc_ddrphy_apb_wr(0x9010a, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b75s0 +dwc_ddrphy_apb_wr(0x9010b, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b75s1 +dwc_ddrphy_apb_wr(0x9010c, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b75s2 +dwc_ddrphy_apb_wr(0x9010d, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b76s0 +dwc_ddrphy_apb_wr(0x9010e, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b76s1 +dwc_ddrphy_apb_wr(0x9010f, 0x101); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b76s2 +dwc_ddrphy_apb_wr(0x90110, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b77s0 +dwc_ddrphy_apb_wr(0x90111, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b77s1 +dwc_ddrphy_apb_wr(0x90112, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b77s2 +dwc_ddrphy_apb_wr(0x90113, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b78s0 +dwc_ddrphy_apb_wr(0x90114, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b78s1 +dwc_ddrphy_apb_wr(0x90115, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b78s2 +dwc_ddrphy_apb_wr(0x90116, 0xf); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b79s0 +dwc_ddrphy_apb_wr(0x90117, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b79s1 +dwc_ddrphy_apb_wr(0x90118, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b79s2 +dwc_ddrphy_apb_wr(0x90119, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b80s0 +dwc_ddrphy_apb_wr(0x9011a, 0xe8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b80s1 +dwc_ddrphy_apb_wr(0x9011b, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b80s2 +dwc_ddrphy_apb_wr(0x9011c, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b81s0 +dwc_ddrphy_apb_wr(0x9011d, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b81s1 +dwc_ddrphy_apb_wr(0x9011e, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b81s2 +dwc_ddrphy_apb_wr(0x9011f, 0x47); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b82s0 +dwc_ddrphy_apb_wr(0x90120, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b82s1 +dwc_ddrphy_apb_wr(0x90121, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b82s2 +dwc_ddrphy_apb_wr(0x90122, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b83s0 +dwc_ddrphy_apb_wr(0x90123, 0x618); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b83s1 +dwc_ddrphy_apb_wr(0x90124, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b83s2 +dwc_ddrphy_apb_wr(0x90125, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b84s0 +dwc_ddrphy_apb_wr(0x90126, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b84s1 +dwc_ddrphy_apb_wr(0x90127, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b84s2 +dwc_ddrphy_apb_wr(0x90128, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b85s0 +dwc_ddrphy_apb_wr(0x90129, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b85s1 +dwc_ddrphy_apb_wr(0x9012a, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b85s2 +dwc_ddrphy_apb_wr(0x9012b, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b86s0 +dwc_ddrphy_apb_wr(0x9012c, 0x8140); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b86s1 +dwc_ddrphy_apb_wr(0x9012d, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b86s2 +dwc_ddrphy_apb_wr(0x9012e, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b87s0 +dwc_ddrphy_apb_wr(0x9012f, 0x478); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b87s1 +dwc_ddrphy_apb_wr(0x90130, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b87s2 +dwc_ddrphy_apb_wr(0x90131, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b88s0 +dwc_ddrphy_apb_wr(0x90132, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b88s1 +dwc_ddrphy_apb_wr(0x90133, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b88s2 +dwc_ddrphy_apb_wr(0x90134, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b89s0 +dwc_ddrphy_apb_wr(0x90135, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b89s1 +dwc_ddrphy_apb_wr(0x90136, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b89s2 +dwc_ddrphy_apb_wr(0x90137, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b90s0 +dwc_ddrphy_apb_wr(0x90138, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b90s1 +dwc_ddrphy_apb_wr(0x90139, 0x101); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b90s2 +//// [phyinit_LoadPIECodeSections] Moving start address from 9013a to 90006 +dwc_ddrphy_apb_wr(0x90006, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s0 +dwc_ddrphy_apb_wr(0x90007, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s1 +dwc_ddrphy_apb_wr(0x90008, 0x8); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s2 +dwc_ddrphy_apb_wr(0x90009, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s0 +dwc_ddrphy_apb_wr(0x9000a, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s1 +dwc_ddrphy_apb_wr(0x9000b, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s2 +//// [phyinit_LoadPIECodeSections] Moving start address from 9000c to d00e7 +dwc_ddrphy_apb_wr(0xd00e7, 0x400); // DWC_DDRPHYA_APBONLY0_SequencerOverride +//// [phyinit_LoadPIECodeSections] End of dwc_ddrphy_phyinit_LoadPIECodeSections() +dwc_ddrphy_apb_wr(0x20240, 0x4300); // DWC_DDRPHYA_MASTER0_base0_D5ACSMPtrXlat0 +dwc_ddrphy_apb_wr(0x20242, 0x8944); // DWC_DDRPHYA_MASTER0_base0_D5ACSMPtrXlat2 +dwc_ddrphy_apb_wr(0x20241, 0x4300); // DWC_DDRPHYA_MASTER0_base0_D5ACSMPtrXlat1 +dwc_ddrphy_apb_wr(0x20243, 0x8944); // DWC_DDRPHYA_MASTER0_base0_D5ACSMPtrXlat3 +//seq0b_LoadPstateSeqProductionCode(): --------------------------------------------------------------------------------------------------- +//seq0b_LoadPstateSeqProductionCode(): Programming the 0B sequencer 0b0000 start vector registers with 0. +//seq0b_LoadPstateSeqProductionCode(): Programming the 0B sequencer 0b1000 start vector register with 54. +//seq0b_LoadPstateSeqProductionCode(): Programming the 0B sequencer 0b1111 start vector register with 77. +//seq0b_LoadPstateSeqProductionCode(): --------------------------------------------------------------------------------------------------- +dwc_ddrphy_apb_wr(0x90017, 0x0); // DWC_DDRPHYA_INITENG0_base0_StartVector0b0 +dwc_ddrphy_apb_wr(0x9001f, 0x36); // DWC_DDRPHYA_INITENG0_base0_StartVector0b8 +dwc_ddrphy_apb_wr(0x90026, 0x4d); // DWC_DDRPHYA_INITENG0_base0_StartVector0b15 +dwc_ddrphy_apb_wr(0x9000c, 0x0); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag0 +dwc_ddrphy_apb_wr(0x9000d, 0x173); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag1 +dwc_ddrphy_apb_wr(0x9000e, 0x60); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag2 +dwc_ddrphy_apb_wr(0x9000f, 0x6110); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag3 +dwc_ddrphy_apb_wr(0x90010, 0x2152); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag4 +dwc_ddrphy_apb_wr(0x90011, 0xdfbd); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag5 +dwc_ddrphy_apb_wr(0x90012, 0x8060); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag6 +dwc_ddrphy_apb_wr(0x90013, 0x6152); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag7 +//// [phyinit_I_loadPIEImage] Enabling Phy Master Interface for DRAM drift compensation +//// [phyinit_I_loadPIEImage] Pstate=0, Memclk=1600MHz, Programming PPTTrainSetup::PhyMstrTrainInterval to 0x0 +//// [phyinit_I_loadPIEImage] Pstate=0, Memclk=1600MHz, Programming PPTTrainSetup::PhyMstrMaxReqToAck to 0x0 +dwc_ddrphy_apb_wr(0x20010, 0x0); // DWC_DDRPHYA_MASTER0_base0_PPTTrainSetup_p0 +//// [phyinit_I_loadPIEImage] Pstate=0, Memclk=1600MHz, Programming PPTTrainSetup2::PhyMstrFreqOverride to 0x3 +dwc_ddrphy_apb_wr(0x20011, 0x3); // DWC_DDRPHYA_MASTER0_base0_PPTTrainSetup2_p0 +//// [phyinit_I_loadPIEImage] Programming D5ACSMXlatSelect to 0x1 +dwc_ddrphy_apb_wr(0x20281, 0x1); // DWC_DDRPHYA_MASTER0_base0_D5ACSMXlatSelect +//// [phyinit_I_loadPIEImage] Programming DbyteRxEnTrain::EnDqsSampNegRxEn to 0x1 +dwc_ddrphy_apb_wr(0x2003b, 0x2); // DWC_DDRPHYA_MASTER0_base0_DbyteRxEnTrain +//// [phyinit_I_loadPIEImage] Pstate=0, Memclk=1600MHz, Programming TrackingModeCntrl to 0x131f +dwc_ddrphy_apb_wr(0x20041, 0x131f); // DWC_DDRPHYA_MASTER0_base0_TrackingModeCntrl_p0 +//// [phyinit_I_loadPIEImage] Programming D5ACSM0MaskCs to 0xe +dwc_ddrphy_apb_wr(0x20131, 0xe); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0MaskCs +//// [phyinit_I_loadPIEImage] Programming D5ACSM1MaskCs to 0xf +dwc_ddrphy_apb_wr(0x20151, 0xf); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1MaskCs +//// [phyinit_I_loadPIEImage] Pstate=0, Memclk=1600MHz, Programming Seq0BGPR6[0] with OuterLoopRepeatCnt values to 0x2 +dwc_ddrphy_apb_wr(0x90306, 0x2); // DWC_DDRPHYA_INITENG0_base0_Seq0BGPR6_p0 +//// [phyinit_I_loadPIEImage] Programming D5ACSM<0/1>OuterLoopRepeatCnt=2 +dwc_ddrphy_apb_wr(0x2012a, 0x2); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0OuterLoopRepeatCnt +dwc_ddrphy_apb_wr(0x2014a, 0x2); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1OuterLoopRepeatCnt +//// [phyinit_I_loadPIEImage] Programming D5ACSM<0/1>AddressMask=7ff +dwc_ddrphy_apb_wr(0x20126, 0x7ff); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0AddressMask +dwc_ddrphy_apb_wr(0x20146, 0x7ff); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1AddressMask +//// [phyinit_I_loadPIEImage] Programming D5ACSM<0/1>AlgaIncVal=1 +dwc_ddrphy_apb_wr(0x20127, 0x1); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0AlgaIncVal +dwc_ddrphy_apb_wr(0x20147, 0x1); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1AlgaIncVal +//// [phyinit_I_loadPIEImage] Turn on calibration and hold idle until dfi_init_start is asserted sequence is triggered. +//// [phyinit_I_loadPIEImage] Programming CalZap to 0x1 +//// [phyinit_I_loadPIEImage] Programming CalRate::CalRun to 0x1 +//// [phyinit_I_loadPIEImage] Programming CalRate to 0x19 +dwc_ddrphy_apb_wr(0x20089, 0x1); // DWC_DDRPHYA_MASTER0_base0_CalZap +dwc_ddrphy_apb_wr(0x20088, 0x19); // DWC_DDRPHYA_MASTER0_base0_CalRate +//// [phyinit_I_loadPIEImage] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x0 +dwc_ddrphy_apb_wr(0x200a6, 0x0); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables +//// Disabling Ucclk (PMU) and Hclk (training hardware) +dwc_ddrphy_apb_wr(0xc0080, 0x0); // DWC_DDRPHYA_DRTUB0_UcclkHclkEnables +//// Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. +dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +//// [phyinit_userCustom_wait] Wait 40 DfiClks +//// [phyinit_I_loadPIEImage] End of dwc_ddrphy_phyinit_I_loadPIEImage() +// +// +////############################################################## +//// +//// dwc_ddrphy_phyinit_userCustom_customPostTrain is a user-editable function. +//// +//// The purpose of dwc_ddrphy_phyinit_userCustom_customPostTrain() is to override any +//// CSR values programmed by the training firmware or dwc_ddrphy_phyinit_progCsrSkipTrain() +//// This function is executed after training +//// +//// IMPORTANT: in this function, user shall not override any values in userInputBasic and +//// userInputAdvanced data structures. Only CSR programming should be done in this function. +//// +//// Sequence of Events in this function are: +//// 1. Enable APB access. +//// 2. Issue register writes +//// 3. Isolate APB access. +// +////############################################################## +// +dwc_ddrphy_phyinit_userCustom_customPostTrain(); + +//// [dwc_ddrphy_phyinit_userCustom_customPostTrain] End of dwc_ddrphy_phyinit_userCustom_customPostTrain() +//// [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] Start of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() +// +// +////############################################################## +//// +//// 4.3.10(J) Initialize the PHY to Mission Mode through DFI Initialization +//// +//// Initialize the PHY to mission mode as follows: +//// +//// 1. Set the PHY input clocks to the desired frequency. +//// 2. Initialize the PHY to mission mode by performing DFI Initialization. +//// Please see the DFI specification for more information. See the DFI frequency bus encoding in section <XXX>. +//// Note: The PHY training firmware initializes the DRAM state. if skip +//// training is used, the DRAM state is not initialized. +//// +////############################################################## +// +dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(sdrammc); + +// +//// [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] End of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode() +// [dwc_ddrphy_phyinit_sequence] End of dwc_ddrphy_phyinit_sequence() +// [dwc_ddrphy_phyinit_main] End of dwc_ddrphy_phyinit_main() diff --git a/drivers/ram/aspeed/sdram_ast2700.c b/drivers/ram/aspeed/sdram_ast2700.c new file mode 100644 index 00000000000..4a019c4edb1 --- /dev/null +++ b/drivers/ram/aspeed/sdram_ast2700.c @@ -0,0 +1,1036 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + */ +#include <asm/io.h> +#include <asm/arch/fmc_hdr.h> +#include <asm/arch/scu.h> +#include <asm/arch/sdram.h> +#include <config.h> +#include <dm.h> +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/sizes.h> +#include <ram.h> + +enum ddr_type { + DDR4_1600 = 0x0, + DDR4_2400, + DDR4_3200, + DDR5_3200, + + DDR_TYPES +}; + +enum ddr_size { + DDR_SIZE_256MB, + DDR_SIZE_512MB, + DDR_SIZE_1GB, + DDR_SIZE_2GB, + + DDR_SIZE_MAX, +}; + +#define IS_DDR4(t) \ + (((t) <= DDR4_3200) ? 1 : 0) + +struct sdrammc_ac_timing { + u32 t_cl; + u32 t_cwl; + u32 t_bl; + u32 t_rcd; /* ACT-to-read/write command delay */ + u32 t_rp; /* PRE command period */ + u32 t_ras; /* ACT-to-PRE command delay */ + u32 t_rrd; /* ACT-to-ACT delay for different BG */ + u32 t_rrd_l; /* ACT-to-ACT delay for same BG */ + u32 t_faw; /* Four active window */ + u32 t_rtp; /* Read-to-PRE command delay */ + u32 t_wtr; /* Minimum write to read command for different BG */ + u32 t_wtr_l; /* Minimum write to read command for same BG */ + u32 t_wtr_a; /* Write to read command for same BG with auto precharge */ + u32 t_wtp; /* Minimum write to precharge command delay */ + u32 t_rtw; /* minimum read to write command */ + u32 t_ccd_l; /* CAS-to-CAS delay for same BG */ + u32 t_dllk; /* DLL locking time */ + u32 t_cksre; /* valid clock before after self-refresh or power-down entry/exit process */ + u32 t_pd; /* power-down entry to exit minimum width */ + u32 t_xp; /* exit power-down to valid command delay */ + u32 t_rfc; /* refresh time period */ + u32 t_mrd; + u32 t_refsbrd; + u32 t_rfcsb; + u32 t_cshsr; + u32 t_zq; +}; + +static const struct sdrammc_ac_timing ac_table[] = { + [DDR4_1600] = { + .t_cl = 10, .t_cwl = 9, .t_bl = 8, .t_rcd = 10, + .t_rp = 10, .t_ras = 28, .t_rrd = 5, .t_rrd_l = 6, + .t_faw = 28, .t_rtp = 6, .t_wtr = 2, .t_wtr_l = 6, + .t_wtr_a = 0, .t_wtp = 12, .t_rtw = 0, .t_ccd_l = 5, + .t_dllk = 597, .t_cksre = 8, .t_pd = 4, .t_xp = 5, + .t_rfc = 880, .t_mrd = 24, .t_refsbrd = 0, .t_rfcsb = 0, + .t_cshsr = 0, .t_zq = 80, + }, + [DDR4_2400] = { + .t_cl = 15, .t_cwl = 12, .t_bl = 8, .t_rcd = 16, + .t_rp = 16, .t_ras = 39, .t_rrd = 7, .t_rrd_l = 8, + .t_faw = 37, .t_rtp = 10, .t_wtr = 4, .t_wtr_l = 10, + .t_wtr_a = 0, .t_wtp = 19, .t_rtw = 0, .t_ccd_l = 7, + .t_dllk = 768, .t_cksre = 13, .t_pd = 7, .t_xp = 8, + .t_rfc = 880, .t_mrd = 24, .t_refsbrd = 0, .t_rfcsb = 0, + .t_cshsr = 0, .t_zq = 80, + }, + [DDR4_3200] = { + .t_cl = 20, .t_cwl = 16, .t_bl = 8, .t_rcd = 20, + .t_rp = 20, .t_ras = 52, .t_rrd = 9, .t_rrd_l = 11, + .t_faw = 48, .t_rtp = 12, .t_wtr = 4, .t_wtr_l = 12, + .t_wtr_a = 0, .t_wtp = 24, .t_rtw = 0, .t_ccd_l = 8, + .t_dllk = 1023, .t_cksre = 16, .t_pd = 8, .t_xp = 10, + .t_rfc = 880, .t_mrd = 24, .t_refsbrd = 0, .t_rfcsb = 0, + .t_cshsr = 0, .t_zq = 80, + }, + [DDR5_3200] = { + .t_cl = 26, .t_cwl = 24, .t_bl = 16, .t_rcd = 26, + .t_rp = 26, .t_ras = 52, .t_rrd = 8, .t_rrd_l = 8, + .t_faw = 40, .t_rtp = 12, .t_wtr = 4, .t_wtr_l = 16, + .t_wtr_a = 36, .t_wtp = 48, .t_rtw = 0, .t_ccd_l = 8, + .t_dllk = 1024, .t_cksre = 9, .t_pd = 13, .t_xp = 13, + .t_rfc = 880, .t_mrd = 23, .t_refsbrd = 48, .t_rfcsb = 208, + .t_cshsr = 30, + .t_zq = 48, + }, +}; + +struct sdrammc { + u32 type; + void __iomem *regs; + void __iomem *phy; + void __iomem *scu0; + void __iomem *scu1; + const struct sdrammc_ac_timing *ac; + struct ram_info info; +}; + +static size_t ast2700_sdrammc_get_vga_mem_size(struct sdrammc *sdrammc) +{ + struct sdrammc_regs *regs = sdrammc->regs; + void *scu0 = sdrammc->scu0; + size_t vga_memsz[] = { + SZ_32M, + SZ_64M, + }; + u32 reg, sel, dual = 0; + + sel = readl(®s->gfmcfg) & 0x1; + + reg = readl(scu0 + SCU0_PCI_MISC70); + if (reg & SCU0_PCI_MISC70_EN_PCIEVGA0) { + debug("VGA0:%dMB\n", vga_memsz[sel] / SZ_1M); + dual++; + } + + reg = readl(scu0 + SCU0_PCI_MISC80); + if (reg & SCU0_PCI_MISC80_EN_PCIEVGA1) { + debug("VGA1:%dMB\n", vga_memsz[sel] / SZ_1M); + dual++; + } + + return vga_memsz[sel] * dual; +} + +static int sdrammc_calc_size(struct sdrammc *sdrammc) +{ + struct sdrammc_regs *regs = sdrammc->regs; + u32 val, test_pattern = 0xdeadbeef; + size_t sz; + + struct { + u32 size; + int rfc[2]; + } ddr_capacity[] = { + { 0x10000000UL, {208, 256} }, /* 256MB */ + { 0x20000000UL, {208, 416} }, /* 512MB */ + { 0x40000000UL, {208, 560} }, /* 1GB */ + { 0x80000000UL, {472, 880} }, /* 2GB */ + }; + + /* Configure ram size to max to enable whole area */ + val = readl(®s->mcfg); + val &= ~(0x7 << 2); + writel(val | (DDR_SIZE_2GB << 2), ®s->mcfg); + + /* Clear basement. */ + writel(0, (void *)CFG_SYS_SDRAM_BASE); + + for (sz = DDR_SIZE_2GB - 1; sz > DDR_SIZE_256MB; sz--) { + test_pattern = (test_pattern << 4) + sz; + writel(test_pattern, (void *)(CFG_SYS_SDRAM_BASE + ddr_capacity[sz].size)); + + if (readl((void *)CFG_SYS_SDRAM_BASE) != test_pattern) + break; + } + + /* re-configure ram size to dramc. */ + val = readl(®s->mcfg); + val &= ~(0x7 << 2); + writel(val | ((sz + 1) << 2), ®s->mcfg); + + /* update rfc in ac_timing5 register. */ + val = readl(®s->actime5); + val &= ~(0x3ff); + val |= (ddr_capacity[sz + 1].rfc[IS_DDR4(sdrammc->type)] >> 1); + writel(val, ®s->actime5); + + /* report actual ram base and size to kernel */ + sdrammc->info.base = CFG_SYS_SDRAM_BASE; + sdrammc->info.size = ddr_capacity[sz + 1].size; + + /* reserve the VGA memory */ + sdrammc->info.size -= ast2700_sdrammc_get_vga_mem_size(sdrammc); + + return 0; +} + +static int sdrammc_bist(struct sdrammc *sdrammc, u32 addr, u32 size, u32 cfg, u32 timeout) +{ + struct sdrammc_regs *regs = sdrammc->regs; + u32 val; + u32 err = 0; + + writel(0, ®s->bistcfg); + writel(cfg, ®s->bistcfg); + writel(addr >> 4, ®s->bist_addr); + writel(size >> 4, ®s->bist_size); + writel(0x89abcdef, ®s->bist_patt); + writel(cfg | DRAMC_BISTCFG_START, ®s->bistcfg); + + while (!(readl(®s->intr_status) & DRAMC_IRQSTA_BIST_DONE)) + ; + + writel(DRAMC_IRQSTA_BIST_DONE, ®s->intr_clear); + + val = readl(®s->bist_res); + + if (val & DRAMC_BISTRES_DONE) { + if (val & DRAMC_BISTRES_FAIL) + err++; + } else { + err++; + } + + return err; +} + +static void sdrammc_enable_refresh(struct sdrammc *sdrammc) +{ + struct sdrammc_regs *regs = sdrammc->regs; + + /* refresh update */ + clrbits_le32(®s->refctl, 0x8000); +} + +static void sdrammc_mr_send(struct sdrammc *sdrammc, u32 ctrl, u32 op) +{ + struct sdrammc_regs *regs = sdrammc->regs; + + writel(op, ®s->mrwr); + writel(ctrl | DRAMC_MRCTL_CMD_START, ®s->mrctl); + + while (!(readl(®s->intr_status) & DRAMC_IRQSTA_MR_DONE)) + ; + + writel(DRAMC_IRQSTA_MR_DONE, ®s->intr_clear); +} + +static void sdrammc_config_mrs(struct sdrammc *sdrammc) +{ + const struct sdrammc_ac_timing *ac = sdrammc->ac; + struct sdrammc_regs *regs = sdrammc->regs; + u32 mr0_cas, mr0_rtp, mr0_val; + u32 mr6_tccd_l, mr6_val; + u32 mr2_cwl, mr2_val; + u32 mr1_val; + u32 mr3_val; + u32 mr4_val; + u32 mr5_val; + + if (!IS_DDR4(sdrammc->type)) + return; + + //------------------------------------------------------------------- + // CAS Latency (Table-15) + //------------------------------------------------------------------- + switch (ac->t_cl) { + case 9: + mr0_cas = 0x00; //5'b00000; + break; + case 10: + mr0_cas = 0x01; //5'b00001; + break; + case 11: + mr0_cas = 0x02; //5'b00010; + break; + case 12: + mr0_cas = 0x03; //5'b00011; + break; + case 13: + mr0_cas = 0x04; //5'b00100; + break; + case 14: + mr0_cas = 0x05; //5'b00101; + break; + case 15: + mr0_cas = 0x06; //5'b00110; + break; + case 16: + mr0_cas = 0x07; //5'b00111; + break; + case 18: + mr0_cas = 0x08; //5'b01000; + break; + case 20: + mr0_cas = 0x09; //5'b01001; + break; + case 22: + mr0_cas = 0x0a; //5'b01010; + break; + case 24: + mr0_cas = 0x0b; //5'b01011; + break; + case 23: + mr0_cas = 0x0c; //5'b01100; + break; + case 17: + mr0_cas = 0x0d; //5'b01101; + break; + case 19: + mr0_cas = 0x0e; //5'b01110; + break; + case 21: + mr0_cas = 0x0f; //5'b01111; + break; + case 25: + mr0_cas = 0x10; //5'b10000; + break; + case 26: + mr0_cas = 0x11; //5'b10001; + break; + case 27: + mr0_cas = 0x12; //5'b10010; + break; + case 28: + mr0_cas = 0x13; //5'b10011; + break; + case 30: + mr0_cas = 0x15; //5'b10101; + break; + case 32: + mr0_cas = 0x17; //5'b10111; + break; + } + + //------------------------------------------------------------------- + // WR and RTP (Table-14) + //------------------------------------------------------------------- + switch (ac->t_rtp) { + case 5: + mr0_rtp = 0x0; //4'b0000; + break; + case 6: + mr0_rtp = 0x1; //4'b0001; + break; + case 7: + mr0_rtp = 0x2; //4'b0010; + break; + case 8: + mr0_rtp = 0x3; //4'b0011; + break; + case 9: + mr0_rtp = 0x4; //4'b0100; + break; + case 10: + mr0_rtp = 0x5; //4'b0101; + break; + case 12: + mr0_rtp = 0x6; //4'b0110; + break; + case 11: + mr0_rtp = 0x7; //4'b0111; + break; + case 13: + mr0_rtp = 0x8; //4'b1000; + break; + } + + //------------------------------------------------------------------- + // CAS Write Latency (Table-21) + //------------------------------------------------------------------- + switch (ac->t_cwl) { + case 9: + mr2_cwl = 0x0; // 3'b000; // 1600 + break; + case 10: + mr2_cwl = 0x1; // 3'b001; // 1866 + break; + case 11: + mr2_cwl = 0x2; // 3'b010; // 2133 + break; + case 12: + mr2_cwl = 0x3; // 3'b011; // 2400 + break; + case 14: + mr2_cwl = 0x4; // 3'b100; // 2666 + break; + case 16: + mr2_cwl = 0x5; // 3'b101; // 2933/3200 + break; + case 18: + mr2_cwl = 0x6; // 3'b110; + break; + case 20: + mr2_cwl = 0x7; // 3'b111; + break; + } + + //------------------------------------------------------------------- + // tCCD_L and tDLLK + //------------------------------------------------------------------- + switch (ac->t_ccd_l) { + case 4: + mr6_tccd_l = 0x0; //3'b000; // rate <= 1333 + break; + case 5: + mr6_tccd_l = 0x1; //3'b001; // 1333 < rate <= 1866 + break; + case 6: + mr6_tccd_l = 0x2; //3'b010; // 1866 < rate <= 2400 + break; + case 7: + mr6_tccd_l = 0x3; //3'b011; // 2400 < rate <= 2666 + break; + case 8: + mr6_tccd_l = 0x4; //3'b100; // 2666 < rate <= 3200 + break; + } + + /* + * mr0_val = + * mr0_rtp[3], // 13 + * mr0_cas[4], // 12 + * mr0_rtp[2:0], // 13,11-9: WR and RTP + * 1'b0, // 8: DLL reset + * 1'b0, // 7: TM + * mr0_cas[3:1], // 6-4,2: CAS latency + * 1'b0, // 3: sequential + * mr0_cas[0], + * 2'b00 // 1-0: burst length + */ + mr0_val = ((mr0_cas & 0x1) << 2) | + (((mr0_cas >> 1) & 0x7) << 4) | + (((mr0_cas >> 4) & 0x1) << 12) | + ((mr0_rtp & 0x7) << 9) | + (((mr0_rtp >> 3) & 0x1) << 13); + + /* + * 3'b2 //[10:8]: rtt_nom, 000:disable,001:rzq/4,010:rzq/2,011:rzq/6,100:rzq/1,101:rzq/5,110:rzq/3,111:rzq/7 + * 1'b0 //[7]: write leveling enable + * 2'b0 //[6:5]: reserved + * 2'b0 //[4:3]: additive latency + * 2'b0 //[2:1]: output driver impedance + * 1'b1 //[0]: enable dll + */ + mr1_val = 0x201; + + /* + * [10:9]: rtt_wr, 00:dynamic odt off, 01:rzq/2, 10:rzq/1, 11: hi-z + * [8]: 0 + */ + mr2_val = ((mr2_cwl & 0x7) << 3) | 0x200; + + mr3_val = 0; + + mr4_val = 0; + + /* + * mr5_val = { + * 1'b0, // 13: RFU + * 1'b0, // 12: read DBI + * 1'b0, // 11: write DBI + * 1'b1, // 10: Data mask + * 1'b0, // 9: C/A parity persistent error + * 3'b000, // 8-6: RTT_PARK (disable) + * 1'b1, // 5: ODT input buffer during power down mode + * 1'b0, // 4: C/A parity status + * 1'b0, // 3: CRC error clear + * 3'b0 // 2-0: C/A parity latency mode + * }; + */ + mr5_val = 0x420; + + /* + * mr6_val = { + * 1'b0, // 13, 9-8: RFU + * mr6_tccd_l[2:0], // 12-10: tCCD_L + * 2'b0, // 13, 9-8: RFU + * 1'b0, // 7: VrefDQ training enable + * 1'b0, // 6: VrefDQ training range + * 6'b0 // 5-0: VrefDQ training value + * }; + */ + mr6_val = ((mr6_tccd_l & 0x7) << 10); + + writel((mr1_val << 16) + mr0_val, ®s->mr01); + writel((mr3_val << 16) + mr2_val, ®s->mr23); + writel((mr5_val << 16) + mr4_val, ®s->mr45); + writel(mr6_val, ®s->mr67); + + /* Power-up initialization sequence */ + sdrammc_mr_send(sdrammc, MR_ADDR(3), 0); + sdrammc_mr_send(sdrammc, MR_ADDR(6), 0); + sdrammc_mr_send(sdrammc, MR_ADDR(5), 0); + sdrammc_mr_send(sdrammc, MR_ADDR(4), 0); + sdrammc_mr_send(sdrammc, MR_ADDR(2), 0); + sdrammc_mr_send(sdrammc, MR_ADDR(1), 0); + sdrammc_mr_send(sdrammc, MR_ADDR(0), 0); +} + +static void sdrammc_exit_self_refresh(struct sdrammc *sdrammc) +{ + struct sdrammc_regs *regs = sdrammc->regs; + + /* exit self-refresh after phy init */ + setbits_le32(®s->mctl, DRAMC_MCTL_SELF_REF_START); + + /* query if self-ref done */ + while (!(readl(®s->intr_status) & DRAMC_IRQSTA_REF_DONE)) + ; + + /* clear status */ + writel(DRAMC_IRQSTA_REF_DONE, ®s->intr_clear); + udelay(1); +} + +/* user-customized functions for the vendor PHY init code */ +#define DWC_PHY_IMEM_OFST 0x50000 +#define DWC_PHY_DMEM_OFST 0x58000 +#define DWC_PHY_MB_START_STREAM_MSG 0x8 +#define DWC_PHY_MB_TRAIN_SUCCESS 0x7 +#define DWC_PHY_MB_TRAIN_FAIL 0xff + +#define dwc_ddrphy_apb_wr(addr, data) \ + writew((data), sdrammc->phy + ((addr) << 1)) + +#define dwc_ddrphy_apb_rd(addr) \ + readw(sdrammc->phy + ((addr) << 1)) + +#define dwc_ddrphy_apb_wr_32b(addr, data) \ + writel((data), sdrammc->phy + ((addr) << 1)) + +#define dwc_ddrphy_apb_rd_32b(addr) \ + readl(sdrammc->phy + ((addr) << 1)) + +void dwc_get_mailbox(struct sdrammc *sdrammc, const int mode, u32 *mbox) +{ + u32 val; + + /* 1. Poll the UctWriteProtShadow, looking for a 0 */ + while (dwc_ddrphy_apb_rd(0xd0004) & BIT(0)) + ; + + /* 2. When a 0 is seen, read the UctWriteOnlyShadow register to get the major message number. */ + *mbox = dwc_ddrphy_apb_rd(0xd0032) & 0xffff; + + /* 3. If reading a streaming or SMBus message, also read the UctDatWriteOnlyShadow register. */ + if (mode) { + val = (dwc_ddrphy_apb_rd(0xd0034)) & 0xffff; + *mbox |= (val << 16); + } + + /* 4. Write the DctWriteProt to 0 to acknowledge the reception of the message */ + dwc_ddrphy_apb_wr(0xd0031, 0); + + /* 5. Poll the UctWriteProtShadow, looking for a 1 */ + while (!(dwc_ddrphy_apb_rd(0xd0004) & BIT(0))) + ; + + /* 6. When a 1 is seen, write the DctWriteProt to 1 to complete the protocol */ + dwc_ddrphy_apb_wr(0xd0031, 1); +} + +uint32_t dwc_readMsgBlock(struct sdrammc *sdrammc, const u32 addr_half) +{ + u32 data_word; + + data_word = dwc_ddrphy_apb_rd_32b((addr_half >> 1) << 1); + + if (addr_half & 0x1) + data_word = data_word >> 16; + else + data_word &= 0xffff; + + return data_word; +} + +int dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(struct sdrammc *sdrammc, int train2D) +{ + u32 msg; + + if (IS_DDR4(sdrammc->type)) { + /* DWC_PHY_DDR4_MB_RESULT */ + msg = dwc_readMsgBlock(sdrammc, 0x5800a); + if (msg & 0xff) + debug("%s: Training Failure index (0x%x)\n", __func__, msg); + else + debug("%s: %dD Training Passed\n", __func__, train2D ? 2 : 1); + } else { + /* DWC_PHY_DDR5_MB_RESULT */ + msg = dwc_readMsgBlock(sdrammc, 0x58007); + if (msg & 0xff00) + debug("%s: Training Failure index (0x%x)\n", __func__, msg); + else + debug("%s: DDR5 1D/2D Training Passed\n", __func__); + + /* DWC_PHY_DDR5_MB_RESULT_ADR */ + msg = dwc_readMsgBlock(sdrammc, 0x5800a); + debug("%s: Result Address Offset (0x%x)\n", __func__, msg); + } + + return 0; +} + +void dwc_ddrphy_phyinit_userCustom_A_bringupPower(void) +{ + /* do nothing */ +} + +void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(struct sdrammc *sdrammc) +{ + struct sdrammc_regs *regs = sdrammc->regs; + + /* + * 1. Drive PwrOkIn to 0. Note: Reset, DfiClk, and APBCLK can be X. + * 2. Start DfiClk and APBCLK + * 3. Drive Reset to 1 and PRESETn_APB to 0. + * Note: The combination of PwrOkIn=0 and Reset=1 signals a cold reset to the PHY. + */ + writel(DRAMC_MCTL_PHY_RESET, ®s->mctl); + udelay(2); + + /* + * 5. Drive PwrOkIn to 1. Once the PwrOkIn is asserted (and Reset is still asserted), + * DfiClk synchronously switches to any legal input frequency. + */ + writel(DRAMC_MCTL_PHY_RESET | DRAMC_MCTL_PHY_POWER_ON, ®s->mctl); + udelay(2); + + /* + * 7. Drive Reset to 0. Note: All DFI and APB inputs must be driven at valid reset states + * before the deassertion of Reset. + */ + writel(DRAMC_MCTL_PHY_POWER_ON, ®s->mctl); + udelay(2); + + /* + * 9. Drive PRESETn_APB to 1 to de-assert reset on the ABP bus. + * 10. The PHY is now in the reset state and is ready to accept APB transactions. + */ +} + +void dwc_ddrphy_phyinit_userCustom_overrideUserInput(void) +{ + /* do nothing */ +} + +void dwc_ddrphy_phyinit_userCustom_customPostTrain(void) +{ + /* do nothing */ +} + +void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(struct sdrammc *sdrammc) +{ + dwc_ddrphy_apb_wr(0xd0031, 1); /* DWC_DCTWRITEPROT */ + dwc_ddrphy_apb_wr(0xd0033, 1); /* DWC_UCTWRITEPROT */ +} + +void dwc_ddrphy_phyinit_userCustom_G_waitFwDone(struct sdrammc *sdrammc) +{ + u32 mbox, msg = 0; + + while (msg != DWC_PHY_MB_TRAIN_SUCCESS && msg != DWC_PHY_MB_TRAIN_FAIL) { + dwc_get_mailbox(sdrammc, 0, &mbox); + msg = mbox & 0xffff; + } +} + +void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(struct sdrammc *sdrammc) +{ + struct sdrammc_regs *regs = sdrammc->regs; + u32 val; + + /* + * 1. Set the PHY input clocks to the desired frequency. + * 2. Initialize the PHY to mission mode by performing DFI Initialization. + * Please see the DFI specification for more information. See the DFI frequency bus encoding in section <XXX>. + * Note: The PHY training firmware initializes the DRAM state. if skip + * training is used, the DRAM state is not initialized. + */ + + writel(0xffffffff, (void *)®s->intr_mask); + + writel(0x0, (void *)®s->dcfg); + + if (!IS_DDR4(sdrammc->type)) { + dwc_ddrphy_apb_wr(0xd0000, 0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x20240, 0x3900); /* DWC_DDRPHYA_MASTER0_base0_D5ACSMPtr0lat0 */ + dwc_ddrphy_apb_wr(0x900da, 8); /* DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s0 */ + dwc_ddrphy_apb_wr(0xd0000, 1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + } + + /* phy init start */ + val = readl((void *)®s->mctl); + val = val | DRAMC_MCTL_PHY_INIT_START; + writel(val, (void *)®s->mctl); + + /* wait phy complete */ + while (1) { + val = readl(®s->intr_status) & DRAMC_IRQSTA_PHY_INIT_DONE; + if (val == DRAMC_IRQSTA_PHY_INIT_DONE) + break; + } + + writel(0xffff, (void *)®s->intr_clear); + + while (readl((void *)®s->intr_status)) + ; + + if (!IS_DDR4(sdrammc->type)) { + dwc_ddrphy_apb_wr(0xd0000, 0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x20240, 0x4300); /* DWC_DDRPHYA_MASTER0_base0_D5ACSMPtr0lat0 */ + dwc_ddrphy_apb_wr(0x900da, 0); /* DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s0 */ + dwc_ddrphy_apb_wr(0xd0000, 1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + } +} + +int dwc_ddrphy_phyinit_userCustom_D_loadIMEM(struct sdrammc *sdrammc, const int train2D) +{ + u32 imem_ofst, imem_size; + u32 pb_type; + + if (IS_DDR4(sdrammc->type)) + pb_type = (train2D) ? PBT_DDR4_2D_PMU_TRAIN_IMEM : PBT_DDR4_PMU_TRAIN_IMEM; + else + pb_type = PBT_DDR5_PMU_TRAIN_IMEM; + + fmc_hdr_get_prebuilt(pb_type, &imem_ofst, &imem_size); + + memcpy(sdrammc->phy + (DWC_PHY_IMEM_OFST << 1), + (void *)(0x20000000 + imem_ofst), imem_size); + + return 0; +} + +int dwc_ddrphy_phyinit_userCustom_F_loadDMEM(struct sdrammc *sdrammc, + const int pState, const int train2D) +{ + u32 dmem_ofst, dmem_size; + u32 pb_type; + + if (IS_DDR4(sdrammc->type)) + pb_type = (train2D) ? PBT_DDR4_2D_PMU_TRAIN_DMEM : PBT_DDR4_PMU_TRAIN_DMEM; + else + pb_type = PBT_DDR5_PMU_TRAIN_DMEM; + + fmc_hdr_get_prebuilt(pb_type, &dmem_ofst, &dmem_size); + + memcpy(sdrammc->phy + (DWC_PHY_DMEM_OFST << 1), + (void *)(0x20000000 + dmem_ofst), dmem_size); + + return 0; +} + +static void sdrammc_dwc_phy_init(struct sdrammc *sdrammc) +{ + /* enable ddr phy free-run clock */ + writel(SCU0_CLKGATE1_CLR_DDRPHY, sdrammc->scu0 + SCU0_CLKGATE1_CLR); + + /* include the vendor-provided PHY init code */ + if (IS_DDR4(sdrammc->type)) { + #include "dwc_ddrphy_phyinit_ddr4-3200-nodimm-train2D.c" + } else { + #include "dwc_ddrphy_phyinit_ddr5-3200-nodimm-train2D.c" + } +} + +static void sdrammc_config_ac_timing(struct sdrammc *sdrammc) +{ + const struct sdrammc_ac_timing *ac = sdrammc->ac; + struct sdrammc_regs *regs = sdrammc->regs; + u32 actime; + +#define ACTIME1(ccd, rrd_l, rrd, mrd) \ + (((ccd) << 24) | \ + (((rrd_l) >> 1) << 16) | \ + (((rrd) >> 1) << 8) | \ + ((mrd) >> 1)) + +#define ACTIME2(faw, rp, ras, rcd) \ + ((((faw) >> 1) << 24) | \ + (((rp) >> 1) << 16) | \ + (((ras) >> 1) << 8) | \ + ((rcd) >> 1)) + +#define ACTIME3(wtr, rtw, wtp, rtp) \ + ((((wtr) >> 1) << 24) | \ + (((rtw) >> 1) << 16) | \ + (((wtp) >> 1) << 8) | \ + ((rtp) >> 1)) + +#define ACTIME4(wtr_a, wtr_l) \ + ((((wtr_a) >> 1) << 8) | \ + ((wtr_l) >> 1)) + +#define ACTIME5(refsbrd, rfcsb, rfc) \ + ((((refsbrd) >> 1) << 20) | \ + (((rfcsb) >> 1) << 10) | \ + ((rfc) >> 1)) + +#define ACTIME6(cshsr, pd, xp, cksre) \ + ((((cshsr) >> 1) << 24) | \ + (((pd) >> 1) << 16) | \ + (((xp) >> 1) << 8) | \ + ((cksre) >> 1)) + +#define ACTIME7(zqcs, dllk) \ + ((((zqcs) >> 1) << 10) | \ + ((dllk) >> 1)) + + actime = ACTIME1(ac->t_ccd_l, ac->t_rrd_l, ac->t_rrd, ac->t_mrd); + writel(actime, ®s->actime1); + + actime = ACTIME2(ac->t_faw, ac->t_rp, ac->t_ras, ac->t_rcd); + writel(actime, ®s->actime2); + + actime = ACTIME3(ac->t_cwl + ac->t_bl / 2 + ac->t_wtr, + ac->t_cl - ac->t_cwl + (ac->t_bl / 2) + 2, + ac->t_cwl + ac->t_bl / 2 + ac->t_wtp, + ac->t_rtp); + writel(actime, ®s->actime3); + + actime = ACTIME4(ac->t_cwl + ac->t_bl / 2 + ac->t_wtr_a, + ac->t_cwl + ac->t_bl / 2 + ac->t_wtr_l); + writel(actime, ®s->actime4); + + actime = ACTIME5(ac->t_refsbrd, ac->t_rfcsb, ac->t_rfc); + writel(actime, ®s->actime5); + + actime = ACTIME6(ac->t_cshsr, ac->t_pd, ac->t_xp, ac->t_cksre); + writel(actime, ®s->actime6); + + actime = ACTIME7(ac->t_zq, ac->t_dllk); + writel(actime, ®s->actime7); +} + +static void sdrammc_config_registers(struct sdrammc *sdrammc) +{ + const struct sdrammc_ac_timing *ac = sdrammc->ac; + struct sdrammc_regs *regs = sdrammc->regs; + u32 reg; + + u32 dram_size = 5; + u32 t_phy_wrdata; + u32 t_phy_wrlat; + u32 t_phy_rddata_en; + u32 t_phy_odtlat; + u32 t_phy_odtext; + + if (IS_DDR4(sdrammc->type)) { + t_phy_wrlat = ac->t_cwl - 5 - 4; + t_phy_rddata_en = ac->t_cl - 5 - 4; + t_phy_wrdata = 2; + t_phy_odtlat = ac->t_cwl - 5 - 4; + t_phy_odtext = 0; + } else { + t_phy_wrlat = ac->t_cwl - 13 - 3; + t_phy_rddata_en = ac->t_cl - 13 - 3; + t_phy_wrdata = 6; + t_phy_odtlat = 0; + t_phy_odtext = 0; + } + + writel(0x20 + (dram_size << 2) + !!!IS_DDR4(sdrammc->type), ®s->mcfg); + + reg = (t_phy_odtext << 20) + (t_phy_odtlat << 16) + + (t_phy_rddata_en << 10) + (t_phy_wrdata << 6) + + t_phy_wrlat; + writel(reg, ®s->dfi_timing); + writel(0, ®s->dctl); + + writel(0x40b48200, ®s->refctl); + + writel(0x42aa1800, ®s->zqctl); + + writel(0, ®s->arbctl); + + if (!IS_DDR4(sdrammc->type)) + writel(0, ®s->refmng_ctl); + + writel(0xffffffff, ®s->intr_mask); +} + +static void sdrammc_init(struct sdrammc *sdrammc) +{ + u32 reg; + + reg = readl(sdrammc->scu1 + SCU1_HWSTRAP1); + + if (reg & SCU1_HWSTRAP1_DDR4) { + if (IS_ENABLED(CONFIG_ASPEED_DDR_1600)) + sdrammc->type = DDR4_1600; + else if (IS_ENABLED(CONFIG_ASPEED_DDR_2400)) + sdrammc->type = DDR4_2400; + else if (IS_ENABLED(CONFIG_ASPEED_DDR_3200)) + sdrammc->type = DDR4_3200; + } else { + sdrammc->type = DDR5_3200; + } + + sdrammc->ac = &ac_table[sdrammc->type]; + + sdrammc_config_ac_timing(sdrammc); + sdrammc_config_registers(sdrammc); +} + +static int ast2700_sdrammc_probe(struct udevice *dev) +{ + struct sdrammc *sdrammc = dev_get_priv(dev); + struct sdrammc_regs *regs = sdrammc->regs; + u32 bistcfg; + u32 reg; + int rc; + + /* skip DRAM init if already done */ + reg = readl(sdrammc->scu0 + SCU0_VGA0_SCRATCH); + if (reg & SCU0_VGA0_SCRATCH_DRAM_INIT) + goto out; + + /* unlock DRAM controller */ + writel(DRAMC_UNLK_KEY, ®s->prot_key); + + sdrammc_init(sdrammc); + + sdrammc_dwc_phy_init(sdrammc); + + sdrammc_exit_self_refresh(sdrammc); + + sdrammc_config_mrs(sdrammc); + + sdrammc_enable_refresh(sdrammc); + + bistcfg = FIELD_PREP(DRAMC_BISTCFG_PMODE, BIST_PMODE_CRC) | + FIELD_PREP(DRAMC_BISTCFG_BMODE, BIST_BMODE_RW_SWITCH) | + DRAMC_BISTCFG_ENABLE; + + rc = sdrammc_bist(sdrammc, 0, 0x10000, bistcfg, 0x200000); + if (rc) { + debug("bist test failed, type=%d\n", sdrammc->type); + return rc; + } + + /* set DRAM init flag */ + reg |= SCU0_VGA0_SCRATCH_DRAM_INIT; + writel(reg, sdrammc->scu0 + SCU0_VGA0_SCRATCH); + +out: + sdrammc_calc_size(sdrammc); + + return 0; +} + +static int ast2700_sdrammc_of_to_plat(struct udevice *dev) +{ + struct sdrammc *sdrammc = dev_get_priv(dev); + u32 phandle; + ofnode node; + int rc; + + sdrammc->regs = (struct sdrammc_regs *)devfdt_get_addr_index(dev, 0); + if (sdrammc->regs == (void *)FDT_ADDR_T_NONE) { + debug("cannot map DRAM register\n"); + return -ENODEV; + } + + sdrammc->phy = (void *)devfdt_get_addr_index(dev, 1); + if (sdrammc->phy == (void *)FDT_ADDR_T_NONE) { + debug("cannot map PHY memory\n"); + return -ENODEV; + } + + rc = ofnode_read_u32(dev_ofnode(dev), "aspeed,scu0", &phandle); + if (rc) { + debug("cannot find SCU0 handle\n"); + return -ENODEV; + } + + node = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(node)) { + debug("cannot get SCU0 node\n"); + return -ENODEV; + } + + sdrammc->scu0 = (void *)ofnode_get_addr(node); + if (sdrammc->scu0 == (void *)FDT_ADDR_T_NONE) { + debug("cannot map SCU0 register\n"); + return -ENODEV; + } + + rc = ofnode_read_u32(dev_ofnode(dev), "aspeed,scu1", &phandle); + if (rc) { + debug("cannot find SCU1 handle\n"); + return -ENODEV; + } + + node = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(node)) { + debug("cannot get SCU1 node\n"); + return -ENODEV; + } + + sdrammc->scu1 = (void *)ofnode_get_addr(node); + if (sdrammc->scu1 == (void *)FDT_ADDR_T_NONE) { + debug("cannot map SCU1 register\n"); + return -ENODEV; + } + + return 0; +} + +static int ast2700_sdrammc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct sdrammc *sdrammc = dev_get_priv(dev); + + *info = sdrammc->info; + + return 0; +} + +static struct ram_ops ast2700_sdrammc_ops = { + .get_info = ast2700_sdrammc_get_info, +}; + +static const struct udevice_id ast2700_sdrammc_ids[] = { + { .compatible = "aspeed,ast2700-sdrammc" }, + { } +}; + +U_BOOT_DRIVER(sdrammc_ast2700) = { + .name = "aspeed_ast2700_sdrammc", + .id = UCLASS_RAM, + .of_match = ast2700_sdrammc_ids, + .ops = &ast2700_sdrammc_ops, + .of_to_plat = ast2700_sdrammc_of_to_plat, + .probe = ast2700_sdrammc_probe, + .priv_auto = sizeof(struct sdrammc), +}; diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c index e64354dd52f..3233ff80419 100644 --- a/drivers/remoteproc/rproc-uclass.c +++ b/drivers/remoteproc/rproc-uclass.c @@ -158,9 +158,19 @@ static int rproc_pre_probe(struct udevice *dev) uc_pdata->driver_plat_data = pdata->driver_plat_data; } - /* Else try using device Name */ - if (!uc_pdata->name) - uc_pdata->name = dev->name; + /* Else try using a combination of device Name and devices's parent's name */ + if (!uc_pdata->name) { + /* 2 in the rproc_name_size indicates 1 for null and one for '-' */ + int rproc_name_size = strlen(dev->name) + strlen(dev->parent->name) + 2; + char *buf; + + buf = malloc(rproc_name_size); + if (!buf) + return -ENOMEM; + + snprintf(buf, rproc_name_size, "%s-%s", dev->name, dev->parent->name); + uc_pdata->name = buf; + } if (!uc_pdata->name) { debug("Unnamed device!"); return -EINVAL; diff --git a/drivers/soc/qcom/cmd-db.c b/drivers/soc/qcom/cmd-db.c index 08736ea936a..67be18e89f4 100644 --- a/drivers/soc/qcom/cmd-db.c +++ b/drivers/soc/qcom/cmd-db.c @@ -6,6 +6,7 @@ #define pr_fmt(fmt) "cmd-db: " fmt +#include <asm/system.h> #include <dm.h> #include <dm/ofnode.h> #include <dm/device_compat.h> @@ -141,7 +142,7 @@ static int cmd_db_get_header(const char *id, const struct entry_header **eh, ent = rsc_to_entry_header(rsc_hdr); for (j = 0; j < le16_to_cpu(rsc_hdr->cnt); j++, ent++) { - if (memcmp(ent->id, query, sizeof(ent->id)) == 0) { + if (strncmp(ent->id, query, sizeof(ent->id)) == 0) { if (eh) *eh = ent; if (rh) @@ -182,9 +183,10 @@ u32 cmd_db_read_addr(const char *id) } EXPORT_SYMBOL_GPL(cmd_db_read_addr); -int cmd_db_bind(struct udevice *dev) +static int cmd_db_bind(struct udevice *dev) { void __iomem *base; + fdt_size_t size; ofnode node; if (cmd_db_header) @@ -194,12 +196,15 @@ int cmd_db_bind(struct udevice *dev) debug("%s(%s)\n", __func__, ofnode_get_name(node)); - base = (void __iomem *)ofnode_get_addr(node); + base = (void __iomem *)ofnode_get_addr_size(node, "reg", &size); if ((fdt_addr_t)base == FDT_ADDR_T_NONE) { log_err("%s: Failed to read base address\n", __func__); return -ENOENT; } + /* On SM8550/SM8650 and newer SoCs cmd-db might not be mapped */ + mmu_map_region((phys_addr_t)base, (phys_size_t)size, false); + cmd_db_header = base; if (!cmd_db_magic_matches(cmd_db_header)) { log_err("%s: Invalid Command DB Magic\n", __func__); diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index 61fb2e69558..aee9e55194e 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -294,6 +294,48 @@ static void __tcs_buffer_write(struct rsc_drv *drv, int tcs_id, int cmd_id, } /** + * __tcs_set_trigger() - Start xfer on a TCS or unset trigger on a borrowed TCS + * @drv: The controller. + * @tcs_id: The global ID of this TCS. + * @trigger: If true then untrigger/retrigger. If false then just untrigger. + * + * In the normal case we only ever call with "trigger=true" to start a + * transfer. That will un-trigger/disable the TCS from the last transfer + * then trigger/enable for this transfer. + * + * If we borrowed a wake TCS for an active-only transfer we'll also call + * this function with "trigger=false" to just do the un-trigger/disable + * before using the TCS for wake purposes again. + * + * Note that the AP is only in charge of triggering active-only transfers. + * The AP never triggers sleep/wake values using this function. + */ +static void __tcs_set_trigger(struct rsc_drv *drv, int tcs_id, bool trigger) +{ + u32 enable; + u32 reg = drv->regs[RSC_DRV_CONTROL]; + + /* + * HW req: Clear the DRV_CONTROL and enable TCS again + * While clearing ensure that the AMC mode trigger is cleared + * and then the mode enable is cleared. + */ + enable = read_tcs_reg(drv, reg, tcs_id); + enable &= ~TCS_AMC_MODE_TRIGGER; + write_tcs_reg_sync(drv, reg, tcs_id, enable); + enable &= ~TCS_AMC_MODE_ENABLE; + write_tcs_reg_sync(drv, reg, tcs_id, enable); + + if (trigger) { + /* Enable the AMC mode on the TCS and then trigger the TCS */ + enable = TCS_AMC_MODE_ENABLE; + write_tcs_reg_sync(drv, reg, tcs_id, enable); + enable |= TCS_AMC_MODE_TRIGGER; + write_tcs_reg(drv, reg, tcs_id, enable); + } +} + +/** * rpmh_rsc_send_data() - Write / trigger active-only message. * @drv: The controller. * @msg: The data to be sent. @@ -348,6 +390,7 @@ int rpmh_rsc_send_data(struct rsc_drv *drv, const struct tcs_request *msg) * of __tcs_set_trigger() below. */ __tcs_buffer_write(drv, tcs_id, 0, msg); + __tcs_set_trigger(drv, tcs_id, true); /* U-Boot: Now wait for the TCS to be cleared, indicating that we're done */ for (i = 0; i < USEC_PER_SEC; i++) { diff --git a/drivers/soc/ti/k3-navss-ringacc-u-boot.c b/drivers/soc/ti/k3-navss-ringacc-u-boot.c index f958239c2af..8227d8bc3e3 100644 --- a/drivers/soc/ti/k3-navss-ringacc-u-boot.c +++ b/drivers/soc/ti/k3-navss-ringacc-u-boot.c @@ -25,9 +25,16 @@ struct k3_nav_ring_cfg_regs { #define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_MASK GENMASK(26, 24) #define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT (24) +#define KNAV_RINGACC_CFG_RING_SIZE_MASK GENMASK(19, 0) + static void k3_ringacc_ring_reset_raw(struct k3_nav_ring *ring) { - writel(0, &ring->cfg->size); + u32 reg; + + reg = readl(&ring->cfg->size); + reg &= ~KNAV_RINGACC_CFG_RING_SIZE_MASK; + reg |= ring->size; + writel(reg, &ring->cfg->size); } static void k3_ringacc_ring_reconfig_qmode_raw(struct k3_nav_ring *ring, enum k3_nav_ring_mode mode) @@ -35,7 +42,7 @@ static void k3_ringacc_ring_reconfig_qmode_raw(struct k3_nav_ring *ring, enum k3 u32 val; val = readl(&ring->cfg->size); - val &= KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK; + val &= ~KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK; val |= mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT; writel(val, &ring->cfg->size); } diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c index b2643a30d3d..14114a65830 100644 --- a/drivers/soc/ti/k3-navss-ringacc.c +++ b/drivers/soc/ti/k3-navss-ringacc.c @@ -1028,8 +1028,8 @@ static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringa struct k3_nav_ringacc *k3_ringacc_dmarings_init(struct udevice *dev, struct k3_ringacc_init_data *data) { + void __iomem *base_rt, *base_cfg; struct k3_nav_ringacc *ringacc; - void __iomem *base_rt; int i; ringacc = devm_kzalloc(dev, sizeof(*ringacc), GFP_KERNEL); @@ -1047,6 +1047,20 @@ struct k3_nav_ringacc *k3_ringacc_dmarings_init(struct udevice *dev, if (!base_rt) return ERR_PTR(-EINVAL); + /* + * Since register property is defined as "ring" for PKTDMA and + * "cfg" for UDMA, configure base address of ring configuration + * register accordingly. + */ + base_cfg = dev_remap_addr_name(dev, "ring"); + pr_debug("ring %p\n", base_cfg); + if (!base_cfg) { + base_cfg = dev_remap_addr_name(dev, "cfg"); + pr_debug("cfg %p\n", base_cfg); + if (!base_cfg) + return ERR_PTR(-EINVAL); + } + ringacc->rings = devm_kzalloc(dev, sizeof(*ringacc->rings) * ringacc->num_rings * 2, @@ -1061,6 +1075,7 @@ struct k3_nav_ringacc *k3_ringacc_dmarings_init(struct udevice *dev, for (i = 0; i < ringacc->num_rings; i++) { struct k3_nav_ring *ring = &ringacc->rings[i]; + ring->cfg = base_cfg + KNAV_RINGACC_CFG_REGS_STEP * i; ring->rt = base_rt + K3_DMARING_RING_RT_REGS_STEP * i; ring->parent = ringacc; ring->ring_id = i; diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 6b1de82ae38..cb6fc0e7fda 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -106,6 +106,12 @@ config AST_TIMER This is mostly because they all share several registers which makes it difficult to completely separate them. +config AST_IBEX_TIMER + bool "Aspeed ast2700 Ibex timer" + depends on TIMER + help + Select this to enable a timer support for the Ibex RV32-based MCUs in AST2700. + config ATCPIT100_TIMER bool "ATCPIT100 timer support" depends on TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index fb95c8899e3..fec4af392e6 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_$(SPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_ARM_TWD_TIMER) += arm_twd_timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o +obj-$(CONFIG_AST_IBEX_TIMER) += ast_ibex_timer.o obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o obj-$(CONFIG_$(SPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o obj-$(CONFIG_$(SPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o diff --git a/drivers/timer/ast_ibex_timer.c b/drivers/timer/ast_ibex_timer.c new file mode 100644 index 00000000000..261839661e9 --- /dev/null +++ b/drivers/timer/ast_ibex_timer.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 Aspeed Technology Inc. + */ + +#include <asm/csr.h> +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <timer.h> + +#define CSR_MCYCLE 0xb00 +#define CSR_MCYCLEH 0xb80 + +static u64 ast_ibex_timer_get_count(struct udevice *dev) +{ + uint32_t cnt_l, cnt_h; + + cnt_l = csr_read(CSR_MCYCLE); + cnt_h = csr_read(CSR_MCYCLEH); + + return ((uint64_t)cnt_h << 32) | cnt_l; +} + +static int ast_ibex_timer_probe(struct udevice *dev) +{ + return 0; +} + +static const struct timer_ops ast_ibex_timer_ops = { + .get_count = ast_ibex_timer_get_count, +}; + +static const struct udevice_id ast_ibex_timer_ids[] = { + { .compatible = "aspeed,ast2700-ibex-timer" }, + { } +}; + +U_BOOT_DRIVER(ast_ibex_timer) = { + .name = "ast_ibex_timer", + .id = UCLASS_TIMER, + .of_match = ast_ibex_timer_ids, + .probe = ast_ibex_timer_probe, + .ops = &ast_ibex_timer_ops, +}; diff --git a/drivers/timer/npcm-timer.c b/drivers/timer/npcm-timer.c index 9463fd29ce8..5627c2331ca 100644 --- a/drivers/timer/npcm-timer.c +++ b/drivers/timer/npcm-timer.c @@ -3,93 +3,53 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ -#include <clk.h> #include <dm.h> #include <timer.h> #include <asm/io.h> -#define NPCM_TIMER_CLOCK_RATE 1000000UL /* 1MHz timer */ -#define NPCM_TIMER_INPUT_RATE 25000000UL /* Rate of input clock */ -#define NPCM_TIMER_TDR_MASK GENMASK(23, 0) -#define NPCM_TIMER_MAX_VAL NPCM_TIMER_TDR_MASK /* max counter value */ +#define NPCM_TIMER_CLOCK_RATE 25000000UL /* 25MHz */ /* Register offsets */ -#define TCR0 0x0 /* Timer Control and Status Register */ -#define TICR0 0x8 /* Timer Initial Count Register */ -#define TDR0 0x10 /* Timer Data Register */ +#define SECCNT 0x0 /* Seconds Counter Register */ +#define CNTR25M 0x4 /* 25MHz Counter Register */ -/* TCR fields */ -#define TCR_MODE_PERIODIC BIT(27) -#define TCR_EN BIT(30) -#define TCR_PRESCALE (NPCM_TIMER_INPUT_RATE / NPCM_TIMER_CLOCK_RATE - 1) - -enum input_clock_type { - INPUT_CLOCK_FIXED, /* input clock rate is fixed */ - INPUT_CLOCK_NON_FIXED -}; - -/** - * struct npcm_timer_priv - private data for npcm timer driver - * npcm timer is a 24-bits down-counting timer. - * - * @last_count: last hw counter value - * @counter: the value to be returned for get_count ops - */ struct npcm_timer_priv { void __iomem *base; - u32 last_count; - u64 counter; }; static u64 npcm_timer_get_count(struct udevice *dev) { struct npcm_timer_priv *priv = dev_get_priv(dev); - u32 val; + u64 reg_sec, reg_25m; + u64 counter; - /* The timer is counting down */ - val = readl(priv->base + TDR0) & NPCM_TIMER_TDR_MASK; - if (val <= priv->last_count) - priv->counter += priv->last_count - val; - else - priv->counter += priv->last_count + (NPCM_TIMER_MAX_VAL + 1 - val); - priv->last_count = val; + reg_sec = readl(priv->base + SECCNT); + reg_25m = readl(priv->base + CNTR25M); + /* + * When CNTR25M reaches 25M, it goes to 0 and SECCNT is increased by 1. + * When CNTR25M is zero, wait for CNTR25M to become non-zero in case + * SECCNT is not updated yet. + */ + if (reg_25m == 0) { + while (reg_25m == 0) + reg_25m = readl(priv->base + CNTR25M); + reg_sec = readl(priv->base + SECCNT); + } + counter = reg_sec * NPCM_TIMER_CLOCK_RATE + reg_25m; - return priv->counter; + return counter; } static int npcm_timer_probe(struct udevice *dev) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct npcm_timer_priv *priv = dev_get_priv(dev); - enum input_clock_type type = dev_get_driver_data(dev); - struct clk clk; - int ret; priv->base = dev_read_addr_ptr(dev); if (!priv->base) return -EINVAL; uc_priv->clock_rate = NPCM_TIMER_CLOCK_RATE; - if (type == INPUT_CLOCK_NON_FIXED) { - ret = clk_get_by_index(dev, 0, &clk); - if (ret < 0) - return ret; - - ret = clk_set_rate(&clk, NPCM_TIMER_INPUT_RATE); - if (ret < 0) - return ret; - } - - /* - * Configure timer and start - * periodic mode - * timer clock rate = input clock / prescale - */ - writel(0, priv->base + TCR0); - writel(NPCM_TIMER_MAX_VAL, priv->base + TICR0); - writel(TCR_EN | TCR_MODE_PERIODIC | TCR_PRESCALE, - priv->base + TCR0); - return 0; } @@ -98,8 +58,8 @@ static const struct timer_ops npcm_timer_ops = { }; static const struct udevice_id npcm_timer_ids[] = { - { .compatible = "nuvoton,npcm845-timer", .data = INPUT_CLOCK_FIXED}, - { .compatible = "nuvoton,npcm750-timer", .data = INPUT_CLOCK_NON_FIXED}, + { .compatible = "nuvoton,npcm845-timer"}, + { .compatible = "nuvoton,npcm750-timer"}, {} }; diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index 514c097591b..5d62eb475d0 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -842,9 +842,7 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found FIT\n"); - load.priv = header; - spl_set_bl_len(&load, 1); - load.read = sdp_load_read; + spl_load_init(&load, sdp_load_read, header, 1); spl_load_simple_fit(spl_image, &load, 0, header); @@ -855,9 +853,7 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, valid_container_hdr((void *)header)) { struct spl_load_info load; - load.priv = header; - spl_set_bl_len(&load, 1); - load.read = sdp_load_read; + spl_load_init(&load, sdp_load_read, header, 1); spl_load_imx_container(spl_image, &load, 0); return SDP_EXIT; } diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c index 23c3ed25554..1ae3619ce25 100644 --- a/drivers/usb/host/ehci-generic.c +++ b/drivers/usb/host/ehci-generic.c @@ -94,7 +94,7 @@ static int ehci_usb_probe(struct udevice *dev) if (err) goto reset_err; - err = generic_setup_phy(dev, &priv->phy, 0); + err = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0); if (err) goto regulator_err; diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c index ff336082e3a..a759aea9db3 100644 --- a/drivers/usb/host/ehci-msm.c +++ b/drivers/usb/host/ehci-msm.c @@ -80,7 +80,7 @@ static int ehci_usb_probe(struct udevice *dev) hcor = (struct ehci_hcor *)((phys_addr_t)hccr + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); - ret = generic_setup_phy(dev, &p->phy, 0); + ret = generic_setup_phy(dev, &p->phy, 0, PHY_MODE_USB_HOST, 0); if (ret) goto cleanup_iface; diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index 44912de7787..d8f521befe1 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -79,6 +79,10 @@ /* USB_CTRL_1 */ #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) +#ifndef CFG_MXC_USB_PORTSC +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + int mxc_set_usbcontrol(int port, unsigned int flags) { unsigned int v; diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 31cd8a50f4a..a93fa5d5455 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -703,7 +703,7 @@ static int ehci_usb_probe(struct udevice *dev) usb_phy_enable(ehci, priv->phy_addr); #endif #else - ret = generic_setup_phy(dev, &priv->phy, 0); + ret = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0); if (ret) goto err_regulator; #endif diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 572686580cd..8d05b14e898 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -30,7 +30,7 @@ static int ehci_pci_init(struct udevice *dev, struct ehci_hccr **ret_hccr, int ret; u32 cmd; - ret = generic_setup_phy(dev, &priv->phy, 0); + ret = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0); if (ret) return ret; diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c index f1325cd4953..cc44226f5e0 100644 --- a/drivers/usb/host/ohci-generic.c +++ b/drivers/usb/host/ohci-generic.c @@ -50,7 +50,7 @@ static int ohci_usb_probe(struct udevice *dev) goto reset_err; } - err = generic_setup_phy(dev, &priv->phy, 0); + err = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0); if (err) goto reset_err; diff --git a/drivers/usb/musb-new/ux500.c b/drivers/usb/musb-new/ux500.c index 89dd75b7d05..be0085f403d 100644 --- a/drivers/usb/musb-new/ux500.c +++ b/drivers/usb/musb-new/ux500.c @@ -169,16 +169,14 @@ U_BOOT_DRIVER(ux500_musb) = { .name = "ux500-musb", #ifdef CONFIG_USB_MUSB_HOST .id = UCLASS_USB, + .ops = &musb_usb_ops, #else .id = UCLASS_USB_GADGET_GENERIC, + .ops = &ux500_gadget_ops, #endif .of_match = ux500_musb_ids, - .ops = &ux500_gadget_ops, .probe = ux500_musb_probe, .remove = ux500_musb_remove, -#ifdef CONFIG_USB_MUSB_HOST - .ops = &musb_usb_ops, -#endif .plat_auto = sizeof(struct usb_plat), .priv_auto = sizeof(struct ux500_glue), }; diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c index 039b22086a9..fdeb3cabea7 100644 --- a/drivers/video/imx/mxc_ipuv3_fb.c +++ b/drivers/video/imx/mxc_ipuv3_fb.c @@ -403,7 +403,6 @@ static int mxcfb_map_video_memory(struct fb_info *fbi) (uint32_t) fbi->fix.smem_start, fbi->fix.smem_len); fbi->screen_size = fbi->fix.smem_len; - gd->fb_base = fbi->fix.smem_start; /* Clear the screen */ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); @@ -633,7 +632,6 @@ static int ipuv3_video_probe(struct udevice *dev) mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, DCACHE_WRITEBACK); video_set_flush_dcache(dev, true); - gd->fb_base = fb_start; return 0; } diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 792d6314d15..e72839cead4 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -335,7 +335,6 @@ static int mxs_video_probe(struct udevice *dev) mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, DCACHE_WRITEBACK); video_set_flush_dcache(dev, true); - gd->fb_base = plat->base; return ret; } diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index a5aa8dd5295..41bb7647fda 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -145,13 +145,26 @@ int video_reserve(ulong *addrp) *addrp -= CONFIG_VAL(VIDEO_PCI_DEFAULT_FB_SIZE); gd->video_bottom = *addrp; - gd->fb_base = *addrp; debug("Video frame buffers from %lx to %lx\n", gd->video_bottom, gd->video_top); return 0; } +ulong video_get_fb(void) +{ + struct udevice *dev; + + uclass_find_first_device(UCLASS_VIDEO, &dev); + if (dev) { + const struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); + + return uc_plat->base; + } + + return 0; +} + int video_fill_part(struct udevice *dev, int xstart, int ystart, int xend, int yend, u32 colour) { @@ -210,7 +223,6 @@ int video_reserve_from_bloblist(struct video_handoff *ho) return -ENOENT; gd->video_bottom = ho->fb; - gd->fb_base = ho->fb; gd->video_top = ho->fb + ho->size; debug("%s: Reserving %lx bytes at %08x as per bloblist received\n", __func__, (unsigned long)ho->size, (u32)ho->fb); diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c index 1405b29cb8b..76abfeac443 100644 --- a/drivers/video/zynqmp/zynqmp_dpsub.c +++ b/drivers/video/zynqmp/zynqmp_dpsub.c @@ -49,7 +49,7 @@ static void dma_init_video_descriptor(struct udevice *dev) DPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT) | (upper_32_bits((u64)&cur_desc))); cur_desc.next_desr = lower_32_bits((u64)&cur_desc); - cur_desc.src_addr = lower_32_bits((u64)gd->fb_base); + cur_desc.src_addr = lower_32_bits((u64)video_get_fb()); } static void dma_set_descriptor_address(struct udevice *dev) @@ -2134,7 +2134,6 @@ static int zynqmp_dpsub_probe(struct udevice *dev) dev_dbg(dev, "BPP in bits %d, bpix %d\n", priv->non_live_graphics->bpp, uc_priv->bpix); - uc_priv->fb = (void *)gd->fb_base; uc_priv->xsize = vidc_video_timing_modes[priv->video_mode].video_timing.h_active; uc_priv->ysize = vidc_video_timing_modes[priv->video_mode].video_timing.v_active; /* Calculated by core but need it for my own setup */ diff --git a/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi b/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi index 3c45782ab2b..96378b19c41 100644 --- a/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi @@ -128,6 +128,10 @@ }; }; +&phy_gmii_sel { + bootph-all; +}; + &main_pmx0 { /* First pad number is ALW package and second is AMC package */ main_uart0_pins_default: main-uart0-default-pins { @@ -16,7 +16,7 @@ #include <spi_flash.h> #include <search.h> #include <errno.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <asm/cache.h> #include <asm/global_data.h> #include <dm/device-internal.h> diff --git a/fs/btrfs/btrfs.c b/fs/btrfs/btrfs.c index 1149a3b2007..350cff0cbca 100644 --- a/fs/btrfs/btrfs.c +++ b/fs/btrfs/btrfs.c @@ -7,7 +7,7 @@ #include <config.h> #include <malloc.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <linux/time.h> #include "btrfs.h" #include "crypto/hash.h" diff --git a/fs/btrfs/compat.h b/fs/btrfs/compat.h index 02173dea5f4..4596b9d1dd3 100644 --- a/fs/btrfs/compat.h +++ b/fs/btrfs/compat.h @@ -5,7 +5,7 @@ #include <linux/errno.h> #include <fs_internal.h> -#include <uuid.h> +#include <u-boot/uuid.h> /* Provide a compatibility layer to make code syncing easier */ diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index 34d9d535121..14efe7218df 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ #include <fs_internal.h> #include <log.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <memalign.h> #include "kernel-shared/btrfs_tree.h" #include "common/rbtree-utils.h" diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index da59cb008fc..15587e92e3e 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -27,7 +27,7 @@ #include <div64.h> #include <malloc.h> #include <part.h> -#include <uuid.h> +#include <u-boot/uuid.h> int ext4fs_symlinknest; struct ext_filesystem ext_fs; @@ -526,12 +526,11 @@ int fs_size(const char *filename, loff_t *size) return ret; } -#ifdef CONFIG_LMB +#if CONFIG_IS_ENABLED(LMB) /* Check if a file may be read to the given address */ static int fs_read_lmb_check(const char *filename, ulong addr, loff_t offset, loff_t len, struct fstype_info *info) { - struct lmb lmb; int ret; loff_t size; loff_t read_len; @@ -550,10 +549,9 @@ static int fs_read_lmb_check(const char *filename, ulong addr, loff_t offset, if (len && len < read_len) read_len = len; - lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); - lmb_dump_all(&lmb); + lmb_dump_all(); - if (lmb_alloc_addr(&lmb, addr, read_len) == addr) + if (lmb_alloc_addr(addr, read_len) == addr) return 0; log_err("** Reading file would overwrite reserved memory **\n"); @@ -568,7 +566,7 @@ static int _fs_read(const char *filename, ulong addr, loff_t offset, loff_t len, void *buf; int ret; -#ifdef CONFIG_LMB +#if CONFIG_IS_ENABLED(LMB) if (do_lmb_check) { ret = fs_read_lmb_check(filename, addr, offset, len, info); if (ret) diff --git a/fs/yaffs2/yaffs_guts.c b/fs/yaffs2/yaffs_guts.c index e89d02513c1..c20f2f8298f 100644 --- a/fs/yaffs2/yaffs_guts.c +++ b/fs/yaffs2/yaffs_guts.c @@ -4452,13 +4452,12 @@ loff_t yaffs_get_obj_length(struct yaffs_obj *obj) int yaffs_get_obj_link_count(struct yaffs_obj *obj) { int count = 0; - struct list_head *i; if (!obj->unlinked) count++; /* the object itself */ - list_for_each(i, &obj->hard_links) - count++; /* add the hard links; */ + /* add the hard links; */ + count += list_count_nodes(&obj->hard_links); return count; } diff --git a/include/alist.h b/include/alist.h index 586a1efa5c8..68d268f01af 100644 --- a/include/alist.h +++ b/include/alist.h @@ -83,6 +83,17 @@ static inline bool alist_err(struct alist *lst) } /** + * alist_full() - Check if the alist is full + * + * @lst: List to check + * Return: true if full, false otherwise + */ +static inline bool alist_full(struct alist *lst) +{ + return lst->count == lst->alloc; +} + +/** * alist_get_ptr() - Get the value of a pointer * * @lst: alist to check diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 19c66e1fe5d..d6c15e2c406 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -20,6 +20,7 @@ */ #ifndef __ASSEMBLY__ +#include <board_f.h> #include <cyclic.h> #include <event_internal.h> #include <fdtdec.h> @@ -43,38 +44,140 @@ struct global_data { */ struct bd_info *bd; /** + * @new_gd: pointer to relocated global data + */ + struct global_data *new_gd; + /** + * @fdt_blob: U-Boot's own device tree, NULL if none + */ + const void *fdt_blob; + /** + * @cur_serial_dev: current serial device + */ + struct udevice *cur_serial_dev; +#ifndef CONFIG_SPL_BUILD + /** + * @jt: jump table + * + * The jump table contains pointers to exported functions. A pointer to + * the jump table is passed to standalone applications. + */ + struct jt_funcs *jt; + /** + * @boardf: information only used before relocation + */ + struct board_f *boardf; +#endif + /** + * @ram_size: RAM size in bytes + */ + phys_size_t ram_size; + /** + * @ram_top: top address of RAM used by U-Boot + */ + phys_addr_t ram_top; + /** * @flags: global data flags * * See &enum gd_flags */ unsigned long flags; /** + * @cpu_clk: CPU clock rate in Hz + */ + unsigned long cpu_clk; +#if CONFIG_IS_ENABLED(ENV_SUPPORT) + /** + * @env_addr: address of environment structure + * + * @env_addr contains the address of the structure holding the + * environment variables. + */ + unsigned long env_addr; +#endif /* ENV_SUPPORT */ + /** + * @ram_base: base address of RAM used by U-Boot + */ + unsigned long ram_base; + /** + * @relocaddr: start address of U-Boot in RAM + * + * After relocation this field indicates the address to which U-Boot + * has been relocated. It can be displayed using the bdinfo command. + * Its value is needed to display the source code when debugging with + * GDB using the 'add-symbol-file u-boot <relocaddr>' command. + */ + unsigned long relocaddr; + /** + * @irq_sp: IRQ stack pointer + */ + unsigned long irq_sp; + /** + * @start_addr_sp: initial stack pointer address + */ + unsigned long start_addr_sp; + /** + * @reloc_off: relocation offset + */ + unsigned long reloc_off; + /** + * @bus_clk: platform clock rate in Hz + */ + unsigned int bus_clk; + /** + * @mem_clk: memory clock rate in Hz + */ + unsigned int mem_clk; + /** + * @mon_len: monitor length in bytes + */ + unsigned int mon_len; + /** * @baudrate: baud rate of the serial interface */ unsigned int baudrate; +#if CONFIG_IS_ENABLED(ENV_SUPPORT) /** - * @cpu_clk: CPU clock rate in Hz + * @env_has_init: bit mask indicating environment locations + * + * &enum env_location defines which bit relates to which location */ - unsigned long cpu_clk; + unsigned short env_has_init; /** - * @bus_clk: platform clock rate in Hz + * @env_valid: environment is valid + * + * See &enum env_valid */ - unsigned long bus_clk; + unsigned char env_valid; /** - * @pci_clk: PCI clock rate in Hz + * @env_load_prio: priority of the loaded environment */ - /* We cannot bracket this with CONFIG_PCI due to mpc5xxx */ - unsigned long pci_clk; + char env_load_prio; /** - * @mem_clk: memory clock rate in Hz + * @env_buf: buffer for env_get() before reloc */ - unsigned long mem_clk; -#if CONFIG_IS_ENABLED(VIDEO) + char env_buf[32]; +#endif /* ENV_SUPPORT */ /** - * @fb_base: base address of frame buffer memory + * @fdt_src: Source of FDT */ - unsigned long fb_base; -#endif + enum fdt_source_t fdt_src; + /** + * @arch: architecture-specific data + */ + struct arch_global_data arch; + /** + * @dmtag_list: List of DM tags + */ + struct list_head dmtag_list; + /** + * @timebase_h: high 32 bits of timer + */ + unsigned int timebase_h; + /** + * @timebase_l: low 32 bits of timer + */ + unsigned int timebase_l; #if defined(CONFIG_POST) /** * @post_log_word: active POST tests @@ -104,15 +207,6 @@ struct global_data { */ unsigned long board_type; #endif - /** - * @have_console: console is available - * - * A value of 1 indicates that serial_init() was called and a console - * is available. - * A value of 0 indicates that console input and output drivers shall - * not be called. - */ - unsigned long have_console; #if CONFIG_IS_ENABLED(PRE_CONSOLE_BUFFER) /** * @precon_buf_idx: pre-console buffer index @@ -126,71 +220,6 @@ struct global_data { */ long precon_buf_idx; #endif - /** - * @env_addr: address of environment structure - * - * @env_addr contains the address of the structure holding the - * environment variables. - */ - unsigned long env_addr; - /** - * @env_valid: environment is valid - * - * See &enum env_valid - */ - unsigned long env_valid; - /** - * @env_has_init: bit mask indicating environment locations - * - * &enum env_location defines which bit relates to which location - */ - unsigned long env_has_init; - /** - * @env_load_prio: priority of the loaded environment - */ - int env_load_prio; - /** - * @ram_base: base address of RAM used by U-Boot - */ - unsigned long ram_base; - /** - * @ram_top: top address of RAM used by U-Boot - */ - phys_addr_t ram_top; - /** - * @relocaddr: start address of U-Boot in RAM - * - * After relocation this field indicates the address to which U-Boot - * has been relocated. It can be displayed using the bdinfo command. - * Its value is needed to display the source code when debugging with - * GDB using the 'add-symbol-file u-boot <relocaddr>' command. - */ - unsigned long relocaddr; - /** - * @ram_size: RAM size in bytes - */ - phys_size_t ram_size; - /** - * @mon_len: monitor length in bytes - */ - unsigned long mon_len; - /** - * @irq_sp: IRQ stack pointer - */ - unsigned long irq_sp; - /** - * @start_addr_sp: initial stack pointer address - */ - unsigned long start_addr_sp; - /** - * @reloc_off: relocation offset - */ - unsigned long reloc_off; - /** - * @new_gd: pointer to relocated global data - */ - struct global_data *new_gd; - #ifdef CONFIG_DM /** * @dm_root: root instance for Driver Model @@ -235,46 +264,18 @@ struct global_data { */ struct udevice *timer; #endif - /** - * @fdt_blob: U-Boot's own device tree, NULL if none - */ - const void *fdt_blob; - /** - * @new_fdt: relocated device tree - */ - void *new_fdt; - /** - * @fdt_size: space reserved for relocated device space - */ - unsigned long fdt_size; - /** - * @fdt_src: Source of FDT - */ - enum fdt_source_t fdt_src; #if CONFIG_IS_ENABLED(OF_LIVE) /** * @of_root: root node of the live tree */ struct device_node *of_root; #endif - #if CONFIG_IS_ENABLED(MULTI_DTB_FIT) /** * @multi_dtb_fit: pointer to uncompressed multi-dtb FIT image */ const void *multi_dtb_fit; #endif - /** - * @jt: jump table - * - * The jump table contains pointers to exported functions. A pointer to - * the jump table is passed to standalone applications. - */ - struct jt_funcs *jt; - /** - * @env_buf: buffer for env_get() before reloc - */ - char env_buf[32]; #ifdef CONFIG_TRACE /** * @trace_buff: trace buffer @@ -290,18 +291,10 @@ struct global_data { */ int cur_i2c_bus; #endif - /** - * @timebase_h: high 32 bits of timer - */ - unsigned int timebase_h; - /** - * @timebase_l: low 32 bits of timer - */ - unsigned int timebase_l; +#if CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA) /** * @malloc_start: start of malloc() region */ -#if CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA) unsigned long malloc_start; #endif #if CONFIG_IS_ENABLED(SYS_MALLOC_F) @@ -310,43 +303,14 @@ struct global_data { */ unsigned long malloc_base; /** - * @malloc_limit: limit address of early malloc() + * @malloc_limit: maximum size of early malloc() */ - unsigned long malloc_limit; + unsigned int malloc_limit; /** - * @malloc_ptr: current address of early malloc() + * @malloc_ptr: currently used bytes of early malloc() */ - unsigned long malloc_ptr; + unsigned int malloc_ptr; #endif -#ifdef CONFIG_PCI - /** - * @hose: PCI hose for early use - */ - struct pci_controller *hose; - /** - * @pci_ram_top: top of region accessible to PCI - */ - phys_addr_t pci_ram_top; -#endif -#ifdef CONFIG_PCI_BOOTDELAY - /** - * @pcidelay_done: delay time before scanning of PIC hose expired - * - * If CONFIG_PCI_BOOTDELAY=y, pci_hose_scan() waits for the number of - * milliseconds defined by environment variable pcidelay before - * scanning. Once this delay has expired the flag @pcidelay_done - * is set to 1. - */ - int pcidelay_done; -#endif - /** - * @cur_serial_dev: current serial device - */ - struct udevice *cur_serial_dev; - /** - * @arch: architecture-specific data - */ - struct arch_global_data arch; #ifdef CONFIG_CONSOLE_RECORD /** * @console_out: output buffer for console recording @@ -377,13 +341,19 @@ struct global_data { * @bootstage: boot stage information */ struct bootstage_data *bootstage; - /** - * @new_bootstage: relocated boot stage information - */ - struct bootstage_data *new_bootstage; #endif #ifdef CONFIG_LOG /** + * @log_head: list of logging devices + */ + struct list_head log_head; + /** + * @log_fmt: bit mask for logging format + * + * The @log_fmt bit mask selects the fields to be shown in log messages. + * &enum log_fmt defines the bits of the bit mask. + */ + /** * @log_drop_count: number of dropped log messages * * This counter is incremented for each log message which can not @@ -397,60 +367,39 @@ struct global_data { * For logging devices without filters @default_log_level defines the * logging level, cf. &enum log_level_t. */ - int default_log_level; - /** - * @log_head: list of logging devices - */ - struct list_head log_head; - /** - * @log_fmt: bit mask for logging format - * - * The @log_fmt bit mask selects the fields to be shown in log messages. - * &enum log_fmt defines the bits of the bit mask. - */ - int log_fmt; - - /** - * @processing_msg: a log message is being processed - * - * This flag is used to suppress the creation of additional messages - * while another message is being processed. - */ - bool processing_msg; + char default_log_level; + char log_fmt; /** * @logc_prev: logging category of previous message * * This value is used as logging category for continuation messages. */ - int logc_prev; + unsigned char logc_prev; /** * @logl_prev: logging level of the previous message * * This value is used as logging level for continuation messages. */ - int logl_prev; + unsigned char logl_prev; /** * @log_cont: Previous log line did not finished wtih \n * * This allows for chained log messages on the same line */ bool log_cont; + /** + * @processing_msg: a log message is being processed + * + * This flag is used to suppress the creation of additional messages + * while another message is being processed. + */ + bool processing_msg; #endif #if CONFIG_IS_ENABLED(BLOBLIST) /** * @bloblist: blob list information */ struct bloblist_hdr *bloblist; - /** - * @new_bloblist: relocated blob list information - */ - struct bloblist_hdr *new_bloblist; -#endif -#if CONFIG_IS_ENABLED(HANDOFF) - /** - * @spl_handoff: SPL hand-off information - */ - struct spl_handoff *spl_handoff; #endif #if defined(CONFIG_TRANSLATION_OFFSET) /** @@ -488,10 +437,6 @@ struct global_data { */ struct hlist_head cyclic_list; #endif - /** - * @dmtag_list: List of DM tags - */ - struct list_head dmtag_list; #if CONFIG_IS_ENABLED(UPL) /** * @upl: Universal Payload-handoff information @@ -585,12 +530,6 @@ static_assert(sizeof(struct global_data) == GD_SIZE); #define gd_set_malloc_start(val) #endif -#if CONFIG_IS_ENABLED(PCI) -#define gd_set_pci_ram_top(val) gd->pci_ram_top = val -#else -#define gd_set_pci_ram_top(val) -#endif - #if CONFIG_VAL(SYS_MALLOC_F_LEN) #define gd_malloc_ptr() gd->malloc_ptr #else @@ -720,6 +659,12 @@ enum gd_flags { * @GD_FLG_UPL: Read/write a Universal Payload (UPL) handoff */ GD_FLG_UPL = 0x4000000, + /** + * @GD_FLG_HAVE_CONSOLE: serial_init() was called and a console + * is available. When not set, indicates that console input and output + * drivers shall not be called. + */ + GD_FLG_HAVE_CONSOLE = 0x8000000, }; #endif /* __ASSEMBLY__ */ diff --git a/include/blk.h b/include/blk.h index 7c7cf7f2b10..1fc9a5b8471 100644 --- a/include/blk.h +++ b/include/blk.h @@ -650,7 +650,7 @@ struct blk_driver *blk_driver_lookup_type(int uclass_id); struct blk_desc *blk_get_devnum_by_uclass_id(enum uclass_id uclass_id, int devnum); /** - * blk_get_devnum_by_uclass_id() - Get a block device by type name, and number + * blk_get_devnum_by_uclass_idname() - Get block device by type name and number * * This looks up the block device type based on @uclass_idname, then calls * blk_get_devnum_by_uclass_id(). @@ -660,7 +660,7 @@ struct blk_desc *blk_get_devnum_by_uclass_id(enum uclass_id uclass_id, int devnu * Return: point to block device descriptor, or NULL if not found */ struct blk_desc *blk_get_devnum_by_uclass_idname(const char *uclass_idname, - int devnum); + int devnum); /** * blk_dselect_hwpart() - select a hardware partition diff --git a/include/board_f.h b/include/board_f.h new file mode 100644 index 00000000000..05aa51510c2 --- /dev/null +++ b/include/board_f.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2024 Google LLC + * Written by: Simon Glass <sjg@chromeium.org> + */ + +#ifndef __BOARD_F +#define __BOARD_F + +/** + * struct board_f: Information used only before relocation + * + * This struct is set up in board_init_f() and used to deal with relocation. It + * is not available after relocation. + */ +struct board_f { + /** + * @new_fdt: relocated device tree + */ + void *new_fdt; + /** + * @fdt_size: space reserved for relocated device space + */ + unsigned long fdt_size; + /** + * @new_bootstage: relocated boot stage information + */ + struct bootstage_data *new_bootstage; + /** + * @new_bloblist: relocated blob list information + */ + struct bloblist_hdr *new_bloblist; +}; + +#endif diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 6fd43511ee4..e5df82c6830 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -23,11 +23,6 @@ /* Network */ -/* USB Configs */ -/* Host */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* Framebuffer and LCD */ /* Command definition */ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 9d4a4bbdf43..8a66b1275df 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -411,10 +411,6 @@ /* DMA stuff, needed for GPMI/MXS NAND support */ -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* UBI support */ #define CFG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index b9cc7ba974d..b75db7e7bac 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -35,11 +35,7 @@ #define CFG_SYS_SDRAM_SIZE 0x04000000 #define CFG_SYS_INIT_RAM_SIZE (16 * 1024) -#ifdef CONFIG_AT91SAM9XE -# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM -#else -# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 -#endif +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 38c98c5e21c..d01f0d37316 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -78,7 +78,4 @@ BUR_COMMON_ENV \ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - #endif /* __CONFIG_BRPP2_IMX6_H */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 280ae1e9cca..8c363137b4f 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -95,8 +95,4 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #endif -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #endif /* __CONFIG_H */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 7d0f2b6dc13..f7fd4c517b4 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -134,10 +134,6 @@ /* Ethernet */ #define CFG_FEC_MXC_PHYADDR 0 -/* USB */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* Boot */ #define CFG_SYS_BOOTMAPSZ (8 << 20) diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 8860ceec1a0..26b29bad6a1 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -117,11 +117,6 @@ #define CFG_SYS_NAND_BASE -1 #endif -/* USB Configs */ - -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* USB Device Firmware Update support */ #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 79e5b870b81..664b7c8ce0c 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -21,11 +21,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_SYS_FSL_USDHC_NUM 2 -/* USB Configs */ -/* Host */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* Command definition */ #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 33133a0b96e..c340dfb1189 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -159,9 +159,4 @@ #define CFG_SYS_NAND_BASE 0x40000000 #endif -/* USB Configs */ - -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #endif diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index c5781670864..2b329b4065c 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -46,10 +46,6 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 4b5ef4ad510..9b6f03f6856 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -30,10 +30,6 @@ /* UART */ #define CFG_MXC_UART_BASE UART1_BASE -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* USB Gadget (DFU, UMS) */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/display5.h b/include/configs/display5.h index 2005a256d6e..51fa2b03a2e 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -287,5 +287,4 @@ /* The 0x120000 value corresponds to above SPI-NOR memory MAP */ #endif -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 31c7e104f6b..61c0d755a8d 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -17,10 +17,6 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h deleted file mode 100644 index c327bbbe07d..00000000000 --- a/include/configs/ethernut5.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * egnite GmbH <info@egnite.de> - * - * Configuation settings for Ethernut 5 with AT91SAM9XE. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/hardware.h> - -/* The first stage boot loader expects u-boot running at this address. */ - -/* The first stage boot loader takes care of low level initialization. */ - -/* CPU information */ - -/* ARM asynchronous clock */ -#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ - -/* 32kB internal SRAM */ -#define CFG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */ -#define CFG_SYS_INIT_RAM_SIZE (32 << 10) - -/* 128MB SDRAM in 1 bank */ -#define CFG_SYS_SDRAM_BASE 0x20000000 -#define CFG_SYS_SDRAM_SIZE (128 << 20) - -/* 512kB on-chip NOR flash */ -# define CFG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ - -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CFG_SYS_NAND_BASE 0x40000000 -/* our ALE is AD21 */ -#define CFG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CFG_SYS_NAND_MASK_CLE (1 << 22) -#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) -#endif - -/* JFFS2 */ - -/* Ethernet */ -#define CFG_PHY_ID 0 - -/* MMC */ -#ifdef CONFIG_CMD_MMC -#define CFG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 -#endif - -/* RTC */ -#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) -#define CFG_SYS_I2C_RTC_ADDR 0x51 -#endif - -#define I2C_SOFT_DECLARATIONS - -#define GPIO_I2C_SCL AT91_PIO_PORTA, 24 -#define GPIO_I2C_SDA AT91_PIO_PORTA, 23 - -#define I2C_INIT { \ - at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \ - at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ - at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \ - at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \ - at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ -} - -#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0) -#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0) -#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) -#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit) -#define I2C_DELAY udelay(100) -#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) - -/* File systems */ - -/* Boot command */ - -/* Misc. u-boot settings */ - -#endif diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 49b058cb10d..f3d85c9c11e 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -23,10 +23,6 @@ #define CONSOLE_DEVICE "ttymxc2" /* Base board debug connector */ #endif -/* USB */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* Memory */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index ebc5d03d0d5..acfb5135dbe 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -6,55 +6,22 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* SPL */ -/* Location in NAND to read U-Boot from */ - -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ - #include "mx6_common.h" /* Serial */ #define CFG_MXC_UART_BASE UART2_BASE -/* NAND */ - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -/* - * PCI express - */ - -/* - * PMIC - */ +/* PMIC */ #define CFG_POWER_PFUZE100_I2C_ADDR 0x08 #define CFG_POWER_LTC3676_I2C_ADDR 0x3c -/* Various command support */ - -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - -/* Miscellaneous configurable options */ - -/* Memory configuration */ - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* - * MTD Command for mtdparts - */ - -/* Persistent Environment Config */ - -/* Environment */ - #endif /* __CONFIG_H */ diff --git a/include/configs/ibex_ast2700.h b/include/configs/ibex_ast2700.h new file mode 100644 index 00000000000..0f6850f7240 --- /dev/null +++ b/include/configs/ibex_ast2700.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_SDRAM_BASE 0x80000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 66004a6eb2a..75997469cd9 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -114,12 +114,6 @@ #define CFG_SYS_NAND_BASE 0x40000000 #define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - /* Falcon Mode */ /* Falcon Mode - MMC support: args@1MB kernel@2MB */ diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index 6c61b3f4480..8abb58b0691 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -42,10 +42,6 @@ /* Ethernet */ #define CFG_FEC_MXC_PHYADDR 1 -/* USB */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - /* Falcon */ /* MMC support: args@1MB kernel@2MB */ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 2c998cdcfc7..fab5063b73f 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -110,7 +110,5 @@ #endif #endif -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 #endif /* __IMX6Q_ACC_H */ diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 131f18290b9..36c4c5b8b50 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -77,7 +77,4 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CFG_SYS_FSL_USDHC_NUM 2 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - #endif /* __CONFIG_H */ diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 6442e3d570f..146f7945719 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -137,7 +137,4 @@ #define CFG_FEC_MXC_PHYADDR -1 /* Auto search of PHY on MII */ -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - #endif /*__IMX8MM_CL_IOT_GATE_H*/ diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index 1c92cd78767..015df01db4e 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -24,11 +24,6 @@ /* Board and environment settings */ #define CFG_MXC_UART_BASE UART4_BASE -#ifdef CONFIG_USB_EHCI_HCD -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - /* Boot order for distro boot */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index eee3d2ddb03..3a129c5cce7 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -24,11 +24,6 @@ /* Board and environment settings */ -#ifdef CONFIG_USB_EHCI_HCD -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - /* GUID for capsule updatable firmware image */ #define KONTRON_SL_MX8MM_FIT_IMAGE_GUID \ EFI_GUID(0xd488e45a, 0x4929, 0x4b55, 0x8c, 0x14, \ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index 6e383cbe75f..78c6c67ab99 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -11,7 +11,6 @@ #include <linux/sizes.h> /* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CFG_MXC_USB_FLAGS 0 /* Command definition */ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 1aa4b8ab598..c0cb3db23e7 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -16,12 +16,6 @@ /* FEC ethernet */ -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ "fdt_addr=0x18000000\0" \ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 5811059c8e2..fc6bc6b28ba 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -93,12 +93,6 @@ /* FLASH and environment organization */ -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - #ifdef CONFIG_CMD_NET #define CFG_FEC_ENET_DEV 0 diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index c245cbe427b..1ea4fa59fd5 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -68,8 +68,6 @@ * USB */ #ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORT 1 -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CFG_MXC_USB_FLAGS 0 #endif diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index 6ffc1282411..8e248177b1c 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -23,7 +23,4 @@ /* Environment configs */ -/* USB configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - #endif diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index dff54d04a67..6c8cb78274b 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -33,7 +33,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR /* USB Configs */ -#define CFG_MXC_USB_PORT 1 #define CFG_MXC_USB_PORTSC PORT_PTS_ULPI #define CFG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index dccfdc3a15d..70aa140036f 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -22,8 +22,6 @@ /* bootz: zImage/initrd.img support */ /* USB Configs */ -#define CFG_MXC_USB_PORT 1 -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CFG_MXC_USB_FLAGS 0 /* Command definition */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 7398804e6b5..14095b99f03 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -17,8 +17,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 /* USB Configs */ -#define CFG_MXC_USB_PORT 1 -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CFG_MXC_USB_FLAGS 0 /* PMIC Controller */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index df65dbeea41..6d1f669de50 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -12,8 +12,6 @@ #include <asm/arch/imx-regs.h> /* USB Configs */ -#define CFG_MXC_USB_PORT 1 -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CFG_MXC_USB_FLAGS 0 /* Command definition */ diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index f0d6405d301..068b9e4d25f 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -14,9 +14,6 @@ /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -/* USB */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - /* Command definition */ #define CFG_MXC_UART_BASE UART1_BASE diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index f2edd13eb88..a966c8b2a44 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -31,6 +31,5 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CFG_MXC_USB_PORTSC PORT_PTS_UTMI #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 91544c8a0e2..e491af3e927 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -11,10 +11,6 @@ #define CFG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } #include "mx6sabre_common.h" diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 844f10e4229..e34947c94d0 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -24,10 +24,4 @@ #define CFG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) #endif -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - #endif /* __MX6SABRESD_CONFIG_H */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 39c8ef060c7..d4e66a39882 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -25,9 +25,9 @@ "fdt_addr=0x88000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=1\0" \ + "mmcdev=0\0" \ "mmcpart=1\0" \ - "finduuid=part uuid mmc 1:2 uuid\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=PARTUUID=${uuid} rootwait rw\0" \ "loadbootscript=" \ @@ -88,12 +88,6 @@ /* Environment organization */ -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - #define CFG_SYS_FSL_USDHC_NUM 3 #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 290996b51bc..0ba4054bbe4 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -92,10 +92,5 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CFG_SYS_FSL_USDHC_NUM 3 -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#endif - #include <linux/stringify.h> #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 1c14a6beb0a..36d82e81d5d 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -95,11 +95,6 @@ #define IMX_FEC_BASE ENET2_BASE_ADDR #define CFG_FEC_MXC_PHYADDR 0x0 -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - #define CFG_SYS_FSL_USDHC_NUM 2 #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index fe0ad34ef9c..844becbfd2c 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -117,11 +117,6 @@ #define CFG_FEC_MXC_PHYADDR 0x1 -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - #ifdef CONFIG_CMD_PCI #define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) #define CFG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 98b743b9364..3716dc75b96 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -114,12 +114,6 @@ /* environment organization */ -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - #ifdef CONFIG_CMD_NET #define CFG_FEC_ENET_DEV 1 diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 94bee75fdea..f5ab4720750 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -98,7 +98,4 @@ /* DMA stuff, needed for GPMI/MXS NAND support */ #endif -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - #endif /* __CONFIG_H */ diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index a310c64e794..f8e3950fa32 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -51,5 +51,4 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE SZ_256K -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 2571098d06c..ddd46c8f945 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -29,10 +29,6 @@ /* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ "fdt_addr_r=0x82000000\0" \ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index c03d11dcdae..23eefaffc72 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -18,10 +18,6 @@ #define IMX_FEC_BASE ENET_BASE_ADDR #define CFG_FEC_MXC_PHYADDR 6 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #ifdef CONFIG_CMD_MMC #define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) #else diff --git a/include/configs/novena.h b/include/configs/novena.h index 39d3afd1c8e..059b8104e4b 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -51,12 +51,6 @@ /* UART */ #define CFG_MXC_UART_BASE UART2_BASE -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - /* Extra U-Boot environment. */ #define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 5f933391cc0..1caa63f0227 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -28,10 +28,6 @@ /* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #ifdef CONFIG_CMD_NET #define CFG_FEC_MXC_PHYADDR 0x1 #endif diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index 9050da8738b..f5a4898f90e 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -11,10 +11,6 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -#if IS_ENABLED(CONFIG_CMD_USB) -# define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#endif /* CONFIG_CMD_USB */ - #define CFG_EXTRA_ENV_SETTINGS \ "mmcdev=0\0" \ "mmcpart=2\0" \ diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 1edb1826c4e..fd945235af3 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -17,12 +17,6 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* USB */ -#ifdef CONFIG_USB_EHCI_MX6 -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - /* LCD */ #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 38dcee05359..0c96506b5fb 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -41,10 +41,6 @@ /* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ "fdt_addr_r=0x82000000\0" \ diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index d742201ce43..0f265adc5dc 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -43,10 +43,6 @@ /* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index dd7cfdba52d..0910ae2d870 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -29,6 +29,14 @@ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ "mmcroot=2\0" \ + "update_offset=0x42\0" \ + "update_filename=flash.bin\0" \ + "update_bootimg=" \ + "mmc dev ${mmcdev} ; " \ + "if dhcp ${loadaddr} ${update_filepath}/${update_filename} ; then " \ + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ + "mmc write ${loadaddr} ${update_offset} ${fw_sz} ; " \ + "fi\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console} " \ "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index d806d7d9c57..500dd8c069a 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -15,10 +15,6 @@ /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CFG_DFU_ENV_SETTINGS \ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 8a22f0134b3..37f4c7d8a09 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -21,10 +21,6 @@ /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CFG_DFU_ENV_SETTINGS \ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index e7a8cb20dff..89850d8e4a7 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -105,8 +105,4 @@ #define CFG_SYS_FSL_USDHC_NUM 2 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #endif diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 041a83b057d..c8fdb40d011 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -59,12 +59,6 @@ /* environment organization */ -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 -#endif - #ifdef CONFIG_CMD_NET #define CFG_FEC_MXC_PHYADDR 0x1 #endif diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 256331ae173..9ef774afd0f 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -25,11 +25,6 @@ #define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#endif /* CONFIG_CMD_USB */ - #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index ceeed174ec5..fd4d170456a 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -34,9 +34,6 @@ /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - #if defined(CONFIG_TQMA6X_MMC_BOOT) #define TQMA6_UBOOT_OFFSET SZ_1K diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 27e61f5b8f4..5bdd124be65 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -23,8 +23,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 /* USB */ -#define CFG_MXC_USB_PORT 1 -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CFG_MXC_USB_FLAGS 0 /* Linux boot */ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 12d2b682305..b018bbe29dd 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -63,7 +63,4 @@ #define PHYS_SDRAM_2 0x100000000 #define PHYS_SDRAM_2_SIZE (long)(SZ_1G) -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - #endif /* __VERDIN_IMX8MM_H */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 30654191a26..2cf7bc70d8d 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -36,8 +36,6 @@ /* Network */ #define CFG_FEC_MXC_PHYADDR 0x0 -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 #ifdef CONFIG_CMD_PCI #define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 7b8c5cbe7a8..b5b342b3538 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -16,10 +16,6 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ "splashpos=m,m\0" \ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 0da9250c3b7..a5278d1cb9b 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -92,7 +92,6 @@ #define CFG_SYS_FSL_USDHC_NUM 1 -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) /* USB Device Firmware Update support */ #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/xpress.h b/include/configs/xpress.h index a2aa31008ec..8efebf77c3d 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -27,10 +27,6 @@ /* Environment is in stored in the eMMC boot partition */ -/* USB Configs */ -#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CFG_MXC_USB_FLAGS 0 - #define CFG_FEC_ENET_DEV 0 #define CFG_FEC_MXC_PHYADDR 0x0 diff --git a/include/dt-bindings/clock/sophgo,cv1800.h b/include/dt-bindings/clock/sophgo,cv1800.h new file mode 100644 index 00000000000..cfbeca25a65 --- /dev/null +++ b/include/dt-bindings/clock/sophgo,cv1800.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2023 Sophgo Ltd. + */ + +#ifndef __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ +#define __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ + +#define CLK_MPLL 0 +#define CLK_TPLL 1 +#define CLK_FPLL 2 +#define CLK_MIPIMPLL 3 +#define CLK_A0PLL 4 +#define CLK_DISPPLL 5 +#define CLK_CAM0PLL 6 +#define CLK_CAM1PLL 7 + +#define CLK_MIPIMPLL_D3 8 +#define CLK_CAM0PLL_D2 9 +#define CLK_CAM0PLL_D3 10 + +#define CLK_TPU 11 +#define CLK_TPU_FAB 12 +#define CLK_AHB_ROM 13 +#define CLK_DDR_AXI_REG 14 +#define CLK_RTC_25M 15 +#define CLK_SRC_RTC_SYS_0 16 +#define CLK_TEMPSEN 17 +#define CLK_SARADC 18 +#define CLK_EFUSE 19 +#define CLK_APB_EFUSE 20 +#define CLK_DEBUG 21 +#define CLK_AP_DEBUG 22 +#define CLK_XTAL_MISC 23 +#define CLK_AXI4_EMMC 24 +#define CLK_EMMC 25 +#define CLK_EMMC_100K 26 +#define CLK_AXI4_SD0 27 +#define CLK_SD0 28 +#define CLK_SD0_100K 29 +#define CLK_AXI4_SD1 30 +#define CLK_SD1 31 +#define CLK_SD1_100K 32 +#define CLK_SPI_NAND 33 +#define CLK_ETH0_500M 34 +#define CLK_AXI4_ETH0 35 +#define CLK_ETH1_500M 36 +#define CLK_AXI4_ETH1 37 +#define CLK_APB_GPIO 38 +#define CLK_APB_GPIO_INTR 39 +#define CLK_GPIO_DB 40 +#define CLK_AHB_SF 41 +#define CLK_AHB_SF1 42 +#define CLK_A24M 43 +#define CLK_AUDSRC 44 +#define CLK_APB_AUDSRC 45 +#define CLK_SDMA_AXI 46 +#define CLK_SDMA_AUD0 47 +#define CLK_SDMA_AUD1 48 +#define CLK_SDMA_AUD2 49 +#define CLK_SDMA_AUD3 50 +#define CLK_I2C 51 +#define CLK_APB_I2C 52 +#define CLK_APB_I2C0 53 +#define CLK_APB_I2C1 54 +#define CLK_APB_I2C2 55 +#define CLK_APB_I2C3 56 +#define CLK_APB_I2C4 57 +#define CLK_APB_WDT 58 +#define CLK_PWM_SRC 59 +#define CLK_PWM 60 +#define CLK_SPI 61 +#define CLK_APB_SPI0 62 +#define CLK_APB_SPI1 63 +#define CLK_APB_SPI2 64 +#define CLK_APB_SPI3 65 +#define CLK_1M 66 +#define CLK_CAM0_200 67 +#define CLK_PM 68 +#define CLK_TIMER0 69 +#define CLK_TIMER1 70 +#define CLK_TIMER2 71 +#define CLK_TIMER3 72 +#define CLK_TIMER4 73 +#define CLK_TIMER5 74 +#define CLK_TIMER6 75 +#define CLK_TIMER7 76 +#define CLK_UART0 77 +#define CLK_APB_UART0 78 +#define CLK_UART1 79 +#define CLK_APB_UART1 80 +#define CLK_UART2 81 +#define CLK_APB_UART2 82 +#define CLK_UART3 83 +#define CLK_APB_UART3 84 +#define CLK_UART4 85 +#define CLK_APB_UART4 86 +#define CLK_APB_I2S0 87 +#define CLK_APB_I2S1 88 +#define CLK_APB_I2S2 89 +#define CLK_APB_I2S3 90 +#define CLK_AXI4_USB 91 +#define CLK_APB_USB 92 +#define CLK_USB_125M 93 +#define CLK_USB_33K 94 +#define CLK_USB_12M 95 +#define CLK_AXI4 96 +#define CLK_AXI6 97 +#define CLK_DSI_ESC 98 +#define CLK_AXI_VIP 99 +#define CLK_SRC_VIP_SYS_0 100 +#define CLK_SRC_VIP_SYS_1 101 +#define CLK_SRC_VIP_SYS_2 102 +#define CLK_SRC_VIP_SYS_3 103 +#define CLK_SRC_VIP_SYS_4 104 +#define CLK_CSI_BE_VIP 105 +#define CLK_CSI_MAC0_VIP 106 +#define CLK_CSI_MAC1_VIP 107 +#define CLK_CSI_MAC2_VIP 108 +#define CLK_CSI0_RX_VIP 109 +#define CLK_CSI1_RX_VIP 110 +#define CLK_ISP_TOP_VIP 111 +#define CLK_IMG_D_VIP 112 +#define CLK_IMG_V_VIP 113 +#define CLK_SC_TOP_VIP 114 +#define CLK_SC_D_VIP 115 +#define CLK_SC_V1_VIP 116 +#define CLK_SC_V2_VIP 117 +#define CLK_SC_V3_VIP 118 +#define CLK_DWA_VIP 119 +#define CLK_BT_VIP 120 +#define CLK_DISP_VIP 121 +#define CLK_DSI_MAC_VIP 122 +#define CLK_LVDS0_VIP 123 +#define CLK_LVDS1_VIP 124 +#define CLK_PAD_VI_VIP 125 +#define CLK_PAD_VI1_VIP 126 +#define CLK_PAD_VI2_VIP 127 +#define CLK_CFG_REG_VIP 128 +#define CLK_VIP_IP0 129 +#define CLK_VIP_IP1 130 +#define CLK_VIP_IP2 131 +#define CLK_VIP_IP3 132 +#define CLK_IVE_VIP 133 +#define CLK_RAW_VIP 134 +#define CLK_OSDC_VIP 135 +#define CLK_CAM0_VIP 136 +#define CLK_AXI_VIDEO_CODEC 137 +#define CLK_VC_SRC0 138 +#define CLK_VC_SRC1 139 +#define CLK_VC_SRC2 140 +#define CLK_H264C 141 +#define CLK_APB_H264C 142 +#define CLK_H265C 143 +#define CLK_APB_H265C 144 +#define CLK_JPEG 145 +#define CLK_APB_JPEG 146 +#define CLK_CAM0 147 +#define CLK_CAM1 148 +#define CLK_WGN 149 +#define CLK_WGN0 150 +#define CLK_WGN1 151 +#define CLK_WGN2 152 +#define CLK_KEYSCAN 153 +#define CLK_CFG_REG_VC 154 +#define CLK_C906_0 155 +#define CLK_C906_1 156 +#define CLK_A53 157 +#define CLK_CPU_AXI0 158 +#define CLK_CPU_GIC 159 +#define CLK_XTAL_AP 160 + +// Only for CV181x +#define CLK_DISP_SRC_VIP 161 + +#endif /* __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ */ diff --git a/include/dt-bindings/pinctrl/sandbox-pinmux.h b/include/dt-bindings/pinctrl/sandbox-pinmux.h index 891af072e52..21c5a1762ab 100644 --- a/include/dt-bindings/pinctrl/sandbox-pinmux.h +++ b/include/dt-bindings/pinctrl/sandbox-pinmux.h @@ -13,6 +13,7 @@ #define SANDBOX_PINMUX_GPIO 4 #define SANDBOX_PINMUX_CS 5 #define SANDBOX_PINMUX_PWM 6 +#define SANDBOX_PINMUX_ONEWIRE 7 #define SANDBOX_PINMUX(pin, func) ((func) << 16 | (pin)) diff --git a/include/efi.h b/include/efi.h index d5af2139946..84640cf7b25 100644 --- a/include/efi.h +++ b/include/efi.h @@ -74,7 +74,7 @@ struct efi_device_path { * struct { u32 a; u16; b; u16 c; u8 d[8]; }; which is 4-byte * aligned. */ -typedef struct { +typedef struct efi_guid { u8 b[16]; } efi_guid_t __attribute__((aligned(4))); diff --git a/include/env/phytec/k3_mmc.env b/include/env/phytec/k3_mmc.env index 3d3595ceb7e..ad8d3a8b764 100644 --- a/include/env/phytec/k3_mmc.env +++ b/include/env/phytec/k3_mmc.env @@ -7,15 +7,17 @@ /* Logic for TI K3 based SoCs to boot from a MMC device. */ #include <env/phytec/overlays.env> +#include <env/phytec/rauc.env> mmcargs=setenv bootargs console=${console} earlycon=${earlycon} - root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw -loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} Image -loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -mmcboot=run mmcargs; + root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw +mmcloadimage=load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} Image +mmcloadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +mmcboot=if test ${doraucboot} = 1; then run raucinit; fi; + run mmcargs; mmc dev ${mmcdev}; mmc rescan; - run loadimage; - run loadfdt; + run mmcloadimage; + run mmcloadfdt; run mmc_apply_overlays; - booti ${loadaddr} - ${fdt_addr_r} + booti ${kernel_addr_r} - ${fdt_addr_r} diff --git a/include/env/phytec/k3_net.env b/include/env/phytec/k3_net.env new file mode 100644 index 00000000000..377e406688d --- /dev/null +++ b/include/env/phytec/k3_net.env @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Daniel Schultz <d.schultz@phytec.de> + */ + +/* Logic for TI K3 based SoCs to boot via network. */ + +#include <env/phytec/overlays.env> + +netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp rw + nfsroot=${serverip}:${nfsroot},vers=4,tcp +netloadimage=${net_fetch_cmd} ${kernel_addr_r} ${serverip}:/Image +netloadfdt=${net_fetch_cmd} ${fdt_addr_r} ${serverip}:/${fdtfile} +netboot=run netargs; + setenv autoload no; + dhcp; + run netloadimage; + run netloadfdt; + run net_apply_overlays; + run net_apply_extensions; + booti ${kernel_addr_r} - ${fdt_addr_r} diff --git a/include/env/phytec/k3_spi.env b/include/env/phytec/k3_spi.env new file mode 100644 index 00000000000..97d3a157058 --- /dev/null +++ b/include/env/phytec/k3_spi.env @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Daniel Schultz <d.schultz@phytec.de> + */ + +/* Logic for TI K3 based SoCs to boot from an OSPI/QSPI NOR flash. */ + +spiargs=setenv bootargs console=${console} earlycon=${earlycon} +spiloadimage=sf read ${kernel_addr_r} ${spi_image_addr} ${size_kern} +spiloadfdt=sf read ${fdt_addr_r} ${spi_fdt_addr} ${size_fdt} +spiloadramdisk=sf read ${ramdisk_addr_r} ${spi_ramdisk_addr} ${size_fs} +spiboot=run spiargs; + sf probe; + run spiloadimage; + run spiloadfdt; + run spiloadramdisk; + booti ${kernel_addr_r} ${ramdisk_addr_r}:0x${size_fs} ${fdt_addr_r} diff --git a/include/env_default.h b/include/env_default.h index 076ffdd44e9..aa3dd40f3fa 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -82,9 +82,6 @@ const char default_environment[] = { #ifdef CONFIG_SYS_LOAD_ADDR "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR)"\0" #endif -#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) - "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0" -#endif #ifdef CONFIG_ENV_VARS_UBOOT_CONFIG "arch=" CONFIG_SYS_ARCH "\0" #ifdef CONFIG_SYS_CPU diff --git a/include/env_internal.h b/include/env_internal.h index 0a267e35592..c1c0727e4d0 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -100,6 +100,7 @@ extern const char default_environment[]; #include <env_flags.h> #include <search.h> +/* this is stored as bits in gd->env_has_init so is limited to 16 entries */ enum env_location { ENVL_UNKNOWN, ENVL_EEPROM, diff --git a/include/fwu.h b/include/fwu.h index 77ec65e6180..c317613eaaa 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -10,7 +10,7 @@ #include <efi.h> #include <fwu_mdata.h> #include <mtd.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <linux/types.h> diff --git a/include/generic-phy.h b/include/generic-phy.h index eaab7491660..ba3321f4849 100644 --- a/include/generic-phy.h +++ b/include/generic-phy.h @@ -415,10 +415,13 @@ int generic_phy_power_off_bulk(struct phy_bulk *bulk); * @dev: The consumer device. * @phy: A pointer to the PHY port * @index: The index in the list of available PHYs + * @mode: PHY mode + * @submode: PHY submode * * Return: 0 if OK, or negative error code. */ -int generic_setup_phy(struct udevice *dev, struct phy *phy, int index); +int generic_setup_phy(struct udevice *dev, struct phy *phy, int index, + enum phy_mode mode, int submode); /** * generic_shutdown_phy() - Power off and de-initialize phy. @@ -509,7 +512,8 @@ static inline int generic_phy_power_off_bulk(struct phy_bulk *bulk) return 0; } -static inline int generic_setup_phy(struct udevice *dev, struct phy *phy, int index) +static inline int generic_setup_phy(struct udevice *dev, struct phy *phy, int index, + enum phy_mode mode, int submode) { return 0; } diff --git a/include/handoff.h b/include/handoff.h index c0ae7b19a75..0072ea832f8 100644 --- a/include/handoff.h +++ b/include/handoff.h @@ -32,6 +32,13 @@ void handoff_load_dram_size(struct spl_handoff *ho); void handoff_load_dram_banks(struct spl_handoff *ho); /** + * handoff_get() - Get the SPL handoff information + * + * Return: Pointer to SPL handoff if received, else NULL + */ +struct spl_handoff *handoff_get(void); + +/** * handoff_arch_save() - Save arch-specific info into the handoff area * * This is defined to an empty function by default, but arch-specific code can diff --git a/include/image.h b/include/image.h index dd4042d1bd9..c52fced9b40 100644 --- a/include/image.h +++ b/include/image.h @@ -20,7 +20,6 @@ #include <stdbool.h> /* Define this to avoid #ifdefs later on */ -struct lmb; struct fdt_region; #ifdef USE_HOSTCC @@ -412,18 +411,8 @@ struct bootm_headers { #define BOOTM_STATE_PRE_LOAD 0x00000800 #define BOOTM_STATE_MEASURE 0x00001000 int state; - -#if defined(CONFIG_LMB) && !defined(USE_HOSTCC) - struct lmb lmb; /* for memory mgmt */ -#endif }; -#ifdef CONFIG_LMB -#define images_lmb(_images) (&(_images)->lmb) -#else -#define images_lmb(_images) NULL -#endif - extern struct bootm_headers images; /* @@ -835,13 +824,13 @@ int boot_get_fdt(void *buf, const char *select, uint arch, struct bootm_headers *images, char **of_flat_tree, ulong *of_size); -void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob); -int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size); +void boot_fdt_add_mem_rsv_regions(void *fdt_blob); +int boot_relocate_fdt(char **of_flat_tree, ulong *of_size); -int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, - ulong *initrd_start, ulong *initrd_end); -int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end); -int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd); +int boot_ramdisk_high(ulong rd_data, ulong rd_len, ulong *initrd_start, + ulong *initrd_end); +int boot_get_cmdline(ulong *cmd_start, ulong *cmd_end); +int boot_get_kbd(struct bd_info **kbd); /*******************************************************************/ /* Legacy format specific code (prefixed with image_) */ @@ -1029,11 +1018,10 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, * * @images: Images information * @blob: FDT to update - * @lmb: Points to logical memory block structure + * @lmb: Flag indicating use of lmb for reserving FDT memory region * Return: 0 if ok, <0 on failure */ -int image_setup_libfdt(struct bootm_headers *images, void *blob, - struct lmb *lmb); +int image_setup_libfdt(struct bootm_headers *images, void *blob, bool lmb); /** * Set up the FDT to use for booting a kernel @@ -1858,7 +1846,7 @@ int android_image_get_kernel(const void *hdr, * @vendor_boot_img : Pointer to vendor boot image header * @rd_data: Pointer to a ulong variable, will hold ramdisk address * @rd_len: Pointer to a ulong variable, will hold ramdisk length - * Return: 0 if succeeded, -1 if ramdisk size is 0 + * Return: 0 if OK, -ENOPKG if no ramdisk, -EINVAL if invalid image */ int android_image_get_ramdisk(const void *hdr, const void *vendor_boot_img, ulong *rd_data, ulong *rd_len); diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 537c62424a1..2d85b392465 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -247,6 +247,11 @@ enum nand_ecc_algo { * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers */ #define NAND_USE_BOUNCE_BUFFER 0x00100000 +/* + * Whether the NAND chip is a boot medium. Drivers might use this information + * to select ECC algorithms supported by the boot ROM or similar restrictions. + */ +#define NAND_IS_BOOT_MEDIUM 0x00400000 /* * Do not try to tweak the timings at runtime. This is needed when the diff --git a/include/lmb.h b/include/lmb.h index 231b68b27d9..fc2daaa7bfc 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -3,8 +3,10 @@ #define _LINUX_LMB_H #ifdef __KERNEL__ +#include <alist.h> #include <asm/types.h> #include <asm/u-boot.h> +#include <linux/bitops.h> /* * Logical memory blocks. @@ -18,115 +20,75 @@ * @LMB_NOMAP: don't add to mmu configuration */ enum lmb_flags { - LMB_NONE = 0x0, - LMB_NOMAP = 0x4, + LMB_NONE = 0, + LMB_NOMAP = BIT(1), + LMB_NOOVERWRITE = BIT(2), }; /** - * struct lmb_property - Description of one region. + * struct lmb_region - Description of one region. * * @base: Base address of the region. * @size: Size of the region * @flags: memory region attributes */ -struct lmb_property { +struct lmb_region { phys_addr_t base; phys_size_t size; enum lmb_flags flags; }; -/* - * For regions size management, see LMB configuration in KConfig - * all the #if test are done with CONFIG_LMB_USE_MAX_REGIONS (boolean) - * - * case 1. CONFIG_LMB_USE_MAX_REGIONS is defined (legacy mode) - * => CONFIG_LMB_MAX_REGIONS is used to configure the region size, - * directly in the array lmb_region.region[], with the same - * configuration for memory and reserved regions. +/** + * struct lmb - The LMB structure * - * case 2. CONFIG_LMB_USE_MAX_REGIONS is not defined, the size of each - * region is configurated *independently* with - * => CONFIG_LMB_MEMORY_REGIONS: struct lmb.memory_regions - * => CONFIG_LMB_RESERVED_REGIONS: struct lmb.reserved_regions - * lmb_region.region is only a pointer to the correct buffer, - * initialized in lmb_init(). This configuration is useful to manage - * more reserved memory regions with CONFIG_LMB_RESERVED_REGIONS. + * @free_mem: List of free memory regions + * @used_mem: List of used/reserved memory regions */ +struct lmb { + struct alist free_mem; + struct alist used_mem; +}; /** - * struct lmb_region - Description of a set of region. + * lmb_init() - Initialise the LMB module + * + * Initialise the LMB lists needed for keeping the memory map. There + * are two lists, in form of alloced list data structure. One for the + * available memory, and one for the used memory. Initialise the two + * lists as part of board init. Add memory to the available memory + * list and reserve common areas by adding them to the used memory + * list. * - * @cnt: Number of regions. - * @max: Size of the region array, max value of cnt. - * @region: Array of the region properties + * Return: 0 on success, -ve on error */ -struct lmb_region { - unsigned long cnt; - unsigned long max; -#if IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS) - struct lmb_property region[CONFIG_LMB_MAX_REGIONS]; -#else - struct lmb_property *region; -#endif -}; +int lmb_init(void); /** - * struct lmb - Logical memory block handle. + * lmb_add_memory() - Add memory range for LMB allocations * - * Clients provide storage for Logical memory block (lmb) handles. - * The content of the structure is managed by the lmb library. - * A lmb struct is initialized by lmb_init() functions. - * The lmb struct is passed to all other lmb APIs. + * Add the entire available memory range to the pool of memory that + * can be used by the LMB module for allocations. * - * @memory: Description of memory regions. - * @reserved: Description of reserved regions. - * @memory_regions: Array of the memory regions (statically allocated) - * @reserved_regions: Array of the reserved regions (statically allocated) + * Return: None */ -struct lmb { - struct lmb_region memory; - struct lmb_region reserved; -#if !IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS) - struct lmb_property memory_regions[CONFIG_LMB_MEMORY_REGIONS]; - struct lmb_property reserved_regions[CONFIG_LMB_RESERVED_REGIONS]; -#endif -}; +void lmb_add_memory(void); -void lmb_init(struct lmb *lmb); -void lmb_init_and_reserve(struct lmb *lmb, struct bd_info *bd, void *fdt_blob); -void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base, - phys_size_t size, void *fdt_blob); -long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size); -long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size); +long lmb_add(phys_addr_t base, phys_size_t size); +long lmb_reserve(phys_addr_t base, phys_size_t size); /** * lmb_reserve_flags - Reserve one region with a specific flags bitfield. * - * @lmb: the logical memory block struct * @base: base address of the memory region * @size: size of the memory region * @flags: flags for the memory region * Return: 0 if OK, > 0 for coalesced region or a negative error code. */ -long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base, - phys_size_t size, enum lmb_flags flags); -phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align); -phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, - phys_addr_t max_addr); -phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, - phys_addr_t max_addr); -phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, phys_size_t size); -phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr); - -/** - * lmb_is_reserved() - test if address is in reserved region - * - * The function checks if a reserved region comprising @addr exists. - * - * @lmb: the logical memory block struct - * @addr: address to be tested - * Return: 1 if reservation exists, 0 otherwise - */ -int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr); +long lmb_reserve_flags(phys_addr_t base, phys_size_t size, + enum lmb_flags flags); +phys_addr_t lmb_alloc(phys_size_t size, ulong align); +phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr); +phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size); +phys_size_t lmb_get_free_size(phys_addr_t addr); /** * lmb_is_reserved_flags() - test if address is in reserved region with flag bits set @@ -134,21 +96,20 @@ int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr); * The function checks if a reserved region comprising @addr exists which has * all flag bits set which are set in @flags. * - * @lmb: the logical memory block struct * @addr: address to be tested * @flags: bitmap with bits to be tested * Return: 1 if matching reservation exists, 0 otherwise */ -int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags); +int lmb_is_reserved_flags(phys_addr_t addr, int flags); -long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size); +long lmb_free(phys_addr_t base, phys_size_t size); -void lmb_dump_all(struct lmb *lmb); -void lmb_dump_all_force(struct lmb *lmb); +void lmb_dump_all(void); +void lmb_dump_all_force(void); -void board_lmb_reserve(struct lmb *lmb); -void arch_lmb_reserve(struct lmb *lmb); -void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end, ulong align); +struct lmb *lmb_get(void); +int lmb_push(struct lmb *store); +void lmb_pop(struct lmb *store); #endif /* __KERNEL__ */ diff --git a/include/log.h b/include/log.h index fc0d5984472..69dcb339543 100644 --- a/include/log.h +++ b/include/log.h @@ -125,7 +125,7 @@ static inline int log_uc_cat(enum uclass_id id) * @level: Level of log record (indicating its severity) * @file: File name of file where log record was generated * @line: Line number in file where log record was generated - * @func: Function where log record was generated + * @func: Function where log record was generated, NULL if not known * @fmt: printf() format string for log record * @...: Optional parameters, according to the format string @fmt * Return: 0 if log record was emitted, -ve on error @@ -141,7 +141,7 @@ int _log(enum log_category_t cat, enum log_level_t level, const char *file, * @level: Level of log record (indicating its severity) * @file: File name of file where log record was generated * @line: Line number in file where log record was generated - * @func: Function where log record was generated + * @func: Function where log record was generated, NULL if not known * @addr: Starting address to display at start of line * @data: pointer to data buffer * @width: data value width. May be 1, 2, or 4. @@ -193,6 +193,12 @@ int _log_buffer(enum log_category_t cat, enum log_level_t level, #define _LOG_DEBUG 0 #endif +#ifdef CONFIG_LOGF_FUNC +#define _log_func __func__ +#else +#define _log_func NULL +#endif + #if CONFIG_IS_ENABLED(LOG) /* Emit a log record if the level is less that the maximum */ @@ -201,7 +207,7 @@ int _log_buffer(enum log_category_t cat, enum log_level_t level, if (_LOG_DEBUG != 0 || _l <= _LOG_MAX_LEVEL) \ _log((enum log_category_t)(_cat), \ (enum log_level_t)(_l | _LOG_DEBUG), __FILE__, \ - __LINE__, __func__, \ + __LINE__, _log_func, \ pr_fmt(_fmt), ##_args); \ }) @@ -211,7 +217,7 @@ int _log_buffer(enum log_category_t cat, enum log_level_t level, if (_LOG_DEBUG != 0 || _l <= _LOG_MAX_LEVEL) \ _log_buffer((enum log_category_t)(_cat), \ (enum log_level_t)(_l | _LOG_DEBUG), __FILE__, \ - __LINE__, __func__, _addr, _data, \ + __LINE__, _log_func, _addr, _data, \ _width, _count, _linelen); \ }) #else @@ -314,7 +320,7 @@ void __assert_fail(const char *assertion, const char *file, unsigned int line, #define assert_noisy(x) \ ({ bool _val = (x); \ if (!_val) \ - __assert_fail(#x, "?", __LINE__, __func__); \ + __assert_fail(#x, "?", __LINE__, _log_func); \ _val; \ }) diff --git a/include/mmc.h b/include/mmc.h index 155a8e9f420..f508cd15700 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -372,6 +372,32 @@ enum mmc_voltage { #define MMC_TIMING_MMC_HS200 9 #define MMC_TIMING_MMC_HS400 10 +/* emmc PARTITION_CONFIG BOOT_PARTITION_ENABLE values */ +enum emmc_boot_part { + EMMC_BOOT_PART_DEFAULT = 0, + EMMC_BOOT_PART_BOOT1 = 1, + EMMC_BOOT_PART_BOOT2 = 2, + EMMC_BOOT_PART_USER = 7, +}; + +/* emmc PARTITION_CONFIG BOOT_PARTITION_ENABLE names */ +extern const char *emmc_boot_part_names[8]; + +/* emmc PARTITION_CONFIG ACCESS_ENABLE values */ +enum emmc_hwpart { + EMMC_HWPART_DEFAULT = 0, /* user */ + EMMC_HWPART_BOOT1 = 1, + EMMC_HWPART_BOOT2 = 2, + EMMC_HWPART_RPMB = 3, + EMMC_HWPART_GP1 = 4, + EMMC_HWPART_GP2 = 5, + EMMC_HWPART_GP3 = 6, + EMMC_HWPART_GP4 = 7, +}; + +/* emmc PARTITION_CONFIG ACCESS_ENABLE names */ +extern const char *emmc_hwpart_names[8]; + /* Driver model support */ /** diff --git a/include/part.h b/include/part.h index 54b986cee63..797b542ef1f 100644 --- a/include/part.h +++ b/include/part.h @@ -8,7 +8,7 @@ #include <blk.h> #include <ide.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <linker_lists.h> #include <linux/errno.h> #include <linux/list.h> diff --git a/include/pci_ids.h b/include/pci_ids.h index 191d277bc8a..a8939b105f1 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2600,6 +2600,15 @@ #define PCI_DEVICE_ID_DCI_PCCOM2 0x0004 #define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G 0x4b30 +#define PCI_DEVICE_ID_INTEL_EHL_SGMII1 0x4b31 +#define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32 +#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0 +#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1 +#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 0x4ba2 +#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0 +#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1 +#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 0x4bb2 #define PCI_DEVICE_ID_INTEL_EESSC 0x0008 #define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100 #define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154 diff --git a/include/rkmtd.h b/include/rkmtd.h index 145fede6c84..b7479036b39 100644 --- a/include/rkmtd.h +++ b/include/rkmtd.h @@ -11,7 +11,7 @@ #define __RKMTD__ #include <part_efi.h> -#include <uuid.h> +#include <u-boot/uuid.h> #define LBA 64 + 512 + 33 diff --git a/include/sandbox_efi_capsule.h b/include/sandbox_efi_capsule.h index 3e288e8a84a..84d45ec5cfd 100644 --- a/include/sandbox_efi_capsule.h +++ b/include/sandbox_efi_capsule.h @@ -6,9 +6,9 @@ #if !defined(_SANDBOX_EFI_CAPSULE_H_) #define _SANDBOX_EFI_CAPSULE_H_ -#define SANDBOX_UBOOT_IMAGE_GUID "09d7cf52-0720-4710-91d1-08469b7fe9c8" -#define SANDBOX_UBOOT_ENV_IMAGE_GUID "5a7021f5-fef2-48b4-aaba-832e777418c0" -#define SANDBOX_FIT_IMAGE_GUID "3673b45d-6a7c-46f3-9e60-adabb03f7937" +#define SANDBOX_UBOOT_IMAGE_GUID "985f2937-7c2e-5e9a-8a5e-8e063312964b" +#define SANDBOX_UBOOT_ENV_IMAGE_GUID "9e339473-c2eb-530a-a69b-0cd6bbbed40e" +#define SANDBOX_FIT_IMAGE_GUID "46610520-469e-59dc-a8dd-c11832b877ea" #define SANDBOX_INCORRECT_GUID "058b7d83-50d5-4c47-a195-60d86ad341c4" #define UBOOT_FIT_IMAGE "u-boot_bin_env.itb" diff --git a/include/spl.h b/include/spl.h index f92089b69ea..de808ccd413 100644 --- a/include/spl.h +++ b/include/spl.h @@ -282,55 +282,67 @@ static inline void *spl_image_fdt_addr(struct spl_image_info *info) #endif } +struct spl_load_info; + +/** + * spl_load_reader() - Read from device + * + * @load: Information about the load state + * @offset: Offset to read from in bytes. This must be a multiple of + * @load->bl_len. + * @count: Number of bytes to read. This must be a multiple of + * @load->bl_len. + * @buf: Buffer to read into + * @return number of bytes read, 0 on error + */ +typedef ulong (*spl_load_reader)(struct spl_load_info *load, ulong sector, + ulong count, void *buf); + /** * Information required to load data from a device * + * @read: Function to call to read from the device * @priv: Private data for the device * @bl_len: Block length for reading in bytes - * @read: Function to call to read from the device */ struct spl_load_info { + spl_load_reader read; void *priv; - /** - * read() - Read from device - * - * @load: Information about the load state - * @offset: Offset to read from in bytes. This must be a multiple of - * @load->bl_len. - * @count: Number of bytes to read. This must be a multiple of - * @load->bl_len. - * @buf: Buffer to read into - * @return number of bytes read, 0 on error - */ - ulong (*read)(struct spl_load_info *load, ulong sector, ulong count, - void *buf); #if IS_ENABLED(CONFIG_SPL_LOAD_BLOCK) int bl_len; +#endif }; static inline int spl_get_bl_len(struct spl_load_info *info) { +#if IS_ENABLED(CONFIG_SPL_LOAD_BLOCK) return info->bl_len; +#else + return 1; +#endif } static inline void spl_set_bl_len(struct spl_load_info *info, int bl_len) { +#if IS_ENABLED(CONFIG_SPL_LOAD_BLOCK) info->bl_len = bl_len; -} #else -}; - -static inline int spl_get_bl_len(struct spl_load_info *info) -{ - return 1; + if (bl_len != 1) + panic("CONFIG_SPL_LOAD_BLOCK not enabled"); +#endif } -static inline void spl_set_bl_len(struct spl_load_info *info, int bl_len) +/** + * spl_load_init() - Set up a new spl_load_info structure + */ +static inline void spl_load_init(struct spl_load_info *load, + spl_load_reader h_read, void *priv, + uint bl_len) { - if (bl_len != 1) - panic("CONFIG_SPL_LOAD_BLOCK not enabled"); + load->read = h_read; + load->priv = priv; + spl_set_bl_len(load, bl_len); } -#endif /* * We need to know the position of U-Boot in memory so we can jump to it. We diff --git a/include/spl_load.h b/include/spl_load.h index 1c2b296c0a2..935f7d336f2 100644 --- a/include/spl_load.h +++ b/include/spl_load.h @@ -22,7 +22,7 @@ static inline int _spl_load(struct spl_image_info *spl_image, read = info->read(info, offset, ALIGN(sizeof(*header), spl_get_bl_len(info)), header); - if (read < sizeof(*header)) + if (read < (int)sizeof(*header)) return -EIO; if (image_get_magic(header) == FDT_MAGIC) { @@ -83,6 +83,10 @@ static inline int _spl_load(struct spl_image_info *spl_image, read = info->read(info, offset + image_offset, size, map_sysmem(spl_image->load_addr - overhead, size)); + + if (read < 0) + return read; + return read < spl_image->size ? -EIO : 0; } diff --git a/include/test/log.h b/include/test/log.h index e9028914500..e3362b85e99 100644 --- a/include/test/log.h +++ b/include/test/log.h @@ -13,7 +13,8 @@ #define LOGF_TEST (BIT(LOGF_FUNC) | BIT(LOGF_MSG)) /* Declare a new logging test */ -#define LOG_TEST(_name) UNIT_TEST(_name, 0, log_test) -#define LOG_TEST_FLAGS(_name, _flags) UNIT_TEST(_name, _flags, log_test) +#define LOG_TEST(_name) UNIT_TEST(_name, UTF_CONSOLE, log_test) +#define LOG_TEST_FLAGS(_name, _flags) \ + UNIT_TEST(_name, _flags | UTF_CONSOLE, log_test) #endif /* __TEST_LOG_H__ */ diff --git a/include/uuid.h b/include/u-boot/uuid.h index f5a941250f4..7f8414dc906 100644 --- a/include/uuid.h +++ b/include/u-boot/uuid.h @@ -11,6 +11,7 @@ #define __UUID_H__ #include <linux/bitops.h> +#include <linux/kconfig.h> /* * UUID - Universally Unique IDentifier - 128 bits unique number. @@ -46,8 +47,8 @@ * When converting to a binary UUID, le means the field should be converted * to little endian and be means it should be converted to big endian. * - * UUID is also used as GUID (Globally Unique Identifier) with the same binary - * format but it differs in string format like below. + * UUID is also used as GUID (Globally Unique Identifier) with the same format + * but with some fields stored in little endian. * * GUID: * 0 9 14 19 24 @@ -69,8 +70,8 @@ struct uuid { /* Bits of a bitmask specifying the output format for GUIDs */ #define UUID_STR_FORMAT_STD 0 -#define UUID_STR_FORMAT_GUID BIT(0) -#define UUID_STR_UPPER_CASE BIT(1) +#define UUID_STR_FORMAT_GUID 0x1 +#define UUID_STR_UPPER_CASE 0x2 /* Use UUID_STR_LEN + 1 for string space */ #define UUID_STR_LEN 36 @@ -143,6 +144,18 @@ void gen_rand_uuid(unsigned char *uuid_bin); */ void gen_rand_uuid_str(char *uuid_str, int str_format); +struct efi_guid; + +/** + * gen_v5_guid() - generate little endian v5 GUID from namespace and other seed data. + * + * @namespace: pointer to UUID namespace salt + * @guid: pointer to allocated GUID output + * @...: NULL terminated list of seed data as pairs of pointers + * to data and their lengths + */ +void gen_v5_guid(const struct uuid *namespace, struct efi_guid *guid, ...); + /** * uuid_str_to_le_bin() - Convert string UUID to little endian binary data. * @uuid_str: pointer to UUID string diff --git a/include/video.h b/include/video.h index 4013a949983..606c8a37fb8 100644 --- a/include/video.h +++ b/include/video.h @@ -420,4 +420,15 @@ int bmp_info(ulong addr); */ int video_reserve_from_bloblist(struct video_handoff *ho); +/** + * video_get_fb() - Get the first framebuffer address + * + * This function does not probe video devices, so can only be used after a video + * device has been activated. + * + * Return: address of the framebuffer of the first video device found, or 0 if + * there is no device + */ +ulong video_get_fb(void); + #endif diff --git a/lib/Kconfig b/lib/Kconfig index 2059219a120..1dd4f271595 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -73,6 +73,7 @@ config HAVE_PRIVATE_LIBGCC config LIB_UUID bool + select SHA1 config RANDOM_UUID bool "GPT Random UUID generation" @@ -403,7 +404,7 @@ config TRACE_EARLY_CALL_DEPTH_LIMIT config TRACE_EARLY_ADDR hex "Address of early trace buffer in U-Boot" depends on TRACE_EARLY - default 0x00100000 + default 0x00200000 help Sets the address of the early trace buffer in U-Boot. This memory must be accessible before relocation. @@ -1081,8 +1082,6 @@ config SMBIOS_PARSER help A simple parser for SMBIOS data. -source "lib/efi/Kconfig" -source "lib/efi_loader/Kconfig" source "lib/optee/Kconfig" config TEST_FDTDEC @@ -1102,42 +1101,19 @@ config LMB bool "Enable the logical memory blocks library (lmb)" default y if ARC || ARM || M68K || MICROBLAZE || MIPS || \ NIOS2 || PPC || RISCV || SANDBOX || SH || X86 || XTENSA + select ARCH_MISC_INIT if PPC help - Support the library logical memory blocks. - -config LMB_USE_MAX_REGIONS - bool "Use a common number of memory and reserved regions in lmb lib" - default y - help - Define the number of supported memory regions in the library logical - memory blocks. - This feature allow to reduce the lmb library size by using compiler - optimization when LMB_MEMORY_REGIONS == LMB_RESERVED_REGIONS. - -config LMB_MAX_REGIONS - int "Number of memory and reserved regions in lmb lib" - depends on LMB_USE_MAX_REGIONS - default 16 - help - Define the number of supported regions, memory and reserved, in the - library logical memory blocks. - -config LMB_MEMORY_REGIONS - int "Number of memory regions in lmb lib" - depends on !LMB_USE_MAX_REGIONS - default 8 - help - Define the number of supported memory regions in the library logical - memory blocks. - The minimal value is CONFIG_NR_DRAM_BANKS. + Support the library logical memory blocks. This will require + a malloc() implementation for defining the data structures + needed for maintaining the LMB memory map. -config LMB_RESERVED_REGIONS - int "Number of reserved regions in lmb lib" - depends on !LMB_USE_MAX_REGIONS - default 8 +config SPL_LMB + bool "Enable LMB module for SPL" + depends on SPL && SPL_FRAMEWORK && SPL_SYS_MALLOC help - Define the number of supported reserved regions in the library logical - memory blocks. + Enable support for Logical Memory Block library routines in + SPL. This will require a malloc() implementation for defining + the data structures needed for maintaining the LMB memory map. config PHANDLE_CHECK_SEQ bool "Enable phandle check while getting sequence number" diff --git a/lib/Makefile b/lib/Makefile index 81b503ab526..d300249f57c 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -118,7 +118,7 @@ obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdtdec.o fdtdec_common.o obj-y += hang.o obj-y += linux_compat.o obj-y += linux_string.o -obj-$(CONFIG_LMB) += lmb.o +obj-$(CONFIG_$(SPL_TPL_)LMB) += lmb.o obj-y += membuff.o obj-$(CONFIG_REGEX) += slre.o obj-y += string.o diff --git a/lib/acpi/acpi_dp.c b/lib/acpi/acpi_dp.c index 6733809986a..5714acce088 100644 --- a/lib/acpi/acpi_dp.c +++ b/lib/acpi/acpi_dp.c @@ -9,7 +9,7 @@ #include <dm.h> #include <log.h> #include <malloc.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <acpi/acpigen.h> #include <acpi/acpi_dp.h> #include <dm/acpi.h> diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c index b95cabb9149..ecff5a50d50 100644 --- a/lib/acpi/acpigen.c +++ b/lib/acpi/acpigen.c @@ -10,7 +10,7 @@ #include <dm.h> #include <log.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <acpi/acpigen.h> #include <acpi/acpi_device.h> #include <acpi/acpi_table.h> diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c index 4e2dbda9a71..b6bbcbf76ca 100644 --- a/lib/asm-offsets.c +++ b/lib/asm-offsets.c @@ -44,7 +44,9 @@ int main(void) DEFINE(GD_NEW_GD, offsetof(struct global_data, new_gd)); +#if CONFIG_IS_ENABLED(ENV_SUPPORT) DEFINE(GD_ENV_ADDR, offsetof(struct global_data, env_addr)); +#endif return 0; } diff --git a/lib/crypto/Kconfig b/lib/crypto/Kconfig index 6e0656ad1c5..742f6d9d4ed 100644 --- a/lib/crypto/Kconfig +++ b/lib/crypto/Kconfig @@ -1,6 +1,6 @@ menuconfig ASYMMETRIC_KEY_TYPE bool "Asymmetric (public-key cryptographic) key Support" - depends on FIT_SIGNATURE + depends on FIT_SIGNATURE || RSA_VERIFY_WITH_PKEY help This option provides support for a key type that holds the data for the asymmetric keys used for public key cryptographic operations such diff --git a/lib/efi/Kconfig b/lib/efi/Kconfig index c2b9bb73f71..81ed3e66b34 100644 --- a/lib/efi/Kconfig +++ b/lib/efi/Kconfig @@ -1,3 +1,6 @@ +menu "U-Boot as UEFI application" + depends on X86 + config EFI bool "Support running U-Boot from EFI" depends on X86 @@ -72,3 +75,5 @@ config EFI_RAM_SIZE use. U-Boot allocates this from EFI on start-up (along with a few other smaller amounts) and it can never be increased after that. It is used as the RAM size in with U-Boot. + +endmenu diff --git a/lib/efi/efi_app.c b/lib/efi/efi_app.c index 88332c3c910..9b94a93ee4f 100644 --- a/lib/efi/efi_app.c +++ b/lib/efi/efi_app.c @@ -17,7 +17,7 @@ #include <init.h> #include <malloc.h> #include <sysreset.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <asm/global_data.h> #include <linux/err.h> #include <linux/types.h> diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 1179c31bb13..e58b8825605 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -1,3 +1,5 @@ +menu "UEFI Support" + config EFI_LOADER bool "Support running UEFI applications" depends on OF_LIBFDT && ( \ @@ -41,13 +43,58 @@ config EFI_BINARY_EXEC You may enable CMD_BOOTEFI_BINARY so that you can use bootefi command to do that. -config EFI_BOOTMGR - bool "UEFI Boot Manager" +config EFI_SECURE_BOOT + bool "Enable EFI secure boot support" + depends on EFI_LOADER && FIT_SIGNATURE + select HASH + select SHA256 + select RSA + select RSA_VERIFY_WITH_PKEY + select IMAGE_SIGN_INFO + select ASYMMETRIC_KEY_TYPE + select ASYMMETRIC_PUBLIC_KEY_SUBTYPE + select X509_CERTIFICATE_PARSER + select PKCS7_MESSAGE_PARSER + select PKCS7_VERIFY + select MSCODE_PARSER + select EFI_SIGNATURE_SUPPORT + help + Select this option to enable EFI secure boot support. + Once SecureBoot mode is enforced, any EFI binary can run only if + it is signed with a trusted key. To do that, you need to install, + at least, PK, KEK and db. + +config EFI_SIGNATURE_SUPPORT + bool + +menu "UEFI services" + +config EFI_GET_TIME + bool "GetTime() runtime service" + depends on DM_RTC default y help - Select this option if you want to select the UEFI binary to be booted - via UEFI variables Boot####, BootOrder, and BootNext. You should also - normally enable CMD_BOOTEFI_BOOTMGR so that the command is available. + Provide the GetTime() runtime service at boottime. This service + can be used by an EFI application to read the real time clock. + +config EFI_SET_TIME + bool "SetTime() runtime service" + depends on EFI_GET_TIME + default y if ARCH_QEMU || SANDBOX + help + Provide the SetTime() runtime service at boottime. This service + can be used by an EFI application to adjust the real time clock. + +config EFI_HAVE_RUNTIME_RESET + # bool "Reset runtime service is available" + bool + default y + depends on ARCH_BCM283X || FSL_LAYERSCAPE || PSCI_RESET || \ + SANDBOX || SYSRESET_SBI || SYSRESET_X86 + +endmenu + +menu "UEFI Variables" choice prompt "Store for non-volatile UEFI variables" @@ -172,30 +219,18 @@ config EFI_VAR_BUF_SIZE Minimum 4096, default 131072 -config EFI_GET_TIME - bool "GetTime() runtime service" - depends on DM_RTC - default y +config EFI_PLATFORM_LANG_CODES + string "Language codes supported by firmware" + default "en-US" help - Provide the GetTime() runtime service at boottime. This service - can be used by an EFI application to read the real time clock. + This value is used to initialize the PlatformLangCodes variable. Its + value is a semicolon (;) separated list of language codes in native + RFC 4646 format, e.g. "en-US;de-DE". The first language code is used + to initialize the PlatformLang variable. -config EFI_SET_TIME - bool "SetTime() runtime service" - depends on EFI_GET_TIME - default y if ARCH_QEMU || SANDBOX - help - Provide the SetTime() runtime service at boottime. This service - can be used by an EFI application to adjust the real time clock. +endmenu -config EFI_SCROLL_ON_CLEAR_SCREEN - bool "Avoid overwriting previous output on clear screen" - help - Instead of erasing the screen content when the console screen should - be cleared, emit blank new lines so that previous output is scrolled - out of sight rather than overwritten. On serial consoles this allows - to capture complete boot logs (except for interactive menus etc.) - and can ease debugging related issues. +menu "Capsule support" config EFI_HAVE_CAPSULE_SUPPORT bool @@ -237,6 +272,18 @@ config EFI_CAPSULE_ON_DISK_EARLY executed as part of U-Boot initialisation so that they will surely take place whatever is set to distro_bootcmd. +config EFI_CAPSULE_NAMESPACE_GUID + string "Namespace for dynamic capsule GUIDs" + # v4 UUID as a default for upstream U-Boot boards + default "8c9f137e-91dc-427b-b2d6-b420faebaf2a" + depends on EFI_HAVE_CAPSULE_SUPPORT + help + Define the namespace or "salt" GUID used to generate the per-image + GUIDs. This should be a GUID in the standard 8-4-4-4-12 format. + + Device vendors are expected to generate their own namespace GUID + to avoid conflicts with upstream/community images. + config EFI_CAPSULE_FIRMWARE bool @@ -309,6 +356,10 @@ config EFI_CAPSULE_CRT_FILE embedded in the platform's device tree and used for capsule authentication at the time of capsule update. +endmenu + +menu "UEFI protocol support" + config EFI_DEVICE_PATH_TO_TEXT bool "Device path to text protocol" default y @@ -362,40 +413,6 @@ config EFI_UNICODE_CAPITALIZATION endif -config EFI_LOADER_BOUNCE_BUFFER - bool "EFI Applications use bounce buffers for DMA operations" - depends on ARM64 - help - Some hardware does not support DMA to full 64bit addresses. For this - hardware we can create a bounce buffer so that payloads don't have to - worry about platform details. - -config EFI_PLATFORM_LANG_CODES - string "Language codes supported by firmware" - default "en-US" - help - This value is used to initialize the PlatformLangCodes variable. Its - value is a semicolon (;) separated list of language codes in native - RFC 4646 format, e.g. "en-US;de-DE". The first language code is used - to initialize the PlatformLang variable. - -config EFI_HAVE_RUNTIME_RESET - # bool "Reset runtime service is available" - bool - default y - depends on ARCH_BCM283X || FSL_LAYERSCAPE || PSCI_RESET || \ - SANDBOX || SYSRESET_SBI || SYSRESET_X86 - -config EFI_GRUB_ARM32_WORKAROUND - bool "Workaround for GRUB on 32bit ARM" - default n if ARCH_BCM283X || ARCH_SUNXI || ARCH_QEMU - default y - depends on ARM && !ARM64 - help - GRUB prior to version 2.04 requires U-Boot to disable caches. This - workaround currently is also needed on systems with caches that - cannot be managed via CP15. - config EFI_RNG_PROTOCOL bool "EFI_RNG_PROTOCOL support" depends on DM_RNG @@ -448,29 +465,36 @@ config EFI_LOAD_FILE2_INITRD installed and Linux 5.7+ will ignore any initrd=<ramdisk> command line argument. -config EFI_SECURE_BOOT - bool "Enable EFI secure boot support" - depends on EFI_LOADER && FIT_SIGNATURE - select HASH - select SHA256 - select RSA - select RSA_VERIFY_WITH_PKEY - select IMAGE_SIGN_INFO - select ASYMMETRIC_KEY_TYPE - select ASYMMETRIC_PUBLIC_KEY_SUBTYPE - select X509_CERTIFICATE_PARSER - select PKCS7_MESSAGE_PARSER - select PKCS7_VERIFY - select MSCODE_PARSER - select EFI_SIGNATURE_SUPPORT +config EFI_RISCV_BOOT_PROTOCOL + bool "RISCV_EFI_BOOT_PROTOCOL support" + default y + depends on RISCV help - Select this option to enable EFI secure boot support. - Once SecureBoot mode is enforced, any EFI binary can run only if - it is signed with a trusted key. To do that, you need to install, - at least, PK, KEK and db. + The EFI_RISCV_BOOT_PROTOCOL is used to transfer the boot hart ID + to the next boot stage. It should be enabled as it is meant to + replace the transfer via the device-tree. The latter is not + possible on systems using ACPI. -config EFI_SIGNATURE_SUPPORT - bool +endmenu + +menu "Misc options" +config EFI_LOADER_BOUNCE_BUFFER + bool "EFI Applications use bounce buffers for DMA operations" + depends on ARM64 + help + Some hardware does not support DMA to full 64bit addresses. For this + hardware we can create a bounce buffer so that payloads don't have to + worry about platform details. + +config EFI_GRUB_ARM32_WORKAROUND + bool "Workaround for GRUB on 32bit ARM" + default n if ARCH_BCM283X || ARCH_SUNXI || ARCH_QEMU + default y + depends on ARM && !ARM64 + help + GRUB prior to version 2.04 requires U-Boot to disable caches. This + workaround currently is also needed on systems with caches that + cannot be managed via CP15. config EFI_ESRT bool "Enable the UEFI ESRT generation" @@ -497,15 +521,26 @@ config EFI_EBBR_2_1_CONFORMANCE help Enabling this option adds the EBBRv2.1 conformance entry to the ECPT UEFI table. -config EFI_RISCV_BOOT_PROTOCOL - bool "RISCV_EFI_BOOT_PROTOCOL support" +config EFI_SCROLL_ON_CLEAR_SCREEN + bool "Avoid overwriting previous output on clear screen" + help + Instead of erasing the screen content when the console screen should + be cleared, emit blank new lines so that previous output is scrolled + out of sight rather than overwritten. On serial consoles this allows + to capture complete boot logs (except for interactive menus etc.) + and can ease debugging related issues. + +endmenu + +menu "EFI bootmanager" + +config EFI_BOOTMGR + bool "UEFI Boot Manager" default y - depends on RISCV help - The EFI_RISCV_BOOT_PROTOCOL is used to transfer the boot hart ID - to the next boot stage. It should be enabled as it is meant to - replace the transfer via the device-tree. The latter is not - possible on systems using ACPI. + Select this option if you want to select the UEFI binary to be booted + via UEFI variables Boot####, BootOrder, and BootNext. You should also + normally enable CMD_BOOTEFI_BOOTMGR so that the command is available. config EFI_HTTP_BOOT bool "EFI HTTP Boot support" @@ -515,5 +550,10 @@ config EFI_HTTP_BOOT help Enabling this option adds EFI HTTP Boot support. It allows to directly boot from network. +endmenu endif + +source "lib/efi/Kconfig" + +endmenu diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c index 589d3996b68..a3aa2b8d1b9 100644 --- a/lib/efi_loader/efi_bootmgr.c +++ b/lib/efi_loader/efi_bootmgr.c @@ -380,14 +380,15 @@ err: } /** - * efi_bootmgr_release_uridp_resource() - cleanup uri device path resource + * efi_bootmgr_release_uridp() - cleanup uri device path resource * * @ctx: event context * Return: status code */ -efi_status_t efi_bootmgr_release_uridp_resource(struct uridp_context *ctx) +efi_status_t efi_bootmgr_release_uridp(struct uridp_context *ctx) { efi_status_t ret = EFI_SUCCESS; + efi_status_t ret2 = EFI_SUCCESS; if (!ctx) return ret; @@ -407,32 +408,33 @@ efi_status_t efi_bootmgr_release_uridp_resource(struct uridp_context *ctx) /* cleanup for PE-COFF image */ if (ctx->mem_handle) { - ret = efi_uninstall_multiple_protocol_interfaces( - ctx->mem_handle, &efi_guid_device_path, ctx->loaded_dp, - NULL); - if (ret != EFI_SUCCESS) + ret2 = efi_uninstall_multiple_protocol_interfaces(ctx->mem_handle, + &efi_guid_device_path, + ctx->loaded_dp, + NULL); + if (ret2 != EFI_SUCCESS) log_err("Uninstall device_path protocol failed\n"); } efi_free_pool(ctx->loaded_dp); free(ctx); - return ret; + return ret == EFI_SUCCESS ? ret2 : ret; } /** - * efi_bootmgr_image_return_notify() - return to efibootmgr callback + * efi_bootmgr_http_return() - return to efibootmgr callback * * @event: the event for which this notification function is registered * @context: event context */ -static void EFIAPI efi_bootmgr_image_return_notify(struct efi_event *event, - void *context) +static void EFIAPI efi_bootmgr_http_return(struct efi_event *event, + void *context) { efi_status_t ret; EFI_ENTRY("%p, %p", event, context); - ret = efi_bootmgr_release_uridp_resource(context); + ret = efi_bootmgr_release_uridp(context); EFI_EXIT(ret); } @@ -533,7 +535,7 @@ static efi_status_t try_load_from_uri_path(struct efi_device_path_uri *uridp, /* create event for cleanup when the image returns or error occurs */ ret = efi_create_event(EVT_NOTIFY_SIGNAL, TPL_CALLBACK, - efi_bootmgr_image_return_notify, ctx, + efi_bootmgr_http_return, ctx, &efi_guid_event_group_return_to_efibootmgr, &event); if (ret != EFI_SUCCESS) { @@ -544,7 +546,7 @@ static efi_status_t try_load_from_uri_path(struct efi_device_path_uri *uridp, return ret; err: - efi_bootmgr_release_uridp_resource(ctx); + efi_bootmgr_release_uridp(ctx); return ret; } diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c index 635088f25a1..a4ea2873038 100644 --- a/lib/efi_loader/efi_capsule.c +++ b/lib/efi_loader/efi_capsule.c @@ -20,6 +20,7 @@ #include <sort.h> #include <sysreset.h> #include <asm/global_data.h> +#include <u-boot/uuid.h> #include <crypto/pkcs7.h> #include <crypto/pkcs7_parser.h> diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c index c944c10b216..cea50c748aa 100644 --- a/lib/efi_loader/efi_console.c +++ b/lib/efi_loader/efi_console.c @@ -181,7 +181,7 @@ static efi_status_t EFIAPI efi_cout_output_string( } pos = buf; utf16_utf8_strcpy(&pos, string); - fputs(stdout, buf); + puts(buf); free(buf); /* diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index 0f684590f22..9de3b95d073 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -17,7 +17,7 @@ #include <nvme.h> #include <efi_loader.h> #include <part.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <asm-generic/unaligned.h> #include <linux/compat.h> /* U16_MAX */ diff --git a/lib/efi_loader/efi_dt_fixup.c b/lib/efi_loader/efi_dt_fixup.c index 9886e6897cd..9d017804eea 100644 --- a/lib/efi_loader/efi_dt_fixup.c +++ b/lib/efi_loader/efi_dt_fixup.c @@ -172,7 +172,7 @@ efi_dt_fixup(struct efi_dt_fixup_protocol *this, void *dtb, } fdt_set_totalsize(dtb, *buffer_size); - if (image_setup_libfdt(&img, dtb, NULL)) { + if (image_setup_libfdt(&img, dtb, false)) { log_err("failed to process device tree\n"); ret = EFI_INVALID_PARAMETER; goto out; diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c index ba5aba098c0..6650c2b8071 100644 --- a/lib/efi_loader/efi_firmware.c +++ b/lib/efi_loader/efi_firmware.c @@ -246,6 +246,55 @@ void efi_firmware_fill_version_info(struct efi_firmware_image_descriptor *image_ } /** + * efi_gen_capsule_guids - generate GUIDs for the images + * + * Generate the image_type_id for each image in the update_info.images array + * using the first compatible from the device tree and a salt + * UUID defined at build time. + * + * Returns: status code + */ +static efi_status_t efi_gen_capsule_guids(void) +{ + int ret, i; + struct uuid namespace; + const char *compatible; /* Full array including null bytes */ + struct efi_fw_image *fw_array; + + fw_array = update_info.images; + /* Check if we need to run (there are images and we didn't already generate their IDs) */ + if (!update_info.num_images || + memchr_inv(&fw_array[0].image_type_id, 0, sizeof(fw_array[0].image_type_id))) + return EFI_SUCCESS; + + ret = uuid_str_to_bin(CONFIG_EFI_CAPSULE_NAMESPACE_GUID, + (unsigned char *)&namespace, UUID_STR_FORMAT_GUID); + if (ret) { + log_debug("%s: EFI_CAPSULE_NAMESPACE_GUID is invalid: %d\n", __func__, ret); + return EFI_INVALID_PARAMETER; + } + + compatible = ofnode_read_string(ofnode_root(), "compatible"); + if (!compatible) { + log_debug("%s: model or compatible not defined\n", __func__); + return EFI_INVALID_PARAMETER; + } + + for (i = 0; i < update_info.num_images; i++) { + gen_v5_guid(&namespace, + &fw_array[i].image_type_id, + compatible, strlen(compatible), + fw_array[i].fw_name, u16_strlen(fw_array[i].fw_name) * sizeof(uint16_t), + NULL); + + log_debug("Image %ls UUID %pUl\n", fw_array[i].fw_name, + &fw_array[i].image_type_id); + } + + return EFI_SUCCESS; +} + +/** * efi_fill_image_desc_array - populate image descriptor array * @image_info_size: Size of @image_info * @image_info: Image information @@ -272,7 +321,7 @@ static efi_status_t efi_fill_image_desc_array( { size_t total_size; struct efi_fw_image *fw_array; - int i; + int i, ret; total_size = sizeof(*image_info) * update_info.num_images; @@ -283,6 +332,10 @@ static efi_status_t efi_fill_image_desc_array( } *image_info_size = total_size; + ret = efi_gen_capsule_guids(); + if (ret != EFI_SUCCESS) + return ret; + fw_array = update_info.images; *descriptor_count = update_info.num_images; *descriptor_version = EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION; diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c index 65d2116381a..96f847652ec 100644 --- a/lib/efi_loader/efi_helper.c +++ b/lib/efi_loader/efi_helper.c @@ -74,6 +74,7 @@ out: */ struct efi_device_path *efi_get_dp_from_boot(const efi_guid_t *guid) { + struct efi_device_path *file_path = NULL; struct efi_load_option lo; void *var_value; efi_uintn_t size; @@ -92,11 +93,11 @@ struct efi_device_path *efi_get_dp_from_boot(const efi_guid_t *guid) if (ret != EFI_SUCCESS) goto err; - return efi_dp_from_lo(&lo, guid); + file_path = efi_dp_from_lo(&lo, guid); err: free(var_value); - return NULL; + return file_path; } /** @@ -513,7 +514,7 @@ efi_status_t efi_install_fdt(void *fdt) return EFI_OUT_OF_RESOURCES; } - if (image_setup_libfdt(&img, fdt, NULL)) { + if (image_setup_libfdt(&img, fdt, false)) { log_err("ERROR: failed to process device tree\n"); return EFI_LOAD_ERROR; } diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index e888c52efe3..f3533f4def3 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -16,7 +16,7 @@ #include <malloc.h> #include <rtc.h> #include <search.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <crypto/pkcs7_parser.h> #include <linux/compat.h> #include <u-boot/crc.h> diff --git a/lib/efi_loader/helloworld.c b/lib/efi_loader/helloworld.c index bd72822c0b7..586177de0c8 100644 --- a/lib/efi_loader/helloworld.c +++ b/lib/efi_loader/helloworld.c @@ -2,6 +2,9 @@ /* * Hello world EFI application * + * Copyright (c) 2016 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * * Copyright 2020, Heinrich Schuchardt <xypron.glpk@gmx.de> * * This test program is used to test the invocation of an EFI application. diff --git a/lib/elf.c b/lib/elf.c index 28ec87b8e48..e767a42a3b3 100644 --- a/lib/elf.c +++ b/lib/elf.c @@ -86,7 +86,7 @@ unsigned long load_elf64_image_phdr(unsigned long addr) phdr = (Elf64_Phdr *)(addr + (ulong)ehdr->e_phoff); /* Load each program header */ - for (i = 0; i < ehdr->e_phnum; ++i) { + for (i = 0; i < ehdr->e_phnum; ++i, ++phdr) { void *dst = (void *)(ulong)phdr->p_paddr; void *src = (void *)addr + phdr->p_offset; @@ -103,7 +103,6 @@ unsigned long load_elf64_image_phdr(unsigned long addr) phdr->p_memsz - phdr->p_filesz); flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN), roundup(phdr->p_memsz, ARCH_DMA_MINALIGN)); - ++phdr; } if (ehdr->e_machine == EM_PPC64 && (ehdr->e_flags & @@ -205,7 +204,7 @@ unsigned long load_elf_image_phdr(unsigned long addr) phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff); /* Load each program header */ - for (i = 0; i < ehdr->e_phnum; ++i) { + for (i = 0; i < ehdr->e_phnum; ++i, ++phdr) { void *dst = (void *)(uintptr_t)phdr->p_paddr; void *src = (void *)addr + phdr->p_offset; @@ -222,7 +221,6 @@ unsigned long load_elf_image_phdr(unsigned long addr) phdr->p_memsz - phdr->p_filesz); flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN), roundup(phdr->p_memsz, ARCH_DMA_MINALIGN)); - ++phdr; } return ehdr->e_entry; diff --git a/lib/fwu_updates/fwu_mtd.c b/lib/fwu_updates/fwu_mtd.c index ccaba3f3115..554723046f6 100644 --- a/lib/fwu_updates/fwu_mtd.c +++ b/lib/fwu_updates/fwu_mtd.c @@ -10,7 +10,7 @@ #include <log.h> #include <malloc.h> #include <mtd.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <stdio.h> #include <dm/ofnode.h> @@ -60,10 +60,7 @@ int fwu_mtd_get_alt_num(efi_guid_t *image_id, u8 *alt_num, if (ret) return -ENOENT; - nalt = 0; - list_for_each_entry(dfu, &dfu_list, list) - nalt++; - + nalt = list_count_nodes(&dfu_list); if (!nalt) { log_warning("No entities in dfu_alt_info\n"); dfu_free_entities(); diff --git a/lib/lmb.c b/lib/lmb.c index 44f98205310..3ed570fb29b 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -6,50 +6,72 @@ * Copyright (C) 2001 Peter Bergner. */ +#include <alist.h> #include <efi_loader.h> #include <image.h> #include <mapmem.h> #include <lmb.h> #include <log.h> #include <malloc.h> +#include <spl.h> #include <asm/global_data.h> #include <asm/sections.h> +#include <linux/kernel.h> +#include <linux/sizes.h> DECLARE_GLOBAL_DATA_PTR; #define LMB_ALLOC_ANYWHERE 0 +#define LMB_ALIST_INITIAL_SIZE 4 -static void lmb_dump_region(struct lmb_region *rgn, char *name) +static struct lmb lmb; + +static void lmb_print_region_flags(enum lmb_flags flags) +{ + u64 bitpos; + const char *flag_str[] = { "none", "no-map", "no-overwrite" }; + + do { + bitpos = flags ? fls(flags) - 1 : 0; + printf("%s", flag_str[bitpos]); + flags &= ~(1ull << bitpos); + puts(flags ? ", " : "\n"); + } while (flags); +} + +static void lmb_dump_region(struct alist *lmb_rgn_lst, char *name) { + struct lmb_region *rgn = lmb_rgn_lst->data; unsigned long long base, size, end; enum lmb_flags flags; int i; - printf(" %s.cnt = 0x%lx / max = 0x%lx\n", name, rgn->cnt, rgn->max); + printf(" %s.count = 0x%x\n", name, lmb_rgn_lst->count); - for (i = 0; i < rgn->cnt; i++) { - base = rgn->region[i].base; - size = rgn->region[i].size; + for (i = 0; i < lmb_rgn_lst->count; i++) { + base = rgn[i].base; + size = rgn[i].size; end = base + size - 1; - flags = rgn->region[i].flags; + flags = rgn[i].flags; - printf(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: %x\n", - name, i, base, end, size, flags); + printf(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: ", + name, i, base, end, size); + lmb_print_region_flags(flags); } } -void lmb_dump_all_force(struct lmb *lmb) +void lmb_dump_all_force(void) { printf("lmb_dump_all:\n"); - lmb_dump_region(&lmb->memory, "memory"); - lmb_dump_region(&lmb->reserved, "reserved"); + lmb_dump_region(&lmb.free_mem, "memory"); + lmb_dump_region(&lmb.used_mem, "reserved"); } -void lmb_dump_all(struct lmb *lmb) +void lmb_dump_all(void) { #ifdef DEBUG - lmb_dump_all_force(lmb); + lmb_dump_all_force(); #endif } @@ -73,111 +95,71 @@ static long lmb_addrs_adjacent(phys_addr_t base1, phys_size_t size1, return 0; } -static long lmb_regions_overlap(struct lmb_region *rgn, unsigned long r1, +static long lmb_regions_overlap(struct alist *lmb_rgn_lst, unsigned long r1, unsigned long r2) { - phys_addr_t base1 = rgn->region[r1].base; - phys_size_t size1 = rgn->region[r1].size; - phys_addr_t base2 = rgn->region[r2].base; - phys_size_t size2 = rgn->region[r2].size; + struct lmb_region *rgn = lmb_rgn_lst->data; + + phys_addr_t base1 = rgn[r1].base; + phys_size_t size1 = rgn[r1].size; + phys_addr_t base2 = rgn[r2].base; + phys_size_t size2 = rgn[r2].size; return lmb_addrs_overlap(base1, size1, base2, size2); } -static long lmb_regions_adjacent(struct lmb_region *rgn, unsigned long r1, + +static long lmb_regions_adjacent(struct alist *lmb_rgn_lst, unsigned long r1, unsigned long r2) { - phys_addr_t base1 = rgn->region[r1].base; - phys_size_t size1 = rgn->region[r1].size; - phys_addr_t base2 = rgn->region[r2].base; - phys_size_t size2 = rgn->region[r2].size; + struct lmb_region *rgn = lmb_rgn_lst->data; + + phys_addr_t base1 = rgn[r1].base; + phys_size_t size1 = rgn[r1].size; + phys_addr_t base2 = rgn[r2].base; + phys_size_t size2 = rgn[r2].size; return lmb_addrs_adjacent(base1, size1, base2, size2); } -static void lmb_remove_region(struct lmb_region *rgn, unsigned long r) +static void lmb_remove_region(struct alist *lmb_rgn_lst, unsigned long r) { unsigned long i; + struct lmb_region *rgn = lmb_rgn_lst->data; - for (i = r; i < rgn->cnt - 1; i++) { - rgn->region[i].base = rgn->region[i + 1].base; - rgn->region[i].size = rgn->region[i + 1].size; - rgn->region[i].flags = rgn->region[i + 1].flags; + for (i = r; i < lmb_rgn_lst->count - 1; i++) { + rgn[i].base = rgn[i + 1].base; + rgn[i].size = rgn[i + 1].size; + rgn[i].flags = rgn[i + 1].flags; } - rgn->cnt--; + lmb_rgn_lst->count--; } /* Assumption: base addr of region 1 < base addr of region 2 */ -static void lmb_coalesce_regions(struct lmb_region *rgn, unsigned long r1, +static void lmb_coalesce_regions(struct alist *lmb_rgn_lst, unsigned long r1, unsigned long r2) { - rgn->region[r1].size += rgn->region[r2].size; - lmb_remove_region(rgn, r2); + struct lmb_region *rgn = lmb_rgn_lst->data; + + rgn[r1].size += rgn[r2].size; + lmb_remove_region(lmb_rgn_lst, r2); } /*Assumption : base addr of region 1 < base addr of region 2*/ -static void lmb_fix_over_lap_regions(struct lmb_region *rgn, unsigned long r1, - unsigned long r2) +static void lmb_fix_over_lap_regions(struct alist *lmb_rgn_lst, + unsigned long r1, unsigned long r2) { - phys_addr_t base1 = rgn->region[r1].base; - phys_size_t size1 = rgn->region[r1].size; - phys_addr_t base2 = rgn->region[r2].base; - phys_size_t size2 = rgn->region[r2].size; + struct lmb_region *rgn = lmb_rgn_lst->data; + + phys_addr_t base1 = rgn[r1].base; + phys_size_t size1 = rgn[r1].size; + phys_addr_t base2 = rgn[r2].base; + phys_size_t size2 = rgn[r2].size; if (base1 + size1 > base2 + size2) { printf("This will not be a case any time\n"); return; } - rgn->region[r1].size = base2 + size2 - base1; - lmb_remove_region(rgn, r2); -} - -void lmb_init(struct lmb *lmb) -{ -#if IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS) - lmb->memory.max = CONFIG_LMB_MAX_REGIONS; - lmb->reserved.max = CONFIG_LMB_MAX_REGIONS; -#else - lmb->memory.max = CONFIG_LMB_MEMORY_REGIONS; - lmb->reserved.max = CONFIG_LMB_RESERVED_REGIONS; - lmb->memory.region = lmb->memory_regions; - lmb->reserved.region = lmb->reserved_regions; -#endif - lmb->memory.cnt = 0; - lmb->reserved.cnt = 0; -} - -void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end, ulong align) -{ - ulong bank_end; - int bank; - - /* - * Reserve memory from aligned address below the bottom of U-Boot stack - * until end of U-Boot area using LMB to prevent U-Boot from overwriting - * that memory. - */ - debug("## Current stack ends at 0x%08lx ", sp); - - /* adjust sp by 4K to be safe */ - sp -= align; - for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (!gd->bd->bi_dram[bank].size || - sp < gd->bd->bi_dram[bank].start) - continue; - /* Watch out for RAM at end of address space! */ - bank_end = gd->bd->bi_dram[bank].start + - gd->bd->bi_dram[bank].size - 1; - if (sp > bank_end) - continue; - if (bank_end > end) - bank_end = end - 1; - - lmb_reserve(lmb, sp, bank_end - sp + 1); - - if (gd->flags & GD_FLG_SKIP_RELOC) - lmb_reserve(lmb, (phys_addr_t)(uintptr_t)_start, gd->mon_len); - - break; - } + rgn[r1].size = base2 + size2 - base1; + lmb_remove_region(lmb_rgn_lst, r2); } /** @@ -186,10 +168,9 @@ void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end, ulong align) * Add reservations for all EFI memory areas that are not * EFI_CONVENTIONAL_MEMORY. * - * @lmb: lmb environment * Return: 0 on success, 1 on failure */ -static __maybe_unused int efi_lmb_reserve(struct lmb *lmb) +static __maybe_unused int efi_lmb_reserve(void) { struct efi_mem_desc *memmap = NULL, *map; efi_uintn_t i, map_size = 0; @@ -201,8 +182,7 @@ static __maybe_unused int efi_lmb_reserve(struct lmb *lmb) for (i = 0, map = memmap; i < map_size / sizeof(*map); ++map, ++i) { if (map->type != EFI_CONVENTIONAL_MEMORY) { - lmb_reserve_flags(lmb, - map_to_sysmem((void *)(uintptr_t) + lmb_reserve_flags(map_to_sysmem((void *)(uintptr_t) map->physical_start), map->num_pages * EFI_PAGE_SIZE, map->type == EFI_RESERVED_MEMORY_TYPE @@ -214,64 +194,199 @@ static __maybe_unused int efi_lmb_reserve(struct lmb *lmb) return 0; } -static void lmb_reserve_common(struct lmb *lmb, void *fdt_blob) +static void lmb_reserve_uboot_region(void) +{ + int bank; + ulong end, bank_end; + phys_addr_t rsv_start; + + rsv_start = gd->start_addr_sp - CONFIG_STACK_SIZE; + end = gd->ram_top; + + /* + * Reserve memory from aligned address below the bottom of U-Boot stack + * until end of RAM area to prevent LMB from overwriting that memory. + */ + debug("## Current stack ends at 0x%08lx ", (ulong)rsv_start); + + /* adjust sp by 16K to be safe */ + rsv_start -= SZ_16K; + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + if (!gd->bd->bi_dram[bank].size || + rsv_start < gd->bd->bi_dram[bank].start) + continue; + /* Watch out for RAM at end of address space! */ + bank_end = gd->bd->bi_dram[bank].start + + gd->bd->bi_dram[bank].size - 1; + if (rsv_start > bank_end) + continue; + if (bank_end > end) + bank_end = end - 1; + + lmb_reserve_flags(rsv_start, bank_end - rsv_start + 1, + LMB_NOOVERWRITE); + + if (gd->flags & GD_FLG_SKIP_RELOC) + lmb_reserve_flags((phys_addr_t)(uintptr_t)_start, + gd->mon_len, LMB_NOOVERWRITE); + + break; + } +} + +static void lmb_reserve_common(void *fdt_blob) { - arch_lmb_reserve(lmb); - board_lmb_reserve(lmb); + lmb_reserve_uboot_region(); if (CONFIG_IS_ENABLED(OF_LIBFDT) && fdt_blob) - boot_fdt_add_mem_rsv_regions(lmb, fdt_blob); + boot_fdt_add_mem_rsv_regions(fdt_blob); if (CONFIG_IS_ENABLED(EFI_LOADER)) - efi_lmb_reserve(lmb); + efi_lmb_reserve(); +} + +static __maybe_unused void lmb_reserve_common_spl(void) +{ + phys_addr_t rsv_start; + phys_size_t rsv_size; + + /* + * Assume a SPL stack of 16KB. This must be + * more than enough for the SPL stage. + */ + if (IS_ENABLED(CONFIG_SPL_STACK_R_ADDR)) { + rsv_start = gd->start_addr_sp - 16384; + rsv_size = 16384; + lmb_reserve_flags(rsv_start, rsv_size, LMB_NOOVERWRITE); + } + + if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS)) { + /* Reserve the bss region */ + rsv_start = (phys_addr_t)(uintptr_t)__bss_start; + rsv_size = (phys_addr_t)(uintptr_t)__bss_end - + (phys_addr_t)(uintptr_t)__bss_start; + lmb_reserve_flags(rsv_start, rsv_size, LMB_NOOVERWRITE); + } } -/* Initialize the struct, add memory and call arch/board reserve functions */ -void lmb_init_and_reserve(struct lmb *lmb, struct bd_info *bd, void *fdt_blob) +/** + * lmb_add_memory() - Add memory range for LMB allocations + * + * Add the entire available memory range to the pool of memory that + * can be used by the LMB module for allocations. + * + * Return: None + */ +void lmb_add_memory(void) { int i; + phys_size_t size; + phys_addr_t rgn_top; + u64 ram_top = gd->ram_top; + struct bd_info *bd = gd->bd; - lmb_init(lmb); + /* Assume a 4GB ram_top if not defined */ + if (!ram_top) + ram_top = 0x100000000ULL; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (bd->bi_dram[i].size) { - lmb_add(lmb, bd->bi_dram[i].start, - bd->bi_dram[i].size); + size = bd->bi_dram[i].size; + if (size) { + if (bd->bi_dram[i].start > ram_top) + continue; + + rgn_top = bd->bi_dram[i].start + + bd->bi_dram[i].size; + + if (rgn_top > ram_top) + size -= rgn_top - ram_top; + + lmb_add(bd->bi_dram[i].start, size); } } - - lmb_reserve_common(lmb, fdt_blob); } -/* Initialize the struct, add memory and call arch/board reserve functions */ -void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base, - phys_size_t size, void *fdt_blob) +static long lmb_resize_regions(struct alist *lmb_rgn_lst, + unsigned long idx_start, + phys_addr_t base, phys_size_t size) { - lmb_init(lmb); - lmb_add(lmb, base, size); - lmb_reserve_common(lmb, fdt_blob); + phys_size_t rgnsize; + unsigned long rgn_cnt, idx, idx_end; + phys_addr_t rgnbase, rgnend; + phys_addr_t mergebase, mergeend; + struct lmb_region *rgn = lmb_rgn_lst->data; + + rgn_cnt = 0; + idx = idx_start; + idx_end = idx_start; + + /* + * First thing to do is to identify how many regions + * the requested region overlaps. + * If the flags match, combine all these overlapping + * regions into a single region, and remove the merged + * regions. + */ + while (idx <= lmb_rgn_lst->count - 1) { + rgnbase = rgn[idx].base; + rgnsize = rgn[idx].size; + + if (lmb_addrs_overlap(base, size, rgnbase, + rgnsize)) { + if (rgn[idx].flags != LMB_NONE) + return -1; + rgn_cnt++; + idx_end = idx; + } + idx++; + } + + /* The merged region's base and size */ + rgnbase = rgn[idx_start].base; + mergebase = min(base, rgnbase); + rgnend = rgn[idx_end].base + rgn[idx_end].size; + mergeend = max(rgnend, (base + size)); + + rgn[idx_start].base = mergebase; + rgn[idx_start].size = mergeend - mergebase; + + /* Now remove the merged regions */ + while (--rgn_cnt) + lmb_remove_region(lmb_rgn_lst, idx_start + 1); + + return 0; } -/* This routine called with relocation disabled. */ -static long lmb_add_region_flags(struct lmb_region *rgn, phys_addr_t base, +/** + * lmb_add_region_flags() - Add an lmb region to the given list + * @lmb_rgn_lst: LMB list to which region is to be added(free/used) + * @base: Start address of the region + * @size: Size of the region to be added + * @flags: Attributes of the LMB region + * + * Add a region of memory to the list. If the region does not exist, add + * it to the list. Depending on the attributes of the region to be added, + * the function might resize an already existing region or coalesce two + * adjacent regions. + * + * + * Returns: 0 if the region addition successful, -1 on failure + */ +static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base, phys_size_t size, enum lmb_flags flags) { unsigned long coalesced = 0; - long adjacent, i; + long ret, i; + struct lmb_region *rgn = lmb_rgn_lst->data; - if (rgn->cnt == 0) { - rgn->region[0].base = base; - rgn->region[0].size = size; - rgn->region[0].flags = flags; - rgn->cnt = 1; - return 0; - } + if (alist_err(lmb_rgn_lst)) + return -1; /* First try and coalesce this LMB with another. */ - for (i = 0; i < rgn->cnt; i++) { - phys_addr_t rgnbase = rgn->region[i].base; - phys_size_t rgnsize = rgn->region[i].size; - phys_size_t rgnflags = rgn->region[i].flags; + for (i = 0; i < lmb_rgn_lst->count; i++) { + phys_addr_t rgnbase = rgn[i].base; + phys_size_t rgnsize = rgn[i].size; + phys_size_t rgnflags = rgn[i].flags; phys_addr_t end = base + size - 1; phys_addr_t rgnend = rgnbase + rgnsize - 1; if (rgnbase <= base && end <= rgnend) { @@ -282,119 +397,127 @@ static long lmb_add_region_flags(struct lmb_region *rgn, phys_addr_t base, return -1; /* regions with new flags */ } - adjacent = lmb_addrs_adjacent(base, size, rgnbase, rgnsize); - if (adjacent > 0) { + ret = lmb_addrs_adjacent(base, size, rgnbase, rgnsize); + if (ret > 0) { if (flags != rgnflags) break; - rgn->region[i].base -= size; - rgn->region[i].size += size; + rgn[i].base -= size; + rgn[i].size += size; coalesced++; break; - } else if (adjacent < 0) { + } else if (ret < 0) { if (flags != rgnflags) break; - rgn->region[i].size += size; + rgn[i].size += size; coalesced++; break; } else if (lmb_addrs_overlap(base, size, rgnbase, rgnsize)) { - /* regions overlap */ - return -1; + if (flags == LMB_NONE) { + ret = lmb_resize_regions(lmb_rgn_lst, i, base, + size); + if (ret < 0) + return -1; + + coalesced++; + break; + } else { + return -1; + } } } - if (i < rgn->cnt - 1 && rgn->region[i].flags == rgn->region[i + 1].flags) { - if (lmb_regions_adjacent(rgn, i, i + 1)) { - lmb_coalesce_regions(rgn, i, i + 1); - coalesced++; - } else if (lmb_regions_overlap(rgn, i, i + 1)) { - /* fix overlapping area */ - lmb_fix_over_lap_regions(rgn, i, i + 1); - coalesced++; + if (lmb_rgn_lst->count && i < lmb_rgn_lst->count - 1) { + rgn = lmb_rgn_lst->data; + if (rgn[i].flags == rgn[i + 1].flags) { + if (lmb_regions_adjacent(lmb_rgn_lst, i, i + 1)) { + lmb_coalesce_regions(lmb_rgn_lst, i, i + 1); + coalesced++; + } else if (lmb_regions_overlap(lmb_rgn_lst, i, i + 1)) { + /* fix overlapping area */ + lmb_fix_over_lap_regions(lmb_rgn_lst, i, i + 1); + coalesced++; + } } } if (coalesced) return coalesced; - if (rgn->cnt >= rgn->max) + + if (alist_full(lmb_rgn_lst) && + !alist_expand_by(lmb_rgn_lst, lmb_rgn_lst->alloc)) return -1; + rgn = lmb_rgn_lst->data; /* Couldn't coalesce the LMB, so add it to the sorted table. */ - for (i = rgn->cnt-1; i >= 0; i--) { - if (base < rgn->region[i].base) { - rgn->region[i + 1].base = rgn->region[i].base; - rgn->region[i + 1].size = rgn->region[i].size; - rgn->region[i + 1].flags = rgn->region[i].flags; + for (i = lmb_rgn_lst->count; i >= 0; i--) { + if (i && base < rgn[i - 1].base) { + rgn[i] = rgn[i - 1]; } else { - rgn->region[i + 1].base = base; - rgn->region[i + 1].size = size; - rgn->region[i + 1].flags = flags; + rgn[i].base = base; + rgn[i].size = size; + rgn[i].flags = flags; break; } } - if (base < rgn->region[0].base) { - rgn->region[0].base = base; - rgn->region[0].size = size; - rgn->region[0].flags = flags; - } - - rgn->cnt++; + lmb_rgn_lst->count++; return 0; } -static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, +static long lmb_add_region(struct alist *lmb_rgn_lst, phys_addr_t base, phys_size_t size) { - return lmb_add_region_flags(rgn, base, size, LMB_NONE); + return lmb_add_region_flags(lmb_rgn_lst, base, size, LMB_NONE); } /* This routine may be called with relocation disabled. */ -long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size) +long lmb_add(phys_addr_t base, phys_size_t size) { - struct lmb_region *_rgn = &(lmb->memory); + struct alist *lmb_rgn_lst = &lmb.free_mem; - return lmb_add_region(_rgn, base, size); + return lmb_add_region(lmb_rgn_lst, base, size); } -long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size) +long lmb_free(phys_addr_t base, phys_size_t size) { - struct lmb_region *rgn = &(lmb->reserved); + struct lmb_region *rgn; + struct alist *lmb_rgn_lst = &lmb.used_mem; phys_addr_t rgnbegin, rgnend; phys_addr_t end = base + size - 1; int i; rgnbegin = rgnend = 0; /* supress gcc warnings */ - + rgn = lmb_rgn_lst->data; /* Find the region where (base, size) belongs to */ - for (i = 0; i < rgn->cnt; i++) { - rgnbegin = rgn->region[i].base; - rgnend = rgnbegin + rgn->region[i].size - 1; + for (i = 0; i < lmb_rgn_lst->count; i++) { + rgnbegin = rgn[i].base; + rgnend = rgnbegin + rgn[i].size - 1; if ((rgnbegin <= base) && (end <= rgnend)) break; } /* Didn't find the region */ - if (i == rgn->cnt) + if (i == lmb_rgn_lst->count) return -1; /* Check to see if we are removing entire region */ if ((rgnbegin == base) && (rgnend == end)) { - lmb_remove_region(rgn, i); + lmb_remove_region(lmb_rgn_lst, i); return 0; } /* Check to see if region is matching at the front */ if (rgnbegin == base) { - rgn->region[i].base = end + 1; - rgn->region[i].size -= size; + rgn[i].base = end + 1; + rgn[i].size -= size; return 0; } /* Check to see if the region is matching at the end */ if (rgnend == end) { - rgn->region[i].size -= size; + rgn[i].size -= size; return 0; } @@ -402,55 +525,37 @@ long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size) * We need to split the entry - adjust the current one to the * beginging of the hole and add the region after hole. */ - rgn->region[i].size = base - rgn->region[i].base; - return lmb_add_region_flags(rgn, end + 1, rgnend - end, - rgn->region[i].flags); + rgn[i].size = base - rgn[i].base; + return lmb_add_region_flags(lmb_rgn_lst, end + 1, rgnend - end, + rgn[i].flags); } -long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base, phys_size_t size, - enum lmb_flags flags) +long lmb_reserve_flags(phys_addr_t base, phys_size_t size, enum lmb_flags flags) { - struct lmb_region *_rgn = &(lmb->reserved); + struct alist *lmb_rgn_lst = &lmb.used_mem; - return lmb_add_region_flags(_rgn, base, size, flags); + return lmb_add_region_flags(lmb_rgn_lst, base, size, flags); } -long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size) +long lmb_reserve(phys_addr_t base, phys_size_t size) { - return lmb_reserve_flags(lmb, base, size, LMB_NONE); + return lmb_reserve_flags(base, size, LMB_NONE); } -static long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base, +static long lmb_overlaps_region(struct alist *lmb_rgn_lst, phys_addr_t base, phys_size_t size) { unsigned long i; + struct lmb_region *rgn = lmb_rgn_lst->data; - for (i = 0; i < rgn->cnt; i++) { - phys_addr_t rgnbase = rgn->region[i].base; - phys_size_t rgnsize = rgn->region[i].size; + for (i = 0; i < lmb_rgn_lst->count; i++) { + phys_addr_t rgnbase = rgn[i].base; + phys_size_t rgnsize = rgn[i].size; if (lmb_addrs_overlap(base, size, rgnbase, rgnsize)) break; } - return (i < rgn->cnt) ? i : -1; -} - -phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align) -{ - return lmb_alloc_base(lmb, size, align, LMB_ALLOC_ANYWHERE); -} - -phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phys_addr_t max_addr) -{ - phys_addr_t alloc; - - alloc = __lmb_alloc_base(lmb, size, align, max_addr); - - if (alloc == 0) - printf("ERROR: Failed to allocate 0x%lx bytes below 0x%lx.\n", - (ulong)size, (ulong)max_addr); - - return alloc; + return (i < lmb_rgn_lst->count) ? i : -1; } static phys_addr_t lmb_align_down(phys_addr_t addr, phys_size_t size) @@ -458,15 +563,18 @@ static phys_addr_t lmb_align_down(phys_addr_t addr, phys_size_t size) return addr & ~(size - 1); } -phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phys_addr_t max_addr) +static phys_addr_t __lmb_alloc_base(phys_size_t size, ulong align, + phys_addr_t max_addr, enum lmb_flags flags) { long i, rgn; phys_addr_t base = 0; phys_addr_t res_base; + struct lmb_region *lmb_used = lmb.used_mem.data; + struct lmb_region *lmb_memory = lmb.free_mem.data; - for (i = lmb->memory.cnt - 1; i >= 0; i--) { - phys_addr_t lmbbase = lmb->memory.region[i].base; - phys_size_t lmbsize = lmb->memory.region[i].size; + for (i = lmb.free_mem.count - 1; i >= 0; i--) { + phys_addr_t lmbbase = lmb_memory[i].base; + phys_size_t lmbsize = lmb_memory[i].size; if (lmbsize < size) continue; @@ -482,15 +590,16 @@ phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phy continue; while (base && lmbbase <= base) { - rgn = lmb_overlaps_region(&lmb->reserved, base, size); + rgn = lmb_overlaps_region(&lmb.used_mem, base, size); if (rgn < 0) { /* This area isn't reserved, take it */ - if (lmb_add_region(&lmb->reserved, base, - size) < 0) + if (lmb_add_region_flags(&lmb.used_mem, base, + size, flags) < 0) return 0; return base; } - res_base = lmb->reserved.region[rgn].base; + + res_base = lmb_used[rgn].base; if (res_base < size) break; base = lmb_align_down(res_base - size, align); @@ -499,83 +608,177 @@ phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phy return 0; } -/* - * Try to allocate a specific address range: must be in defined memory but not - * reserved - */ -phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, phys_size_t size) +phys_addr_t lmb_alloc(phys_size_t size, ulong align) +{ + return lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE); +} + +phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr) +{ + phys_addr_t alloc; + + alloc = __lmb_alloc_base(size, align, max_addr, LMB_NONE); + + if (alloc == 0) + printf("ERROR: Failed to allocate 0x%lx bytes below 0x%lx.\n", + (ulong)size, (ulong)max_addr); + + return alloc; +} + +static phys_addr_t __lmb_alloc_addr(phys_addr_t base, phys_size_t size, + enum lmb_flags flags) { long rgn; + struct lmb_region *lmb_memory = lmb.free_mem.data; /* Check if the requested address is in one of the memory regions */ - rgn = lmb_overlaps_region(&lmb->memory, base, size); + rgn = lmb_overlaps_region(&lmb.free_mem, base, size); if (rgn >= 0) { /* * Check if the requested end address is in the same memory * region we found. */ - if (lmb_addrs_overlap(lmb->memory.region[rgn].base, - lmb->memory.region[rgn].size, + if (lmb_addrs_overlap(lmb_memory[rgn].base, + lmb_memory[rgn].size, base + size - 1, 1)) { /* ok, reserve the memory */ - if (lmb_reserve(lmb, base, size) >= 0) + if (lmb_reserve_flags(base, size, flags) >= 0) return base; } } + return 0; } +/* + * Try to allocate a specific address range: must be in defined memory but not + * reserved + */ +phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size) +{ + return __lmb_alloc_addr(base, size, LMB_NONE); +} + /* Return number of bytes from a given address that are free */ -phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr) +phys_size_t lmb_get_free_size(phys_addr_t addr) { int i; long rgn; + struct lmb_region *lmb_used = lmb.used_mem.data; + struct lmb_region *lmb_memory = lmb.free_mem.data; /* check if the requested address is in the memory regions */ - rgn = lmb_overlaps_region(&lmb->memory, addr, 1); + rgn = lmb_overlaps_region(&lmb.free_mem, addr, 1); if (rgn >= 0) { - for (i = 0; i < lmb->reserved.cnt; i++) { - if (addr < lmb->reserved.region[i].base) { + for (i = 0; i < lmb.used_mem.count; i++) { + if (addr < lmb_used[i].base) { /* first reserved range > requested address */ - return lmb->reserved.region[i].base - addr; + return lmb_used[i].base - addr; } - if (lmb->reserved.region[i].base + - lmb->reserved.region[i].size > addr) { + if (lmb_used[i].base + + lmb_used[i].size > addr) { /* requested addr is in this reserved range */ return 0; } } /* if we come here: no reserved ranges above requested addr */ - return lmb->memory.region[lmb->memory.cnt - 1].base + - lmb->memory.region[lmb->memory.cnt - 1].size - addr; + return lmb_memory[lmb.free_mem.count - 1].base + + lmb_memory[lmb.free_mem.count - 1].size - addr; } return 0; } -int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags) +int lmb_is_reserved_flags(phys_addr_t addr, int flags) { int i; + struct lmb_region *lmb_used = lmb.used_mem.data; - for (i = 0; i < lmb->reserved.cnt; i++) { - phys_addr_t upper = lmb->reserved.region[i].base + - lmb->reserved.region[i].size - 1; - if ((addr >= lmb->reserved.region[i].base) && (addr <= upper)) - return (lmb->reserved.region[i].flags & flags) == flags; + for (i = 0; i < lmb.used_mem.count; i++) { + phys_addr_t upper = lmb_used[i].base + + lmb_used[i].size - 1; + if (addr >= lmb_used[i].base && addr <= upper) + return (lmb_used[i].flags & flags) == flags; } return 0; } -int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr) +static int lmb_setup(void) { - return lmb_is_reserved_flags(lmb, addr, LMB_NONE); + bool ret; + + ret = alist_init(&lmb.free_mem, sizeof(struct lmb_region), + (uint)LMB_ALIST_INITIAL_SIZE); + if (!ret) { + log_debug("Unable to initialise the list for LMB free memory\n"); + return -ENOMEM; + } + + ret = alist_init(&lmb.used_mem, sizeof(struct lmb_region), + (uint)LMB_ALIST_INITIAL_SIZE); + if (!ret) { + log_debug("Unable to initialise the list for LMB used memory\n"); + return -ENOMEM; + } + + return 0; } -__weak void board_lmb_reserve(struct lmb *lmb) +/** + * lmb_init() - Initialise the LMB module + * + * Initialise the LMB lists needed for keeping the memory map. There + * are two lists, in form of alloced list data structure. One for the + * available memory, and one for the used memory. Initialise the two + * lists as part of board init. Add memory to the available memory + * list and reserve common areas by adding them to the used memory + * list. + * + * Return: 0 on success, -ve on error + */ +int lmb_init(void) { - /* please define platform specific board_lmb_reserve() */ + int ret; + + ret = lmb_setup(); + if (ret) { + log_info("Unable to init LMB\n"); + return ret; + } + + lmb_add_memory(); + + /* Reserve the U-Boot image region once U-Boot has relocated */ + if (spl_phase() == PHASE_SPL) + lmb_reserve_common_spl(); + else if (spl_phase() == PHASE_BOARD_R) + lmb_reserve_common((void *)gd->fdt_blob); + + return 0; +} + +#if CONFIG_IS_ENABLED(UNIT_TEST) +struct lmb *lmb_get(void) +{ + return &lmb; +} + +int lmb_push(struct lmb *store) +{ + int ret; + + *store = lmb; + ret = lmb_setup(); + if (ret) + return ret; + + return 0; } -__weak void arch_lmb_reserve(struct lmb *lmb) +void lmb_pop(struct lmb *store) { - /* please define platform specific arch_lmb_reserve() */ + alist_uninit(&lmb.free_mem); + alist_uninit(&lmb.used_mem); + lmb = *store; } +#endif /* UNIT_TEST */ diff --git a/lib/uuid.c b/lib/uuid.c index dfa2320ba26..11b86ffb02e 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -7,21 +7,35 @@ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> */ -#define LOG_CATEGOT LOGC_CORE - +#ifndef USE_HOSTCC #include <command.h> #include <efi_api.h> #include <env.h> #include <rand.h> #include <time.h> -#include <uuid.h> -#include <linux/ctype.h> -#include <errno.h> #include <asm/io.h> #include <part_efi.h> #include <malloc.h> #include <dm/uclass.h> #include <rng.h> +#include <linux/ctype.h> +#include <hexdump.h> +#else +#include <stdarg.h> +#include <stdint.h> +#include <eficapsule.h> +#include <ctype.h> +#endif +#include <linux/types.h> +#include <errno.h> +#include <linux/kconfig.h> +#include <u-boot/uuid.h> +#include <u-boot/sha1.h> + +#ifdef USE_HOSTCC +/* polyfill hextoul to avoid pulling in strto.c */ +#define hextoul(cp, endp) strtoul(cp, endp, 16) +#endif int uuid_str_valid(const char *uuid) { @@ -51,6 +65,7 @@ static const struct { const char *string; efi_guid_t guid; } list_guid[] = { +#ifndef USE_HOSTCC #ifdef CONFIG_PARTITION_TYPE_GUID {"system", PARTITION_SYSTEM_GUID}, {"mbr", LEGACY_MBR_PARTITION_GUID}, @@ -231,6 +246,7 @@ static const struct { { "EFI_MEM_STATUS_CODE_REC", EFI_MEM_STATUS_CODE_REC }, { "EFI_GUID_EFI_ACPI1", EFI_GUID_EFI_ACPI1 }, #endif +#endif /* !USE_HOSTCC */ }; int uuid_guid_get_bin(const char *guid_str, unsigned char *guid_bin) @@ -266,7 +282,6 @@ int uuid_str_to_bin(const char *uuid_str, unsigned char *uuid_bin, uint64_t tmp64; if (!uuid_str_valid(uuid_str)) { - log_debug("not valid\n"); #ifdef CONFIG_PARTITION_TYPE_GUID if (!uuid_guid_get_bin(uuid_str, uuid_bin)) return 0; @@ -297,7 +312,7 @@ int uuid_str_to_bin(const char *uuid_str, unsigned char *uuid_bin, tmp16 = cpu_to_be16(hextoul(uuid_str + 19, NULL)); memcpy(uuid_bin + 8, &tmp16, 2); - tmp64 = cpu_to_be64(simple_strtoull(uuid_str + 24, NULL, 16)); + tmp64 = cpu_to_be64(hextoul(uuid_str + 24, NULL)); memcpy(uuid_bin + 10, (char *)&tmp64 + 2, 6); return 0; @@ -305,9 +320,9 @@ int uuid_str_to_bin(const char *uuid_str, unsigned char *uuid_bin, int uuid_str_to_le_bin(const char *uuid_str, unsigned char *uuid_bin) { - u16 tmp16; - u32 tmp32; - u64 tmp64; + uint16_t tmp16; + uint32_t tmp32; + uint64_t tmp64; if (!uuid_str_valid(uuid_str) || !uuid_bin) return -EINVAL; @@ -324,7 +339,7 @@ int uuid_str_to_le_bin(const char *uuid_str, unsigned char *uuid_bin) tmp16 = cpu_to_le16(hextoul(uuid_str + 19, NULL)); memcpy(uuid_bin + 8, &tmp16, 2); - tmp64 = cpu_to_le64(simple_strtoull(uuid_str + 24, NULL, 16)); + tmp64 = cpu_to_le64(hextoul(uuid_str + 24, NULL)); memcpy(uuid_bin + 10, &tmp64, 6); return 0; @@ -333,11 +348,11 @@ int uuid_str_to_le_bin(const char *uuid_str, unsigned char *uuid_bin) void uuid_bin_to_str(const unsigned char *uuid_bin, char *uuid_str, int str_format) { - const u8 uuid_char_order[UUID_BIN_LEN] = {0, 1, 2, 3, 4, 5, 6, 7, 8, + const uint8_t uuid_char_order[UUID_BIN_LEN] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; - const u8 guid_char_order[UUID_BIN_LEN] = {3, 2, 1, 0, 5, 4, 7, 6, 8, + const uint8_t guid_char_order[UUID_BIN_LEN] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15}; - const u8 *char_order; + const uint8_t *char_order; const char *format; int i; @@ -369,6 +384,57 @@ void uuid_bin_to_str(const unsigned char *uuid_bin, char *uuid_str, } } +static void configure_uuid(struct uuid *uuid, unsigned char version) +{ + uint16_t tmp; + + /* Configure variant/version bits */ + tmp = be16_to_cpu(uuid->time_hi_and_version); + tmp = (tmp & ~UUID_VERSION_MASK) | (version << UUID_VERSION_SHIFT); + uuid->time_hi_and_version = cpu_to_be16(tmp); + + uuid->clock_seq_hi_and_reserved &= ~UUID_VARIANT_MASK; + uuid->clock_seq_hi_and_reserved |= (UUID_VARIANT << UUID_VARIANT_SHIFT); +} + +void gen_v5_guid(const struct uuid *namespace, struct efi_guid *guid, ...) +{ + sha1_context ctx; + va_list args; + const uint8_t *data; + uint32_t *tmp32; + uint16_t *tmp16; + uint8_t hash[SHA1_SUM_LEN]; + + sha1_starts(&ctx); + /* Hash the namespace UUID as salt */ + sha1_update(&ctx, (unsigned char *)namespace, UUID_BIN_LEN); + va_start(args, guid); + + while ((data = va_arg(args, const uint8_t *))) { + unsigned int len = va_arg(args, size_t); + + sha1_update(&ctx, data, len); + } + + va_end(args); + sha1_finish(&ctx, hash); + + /* Truncate the hash into output UUID, it is already big endian */ + memcpy(guid, hash, sizeof(*guid)); + + configure_uuid((struct uuid *)guid, 5); + + /* Make little endian */ + tmp32 = (uint32_t *)&guid->b[0]; + *tmp32 = cpu_to_le32(be32_to_cpu(*tmp32)); + tmp16 = (uint16_t *)&guid->b[4]; + *tmp16 = cpu_to_le16(be16_to_cpu(*tmp16)); + tmp16 = (uint16_t *)&guid->b[6]; + *tmp16 = cpu_to_le16(be16_to_cpu(*tmp16)); +} + +#ifndef USE_HOSTCC #if defined(CONFIG_RANDOM_UUID) || defined(CONFIG_CMD_UUID) void gen_rand_uuid(unsigned char *uuid_bin) { @@ -395,13 +461,7 @@ void gen_rand_uuid(unsigned char *uuid_bin) for (i = 0; i < 4; i++) ptr[i] = rand(); - clrsetbits_be16(&uuid->time_hi_and_version, - UUID_VERSION_MASK, - UUID_VERSION << UUID_VERSION_SHIFT); - - clrsetbits_8(&uuid->clock_seq_hi_and_reserved, - UUID_VARIANT_MASK, - UUID_VARIANT << UUID_VARIANT_SHIFT); + configure_uuid(uuid, UUID_VERSION); memcpy(uuid_bin, uuid, 16); } @@ -458,3 +518,4 @@ U_BOOT_CMD(guid, CONFIG_SYS_MAXARGS, 1, do_uuid, ); #endif /* CONFIG_CMD_UUID */ #endif /* CONFIG_RANDOM_UUID || CONFIG_CMD_UUID */ +#endif /* !USE_HOSTCC */ diff --git a/lib/vsprintf.c b/lib/vsprintf.c index cfd1f1914ed..e5802866632 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -18,7 +18,7 @@ #include <div64.h> #include <hexdump.h> #include <stdarg.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <stdio.h> #include <vsprintf.h> #include <linux/ctype.h> diff --git a/net/bootp.c b/net/bootp.c index 9dfb50749b4..512ab2ed7c8 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -15,7 +15,7 @@ #include <log.h> #include <net.h> #include <rand.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <linux/delay.h> #include <net/tftp.h> #include "bootp.h" diff --git a/net/net.c b/net/net.c index d9bc9df643f..1e0b7c85624 100644 --- a/net/net.c +++ b/net/net.c @@ -334,17 +334,22 @@ void net_auto_load(void) net_set_state(NETLOOP_SUCCESS); return; } - if (net_check_prereq(TFTPGET)) { -/* We aren't expecting to get a serverip, so just accept the assigned IP */ - if (IS_ENABLED(CONFIG_BOOTP_SERVERIP)) { - net_set_state(NETLOOP_SUCCESS); - } else { - printf("Cannot autoload with TFTPGET\n"); - net_set_state(NETLOOP_FAIL); + if (IS_ENABLED(CONFIG_CMD_TFTPBOOT)) { + if (net_check_prereq(TFTPGET)) { + /* + * We aren't expecting to get a serverip, so just + * accept the assigned IP + */ + if (IS_ENABLED(CONFIG_BOOTP_SERVERIP)) { + net_set_state(NETLOOP_SUCCESS); + } else { + printf("Cannot autoload with TFTPGET\n"); + net_set_state(NETLOOP_FAIL); + } + return; } - return; + tftp_start(TFTPGET); } - tftp_start(TFTPGET); } static int net_init_loop(void) diff --git a/net/tftp.c b/net/tftp.c index 2e073183d5a..b5d227d8bc2 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -82,9 +82,7 @@ static ulong tftp_block_wrap; static ulong tftp_block_wrap_offset; static int tftp_state; static ulong tftp_load_addr; -#ifdef CONFIG_LMB static ulong tftp_load_size; -#endif #ifdef CONFIG_TFTP_TSIZE /* The file size reported by the server */ static int tftp_tsize; @@ -160,19 +158,20 @@ static inline int store_block(int block, uchar *src, unsigned int len) ulong store_addr = tftp_load_addr + offset; void *ptr; -#ifdef CONFIG_LMB - ulong end_addr = tftp_load_addr + tftp_load_size; + if (CONFIG_IS_ENABLED(LMB)) { + ulong end_addr = tftp_load_addr + tftp_load_size; - if (!end_addr) - end_addr = ULONG_MAX; + if (!end_addr) + end_addr = ULONG_MAX; - if (store_addr < tftp_load_addr || - store_addr + len > end_addr) { - puts("\nTFTP error: "); - puts("trying to overwrite reserved memory...\n"); - return -1; + if (store_addr < tftp_load_addr || + store_addr + len > end_addr) { + puts("\nTFTP error: "); + puts("trying to overwrite reserved memory...\n"); + return -1; + } } -#endif + ptr = map_sysmem(store_addr, len); memcpy(ptr, src, len); unmap_sysmem(ptr); @@ -716,18 +715,16 @@ static void tftp_timeout_handler(void) /* Initialize tftp_load_addr and tftp_load_size from image_load_addr and lmb */ static int tftp_init_load_addr(void) { -#ifdef CONFIG_LMB - struct lmb lmb; - phys_size_t max_size; + if (CONFIG_IS_ENABLED(LMB)) { + phys_size_t max_size; - lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); + max_size = lmb_get_free_size(image_load_addr); + if (!max_size) + return -1; - max_size = lmb_get_free_size(&lmb, image_load_addr); - if (!max_size) - return -1; + tftp_load_size = max_size; + } - tftp_load_size = max_size; -#endif tftp_load_addr = image_load_addr; return 0; } diff --git a/net/wget.c b/net/wget.c index 945bfd26693..4a168641c65 100644 --- a/net/wget.c +++ b/net/wget.c @@ -73,12 +73,9 @@ static ulong wget_load_size; */ static int wget_init_load_size(void) { - struct lmb lmb; phys_size_t max_size; - lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); - - max_size = lmb_get_free_size(&lmb, image_load_addr); + max_size = lmb_get_free_size(image_load_addr); if (!max_size) return -1; @@ -99,7 +96,7 @@ static inline int store_block(uchar *src, unsigned int offset, unsigned int len) ulong newsize = offset + len; uchar *ptr; - if (IS_ENABLED(CONFIG_LMB)) { + if (CONFIG_IS_ENABLED(LMB)) { ulong end_addr = image_load_addr + wget_load_size; if (!end_addr) @@ -496,7 +493,7 @@ void wget_start(void) debug_cond(DEBUG_WGET, "\nwget:Load address: 0x%lx\nLoading: *\b", image_load_addr); - if (IS_ENABLED(CONFIG_LMB)) { + if (CONFIG_IS_ENABLED(LMB)) { if (wget_init_load_size()) { printf("\nwget error: "); printf("trying to overwrite reserved memory...\n"); diff --git a/scripts/kconfig/symbol.c b/scripts/kconfig/symbol.c index 703b9b899ee..5245804bb33 100644 --- a/scripts/kconfig/symbol.c +++ b/scripts/kconfig/symbol.c @@ -1117,7 +1117,7 @@ static void sym_check_print_recursive(struct symbol *last_sym) } fprintf(stderr, - "For a resolution refer to Documentation/kbuild/kconfig-language.txt\n" + "For a resolution refer to Documentation/kbuild/kconfig-language.rst\n" "subsection \"Kconfig recursive dependency limitations\"\n" "\n"); diff --git a/scripts/kconfig/tests/err_recursive_dep/expected_stderr b/scripts/kconfig/tests/err_recursive_dep/expected_stderr index 84679b10465..c9f4abf9a79 100644 --- a/scripts/kconfig/tests/err_recursive_dep/expected_stderr +++ b/scripts/kconfig/tests/err_recursive_dep/expected_stderr @@ -1,38 +1,38 @@ Kconfig:11:error: recursive dependency detected! Kconfig:11: symbol B is selected by B -For a resolution refer to Documentation/kbuild/kconfig-language.txt +For a resolution refer to Documentation/kbuild/kconfig-language.rst subsection "Kconfig recursive dependency limitations" Kconfig:5:error: recursive dependency detected! Kconfig:5: symbol A depends on A -For a resolution refer to Documentation/kbuild/kconfig-language.txt +For a resolution refer to Documentation/kbuild/kconfig-language.rst subsection "Kconfig recursive dependency limitations" Kconfig:17:error: recursive dependency detected! Kconfig:17: symbol C1 depends on C2 Kconfig:21: symbol C2 depends on C1 -For a resolution refer to Documentation/kbuild/kconfig-language.txt +For a resolution refer to Documentation/kbuild/kconfig-language.rst subsection "Kconfig recursive dependency limitations" Kconfig:32:error: recursive dependency detected! Kconfig:32: symbol D2 is selected by D1 Kconfig:27: symbol D1 depends on D2 -For a resolution refer to Documentation/kbuild/kconfig-language.txt +For a resolution refer to Documentation/kbuild/kconfig-language.rst subsection "Kconfig recursive dependency limitations" Kconfig:37:error: recursive dependency detected! Kconfig:37: symbol E1 depends on E2 Kconfig:42: symbol E2 is implied by E1 -For a resolution refer to Documentation/kbuild/kconfig-language.txt +For a resolution refer to Documentation/kbuild/kconfig-language.rst subsection "Kconfig recursive dependency limitations" Kconfig:60:error: recursive dependency detected! Kconfig:60: symbol G depends on G -For a resolution refer to Documentation/kbuild/kconfig-language.txt +For a resolution refer to Documentation/kbuild/kconfig-language.rst subsection "Kconfig recursive dependency limitations" Kconfig:51:error: recursive dependency detected! Kconfig:51: symbol F2 depends on F1 Kconfig:49: symbol F1 default value contains F2 -For a resolution refer to Documentation/kbuild/kconfig-language.txt +For a resolution refer to Documentation/kbuild/kconfig-language.rst subsection "Kconfig recursive dependency limitations" diff --git a/test/boot/Makefile b/test/boot/Makefile index 8ec5daa7bfe..d8eded20d4f 100644 --- a/test/boot/Makefile +++ b/test/boot/Makefile @@ -2,12 +2,15 @@ # # Copyright 2021 Google LLC +ifdef CONFIG_UT_BOOTSTD obj-$(CONFIG_BOOTSTD) += bootdev.o bootstd_common.o bootflow.o bootmeth.o obj-$(CONFIG_FIT) += image.o -obj-$(CONFIG_MEASURED_BOOT) += measurement.o obj-$(CONFIG_EXPO) += expo.o obj-$(CONFIG_CEDIT) += cedit.o +endif + +obj-$(CONFIG_MEASURED_BOOT) += measurement.o ifdef CONFIG_OF_LIVE obj-$(CONFIG_BOOTMETH_VBE_SIMPLE) += vbe_simple.o diff --git a/test/boot/expo.c b/test/boot/expo.c index 4b24f504e21..9b4aa803eb1 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -702,9 +702,7 @@ static int expo_test_build(struct unit_test_state *uts) txt = scene_obj_find(scn, item->label_id, SCENEOBJT_NONE); ut_asserteq_str("2 GHz", expo_get_str(exp, txt->str_id)); - count = 0; - list_for_each_entry(item, &menu->item_head, sibling) - count++; + count = list_count_nodes(&menu->item_head); ut_asserteq(3, count); expo_destroy(exp); diff --git a/test/cmd/Makefile b/test/cmd/Makefile index 478ef4c6f05..8f2134998ad 100644 --- a/test/cmd/Makefile +++ b/test/cmd/Makefile @@ -30,7 +30,7 @@ ifdef CONFIG_SANDBOX obj-$(CONFIG_CMD_MBR) += mbr.o obj-$(CONFIG_CMD_READ) += rw.o obj-$(CONFIG_CMD_SETEXPR) += setexpr.o +obj-$(CONFIG_CMD_WGET) += wget.o obj-$(CONFIG_ARM_FFA_TRANSPORT) += armffa.o endif obj-$(CONFIG_CMD_TEMPERATURE) += temperature.o -obj-$(CONFIG_CMD_WGET) += wget.o diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c index 810174fe8d1..770b3bfb560 100644 --- a/test/cmd/bdinfo.c +++ b/test/cmd/bdinfo.c @@ -5,6 +5,7 @@ * Copyright 2023 Marek Vasut <marek.vasut+renesas@mailbox.org> */ +#include <alist.h> #include <console.h> #include <mapmem.h> #include <asm/global_data.h> @@ -99,44 +100,39 @@ static int test_video_info(struct unit_test_state *uts) } static int lmb_test_dump_region(struct unit_test_state *uts, - struct lmb_region *rgn, char *name) + struct alist *lmb_rgn_lst, char *name) { + struct lmb_region *rgn = lmb_rgn_lst->data; unsigned long long base, size, end; enum lmb_flags flags; int i; - ut_assert_nextline(" %s.cnt = 0x%lx / max = 0x%lx", name, rgn->cnt, rgn->max); + ut_assert_nextline(" %s.count = 0x%hx", name, lmb_rgn_lst->count); - for (i = 0; i < rgn->cnt; i++) { - base = rgn->region[i].base; - size = rgn->region[i].size; + for (i = 0; i < lmb_rgn_lst->count; i++) { + base = rgn[i].base; + size = rgn[i].size; end = base + size - 1; - flags = rgn->region[i].flags; - - /* - * this entry includes the stack (get_sp()) on many platforms - * so will different each time lmb_init_and_reserve() is called. - * We could instead have the bdinfo command put its lmb region - * in a known location, so we can check it directly, rather than - * calling lmb_init_and_reserve() to create a new (and hopefully - * identical one). But for now this seems good enough. - */ + flags = rgn[i].flags; + if (!IS_ENABLED(CONFIG_SANDBOX) && i == 3) { ut_assert_nextlinen(" %s[%d]\t[", name, i); continue; } - ut_assert_nextline(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: %x", - name, i, base, end, size, flags); + ut_assert_nextlinen(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: ", + name, i, base, end, size); } return 0; } -static int lmb_test_dump_all(struct unit_test_state *uts, struct lmb *lmb) +static int lmb_test_dump_all(struct unit_test_state *uts) { + struct lmb *lmb = lmb_get(); + ut_assert_nextline("lmb_dump_all:"); - ut_assertok(lmb_test_dump_region(uts, &lmb->memory, "memory")); - ut_assertok(lmb_test_dump_region(uts, &lmb->reserved, "reserved")); + ut_assertok(lmb_test_dump_region(uts, &lmb->free_mem, "memory")); + ut_assertok(lmb_test_dump_region(uts, &lmb->used_mem, "reserved")); return 0; } @@ -185,9 +181,6 @@ static int bdinfo_test_all(struct unit_test_state *uts) ut_assert(map_to_sysmem(gd->fdt_blob) == env_get_hex("fdtcontroladdr", 0x1234)); ut_assertok(test_num_l(uts, "fdt_blob", (ulong)map_to_sysmem(gd->fdt_blob))); - ut_assertok(test_num_l(uts, "new_fdt", - (ulong)map_to_sysmem(gd->new_fdt))); - ut_assertok(test_num_l(uts, "fdt_size", (ulong)gd->fdt_size)); if (IS_ENABLED(CONFIG_VIDEO)) ut_assertok(test_video_info(uts)); @@ -198,10 +191,7 @@ static int bdinfo_test_all(struct unit_test_state *uts) #endif if (IS_ENABLED(CONFIG_LMB) && gd->fdt_blob) { - struct lmb lmb; - - lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); - ut_assertok(lmb_test_dump_all(uts, &lmb)); + ut_assertok(lmb_test_dump_all(uts)); if (IS_ENABLED(CONFIG_OF_REAL)) ut_assert_nextline("devicetree = %s", fdtdec_get_srcname()); } @@ -239,7 +229,7 @@ static int bdinfo_test_full(struct unit_test_state *uts) ut_assertok(bdinfo_test_all(uts)); ut_assertok(run_commandf("bdinfo -a")); ut_assertok(bdinfo_test_all(uts)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -259,7 +249,7 @@ static int bdinfo_test_help(struct unit_test_state *uts) ut_assert_nextlinen("Usage:"); ut_assert_nextlinen("bdinfo"); } - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -273,7 +263,7 @@ static int bdinfo_test_memory(struct unit_test_state *uts) ut_assertok(bdinfo_test_all(uts)); else ut_assertok(bdinfo_check_mem(uts)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -287,7 +277,7 @@ static int bdinfo_test_eth(struct unit_test_state *uts) ut_assertok(bdinfo_test_all(uts)); else if (IS_ENABLED(CONFIG_CMD_NET)) ut_assertok(test_eth(uts)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } diff --git a/test/cmd/exit.c b/test/cmd/exit.c index 093f51b4dfc..af58a57fca7 100644 --- a/test/cmd/exit.c +++ b/test/cmd/exit.c @@ -36,14 +36,14 @@ static int cmd_exit_test(struct unit_test_state *uts) ut_assertok(run_commandf("setenv foo 'echo bar ; exit %d ; echo baz' ; run foo ; echo $?", i)); ut_assert_nextline("bar"); ut_assert_nextline("%d", i > 0 ? i : 0); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); ut_assertok(run_commandf("setenv foo 'echo bar ; exit %d ; echo baz' ; run foo && echo quux ; echo $?", i)); ut_assert_nextline("bar"); if (i <= 0) ut_assert_nextline("quux"); ut_assert_nextline("%d", i > 0 ? i : 0); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); ut_assertok(run_commandf("setenv foo 'echo bar ; exit %d ; echo baz' ; run foo || echo quux ; echo $?", i)); ut_assert_nextline("bar"); @@ -51,61 +51,61 @@ static int cmd_exit_test(struct unit_test_state *uts) ut_assert_nextline("quux"); /* Either 'exit' returns 0, or 'echo quux' returns 0 */ ut_assert_nextline("0"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); } /* Validate that 'exit' behaves the same way as 'exit 0' */ ut_assertok(run_commandf("setenv foo 'echo bar ; exit ; echo baz' ; run foo ; echo $?")); ut_assert_nextline("bar"); ut_assert_nextline("0"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); ut_assertok(run_commandf("setenv foo 'echo bar ; exit ; echo baz' ; run foo && echo quux ; echo $?")); ut_assert_nextline("bar"); ut_assert_nextline("quux"); ut_assert_nextline("0"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); ut_assertok(run_commandf("setenv foo 'echo bar ; exit ; echo baz' ; run foo || echo quux ; echo $?")); ut_assert_nextline("bar"); /* Either 'exit' returns 0, or 'echo quux' returns 0 */ ut_assert_nextline("0"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Validate that return value still propagates from 'run' command */ ut_assertok(run_commandf("setenv foo 'echo bar ; true' ; run foo ; echo $?")); ut_assert_nextline("bar"); ut_assert_nextline("0"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); ut_assertok(run_commandf("setenv foo 'echo bar ; true' ; run foo && echo quux ; echo $?")); ut_assert_nextline("bar"); ut_assert_nextline("quux"); ut_assert_nextline("0"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); ut_assertok(run_commandf("setenv foo 'echo bar ; true' ; run foo || echo quux ; echo $?")); ut_assert_nextline("bar"); /* The 'true' returns 0 */ ut_assert_nextline("0"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); ut_assertok(run_commandf("setenv foo 'echo bar ; false' ; run foo ; echo $?")); ut_assert_nextline("bar"); ut_assert_nextline("1"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); ut_assertok(run_commandf("setenv foo 'echo bar ; false' ; run foo && echo quux ; echo $?")); ut_assert_nextline("bar"); ut_assert_nextline("1"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); ut_assertok(run_commandf("setenv foo 'echo bar ; false' ; run foo || echo quux ; echo $?")); ut_assert_nextline("bar"); ut_assert_nextline("quux"); /* The 'echo quux' returns 0 */ ut_assert_nextline("0"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } diff --git a/test/cmd/fdt.c b/test/cmd/fdt.c index ac0d6f06150..e64785101cd 100644 --- a/test/cmd/fdt.c +++ b/test/cmd/fdt.c @@ -171,7 +171,7 @@ static int fdt_test_addr(struct unit_test_state *uts) ut_assertok(run_command("fdt addr -c", 0)); ut_assert_nextline("Control fdt: %08lx", (ulong)map_to_sysmem(gd->fdt_blob)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* The working fdt is not set, so this should fail */ set_working_fdt_addr(0); @@ -184,13 +184,13 @@ static int fdt_test_addr(struct unit_test_state *uts) */ if (IS_ENABLED(CONFIG_SANDBOX)) ut_assert_nextline("libfdt fdt_check_header(): FDT_ERR_BADMAGIC"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Set up a working FDT and try again */ ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt), &addr)); ut_assertok(run_command("fdt addr", 0)); ut_assert_nextline("Working fdt: %08lx", (ulong)map_to_sysmem(fdt)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Set the working FDT */ set_working_fdt_addr(0); @@ -198,7 +198,7 @@ static int fdt_test_addr(struct unit_test_state *uts) ut_assertok(run_commandf("fdt addr %08lx", addr)); ut_assert_nextline("Working FDT set to %lx", addr); ut_asserteq(addr, map_to_sysmem(working_fdt)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); set_working_fdt_addr(0); ut_assert_nextline("Working FDT set to 0"); @@ -210,13 +210,13 @@ static int fdt_test_addr(struct unit_test_state *uts) gd->fdt_blob = fdt_blob; ut_assertok(ret); ut_asserteq(addr, map_to_sysmem(new_fdt)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test setting an invalid FDT */ fdt[0] = 123; ut_asserteq(1, run_commandf("fdt addr %08lx", addr)); ut_assert_nextline("libfdt fdt_check_header(): FDT_ERR_BADMAGIC"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test detecting an invalid FDT */ fdt[0] = 123; @@ -224,7 +224,7 @@ static int fdt_test_addr(struct unit_test_state *uts) ut_assert_nextline("Working FDT set to %lx", addr); ut_asserteq(1, run_commandf("fdt addr")); ut_assert_nextline("libfdt fdt_check_header(): FDT_ERR_BADMAGIC"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -242,18 +242,18 @@ static int fdt_test_addr_resize(struct unit_test_state *uts) /* Test setting and resizing the working FDT to a larger size */ ut_assertok(run_commandf("fdt addr %08lx %x", addr, newsize)); ut_assert_nextline("Working FDT set to %lx", addr); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Try shrinking it */ ut_assertok(run_commandf("fdt addr %08lx %zx", addr, sizeof(fdt) / 4)); ut_assert_nextline("Working FDT set to %lx", addr); ut_assert_nextline("New length %d < existing length %d, ignoring", (int)sizeof(fdt) / 4, newsize); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* ...quietly */ ut_assertok(run_commandf("fdt addr -q %08lx %zx", addr, sizeof(fdt) / 4)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* We cannot easily provoke errors in fdt_open_into(), so ignore that */ @@ -280,12 +280,12 @@ static int fdt_test_move(struct unit_test_state *uts) /* Test moving the working FDT to a new location */ ut_assertok(run_commandf("fdt move %08lx %08lx %x", addr, newaddr, ts)); ut_assert_nextline("Working FDT set to %lx", newaddr); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Compare the source and destination DTs */ ut_assertok(run_commandf("cmp.b %08lx %08lx %x", addr, newaddr, ts)); ut_assert_nextline("Total of %d byte(s) were the same", ts); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -306,7 +306,7 @@ static int fdt_test_resize(struct unit_test_state *uts) /* Test resizing the working FDT and verify the new space was added */ ut_assertok(run_commandf("fdt resize %x", newsize)); ut_asserteq(ts + newsize, fdt_totalsize(fdt)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -325,7 +325,7 @@ static int fdt_test_print_list_common(struct unit_test_state *uts, ut_assert_nextline("\t#size-cells = <0x00000000>;"); ut_assert_nextline("\tcompatible = \"u-boot,fdt-subnode-test-device\";"); ut_assert_nextline("};"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* * Test printing/listing the working FDT @@ -333,7 +333,7 @@ static int fdt_test_print_list_common(struct unit_test_state *uts, */ ut_assertok(run_commandf("fdt %s / model", opc)); ut_assert_nextline("model = \"U-Boot FDT test\""); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* * Test printing/listing the working FDT @@ -341,7 +341,7 @@ static int fdt_test_print_list_common(struct unit_test_state *uts, */ ut_assertok(run_commandf("fdt %s %s compatible", opc, node)); ut_assert_nextline("compatible = \"u-boot,fdt-test-device1\""); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* * Test printing/listing the working FDT @@ -349,7 +349,7 @@ static int fdt_test_print_list_common(struct unit_test_state *uts, */ ut_assertok(run_commandf("fdt %s %s clock-names", opc, node)); ut_assert_nextline("clock-names = \"fixed\", \"i2c\", \"spi\", \"uart2\", \"uart1\""); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* * Test printing/listing the working FDT @@ -357,7 +357,7 @@ static int fdt_test_print_list_common(struct unit_test_state *uts, */ ut_assertok(run_commandf("fdt %s %s clock-frequency", opc, node)); ut_assert_nextline("clock-frequency = <0x00fde800>"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* * Test printing/listing the working FDT @@ -370,7 +370,7 @@ static int fdt_test_print_list_common(struct unit_test_state *uts, * since the beginning of the command 'fdt', keep it. */ ut_assert_nextline("%s u-boot,empty-property", node); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* * Test printing/listing the working FDT @@ -378,7 +378,7 @@ static int fdt_test_print_list_common(struct unit_test_state *uts, */ ut_assertok(run_commandf("fdt %s %s regs", opc, node)); ut_assert_nextline("regs = <0x00001234 0x00001000>"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -424,7 +424,7 @@ static int fdt_test_print_list(struct unit_test_state *uts, bool print) } ut_assert_nextline("\t};"); ut_assert_nextline("};"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); ret = fdt_test_print_list_common(uts, opc, "/test-node@1234"); if (!ret) @@ -457,7 +457,7 @@ static int fdt_test_get_value_string(struct unit_test_state *uts, ut_asserteq_str(strres, env_get("var")); else ut_asserteq(intres, env_get_hex("var", 0x1234)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -501,16 +501,16 @@ static int fdt_test_get_value_common(struct unit_test_state *uts, /* Test missing 10th element of $node node clock-names property */ ut_asserteq(1, run_commandf("fdt get value ften %s clock-names 10", node)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test missing 10th element of $node node regs property */ ut_asserteq(1, run_commandf("fdt get value ften %s regs 10", node)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting default element of $node node nonexistent property */ ut_asserteq(1, run_commandf("fdt get value fnone %s nonexistent", node)); ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -528,17 +528,17 @@ static int fdt_test_get_value(struct unit_test_state *uts) /* Test getting default element of /nonexistent node */ ut_asserteq(1, run_command("fdt get value fnode /nonexistent nonexistent", 1)); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting default element of bad alias */ ut_asserteq(1, run_command("fdt get value vbadalias badalias nonexistent", 1)); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting default element of nonexistent alias */ ut_asserteq(1, run_command("fdt get value vnoalias noalias nonexistent", 1)); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -554,58 +554,58 @@ static int fdt_test_get_name(struct unit_test_state *uts) /* Test getting name of node 0 in /, which is /aliases node */ ut_assertok(run_command("fdt get name nzero / 0", 0)); ut_asserteq_str("aliases", env_get("nzero")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting name of node 1 in /, which is /test-node@1234 node */ ut_assertok(run_command("fdt get name none / 1", 0)); ut_asserteq_str("test-node@1234", env_get("none")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting name of node -1 in /, which is /aliases node, same as 0 */ ut_assertok(run_command("fdt get name nmone / -1", 0)); ut_asserteq_str("aliases", env_get("nmone")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting name of node 2 in /, which does not exist */ ut_asserteq(1, run_command("fdt get name ntwo / 2", 1)); ut_assert_nextline("libfdt node not found"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting name of node 0 in /test-node@1234, which is /subnode node */ ut_assertok(run_command("fdt get name snzero /test-node@1234 0", 0)); ut_asserteq_str("subnode", env_get("snzero")); ut_assertok(run_command("fdt get name asnzero testnodealias 0", 0)); ut_asserteq_str("subnode", env_get("asnzero")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting name of node 1 in /test-node@1234, which does not exist */ ut_asserteq(1, run_command("fdt get name snone /test-node@1234 1", 1)); ut_assert_nextline("libfdt node not found"); ut_asserteq(1, run_command("fdt get name asnone testnodealias 1", 1)); ut_assert_nextline("libfdt node not found"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting name of node -1 in /test-node@1234, which is /subnode node, same as 0 */ ut_assertok(run_command("fdt get name snmone /test-node@1234 -1", 0)); ut_asserteq_str("subnode", env_get("snmone")); ut_assertok(run_command("fdt get name asnmone testnodealias -1", 0)); ut_asserteq_str("subnode", env_get("asnmone")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting name of nonexistent node */ ut_asserteq(1, run_command("fdt get name nonode /nonexistent 0", 1)); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting name of bad alias */ ut_asserteq(1, run_command("fdt get name vbadalias badalias 0", 1)); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting name of nonexistent alias */ ut_asserteq(1, run_command("fdt get name vnoalias noalias 0", 1)); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -628,7 +628,7 @@ static int fdt_test_get_addr_common(struct unit_test_state *uts, char *fdt, ut_assertok(run_commandf("fdt get addr pstr %s %s", path, prop)); ut_asserteq((ulong)map_sysmem(env_get_hex("fdtaddr", 0x1234), 0), (ulong)(map_sysmem(env_get_hex("pstr", 0x1234), 0) - offset)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -670,12 +670,12 @@ static int fdt_test_get_addr(struct unit_test_state *uts) /* Test getting address of node /test-node@1234/subnode non-existent property "noprop" */ ut_asserteq(1, run_command("fdt get addr pnoprop /test-node@1234/subnode noprop", 1)); ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting address of non-existent node /test-node@1234/nonode@1 property "noprop" */ ut_asserteq(1, run_command("fdt get addr pnonode /test-node@1234/nonode@1 noprop", 1)); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -691,7 +691,7 @@ static int fdt_test_get_size_common(struct unit_test_state *uts, ut_assertok(run_commandf("fdt get size sstr %s", path)); } ut_asserteq(val, env_get_hex("sstr", 0x1234)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -742,27 +742,27 @@ static int fdt_test_get_size(struct unit_test_state *uts) ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND"); ut_asserteq(1, run_command("fdt get size pnoprop subnodealias noprop", 1)); ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting size of non-existent node /test-node@1234/nonode@1 property "noprop" */ ut_asserteq(1, run_command("fdt get size pnonode /test-node@1234/nonode@1 noprop", 1)); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting node count of non-existent node /test-node@1234/nonode@1 */ ut_asserteq(1, run_command("fdt get size pnonode /test-node@1234/nonode@1", 1)); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting node count of bad alias badalias */ ut_asserteq(1, run_command("fdt get size pnonode badalias noprop", 1)); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting node count of non-existent alias noalias */ ut_asserteq(1, run_command("fdt get size pnonode noalias", 1)); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -793,7 +793,7 @@ static int fdt_test_set_single(struct unit_test_state *uts, ut_asserteq(ival, env_get_hex("svar", 0x1234)); else ut_assertnull(env_get("svar")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -842,7 +842,7 @@ static int fdt_test_set_multi(struct unit_test_state *uts, ut_asserteq(ival2, env_get_hex("svar2", 0x1234)); ut_assertnull(env_get("svarn")); } - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -889,17 +889,17 @@ static int fdt_test_set(struct unit_test_state *uts) /* Test setting property of non-existent node */ ut_asserteq(1, run_command("fdt set /no-node noprop", 1)); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test setting property of non-existent alias */ ut_asserteq(1, run_command("fdt set noalias noprop", 1)); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test setting property of bad alias */ ut_asserteq(1, run_command("fdt set badalias noprop", 1)); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -918,46 +918,46 @@ static int fdt_test_mknode(struct unit_test_state *uts) ut_assertok(run_commandf("fdt list /newnode")); ut_assert_nextline("newnode {"); ut_assert_nextline("};"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test creation of new node in /test-node@1234 */ ut_assertok(run_commandf("fdt mknode /test-node@1234 newsubnode")); ut_assertok(run_commandf("fdt list /test-node@1234/newsubnode")); ut_assert_nextline("newsubnode {"); ut_assert_nextline("};"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test creation of new node in /test-node@1234 by alias */ ut_assertok(run_commandf("fdt mknode testnodealias newersubnode")); ut_assertok(run_commandf("fdt list testnodealias/newersubnode")); ut_assert_nextline("newersubnode {"); ut_assert_nextline("};"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test creation of new node in /test-node@1234 over existing node */ ut_asserteq(1, run_commandf("fdt mknode testnodealias newsubnode")); ut_assert_nextline("libfdt fdt_add_subnode(): FDT_ERR_EXISTS"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test creation of new node in /test-node@1234 by alias over existing node */ ut_asserteq(1, run_commandf("fdt mknode testnodealias newersubnode")); ut_assert_nextline("libfdt fdt_add_subnode(): FDT_ERR_EXISTS"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test creation of new node in non-existent node */ ut_asserteq(1, run_commandf("fdt mknode /no-node newnosubnode")); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test creation of new node in non-existent alias */ ut_asserteq(1, run_commandf("fdt mknode noalias newfailsubnode")); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test creation of new node in bad alias */ ut_asserteq(1, run_commandf("fdt mknode badalias newbadsubnode")); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -976,7 +976,7 @@ static int fdt_test_rm(struct unit_test_state *uts) ut_assertok(run_commandf("fdt rm / compatible")); ut_asserteq(1, run_commandf("fdt print / compatible")); ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test removal of property clock-names in subnode /test-node@1234 */ ut_assertok(run_commandf("fdt print /test-node@1234 clock-names")); @@ -984,7 +984,7 @@ static int fdt_test_rm(struct unit_test_state *uts) ut_assertok(run_commandf("fdt rm /test-node@1234 clock-names")); ut_asserteq(1, run_commandf("fdt print /test-node@1234 clock-names")); ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test removal of property u-boot,empty-property in subnode /test-node@1234 by alias */ ut_assertok(run_commandf("fdt print testnodealias u-boot,empty-property")); @@ -992,44 +992,44 @@ static int fdt_test_rm(struct unit_test_state *uts) ut_assertok(run_commandf("fdt rm testnodealias u-boot,empty-property")); ut_asserteq(1, run_commandf("fdt print testnodealias u-boot,empty-property")); ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test removal of non-existent property noprop in subnode /test-node@1234 */ ut_asserteq(1, run_commandf("fdt rm /test-node@1234 noprop")); ut_assert_nextline("libfdt fdt_delprop(): FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test removal of non-existent node /no-node@5678 */ ut_asserteq(1, run_commandf("fdt rm /no-node@5678")); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test removal of subnode /test-node@1234/subnode by alias */ ut_assertok(run_commandf("fdt rm subnodealias")); ut_asserteq(1, run_commandf("fdt print /test-node@1234/subnode")); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test removal of node by non-existent alias */ ut_asserteq(1, run_commandf("fdt rm noalias")); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test removal of node by bad alias */ ut_asserteq(1, run_commandf("fdt rm noalias")); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test removal of node /test-node@1234 */ ut_assertok(run_commandf("fdt rm /test-node@1234")); ut_asserteq(1, run_commandf("fdt print /test-node@1234")); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test removal of node / */ ut_assertok(run_commandf("fdt rm /")); ut_asserteq(1, run_commandf("fdt print /")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -1046,17 +1046,17 @@ static int fdt_test_bootcpu(struct unit_test_state *uts) /* Test getting default bootcpu entry */ ut_assertok(run_commandf("fdt header get bootcpu boot_cpuid_phys")); ut_asserteq(0, env_get_ulong("bootcpu", 10, 0x1234)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test setting and getting new bootcpu entry, twice, to test overwrite */ for (i = 42; i <= 43; i++) { ut_assertok(run_commandf("fdt bootcpu %d", i)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting new bootcpu entry */ ut_assertok(run_commandf("fdt header get bootcpu boot_cpuid_phys")); ut_asserteq(i, env_get_ulong("bootcpu", 10, 0x1234)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); } return 0; @@ -1069,11 +1069,11 @@ static int fdt_test_header_get(struct unit_test_state *uts, /* Test getting valid header entry */ ut_assertok(run_commandf("fdt header get fvar %s", field)); ut_asserteq(val, env_get_hex("fvar", 0x1234)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test getting malformed header entry */ ut_asserteq(1, run_commandf("fdt header get fvar typo%stypo", field)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -1099,7 +1099,7 @@ static int fdt_test_header(struct unit_test_state *uts) ut_assert_nextline("size_dt_struct:\t\t0x%x", fdt_size_dt_struct(fdt)); ut_assert_nextline("number mem_rsv:\t\t0x%x", fdt_num_mem_rsv(fdt)); ut_assert_nextline_empty(); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test header get */ ut_assertok(fdt_test_header_get(uts, "magic", fdt_magic(fdt))); @@ -1175,7 +1175,7 @@ static int fdt_test_memory_cells(struct unit_test_state *uts, ut_assert_nextline("\tdevice_type = \"memory\";"); ut_assert_nextline("\treg = <%s %s>;", pada, pads); ut_assert_nextline("};"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); free(sets); free(seta); @@ -1223,7 +1223,7 @@ static int fdt_test_rsvmem(struct unit_test_state *uts) ut_assert_nextline("------------------------------------------------"); ut_assert_nextline(" %x\t%016x\t%016x", 0, 0x42, 0x1701); ut_assert_nextline(" %x\t%016x\t%016x", 1, 0x74656, 0x9); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test add new reserved memory node */ ut_assertok(run_commandf("fdt rsvmem add 0x1234 0x5678")); @@ -1233,7 +1233,7 @@ static int fdt_test_rsvmem(struct unit_test_state *uts) ut_assert_nextline(" %x\t%016x\t%016x", 0, 0x42, 0x1701); ut_assert_nextline(" %x\t%016x\t%016x", 1, 0x74656, 0x9); ut_assert_nextline(" %x\t%016x\t%016x", 2, 0x1234, 0x5678); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test delete reserved memory node */ ut_assertok(run_commandf("fdt rsvmem delete 0")); @@ -1242,7 +1242,7 @@ static int fdt_test_rsvmem(struct unit_test_state *uts) ut_assert_nextline("------------------------------------------------"); ut_assert_nextline(" %x\t%016x\t%016x", 0, 0x74656, 0x9); ut_assert_nextline(" %x\t%016x\t%016x", 1, 0x1234, 0x5678); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test re-add new reserved memory node */ ut_assertok(run_commandf("fdt rsvmem add 0x42 0x1701")); @@ -1252,12 +1252,12 @@ static int fdt_test_rsvmem(struct unit_test_state *uts) ut_assert_nextline(" %x\t%016x\t%016x", 0, 0x74656, 0x9); ut_assert_nextline(" %x\t%016x\t%016x", 1, 0x1234, 0x5678); ut_assert_nextline(" %x\t%016x\t%016x", 2, 0x42, 0x1701); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test delete nonexistent reserved memory node */ ut_asserteq(1, run_commandf("fdt rsvmem delete 10")); ut_assert_nextline("libfdt fdt_del_mem_rsv(): FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -1275,7 +1275,7 @@ static int fdt_test_chosen(struct unit_test_state *uts) /* Test default chosen node presence, fail as there is no /chosen node */ ut_asserteq(1, run_commandf("fdt print /chosen")); ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test add new chosen node without initrd */ ut_assertok(run_commandf("fdt chosen")); @@ -1289,7 +1289,7 @@ static int fdt_test_chosen(struct unit_test_state *uts) !IS_ENABLED(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT)) ut_assert_nextlinen("\tkaslr-seed = "); ut_assert_nextline("};"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test add new chosen node with initrd */ ut_assertok(run_commandf("fdt chosen 0x1234 0x5678")); @@ -1308,7 +1308,7 @@ static int fdt_test_chosen(struct unit_test_state *uts) !IS_ENABLED(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT)) ut_assert_nextlinen("\tkaslr-seed = "); ut_assert_nextline("};"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -1351,7 +1351,7 @@ static int fdt_test_apply(struct unit_test_state *uts) ut_assert_nextline("\t__symbols__ {"); ut_assert_nextline("\t};"); ut_assert_nextline("};"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test simple DTO application */ ut_assertok(run_commandf("fdt apply 0x%08lx", addro)); @@ -1361,7 +1361,7 @@ static int fdt_test_apply(struct unit_test_state *uts) ut_assert_nextline("\t__symbols__ {"); ut_assert_nextline("\t};"); ut_assert_nextline("};"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* * Create complex DTO which: @@ -1414,7 +1414,7 @@ static int fdt_test_apply(struct unit_test_state *uts) ut_assert_nextline("\t\tsubnodephandle = \"/subnode\";"); ut_assert_nextline("\t};"); ut_assert_nextline("};"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* * Create complex DTO which: @@ -1457,7 +1457,7 @@ static int fdt_test_apply(struct unit_test_state *uts) ut_assert_nextline("\t\tsubnodephandle = \"/subnode\";"); ut_assert_nextline("\t};"); ut_assert_nextline("};"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } diff --git a/test/cmd/font.c b/test/cmd/font.c index 6f4e54e7f3f..25d365dedd2 100644 --- a/test/cmd/font.c +++ b/test/cmd/font.c @@ -30,7 +30,7 @@ static int font_test_base(struct unit_test_state *uts) ut_assert_nextline("nimbus_sans_l_regular"); if (IS_ENABLED(CONFIG_CONSOLE_TRUETYPE_CANTORAONE)) ut_assert_nextline("cantoraone_regular"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); ut_assertok(vidconsole_get_font_size(dev, &name, &size)); ut_asserteq_str("nimbus_sans_l_regular", name); @@ -48,19 +48,19 @@ static int font_test_base(struct unit_test_state *uts) if (max_metrics < 2) { ut_asserteq(1, ret); ut_assert_nextline("Failed (error -7)"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } ut_assertok(ret); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); ut_assertok(vidconsole_get_font_size(dev, &name, &size)); ut_asserteq_str("cantoraone_regular", name); ut_asserteq(40, size); ut_assertok(run_command("font size 30", 0)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); ut_assertok(vidconsole_get_font_size(dev, &name, &size)); ut_asserteq_str("cantoraone_regular", name); diff --git a/test/cmd/mbr.c b/test/cmd/mbr.c index 8c9d01130a3..e1a9cdffb04 100644 --- a/test/cmd/mbr.c +++ b/test/cmd/mbr.c @@ -264,7 +264,7 @@ static int mbr_test_run(struct unit_test_state *uts) ut_assertok(run_commandf("mmc dev 6")); ut_assert_nextline("switch to partitions #0, OK"); ut_assert_nextline("mmc6 is current device"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Make sure mmc6 is 12+ MiB in size */ ut_assertok(run_commandf("mmc read 0x%lx 0x%lx 1", ra, (ulong)0xBFFE00 / 0x200)); @@ -289,7 +289,7 @@ static int mbr_test_run(struct unit_test_state *uts) memset(rbuf, 0, sizeof(rbuf)); ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk)); ut_assertok(memcmp(ebr_wbuf, rbuf, 512)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* 000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....| 000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 00 |...%$..@........| @@ -324,7 +324,7 @@ static int mbr_test_run(struct unit_test_state *uts) memset(rbuf, 0, sizeof(rbuf)); ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk)); ut_assertok(memcmp(ebr_wbuf, rbuf, 512)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* 000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....| 000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%| @@ -359,7 +359,7 @@ static int mbr_test_run(struct unit_test_state *uts) memset(rbuf, 0, sizeof(rbuf)); ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk)); ut_assertok(memcmp(ebr_wbuf, rbuf, 512)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* 000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....| 000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%| @@ -394,7 +394,7 @@ static int mbr_test_run(struct unit_test_state *uts) memset(rbuf, 0, sizeof(rbuf)); ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk)); ut_assertok(memcmp(ebr_wbuf, rbuf, 512)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* 000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....| 000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%| @@ -426,7 +426,7 @@ static int mbr_test_run(struct unit_test_state *uts) ut_assert_nextline("MBR: write success!"); ut_assertok(run_commandf("mbr verify mmc 6")); ut_assert_nextline("MBR: verify success!"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* 000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....| 000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%| diff --git a/test/cmd/pinmux.c b/test/cmd/pinmux.c index be39dbc61bd..65974d03f88 100644 --- a/test/cmd/pinmux.c +++ b/test/cmd/pinmux.c @@ -27,7 +27,13 @@ static int dm_test_cmd_pinmux_status_pinname(struct unit_test_state *uts) ut_assert_console_end(); run_command("pinmux status P9", 0); - ut_assert_nextlinen("single-pinctrl pinctrl-single-no-width: missing register width"); + if (IS_ENABLED(CONFIG_LOGF_FUNC)) { + ut_assert_nextlinen( + " single_of_to_plat() single-pinctrl pinctrl-single-no-width: missing register width"); + } else { + ut_assert_nextlinen( + "single-pinctrl pinctrl-single-no-width: missing register width"); + } ut_assert_nextlinen("P9 not found"); ut_assert_console_end(); diff --git a/test/cmd/test_echo.c b/test/cmd/test_echo.c index b829f71c591..8b306cc907f 100644 --- a/test/cmd/test_echo.c +++ b/test/cmd/test_echo.c @@ -49,7 +49,7 @@ static int lib_test_hush_echo(struct unit_test_state *uts) console_record_readline(uts->actual_str, sizeof(uts->actual_str)); ut_asserteq_str(echo_data[i].expected, uts->actual_str); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); } return 0; } diff --git a/test/cmd/test_pause.c b/test/cmd/test_pause.c index 927fe174d74..174c31a3852 100644 --- a/test/cmd/test_pause.c +++ b/test/cmd/test_pause.c @@ -19,7 +19,7 @@ static int lib_test_hush_pause(struct unit_test_state *uts) ut_assertok(run_command("pause", 0)); console_record_readline(uts->actual_str, sizeof(uts->actual_str)); ut_asserteq_str("Press any key to continue...", uts->actual_str); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test provided message */ /* Cook a newline when the command is expected to pause */ @@ -27,7 +27,7 @@ static int lib_test_hush_pause(struct unit_test_state *uts) ut_assertok(run_command("pause 'Prompt for pause...'", 0)); console_record_readline(uts->actual_str, sizeof(uts->actual_str)); ut_asserteq_str("Prompt for pause...", uts->actual_str); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Test providing more than one params */ /* No newline cooked here since the command is expected to fail */ diff --git a/test/cmd/wget.c b/test/cmd/wget.c index 1660d2bdcb0..fe26fee54c9 100644 --- a/test/cmd/wget.c +++ b/test/cmd/wget.c @@ -221,7 +221,7 @@ static int net_test_wget(struct unit_test_state *uts) run_command("md5sum ${loadaddr} ${filesize}", 0); ut_assert_nextline("md5 for 00020000 ... 0002001f ==> 234af48e94b0085060249ecb5942ab57"); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } diff --git a/test/common/cread.c b/test/common/cread.c index e159caed041..4926c216803 100644 --- a/test/common/cread.c +++ b/test/common/cread.c @@ -66,8 +66,6 @@ static int cread_test(struct unit_test_state *uts) * print_buffer(0, buf, 1, 7, 0); */ - console_record_reset_enable(); - /* simple input */ *buf = '\0'; ut_asserteq(4, console_in_puts("abc\n")); @@ -102,4 +100,4 @@ static int cread_test(struct unit_test_state *uts) return 0; } -COMMON_TEST(cread_test, 0); +COMMON_TEST(cread_test, UTF_CONSOLE); diff --git a/test/common/test_autoboot.c b/test/common/test_autoboot.c index a556cbf8e33..e3050d02c60 100644 --- a/test/common/test_autoboot.c +++ b/test/common/test_autoboot.c @@ -20,7 +20,6 @@ static int check_for_input(struct unit_test_state *uts, const char *in, const char *autoboot_prompt = "Enter password \"a\" in 1 seconds to stop autoboot"; - console_record_reset_enable(); console_in_puts(in); /* turn on keyed autoboot for the test, if possible */ @@ -91,4 +90,4 @@ static int test_autoboot(struct unit_test_state *uts) return CMD_RET_SUCCESS; } -COMMON_TEST(test_autoboot, 0); +COMMON_TEST(test_autoboot, UTF_CONSOLE); diff --git a/test/dm/acpi_dp.c b/test/dm/acpi_dp.c index eaeda2b8a7a..038806004b5 100644 --- a/test/dm/acpi_dp.c +++ b/test/dm/acpi_dp.c @@ -7,7 +7,7 @@ */ #include <dm.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <acpi/acpigen.h> #include <acpi/acpi_dp.h> #include <asm/unaligned.h> diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c index 3e912fadaef..23c16bd9866 100644 --- a/test/dm/acpigen.c +++ b/test/dm/acpigen.c @@ -9,7 +9,7 @@ #include <dm.h> #include <irq.h> #include <malloc.h> -#include <uuid.h> +#include <u-boot/uuid.h> #include <acpi/acpigen.h> #include <acpi/acpi_device.h> #include <acpi/acpi_table.h> diff --git a/test/dm/phy.c b/test/dm/phy.c index 9b4cff60e6a..194cad0bf70 100644 --- a/test/dm/phy.c +++ b/test/dm/phy.c @@ -243,20 +243,27 @@ static int dm_test_phy_setup(struct unit_test_state *uts) "gen_phy_user", &parent)); /* normal */ - ut_assertok(generic_setup_phy(parent, &phy, 0)); + ut_assertok(generic_setup_phy(parent, &phy, 0, PHY_MODE_USB_HOST, 0)); + ut_assertok(generic_shutdown_phy(&phy)); + + /* set_mode as USB Host passes, anything else is not supported */ + ut_assertok(generic_setup_phy(parent, &phy, 0, PHY_MODE_USB_HOST, 0)); + ut_assertok(generic_phy_set_mode(&phy, PHY_MODE_USB_HOST, 0)); + ut_asserteq(-EOPNOTSUPP, generic_phy_set_mode(&phy, PHY_MODE_USB_HOST, 1)); + ut_asserteq(-EINVAL, generic_phy_set_mode(&phy, PHY_MODE_USB_DEVICE, 0)); ut_assertok(generic_shutdown_phy(&phy)); /* power_off fail with -EIO */ - ut_assertok(generic_setup_phy(parent, &phy, 1)); + ut_assertok(generic_setup_phy(parent, &phy, 1, PHY_MODE_USB_HOST, 0)); ut_asserteq(-EIO, generic_shutdown_phy(&phy)); /* power_on fail with -EIO */ - ut_asserteq(-EIO, generic_setup_phy(parent, &phy, 2)); + ut_asserteq(-EIO, generic_setup_phy(parent, &phy, 2, PHY_MODE_USB_HOST, 0)); ut_assertok(generic_shutdown_phy(&phy)); /* generic_phy_get_by_index fail with -ENOENT */ ut_asserteq(-ENOENT, generic_phy_get_by_index(parent, 3, &phy)); - ut_assertok(generic_setup_phy(parent, &phy, 3)); + ut_assertok(generic_setup_phy(parent, &phy, 3, PHY_MODE_USB_HOST, 0)); ut_assertok(generic_shutdown_phy(&phy)); return 0; diff --git a/test/hush/dollar.c b/test/hush/dollar.c index cfcb1bd3e1d..077dcd62c0e 100644 --- a/test/hush/dollar.c +++ b/test/hush/dollar.c @@ -14,7 +14,6 @@ DECLARE_GLOBAL_DATA_PTR; static int hush_test_simple_dollar(struct unit_test_state *uts) { - console_record_reset_enable(); ut_assertok(run_command("echo $dollar_foo", 0)); ut_assert_nextline_empty(); ut_assert_console_end(); @@ -114,12 +113,11 @@ static int hush_test_simple_dollar(struct unit_test_state *uts) return 0; } -HUSH_TEST(hush_test_simple_dollar, 0); +HUSH_TEST(hush_test_simple_dollar, UTF_CONSOLE); static int hush_test_env_dollar(struct unit_test_state *uts) { env_set("env_foo", "bar"); - console_record_reset_enable(); ut_assertok(run_command("echo $env_foo", 0)); ut_assert_nextline("bar"); @@ -147,12 +145,10 @@ static int hush_test_env_dollar(struct unit_test_state *uts) return 0; } -HUSH_TEST(hush_test_env_dollar, 0); +HUSH_TEST(hush_test_env_dollar, UTF_CONSOLE); static int hush_test_command_dollar(struct unit_test_state *uts) { - console_record_reset_enable(); - ut_assertok(run_command("dollar_bar=\"echo bar\"", 0)); ut_assertok(run_command("$dollar_bar", 0)); @@ -215,4 +211,4 @@ static int hush_test_command_dollar(struct unit_test_state *uts) return 0; } -HUSH_TEST(hush_test_command_dollar, 0); +HUSH_TEST(hush_test_command_dollar, UTF_CONSOLE); diff --git a/test/hush/loop.c b/test/hush/loop.c index d734abf136d..a9b6a8edf24 100644 --- a/test/hush/loop.c +++ b/test/hush/loop.c @@ -14,8 +14,6 @@ DECLARE_GLOBAL_DATA_PTR; static int hush_test_for(struct unit_test_state *uts) { - console_record_reset_enable(); - ut_assertok(run_command("for loop_i in foo bar quux quux; do echo $loop_i; done", 0)); ut_assert_nextline("foo"); ut_assert_nextline("bar"); @@ -32,12 +30,10 @@ static int hush_test_for(struct unit_test_state *uts) return 0; } -HUSH_TEST(hush_test_for, 0); +HUSH_TEST(hush_test_for, UTF_CONSOLE); static int hush_test_while(struct unit_test_state *uts) { - console_record_reset_enable(); - if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) { /* * Hush 2021 always returns 0 from while loop... @@ -65,11 +61,10 @@ static int hush_test_while(struct unit_test_state *uts) return 0; } -HUSH_TEST(hush_test_while, 0); +HUSH_TEST(hush_test_while, UTF_CONSOLE); static int hush_test_until(struct unit_test_state *uts) { - console_record_reset_enable(); env_set("loop_bar", "bar"); /* @@ -87,4 +82,4 @@ static int hush_test_until(struct unit_test_state *uts) env_set("loop_bar", NULL); return 0; } -HUSH_TEST(hush_test_until, 0); +HUSH_TEST(hush_test_until, UTF_CONSOLE); diff --git a/test/image/spl_load.c b/test/image/spl_load.c index 7cbad40ea0c..3b6206955d3 100644 --- a/test/image/spl_load.c +++ b/test/image/spl_load.c @@ -343,9 +343,7 @@ static int spl_test_image(struct unit_test_state *uts, const char *test_name, } else { struct spl_load_info load; - spl_set_bl_len(&load, 1); - load.priv = img; - load.read = spl_test_read; + spl_load_init(&load, spl_test_read, img, 1); if (type == IMX8) ut_assertok(spl_load_imx_container(&info_read, &load, 0)); diff --git a/test/image/spl_load_os.c b/test/image/spl_load_os.c index 56105a59236..d17cf116a0e 100644 --- a/test/image/spl_load_os.c +++ b/test/image/spl_load_os.c @@ -20,3 +20,4 @@ static int spl_test_load(struct unit_test_state *uts) return 0; } SPL_TEST(spl_test_load, 0); + diff --git a/test/lib/lmb.c b/test/lib/lmb.c index 3c66138f732..b2c54fb4bcb 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -3,6 +3,7 @@ * (C) Copyright 2018 Simon Goldschmidt */ +#include <alist.h> #include <dm.h> #include <lmb.h> #include <log.h> @@ -12,50 +13,64 @@ #include <test/test.h> #include <test/ut.h> -static inline bool lmb_is_nomap(struct lmb_property *m) +static inline bool lmb_is_nomap(struct lmb_region *m) { return m->flags & LMB_NOMAP; } -static int check_lmb(struct unit_test_state *uts, struct lmb *lmb, - phys_addr_t ram_base, phys_size_t ram_size, - unsigned long num_reserved, +static int check_lmb(struct unit_test_state *uts, struct alist *mem_lst, + struct alist *used_lst, phys_addr_t ram_base, + phys_size_t ram_size, unsigned long num_reserved, phys_addr_t base1, phys_size_t size1, phys_addr_t base2, phys_size_t size2, phys_addr_t base3, phys_size_t size3) { + struct lmb_region *mem, *used; + + mem = mem_lst->data; + used = used_lst->data; + if (ram_size) { - ut_asserteq(lmb->memory.cnt, 1); - ut_asserteq(lmb->memory.region[0].base, ram_base); - ut_asserteq(lmb->memory.region[0].size, ram_size); + ut_asserteq(mem_lst->count, 1); + ut_asserteq(mem[0].base, ram_base); + ut_asserteq(mem[0].size, ram_size); } - ut_asserteq(lmb->reserved.cnt, num_reserved); + ut_asserteq(used_lst->count, num_reserved); if (num_reserved > 0) { - ut_asserteq(lmb->reserved.region[0].base, base1); - ut_asserteq(lmb->reserved.region[0].size, size1); + ut_asserteq(used[0].base, base1); + ut_asserteq(used[0].size, size1); } if (num_reserved > 1) { - ut_asserteq(lmb->reserved.region[1].base, base2); - ut_asserteq(lmb->reserved.region[1].size, size2); + ut_asserteq(used[1].base, base2); + ut_asserteq(used[1].size, size2); } if (num_reserved > 2) { - ut_asserteq(lmb->reserved.region[2].base, base3); - ut_asserteq(lmb->reserved.region[2].size, size3); + ut_asserteq(used[2].base, base3); + ut_asserteq(used[2].size, size3); } return 0; } -#define ASSERT_LMB(lmb, ram_base, ram_size, num_reserved, base1, size1, \ +#define ASSERT_LMB(mem_lst, used_lst, ram_base, ram_size, num_reserved, base1, size1, \ base2, size2, base3, size3) \ - ut_assert(!check_lmb(uts, lmb, ram_base, ram_size, \ + ut_assert(!check_lmb(uts, mem_lst, used_lst, ram_base, ram_size, \ num_reserved, base1, size1, base2, size2, base3, \ size3)) -/* - * Test helper function that reserves 64 KiB somewhere in the simulated RAM and - * then does some alloc + free tests. - */ +static int setup_lmb_test(struct unit_test_state *uts, struct lmb *store, + struct alist **mem_lstp, struct alist **used_lstp) +{ + struct lmb *lmb; + + ut_assertok(lmb_push(store)); + lmb = lmb_get(); + *mem_lstp = &lmb->free_mem; + *used_lstp = &lmb->used_mem; + + return 0; +} + static int test_multi_alloc(struct unit_test_state *uts, const phys_addr_t ram, const phys_size_t ram_size, const phys_addr_t ram0, const phys_size_t ram0_size, @@ -64,9 +79,11 @@ static int test_multi_alloc(struct unit_test_state *uts, const phys_addr_t ram, const phys_addr_t ram_end = ram + ram_size; const phys_addr_t alloc_64k_end = alloc_64k_addr + 0x10000; - struct lmb lmb; long ret; + struct alist *mem_lst, *used_lst; + struct lmb_region *mem, *used; phys_addr_t a, a2, b, b2, c, d; + struct lmb store; /* check for overflow */ ut_assert(ram_end == 0 || ram_end > ram); @@ -75,106 +92,110 @@ static int test_multi_alloc(struct unit_test_state *uts, const phys_addr_t ram, ut_assert(alloc_64k_addr >= ram + 8); ut_assert(alloc_64k_end <= ram_end - 8); - lmb_init(&lmb); + ut_assertok(setup_lmb_test(uts, &store, &mem_lst, &used_lst)); + mem = mem_lst->data; + used = used_lst->data; if (ram0_size) { - ret = lmb_add(&lmb, ram0, ram0_size); + ret = lmb_add(ram0, ram0_size); ut_asserteq(ret, 0); } - ret = lmb_add(&lmb, ram, ram_size); + ret = lmb_add(ram, ram_size); ut_asserteq(ret, 0); if (ram0_size) { - ut_asserteq(lmb.memory.cnt, 2); - ut_asserteq(lmb.memory.region[0].base, ram0); - ut_asserteq(lmb.memory.region[0].size, ram0_size); - ut_asserteq(lmb.memory.region[1].base, ram); - ut_asserteq(lmb.memory.region[1].size, ram_size); + ut_asserteq(mem_lst->count, 2); + ut_asserteq(mem[0].base, ram0); + ut_asserteq(mem[0].size, ram0_size); + ut_asserteq(mem[1].base, ram); + ut_asserteq(mem[1].size, ram_size); } else { - ut_asserteq(lmb.memory.cnt, 1); - ut_asserteq(lmb.memory.region[0].base, ram); - ut_asserteq(lmb.memory.region[0].size, ram_size); + ut_asserteq(mem_lst->count, 1); + ut_asserteq(mem[0].base, ram); + ut_asserteq(mem[0].size, ram_size); } /* reserve 64KiB somewhere */ - ret = lmb_reserve(&lmb, alloc_64k_addr, 0x10000); + ret = lmb_reserve(alloc_64k_addr, 0x10000); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, 0, 0, 1, alloc_64k_addr, 0x10000, + ASSERT_LMB(mem_lst, used_lst, 0, 0, 1, alloc_64k_addr, 0x10000, 0, 0, 0, 0); /* allocate somewhere, should be at the end of RAM */ - a = lmb_alloc(&lmb, 4, 1); + a = lmb_alloc(4, 1); ut_asserteq(a, ram_end - 4); - ASSERT_LMB(&lmb, 0, 0, 2, alloc_64k_addr, 0x10000, + ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr, 0x10000, ram_end - 4, 4, 0, 0); /* alloc below end of reserved region -> below reserved region */ - b = lmb_alloc_base(&lmb, 4, 1, alloc_64k_end); + b = lmb_alloc_base(4, 1, alloc_64k_end); ut_asserteq(b, alloc_64k_addr - 4); - ASSERT_LMB(&lmb, 0, 0, 2, + ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 4, 0x10000 + 4, ram_end - 4, 4, 0, 0); /* 2nd time */ - c = lmb_alloc(&lmb, 4, 1); + c = lmb_alloc(4, 1); ut_asserteq(c, ram_end - 8); - ASSERT_LMB(&lmb, 0, 0, 2, + ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 4, 0x10000 + 4, ram_end - 8, 8, 0, 0); - d = lmb_alloc_base(&lmb, 4, 1, alloc_64k_end); + d = lmb_alloc_base(4, 1, alloc_64k_end); ut_asserteq(d, alloc_64k_addr - 8); - ASSERT_LMB(&lmb, 0, 0, 2, + ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 8, 0, 0); - ret = lmb_free(&lmb, a, 4); + ret = lmb_free(a, 4); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, 0, 0, 2, + ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 4, 0, 0); /* allocate again to ensure we get the same address */ - a2 = lmb_alloc(&lmb, 4, 1); + a2 = lmb_alloc(4, 1); ut_asserteq(a, a2); - ASSERT_LMB(&lmb, 0, 0, 2, + ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 8, 0, 0); - ret = lmb_free(&lmb, a2, 4); + ret = lmb_free(a2, 4); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, 0, 0, 2, + ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 4, 0, 0); - ret = lmb_free(&lmb, b, 4); + ret = lmb_free(b, 4); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, 0, 0, 3, + ASSERT_LMB(mem_lst, used_lst, 0, 0, 3, alloc_64k_addr - 8, 4, alloc_64k_addr, 0x10000, ram_end - 8, 4); /* allocate again to ensure we get the same address */ - b2 = lmb_alloc_base(&lmb, 4, 1, alloc_64k_end); + b2 = lmb_alloc_base(4, 1, alloc_64k_end); ut_asserteq(b, b2); - ASSERT_LMB(&lmb, 0, 0, 2, + ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 4, 0, 0); - ret = lmb_free(&lmb, b2, 4); + ret = lmb_free(b2, 4); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, 0, 0, 3, + ASSERT_LMB(mem_lst, used_lst, 0, 0, 3, alloc_64k_addr - 8, 4, alloc_64k_addr, 0x10000, ram_end - 8, 4); - ret = lmb_free(&lmb, c, 4); + ret = lmb_free(c, 4); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, 0, 0, 2, + ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 8, 4, alloc_64k_addr, 0x10000, 0, 0); - ret = lmb_free(&lmb, d, 4); + ret = lmb_free(d, 4); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, 0, 0, 1, alloc_64k_addr, 0x10000, + ASSERT_LMB(mem_lst, used_lst, 0, 0, 1, alloc_64k_addr, 0x10000, 0, 0, 0, 0); if (ram0_size) { - ut_asserteq(lmb.memory.cnt, 2); - ut_asserteq(lmb.memory.region[0].base, ram0); - ut_asserteq(lmb.memory.region[0].size, ram0_size); - ut_asserteq(lmb.memory.region[1].base, ram); - ut_asserteq(lmb.memory.region[1].size, ram_size); + ut_asserteq(mem_lst->count, 2); + ut_asserteq(mem[0].base, ram0); + ut_asserteq(mem[0].size, ram0_size); + ut_asserteq(mem[1].base, ram); + ut_asserteq(mem[1].size, ram_size); } else { - ut_asserteq(lmb.memory.cnt, 1); - ut_asserteq(lmb.memory.region[0].base, ram); - ut_asserteq(lmb.memory.region[0].size, ram_size); + ut_asserteq(mem_lst->count, 1); + ut_asserteq(mem[0].base, ram); + ut_asserteq(mem[0].size, ram_size); } + lmb_pop(&store); + return 0; } @@ -229,48 +250,51 @@ static int test_bigblock(struct unit_test_state *uts, const phys_addr_t ram) const phys_size_t big_block_size = 0x10000000; const phys_addr_t ram_end = ram + ram_size; const phys_addr_t alloc_64k_addr = ram + 0x10000000; - struct lmb lmb; + struct alist *mem_lst, *used_lst; long ret; phys_addr_t a, b; + struct lmb store; /* check for overflow */ ut_assert(ram_end == 0 || ram_end > ram); - lmb_init(&lmb); + ut_assertok(setup_lmb_test(uts, &store, &mem_lst, &used_lst)); - ret = lmb_add(&lmb, ram, ram_size); + ret = lmb_add(ram, ram_size); ut_asserteq(ret, 0); /* reserve 64KiB in the middle of RAM */ - ret = lmb_reserve(&lmb, alloc_64k_addr, 0x10000); + ret = lmb_reserve(alloc_64k_addr, 0x10000); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 1, alloc_64k_addr, 0x10000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, alloc_64k_addr, 0x10000, 0, 0, 0, 0); /* allocate a big block, should be below reserved */ - a = lmb_alloc(&lmb, big_block_size, 1); + a = lmb_alloc(big_block_size, 1); ut_asserteq(a, ram); - ASSERT_LMB(&lmb, ram, ram_size, 1, a, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, a, big_block_size + 0x10000, 0, 0, 0, 0); /* allocate 2nd big block */ /* This should fail, printing an error */ - b = lmb_alloc(&lmb, big_block_size, 1); + b = lmb_alloc(big_block_size, 1); ut_asserteq(b, 0); - ASSERT_LMB(&lmb, ram, ram_size, 1, a, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, a, big_block_size + 0x10000, 0, 0, 0, 0); - ret = lmb_free(&lmb, a, big_block_size); + ret = lmb_free(a, big_block_size); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 1, alloc_64k_addr, 0x10000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, alloc_64k_addr, 0x10000, 0, 0, 0, 0); /* allocate too big block */ /* This should fail, printing an error */ - a = lmb_alloc(&lmb, ram_size, 1); + a = lmb_alloc(ram_size, 1); ut_asserteq(a, 0); - ASSERT_LMB(&lmb, ram, ram_size, 1, alloc_64k_addr, 0x10000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, alloc_64k_addr, 0x10000, 0, 0, 0, 0); + lmb_pop(&store); + return 0; } @@ -294,56 +318,62 @@ static int test_noreserved(struct unit_test_state *uts, const phys_addr_t ram, { const phys_size_t ram_size = 0x20000000; const phys_addr_t ram_end = ram + ram_size; - struct lmb lmb; long ret; phys_addr_t a, b; + struct lmb store; + struct alist *mem_lst, *used_lst; const phys_addr_t alloc_size_aligned = (alloc_size + align - 1) & ~(align - 1); /* check for overflow */ ut_assert(ram_end == 0 || ram_end > ram); - lmb_init(&lmb); + ut_assertok(setup_lmb_test(uts, &store, &mem_lst, &used_lst)); - ret = lmb_add(&lmb, ram, ram_size); + ret = lmb_add(ram, ram_size); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 0, 0, 0, 0, 0, 0, 0); + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 0, 0, 0, 0, 0, 0, 0); /* allocate a block */ - a = lmb_alloc(&lmb, alloc_size, align); + a = lmb_alloc(alloc_size, align); ut_assert(a != 0); - ASSERT_LMB(&lmb, ram, ram_size, 1, ram + ram_size - alloc_size_aligned, - alloc_size, 0, 0, 0, 0); + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, + ram + ram_size - alloc_size_aligned, alloc_size, 0, 0, 0, 0); + /* allocate another block */ - b = lmb_alloc(&lmb, alloc_size, align); + b = lmb_alloc(alloc_size, align); ut_assert(b != 0); if (alloc_size == alloc_size_aligned) { - ASSERT_LMB(&lmb, ram, ram_size, 1, ram + ram_size - + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram + ram_size - (alloc_size_aligned * 2), alloc_size * 2, 0, 0, 0, 0); } else { - ASSERT_LMB(&lmb, ram, ram_size, 2, ram + ram_size - + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram + ram_size - (alloc_size_aligned * 2), alloc_size, ram + ram_size - alloc_size_aligned, alloc_size, 0, 0); } /* and free them */ - ret = lmb_free(&lmb, b, alloc_size); + ret = lmb_free(b, alloc_size); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 1, ram + ram_size - alloc_size_aligned, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, + ram + ram_size - alloc_size_aligned, alloc_size, 0, 0, 0, 0); - ret = lmb_free(&lmb, a, alloc_size); + ret = lmb_free(a, alloc_size); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 0, 0, 0, 0, 0, 0, 0); + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 0, 0, 0, 0, 0, 0, 0); /* allocate a block with base*/ - b = lmb_alloc_base(&lmb, alloc_size, align, ram_end); + b = lmb_alloc_base(alloc_size, align, ram_end); ut_assert(a == b); - ASSERT_LMB(&lmb, ram, ram_size, 1, ram + ram_size - alloc_size_aligned, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, + ram + ram_size - alloc_size_aligned, alloc_size, 0, 0, 0, 0); /* and free it */ - ret = lmb_free(&lmb, b, alloc_size); + ret = lmb_free(b, alloc_size); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 0, 0, 0, 0, 0, 0, 0); + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 0, 0, 0, 0, 0, 0, 0); + + lmb_pop(&store); return 0; } @@ -384,36 +414,39 @@ static int lib_test_lmb_at_0(struct unit_test_state *uts) { const phys_addr_t ram = 0; const phys_size_t ram_size = 0x20000000; - struct lmb lmb; + struct lmb store; + struct alist *mem_lst, *used_lst; long ret; phys_addr_t a, b; - lmb_init(&lmb); + ut_assertok(setup_lmb_test(uts, &store, &mem_lst, &used_lst)); - ret = lmb_add(&lmb, ram, ram_size); + ret = lmb_add(ram, ram_size); ut_asserteq(ret, 0); /* allocate nearly everything */ - a = lmb_alloc(&lmb, ram_size - 4, 1); + a = lmb_alloc(ram_size - 4, 1); ut_asserteq(a, ram + 4); - ASSERT_LMB(&lmb, ram, ram_size, 1, a, ram_size - 4, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, a, ram_size - 4, 0, 0, 0, 0); /* allocate the rest */ /* This should fail as the allocated address would be 0 */ - b = lmb_alloc(&lmb, 4, 1); + b = lmb_alloc(4, 1); ut_asserteq(b, 0); /* check that this was an error by checking lmb */ - ASSERT_LMB(&lmb, ram, ram_size, 1, a, ram_size - 4, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, a, ram_size - 4, 0, 0, 0, 0); /* check that this was an error by freeing b */ - ret = lmb_free(&lmb, b, 4); + ret = lmb_free(b, 4); ut_asserteq(ret, -1); - ASSERT_LMB(&lmb, ram, ram_size, 1, a, ram_size - 4, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, a, ram_size - 4, 0, 0, 0, 0); - ret = lmb_free(&lmb, a, ram_size - 4); + ret = lmb_free(a, ram_size - 4); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 0, 0, 0, 0, 0, 0, 0); + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 0, 0, 0, 0, 0, 0, 0); + + lmb_pop(&store); return 0; } @@ -424,45 +457,50 @@ static int lib_test_lmb_overlapping_reserve(struct unit_test_state *uts) { const phys_addr_t ram = 0x40000000; const phys_size_t ram_size = 0x20000000; - struct lmb lmb; + struct lmb store; + struct alist *mem_lst, *used_lst; long ret; - lmb_init(&lmb); + ut_assertok(setup_lmb_test(uts, &store, &mem_lst, &used_lst)); - ret = lmb_add(&lmb, ram, ram_size); + ret = lmb_add(ram, ram_size); ut_asserteq(ret, 0); - ret = lmb_reserve(&lmb, 0x40010000, 0x10000); + ret = lmb_reserve(0x40010000, 0x10000); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000, 0, 0, 0, 0); - /* allocate overlapping region should fail */ - ret = lmb_reserve(&lmb, 0x40011000, 0x10000); - ut_asserteq(ret, -1); - ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000, + + /* allocate overlapping region should return the coalesced count */ + ret = lmb_reserve(0x40011000, 0x10000); + ut_asserteq(ret, 1); + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x11000, 0, 0, 0, 0); /* allocate 3nd region */ - ret = lmb_reserve(&lmb, 0x40030000, 0x10000); + ret = lmb_reserve(0x40030000, 0x10000); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40010000, 0x10000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40010000, 0x11000, 0x40030000, 0x10000, 0, 0); /* allocate 2nd region , This should coalesced all region into one */ - ret = lmb_reserve(&lmb, 0x40020000, 0x10000); + ret = lmb_reserve(0x40020000, 0x10000); ut_assert(ret >= 0); - ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x30000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x30000, 0, 0, 0, 0); /* allocate 2nd region, which should be added as first region */ - ret = lmb_reserve(&lmb, 0x40000000, 0x8000); + ret = lmb_reserve(0x40000000, 0x8000); ut_assert(ret >= 0); - ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40000000, 0x8000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x8000, 0x40010000, 0x30000, 0, 0); /* allocate 3rd region, coalesce with first and overlap with second */ - ret = lmb_reserve(&lmb, 0x40008000, 0x10000); + ret = lmb_reserve(0x40008000, 0x10000); ut_assert(ret >= 0); - ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40000000, 0x40000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40000000, 0x40000, 0, 0, 0, 0); + + lmb_pop(&store); + return 0; } LIB_TEST(lib_test_lmb_overlapping_reserve, 0); @@ -473,112 +511,116 @@ LIB_TEST(lib_test_lmb_overlapping_reserve, 0); */ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) { + struct lmb store; + struct alist *mem_lst, *used_lst; const phys_size_t ram_size = 0x20000000; const phys_addr_t ram_end = ram + ram_size; const phys_size_t alloc_addr_a = ram + 0x8000000; const phys_size_t alloc_addr_b = ram + 0x8000000 * 2; const phys_size_t alloc_addr_c = ram + 0x8000000 * 3; - struct lmb lmb; long ret; phys_addr_t a, b, c, d, e; /* check for overflow */ ut_assert(ram_end == 0 || ram_end > ram); - lmb_init(&lmb); + ut_assertok(setup_lmb_test(uts, &store, &mem_lst, &used_lst)); - ret = lmb_add(&lmb, ram, ram_size); + ret = lmb_add(ram, ram_size); ut_asserteq(ret, 0); /* reserve 3 blocks */ - ret = lmb_reserve(&lmb, alloc_addr_a, 0x10000); + ret = lmb_reserve(alloc_addr_a, 0x10000); ut_asserteq(ret, 0); - ret = lmb_reserve(&lmb, alloc_addr_b, 0x10000); + ret = lmb_reserve(alloc_addr_b, 0x10000); ut_asserteq(ret, 0); - ret = lmb_reserve(&lmb, alloc_addr_c, 0x10000); + ret = lmb_reserve(alloc_addr_c, 0x10000); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 3, alloc_addr_a, 0x10000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, alloc_addr_a, 0x10000, alloc_addr_b, 0x10000, alloc_addr_c, 0x10000); /* allocate blocks */ - a = lmb_alloc_addr(&lmb, ram, alloc_addr_a - ram); + a = lmb_alloc_addr(ram, alloc_addr_a - ram); ut_asserteq(a, ram); - ASSERT_LMB(&lmb, ram, ram_size, 3, ram, 0x8010000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, ram, 0x8010000, alloc_addr_b, 0x10000, alloc_addr_c, 0x10000); - b = lmb_alloc_addr(&lmb, alloc_addr_a + 0x10000, + b = lmb_alloc_addr(alloc_addr_a + 0x10000, alloc_addr_b - alloc_addr_a - 0x10000); ut_asserteq(b, alloc_addr_a + 0x10000); - ASSERT_LMB(&lmb, ram, ram_size, 2, ram, 0x10010000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x10010000, alloc_addr_c, 0x10000, 0, 0); - c = lmb_alloc_addr(&lmb, alloc_addr_b + 0x10000, + c = lmb_alloc_addr(alloc_addr_b + 0x10000, alloc_addr_c - alloc_addr_b - 0x10000); ut_asserteq(c, alloc_addr_b + 0x10000); - ASSERT_LMB(&lmb, ram, ram_size, 1, ram, 0x18010000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000, 0, 0, 0, 0); - d = lmb_alloc_addr(&lmb, alloc_addr_c + 0x10000, + d = lmb_alloc_addr(alloc_addr_c + 0x10000, ram_end - alloc_addr_c - 0x10000); ut_asserteq(d, alloc_addr_c + 0x10000); - ASSERT_LMB(&lmb, ram, ram_size, 1, ram, ram_size, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, ram_size, 0, 0, 0, 0); /* allocating anything else should fail */ - e = lmb_alloc(&lmb, 1, 1); + e = lmb_alloc(1, 1); ut_asserteq(e, 0); - ASSERT_LMB(&lmb, ram, ram_size, 1, ram, ram_size, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, ram_size, 0, 0, 0, 0); - ret = lmb_free(&lmb, d, ram_end - alloc_addr_c - 0x10000); + ret = lmb_free(d, ram_end - alloc_addr_c - 0x10000); ut_asserteq(ret, 0); /* allocate at 3 points in free range */ - d = lmb_alloc_addr(&lmb, ram_end - 4, 4); + d = lmb_alloc_addr(ram_end - 4, 4); ut_asserteq(d, ram_end - 4); - ASSERT_LMB(&lmb, ram, ram_size, 2, ram, 0x18010000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x18010000, d, 4, 0, 0); - ret = lmb_free(&lmb, d, 4); + ret = lmb_free(d, 4); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 1, ram, 0x18010000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000, 0, 0, 0, 0); - d = lmb_alloc_addr(&lmb, ram_end - 128, 4); + d = lmb_alloc_addr(ram_end - 128, 4); ut_asserteq(d, ram_end - 128); - ASSERT_LMB(&lmb, ram, ram_size, 2, ram, 0x18010000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x18010000, d, 4, 0, 0); - ret = lmb_free(&lmb, d, 4); + ret = lmb_free(d, 4); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 1, ram, 0x18010000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000, 0, 0, 0, 0); - d = lmb_alloc_addr(&lmb, alloc_addr_c + 0x10000, 4); + d = lmb_alloc_addr(alloc_addr_c + 0x10000, 4); ut_asserteq(d, alloc_addr_c + 0x10000); - ASSERT_LMB(&lmb, ram, ram_size, 1, ram, 0x18010004, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010004, 0, 0, 0, 0); - ret = lmb_free(&lmb, d, 4); + ret = lmb_free(d, 4); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 1, ram, 0x18010000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000, 0, 0, 0, 0); /* allocate at the bottom */ - ret = lmb_free(&lmb, a, alloc_addr_a - ram); + ret = lmb_free(a, alloc_addr_a - ram); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 1, ram + 0x8000000, 0x10010000, - 0, 0, 0, 0); - d = lmb_alloc_addr(&lmb, ram, 4); + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram + 0x8000000, + 0x10010000, 0, 0, 0, 0); + + d = lmb_alloc_addr(ram, 4); ut_asserteq(d, ram); - ASSERT_LMB(&lmb, ram, ram_size, 2, d, 4, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, d, 4, ram + 0x8000000, 0x10010000, 0, 0); /* check that allocating outside memory fails */ if (ram_end != 0) { - ret = lmb_alloc_addr(&lmb, ram_end, 1); + ret = lmb_alloc_addr(ram_end, 1); ut_asserteq(ret, 0); } if (ram != 0) { - ret = lmb_alloc_addr(&lmb, ram - 1, 1); + ret = lmb_alloc_addr(ram - 1, 1); ut_asserteq(ret, 0); } + lmb_pop(&store); + return 0; } @@ -600,55 +642,57 @@ LIB_TEST(lib_test_lmb_alloc_addr, 0); static int test_get_unreserved_size(struct unit_test_state *uts, const phys_addr_t ram) { + struct lmb store; + struct alist *mem_lst, *used_lst; const phys_size_t ram_size = 0x20000000; const phys_addr_t ram_end = ram + ram_size; const phys_size_t alloc_addr_a = ram + 0x8000000; const phys_size_t alloc_addr_b = ram + 0x8000000 * 2; const phys_size_t alloc_addr_c = ram + 0x8000000 * 3; - struct lmb lmb; long ret; phys_size_t s; /* check for overflow */ ut_assert(ram_end == 0 || ram_end > ram); + ut_assertok(setup_lmb_test(uts, &store, &mem_lst, &used_lst)); - lmb_init(&lmb); - - ret = lmb_add(&lmb, ram, ram_size); + ret = lmb_add(ram, ram_size); ut_asserteq(ret, 0); /* reserve 3 blocks */ - ret = lmb_reserve(&lmb, alloc_addr_a, 0x10000); + ret = lmb_reserve(alloc_addr_a, 0x10000); ut_asserteq(ret, 0); - ret = lmb_reserve(&lmb, alloc_addr_b, 0x10000); + ret = lmb_reserve(alloc_addr_b, 0x10000); ut_asserteq(ret, 0); - ret = lmb_reserve(&lmb, alloc_addr_c, 0x10000); + ret = lmb_reserve(alloc_addr_c, 0x10000); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 3, alloc_addr_a, 0x10000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, alloc_addr_a, 0x10000, alloc_addr_b, 0x10000, alloc_addr_c, 0x10000); /* check addresses in between blocks */ - s = lmb_get_free_size(&lmb, ram); + s = lmb_get_free_size(ram); ut_asserteq(s, alloc_addr_a - ram); - s = lmb_get_free_size(&lmb, ram + 0x10000); + s = lmb_get_free_size(ram + 0x10000); ut_asserteq(s, alloc_addr_a - ram - 0x10000); - s = lmb_get_free_size(&lmb, alloc_addr_a - 4); + s = lmb_get_free_size(alloc_addr_a - 4); ut_asserteq(s, 4); - s = lmb_get_free_size(&lmb, alloc_addr_a + 0x10000); + s = lmb_get_free_size(alloc_addr_a + 0x10000); ut_asserteq(s, alloc_addr_b - alloc_addr_a - 0x10000); - s = lmb_get_free_size(&lmb, alloc_addr_a + 0x20000); + s = lmb_get_free_size(alloc_addr_a + 0x20000); ut_asserteq(s, alloc_addr_b - alloc_addr_a - 0x20000); - s = lmb_get_free_size(&lmb, alloc_addr_b - 4); + s = lmb_get_free_size(alloc_addr_b - 4); ut_asserteq(s, 4); - s = lmb_get_free_size(&lmb, alloc_addr_c + 0x10000); + s = lmb_get_free_size(alloc_addr_c + 0x10000); ut_asserteq(s, ram_end - alloc_addr_c - 0x10000); - s = lmb_get_free_size(&lmb, alloc_addr_c + 0x20000); + s = lmb_get_free_size(alloc_addr_c + 0x20000); ut_asserteq(s, ram_end - alloc_addr_c - 0x20000); - s = lmb_get_free_size(&lmb, ram_end - 4); + s = lmb_get_free_size(ram_end - 4); ut_asserteq(s, 4); + lmb_pop(&store); + return 0; } @@ -666,158 +710,94 @@ static int lib_test_lmb_get_free_size(struct unit_test_state *uts) } LIB_TEST(lib_test_lmb_get_free_size, 0); -#ifdef CONFIG_LMB_USE_MAX_REGIONS -static int lib_test_lmb_max_regions(struct unit_test_state *uts) -{ - const phys_addr_t ram = 0x00000000; - /* - * All of 32bit memory space will contain regions for this test, so - * we need to scale ram_size (which in this case is the size of the lmb - * region) to match. - */ - const phys_size_t ram_size = ((0xFFFFFFFF >> CONFIG_LMB_MAX_REGIONS) - + 1) * CONFIG_LMB_MAX_REGIONS; - const phys_size_t blk_size = 0x10000; - phys_addr_t offset; - struct lmb lmb; - int ret, i; - - lmb_init(&lmb); - - ut_asserteq(lmb.memory.cnt, 0); - ut_asserteq(lmb.memory.max, CONFIG_LMB_MAX_REGIONS); - ut_asserteq(lmb.reserved.cnt, 0); - ut_asserteq(lmb.reserved.max, CONFIG_LMB_MAX_REGIONS); - - /* Add CONFIG_LMB_MAX_REGIONS memory regions */ - for (i = 0; i < CONFIG_LMB_MAX_REGIONS; i++) { - offset = ram + 2 * i * ram_size; - ret = lmb_add(&lmb, offset, ram_size); - ut_asserteq(ret, 0); - } - ut_asserteq(lmb.memory.cnt, CONFIG_LMB_MAX_REGIONS); - ut_asserteq(lmb.reserved.cnt, 0); - - /* error for the (CONFIG_LMB_MAX_REGIONS + 1) memory regions */ - offset = ram + 2 * (CONFIG_LMB_MAX_REGIONS + 1) * ram_size; - ret = lmb_add(&lmb, offset, ram_size); - ut_asserteq(ret, -1); - - ut_asserteq(lmb.memory.cnt, CONFIG_LMB_MAX_REGIONS); - ut_asserteq(lmb.reserved.cnt, 0); - - /* reserve CONFIG_LMB_MAX_REGIONS regions */ - for (i = 0; i < CONFIG_LMB_MAX_REGIONS; i++) { - offset = ram + 2 * i * blk_size; - ret = lmb_reserve(&lmb, offset, blk_size); - ut_asserteq(ret, 0); - } - - ut_asserteq(lmb.memory.cnt, CONFIG_LMB_MAX_REGIONS); - ut_asserteq(lmb.reserved.cnt, CONFIG_LMB_MAX_REGIONS); - - /* error for the 9th reserved blocks */ - offset = ram + 2 * (CONFIG_LMB_MAX_REGIONS + 1) * blk_size; - ret = lmb_reserve(&lmb, offset, blk_size); - ut_asserteq(ret, -1); - - ut_asserteq(lmb.memory.cnt, CONFIG_LMB_MAX_REGIONS); - ut_asserteq(lmb.reserved.cnt, CONFIG_LMB_MAX_REGIONS); - - /* check each regions */ - for (i = 0; i < CONFIG_LMB_MAX_REGIONS; i++) - ut_asserteq(lmb.memory.region[i].base, ram + 2 * i * ram_size); - - for (i = 0; i < CONFIG_LMB_MAX_REGIONS; i++) - ut_asserteq(lmb.reserved.region[i].base, ram + 2 * i * blk_size); - - return 0; -} -LIB_TEST(lib_test_lmb_max_regions, 0); -#endif - static int lib_test_lmb_flags(struct unit_test_state *uts) { + struct lmb store; + struct lmb_region *mem, *used; + struct alist *mem_lst, *used_lst; const phys_addr_t ram = 0x40000000; const phys_size_t ram_size = 0x20000000; - struct lmb lmb; long ret; - lmb_init(&lmb); + ut_assertok(setup_lmb_test(uts, &store, &mem_lst, &used_lst)); + mem = mem_lst->data; + used = used_lst->data; - ret = lmb_add(&lmb, ram, ram_size); + ret = lmb_add(ram, ram_size); ut_asserteq(ret, 0); /* reserve, same flag */ - ret = lmb_reserve_flags(&lmb, 0x40010000, 0x10000, LMB_NOMAP); + ret = lmb_reserve_flags(0x40010000, 0x10000, LMB_NOMAP); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000, 0, 0, 0, 0); /* reserve again, same flag */ - ret = lmb_reserve_flags(&lmb, 0x40010000, 0x10000, LMB_NOMAP); + ret = lmb_reserve_flags(0x40010000, 0x10000, LMB_NOMAP); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000, 0, 0, 0, 0); /* reserve again, new flag */ - ret = lmb_reserve_flags(&lmb, 0x40010000, 0x10000, LMB_NONE); + ret = lmb_reserve_flags(0x40010000, 0x10000, LMB_NONE); ut_asserteq(ret, -1); - ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000, 0, 0, 0, 0); - ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1); + ut_asserteq(lmb_is_nomap(&used[0]), 1); /* merge after */ - ret = lmb_reserve_flags(&lmb, 0x40020000, 0x10000, LMB_NOMAP); + ret = lmb_reserve_flags(0x40020000, 0x10000, LMB_NOMAP); ut_asserteq(ret, 1); - ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x20000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x20000, 0, 0, 0, 0); /* merge before */ - ret = lmb_reserve_flags(&lmb, 0x40000000, 0x10000, LMB_NOMAP); + ret = lmb_reserve_flags(0x40000000, 0x10000, LMB_NOMAP); ut_asserteq(ret, 1); - ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40000000, 0x30000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40000000, 0x30000, 0, 0, 0, 0); - ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1); + ut_asserteq(lmb_is_nomap(&used[0]), 1); - ret = lmb_reserve_flags(&lmb, 0x40030000, 0x10000, LMB_NONE); + ret = lmb_reserve_flags(0x40030000, 0x10000, LMB_NONE); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40000000, 0x30000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x30000, 0x40030000, 0x10000, 0, 0); - ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1); - ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0); + ut_asserteq(lmb_is_nomap(&used[0]), 1); + ut_asserteq(lmb_is_nomap(&used[1]), 0); /* test that old API use LMB_NONE */ - ret = lmb_reserve(&lmb, 0x40040000, 0x10000); + ret = lmb_reserve(0x40040000, 0x10000); ut_asserteq(ret, 1); - ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40000000, 0x30000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x30000, 0x40030000, 0x20000, 0, 0); - ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1); - ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0); + ut_asserteq(lmb_is_nomap(&used[0]), 1); + ut_asserteq(lmb_is_nomap(&used[1]), 0); - ret = lmb_reserve_flags(&lmb, 0x40070000, 0x10000, LMB_NOMAP); + ret = lmb_reserve_flags(0x40070000, 0x10000, LMB_NOMAP); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 3, 0x40000000, 0x30000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, 0x40000000, 0x30000, 0x40030000, 0x20000, 0x40070000, 0x10000); - ret = lmb_reserve_flags(&lmb, 0x40050000, 0x10000, LMB_NOMAP); + ret = lmb_reserve_flags(0x40050000, 0x10000, LMB_NOMAP); ut_asserteq(ret, 0); - ASSERT_LMB(&lmb, ram, ram_size, 4, 0x40000000, 0x30000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 4, 0x40000000, 0x30000, 0x40030000, 0x20000, 0x40050000, 0x10000); /* merge with 2 adjacent regions */ - ret = lmb_reserve_flags(&lmb, 0x40060000, 0x10000, LMB_NOMAP); + ret = lmb_reserve_flags(0x40060000, 0x10000, LMB_NOMAP); ut_asserteq(ret, 2); - ASSERT_LMB(&lmb, ram, ram_size, 3, 0x40000000, 0x30000, + ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, 0x40000000, 0x30000, 0x40030000, 0x20000, 0x40050000, 0x30000); - ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1); - ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0); - ut_asserteq(lmb_is_nomap(&lmb.reserved.region[2]), 1); + ut_asserteq(lmb_is_nomap(&used[0]), 1); + ut_asserteq(lmb_is_nomap(&used[1]), 0); + ut_asserteq(lmb_is_nomap(&used[2]), 1); + + lmb_pop(&store); return 0; } diff --git a/test/lib/test_print.c b/test/lib/test_print.c index e356afc22ba..cd7f3f85769 100644 --- a/test/lib/test_print.c +++ b/test/lib/test_print.c @@ -17,13 +17,10 @@ DECLARE_GLOBAL_DATA_PTR; static int test_print_freq(struct unit_test_state *uts, uint64_t freq, char *expected) { - ut_silence_console(uts); - console_record_reset_enable(); print_freq(freq, ";\n"); - ut_unsilence_console(uts); console_record_readline(uts->actual_str, sizeof(uts->actual_str)); ut_asserteq_str(expected, uts->actual_str); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -41,18 +38,15 @@ static int lib_test_print_freq(struct unit_test_state *uts) ut_assertok(test_print_freq(uts, 54321987654321, "54321.99 GHz;")); return 0; } -LIB_TEST(lib_test_print_freq, 0); +LIB_TEST(lib_test_print_freq, UTF_CONSOLE); static int test_print_size(struct unit_test_state *uts, uint64_t freq, char *expected) { - ut_silence_console(uts); - console_record_reset_enable(); print_size(freq, ";\n"); - ut_unsilence_console(uts); console_record_readline(uts->actual_str, sizeof(uts->actual_str)); ut_asserteq_str(expected, uts->actual_str); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } @@ -73,4 +67,4 @@ static int lib_test_print_size(struct unit_test_state *uts) ut_assertok(test_print_size(uts, 54321987654321, "49.4 TiB;")); return 0; } -LIB_TEST(lib_test_print_size, 0); +LIB_TEST(lib_test_print_size, UTF_CONSOLE); diff --git a/test/lib/uuid.c b/test/lib/uuid.c index 8fe65dbf78b..d00e9563a47 100644 --- a/test/lib/uuid.c +++ b/test/lib/uuid.c @@ -8,13 +8,18 @@ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> */ -#include <uuid.h> +#include <charset.h> +#include <u-boot/uuid.h> #include <test/lib.h> #include <test/test.h> #include <test/ut.h> +#include <efi.h> + /* test UUID */ #define TEST_SVC_UUID "ed32d533-4209-99e6-2d72-cdd998a79cc0" +/* U-Boot default fw image namespace */ +#define DEFAULT_FW_IMAGE_NAMESPACE "8c9f137e-91dc-427b-b2d6-b420faebaf2a" #define UUID_SIZE 16 @@ -37,3 +42,120 @@ static int lib_test_uuid_to_le(struct unit_test_state *uts) return 0; } LIB_TEST(lib_test_uuid_to_le, 0); + +#if defined(CONFIG_RANDOM_UUID) || defined(CONFIG_CMD_UUID) +/* Test UUID attribute bits (version, variant) */ +static int lib_test_uuid_bits(struct unit_test_state *uts) +{ + unsigned char uuid[16]; + efi_guid_t guid; + int i; + + /* + * Reduce the chance of a randomly generated UUID disguising + * a regression by testing multiple times. + */ + for (i = 0; i < 5; i++) { + /* Test UUID v4 */ + gen_rand_uuid((unsigned char *)&uuid); + + printf("v4 UUID: %pUb\n", (efi_guid_t *)uuid); + + /* version 4 */ + ut_assert((uuid[6] & 0xf0) == 0x40); + /* variant 1 */ + ut_assert((uuid[8] & UUID_VARIANT_MASK) == (UUID_VARIANT << UUID_VARIANT_SHIFT)); + + /* Test v5, use the v4 UUID as the namespace */ + gen_v5_guid((struct uuid *)uuid, + &guid, "test", 4, NULL); + + printf("v5 GUID: %pUl\n", (efi_guid_t *)uuid); + + /* This is a GUID so bits 6 and 7 are swapped (little endian). Version 5 */ + ut_assert((guid.b[7] & 0xf0) == 0x50); + /* variant 1 */ + ut_assert((guid.b[8] & UUID_VARIANT_MASK) == (UUID_VARIANT << UUID_VARIANT_SHIFT)); + } + + return 0; +} + +LIB_TEST(lib_test_uuid_bits, 0); +#endif + +struct dynamic_uuid_test_data { + const char *compatible; + const u16 *images[4]; + const char *expected_uuids[4]; +}; + +static int lib_test_dynamic_uuid_case(struct unit_test_state *uts, + const struct dynamic_uuid_test_data *data) +{ + struct uuid namespace; + int j; + + ut_assertok(uuid_str_to_bin(DEFAULT_FW_IMAGE_NAMESPACE, (unsigned char *)&namespace, + UUID_STR_FORMAT_GUID)); + + for (j = 0; data->images[j]; j++) { + const char *expected_uuid = data->expected_uuids[j]; + const u16 *image = data->images[j]; + efi_guid_t uuid; + char uuid_str[37]; + + gen_v5_guid(&namespace, &uuid, + data->compatible, strlen(data->compatible), + image, u16_strlen(image) * sizeof(uint16_t), + NULL); + uuid_bin_to_str((unsigned char *)&uuid, uuid_str, UUID_STR_FORMAT_GUID); + + ut_asserteq_str(expected_uuid, uuid_str); + } + + return 0; +} + +static int lib_test_dynamic_uuid(struct unit_test_state *uts) +{ + int ret, i; + const struct dynamic_uuid_test_data test_data[] = { + { + .compatible = "sandbox", + .images = { + u"SANDBOX-UBOOT", + u"SANDBOX-UBOOT-ENV", + u"SANDBOX-FIT", + NULL, + }, + .expected_uuids = { + "985f2937-7c2e-5e9a-8a5e-8e063312964b", + "9e339473-c2eb-530a-a69b-0cd6bbbed40e", + "46610520-469e-59dc-a8dd-c11832b877ea", + NULL, + } + }, + { + .compatible = "qcom,qrb4210-rb2", + .images = { + u"QUALCOMM-UBOOT", + NULL, + }, + .expected_uuids = { + "d5021fac-8dd0-5ed7-90c2-763c304aaf86", + NULL, + } + }, + }; + + for (i = 0; i < ARRAY_SIZE(test_data); i++) { + ret = lib_test_dynamic_uuid_case(uts, &test_data[i]); + if (ret) + return ret; + } + + return 0; +} + +LIB_TEST(lib_test_dynamic_uuid, 0); diff --git a/test/log/cont_test.c b/test/log/cont_test.c index 036d44b9d73..32b1c792367 100644 --- a/test/log/cont_test.c +++ b/test/log/cont_test.c @@ -25,7 +25,6 @@ static int log_test_cont(struct unit_test_state *uts) /* Write two messages, the second continuing the first */ gd->log_fmt = (1 << LOGF_CAT) | (1 << LOGF_LEVEL) | (1 << LOGF_MSG); gd->default_log_level = LOGL_INFO; - console_record_reset_enable(); log(LOGC_ARCH, LOGL_ERR, "ea%d\n", 1); log(LOGC_CONT, LOGL_CONT, "cc%d\n", 2); gd->default_log_level = log_level; @@ -33,7 +32,7 @@ static int log_test_cont(struct unit_test_state *uts) gd->flags &= ~GD_FLG_RECORD; ut_assertok(ut_check_console_line(uts, "ERR.arch, ea1")); ut_assertok(ut_check_console_line(uts, "ERR.arch, cc2")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Write a third message which is not a continuation */ gd->log_fmt = (1 << LOGF_CAT) | (1 << LOGF_LEVEL) | (1 << LOGF_MSG); @@ -44,7 +43,7 @@ static int log_test_cont(struct unit_test_state *uts) gd->log_fmt = log_fmt; gd->flags &= ~GD_FLG_RECORD; ut_assertok(ut_check_console_line(uts, "INFO.efi, ie3")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); /* Write two messages without a newline between them */ gd->log_fmt = (1 << LOGF_CAT) | (1 << LOGF_LEVEL) | (1 << LOGF_MSG); @@ -56,7 +55,7 @@ static int log_test_cont(struct unit_test_state *uts) gd->log_fmt = log_fmt; gd->flags &= ~GD_FLG_RECORD; ut_assertok(ut_check_console_line(uts, "ERR.arch, ea1 cc2")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } diff --git a/test/log/log_filter.c b/test/log/log_filter.c index e175f409c9b..d36e9d9714e 100644 --- a/test/log/log_filter.c +++ b/test/log/log_filter.c @@ -38,7 +38,6 @@ static int log_test_filter(struct unit_test_state *uts) ulong filt1, filt2; #define create_filter(args, filter_num) do {\ - ut_assertok(console_record_reset_enable()); \ ut_assertok(run_command("log filter-add -p " args, 0)); \ ut_assert_skipline(); \ ut_assertok(strict_strtoul(uts->actual_str, 10, &(filter_num))); \ @@ -72,7 +71,6 @@ static int log_test_filter(struct unit_test_state *uts) ut_asserteq(true, filt2_found); #define remove_filter(filter_num) do { \ - ut_assertok(console_record_reset_enable()); \ snprintf(cmd, sizeof(cmd), "log filter-remove %lu", filter_num); \ ut_assertok(run_command(cmd, 0)); \ ut_assert_console_end(); \ @@ -95,7 +93,6 @@ static int log_test_filter(struct unit_test_state *uts) create_filter("", filt1); create_filter("", filt2); - ut_assertok(console_record_reset_enable()); ut_assertok(run_command("log filter-remove -a", 0)); ut_assert_console_end(); diff --git a/test/log/log_test.c b/test/log/log_test.c index 357a3b57feb..1c89df4ef18 100644 --- a/test/log/log_test.c +++ b/test/log/log_test.c @@ -110,11 +110,9 @@ int log_test_cat_allow(struct unit_test_state *uts) filt = log_add_filter("console", cat_list, LOGL_MAX, NULL); ut_assert(filt >= 0); - ut_assertok(console_record_reset_enable()); log_run_cat(UCLASS_MMC); check_log_entries_extra(); - ut_assertok(console_record_reset_enable()); log_run_cat(UCLASS_SPI); check_log_entries_extra(); @@ -134,7 +132,6 @@ int log_test_cat_deny_implicit(struct unit_test_state *uts) filt = log_add_filter("console", cat_list, LOGL_MAX, NULL); ut_assert(filt >= 0); - ut_assertok(console_record_reset_enable()); log_run_cat(UCLASS_SPI); check_log_entries_none(); @@ -151,11 +148,9 @@ int log_test_file(struct unit_test_state *uts) filt = log_add_filter("console", NULL, LOGL_MAX, "file"); ut_assert(filt >= 0); - ut_assertok(console_record_reset_enable()); log_run_file("file"); check_log_entries_flags(EXPECT_DIRECT | EXPECT_EXTRA | EXPECT_FORCE); - ut_assertok(console_record_reset_enable()); log_run_file("file2"); check_log_entries_none(); @@ -172,7 +167,6 @@ int log_test_file_second(struct unit_test_state *uts) filt = log_add_filter("console", NULL, LOGL_MAX, "file,file2"); ut_assert(filt >= 0); - ut_assertok(console_record_reset_enable()); log_run_file("file2"); check_log_entries_flags(EXPECT_DIRECT | EXPECT_EXTRA | EXPECT_FORCE); @@ -190,7 +184,6 @@ int log_test_file_mid(struct unit_test_state *uts) "file,file2,log/log_test.c"); ut_assert(filt >= 0); - ut_assertok(console_record_reset_enable()); log_run_file("file2"); check_log_entries_extra(); @@ -207,7 +200,6 @@ int log_test_level(struct unit_test_state *uts) filt = log_add_filter("console", NULL, LOGL_WARNING, NULL); ut_assert(filt >= 0); - ut_assertok(console_record_reset_enable()); log_run(); check_log_entries_flags_levels(EXPECT_LOG | EXPECT_DIRECT | EXPECT_FORCE, LOGL_FIRST, LOGL_WARNING); @@ -227,7 +219,6 @@ int log_test_double(struct unit_test_state *uts) filt2 = log_add_filter("console", NULL, LOGL_MAX, NULL); ut_assert(filt2 >= 0); - ut_assertok(console_record_reset_enable()); log_run(); check_log_entries_extra(); @@ -249,7 +240,6 @@ int log_test_triple(struct unit_test_state *uts) filt3 = log_add_filter("console", NULL, LOGL_MAX, "log/log_test.c"); ut_assert(filt3 >= 0); - ut_assertok(console_record_reset_enable()); log_run_file("file2"); check_log_entries_extra(); @@ -264,7 +254,6 @@ int do_log_test_helpers(struct unit_test_state *uts) { int i; - ut_assertok(console_record_reset_enable()); log_err("level %d\n", LOGL_EMERG); log_err("level %d\n", LOGL_ALERT); log_err("level %d\n", LOGL_CRIT); @@ -296,7 +285,6 @@ LOG_TEST_FLAGS(log_test_helpers, UTF_CONSOLE); int do_log_test_disable(struct unit_test_state *uts) { - ut_assertok(console_record_reset_enable()); log_err("default\n"); ut_assert_nextline("%*s() default", CONFIG_LOGF_FUNC_PAD, __func__); @@ -335,7 +323,6 @@ int log_test_cat_deny(struct unit_test_state *uts) LOGFF_DENY); ut_assert(filt2 >= 0); - ut_assertok(console_record_reset_enable()); log_run_cat(UCLASS_SPI); check_log_entries_none(); @@ -356,7 +343,6 @@ int log_test_file_deny(struct unit_test_state *uts) LOGFF_DENY); ut_assert(filt2 >= 0); - ut_assertok(console_record_reset_enable()); log_run_file("file"); check_log_entries_none(); @@ -377,11 +363,10 @@ int log_test_level_deny(struct unit_test_state *uts) LOGFF_DENY); ut_assert(filt2 >= 0); - ut_assertok(console_record_reset_enable()); log_run(); - check_log_entries_flags_levels(EXPECT_LOG | EXPECT_DIRECT | EXPECT_FORCE, - LOGL_WARNING + 1, - min(gd->default_log_level, LOGL_INFO)); + check_log_entries_flags_levels( + EXPECT_LOG | EXPECT_DIRECT | EXPECT_FORCE, + LOGL_WARNING + 1, min((int)gd->default_log_level, LOGL_INFO)); ut_assertok(log_remove_filter("console", filt1)); ut_assertok(log_remove_filter("console", filt2)); @@ -401,7 +386,6 @@ int log_test_min(struct unit_test_state *uts) LOGFF_DENY | LOGFF_LEVEL_MIN); ut_assert(filt2 >= 0); - ut_assertok(console_record_reset_enable()); log_run(); check_log_entries_flags_levels(EXPECT_LOG | EXPECT_DIRECT | EXPECT_FORCE, LOGL_WARNING, LOGL_INFO - 1); @@ -419,8 +403,6 @@ int log_test_dropped(struct unit_test_state *uts) gd->flags &= ~(GD_FLG_LOG_READY); gd->log_drop_count = 0; - ut_assertok(console_record_reset_enable()); - log_run(); ut_asserteq(2 * (LOGL_COUNT - LOGL_FIRST) + _LOG_MAX_LEVEL - LOGL_FIRST + 1, @@ -446,14 +428,15 @@ int log_test_buffer(struct unit_test_state *uts) for (i = 0; i < 0x11; i++) buf[i] = i * 0x11; - ut_assertok(console_record_reset_enable()); log_buffer(LOGC_BOOT, LOGL_INFO, 0, buf, 1, 0x12, 0); /* This one should product no output due to the debug level */ log_buffer(LOGC_BOOT, LOGL_DEBUG, 0, buf, 1, 0x12, 0); - ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........"); - ut_assert_nextline("00000010: 10 00 .."); + ut_assert_nextline( + " log_test_buffer() 00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........"); + ut_assert_nextline( + " log_test_buffer() 00000010: 10 00 .."); ut_assert_console_end(); free(buf); diff --git a/test/log/nolog_ndebug.c b/test/log/nolog_ndebug.c index b714a16d2e7..4dc0f2d3a33 100644 --- a/test/log/nolog_ndebug.c +++ b/test/log/nolog_ndebug.c @@ -21,7 +21,6 @@ static int log_test_log_disabled_ndebug(struct unit_test_state *uts) int i; memset(buf, 0, BUFFSIZE); - console_record_reset_enable(); /* Output a log record at every level */ for (i = LOGL_EMERG; i < LOGL_COUNT; i++) @@ -31,7 +30,7 @@ static int log_test_log_disabled_ndebug(struct unit_test_state *uts) /* Since DEBUG is not defined, we expect to not get debug output */ for (i = LOGL_EMERG; i < LOGL_DEBUG; i++) ut_assertok(ut_check_console_line(uts, "testing level %d", i)); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } diff --git a/test/log/nolog_test.c b/test/log/nolog_test.c index c4c0fa6cf81..341dbfc9310 100644 --- a/test/log/nolog_test.c +++ b/test/log/nolog_test.c @@ -25,11 +25,10 @@ static int log_test_nolog_err(struct unit_test_state *uts) char buf[BUFFSIZE]; memset(buf, 0, BUFFSIZE); - console_record_reset_enable(); log_err("testing %s\n", "log_err"); gd->flags &= ~GD_FLG_RECORD; ut_assertok(ut_check_console_line(uts, "testing log_err")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } LOG_TEST(log_test_nolog_err); @@ -39,11 +38,10 @@ static int log_test_nolog_warning(struct unit_test_state *uts) char buf[BUFFSIZE]; memset(buf, 0, BUFFSIZE); - console_record_reset_enable(); log_warning("testing %s\n", "log_warning"); gd->flags &= ~GD_FLG_RECORD; ut_assertok(ut_check_console_line(uts, "testing log_warning")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } LOG_TEST(log_test_nolog_warning); @@ -53,11 +51,10 @@ static int log_test_nolog_notice(struct unit_test_state *uts) char buf[BUFFSIZE]; memset(buf, 0, BUFFSIZE); - console_record_reset_enable(); log_notice("testing %s\n", "log_notice"); gd->flags &= ~GD_FLG_RECORD; ut_assertok(ut_check_console_line(uts, "testing log_notice")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } LOG_TEST(log_test_nolog_notice); @@ -67,11 +64,10 @@ static int log_test_nolog_info(struct unit_test_state *uts) char buf[BUFFSIZE]; memset(buf, 0, BUFFSIZE); - console_record_reset_enable(); log_err("testing %s\n", "log_info"); gd->flags &= ~GD_FLG_RECORD; ut_assertok(ut_check_console_line(uts, "testing log_info")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } LOG_TEST(log_test_nolog_info); @@ -83,10 +79,9 @@ static int nolog_test_nodebug(struct unit_test_state *uts) char buf[BUFFSIZE]; memset(buf, 0, BUFFSIZE); - console_record_reset_enable(); debug("testing %s\n", "debug"); gd->flags &= ~GD_FLG_RECORD; - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } LOG_TEST(nolog_test_nodebug); @@ -96,11 +91,10 @@ static int log_test_nolog_nodebug(struct unit_test_state *uts) char buf[BUFFSIZE]; memset(buf, 0, BUFFSIZE); - console_record_reset_enable(); log_debug("testing %s\n", "log_debug"); gd->flags &= ~GD_FLG_RECORD; ut_assert(!strcmp(buf, "")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } LOG_TEST(log_test_nolog_nodebug); @@ -112,11 +106,10 @@ static int nolog_test_debug(struct unit_test_state *uts) char buf[BUFFSIZE]; memset(buf, 0, BUFFSIZE); - console_record_reset_enable(); debug("testing %s\n", "debug"); gd->flags &= ~GD_FLG_RECORD; ut_assertok(ut_check_console_line(uts, "testing debug")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } LOG_TEST(nolog_test_debug); @@ -126,13 +119,12 @@ static int log_test_nolog_debug(struct unit_test_state *uts) char buf[BUFFSIZE]; memset(buf, 0, BUFFSIZE); - console_record_reset_enable(); log_debug("testing %s\n", "log_debug"); log(LOGC_NONE, LOGL_DEBUG, "more %s\n", "log_debug"); gd->flags &= ~GD_FLG_RECORD; ut_assertok(ut_check_console_line(uts, "testing log_debug")); ut_assertok(ut_check_console_line(uts, "more log_debug")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } LOG_TEST(log_test_nolog_debug); diff --git a/test/log/pr_cont_test.c b/test/log/pr_cont_test.c index 30f30d98fe1..7734e927f98 100644 --- a/test/log/pr_cont_test.c +++ b/test/log/pr_cont_test.c @@ -28,14 +28,13 @@ static int log_test_pr_cont(struct unit_test_state *uts) /* Write two messages, the second continuing the first */ gd->log_fmt = BIT(LOGF_MSG); gd->default_log_level = LOGL_INFO; - console_record_reset_enable(); pr_err("ea%d ", 1); pr_cont("cc%d\n", 2); gd->default_log_level = log_level; gd->log_fmt = log_fmt; gd->flags &= ~GD_FLG_RECORD; ut_assertok(ut_check_console_line(uts, "ea1 cc2")); - ut_assertok(ut_check_console_end(uts)); + ut_assert_console_end(); return 0; } diff --git a/test/overlay/Kconfig b/test/overlay/Kconfig index a4f154415db..881848968bb 100644 --- a/test/overlay/Kconfig +++ b/test/overlay/Kconfig @@ -1,6 +1,6 @@ config UT_OVERLAY bool "Enable Device Tree Overlays Unit Tests" - depends on UNIT_TEST && OF_CONTROL + depends on UNIT_TEST && OF_CONTROL && SANDBOX default y select OF_LIBFDT_OVERLAY help diff --git a/test/print_ut.c b/test/print_ut.c index cf0d5929508..f5e607b21a3 100644 --- a/test/print_ut.c +++ b/test/print_ut.c @@ -180,14 +180,12 @@ static int print_display_buffer(struct unit_test_state *uts) buf[i] = i * 0x11; /* bytes */ - console_record_reset(); print_buffer(0, buf, 1, 0x12, 0); ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........"); ut_assert_nextline("00000010: 10 00 .."); ut_assert_console_end(); /* line length */ - console_record_reset(); print_buffer(0, buf, 1, 0x12, 8); ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 ..\"3DUfw"); ut_assert_nextline("00000008: 88 99 aa bb cc dd ee ff ........"); @@ -195,7 +193,6 @@ static int print_display_buffer(struct unit_test_state *uts) ut_assert_console_end(); /* long line */ - console_record_reset(); buf[0x41] = 0x41; print_buffer(0, buf, 1, 0x42, 0x40); ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..\"3DUfw........................................................"); @@ -203,35 +200,30 @@ static int print_display_buffer(struct unit_test_state *uts) ut_assert_console_end(); /* address */ - console_record_reset(); print_buffer(0x12345678, buf, 1, 0x12, 0); ut_assert_nextline("12345678: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........"); ut_assert_nextline("12345688: 10 00 .."); ut_assert_console_end(); /* 16-bit */ - console_record_reset(); print_buffer(0, buf, 2, 9, 0); ut_assert_nextline("00000000: 1100 3322 5544 7766 9988 bbaa ddcc ffee ..\"3DUfw........"); ut_assert_nextline("00000010: 0010 .."); ut_assert_console_end(); /* 32-bit */ - console_record_reset(); print_buffer(0, buf, 4, 5, 0); ut_assert_nextline("00000000: 33221100 77665544 bbaa9988 ffeeddcc ..\"3DUfw........"); ut_assert_nextline("00000010: 00000010 ...."); ut_assert_console_end(); /* 64-bit */ - console_record_reset(); print_buffer(0, buf, 8, 3, 0); ut_assert_nextline("00000000: 7766554433221100 ffeeddccbbaa9988 ..\"3DUfw........"); ut_assert_nextline("00000010: 0000000000000010 ........"); ut_assert_console_end(); /* ASCII */ - console_record_reset(); buf[1] = 31; buf[2] = 32; buf[3] = 33; @@ -289,7 +281,6 @@ static int print_do_hex_dump(struct unit_test_state *uts) buf[i] = i * 0x11; /* bytes */ - console_record_reset(); print_hex_dump_bytes("", DUMP_PREFIX_ADDRESS, buf, 0x12); ut_assert_nextline("%0*lx: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........", IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL); @@ -298,7 +289,6 @@ static int print_do_hex_dump(struct unit_test_state *uts) ut_assert_console_end(); /* line length */ - console_record_reset(); print_hex_dump("", DUMP_PREFIX_ADDRESS, 8, 1, buf, 0x12, true); ut_assert_nextline("%0*lx: 00 11 22 33 44 55 66 77 ..\"3DUfw", IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL); @@ -310,7 +300,6 @@ static int print_do_hex_dump(struct unit_test_state *uts) unmap_sysmem(buf); /* long line */ - console_record_reset(); buf[0x41] = 0x41; print_hex_dump("", DUMP_PREFIX_ADDRESS, 0x40, 1, buf, 0x42, true); ut_assert_nextline("%0*lx: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..\"3DUfw........................................................", @@ -320,7 +309,6 @@ static int print_do_hex_dump(struct unit_test_state *uts) ut_assert_console_end(); /* 16-bit */ - console_record_reset(); print_hex_dump("", DUMP_PREFIX_ADDRESS, 0, 2, buf, 0x12, true); ut_assert_nextline("%0*lx: 1100 3322 5544 7766 9988 bbaa ddcc ffee ..\"3DUfw........", IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL); @@ -330,7 +318,6 @@ static int print_do_hex_dump(struct unit_test_state *uts) unmap_sysmem(buf); /* 32-bit */ - console_record_reset(); print_hex_dump("", DUMP_PREFIX_ADDRESS, 0, 4, buf, 0x14, true); ut_assert_nextline("%0*lx: 33221100 77665544 bbaa9988 ffeeddcc ..\"3DUfw........", IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL); @@ -340,7 +327,6 @@ static int print_do_hex_dump(struct unit_test_state *uts) unmap_sysmem(buf); /* 64-bit */ - console_record_reset(); print_hex_dump("", DUMP_PREFIX_ADDRESS, 16, 8, buf, 0x18, true); ut_assert_nextline("%0*lx: 7766554433221100 ffeeddccbbaa9988 ..\"3DUfw........", IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL); @@ -350,7 +336,6 @@ static int print_do_hex_dump(struct unit_test_state *uts) unmap_sysmem(buf); /* ASCII */ - console_record_reset(); buf[1] = 31; buf[2] = 32; buf[3] = 33; diff --git a/test/py/requirements.txt b/test/py/requirements.txt index 2b1489808c0..75760f96e56 100644 --- a/test/py/requirements.txt +++ b/test/py/requirements.txt @@ -1,14 +1,14 @@ atomicwrites==1.4.1 attrs==19.3.0 concurrencytest==0.1.2 -coverage==4.5.4 +coverage==6.2 extras==1.0.0 filelock==3.0.12 fixtures==3.0.0 importlib-metadata==0.23 linecache2==1.0.0 more-itertools==7.2.0 -packaging==23.2 +packaging==24.1 pbr==5.4.3 pluggy==0.13.0 py==1.11.0 @@ -20,7 +20,7 @@ pytest==6.2.5 pytest-xdist==2.5.0 python-mimeparse==1.6.0 python-subunit==1.3.0 -requests==2.32.2 +requests==2.32.3 setuptools==70.3.0 six==1.16.0 testtools==2.3.0 diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py index 11bcdc2bb29..a726c71c113 100644 --- a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py +++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py @@ -147,7 +147,7 @@ class TestEfiCapsuleFirmwareFit(): verify_content(u_boot_console, '150000', 'u-boot-env:Old') else: # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT. - assert '3673B45D-6A7C-46F3-9E60-ADABB03F7937' in ''.join(output) + assert '985F2937-7C2E-5E9A-8A5E-8E063312964B' in ''.join(output) assert 'ESRT: fw_version=5' in ''.join(output) assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output) diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py index f3a2dff5c2c..8a790405c7c 100644 --- a/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py +++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py @@ -145,10 +145,10 @@ class TestEfiCapsuleFirmwareRaw: 'efidebug capsule esrt']) # ensure that SANDBOX_UBOOT_ENV_IMAGE_GUID is in the ESRT. - assert '5A7021F5-FEF2-48B4-AABA-832E777418C0' in ''.join(output) + assert '9E339473-C2EB-530A-A69B-0CD6BBBED40E' in ''.join(output) # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT. - assert '09D7CF52-0720-4710-91D1-08469B7FE9C8' in ''.join(output) + assert '985F2937-7C2E-5E9A-8A5E-8E063312964B' in ''.join(output) check_file_removed(u_boot_console, disk_img, capsule_files) @@ -199,12 +199,12 @@ class TestEfiCapsuleFirmwareRaw: verify_content(u_boot_console, '150000', 'u-boot-env:Old') else: # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT. - assert '09D7CF52-0720-4710-91D1-08469B7FE9C8' in ''.join(output) + assert '985F2937-7C2E-5E9A-8A5E-8E063312964B' in ''.join(output) assert 'ESRT: fw_version=5' in ''.join(output) assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output) # ensure that SANDBOX_UBOOT_ENV_IMAGE_GUID is in the ESRT. - assert '5A7021F5-FEF2-48B4-AABA-832E777418C0' in ''.join(output) + assert '9E339473-C2EB-530A-A69B-0CD6BBBED40E' in ''.join(output) assert 'ESRT: fw_version=10' in ''.join(output) assert 'ESRT: lowest_supported_fw_version=7' in ''.join(output) diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py index 44a58baa310..debbce8bdbd 100644 --- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py +++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py @@ -157,7 +157,7 @@ class TestEfiCapsuleFirmwareSignedFit(): 'efidebug capsule esrt']) # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT. - assert '3673B45D-6A7C-46F3-9E60-ADABB03F7937' in ''.join(output) + assert '46610520-469E-59DC-A8DD-C11832B877EA' in ''.join(output) assert 'ESRT: fw_version=5' in ''.join(output) assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output) diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py index 83a10e160b8..439bd71b3a7 100644 --- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py +++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py @@ -151,12 +151,12 @@ class TestEfiCapsuleFirmwareSignedRaw(): 'efidebug capsule esrt']) # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT. - assert '09D7CF52-0720-4710-91D1-08469B7FE9C8' in ''.join(output) + assert '985F2937-7C2E-5E9A-8A5E-8E063312964B' in ''.join(output) assert 'ESRT: fw_version=5' in ''.join(output) assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output) # ensure that SANDBOX_UBOOT_ENV_IMAGE_GUID is in the ESRT. - assert '5A7021F5-FEF2-48B4-AABA-832E777418C0' in ''.join(output) + assert '9E339473-C2EB-530A-A69B-0CD6BBBED40E' in ''.join(output) assert 'ESRT: fw_version=10' in ''.join(output) assert 'ESRT: lowest_supported_fw_version=7' in ''.join(output) diff --git a/test/py/tests/test_efi_capsule/version.dtso b/test/py/tests/test_efi_capsule/version.dtso index 07850cc6064..3aebb5b64fb 100644 --- a/test/py/tests/test_efi_capsule/version.dtso +++ b/test/py/tests/test_efi_capsule/version.dtso @@ -8,17 +8,17 @@ image1 { lowest-supported-version = <3>; image-index = <1>; - image-type-id = "09D7CF52-0720-4710-91D1-08469B7FE9C8"; + image-type-id = "985F2937-7C2E-5E9A-8A5E-8E063312964B"; }; image2 { lowest-supported-version = <7>; image-index = <2>; - image-type-id = "5A7021F5-FEF2-48B4-AABA-832E777418C0"; + image-type-id = "9E339473-C2EB-530A-A69B-0CD6BBBED40E"; }; image3 { lowest-supported-version = <3>; image-index = <1>; - image-type-id = "3673B45D-6A7C-46F3-9E60-ADABB03F7937"; + image-type-id = "46610520-469E-59DC-A8DD-C11832B877EA"; }; }; }; diff --git a/test/py/tests/test_spi.py b/test/py/tests/test_spi.py new file mode 100644 index 00000000000..3160d58540f --- /dev/null +++ b/test/py/tests/test_spi.py @@ -0,0 +1,696 @@ +# SPDX-License-Identifier: GPL-2.0 +# (C) Copyright 2024, Advanced Micro Devices, Inc. + +""" +Note: This test relies on boardenv_* containing configuration values to define +spi minimum and maximum frequencies at which the flash part can operate on and +these tests run at different spi frequency randomised values in the range +multiple times based on the user defined iteration value. +It also defines the SPI bus number containing the SPI-flash chip, SPI +chip-select, SPI mode, SPI flash part name and timeout parameters. If minimum +and maximum frequency is not defined, it will run on freq 0 by default. + +Without the boardenv_* configuration, this test will be automatically skipped. + +It also relies on configuration values for supported flashes for lock and +unlock cases for SPI family flash. It will run lock-unlock cases only for the +supported flash parts. + +For Example: + +# Details of SPI device test parameters required for SPI device testing: + +# bus - SPI bus number to init the flash device +# chip_select - SPI chip select number to init the flash device +# min_freq - Minimum frequency in hz at which the flash part can operate, set 0 +# or None for default frequency +# max_freq - Maximum frequency in hz at which the flash part can operate, set 0 +# or None for default frequency +# mode - SPI mode to init the flash device +# part_name - SPI flash part name to be detected +# timeout - Default timeout to run the sf commands +# iteration - No of iteration to run SPI flash test + +env__spi_device_test = { + 'bus': 0, + 'chip_select': 0, + 'min_freq': 10000000, + 'max_freq': 100000000, + 'mode': 0, + 'part_name': 'n25q00a', + 'timeout': 100000, + 'iteration': 5, +} + +# supported_flash - Flash parts name which support lock-unlock functionality +env__spi_lock_unlock = { + 'supported_flash': 'mt25qu512a, n25q00a, n25q512ax3', +} +""" + +import random +import re +import pytest +import u_boot_utils + +SPI_DATA = {} +EXPECTED_ERASE = 'Erased: OK' +EXPECTED_WRITE = 'Written: OK' +EXPECTED_READ = 'Read: OK' +EXPECTED_ERASE_ERRORS = [ + 'Erase operation failed', + 'Attempted to modify a protected sector', + 'Erased: ERROR', + 'is protected and cannot be erased', + 'ERROR: flash area is locked', +] +EXPECTED_WRITE_ERRORS = [ + 'ERROR: flash area is locked', + 'Program operation failed', + 'Attempted to modify a protected sector', + 'Written: ERROR', +] + +def get_params_spi(u_boot_console): + ''' Get SPI device test parameters from boardenv file ''' + f = u_boot_console.config.env.get('env__spi_device_test', None) + if not f: + pytest.skip('No env file to read for SPI family device test') + + bus = f.get('bus', 0) + cs = f.get('chip_select', 0) + mode = f.get('mode', 0) + part_name = f.get('part_name', None) + timeout = f.get('timeout', None) + + if not part_name: + pytest.skip('No env file to read SPI family flash part name') + + return bus, cs, mode, part_name, timeout + +def spi_find_freq_range(u_boot_console): + '''Find out minimum and maximum frequnecies that SPI device can operate''' + f = u_boot_console.config.env.get('env__spi_device_test', None) + if not f: + pytest.skip('No env file to read for SPI family device test') + + min_f = f.get('min_freq', None) + max_f = f.get('max_freq', None) + iterations = f.get('iteration', 1) + + if not min_f: + min_f = 0 + if not max_f: + max_f = 0 + + max_f = max(max_f, min_f) + + return min_f, max_f, iterations + +def spi_pre_commands(u_boot_console, freq): + ''' Find out SPI family flash memory parameters ''' + bus, cs, mode, part_name, timeout = get_params_spi(u_boot_console) + + output = u_boot_console.run_command(f'sf probe {bus}:{cs} {freq} {mode}') + if not 'SF: Detected' in output: + pytest.fail('No SPI device available') + + if not part_name in output: + pytest.fail('SPI flash part name not recognized') + + m = re.search('page size (.+?) Bytes', output) + if m: + try: + page_size = int(m.group(1)) + except ValueError: + pytest.fail('SPI page size not recognized') + + m = re.search('erase size (.+?) KiB', output) + if m: + try: + erase_size = int(m.group(1)) + except ValueError: + pytest.fail('SPI erase size not recognized') + + erase_size *= 1024 + + m = re.search('total (.+?) MiB', output) + if m: + try: + total_size = int(m.group(1)) + except ValueError: + pytest.fail('SPI total size not recognized') + + total_size *= 1024 * 1024 + + m = re.search('Detected (.+?) with', output) + if m: + try: + flash_part = m.group(1) + assert flash_part == part_name + except ValueError: + pytest.fail('SPI flash part not recognized') + + global SPI_DATA + SPI_DATA = { + 'page_size': page_size, + 'erase_size': erase_size, + 'total_size': total_size, + 'flash_part': flash_part, + 'timeout': timeout, + } + +def get_page_size(): + ''' Get the SPI page size from spi data ''' + return SPI_DATA['page_size'] + +def get_erase_size(): + ''' Get the SPI erase size from spi data ''' + return SPI_DATA['erase_size'] + +def get_total_size(): + ''' Get the SPI total size from spi data ''' + return SPI_DATA['total_size'] + +def get_flash_part(): + ''' Get the SPI flash part name from spi data ''' + return SPI_DATA['flash_part'] + +def get_timeout(): + ''' Get the SPI timeout from spi data ''' + return SPI_DATA['timeout'] + +def spi_erase_block(u_boot_console, erase_size, total_size): + ''' Erase SPI flash memory block wise ''' + for start in range(0, total_size, erase_size): + output = u_boot_console.run_command(f'sf erase {hex(start)} {hex(erase_size)}') + assert EXPECTED_ERASE in output + +@pytest.mark.buildconfigspec('cmd_sf') +def test_spi_erase_block(u_boot_console): + ''' Test case to check SPI erase functionality by erasing memory regions + block-wise ''' + + min_f, max_f, loop = spi_find_freq_range(u_boot_console) + i = 0 + while i < loop: + spi_pre_commands(u_boot_console, random.randint(min_f, max_f)) + spi_erase_block(u_boot_console, get_erase_size(), get_total_size()) + i = i + 1 + +def spi_write_twice(u_boot_console, page_size, erase_size, total_size, timeout): + ''' Random write till page size, random till size and full size ''' + addr = u_boot_utils.find_ram_base(u_boot_console) + + old_size = 0 + for size in ( + random.randint(4, page_size), + random.randint(page_size, total_size), + total_size, + ): + offset = random.randint(4, page_size) + offset = offset & ~3 + size = size & ~3 + size = size - old_size + output = u_boot_console.run_command(f'crc32 {hex(addr + total_size)} {hex(size)}') + m = re.search('==> (.+?)$', output) + if not m: + pytest.fail('CRC32 failed') + + expected_crc32 = m.group(1) + if old_size % page_size: + old_size = int(old_size / page_size) + old_size *= page_size + + if size % erase_size: + erasesize = int(size / erase_size + 1) + erasesize *= erase_size + + eraseoffset = int(old_size / erase_size) + eraseoffset *= erase_size + + timeout = 100000000 + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command( + f'sf erase {hex(eraseoffset)} {hex(erasesize)}' + ) + assert EXPECTED_ERASE in output + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command( + f'sf write {hex(addr + total_size)} {hex(old_size)} {hex(size)}' + ) + assert EXPECTED_WRITE in output + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command( + f'sf read {hex(addr + total_size + offset)} {hex(old_size)} {hex(size)}' + ) + assert EXPECTED_READ in output + output = u_boot_console.run_command( + f'crc32 {hex(addr + total_size + offset)} {hex(size)}' + ) + assert expected_crc32 in output + old_size = size + +@pytest.mark.buildconfigspec('cmd_bdi') +@pytest.mark.buildconfigspec('cmd_sf') +@pytest.mark.buildconfigspec('cmd_memory') +def test_spi_write_twice(u_boot_console): + ''' Test to write data with random size twice for SPI ''' + min_f, max_f, loop = spi_find_freq_range(u_boot_console) + i = 0 + while i < loop: + spi_pre_commands(u_boot_console, random.randint(min_f, max_f)) + spi_write_twice( + u_boot_console, + get_page_size(), + get_erase_size(), + get_total_size(), + get_timeout() + ) + i = i + 1 + +def spi_write_continues(u_boot_console, page_size, erase_size, total_size, timeout): + ''' Write with random size of data to continue SPI write case ''' + spi_erase_block(u_boot_console, erase_size, total_size) + addr = u_boot_utils.find_ram_base(u_boot_console) + + output = u_boot_console.run_command(f'crc32 {hex(addr + 0x10000)} {hex(total_size)}') + m = re.search('==> (.+?)$', output) + if not m: + pytest.fail('CRC32 failed') + expected_crc32 = m.group(1) + + old_size = 0 + for size in ( + random.randint(4, page_size), + random.randint(page_size, total_size), + total_size, + ): + size = size & ~3 + size = size - old_size + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command( + f'sf write {hex(addr + 0x10000 + old_size)} {hex(old_size)} {hex(size)}' + ) + assert EXPECTED_WRITE in output + old_size += size + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command( + f'sf read {hex(addr + 0x10000 + total_size)} 0 {hex(total_size)}' + ) + assert EXPECTED_READ in output + + output = u_boot_console.run_command( + f'crc32 {hex(addr + 0x10000 + total_size)} {hex(total_size)}' + ) + assert expected_crc32 in output + +@pytest.mark.buildconfigspec('cmd_bdi') +@pytest.mark.buildconfigspec('cmd_sf') +@pytest.mark.buildconfigspec('cmd_memory') +def test_spi_write_continues(u_boot_console): + ''' Test to write more random size data for SPI ''' + min_f, max_f, loop = spi_find_freq_range(u_boot_console) + i = 0 + while i < loop: + spi_pre_commands(u_boot_console, random.randint(min_f, max_f)) + spi_write_twice( + u_boot_console, + get_page_size(), + get_erase_size(), + get_total_size(), + get_timeout(), + ) + i = i + 1 + +def spi_read_twice(u_boot_console, page_size, total_size, timeout): + ''' Read the whole SPI flash twice, random_size till full flash size, + random till page size ''' + for size in random.randint(4, page_size), random.randint(4, total_size), total_size: + addr = u_boot_utils.find_ram_base(u_boot_console) + size = size & ~3 + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command( + f'sf read {hex(addr + total_size)} 0 {hex(size)}' + ) + assert EXPECTED_READ in output + output = u_boot_console.run_command(f'crc32 {hex(addr + total_size)} {hex(size)}') + m = re.search('==> (.+?)$', output) + if not m: + pytest.fail('CRC32 failed') + expected_crc32 = m.group(1) + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command( + f'sf read {hex(addr + total_size + 10)} 0 {hex(size)}' + ) + assert EXPECTED_READ in output + output = u_boot_console.run_command( + f'crc32 {hex(addr + total_size + 10)} {hex(size)}' + ) + assert expected_crc32 in output + +@pytest.mark.buildconfigspec('cmd_sf') +@pytest.mark.buildconfigspec('cmd_bdi') +@pytest.mark.buildconfigspec('cmd_memory') +def test_spi_read_twice(u_boot_console): + ''' Test to read random data twice from SPI ''' + min_f, max_f, loop = spi_find_freq_range(u_boot_console) + i = 0 + while i < loop: + spi_pre_commands(u_boot_console, random.randint(min_f, max_f)) + spi_read_twice(u_boot_console, get_page_size(), get_total_size(), get_timeout()) + i = i + 1 + +def spi_erase_all(u_boot_console, total_size, timeout): + ''' Erase the full chip SPI ''' + start = 0 + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command(f'sf erase {start} {hex(total_size)}') + assert EXPECTED_ERASE in output + +@pytest.mark.buildconfigspec('cmd_sf') +def test_spi_erase_all(u_boot_console): + ''' Test to check full chip erase for SPI ''' + min_f, max_f, loop = spi_find_freq_range(u_boot_console) + i = 0 + while i < loop: + spi_pre_commands(u_boot_console, random.randint(min_f, max_f)) + spi_erase_all(u_boot_console, get_total_size(), get_timeout()) + i = i + 1 + +def flash_ops( + u_boot_console, ops, start, size, offset=0, exp_ret=0, exp_str='', not_exp_str='' +): + ''' Flash operations: erase, write and read ''' + + f = u_boot_console.config.env.get('env__spi_device_test', None) + if not f: + timeout = 1000000 + + timeout = f.get('timeout', 1000000) + + if ops == 'erase': + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command(f'sf erase {hex(start)} {hex(size)}') + else: + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command( + f'sf {ops} {hex(offset)} {hex(start)} {hex(size)}' + ) + + if exp_str: + assert exp_str in output + if not_exp_str: + assert not_exp_str not in output + + ret_code = u_boot_console.run_command('echo $?') + if exp_ret >= 0: + assert ret_code.endswith(str(exp_ret)) + + return output, ret_code + +def spi_unlock_exit(u_boot_console, addr, size): + ''' Unlock the flash before making it fail ''' + u_boot_console.run_command(f'sf protect unlock {hex(addr)} {hex(size)}') + assert False, 'FAIL: Flash lock is unable to protect the data!' + +def find_prot_region(lock_addr, lock_size): + ''' Get the protected and un-protected region of flash ''' + total_size = get_total_size() + erase_size = get_erase_size() + + if lock_addr < (total_size // 2): + sect_num = (lock_addr + lock_size) // erase_size + x = 1 + while x < sect_num: + x *= 2 + prot_start = 0 + prot_size = x * erase_size + unprot_start = prot_start + prot_size + unprot_size = total_size - unprot_start + else: + sect_num = (total_size - lock_addr) // erase_size + x = 1 + while x < sect_num: + x *= 2 + prot_start = total_size - (x * erase_size) + prot_size = total_size - prot_start + unprot_start = 0 + unprot_size = prot_start + + return prot_start, prot_size, unprot_start, unprot_size + +def protect_ops(u_boot_console, lock_addr, lock_size, ops="unlock"): + ''' Run the command to lock or Unlock the flash ''' + u_boot_console.run_command(f'sf protect {ops} {hex(lock_addr)} {hex(lock_size)}') + output = u_boot_console.run_command('echo $?') + if ops == "lock" and not output.endswith('0'): + u_boot_console.run_command(f'sf protect unlock {hex(lock_addr)} {hex(lock_size)}') + assert False, "sf protect lock command exits with non-zero return code" + assert output.endswith('0') + +def erase_write_ops(u_boot_console, start, size): + ''' Basic erase and write operation for flash ''' + addr = u_boot_utils.find_ram_base(u_boot_console) + flash_ops(u_boot_console, 'erase', start, size, 0, 0, EXPECTED_ERASE) + flash_ops(u_boot_console, 'write', start, size, addr, 0, EXPECTED_WRITE) + +def spi_lock_unlock(u_boot_console, lock_addr, lock_size): + ''' Lock unlock operations for SPI family flash ''' + addr = u_boot_utils.find_ram_base(u_boot_console) + erase_size = get_erase_size() + + # Find the protected/un-protected region + prot_start, prot_size, unprot_start, unprot_size = find_prot_region(lock_addr, lock_size) + + # Check erase/write operation before locking + erase_write_ops(u_boot_console, prot_start, prot_size) + + # Locking the flash + protect_ops(u_boot_console, lock_addr, lock_size, 'lock') + + # Check erase/write operation after locking + output, ret_code = flash_ops(u_boot_console, 'erase', prot_start, prot_size, 0, -1) + if not any(error in output for error in EXPECTED_ERASE_ERRORS) or ret_code.endswith( + '0' + ): + spi_unlock_exit(u_boot_console, lock_addr, lock_size) + + output, ret_code = flash_ops( + u_boot_console, 'write', prot_start, prot_size, addr, -1 + ) + if not any(error in output for error in EXPECTED_WRITE_ERRORS) or ret_code.endswith( + '0' + ): + spi_unlock_exit(u_boot_console, lock_addr, lock_size) + + # Check locked sectors + sect_lock_start = random.randrange(prot_start, (prot_start + prot_size), erase_size) + if prot_size > erase_size: + sect_lock_size = random.randrange( + erase_size, (prot_start + prot_size - sect_lock_start), erase_size + ) + else: + sect_lock_size = erase_size + sect_write_size = random.randint(1, sect_lock_size) + + output, ret_code = flash_ops( + u_boot_console, 'erase', sect_lock_start, sect_lock_size, 0, -1 + ) + if not any(error in output for error in EXPECTED_ERASE_ERRORS) or ret_code.endswith( + '0' + ): + spi_unlock_exit(u_boot_console, lock_addr, lock_size) + + output, ret_code = flash_ops( + u_boot_console, 'write', sect_lock_start, sect_write_size, addr, -1 + ) + if not any(error in output for error in EXPECTED_WRITE_ERRORS) or ret_code.endswith( + '0' + ): + spi_unlock_exit(u_boot_console, lock_addr, lock_size) + + # Check unlocked sectors + if unprot_size != 0: + sect_unlock_start = random.randrange( + unprot_start, (unprot_start + unprot_size), erase_size + ) + if unprot_size > erase_size: + sect_unlock_size = random.randrange( + erase_size, (unprot_start + unprot_size - sect_unlock_start), erase_size + ) + else: + sect_unlock_size = erase_size + sect_write_size = random.randint(1, sect_unlock_size) + + output, ret_code = flash_ops( + u_boot_console, 'erase', sect_unlock_start, sect_unlock_size, 0, -1 + ) + if EXPECTED_ERASE not in output or ret_code.endswith('1'): + spi_unlock_exit(u_boot_console, lock_addr, lock_size) + + output, ret_code = flash_ops( + u_boot_console, 'write', sect_unlock_start, sect_write_size, addr, -1 + ) + if EXPECTED_WRITE not in output or ret_code.endswith('1'): + spi_unlock_exit(u_boot_console, lock_addr, lock_size) + + # Unlocking the flash + protect_ops(u_boot_console, lock_addr, lock_size, 'unlock') + + # Check erase/write operation after un-locking + erase_write_ops(u_boot_console, prot_start, prot_size) + + # Check previous locked sectors + sect_lock_start = random.randrange(prot_start, (prot_start + prot_size), erase_size) + if prot_size > erase_size: + sect_lock_size = random.randrange( + erase_size, (prot_start + prot_size - sect_lock_start), erase_size + ) + else: + sect_lock_size = erase_size + sect_write_size = random.randint(1, sect_lock_size) + + flash_ops( + u_boot_console, 'erase', sect_lock_start, sect_lock_size, 0, 0, EXPECTED_ERASE + ) + flash_ops( + u_boot_console, + 'write', + sect_lock_start, + sect_write_size, + addr, + 0, + EXPECTED_WRITE, + ) + +@pytest.mark.buildconfigspec('cmd_bdi') +@pytest.mark.buildconfigspec('cmd_sf') +@pytest.mark.buildconfigspec('cmd_memory') +def test_spi_lock_unlock(u_boot_console): + ''' Test to check the lock-unlock functionality for SPI family flash ''' + min_f, max_f, loop = spi_find_freq_range(u_boot_console) + flashes = u_boot_console.config.env.get('env__spi_lock_unlock', False) + if not flashes: + pytest.skip('No supported flash list for lock/unlock provided') + + i = 0 + while i < loop: + spi_pre_commands(u_boot_console, random.randint(min_f, max_f)) + total_size = get_total_size() + flash_part = get_flash_part() + + flashes_list = flashes.get('supported_flash', None).split(',') + flashes_list = [x.strip() for x in flashes_list] + if flash_part not in flashes_list: + pytest.skip('Detected flash does not support lock/unlock') + + # For lower half of memory + lock_addr = random.randint(0, (total_size // 2) - 1) + lock_size = random.randint(1, ((total_size // 2) - lock_addr)) + spi_lock_unlock(u_boot_console, lock_addr, lock_size) + + # For upper half of memory + lock_addr = random.randint((total_size // 2), total_size - 1) + lock_size = random.randint(1, (total_size - lock_addr)) + spi_lock_unlock(u_boot_console, lock_addr, lock_size) + + # For entire flash + lock_addr = random.randint(0, total_size - 1) + lock_size = random.randint(1, (total_size - lock_addr)) + spi_lock_unlock(u_boot_console, lock_addr, lock_size) + + i = i + 1 + +@pytest.mark.buildconfigspec('cmd_bdi') +@pytest.mark.buildconfigspec('cmd_sf') +@pytest.mark.buildconfigspec('cmd_memory') +def test_spi_negative(u_boot_console): + ''' Negative tests for SPI ''' + min_f, max_f, loop = spi_find_freq_range(u_boot_console) + spi_pre_commands(u_boot_console, random.randint(min_f, max_f)) + total_size = get_total_size() + erase_size = get_erase_size() + page_size = get_page_size() + addr = u_boot_utils.find_ram_base(u_boot_console) + i = 0 + while i < loop: + # Erase negative test + start = random.randint(0, total_size) + esize = erase_size + + # If erasesize is not multiple of flash's erase size + while esize % erase_size == 0: + esize = random.randint(0, total_size - start) + + error_msg = 'Erased: ERROR' + flash_ops( + u_boot_console, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE + ) + + # If eraseoffset exceeds beyond flash size + eoffset = random.randint(total_size, (total_size + int(0x1000000))) + error_msg = 'Offset exceeds device limit' + flash_ops( + u_boot_console, 'erase', eoffset, esize, 0, 1, error_msg, EXPECTED_ERASE + ) + + # If erasesize exceeds beyond flash size + esize = random.randint((total_size - start), (total_size + int(0x1000000))) + error_msg = 'ERROR: attempting erase past flash size' + flash_ops( + u_boot_console, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE + ) + + # If erase size is 0 + esize = 0 + error_msg = None + flash_ops( + u_boot_console, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE + ) + + # If erasesize is less than flash's page size + esize = random.randint(0, page_size) + start = random.randint(0, (total_size - page_size)) + error_msg = 'Erased: ERROR' + flash_ops( + u_boot_console, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE + ) + + # Write/Read negative test + # if Write/Read size exceeds beyond flash size + offset = random.randint(0, total_size) + size = random.randint((total_size - offset), (total_size + int(0x1000000))) + error_msg = 'Size exceeds partition or device limit' + flash_ops( + u_boot_console, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE + ) + flash_ops( + u_boot_console, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ + ) + + # if Write/Read offset exceeds beyond flash size + offset = random.randint(total_size, (total_size + int(0x1000000))) + size = random.randint(0, total_size) + error_msg = 'Offset exceeds device limit' + flash_ops( + u_boot_console, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE + ) + flash_ops( + u_boot_console, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ + ) + + # if Write/Read size is 0 + offset = random.randint(0, 2) + size = 0 + error_msg = None + flash_ops( + u_boot_console, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE + ) + flash_ops( + u_boot_console, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ + ) + + i = i + 1 diff --git a/tools/Makefile b/tools/Makefile index 6a4280e3668..ee08a9675df 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -246,12 +246,12 @@ HOSTCFLAGS_asn1_compiler.o = -idirafter $(srctree)/include HOSTCFLAGS_mkeficapsule.o += \ $(shell pkg-config --cflags gnutls 2> /dev/null || echo "") -HOSTCFLAGS_mkeficapsule.o += \ - $(shell pkg-config --cflags uuid 2> /dev/null || echo "") HOSTLDLIBS_mkeficapsule += \ $(shell pkg-config --libs gnutls 2> /dev/null || echo "-lgnutls") -HOSTLDLIBS_mkeficapsule += \ - $(shell pkg-config --libs uuid 2> /dev/null || echo "-luuid") +mkeficapsule-objs := generated/lib/uuid.o \ + generated/lib/sha1.o \ + $(LIBFDT_OBJS) \ + mkeficapsule.o hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule mkfwumdata-objs := mkfwumdata.o generated/lib/crc32.o diff --git a/tools/binman/etype/efi_capsule.py b/tools/binman/etype/efi_capsule.py index 5941545d0b2..768e006dc50 100644 --- a/tools/binman/etype/efi_capsule.py +++ b/tools/binman/etype/efi_capsule.py @@ -24,7 +24,7 @@ def get_binman_test_guid(type_str): The actual GUID value (str) """ TYPE_TO_GUID = { - 'binman-test' : '09d7cf52-0720-4710-91d1-08469b7fe9c8' + 'binman-test' : '985f2937-7c2e-5e9a-8a5e-8e063312964b' } return TYPE_TO_GUID[type_str] diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index 93f3d22cf57..2577c0016c0 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -125,7 +125,7 @@ TEE_ADDR = 0x5678 # Firmware Management Protocol(FMP) GUID FW_MGMT_GUID = '6dcbd5ed-e82d-4c44-bda1-7194199ad92a' # Image GUID specified in the DTS -CAPSULE_IMAGE_GUID = '09d7cf52-0720-4710-91d1-08469b7fe9c8' +CAPSULE_IMAGE_GUID = '985F2937-7C2E-5E9A-8A5E-8E063312964B' # Windows cert GUID WIN_CERT_TYPE_EFI_GUID = '4aafd29d-68df-49ee-8aa9-347d375665a7' # Empty capsule GUIDs diff --git a/tools/buildman/bsettings.py b/tools/buildman/bsettings.py index aea724fc559..a7358cfc08a 100644 --- a/tools/buildman/bsettings.py +++ b/tools/buildman/bsettings.py @@ -31,6 +31,9 @@ def setup(fname=''): def add_file(data): settings.read_file(io.StringIO(data)) +def add_section(name): + settings.add_section(name) + def get_items(section): """Get the items from a section of the config. diff --git a/tools/buildman/kconfiglib.py b/tools/buildman/kconfiglib.py index b9f37567559..27abbf9a7a1 100644 --- a/tools/buildman/kconfiglib.py +++ b/tools/buildman/kconfiglib.py @@ -6,7 +6,7 @@ Overview ======== Kconfiglib is a Python 2/3 library for scripting and extracting information -from Kconfig (https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt) +from Kconfig (https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.rst) configuration systems. See the homepage at https://github.com/ulfalizer/Kconfiglib for a longer @@ -709,7 +709,7 @@ class Kconfig(object): mainmenu_text: The prompt (title) of the top menu (top_node). Defaults to "Main menu". - Can be changed with the 'mainmenu' statement (see kconfig-language.txt). + Can be changed with the 'mainmenu' statement (see kconfig-language.rst). variables: A dictionary with all preprocessor variables, indexed by name. See the @@ -3562,7 +3562,7 @@ class Kconfig(object): # # - Propagates dependencies from parent to child nodes # - # - Creates implicit menus (see kconfig-language.txt) + # - Creates implicit menus (see kconfig-language.rst) # # - Removes 'if' nodes # @@ -5030,7 +5030,7 @@ class Choice(object): 0 (n) - The choice is disabled and no symbols can be selected. For visible choices, this mode is only possible for choices with - the 'optional' flag set (see kconfig-language.txt). + the 'optional' flag set (see kconfig-language.rst). 1 (m) - Any number of choice symbols can be set to m, the rest will be n. @@ -5498,7 +5498,7 @@ class MenuNode(object): Choices and menus naturally have children, but Symbols can also have children because of menus created automatically from dependencies (see - kconfig-language.txt). + kconfig-language.rst). parent: The parent menu node. None if there is no parent. diff --git a/tools/buildman/test.py b/tools/buildman/test.py index e9d2c7e41b0..5eed013d51c 100644 --- a/tools/buildman/test.py +++ b/tools/buildman/test.py @@ -148,6 +148,7 @@ class TestBuild(unittest.TestCase): self.toolchains.Add('arm-linux-gcc', test=False) self.toolchains.Add('sparc-linux-gcc', test=False) self.toolchains.Add('powerpc-linux-gcc', test=False) + self.toolchains.Add('/path/to/aarch64-linux-gcc', test=False) self.toolchains.Add('gcc', test=False) # Avoid sending any output @@ -869,6 +870,89 @@ class TestBuild(unittest.TestCase): self.assertEqual([4, 5], control.read_procs(tmpdir)) self.assertEqual(self.finish_time, self.cur_time) + def call_make_environment(self, tchn, full_path, in_env=None): + """Call Toolchain.MakeEnvironment() and process the result + + Args: + tchn (Toolchain): Toolchain to use + full_path (bool): True to return the full path in CROSS_COMPILE + rather than adding it to the PATH variable + in_env (dict): Input environment to use, None to use current env + + Returns: + tuple: + dict: Changes that MakeEnvironment has made to the environment + key: Environment variable that was changed + value: New value (for PATH this only includes components + which were added) + str: Full value of the new PATH variable + """ + env = tchn.MakeEnvironment(full_path, env=in_env) + + # Get the original environment + orig_env = dict(os.environb if in_env is None else in_env) + orig_path = orig_env[b'PATH'].split(b':') + + # Find new variables + diff = dict((k, env[k]) for k in env if orig_env.get(k) != env[k]) + + # Find new / different path components + diff_path = None + new_path = None + if b'PATH' in diff: + new_path = diff[b'PATH'].split(b':') + diff_paths = [p for p in new_path if p not in orig_path] + diff_path = b':'.join(p for p in new_path if p not in orig_path) + if diff_path: + diff[b'PATH'] = diff_path + else: + del diff[b'PATH'] + return diff, new_path + + def test_toolchain_env(self): + """Test PATH and other environment settings for toolchains""" + # Use a toolchain which has a path, so that full_path makes a difference + tchn = self.toolchains.Select('aarch64') + + # Normal cases + diff = self.call_make_environment(tchn, full_path=False)[0] + self.assertEqual( + {b'CROSS_COMPILE': b'aarch64-linux-', b'LC_ALL': b'C', + b'PATH': b'/path/to'}, diff) + + diff = self.call_make_environment(tchn, full_path=True)[0] + self.assertEqual( + {b'CROSS_COMPILE': b'/path/to/aarch64-linux-', b'LC_ALL': b'C'}, + diff) + + # When overriding the toolchain, only LC_ALL should be set + tchn.override_toolchain = True + diff = self.call_make_environment(tchn, full_path=True)[0] + self.assertEqual({b'LC_ALL': b'C'}, diff) + + # Test that virtualenv is handled correctly + tchn.override_toolchain = False + sys.prefix = '/some/venv' + env = dict(os.environb) + env[b'PATH'] = b'/some/venv/bin:other/things' + tchn.path = '/my/path' + diff, diff_path = self.call_make_environment(tchn, False, env) + + self.assertIn(b'PATH', diff) + self.assertEqual([b'/some/venv/bin', b'/my/path', b'other/things'], + diff_path) + self.assertEqual( + {b'CROSS_COMPILE': b'aarch64-linux-', b'LC_ALL': b'C', + b'PATH': b'/my/path'}, diff) + + # Handle a toolchain wrapper + tchn.path = '' + bsettings.add_section('toolchain-wrapper') + bsettings.set_item('toolchain-wrapper', 'my-wrapper', 'fred') + diff = self.call_make_environment(tchn, full_path=True)[0] + self.assertEqual( + {b'CROSS_COMPILE': b'fred aarch64-linux-', b'LC_ALL': b'C'}, diff) + if __name__ == "__main__": unittest.main() diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index 324ad0e0821..6ca79c2c0f9 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -172,13 +172,14 @@ class Toolchain: else: raise ValueError('Unknown arg to GetEnvArgs (%d)' % which) - def MakeEnvironment(self, full_path): + def MakeEnvironment(self, full_path, env=None): """Returns an environment for using the toolchain. This takes the current environment and adds CROSS_COMPILE so that the tool chain will operate correctly. This also disables localized output and possibly Unicode encoded output of all build tools by - adding LC_ALL=C. + adding LC_ALL=C. For the case where full_path is False, it prepends + the toolchain to PATH Note that os.environb is used to obtain the environment, since in some cases the environment many contain non-ASCII characters and we see @@ -187,15 +188,21 @@ class Toolchain: UnicodeEncodeError: 'utf-8' codec can't encode characters in position 569-570: surrogates not allowed + When running inside a Python venv, care is taken not to put the + toolchain path before the venv path, so that builds initiated by + buildman will still respect the venv. + Args: full_path: Return the full path in CROSS_COMPILE and don't set PATH + env (dict of bytes): Original environment, used for testing Returns: Dict containing the (bytes) environment to use. This is based on the current environment, with changes as needed to CROSS_COMPILE, PATH and LC_ALL. """ - env = dict(os.environb) + env = dict(env or os.environb) + wrapper = self.GetWrapper() if self.override_toolchain: @@ -206,7 +213,23 @@ class Toolchain: wrapper + os.path.join(self.path, self.cross)) else: env[b'CROSS_COMPILE'] = tools.to_bytes(wrapper + self.cross) - env[b'PATH'] = tools.to_bytes(self.path) + b':' + env[b'PATH'] + + # Detect a Python virtualenv and avoid defeating it + if sys.prefix != sys.base_prefix: + paths = env[b'PATH'].split(b':') + new_paths = [] + to_insert = tools.to_bytes(self.path) + insert_after = tools.to_bytes(sys.prefix) + for path in paths: + new_paths.append(path) + if to_insert and path.startswith(insert_after): + new_paths.append(to_insert) + to_insert = None + if to_insert: + new_paths.append(to_insert) + env[b'PATH'] = b':'.join(new_paths) + else: + env[b'PATH'] = tools.to_bytes(self.path) + b':' + env[b'PATH'] env[b'LC_ALL'] = b'C' diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index cda87354566..c401170b1e1 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -2,9 +2,9 @@ # This Dockerfile is used to build an image containing basic stuff to be used # to build U-Boot and run our test suites. -FROM ubuntu:jammy-20240227 -MAINTAINER Tom Rini <trini@konsulko.com> -LABEL Description=" This image is for building U-Boot inside a container" +FROM ubuntu:jammy-20240808 +LABEL org.opencontainers.image.authors="Tom Rini <trini@konsulko.com>" +LABEL org.opencontainers.image.description=" This image is for building U-Boot inside a container" # Make sure apt is happy ENV DEBIAN_FRONTEND=noninteractive diff --git a/tools/eficapsule.h b/tools/eficapsule.h index 6efd07d2eb6..97d077536d5 100644 --- a/tools/eficapsule.h +++ b/tools/eficapsule.h @@ -24,7 +24,7 @@ #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -typedef struct { +typedef struct efi_guid { uint8_t b[16]; } efi_guid_t __aligned(8); diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c index f28008a0829..49f5b7849e4 100644 --- a/tools/mkeficapsule.c +++ b/tools/mkeficapsule.c @@ -5,6 +5,7 @@ */ #include <getopt.h> +#include <inttypes.h> #include <pe.h> #include <stdbool.h> #include <stdint.h> @@ -15,16 +16,20 @@ #include <sys/stat.h> #include <sys/types.h> -#include <uuid/uuid.h> #include <gnutls/gnutls.h> #include <gnutls/pkcs7.h> #include <gnutls/abstract.h> #include <version.h> +#include <libfdt.h> +#include <u-boot/uuid.h> #include "eficapsule.h" +// Matches CONFIG_EFI_CAPSULE_NAMESPACE_GUID +#define DEFAULT_NAMESPACE_GUID "8c9f137e-91dc-427b-b2d6-b420faebaf2a" + static const char *tool_name = "mkeficapsule"; efi_guid_t efi_guid_fm_capsule = EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID; @@ -55,9 +60,20 @@ static struct option options[] = { {NULL, 0, NULL, 0}, }; -static void print_usage(void) +static void print_usage_guidgen(void) { - fprintf(stderr, "Usage: %s [options] <image blob> <output file>\n" + fprintf(stderr, "%s guidgen [GUID] DTB IMAGE_NAME...\n" + "Options:\n" + + "\tGUID Namespace GUID (default: %s)\n" + "\tDTB Device Tree Blob\n" + "\tIMAGE_NAME... One or more names of fw_images to generate GUIDs for\n", + tool_name, DEFAULT_NAMESPACE_GUID); +} + +static void print_usage_mkeficapsule(void) +{ + fprintf(stderr, "Usage:\n\n%s [options] <image blob> <output file>\n" "Options:\n" "\t-g, --guid <guid string> guid for image blob type\n" @@ -73,8 +89,9 @@ static void print_usage(void) "\t-o, --capoemflag Capsule OEM Flag, an integer between 0x0000 and 0xffff\n" "\t-D, --dump-capsule dump the contents of the capsule headers\n" "\t-V, --version show version number\n" - "\t-h, --help print a help message\n", + "\t-h, --help print a help message\n\n", tool_name); + print_usage_guidgen(); } /** @@ -577,37 +594,6 @@ err: return ret; } -/** - * convert_uuid_to_guid() - convert UUID to GUID - * @buf: UUID binary - * - * UUID and GUID have the same data structure, but their binary - * formats are different due to the endianness. See lib/uuid.c. - * Since uuid_parse() can handle only UUID, this function must - * be called to get correct data for GUID when parsing a string. - * - * The correct data will be returned in @buf. - */ -void convert_uuid_to_guid(unsigned char *buf) -{ - unsigned char c; - - c = buf[0]; - buf[0] = buf[3]; - buf[3] = c; - c = buf[1]; - buf[1] = buf[2]; - buf[2] = c; - - c = buf[4]; - buf[4] = buf[5]; - buf[5] = c; - - c = buf[6]; - buf[6] = buf[7]; - buf[7] = c; -} - static int create_empty_capsule(char *path, efi_guid_t *guid, bool fw_accept) { struct efi_capsule_header header = { 0 }; @@ -653,20 +639,10 @@ err: static void print_guid(void *ptr) { - int i; - efi_guid_t *guid = ptr; - const uint8_t seq[] = { - 3, 2, 1, 0, '-', 5, 4, '-', 7, 6, - '-', 8, 9, '-', 10, 11, 12, 13, 14, 15 }; - - for (i = 0; i < ARRAY_SIZE(seq); i++) { - if (seq[i] == '-') - putchar(seq[i]); - else - printf("%02X", guid->b[seq[i]]); - } + static char buf[37] = { 0 }; - printf("\n"); + uuid_bin_to_str(ptr, buf, UUID_STR_FORMAT_GUID | UUID_STR_UPPER_CASE); + printf("%s\n", buf); } static uint32_t dump_fmp_payload_header( @@ -691,7 +667,7 @@ static uint32_t dump_fmp_payload_header( static void dump_capsule_auth_header( struct efi_firmware_image_authentication *capsule_auth_hdr) { - printf("EFI_FIRMWARE_IMAGE_AUTH.MONOTONIC_COUNT\t\t: %08lX\n", + printf("EFI_FIRMWARE_IMAGE_AUTH.MONOTONIC_COUNT\t\t: %08" PRIX64 "\n", capsule_auth_hdr->monotonic_count); printf("EFI_FIRMWARE_IMAGE_AUTH.AUTH_INFO.HDR.dwLENGTH\t: %08X\n", capsule_auth_hdr->auth_info.hdr.dwLength); @@ -724,9 +700,9 @@ static void dump_fmp_capsule_image_header( image_hdr->update_image_size); printf("FMP_CAPSULE_IMAGE_HDR.UPDATE_VENDOR_CODE_SIZE\t: %08X\n", image_hdr->update_vendor_code_size); - printf("FMP_CAPSULE_IMAGE_HDR.UPDATE_HARDWARE_INSTANCE\t: %08lX\n", + printf("FMP_CAPSULE_IMAGE_HDR.UPDATE_HARDWARE_INSTANCE\t: %08" PRIX64 "\n", image_hdr->update_hardware_instance); - printf("FMP_CAPSULE_IMAGE_HDR.IMAGE_CAPSULE_SUPPORT\t: %08lX\n", + printf("FMP_CAPSULE_IMAGE_HDR.IMAGE_CAPSULE_SUPPORT\t: %08" PRIX64 "\n", image_hdr->image_capsule_support); printf("--------\n"); @@ -860,6 +836,129 @@ static void dump_capsule_contents(char *capsule_file) } } +static struct fdt_header *load_dtb(const char *path) +{ + struct fdt_header *dtb; + ssize_t dtb_size; + FILE *f; + + /* Open and parse DTB */ + f = fopen(path, "r"); + if (!f) { + fprintf(stderr, "Cannot open %s\n", path); + return NULL; + } + + if (fseek(f, 0, SEEK_END)) { + fprintf(stderr, "Cannot seek to the end of %s: %s\n", + path, strerror(errno)); + return NULL; + } + + dtb_size = ftell(f); + if (dtb_size < 0) { + fprintf(stderr, "Cannot ftell %s: %s\n", + path, strerror(errno)); + return NULL; + } + + fseek(f, 0, SEEK_SET); + + dtb = malloc(dtb_size); + if (!dtb) { + fprintf(stderr, "Can't allocated %ld\n", dtb_size); + return NULL; + } + + if (fread(dtb, dtb_size, 1, f) != 1) { + fprintf(stderr, "Can't read %ld bytes from %s\n", + dtb_size, path); + free(dtb); + return NULL; + } + + fclose(f); + + return dtb; +} + +#define MAX_IMAGE_NAME_LEN 128 +static int genguid(int argc, char **argv) +{ + int idx = 2, ret; + unsigned char namespace[16]; + struct efi_guid image_type_id; + const char *dtb_path; + struct fdt_header *dtb; + const char *compatible; + int compatlen, namelen; + uint16_t fw_image[MAX_IMAGE_NAME_LEN]; + + if (argc < 2) { + fprintf(stderr, "Usage: "); + print_usage_guidgen(); + return -1; + } + + if (uuid_str_to_bin(argv[1], namespace, UUID_STR_FORMAT_GUID)) { + uuid_str_to_bin(DEFAULT_NAMESPACE_GUID, namespace, UUID_STR_FORMAT_GUID); + dtb_path = argv[1]; + } else { + dtb_path = argv[2]; + idx = 3; + } + + if (idx == argc) { + fprintf(stderr, "Usage: "); + print_usage_guidgen(); + return -1; + } + + dtb = load_dtb(dtb_path); + if (!dtb) + return -1; + + ret = fdt_check_header(dtb); + if (ret) { + fprintf(stderr, "Invalid DTB header: %d\n", ret); + return -1; + } + + compatible = fdt_getprop(dtb, 0, "compatible", &compatlen); + if (!compatible) { + fprintf(stderr, "No compatible string found in DTB\n"); + return -1; + } + if (strnlen(compatible, compatlen) >= compatlen) { + fprintf(stderr, "Compatible string not null-terminated\n"); + return -1; + } + + printf("Generating GUIDs for %s with namespace %s:\n", + compatible, DEFAULT_NAMESPACE_GUID); + for (; idx < argc; idx++) { + memset(fw_image, 0, sizeof(fw_image)); + namelen = strlen(argv[idx]); + if (namelen > MAX_IMAGE_NAME_LEN) { + fprintf(stderr, "Image name too long: %s\n", argv[idx]); + return -1; + } + + for (int i = 0; i < namelen; i++) + fw_image[i] = (uint16_t)argv[idx][i]; + + gen_v5_guid((struct uuid *)&namespace, &image_type_id, + compatible, strlen(compatible), + fw_image, namelen * sizeof(uint16_t), + NULL); + + printf("%s: ", argv[idx]); + print_guid(&image_type_id); + } + + return 0; +} + /** * main - main entry function of mkeficapsule * @argc: Number of arguments @@ -884,6 +983,13 @@ int main(int argc, char **argv) int c, idx; struct fmp_payload_header_params fmp_ph_params = { 0 }; + /* Generate dynamic GUIDs */ + if (argc > 1 && !strcmp(argv[1], "guidgen")) { + if (genguid(argc - 1, argv + 1)) + exit(EXIT_FAILURE); + exit(EXIT_SUCCESS); + } + guid = NULL; index = 0; instance = 0; @@ -906,11 +1012,10 @@ int main(int argc, char **argv) "Image type already specified\n"); exit(EXIT_FAILURE); } - if (uuid_parse(optarg, uuid_buf)) { + if (uuid_str_to_bin(optarg, uuid_buf, UUID_STR_FORMAT_GUID)) { fprintf(stderr, "Wrong guid format\n"); exit(EXIT_FAILURE); } - convert_uuid_to_guid(uuid_buf); guid = (efi_guid_t *)uuid_buf; break; case 'i': @@ -976,7 +1081,7 @@ int main(int argc, char **argv) printf("mkeficapsule version %s\n", PLAIN_VERSION); exit(EXIT_SUCCESS); default: - print_usage(); + print_usage_mkeficapsule(); exit(EXIT_FAILURE); } } @@ -999,7 +1104,7 @@ int main(int argc, char **argv) ((argc != optind + 1) || ((capsule_type == CAPSULE_ACCEPT) && !guid) || ((capsule_type == CAPSULE_REVERT) && guid)))) { - print_usage(); + print_usage_mkeficapsule(); exit(EXIT_FAILURE); } diff --git a/tools/patman/commit.py b/tools/patman/commit.py index 684225c0e60..ce37a3d95eb 100644 --- a/tools/patman/commit.py +++ b/tools/patman/commit.py @@ -6,7 +6,7 @@ import collections import re # Separates a tag: at the beginning of the subject from the rest of it -re_subject_tag = re.compile('([^:\s]*):\s*(.*)') +re_subject_tag = re.compile(r'([^:\s]*):\s*(.*)') class Commit: """Holds information about a single commit/patch in the series. diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index a09ae9c7371..4955f6aaab9 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -48,7 +48,7 @@ RE_TAG = re.compile('^(Tested-by|Acked-by|Reviewed-by|Patch-cc|Fixes): (.*)') RE_COMMIT = re.compile('^commit ([0-9a-f]*)$') # We detect these since checkpatch doesn't always do it -RE_SPACE_BEFORE_TAB = re.compile('^[+].* \t') +RE_SPACE_BEFORE_TAB = re.compile(r'^[+].* \t') # Match indented lines for changes RE_LEADING_WHITESPACE = re.compile(r'^\s') diff --git a/tools/qconfig.py b/tools/qconfig.py index 7b868c7d72c..8c2fc9efc5f 100755 --- a/tools/qconfig.py +++ b/tools/qconfig.py @@ -1595,7 +1595,7 @@ def imply(args): if flag == 'help' or bad: print("Imply flags: (separate with ',')") for name, info in IMPLY_FLAGS.items(): - print(f' {name:-15s}: {info[1]}') + print(f' {name.ljust(15)}: {info[1]}') return 1 imply_flags |= IMPLY_FLAGS[flag][0] |