diff options
189 files changed, 7307 insertions, 1021 deletions
@@ -35,6 +35,7 @@ Bhupesh Sharma <bhupesh.linux@gmail.com> <bhupesh.sharma@linaro.org> Bin Meng <bmeng.cn@gmail.com> <bin.meng@windriver.com> Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com> Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com> +Casey Connolly <casey.connolly@linaro.org> <caleb.connolly@linaro.org> Christian Kohn <chris.kohn@amd.com> <christian.kohn@xilinx.com> Christopher Obbard <christopher.obbard@linaro.org> <chris.obbard@collabora.com> Dirk Behme <dirk.behme@googlemail.com> @@ -454,6 +454,12 @@ config TOOLS_DEBUG it is possible to set breakpoints on particular lines, single-step debug through the source code, etc. +config SKIP_RELOCATE + bool "Skips relocation of U-Boot to end of RAM" + help + Skips relocation of U-Boot allowing for systems that have extremely + limited RAM to run U-Boot. + endif # EXPERT config PHYS_64BIT diff --git a/MAINTAINERS b/MAINTAINERS index a0b06e9ee24..9d5af7ebca4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -157,6 +157,7 @@ S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git F: drivers/ddr/altera/ F: arch/arm/mach-socfpga/ +F: configs/socfpga_agilex5_vab_defconfig F: drivers/sysreset/sysreset_socfpga* ARM AMLOGIC SOC SUPPORT diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d8c99d3ab19..df373d38a55 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1138,6 +1138,7 @@ config ARCH_SOCFPGA select DM_SERIAL select GPIO_EXTRA_HEADER select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select LMB_ARCH_MEM_MAP if TARGET_SOCFPGA_SOC64 select OF_CONTROL select SPL_DM_RESET if DM_RESET select SPL_DM_SERIAL @@ -1171,8 +1172,6 @@ config ARCH_SOCFPGA imply SPL_DM_SPI_FLASH imply SPL_LIBDISK_SUPPORT imply SPL_MMC - imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION - imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE imply SPL_SPI_FLASH_SUPPORT imply SPL_SPI imply L2X0_CACHE diff --git a/arch/arm/cpu/armv8/spin_table.c b/arch/arm/cpu/armv8/spin_table.c index 485294b88d0..5ba20efa33b 100644 --- a/arch/arm/cpu/armv8/spin_table.c +++ b/arch/arm/cpu/armv8/spin_table.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada <yamada.masahiro@socionext.com> */ +#include <errno.h> #include <linux/libfdt.h> #include <asm/spin_table.h> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 57d3dd98ffb..bcf3f4be36e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -303,6 +303,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zc1751-xm017-dc3.dtb \ zynqmp-zc1751-xm018-dc4.dtb \ zynqmp-zc1751-xm019-dc5.dtb +dtb-$(CONFIG_TARGET_ZYNQ_BR) += \ + zynq-brcp1_2r.dtb \ + zynq-brcp1_1r.dtb \ + zynq-brcp1_1r_switch.dtb \ + zynq-brsmarc2.dtb \ + zynq-brcp150.dtb \ + zynq-brcp170.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo zynqmp-p-a2197-00-revA-x-prc-02-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo diff --git a/arch/arm/dts/an7581-u-boot.dtsi b/arch/arm/dts/an7581-u-boot.dtsi index 0316b73f3a5..a9297ca6503 100644 --- a/arch/arm/dts/an7581-u-boot.dtsi +++ b/arch/arm/dts/an7581-u-boot.dtsi @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ +#include <dt-bindings/reset/airoha,en7581-reset.h> + / { reserved-memory { #address-cells = <2>; @@ -11,6 +13,94 @@ reg = <0x0 0x80000000 0x0 0x40000>; }; }; + + clk25m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "clkxtal"; + }; + + vmmc_3v3: regulator-vmmc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + soc { + chip_scu: syscon@1fa20000 { + compatible = "airoha,en7581-chip-scu", "syscon"; + reg = <0x0 0x1fa20000 0x0 0x388>; + }; + + eth: ethernet@1fb50000 { + compatible = "airoha,en7581-eth"; + reg = <0 0x1fb50000 0 0x2600>, + <0 0x1fb54000 0 0x2000>, + <0 0x1fb56000 0 0x2000>; + reg-names = "fe", "qdma0", "qdma1"; + + resets = <&scuclk EN7581_FE_RST>, + <&scuclk EN7581_FE_PDMA_RST>, + <&scuclk EN7581_FE_QDMA_RST>, + <&scuclk EN7581_DUAL_HSI0_MAC_RST>, + <&scuclk EN7581_DUAL_HSI1_MAC_RST>, + <&scuclk EN7581_HSI_MAC_RST>, + <&scuclk EN7581_XFP_MAC_RST>; + reset-names = "fe", "pdma", "qdma", + "hsi0-mac", "hsi1-mac", "hsi-mac", + "xfp-mac"; + }; + + switch: switch@1fb58000 { + compatible = "airoha,en7581-switch"; + reg = <0 0x1fb58000 0 0x8000>; + }; + + snfi: spi@1fa10000 { + compatible = "airoha,en7581-snand"; + reg = <0x0 0x1fa10000 0x0 0x140>, + <0x0 0x1fa11000 0x0 0x600>; + + clocks = <&scuclk EN7523_CLK_SPI>; + clock-names = "spi"; + + #address-cells = <1>; + #size-cells = <0>; + + spi_nand: nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <2>; + }; + }; + + mmc0: mmc@1fa0e000 { + compatible = "mediatek,mt7622-mmc"; + reg = <0x0 0x1fa0e000 0x0 0x1000>, + <0x0 0x1fa0c000 0x0 0x60>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scuclk EN7581_CLK_EMMC>, <&clk25m>; + clock-names = "source", "hclk"; + bus-width = <4>; + max-frequency = <52000000>; + vmmc-supply = <&vmmc_3v3>; + disable-wp; + cap-mmc-highspeed; + non-removable; + + assigned-clocks = <&scuclk EN7581_CLK_EMMC>; + assigned-clock-rates = <200000000>; + }; + }; +}; + +&scuclk { + compatible = "airoha,en7581-scu", "syscon"; }; &uart1 { diff --git a/arch/arm/dts/at91-sam9x60_curiosity.dts b/arch/arm/dts/at91-sam9x60_curiosity.dts index 7f00014f13c..1c7f0fa6a49 100644 --- a/arch/arm/dts/at91-sam9x60_curiosity.dts +++ b/arch/arm/dts/at91-sam9x60_curiosity.dts @@ -319,6 +319,10 @@ pinctrl-0 = <&pinctrl_sdhci1>; }; +&usb0 { + status = "okay"; +}; + &usb1 { num-ports = <3>; atmel,vbus-gpio = <0 diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index 60de9140226..7631dfaa07f 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -70,6 +70,19 @@ #size-cells = <1>; ranges; + usb0: gadget@500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sam9x60-udc"; + reg = <0x500000 0x100000>, + <0xf803c000 0x400>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE 8>; + clock-names = "pclk", "hclk"; + assigned-clocks = <&pmc PMC_TYPE_CORE 8>; + assigned-clock-rates = <480000000>; + status = "disabled"; + }; + usb1: usb@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 7b62fffb4ff..62191ff5d97 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -778,6 +778,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xf8048030 0x10>; clocks = <&h32ck>; + bootph-all; }; watchdog: watchdog@f8048040 { diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index 8d6503dd091..874e71b5ca4 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -208,7 +208,8 @@ intel,offset-settings = /* DMIUSMCTCR */ <0x00000300 0x00000001 0x00000003>, - <0x00000300 0x00000003 0x00000003>; + <0x00000300 0x00000003 0x00000003>, + <0x00000308 0x00000004 0x0000001F>; bootph-all; }; @@ -218,7 +219,8 @@ intel,offset-settings = /* DMIUSMCTCR */ <0x00000300 0x00000001 0x00000003>, - <0x00000300 0x00000003 0x00000003>; + <0x00000300 0x00000003 0x00000003>, + <0x00000308 0x00000004 0x0000001F>; bootph-all; }; }; @@ -673,6 +675,17 @@ bootph-all; }; +&gpio1 { + /* Configure GPIO 1 pin 3 as output pin with value 0 during GPIO probe */ + portb: gpio-controller@0{ + sdio_sel { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-low; + }; + }; +}; + &i2c0 { reset-names = "i2c"; }; diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi index d7ab58267eb..8d7dc0945ab 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -25,34 +25,44 @@ /* * Both Memory base address and size default info is retrieved from HW setting. * Reconfiguration / Overwrite these info can be done with examples below. - */ - /* + * + * When LPDDR ECC is enabled, the last 1/8 of the memory region must + * be reserved for the Inline ECC buffer. + * * Example for memory size with 2GB: * memory { * reg = <0x0 0x80000000 0x0 0x80000000>; * }; - */ - /* + * * Example for memory size with 8GB: * memory { * reg = <0x0 0x80000000 0x0 0x80000000>, * <0x8 0x80000000 0x1 0x80000000>; * }; - */ - /* + * * Example for memory size with 32GB: * memory { * reg = <0x0 0x80000000 0x0 0x80000000>, * <0x8 0x80000000 0x7 0x80000000>; * }; - */ - /* + * * Example for memory size with 512GB: * memory { * reg = <0x0 0x80000000 0x0 0x80000000>, * <0x8 0x80000000 0x7 0x80000000>, * <0x88 0x00000000 0x78 0x00000000>; * }; + * + * Example for memory size with 2GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x80000000 0x0 0x70000000>; + * }; + * + * Example for memory size with 8GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x1 0x40000000>; + * }; */ chosen { diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi index 15306db6002..93a8e0697d6 100644 --- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi @@ -106,8 +106,13 @@ arch = "arm64"; os = "linux"; compression = "none"; + #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + load = <0x86000000>; + entry = <0x86000000>; + #else load = <0x6000000>; entry = <0x6000000>; + #endif kernel_blob: blob-ext { filename = "Image"; }; diff --git a/arch/arm/dts/zynq-binman-brcp1.dtsi b/arch/arm/dts/zynq-binman-brcp1.dtsi new file mode 100644 index 00000000000..3cc8ee8b810 --- /dev/null +++ b/arch/arm/dts/zynq-binman-brcp1.dtsi @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 B&R Industrial Automation GmbH + */ + + #include <config.h> + +/ { + binman { + bootph-all; + filename = "flash.bin"; + pad-byte = <0xff>; + align-size = <16>; + align = <16>; + + blob@0 { + filename = "spl/boot.bin"; + offset = <0x0>; + }; + + fit { + description = "U-Boot BR Zynq boards"; + offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; + + images { + uboot { + description = "U-Boot BR Zynq"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = <CONFIG_TEXT_BASE>; + u-boot-nodtb { + }; + }; + + fdt-0 { + description = "DTB BR Zynq"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + u-boot-dtb { + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "BR Zynq"; + firmware = "uboot"; + fdt = "fdt-0"; + }; + }; + }; + + blob-ext@0 { + filename = "blobs/cfg.img"; + offset = <0xC0000>; + size = <0x10000>; + optional; + }; + + blob-ext@5 { + filename = "blobs/cfg_opt.img"; + offset = <0xD0000>; + size = <0x10000>; + optional; + }; + + blob-ext@1 { + bootph-all; + filename = "blobs/bitstream.bit"; + offset = <0x100000>; + size = <0x200000>; + optional; + }; + + blob-ext@4 { + bootph-all; + filename = "blobs/bitstream_update.bit"; + offset = <0x400000>; + size = <0x200000>; + optional; + }; + + blob-ext@2 { + filename = "blobs/bootar.itb"; + offset = <0x900000>; + size = <0x600000>; + optional; + }; + + blob-ext@3 { + filename = "blobs/dtb.bin"; + offset = <0xF00000>; + size = <0x100000>; + optional; + }; + }; +}; diff --git a/arch/arm/dts/zynq-brcp1.dtsi b/arch/arm/dts/zynq-brcp1.dtsi new file mode 100644 index 00000000000..ebaf42d9419 --- /dev/null +++ b/arch/arm/dts/zynq-brcp1.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/include/ "zynq-7000.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "BRCP1 CPU"; + compatible = "br,cp1", + "xlnx,zynq-7000"; + + aliases { + i2c0 = &i2c0; + serial0 = &uart0; + spi0 = &qspi; + mmc0 = &sdhci0; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + brd_rst: board_reset { + compatible = "br,board-reset"; + pin = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + se_green { + label = "S_E_GREEN"; + gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + se_red { + label = "S_E_RED"; + gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + rdy_f_yellow { + label = "RDY_F_YELLOW"; + gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + re_green { + label = "R_E_GREEN"; + gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + re_red { + label = "R_E_RED"; + gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + plk_se_green { + label = "PLK_S_E_GREEN"; + gpios = <&ledgpio 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + eth_se_green { + label = "ETH_S_E_GREEN"; + gpios = <&ledgpio 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + ledgpio: max7320@5d { /* board LED */ + status = "okay"; + compatible = "maxim,max7320"; + reg = <0x5d>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <8>; + }; + + pmic0: da9062@58 { + compatible = "dlg,da9062"; + reg = <0x58>; + }; +}; + +&sdhci0 { + status = "okay"; + max-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + spi-max-frequency = <100000000>; + + spi_flash: spiflash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1"; + spi-max-frequency = <100000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; + +&gpio0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-brcp150-u-boot.dtsi b/arch/arm/dts/zynq-brcp150-u-boot.dtsi new file mode 100644 index 00000000000..1bfd5f27a7e --- /dev/null +++ b/arch/arm/dts/zynq-brcp150-u-boot.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +#include "zynq-binman-brcp1.dtsi" + +&i2c0 { + bootph-all; +}; + +&uart0 { + bootph-all; +}; + +&qspi { + bootph-all; +}; + +&spi_flash { + bootph-all; +}; + +&gpio0 { + bootph-all; +}; + +&brd_rst { + bootph-all; +}; + +&rs232_en { + bootph-all; +}; diff --git a/arch/arm/dts/zynq-brcp150.dts b/arch/arm/dts/zynq-brcp150.dts new file mode 100644 index 00000000000..1b22d3793db --- /dev/null +++ b/arch/arm/dts/zynq-brcp150.dts @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +/include/ "zynq-7000.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "BRCP150 CPU"; + compatible = "br,cp150", + "xlnx,zynq-7000"; + + aliases { + i2c0 = &i2c0; + serial0 = &uart0; + spi0 = &qspi; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + brd_rst: board_reset { + compatible = "br,board-reset"; + pin = <&gpio0 27 GPIO_ACTIVE_HIGH>; + }; + + /* Put this pin active high to enable RS232 debug serial */ + rs232_en: rs232_enable { + compatible = "br,rs232-en"; + pin = <&gpio0 52 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + re_green { + label = "R_E_GREEN"; + gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + re_red { + label = "R_E_RED"; + gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + rdy_f_red { + label = "RDY_F_RED"; + gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + rdy_f_yellow { + label = "RDY_F_YELLOW"; + gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + se_green { + label = "S_E_GREEN"; + gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + se_red { + label = "S_E_RED"; + gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + plk_se_green { + label = "PLK_S_E_GREEN"; + gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + eth_se_green { + label = "ETH_S_E_GREEN"; + gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + user1_green { + label = "USER1_GREEN"; + gpios = <&ledgpio 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + user1_red { + label = "USER1_RED"; + gpios = <&ledgpio 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + user2_green { + label = "USER2_GREEN"; + gpios = <&ledgpio 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + user2_red { + label = "USER2_RED"; + gpios = <&ledgpio 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "mii"; + phy-handle = <ðernet_phy>; + + ethernet_phy: emio-phy@2 { + reg = <2>; + max-speed = <100>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + ledgpio: max7320@5d { /* board LED */ + status = "okay"; + compatible = "maxim,max7320"; + reg = <0x5d>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <16>; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + spi-max-frequency = <100000000>; + + spi_flash: spiflash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1"; + spi-max-frequency = <100000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; + +&gpio0 { + status = "okay"; +}; + +/* Since the gem0 clock is configured EMIO this dummy entry is needed */ +&clkc { + clocks = <&clkc 16>; + clock-names = "gem0_emio_clk"; +}; diff --git a/arch/arm/dts/zynq-brcp170-u-boot.dtsi b/arch/arm/dts/zynq-brcp170-u-boot.dtsi new file mode 100644 index 00000000000..ceea610ec17 --- /dev/null +++ b/arch/arm/dts/zynq-brcp170-u-boot.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +#include "zynq-binman-brcp1.dtsi" + +&i2c0 { + bootph-all; +}; + +&uart0 { + bootph-all; +}; + +&qspi { + bootph-all; +}; + +&spi_flash { + bootph-all; +}; + +&gpio0 { + bootph-all; +}; diff --git a/arch/arm/dts/zynq-brcp170.dts b/arch/arm/dts/zynq-brcp170.dts new file mode 100644 index 00000000000..eee19ce4c5f --- /dev/null +++ b/arch/arm/dts/zynq-brcp170.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +/include/ "zynq-7000.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "BRCP170 CPU"; + compatible = "br,cp170", + "xlnx,zynq-7000"; + + aliases { + i2c0 = &i2c0; + serial0 = &uart0; + spi0 = &qspi; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + re_green { + label = "R_E_GREEN"; + gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + re_red { + label = "R_E_RED"; + gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + rdy_f_red { + label = "RDY_F_RED"; + gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + rdy_f_yellow { + label = "RDY_F_YELLOW"; + gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + se_green { + label = "S_E_GREEN"; + gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + se_red { + label = "S_E_RED"; + gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + plk_se_green { + label = "PLK_S_E_GREEN"; + gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + eth_se_green { + label = "ETH_S_E_GREEN"; + gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + max-speed = <100>; + ti,rx-internal-delay = <7>; + ti,tx-internal-delay = <7>; + ti,fifo-depth = <0>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + ledgpio: max7320@58 { /* board LED */ + status = "okay"; + compatible = "maxim,max7320"; + reg = <0x58>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <8>; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + spi-max-frequency = <100000000>; + + spi_flash: spiflash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1"; + spi-max-frequency = <100000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; + +&gpio0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi new file mode 100644 index 00000000000..58c4558ddff --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +#include "zynq-binman-brcp1.dtsi" + +&i2c0 { + bootph-all; +}; + +&uart0 { + bootph-all; +}; + +&qspi { + bootph-all; +}; + +&spi_flash { + bootph-all; +}; + +&gpio0 { + bootph-all; +}; + +&brd_rst { + bootph-all; +}; diff --git a/arch/arm/dts/zynq-brcp1_1r.dts b/arch/arm/dts/zynq-brcp1_1r.dts new file mode 100644 index 00000000000..fd7ae5539c3 --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_1r.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +#include "zynq-brcp1.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <7>; + ti,tx-internal-delay = <7>; + ti,fifo-depth = <0>; + max-speed = <1000>; + }; +}; diff --git a/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi new file mode 120000 index 00000000000..5a31a05ea66 --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi @@ -0,0 +1 @@ +zynq-brcp1_1r-u-boot.dtsi
\ No newline at end of file diff --git a/arch/arm/dts/zynq-brcp1_1r_switch.dts b/arch/arm/dts/zynq-brcp1_1r_switch.dts new file mode 100644 index 00000000000..a68d530bfe2 --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_1r_switch.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +#include "zynq-brcp1.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "gmii"; + + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +/* Since the gem0 clock is configured EMIO this dummy entry is needed */ +&clkc { + clocks = <&clkc 16>; + clock-names = "gem0_emio_clk"; +}; diff --git a/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi new file mode 120000 index 00000000000..5a31a05ea66 --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi @@ -0,0 +1 @@ +zynq-brcp1_1r-u-boot.dtsi
\ No newline at end of file diff --git a/arch/arm/dts/zynq-brcp1_2r.dts b/arch/arm/dts/zynq-brcp1_2r.dts new file mode 100644 index 00000000000..353d8a1235c --- /dev/null +++ b/arch/arm/dts/zynq-brcp1_2r.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +#include "zynq-brcp1.dtsi" + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <7>; + ti,tx-internal-delay = <7>; + ti,fifo-depth = <0>; + max-speed = <1000>; + }; +}; diff --git a/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi b/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi new file mode 100644 index 00000000000..58c4558ddff --- /dev/null +++ b/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +#include "zynq-binman-brcp1.dtsi" + +&i2c0 { + bootph-all; +}; + +&uart0 { + bootph-all; +}; + +&qspi { + bootph-all; +}; + +&spi_flash { + bootph-all; +}; + +&gpio0 { + bootph-all; +}; + +&brd_rst { + bootph-all; +}; diff --git a/arch/arm/dts/zynq-brsmarc2.dts b/arch/arm/dts/zynq-brsmarc2.dts new file mode 100644 index 00000000000..32f873d1b4c --- /dev/null +++ b/arch/arm/dts/zynq-brsmarc2.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 B&R Industrial Automation GmbH + */ + +/dts-v1/; +/include/ "zynq-7000.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "BRSMARC2 CPU"; + compatible = "br,smarc2", + "xlnx,zynq-7000"; + + aliases { + i2c0 = &i2c0; + serial0 = &uart0; + spi0 = &qspi; + mmc0 = &sdhci0; + can0 = &can0; + can1 = &can1; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x10000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + brd_rst: board_reset { + compatible = "br,board-reset"; + pin = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + plk_se_green { + label = "PLK_S_E_GREEN"; + gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + plk_se_red { + label = "PLK_S_E_RED"; + gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + rdy_f_yellow { + label = "RDY_F_YELLOW"; + gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + re_green { + label = "R_E_GREEN"; + gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + re_red { + label = "R_E_RED"; + gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy0>; + + ethernet_phy0: ethernet-phy@1 { + ti,ledcr = <0x0480>; + ti,rgmii-rxclk-shift; + reg = <1>; + }; +}; + +&gem1 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy1>; + mac-address = [ 00 00 00 00 00 00 ]; + + ethernet_phy1: ethernet-phy@3{ + ti,ledcr = <0x0480>; + reg = <3>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + resetc: rststm@60 { /* reset controller */ + compatible = "bur,rststm"; + reg = <0x60>; + hit-gpios = <&gpio0 84 GPIO_ACTIVE_HIGH>; + cooling-min-state = <0>; + cooling-max-state = <1>; /* reset gets fired */ + #cooling-cells = <2>; /* min followed by max */ + }; + + ledgpio: max7320@5d { /* board LED */ + status = "okay"; + compatible = "maxim,max7320"; + reg = <0x5d>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <8>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; +}; + +&sdhci0 { + status = "okay"; + max-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + spi-max-frequency = <100000000>; + + spi_flash: spiflash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1"; + spi-max-frequency = <100000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; diff --git a/arch/arm/dts/zynq-topic-miami.dts b/arch/arm/dts/zynq-topic-miami.dts index 8307a2ef9dd..73eea372079 100644 --- a/arch/arm/dts/zynq-topic-miami.dts +++ b/arch/arm/dts/zynq-topic-miami.dts @@ -11,6 +11,10 @@ model = "Topic Miami Zynq Board"; compatible = "topic,miami", "xlnx,zynq-7000"; + config { + u-boot,spl-payload-offset = <0x20000>; + }; + aliases { serial0 = &uart0; spi0 = &qspi; @@ -35,6 +39,7 @@ status = "okay"; num-cs = <1>; flash@0 { + bootph-all; compatible = "st,m25p80", "n25q256a", "jedec,spi-nor"; m25p,fast-read; reg = <0x0>; @@ -44,24 +49,12 @@ #address-cells = <1>; #size-cells = <1>; partition@0 { - label = "qspi-u-boot-spl"; - reg = <0x00000 0x10000>; - }; - partition@10000 { - label = "qspi-u-boot-img"; - reg = <0x10000 0x60000>; + label = "qspi-boot-bin"; + reg = <0x00000 0x100000>; }; - partition@70000 { - label = "qspi-device-tree"; - reg = <0x70000 0x10000>; - }; - partition@80000 { - label = "qspi-linux"; - reg = <0x80000 0x400000>; - }; - partition@480000 { + partition@100000 { label = "qspi-rootfs"; - reg = <0x480000 0x1b80000>; + reg = <0x100000 0>; }; }; }; @@ -74,6 +67,14 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; + /* GPIO expander */ + gpioex: gpio@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-line-names = "USB_RESET", "VTT_SHDWN_N", "V_PRESENT", "DEBUG_PRESENT"; + gpio-controller; + #gpio-cells = <2>; + }; }; &clkc { diff --git a/arch/arm/dts/zynqmp-binman-som.dts b/arch/arm/dts/zynqmp-binman-som.dts index d5b63ef604b..a70123feead 100644 --- a/arch/arm/dts/zynqmp-binman-som.dts +++ b/arch/arm/dts/zynqmp-binman-som.dts @@ -2,13 +2,19 @@ /* * dts file for Xilinx ZynqMP SOMs (k24/k26) * - * (C) Copyright 2024, Advanced Micro Devices, Inc. + * (C) Copyright 2024-2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ #include <config.h> +#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) +#define U_BOOT_ITB_FILENAME CONFIG_SPL_FS_LOAD_PAYLOAD_NAME +#else +#define U_BOOT_ITB_FILENAME "u-boot.itb" +#endif + /dts-v1/; / { binman: binman { @@ -103,9 +109,9 @@ }; }; - /* u-boot.itb generation in a static way */ + /* Generation in a static way */ itb { - filename = "u-boot.itb"; + filename = U_BOOT_ITB_FILENAME; pad-byte = <0>; fit { @@ -227,7 +233,7 @@ }; blob-ext@2 { offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; - filename = "u-boot.itb"; + filename = U_BOOT_ITB_FILENAME; }; fdtmap { }; diff --git a/arch/arm/dts/zynqmp-binman.dts b/arch/arm/dts/zynqmp-binman.dts index 252c2ad552b..59c1388fb1d 100644 --- a/arch/arm/dts/zynqmp-binman.dts +++ b/arch/arm/dts/zynqmp-binman.dts @@ -2,22 +2,28 @@ /* * dts file for Xilinx ZynqMP platforms * - * (C) Copyright 2024, Advanced Micro Devices, Inc. + * (C) Copyright 2024-2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ #include <config.h> +#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) +#define U_BOOT_ITB_FILENAME CONFIG_SPL_FS_LOAD_PAYLOAD_NAME +#else +#define U_BOOT_ITB_FILENAME "u-boot.itb" +#endif + /dts-v1/; / { binman: binman { multiple-images; #ifdef CONFIG_SPL - /* u-boot.itb generation in a static way */ + /* Generation in a static way */ itb { - filename = "u-boot.itb"; + filename = U_BOOT_ITB_FILENAME; pad-byte = <0>; fit { @@ -196,7 +202,7 @@ }; blob-ext@2 { offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; - filename = "u-boot.itb"; + filename = U_BOOT_ITB_FILENAME; }; fdtmap { }; diff --git a/arch/arm/mach-k3/r5/am62ax/clk-data.c b/arch/arm/mach-k3/r5/am62ax/clk-data.c index 7f1b6d5b4e0..9d9a43c055b 100644 --- a/arch/arm/mach-k3/r5/am62ax/clk-data.c +++ b/arch/arm/mach-k3/r5/am62ax/clk-data.c @@ -64,7 +64,7 @@ static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { static const char * const clkout0_ctrl_out0_parents[] = { "hsdiv4_16fft_main_2_hsdivout1_clk", - "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk10", }; static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { @@ -200,6 +200,7 @@ static const struct clk_data clk_list[] = { CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), @@ -316,7 +317,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 20, "clkout0_ctrl_out0"), DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk10"), DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 25, "board_0_ddr0_ck0_out"), DEV_CLK(157, 40, "mshsi2c_main_0_porscl"), diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c b/arch/arm/mach-k3/r5/am62px/clk-data.c index 4b9892fe051..bc62d1d0d08 100644 --- a/arch/arm/mach-k3/r5/am62px/clk-data.c +++ b/arch/arm/mach-k3/r5/am62px/clk-data.c @@ -59,7 +59,7 @@ static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { static const char * const clkout0_ctrl_out0_parents[] = { "hsdiv4_16fft_main_2_hsdivout1_clk", - "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk10", }; static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { @@ -193,6 +193,7 @@ static const struct clk_data clk_list[] = { CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x68108c, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), @@ -281,7 +282,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 36, "clkout0_ctrl_out0"), DEV_CLK(157, 37, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(157, 38, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 38, "hsdiv4_16fft_main_2_hsdivout1_clk10"), DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 54, "mshsi2c_main_0_porscl"), DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index adb816982f8..b76510ab452 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -260,7 +260,7 @@ config DDR_LOG_LEVEL failure, RL, WL errors and other algorithm failure. At level 1, provides the D-Unit setup (SPD/Static configuration). At level 2, provides the windows margin as a results of DQS centeralization. - At level 3, rovides the windows margin of each DQ as a results of + At level 3, provides the windows margin of each DQ as a results of DQS centeralization. config DDR_IMMUTABLE_DEBUG_SETTINGS @@ -394,7 +394,6 @@ config MVEBU_SPL_BOOT_DEVICE_MMC imply SPL_LIBDISK_SUPPORT imply SPL_MMC select SUPPORT_EMMC_BOOT if SPL_MMC - select SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR if SPL_MMC select SPL_BOOTROM_SUPPORT config MVEBU_SPL_BOOT_DEVICE_SATA @@ -450,7 +449,7 @@ config MVEBU_EFUSE_VHV_GPIO string "VHV_Enable GPIO name for eFuse programming" depends on MVEBU_EFUSE && !ARMADA_3700 help - The eFuse programing (burning) phase requires supplying 1.8V to the + The eFuse programming (burning) phase requires supplying 1.8V to the device on the VHV power pin, while for normal operation the VHV power rail must be left unconnected. See Marvell AN-389: ARMADA VHV Power document (Doc. No. MV-S302545-00 Rev. C, August 2, 2016) for details. diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 22d48dfae1c..c43fdee4a48 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -68,6 +68,8 @@ obj-y += altera-sysmgr.o obj-y += ccu_ncore3.o obj-y += system_manager_soc64.o obj-y += timer_s10.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o endif ifdef CONFIG_TARGET_SOCFPGA_N5X diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 27072e53135..8506d510413 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -195,3 +195,16 @@ void board_prep_linux(struct bootm_headers *images) } } #endif + +#if CONFIG_IS_ENABLED(LMB_ARCH_MEM_MAP) +void lmb_arch_add_memory(void) +{ + int i; + struct bd_info *bd = gd->bd; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + if (bd->bi_dram[i].size) + lmb_add(bd->bi_dram[i].start, bd->bi_dram[i].size); + } +} +#endif diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 65721098b2b..5ac868a281b 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -51,6 +51,7 @@ #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 #endif +#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0xf8024000 #define SOCFPGA_SMMU_ADDRESS 0xfa000000 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index 45cc9912f94..2099c51b682 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -128,6 +128,7 @@ enum ALT_SDM_MBOX_RESP_CODE { #define MBOX_QSPI_CLOSE 51 #define MBOX_QSPI_DIRECT 59 #define MBOX_REBOOT_HPS 71 +#define MBOX_HPS_STAGE_NOTIFY 93 /* Mailbox registers */ #define MBOX_CIN 0 /* command valid offset */ @@ -385,6 +386,8 @@ enum MBOX_CFGSTAT_MINOR_ERR_CODE { #define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3) #define RCF_PIN_STATUS_NSTATUS BIT(31) +#define HPS_EXECUTION_STATE_FSBL 0 + int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, u32 *resp_buf); int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, @@ -401,6 +404,7 @@ int mbox_qspi_open(void); #endif int mbox_reset_cold(void); +int mbox_hps_stage_notify(u32 execution_stage); int mbox_get_fpga_config_status(u32 cmd); int mbox_get_fpga_config_status_psci(u32 cmd); #endif /* _MAILBOX_S10_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index 058fdd6e548..4b010be9ee8 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -10,9 +10,12 @@ void reset_deassert_peripherals_handoff(void); int cpu_has_been_warmreset(void); void print_reset_info(void); -void socfpga_bridges_reset(int enable); +void socfpga_bridges_reset(int enable, unsigned int mask); #define RSTMGR_SOC64_STATUS 0x00 +#define RSTMGR_SOC64_HDSKEN 0x10 +#define RSTMGR_SOC64_HDSKREQ 0x14 +#define RSTMGR_SOC64_HDSKACK 0x18 #define RSTMGR_SOC64_MPUMODRST 0x20 #define RSTMGR_SOC64_PER0MODRST 0x24 #define RSTMGR_SOC64_PER1MODRST 0x28 @@ -20,8 +23,17 @@ void socfpga_bridges_reset(int enable); #define RSTMGR_MPUMODRST_CORE0 0 #define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 -#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 -#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 + +#define RSTMGR_BRGMODRST_SOC2FPGA_MASK BIT(0) +#define RSTMGR_BRGMODRST_LWSOC2FPGA_MASK BIT(1) +#define RSTMGR_BRGMODRST_FPGA2SOC_MASK BIT(2) +#define RSTMGR_BRGMODRST_F2SDRAM0_MASK BIT(3) +#define RSTMGR_BRGMODRST_F2SDRAM1_MASK BIT(4) +#define RSTMGR_BRGMODRST_F2SDRAM2_MASK BIT(5) +#define RSTMGR_BRGMODRST_DDRSCH_MASK BIT(6) + +#define RSTMGR_HDSKEN_FPGAHSEN BIT(2) +#define RSTMGR_HDSKREQ_FPGAHSREQ BIT(2) /* SDM, Watchdogs and MPU warm reset mask */ #define RSTMGR_STAT_SDMWARMRST 0x2 diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index b69bd3e47ec..f9c34e85711 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -6,6 +6,7 @@ #include <asm/arch/clock_manager.h> #include <asm/arch/mailbox_s10.h> +#include <asm/arch/smc_api.h> #include <asm/arch/system_manager.h> #include <asm/global_data.h> #include <asm/io.h> @@ -474,6 +475,17 @@ int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, urgent, resp_buf_len, resp_buf); } +int mbox_hps_stage_notify(u32 execution_stage) +{ +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + return smc_send_mailbox(MBOX_HPS_STAGE_NOTIFY, 1, &execution_stage, + 0, 0, NULL); +#else + return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_HPS_STAGE_NOTIFY, + MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0, NULL); +#endif +} + int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg) { return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg); diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index e0b2b4237e1..4f080f4f0b3 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -61,7 +61,7 @@ void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - printf("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n", + printf("CPU: Altera FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n", IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) ? "A55/A76" : "A53"); return 0; @@ -107,5 +107,5 @@ void do_bridge_reset(int enable, unsigned int mask) return; } - socfpga_bridges_reset(enable); + socfpga_bridges_reset(enable, mask); } diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c index b8e40d9a788..1dc44ab4797 100644 --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -58,6 +58,20 @@ static struct mm_region socfpga_agilex5_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE, }, { + /* MEM 30GB */ + .virt = 0x880000000UL, + .phys = 0x880000000UL, + .size = 0x780000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + /* MEM 480GB */ + .virt = 0x8800000000UL, + .phys = 0x8800000000UL, + .size = 0x7800000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { /* List terminator */ }, }; diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index a634c11a028..abb62a9b49f 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -1,21 +1,34 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ +#include <errno.h> #include <hang.h> #include <asm/global_data.h> #include <asm/io.h> +#include <asm/secure.h> #include <asm/arch/reset_manager.h> #include <asm/arch/smc_api.h> #include <asm/arch/system_manager.h> +#include <asm/arch/timer.h> #include <dt-bindings/reset/altr,rst-mgr-s10.h> +#include <exports.h> #include <linux/iopoll.h> #include <linux/intel-smc.h> +#include <wait_bit.h> DECLARE_GLOBAL_DATA_PTR; +#define TIMEOUT_300MS 300 + +/* F2S manager registers */ +#define F2SDRAM_SIDEBAND_FLAGINSTATUS0 0x14 +#define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50 +#define F2SDRAM_SIDEBAND_FLAGOUTCLR0 0x54 + /* Assert or de-assert SoCFPGA reset manager reset. */ void socfpga_per_reset(u32 reset, int set) { @@ -56,66 +69,213 @@ void socfpga_per_reset_all(void) writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST); } -void socfpga_bridges_reset(int enable) +static void socfpga_f2s_bridges_reset(int enable, unsigned int mask) { -#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) - u64 arg = enable; + int ret; + u32 brg_mask; + u32 flagout_idlereq = 0; + u32 flagoutset_fdrain = 0; + u32 flagoutset_en = 0; + u32 flaginstatus_idleack = 0; + u32 flaginstatus_respempty = 0; + + if (CONFIG_IS_ENABLED(TARGET_SOCFPGA_STRATIX10)) { + /* Support fpga2soc and f2sdram */ + brg_mask = mask & (RSTMGR_BRGMODRST_FPGA2SOC_MASK | + RSTMGR_BRGMODRST_F2SDRAM0_MASK | + RSTMGR_BRGMODRST_F2SDRAM1_MASK | + RSTMGR_BRGMODRST_F2SDRAM2_MASK); - int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0); - if (ret) { - printf("SMC call failed with error %d in %s.\n", ret, __func__); + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM0_MASK) { + flagout_idlereq |= BIT(0); + flaginstatus_idleack |= BIT(1); + flagoutset_fdrain |= BIT(2); + flagoutset_en |= BIT(1); + flaginstatus_respempty |= BIT(3); + } + + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM1_MASK) { + flagout_idlereq |= BIT(3); + flaginstatus_idleack |= BIT(5); + flagoutset_fdrain |= BIT(5); + flagoutset_en |= BIT(4); + flaginstatus_respempty |= BIT(7); + } + + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM2_MASK) { + flagout_idlereq |= BIT(6); + flaginstatus_idleack |= BIT(9); + flagoutset_fdrain |= BIT(8); + flagoutset_en |= BIT(7); + flaginstatus_respempty |= BIT(11); + } + } else { + /* Support fpga2soc only */ + brg_mask = mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK; + if (brg_mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK) { + flagout_idlereq |= BIT(0); + flaginstatus_idleack |= BIT(1); + flagoutset_fdrain |= BIT(2); + flagoutset_en |= BIT(1); + flaginstatus_respempty |= BIT(3); + } + } + + /* mask is not set, return here */ + if (!brg_mask) return; + + if (enable) { + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, + brg_mask); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, + flagout_idlereq); + + /* Wait for mpfe noc idleack to 0 */ + wait_for_bit_le32((u32 *)(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGINSTATUS0), + flaginstatus_idleack, false, TIMEOUT_300MS, false); + + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, + flagoutset_fdrain); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_en); + + udelay(1); /* wait 1us */ + } else { + if (readl((socfpga_get_rstmgr_addr() + + RSTMGR_SOC64_BRGMODRST) & brg_mask)) { + /* Bridge cannot be reset twice */ + return; + } + + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKEN, + RSTMGR_HDSKEN_FPGAHSEN); + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ, + RSTMGR_HDSKREQ_FPGAHSREQ); + + /* Wait for FPGA ack the handshake request to 1 */ + wait_for_bit_le32((u32 *)(socfpga_get_rstmgr_addr() + + RSTMGR_SOC64_HDSKACK), RSTMGR_HDSKREQ_FPGAHSREQ, + true, TIMEOUT_300MS, false); + + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, flagoutset_en); + + udelay(1); + + /* Requests MPFE NoC to idle */ + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagout_idlereq); + + /* Force F2S bridge to drain */ + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_fdrain); + + /* Wait for respond queue empty status to 1 (resp idle) */ + ret = wait_for_bit_le32((u32 *)(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGINSTATUS0), + flaginstatus_respempty, true, + TIMEOUT_300MS, false); + + /* Confirm again */ + if (!ret) + ret = wait_for_bit_le32((u32 *) + (SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGINSTATUS0), + flaginstatus_respempty, true, + TIMEOUT_300MS, false); + + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, + brg_mask & ~RSTMGR_BRGMODRST_FPGA2SOC_MASK); + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ, + RSTMGR_HDSKREQ_FPGAHSREQ); + setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + + F2SDRAM_SIDEBAND_FLAGOUTCLR0, + flagout_idlereq); } -#else - u32 reg; +} + +static void socfpga_s2f_bridges_reset(int enable, unsigned int mask) +{ + unsigned int noc_mask = 0; + unsigned int brg_mask = 0; + + if (mask & RSTMGR_BRGMODRST_SOC2FPGA_MASK) { + noc_mask = SYSMGR_NOC_H2F_MSK; + brg_mask = RSTMGR_BRGMODRST_SOC2FPGA_MASK; + } + + if (mask & RSTMGR_BRGMODRST_LWSOC2FPGA_MASK) { + noc_mask |= SYSMGR_NOC_LWH2F_MSK; + brg_mask |= RSTMGR_BRGMODRST_LWSOC2FPGA_MASK; + } + + /* s2f mask is not set, return here */ + if (!brg_mask) + return; if (enable) { /* clear idle request to all bridges */ setbits_le32(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0); + SYSMGR_SOC64_NOC_IDLEREQ_CLR, noc_mask); - /* Release all bridges from reset state */ + /* Release SOC2FPGA bridges from reset state */ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - ~0); + brg_mask); - /* Poll until all idleack to 0 */ - read_poll_timeout(readl, reg, !reg, 1000, 300000, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEACK); + /* Wait for all NOC master ack to 0 */ + wait_for_bit_le32((u32 *)(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEACK), noc_mask, false, + TIMEOUT_300MS, false); } else { /* set idle request to all bridges */ - writel(~0, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEREQ_SET); + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEREQ_SET, noc_mask); /* Enable the NOC timeout */ writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); - /* Poll until all idleack to 1 */ - read_poll_timeout(readl, reg, - reg == (SYSMGR_NOC_H2F_MSK | - SYSMGR_NOC_LWH2F_MSK), - 1000, 300000, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEACK); - - /* Poll until all idlestatus to 1 */ - read_poll_timeout(readl, reg, - reg == (SYSMGR_NOC_H2F_MSK | - SYSMGR_NOC_LWH2F_MSK), - 1000, 300000, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLESTATUS); - - /* Reset all bridges (except NOR DDR scheduler & F2S) */ + /* Wait for all NOC master ack to 1 */ + wait_for_bit_le32((u32 *)(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEACK), noc_mask, true, + TIMEOUT_300MS, false); + + /* Wait for all NOC master idlestatus to 1 */ + wait_for_bit_le32((u32 *)(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLESTATUS), noc_mask, true, + TIMEOUT_300MS, false); + + /* Reset all SOC2FPGA bridges */ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - ~(RSTMGR_BRGMODRST_DDRSCH_MASK | - RSTMGR_BRGMODRST_FPGA2SOC_MASK)); + brg_mask); /* Disable NOC timeout */ writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); } -#endif +} + +void socfpga_bridges_reset(int enable, unsigned int mask) +{ + if (!IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) { + u64 arg[2]; + int ret; + + /* Set bit-1 to indicate has mask value in arg[1]. */ + arg[0] = (enable & BIT(0)) | BIT(1); + arg[1] = mask; + + ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, arg, + ARRAY_SIZE(arg), NULL, 0); + if (ret) + printf("Failed to %s the HPS bridges, check bridges availability. Status %d.\n", + enable ? "enable" : "disable", ret); + } else { + socfpga_s2f_bridges_reset(enable, mask); + socfpga_f2s_bridges_reset(enable, mask); + } } /* diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index 52617a39cca..91c27a5543d 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -50,6 +50,10 @@ void board_init_f(ulong dummy) timer_init(); + mbox_init(); + + mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL); + sysmgr_pinmux_init(); ret = uclass_get_device(UCLASS_CLK, 0, &dev); @@ -77,8 +81,6 @@ void board_init_f(ulong dummy) } #endif - mbox_init(); - #ifdef CONFIG_CADENCE_QSPI mbox_qspi_open(); #endif diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c index 3451611082d..a9aad5350d2 100644 --- a/arch/arm/mach-socfpga/spl_agilex5.c +++ b/arch/arm/mach-socfpga/spl_agilex5.c @@ -62,6 +62,10 @@ void board_init_f(ulong dummy) timer_init(); + mbox_init(); + + mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL); + ret = uclass_get_device(UCLASS_CLK, 0, &dev); if (ret) { debug("Clock init failed: %d\n", ret); @@ -100,8 +104,6 @@ void board_init_f(ulong dummy) } } - mbox_init(); - if (IS_ENABLED(CONFIG_CADENCE_QSPI)) mbox_qspi_open(); diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c index 5ff137e5c6f..81283ef7162 100644 --- a/arch/arm/mach-socfpga/spl_n5x.c +++ b/arch/arm/mach-socfpga/spl_n5x.c @@ -49,6 +49,10 @@ void board_init_f(ulong dummy) timer_init(); + mbox_init(); + + mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL); + sysmgr_pinmux_init(); preloader_console_init(); @@ -84,8 +88,6 @@ void board_init_f(ulong dummy) } #endif - mbox_init(); - #ifdef CONFIG_CADENCE_QSPI mbox_qspi_open(); #endif diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index 53852cb7443..fa83ff96adc 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -52,6 +52,10 @@ void board_init_f(ulong dummy) socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); timer_init(); + mbox_init(); + + mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL); + sysmgr_pinmux_init(); /* configuring the HPS clocks */ @@ -84,8 +88,6 @@ void board_init_f(ulong dummy) } #endif - mbox_init(); - #ifdef CONFIG_CADENCE_QSPI mbox_qspi_open(); #endif diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig index 54fb93aeb53..7def7b9139a 100644 --- a/arch/arm/mach-versal-net/Kconfig +++ b/arch/arm/mach-versal-net/Kconfig @@ -45,6 +45,5 @@ config ZYNQ_SDHCI_MAX_FREQ default 200000000 source "board/xilinx/Kconfig" -source "board/xilinx/versal-net/Kconfig" endif diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig index 629a14129d5..5ab901c81ca 100644 --- a/arch/arm/mach-versal/Kconfig +++ b/arch/arm/mach-versal/Kconfig @@ -46,6 +46,5 @@ config VERSAL_NO_DDR access to DDR memory where DDR is not present. source "board/xilinx/Kconfig" -source "board/xilinx/versal/Kconfig" endif diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h index 9d1c2f0dcfc..b5f80a8e3a9 100644 --- a/arch/arm/mach-versal/include/mach/hardware.h +++ b/arch/arm/mach-versal/include/mach/hardware.h @@ -87,6 +87,8 @@ struct crp_regs { #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 #define BOOT_MODE_ALT_SHIFT 12 +#define PMC_MULTI_BOOT_REG 0xF1110004 +#define PMC_MULTI_BOOT_MASK 0x1FFF #define FLASH_RESET_GPIO 0xc #define WPROT_CRP 0xF126001C diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index 757bd873fbe..a6dfa556966 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -5,11 +5,11 @@ #include <linux/build_bug.h> -enum { - TCM_LOCK, - TCM_SPLIT, +enum tcm_mode { + TCM_LOCK = 0, + TCM_SPLIT = 1, }; -void initialize_tcm(bool mode); -void tcm_init(u8 mode); +void initialize_tcm(enum tcm_mode mode); +void tcm_init(enum tcm_mode mode); void mem_map_fill(void); diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c index 921ca49c359..7423b8dc312 100644 --- a/arch/arm/mach-versal/mp.c +++ b/arch/arm/mach-versal/mp.c @@ -24,7 +24,7 @@ #define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK 0x10 #define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000 -static void set_r5_halt_mode(u8 halt, u8 mode) +static void set_r5_halt_mode(u8 halt, enum tcm_mode mode) { u32 tmp; @@ -45,7 +45,7 @@ static void set_r5_halt_mode(u8 halt, u8 mode) } } -static void set_r5_tcm_mode(u8 mode) +static void set_r5_tcm_mode(enum tcm_mode mode) { u32 tmp; @@ -63,7 +63,7 @@ static void set_r5_tcm_mode(u8 mode) writel(tmp, &rpu_base->rpu_glbl_ctrl); } -static void release_r5_reset(u8 mode) +static void release_r5_reset(enum tcm_mode mode) { u32 tmp; @@ -87,9 +87,9 @@ static void enable_clock_r5(void) writel(tmp, &crlapb_base->cpu_r5_ctrl); } -void initialize_tcm(bool mode) +void initialize_tcm(enum tcm_mode mode) { - if (!mode) { + if (mode == TCM_LOCK) { set_r5_tcm_mode(TCM_LOCK); set_r5_halt_mode(HALT, TCM_LOCK); enable_clock_r5(); @@ -102,7 +102,7 @@ void initialize_tcm(bool mode) } } -void tcm_init(u8 mode) +void tcm_init(enum tcm_mode mode) { puts("WARNING: Initializing TCM overwrites TCM content\n"); initialize_tcm(mode); diff --git a/arch/arm/mach-versal2/Kconfig b/arch/arm/mach-versal2/Kconfig index 3f18e3351aa..2a595151d6f 100644 --- a/arch/arm/mach-versal2/Kconfig +++ b/arch/arm/mach-versal2/Kconfig @@ -50,6 +50,5 @@ config ZYNQ_SDHCI_MAX_FREQ default 200000000 source "board/xilinx/Kconfig" -source "board/amd/versal2/Kconfig" endif diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h index 15085f941e0..7ca2bbb7550 100644 --- a/arch/arm/mach-versal2/include/mach/hardware.h +++ b/arch/arm/mach-versal2/include/mach/hardware.h @@ -68,6 +68,7 @@ struct crp_regs { #define USB_MODE 0x00000007 #define OSPI_MODE 0x00000008 #define SELECTMAP_MODE 0x0000000A +#define UFS_MODE 0x0000000B #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 @@ -96,3 +97,9 @@ enum versal2_platform { #define MIO_PIN_12 0xF1060030 #define BANK0_OUTPUT 0xF1020040 #define BANK0_TRI 0xF1060200 + +#define PMXC_EFUSE_CACHE_BASE_ADDRESS 0xF1250000 +#define PMXC_SLCR_BASE_ADDRESS 0xF1061000 +#define PMXC_UFS_CAL_1_OFFSET 0xBE8 +#define PMXC_SRAM_CSR 0x4C +#define PMXC_TX_RX_CFG_RDY 0x54 diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 376d1bc7131..c3f505fa15c 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -58,5 +58,6 @@ config ZYNQ_SDHCI_MAX_FREQ source "board/xilinx/Kconfig" source "board/xilinx/zynq/Kconfig" +source "board/BuR/zynq/Kconfig" endif diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 960ffac2105..b7a4142fd54 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -113,7 +113,7 @@ u64 get_page_table_size(void) } #if defined(CONFIG_DEFINE_TCM_OCM_MMAP) -void tcm_init(u8 mode) +void tcm_init(enum tcm_mode mode) { int ret; diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index 9af3ab5d6b6..b6a41df1da4 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -41,18 +41,18 @@ enum { ZYNQMP_SILICON_V4, }; -enum { - TCM_LOCK, - TCM_SPLIT, +enum tcm_mode { + TCM_LOCK = 0, + TCM_SPLIT = 1, }; unsigned int zynqmp_get_silicon_version(void); -int check_tcm_mode(bool mode); -void initialize_tcm(bool mode); +int check_tcm_mode(enum tcm_mode mode); +void initialize_tcm(enum tcm_mode mode); void mem_map_fill(void); #if defined(CONFIG_DEFINE_TCM_OCM_MMAP) -void tcm_init(u8 mode); +void tcm_init(enum tcm_mode mode); #endif #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 448bc532867..d2a7f305ccc 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -17,9 +17,6 @@ #include <linux/errno.h> #include <linux/string.h> -#define LOCK 0 -#define SPLIT 1 - #define HALT 0 #define RELEASE 1 @@ -65,11 +62,11 @@ int cpu_reset(u32 nr) return 0; } -static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode) +static void set_r5_halt_mode(u32 nr, u8 halt, enum tcm_mode mode) { u32 tmp; - if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) { + if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU0) { tmp = readl(&rpu_base->rpu0_cfg); if (halt == HALT) tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; @@ -78,7 +75,7 @@ static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode) writel(tmp, &rpu_base->rpu0_cfg); } - if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) { + if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU1) { tmp = readl(&rpu_base->rpu1_cfg); if (halt == HALT) tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; @@ -88,12 +85,12 @@ static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode) } } -static void set_r5_tcm_mode(u8 mode) +static void set_r5_tcm_mode(enum tcm_mode mode) { u32 tmp; tmp = readl(&rpu_base->rpu_glbl_ctrl); - if (mode == LOCK) { + if (mode == TCM_LOCK) { tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK | ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK; @@ -106,12 +103,12 @@ static void set_r5_tcm_mode(u8 mode) writel(tmp, &rpu_base->rpu_glbl_ctrl); } -static void set_r5_reset(u32 nr, u8 mode) +static void set_r5_reset(u32 nr, enum tcm_mode mode) { u32 tmp; tmp = readl(&crlapb_base->rst_lpd_top); - if (mode == LOCK) { + if (mode == TCM_LOCK) { tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK | ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK); @@ -130,16 +127,16 @@ static void set_r5_reset(u32 nr, u8 mode) writel(tmp, &crlapb_base->rst_lpd_top); } -static void release_r5_reset(u32 nr, u8 mode) +static void release_r5_reset(u32 nr, enum tcm_mode mode) { u32 tmp; tmp = readl(&crlapb_base->rst_lpd_top); - if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) + if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU0) tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK); - if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) + if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU1) tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK); @@ -165,9 +162,9 @@ static int check_r5_mode(void) tmp = readl(&rpu_base->rpu_glbl_ctrl); if (tmp & ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK) - return SPLIT; + return TCM_SPLIT; - return LOCK; + return TCM_LOCK; } int cpu_disable(u32 nr) @@ -249,27 +246,27 @@ static void write_tcm_boot_trampoline(u32 nr, u32 boot_addr) } } -void initialize_tcm(bool mode) +void initialize_tcm(enum tcm_mode mode) { - if (!mode) { - set_r5_tcm_mode(LOCK); - set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, LOCK); + if (mode == TCM_LOCK) { + set_r5_tcm_mode(TCM_LOCK); + set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, TCM_LOCK); enable_clock_r5(); - release_r5_reset(ZYNQMP_CORE_RPU0, LOCK); + release_r5_reset(ZYNQMP_CORE_RPU0, TCM_LOCK); } else { - set_r5_tcm_mode(SPLIT); - set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, SPLIT); - set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT); + set_r5_tcm_mode(TCM_SPLIT); + set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, TCM_SPLIT); + set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, TCM_SPLIT); enable_clock_r5(); - release_r5_reset(ZYNQMP_CORE_RPU0, SPLIT); - release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT); + release_r5_reset(ZYNQMP_CORE_RPU0, TCM_SPLIT); + release_r5_reset(ZYNQMP_CORE_RPU1, TCM_SPLIT); } } -int check_tcm_mode(bool mode) +int check_tcm_mode(enum tcm_mode mode) { u32 tmp, cpu_state; - bool mode_prev; + enum tcm_mode mode_prev; tmp = readl(&rpu_base->rpu_glbl_ctrl); mode_prev = FIELD_GET(ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK, tmp); @@ -279,7 +276,7 @@ int check_tcm_mode(bool mode) ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK, tmp); cpu_state = cpu_state ? false : true; - if ((mode_prev == SPLIT && mode == LOCK) && cpu_state) + if ((mode_prev == TCM_SPLIT && mode == TCM_LOCK) && cpu_state) return -EACCES; if (mode_prev == mode) @@ -288,11 +285,11 @@ int check_tcm_mode(bool mode) return 0; } -static void mark_r5_used(u32 nr, u8 mode) +static void mark_r5_used(u32 nr, enum tcm_mode mode) { u32 mask = 0; - if (mode == LOCK) { + if (mode == TCM_LOCK) { mask = ZYNQMP_RPU0_USE_MASK | ZYNQMP_RPU1_USE_MASK; } else { switch (nr) { @@ -358,30 +355,30 @@ int cpu_release(u32 nr, int argc, char *const argv[]) return 1; } printf("R5 lockstep mode\n"); - set_r5_reset(nr, LOCK); - set_r5_tcm_mode(LOCK); - set_r5_halt_mode(nr, HALT, LOCK); + set_r5_reset(nr, TCM_LOCK); + set_r5_tcm_mode(TCM_LOCK); + set_r5_halt_mode(nr, HALT, TCM_LOCK); set_r5_start(boot_addr); enable_clock_r5(); - release_r5_reset(nr, LOCK); + release_r5_reset(nr, TCM_LOCK); dcache_disable(); write_tcm_boot_trampoline(nr, boot_addr_uniq); dcache_enable(); - set_r5_halt_mode(nr, RELEASE, LOCK); - mark_r5_used(nr, LOCK); + set_r5_halt_mode(nr, RELEASE, TCM_LOCK); + mark_r5_used(nr, TCM_LOCK); } else if (!strcmp(argv[1], "split") || !strcmp(argv[1], "1")) { printf("R5 split mode\n"); - set_r5_reset(nr, SPLIT); - set_r5_tcm_mode(SPLIT); - set_r5_halt_mode(nr, HALT, SPLIT); + set_r5_reset(nr, TCM_SPLIT); + set_r5_tcm_mode(TCM_SPLIT); + set_r5_halt_mode(nr, HALT, TCM_SPLIT); set_r5_start(boot_addr); enable_clock_r5(); - release_r5_reset(nr, SPLIT); + release_r5_reset(nr, TCM_SPLIT); dcache_disable(); write_tcm_boot_trampoline(nr, boot_addr_uniq); dcache_enable(); - set_r5_halt_mode(nr, RELEASE, SPLIT); - mark_r5_used(nr, SPLIT); + set_r5_halt_mode(nr, RELEASE, TCM_SPLIT); + mark_r5_used(nr, TCM_SPLIT); } else { printf("Unsupported mode\n"); return 1; diff --git a/arch/arm/mach-zynqmp/zynqmp.c b/arch/arm/mach-zynqmp/zynqmp.c index 3aa218545bb..279006b4d13 100644 --- a/arch/arm/mach-zynqmp/zynqmp.c +++ b/arch/arm/mach-zynqmp/zynqmp.c @@ -146,7 +146,7 @@ static int do_zynqmp_aes(struct cmd_tbl *cmdtp, int flag, int argc, static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - u8 mode; + enum tcm_mode mode; if (argc != cmdtp->maxargs) return CMD_RET_USAGE; diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7ea439e857c..d7065a80e23 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -322,6 +322,7 @@ config MIPS_CACHE_DISABLE config MIPS_RELOCATION_TABLE_SIZE hex "Relocation table size" range 0x100 0x10000 + default "0xc000" if TARGET_MALTA default "0x8000" ---help--- A table of relocation data will be appended to the U-Boot binary diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index ce7d9e16961..a9e318c4a31 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -102,6 +102,10 @@ bootph-pre-ram; }; +&pllclk { + bootph-pre-ram; +}; + &syscrg { bootph-pre-ram; }; diff --git a/board/BuR/common/Kconfig b/board/BuR/common/Kconfig new file mode 100644 index 00000000000..490201e7407 --- /dev/null +++ b/board/BuR/common/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# B&R Industrial Automation GmbH - http://www.br-automation.com + +config BR_RESETC_I2CBUS + int "I2C Bus address of B&R reset controller" + depends on SYS_VENDOR = "BuR" && DM_I2C + default 0 diff --git a/board/BuR/common/br_resetc.c b/board/BuR/common/br_resetc.c index f5d09fef3d3..dfe2c2e0155 100644 --- a/board/BuR/common/br_resetc.c +++ b/board/BuR/common/br_resetc.c @@ -52,10 +52,16 @@ static int resetc_init(void) { struct udevice *i2cbus; int rc; +#if !defined(BR_RESETC_I2CBUS) + int busno = 0; +#else + int busno = CONFIG_BR_RESETC_I2CBUS; +#endif + + rc = uclass_get_device_by_seq(UCLASS_I2C, busno, &i2cbus); - rc = uclass_get_device_by_seq(UCLASS_I2C, 0, &i2cbus); if (rc) { - printf("Cannot find I2C bus #0!\n"); + printf("Cannot find I2C bus #%d!\n", busno); return -1; } @@ -108,9 +114,73 @@ int br_resetc_bmode(void) { int rc = 0; u16 regw; + unsigned int bmode = 0; + + if (!resetc.i2cdev) + rc = resetc_init(); + + if (rc != 0) + return rc; + + board_boot_led(1); + + rc = br_resetc_bmode_get(&bmode); + if (rc != 0) + return rc; + + LCD_SETCURSOR(1, 8); + + switch (bmode) { + case BMODE_PME: + LCD_PUTS("entering PME-Mode (netscript). "); + regw = 0x0C0C; + break; + case BMODE_DEFAULTAR: + LCD_PUTS("entering BOOT-mode. "); + regw = 0x0000; + break; + case BMODE_DIAG: + LCD_PUTS("entering DIAGNOSE-mode. "); + regw = 0x0F0F; + break; + case BMODE_SERVICE: + LCD_PUTS("entering SERVICE mode. "); + regw = 0xB4B4; + break; + case BMODE_RUN: + LCD_PUTS("loading OS... "); + regw = 0x0404; + break; + } + + board_boot_led(0); + + if (resetc.is_psoc) + rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0, + (u8 *)®w, 2); + else + rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0, + (u8 *)®w, 1); + + if (rc != 0) + printf("WARN: cannot write into resetcontroller!\n"); + + if (resetc.is_psoc) + printf("Reset: PSOC controller\n"); + else + printf("Reset: STM32 controller\n"); + + printf("Mode: %s\n", bootmodeascii[regw & 0x0F]); + env_set_ulong("b_mode", regw & 0x0F); + + return rc; +} + +int br_resetc_bmode_get(unsigned int *bmode) +{ + int rc = 0; u8 regb, scr; int cnt; - unsigned int bmode = 0; if (!resetc.i2cdev) rc = resetc_init(); @@ -130,13 +200,11 @@ int br_resetc_bmode(void) return -1; } - board_boot_led(1); - /* special bootmode from resetcontroller */ if (regb & 0x4) { - bmode = BMODE_DIAG; + *bmode = BMODE_DIAG; } else if (regb & 0x8) { - bmode = BMODE_DEFAULTAR; + *bmode = BMODE_DEFAULTAR; } else if (board_boot_key() != 0) { cnt = 4; do { @@ -163,68 +231,23 @@ int br_resetc_bmode(void) switch (cnt) { case 0: - bmode = BMODE_PME; + *bmode = BMODE_PME; break; case 1: - bmode = BMODE_DEFAULTAR; + *bmode = BMODE_DEFAULTAR; break; case 2: - bmode = BMODE_DIAG; + *bmode = BMODE_DIAG; break; case 3: - bmode = BMODE_SERVICE; + *bmode = BMODE_SERVICE; break; } } else if ((regb & 0x1) || scr == 0xCC) { - bmode = BMODE_PME; + *bmode = BMODE_PME; } else { - bmode = BMODE_RUN; - } - - LCD_SETCURSOR(1, 8); - - switch (bmode) { - case BMODE_PME: - LCD_PUTS("entering PME-Mode (netscript). "); - regw = 0x0C0C; - break; - case BMODE_DEFAULTAR: - LCD_PUTS("entering BOOT-mode. "); - regw = 0x0000; - break; - case BMODE_DIAG: - LCD_PUTS("entering DIAGNOSE-mode. "); - regw = 0x0F0F; - break; - case BMODE_SERVICE: - LCD_PUTS("entering SERVICE mode. "); - regw = 0xB4B4; - break; - case BMODE_RUN: - LCD_PUTS("loading OS... "); - regw = 0x0404; - break; + *bmode = BMODE_RUN; } - board_boot_led(0); - - if (resetc.is_psoc) - rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0, - (u8 *)®w, 2); - else - rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0, - (u8 *)®w, 1); - - if (rc != 0) - printf("WARN: cannot write into resetcontroller!\n"); - - if (resetc.is_psoc) - printf("Reset: PSOC controller\n"); - else - printf("Reset: STM32 controller\n"); - - printf("Mode: %s\n", bootmodeascii[regw & 0x0F]); - env_set_ulong("b_mode", regw & 0x0F); - return rc; } diff --git a/board/BuR/common/br_resetc.h b/board/BuR/common/br_resetc.h index 999045b867d..3bd5ac20ae1 100644 --- a/board/BuR/common/br_resetc.h +++ b/board/BuR/common/br_resetc.h @@ -11,6 +11,7 @@ int br_resetc_regget(u8 reg, u8 *dst); int br_resetc_regset(u8 reg, u8 val); int br_resetc_bmode(void); +int br_resetc_bmode_get(unsigned int *bmode); /* reset controller register defines */ #define RSTCTRL_CTRLREG 0x01 diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 7fb61736710..3513f43a9f5 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -68,7 +68,7 @@ int brdefaultip_setup(int bus, int chip) "if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.%d; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;", u8buf); else - strncpy(defip, + strlcpy(defip, "if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;", sizeof(defip)); diff --git a/board/BuR/zynq/Kconfig b/board/BuR/zynq/Kconfig new file mode 100644 index 00000000000..b450a21bd98 --- /dev/null +++ b/board/BuR/zynq/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# B&R Industrial Automation GmbH - http://www.br-automation.com +if ARCH_ZYNQ + +config TARGET_ZYNQ_BR + bool "Support BR Zynq builds" + depends on SYS_VENDOR = "BuR" + select BINMAN + select SPL_BINMAN_FDT + +endif + +source "board/BuR/common/Kconfig" diff --git a/board/BuR/zynq/MAINTAINERS b/board/BuR/zynq/MAINTAINERS new file mode 100644 index 00000000000..d655cae58d4 --- /dev/null +++ b/board/BuR/zynq/MAINTAINERS @@ -0,0 +1,11 @@ +ZYNQ BOARD +M: Wolfgang Wallner <wolfgang.wallner@br-automation.com> +S: Maintained +F: board/BuR/zynq/ +F: board/BuR/common/ +F: include/configs/brzynq.h +F: arch/arm/dts/zynq-br* +F: configs/brcp1_* +F: configs/brcp150_defconfig +F: configs/brcp170_defconfig +F: configs/brsmarc2_defconfig diff --git a/board/BuR/zynq/Makefile b/board/BuR/zynq/Makefile new file mode 100644 index 00000000000..fed40b0a069 --- /dev/null +++ b/board/BuR/zynq/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# B&R Industrial Automation GmbH - http://www.br-automation.com + +hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/zynq-//') + +obj-y := ../common/common.o +obj-y += ../common/br_resetc.o +obj-y += common/board.o +obj-y += $(hw-platform-y)/board.o + +obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o + +# Suppress "warning: function declaration isn't a prototype" +CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes diff --git a/board/BuR/zynq/brcp150/board.c b/board/BuR/zynq/brcp150/board.c new file mode 100644 index 00000000000..456d4900680 --- /dev/null +++ b/board/BuR/zynq/brcp150/board.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * B&R Industrial Automation GmbH - http://www.br-automation.com + */ diff --git a/board/BuR/zynq/brcp150/ps7_init_gpl.c b/board/BuR/zynq/brcp150/ps7_init_gpl.c new file mode 100644 index 00000000000..822bce358aa --- /dev/null +++ b/board/BuR/zynq/brcp150/ps7_init_gpl.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/arch/ps7_init_gpl.h> + +unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500141U), + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000801U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001001U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001003U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000802U), + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00A01403U), + EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000801U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400800U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FF844DU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000103FU), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00042E1AU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D154D4U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C000U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C5U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x000003E0U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x000003E1U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001220U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001220U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000013E1U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000003E0U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), +}; + +unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} diff --git a/board/BuR/zynq/brcp170/board.c b/board/BuR/zynq/brcp170/board.c new file mode 100644 index 00000000000..456d4900680 --- /dev/null +++ b/board/BuR/zynq/brcp170/board.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * B&R Industrial Automation GmbH - http://www.br-automation.com + */ diff --git a/board/BuR/zynq/brcp170/ps7_init_gpl.c b/board/BuR/zynq/brcp170/ps7_init_gpl.c new file mode 100644 index 00000000000..223d13cc389 --- /dev/null +++ b/board/BuR/zynq/brcp170/ps7_init_gpl.c @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/arch/ps7_init_gpl.h> + +unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U), + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501903U), + EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DF844DU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000103FU), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00042E1AU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D154D4U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C000U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C5U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001220U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001220U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000013E1U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000003E0U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), +}; + +unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} diff --git a/board/BuR/zynq/brcp1_1r/board.c b/board/BuR/zynq/brcp1_1r/board.c new file mode 100644 index 00000000000..456d4900680 --- /dev/null +++ b/board/BuR/zynq/brcp1_1r/board.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * B&R Industrial Automation GmbH - http://www.br-automation.com + */ diff --git a/board/BuR/zynq/brcp1_1r/ps7_init_gpl.c b/board/BuR/zynq/brcp1_1r/ps7_init_gpl.c new file mode 100644 index 00000000000..be39db9caaa --- /dev/null +++ b/board/BuR/zynq/brcp1_1r/ps7_init_gpl.c @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/arch/ps7_init_gpl.h> + +unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA240U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0003C000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000300U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x000FA240U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0003C000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00101001U), + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001401U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000A02U), + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00A01901U), + EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00500800U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD844DU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000084U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000666U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFFF0000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF5555U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000000U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000000U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000085U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000800U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000800U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000220U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000000U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), +}; + +unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} diff --git a/board/BuR/zynq/brcp1_1r_switch/board.c b/board/BuR/zynq/brcp1_1r_switch/board.c new file mode 100644 index 00000000000..456d4900680 --- /dev/null +++ b/board/BuR/zynq/brcp1_1r_switch/board.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * B&R Industrial Automation GmbH - http://www.br-automation.com + */ diff --git a/board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c b/board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c new file mode 100644 index 00000000000..e4fc708a45c --- /dev/null +++ b/board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/arch/ps7_init_gpl.h> + +unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500141U), + EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00500141U), + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U), + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501901U), + EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD84CDU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000084U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000666U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFFF0000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF5555U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000000U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000000U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000085U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000800U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000800U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000220U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000300U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000000U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + EMIT_EXIT(), +}; + +unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} diff --git a/board/BuR/zynq/brcp1_2r/board.c b/board/BuR/zynq/brcp1_2r/board.c new file mode 100644 index 00000000000..456d4900680 --- /dev/null +++ b/board/BuR/zynq/brcp1_2r/board.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * B&R Industrial Automation GmbH - http://www.br-automation.com + */ diff --git a/board/BuR/zynq/brcp1_2r/ps7_init_gpl.c b/board/BuR/zynq/brcp1_2r/ps7_init_gpl.c new file mode 100644 index 00000000000..4ebed8bf90f --- /dev/null +++ b/board/BuR/zynq/brcp1_2r/ps7_init_gpl.c @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/arch/ps7_init_gpl.h> + +unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA3C0U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0002E000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U), + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000502U), + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501901U), + EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00101400U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U), + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DD844DU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00000740U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000360U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000361U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x000012E1U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x000002E0U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), +}; + +unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} diff --git a/board/BuR/zynq/brsmarc2/board.c b/board/BuR/zynq/brsmarc2/board.c new file mode 100644 index 00000000000..7d9e13a5eec --- /dev/null +++ b/board/BuR/zynq/brsmarc2/board.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * B&R Industrial Automation GmbH - http://www.br-automation.com + */ +#include <linux/types.h> +#include <i2c.h> +#include <init.h> +#include "../../common/br_resetc.h" +#include "../../common/bur_common.h" + +int board_boot_key(void) +{ + unsigned char u8buf = 0; + int rc; + + rc = br_resetc_regget(RSTCTRL_ENHSTATUS, &u8buf); + if (rc == 0) + return (u8buf & 0x1); + + return 0; +} + +#if defined(CONFIG_SPL_BUILD) +int br_board_late_init(void) +{ + brdefaultip_setup(0, 0x57); + + return 0; +} +#endif diff --git a/board/BuR/zynq/brsmarc2/ps7_init_gpl.c b/board/BuR/zynq/brsmarc2/ps7_init_gpl.c new file mode 100644 index 00000000000..51ff8bfb70f --- /dev/null +++ b/board/BuR/zynq/brsmarc2/ps7_init_gpl.c @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/arch/ps7_init_gpl.h> + +unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500801U), + EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00500141U), + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000503U), + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501903U), + EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DFC4CDU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x00040EDAU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FFF6666U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x000016E1U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x000006E0U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000320U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000320U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000340U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000340U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), +}; + +unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} diff --git a/board/BuR/zynq/common/board.c b/board/BuR/zynq/common/board.c new file mode 100644 index 00000000000..35e8ed81181 --- /dev/null +++ b/board/BuR/zynq/common/board.c @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board functions for B&R brcp150, brcp170, brcp1, brsmarc2 Board + * + * B&R Industrial Automation GmbH - http://www.br-automation.com + * + */ + +#include <fdtdec.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <init.h> +#include <i2c.h> +#include <dm/uclass.h> +#include <command.h> +#include <binman.h> +#include "../../common/br_resetc.h" +#include "../../common/bur_common.h" + +#include <fdt_support.h> +#include <spi_flash.h> +#include <fpga.h> +#include <zynqpl.h> + +#define RSTCTRL_CTRLSPEC_nPCIRST 0x1 + +__weak int br_board_late_init(void) +{ + return 0; +} + +#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(FPGA) +const char *fpga_paths[2] = { "/binman/blob-ext@4", + "/binman/blob-ext@1"}; + +static int start_fpga(unsigned int bank) +{ + struct spi_flash *flash_dev; + ofnode fpga_node; + void *buf; + + u32 flash_offset, flash_size; + int rc; + + fpga_node = ofnode_path(fpga_paths[bank]); + + if (!ofnode_valid(fpga_node)) { + printf("WARN: binman node not found %s\n", fpga_paths[bank]); + return -ENOENT; + } + + flash_offset = ofnode_read_u32_default(fpga_node, "offset", ~0UL); + flash_size = ofnode_read_u32_default(fpga_node, "size", ~0UL); + + if (flash_offset == ~0UL || flash_size == ~0UL) { + printf("WARN: invalid fpga 'offset, size' in fdt (0x%x, 0x%x)", + flash_offset, flash_size); + return -EINVAL; + } + + printf("loading bitstream from bank #%d (0x%08x / 0x%08x)\n", bank, + flash_offset, flash_size); + + flash_dev = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE); + + if (rc) { + printf("WARN: cannot probe SPI-flash for bitstream!\n"); + return -ENODEV; + } + + buf = kmalloc(flash_size, 0); + if (!buf) { + spi_flash_free(flash_dev); + return -ENOMEM; + } + + debug("using buf @ %p, flashbase: 0x%08x, len: 0x%08x\n", + buf, flash_offset, flash_size); + + rc = spi_flash_read(flash_dev, flash_offset, flash_size, buf); + + spi_flash_free(flash_dev); + + if (rc) { + printf("WARN: cannot read bitstream from spi-flash!\n"); + kfree(buf); + + return -EIO; + } + + rc = fpga_loadbitstream(0, buf, flash_size, BIT_FULL); + if (rc) { + printf("WARN: FPGA configuration from bank #%d failed!\n", bank); + kfree(buf); + + return -EIO; + } + + kfree(buf); + + return 0; +} +#endif + +#if defined(CONFIG_SPL_BUILD) +const char *boot_gpios[] = { "br,rs232-en", + "br,board-reset", + NULL}; + +/* spl stage */ +int board_init(void) +{ + struct gpio_desc gpio; + int node; + int rc; + + /* peripheral RESET on PSOC reset-controller */ + rc = br_resetc_regset(RSTCTRL_SPECGPIO_O, RSTCTRL_CTRLSPEC_nPCIRST); + if (rc != 0) + printf("ERROR: cannot write to resetc (nPCIRST)!\n"); + + for (int i = 0; boot_gpios[i]; i++) { + node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, boot_gpios[i]); + + if (node < 0) { + printf("INFO: %s not found!\n", boot_gpios[i]); + } else { + rc = gpio_request_by_name_nodev(offset_to_ofnode(node), "pin", + 0, &gpio, GPIOD_IS_OUT); + + if (!rc) + dm_gpio_set_value(&gpio, 1); + else + printf("ERROR: failed to setup %s!\n", boot_gpios[i]); + } + } + +#if CONFIG_IS_ENABLED(FPGA) + unsigned int bmode; + unsigned int bank; + + rc = br_resetc_bmode_get(&bmode); + if (rc) { + printf("WARN: can't get Boot Mode!\n"); + return -ENODEV; + } + + /* use golden FPGA image in case of special boot flow (PME, BootAR, USB, Net ...) */ + bank = ((bmode == 0) || (bmode == 12)) ? 1 : 0; + + /* bring up FPGA */ + if (start_fpga(bank) != 0) { + printf("WARN: cannot start fpga from bank %d, trying bank %d!\n", bank, bank ^ 1); + bank ^= 1; + start_fpga(bank); + } +#endif + return 0; +} +#else +int board_init(void) +{ + return 0; +} + +/* + * PMIC buckboost regulator workaround: + * The DA9062 PMIC can switch its buckboost regulator output + * between PFM and PWM mode for eco-purpose. + * In very rare situations this transition leads into a non- + * functional buckboost regulator with zero output. + * With this workaround we prevent this with turning this + * feature off by forcing PWM-mode if auto-mode is selected. + */ +static void pmic_fixup(int addr) +{ + u8 regs[] = { 0x9E, 0x9D, 0xA0, 0x9F }; + struct udevice *i2cdev = NULL; + unsigned int i; + u8 val; + int rc; + + i2c_get_chip_for_busnum(0, addr, 1, &i2cdev); + if (!i2cdev) + return; + + printf("PMIC: fixup buckboost at i2c device 0x%x\n", addr); + + for (i = 0; i < sizeof(regs); i++) { + rc = dm_i2c_read(i2cdev, regs[i], &val, 1); + if (rc == 0 && val == 0xC0) { + val = 0x80; + dm_i2c_write(i2cdev, regs[i], &val, 1); + } + } +} + +int board_late_init(void) +{ + ofnode node; + u32 addr; + + br_resetc_bmode(); + br_board_late_init(); + + node = ofnode_by_compatible(ofnode_null(), "dlg,da9062"); + + if (!ofnode_valid(node)) + return 0; + + if (!ofnode_read_u32(node, "reg", &addr)) + pmic_fixup(addr); + else + printf("WARN: cannot read PMIC address!"); + + return 0; +} +#endif + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + return -EINVAL; + + zynq_ddrc_init(); + + return 0; +} diff --git a/board/BuR/zynq/env/brcp1.env b/board/BuR/zynq/env/brcp1.env new file mode 100644 index 00000000000..269e5193046 --- /dev/null +++ b/board/BuR/zynq/env/brcp1.env @@ -0,0 +1,109 @@ +autoload=0 +b_break=0 +fpgastatus=disabled +/* Memory variable */ +scradr=0xC0000 +fdtbackaddr=0x4000000 +loadaddr=CONFIG_SYS_LOAD_ADDR + +/* PREBOOT */ +preboot=run setupaddr_spi; run brdefaultip; run cfgscr; setenv bootstart 1 + +/* SPI layout variables */ +cfg_addr= + fdt get value cfgaddr_spi /binman/blob-ext@0 offset && + fdt get value cfgsize_spi /binman/blob-ext@0 size + +fpga_addr= + fdt get value fpgaaddr_spi /binman/blob-ext@1 offset && + fdt get value fpgasize_spi /binman/blob-ext@1 size + +os_addr= + fdt get value osaddr_spi /binman/blob-ext@2 offset && + fdt get value ossize_spi /binman/blob-ext@2 size + +dtb_addr= + fdt get value dtbaddr_spi /binman/blob-ext@3 offset && + fdt get value dtbsize_spi /binman/blob-ext@3 size + +setupaddr_spi= + fdt addr ${fdtcontroladdr}; + run dtb_addr; run os_addr; + run fpga_addr; run cfg_addr + +/* IP setup */ +brdefaultip= + if test -r ${ipaddr}; then; + else + setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254; + setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; + fi + +/* Boot orders */ +b_tgts_std=mmc0 mmc1 spi usb0 usb1 net +b_tgts_rcy=spi usb0 usb1 net +b_tgts_pme=net usb0 usb1 mmc spi + +/* Boot targets */ +b_mmc0= + run fpga; mmc dev 0; load mmc 0 ${loadaddr} arimg.itb && + run vxargs && bootm ${loadaddr} + +b_mmc1= + run fpga; mmc dev 0; load mmc 0 ${loadaddr} arimg && + run vxargs && + sf read ${fdtbackaddr} ${dtbaddr_spi} ${dtbsize_spi} && + fdt addr ${fdtbackaddr} && + bootm ${loadaddr} - ${fdtbackaddr} + +b_spi= + run fpga; sf read ${loadaddr} ${osaddr_spi} ${ossize_spi} && + run vxargs && bootm ${loadaddr} + +b_net=run fpga; tftp ${scradr} netscript.img && source ${scradr} +b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr} +b_usb1=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr} + +/* FPGA setup */ +fpga= + setenv fpgastatus disabled; + sf read ${loadaddr} ${fpgaaddr_spi} ${fpgasize_spi} && + fpga loadb 0 ${loadaddr} ${fpgasize_spi} && + setenv fpgastatus okay + +/* Configuration preboot*/ +cfgscr= + sf probe && + sf read ${scradr} ${cfgaddr_spi} ${cfgsize_spi} && + source ${scradr} + +/* OS Boot */ +fdt_fixup= + run cfgscr; run vxfdt + +vxargs= + setenv bootargs gem(0,0)host:vxWorks h=${serverip} + e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks f=0x1 + +vxfdt= + fdt set /fpga/pci status ${fpgastatus}; + fdt set /fpga status ${fpgastatus} + +/* Boot code */ +b_default= + run b_deftgts; + for target in ${b_tgts}; do + run b_${target}; + if test ${b_break} = 1; then; + exit; + fi; + done + +b_deftgts= + if test ${b_mode} = 12; then + setenv b_tgts ${b_tgts_pme}; + elif test ${b_mode} = 0; then + setenv b_tgts ${b_tgts_rcy}; + else + setenv b_tgts ${b_tgts_std}; + fi diff --git a/board/BuR/zynq/env/brcp150.env b/board/BuR/zynq/env/brcp150.env new file mode 100644 index 00000000000..9c27f0fa325 --- /dev/null +++ b/board/BuR/zynq/env/brcp150.env @@ -0,0 +1,119 @@ +autoload=0 +b_break=0 +fpgastatus=disabled +/* Memory variable */ +scradr=0xC0000 +fdtbackaddr=0x4000000 +loadaddr=CONFIG_SYS_LOAD_ADDR + +/* PREBOOT */ +preboot=run setupaddr_spi; run brdefaultip; run cfgscr; setenv bootstart 1 + +/* SPI layout variables */ +cfg_addr= + fdt get value cfgaddr_spi /binman/blob-ext@0 offset && + fdt get value cfgsize_spi /binman/blob-ext@0 size + +fpga_addr= + fdt get value fpgaaddr_spi /binman/blob-ext@1 offset && + fdt get value fpgasize_spi /binman/blob-ext@1 size + +os_addr= + fdt get value osaddr_spi /binman/blob-ext@2 offset && + fdt get value ossize_spi /binman/blob-ext@2 size + +dtb_addr= + fdt get value dtbaddr_spi /binman/blob-ext@3 offset && + fdt get value dtbsize_spi /binman/blob-ext@3 size + +opt_addr= + fdt get value optaddr_spi /binman/blob-ext@5 offset && + fdt get value optsize_spi /binman/blob-ext@5 size + +setupaddr_spi= + fdt addr ${fdtcontroladdr}; + run dtb_addr; run os_addr; + run fpga_addr; run cfg_addr; + run opt_addr + +/* IP setup */ +brdefaultip= + if test -r ${ipaddr}; then; + else + setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254; + setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; + fi + +/* Boot orders */ +b_tgts_std=mmc0 mmc1 fpga spi usb0 usb1 net +b_tgts_rcy=spi usb0 usb1 net +b_tgts_pme=net usb0 usb1 mmc spi + +/* Boot targets */ +b_mmc0= + mmc dev 0; load mmc 0 ${loadaddr} arimg.itb && + run vxargs && bootm ${loadaddr} + +b_mmc1= + mmc dev 0; load mmc 0 ${loadaddr} arimg && + run vxargs && + sf read ${fdtbackaddr} ${dtbaddr_spi} ${dtbsize_spi} && + fdt addr ${fdtbackaddr} && + bootm ${loadaddr} - ${fdtbackaddr} + +b_spi= + sf read ${loadaddr} ${osaddr_spi} ${ossize_spi} && + run vxargs && bootm ${loadaddr} + +b_net=tftp ${scradr} netscript.img && source ${scradr} +b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr} +b_usb1=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr} + +/* FPGA setup */ +b_fpga= + setenv fpgastatus disabled; + sf read ${loadaddr} ${fpgaaddr_spi} ${fpgasize_spi} && + fpga loadb 0 ${loadaddr} ${fpgasize_spi} && + setenv fpgastatus okay + +/* Configuration preboot*/ +cfgscr= + sf probe && + sf read ${scradr} ${cfgaddr_spi} ${cfgsize_spi} && + source ${scradr} + +cfgoptsct= + sf probe && + sf read ${scradr} ${optaddr_spi} ${optsize_spi} && + source ${scradr} + +/* OS Boot */ +fdt_fixup= + run cfgscr; run cfgoptsct; run vxfdt + +vxargs= + setenv bootargs gem(0,0)host:vxWorks h=${serverip} + e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks f=0x1 + +vxfdt= + fdt set /fpga/pci status ${fpgastatus}; + fdt set /fpga status ${fpgastatus} + +/* Boot code */ +b_default= + run b_deftgts; + for target in ${b_tgts}; do + run b_${target}; + if test ${b_break} = 1; then; + exit; + fi; + done + +b_deftgts= + if test ${b_mode} = 12; then + setenv b_tgts ${b_tgts_pme}; + elif test ${b_mode} = 0; then + setenv b_tgts ${b_tgts_rcy}; + else + setenv b_tgts ${b_tgts_std}; + fi diff --git a/board/amd/versal2/Kconfig b/board/amd/versal2/Kconfig deleted file mode 100644 index ab46af6935e..00000000000 --- a/board/amd/versal2/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (C) 2020 - 2022, Xilinx, Inc. -# Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. -# -if ARCH_VERSAL2 - -config CMD_VERSAL2 - bool "Enable Versal Gen 2 specific commands" - default y - depends on ZYNQMP_FIRMWARE - help - Select this to enable AMD Versal Gen 2 specific commands. - Commands like versal2 loadpdi are enabled by this. - -endif diff --git a/board/amd/versal2/Makefile b/board/amd/versal2/Makefile index 3a044517f0c..1673be4a6df 100644 --- a/board/amd/versal2/Makefile +++ b/board/amd/versal2/Makefile @@ -8,4 +8,3 @@ obj-y := board.o -obj-$(CONFIG_CMD_VERSAL2) += cmds.o diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index 5651d516a9e..72967e69a84 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2021 - 2022, Xilinx, Inc. - * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -20,6 +20,7 @@ #include <asm/arch/sys_proto.h> #include <dm/device.h> #include <dm/uclass.h> +#include <versalpl.h> #include "../../xilinx/common/board.h" #include <linux/bitfield.h> @@ -28,10 +29,25 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_FPGA_VERSALPL) +static xilinx_desc versalpl = { + xilinx_versal2, csu_dma, 1, &versal_op, 0, &versal_op, NULL, + FPGA_LEGACY +}; +#endif + int board_init(void) { printf("EL Level:\tEL%d\n", current_el()); +#if defined(CONFIG_FPGA_VERSALPL) + fpga_init(); + fpga_add(fpga_xilinx, &versalpl); +#endif + + if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM)) + xilinx_read_eeprom(); + return 0; } @@ -149,7 +165,7 @@ int board_early_init_r(void) return 0; } -static u8 versal_net_get_bootmode(void) +static u8 versal2_get_bootmode(void) { u8 bootmode; u32 reg = 0; @@ -175,7 +191,7 @@ static int boot_targets_setup(void) char *new_targets; char *env_targets; - bootmode = versal_net_get_bootmode(); + bootmode = versal2_get_bootmode(); puts("Bootmode: "); switch (bootmode) { @@ -252,6 +268,16 @@ static int boot_targets_setup(void) mode = "mmc"; bootseq = dev_seq(dev); break; + case UFS_MODE: + puts("UFS_MODE\n"); + if (uclass_get_device(UCLASS_UFS, 0, &dev)) { + debug("UFS driver for UFS device is not present\n"); + break; + } + debug("ufs device found at %p\n", dev); + + mode = "ufs"; + break; default: printf("Invalid Boot Mode:0x%x\n", bootmode); break; @@ -284,6 +310,7 @@ static int boot_targets_setup(void) env_targets ? env_targets : ""); env_set("boot_targets", new_targets); + free(new_targets); } return 0; @@ -341,3 +368,35 @@ int dram_init(void) void reset_cpu(void) { } + +#if defined(CONFIG_ENV_IS_NOWHERE) +enum env_location env_get_location(enum env_operation op, int prio) +{ + u32 bootmode = versal2_get_bootmode(); + + if (prio) + return ENVL_UNKNOWN; + + switch (bootmode) { + case EMMC_MODE: + case SD_MODE: + case SD1_LSHFT_MODE: + case SD_MODE1: + if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT)) + return ENVL_FAT; + if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4)) + return ENVL_EXT4; + return ENVL_NOWHERE; + case OSPI_MODE: + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + return ENVL_NOWHERE; + case JTAG_MODE: + case SELECTMAP_MODE: + default: + return ENVL_NOWHERE; + } +} +#endif diff --git a/board/amd/versal2/cmds.c b/board/amd/versal2/cmds.c deleted file mode 100644 index 56ae39bc6a1..00000000000 --- a/board/amd/versal2/cmds.c +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2024, Advanced Micro Devices, Inc. - * - * Michal Simek <michal.simek@amd.com> - */ - -#include <cpu_func.h> -#include <command.h> -#include <log.h> -#include <memalign.h> -#include <versalpl.h> -#include <vsprintf.h> -#include <zynqmp_firmware.h> - -/** - * do_versal2_load_pdi - Handle the "versal2 load pdi" command-line command - * @cmdtp: Command data struct pointer - * @flag: Command flag - * @argc: Command-line argument count - * @argv: Array of command-line arguments - * - * Processes the versal2 load pdi command - * - * Return: return 0 on success, Error value if command fails. - * CMD_RET_USAGE incase of incorrect/missing parameters. - */ -static int do_versal2_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc, - char * const argv[]) -{ - u32 buf_lo, buf_hi; - u32 ret_payload[PAYLOAD_ARG_CNT]; - ulong addr, *pdi_buf; - size_t len; - int ret; - - if (argc != cmdtp->maxargs) { - debug("pdi_load: incorrect parameters passed\n"); - return CMD_RET_USAGE; - } - - addr = simple_strtol(argv[1], NULL, 16); - if (!addr) { - debug("pdi_load: zero pdi_data address\n"); - return CMD_RET_USAGE; - } - - len = hextoul(argv[2], NULL); - if (!len) { - debug("pdi_load: zero size\n"); - return CMD_RET_USAGE; - } - - pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN); - if ((ulong)addr != (ulong)pdi_buf) { - memcpy((void *)pdi_buf, (void *)addr, len); - debug("Pdi addr:0x%lx aligned to 0x%lx\n", - addr, (ulong)pdi_buf); - } - - flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len); - - buf_lo = lower_32_bits((ulong)pdi_buf); - buf_hi = upper_32_bits((ulong)pdi_buf); - - ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, - buf_hi, 0, ret_payload); - if (ret) - printf("PDI load failed with err: 0x%08x\n", ret); - - return cmd_process_error(cmdtp, ret); -} - -U_BOOT_LONGHELP(versal2, - "loadpdi addr len - Load pdi image\n" - "load pdi image at ddr address 'addr' with pdi image size 'len'\n"); - -U_BOOT_CMD_WITH_SUBCMDS(versal2, "Versal Gen 2 sub-system", versal2_help_text, - U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1, - do_versal2_load_pdi)); diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c index 4c8407bb676..7714076edf1 100644 --- a/board/kobol/helios4/helios4.c +++ b/board/kobol/helios4/helios4.c @@ -73,7 +73,11 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ NOT_COMBINED, /* ddr twin-die combined */ { {0} }, /* raw spd data */ - {0} /* timing parameters */ + {0}, /* timing parameters */ + { {0} }, /* electrical configuration */ + {0,}, /* electrical parameters */ + 0x30000, /* ODT configuration */ + 0x3, /* clock enable mask */ }; struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index 1f2213902ed..4d7c9b9f80f 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -295,17 +295,16 @@ static int phytec_get_product_name(struct phytec_eeprom_data *data, switch (api2->som_type) { case 0: + case 1: + case 2: + case 3: som_type = api2->som_type; break; case 4: - som_type = 0; - break; case 5: som_type = 0; break; case 6: - som_type = 1; - break; case 7: som_type = 1; break; diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 6ecd3eb120f..1b0b664fa2b 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -359,9 +359,6 @@ static void set_fdtfile(void) */ static void set_fdt_addr(void) { - if (env_get("fdt_addr")) - return; - if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC) return; @@ -602,6 +599,9 @@ void update_fdt_from_fw(void *fdt, void *fw_fdt) /* Bluetooth device address as provided by the firmware */ copy_property(fdt, fw_fdt, "/soc/serial@7e201000/bluetooth", "local-bd-address"); + + /* copy uart clk as provided by the firmware */ + copy_property(fdt, fw_fdt, "/clocks/clk-uart", "clock-frequency"); } int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/board/raspberrypi/rpi/rpi.env b/board/raspberrypi/rpi/rpi.env index 30228285edd..9ac9d6768ca 100644 --- a/board/raspberrypi/rpi/rpi.env +++ b/board/raspberrypi/rpi/rpi.env @@ -48,30 +48,33 @@ dfu_alt_info+=zImage fat 0 1 * * scriptaddr and pxefile_addr_r can be pretty much anywhere that doesn't * conflict with something else. Reserving 1M for each of them at - * 0x02400000-0x02500000 and 0x02500000-0x02600000 should be plenty. + * 0x05400000-0x05500000 and 0x05500000-0x05600000 should be plenty. * * On ARM, both the DTB and any possible initrd must be loaded such that they * fit inside the lowmem mapping in Linux. In practice, this usually means not * more than ~700M away from the start of the kernel image but this number can * be larger OR smaller depending on e.g. the 'vmalloc=xxxM' command line * parameter given to the kernel. So reserving memory from low to high - * satisfies this constraint again. Reserving 1M at 0x02600000-0x02700000 for - * the DTB leaves rest of the free RAM to the initrd starting at 0x02700000. - * Even with the smallest possible CPU-GPU memory split of the CPU getting - * only 64M, the remaining 25M starting at 0x02700000 should allow quite - * large initrds before they start colliding with U-Boot. + * satisfies this constraint again. Reserving 1M at 0x05600000-0x05700000 for + * the DTB leaves rest of the free RAM to the initrd starting at 0x05700000. + * This means that the board must have at least 128MB of RAM available to + * U-Boot, more if the initrd is large. + * + * For compressed kernels, the maximum size is just under 32MB, with an area for + * decompression at 0x02000000 with space for 52MB, which is plenty for current + * kernels. + * + * limit bootm_size to 512MB so that all boot images stay within the bottom + * 512MB of memory */ -#ifdef CONFIG_ARM64 -fdt_high=ffffffffffffffff -initrd_high=ffffffffffffffff -#else -fdt_high=ffffffff -initrd_high=ffffffff -#endif +bootm_size=0x20000000 + kernel_addr_r=0x00080000 -scriptaddr=0x02400000 -pxefile_addr_r=0x02500000 -fdt_addr_r=0x02600000 -ramdisk_addr_r=0x02700000 +kernel_comp_addr_r=0x02000000 +kernel_comp_size=0x03400000 +scriptaddr=0x05400000 +pxefile_addr_r=0x05500000 +fdt_addr_r=0x05600000 +ramdisk_addr_r=0x05700000 boot_targets=mmc usb pxe dhcp diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index deea6c71103..8ffe7429901 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -80,7 +80,7 @@ struct xilinx_board_description { }; static int highest_id = -1; -static struct xilinx_board_description *board_info; +static struct xilinx_board_description *board_info __section(".data"); #define XILINX_I2C_DETECTION_BITS sizeof(struct fru_common_hdr) @@ -468,6 +468,9 @@ int board_late_init_xilinx(void) ret |= env_set_addr("bootm_size", (void *)bootm_size); for (id = 0; id <= highest_id; id++) { + if (!board_info) + break; + desc = &board_info[id]; if (desc && desc->header == EEPROM_HEADER_MAGIC) { if (desc->manufacturer[0]) diff --git a/board/xilinx/versal-net/Kconfig b/board/xilinx/versal-net/Kconfig deleted file mode 100644 index 2484429d3cb..00000000000 --- a/board/xilinx/versal-net/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (C) 2020 - 2022, Xilinx, Inc. -# Copyright (C) 2022, Advanced Micro Devices, Inc. -# - -if ARCH_VERSAL_NET - -config CMD_VERSAL_NET - bool "Enable Versal NET specific commands" - default y - depends on ZYNQMP_FIRMWARE - help - Select this to enable Versal NET specific commands. - Commands like versalnet loadpdi are enabled by this. - -endif diff --git a/board/xilinx/versal-net/Makefile b/board/xilinx/versal-net/Makefile index f9ff07c11c6..2008d4e231c 100644 --- a/board/xilinx/versal-net/Makefile +++ b/board/xilinx/versal-net/Makefile @@ -7,4 +7,3 @@ # obj-y := board.o -obj-$(CONFIG_CMD_VERSAL_NET) += cmds.o diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index 4d5913cff1d..65b2a451ad7 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -21,6 +21,8 @@ #include <asm/arch/sys_proto.h> #include <dm/device.h> #include <dm/uclass.h> +#include <zynqmp_firmware.h> +#include <versalpl.h> #include "../common/board.h" #include <linux/bitfield.h> @@ -29,10 +31,21 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_FPGA_VERSALPL) +static xilinx_desc versalpl = { + xilinx_versal_net, csu_dma, 1, &versal_op, 0, &versal_op, NULL, + FPGA_LEGACY +}; +#endif + int board_init(void) { printf("EL Level:\tEL%d\n", current_el()); +#if defined(CONFIG_FPGA_VERSALPL) + fpga_init(); + fpga_add(fpga_xilinx, &versalpl); +#endif return 0; } @@ -184,7 +197,11 @@ static u8 versal_net_get_bootmode(void) u8 bootmode; u32 reg = 0; - reg = readl(&crp_base->boot_mode_usr); + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) { + reg = zynqmp_pm_get_bootmode_reg(); + } else { + reg = readl(&crp_base->boot_mode_usr); + } if (reg >> BOOT_MODE_ALT_SHIFT) reg >>= BOOT_MODE_ALT_SHIFT; diff --git a/board/xilinx/versal-net/cmds.c b/board/xilinx/versal-net/cmds.c deleted file mode 100644 index e8b669f0fd4..00000000000 --- a/board/xilinx/versal-net/cmds.c +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023, Advanced Micro Devices, Inc. - * - * Michal Simek <michal.simek@amd.com> - */ - -#include <cpu_func.h> -#include <command.h> -#include <log.h> -#include <memalign.h> -#include <versalpl.h> -#include <vsprintf.h> -#include <zynqmp_firmware.h> - -/** - * do_versalnet_load_pdi - Handle the "versalnet load pdi" command-line command - * @cmdtp: Command data struct pointer - * @flag: Command flag - * @argc: Command-line argument count - * @argv: Array of command-line arguments - * - * Processes the Versal NET load pdi command - * - * Return: return 0 on success, Error value if command fails. - * CMD_RET_USAGE incase of incorrect/missing parameters. - */ -static int do_versalnet_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc, - char * const argv[]) -{ - u32 buf_lo, buf_hi; - u32 ret_payload[PAYLOAD_ARG_CNT]; - ulong addr, *pdi_buf; - size_t len; - int ret; - - if (argc != cmdtp->maxargs) { - debug("pdi_load: incorrect parameters passed\n"); - return CMD_RET_USAGE; - } - - addr = simple_strtol(argv[1], NULL, 16); - if (!addr) { - debug("pdi_load: zero pdi_data address\n"); - return CMD_RET_USAGE; - } - - len = hextoul(argv[2], NULL); - if (!len) { - debug("pdi_load: zero size\n"); - return CMD_RET_USAGE; - } - - pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN); - if ((ulong)addr != (ulong)pdi_buf) { - memcpy((void *)pdi_buf, (void *)addr, len); - debug("Pdi addr:0x%lx aligned to 0x%lx\n", - addr, (ulong)pdi_buf); - } - - flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len); - - buf_lo = lower_32_bits((ulong)pdi_buf); - buf_hi = upper_32_bits((ulong)pdi_buf); - - ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, - buf_hi, 0, ret_payload); - if (ret) - printf("PDI load failed with err: 0x%08x\n", ret); - - return cmd_process_error(cmdtp, ret); -} - -U_BOOT_LONGHELP(versalnet, - "loadpdi addr len - Load pdi image\n" - "load pdi image at ddr address 'addr' with pdi image size 'len'\n"); - -U_BOOT_CMD_WITH_SUBCMDS(versalnet, "Versal NET sub-system", versalnet_help_text, - U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1, - do_versalnet_load_pdi)); diff --git a/board/xilinx/versal/Kconfig b/board/xilinx/versal/Kconfig deleted file mode 100644 index c0cccc2068b..00000000000 --- a/board/xilinx/versal/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2020, Xilinx, Inc. -# -# SPDX-License-Identifier: GPL-2.0 - -if ARCH_VERSAL - -config CMD_VERSAL - bool "Enable Versal specific commands" - default y - depends on ZYNQMP_FIRMWARE - help - Enable Versal specific commands. - -endif diff --git a/board/xilinx/versal/Makefile b/board/xilinx/versal/Makefile index d912f2e74f3..761e084e77c 100644 --- a/board/xilinx/versal/Makefile +++ b/board/xilinx/versal/Makefile @@ -5,4 +5,3 @@ # obj-y := board.o -obj-$(CONFIG_CMD_VERSAL) += cmds.o diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 05530736751..9371c30ea27 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -27,6 +27,7 @@ #include <dm/device.h> #include <dm/uclass.h> #include <versalpl.h> +#include <zynqmp_firmware.h> #include "../common/board.h" DECLARE_GLOBAL_DATA_PTR; @@ -43,7 +44,11 @@ static u8 versal_get_bootmode(void) u8 bootmode; u32 reg = 0; - reg = readl(&crp_base->boot_mode_usr); + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) { + reg = zynqmp_pm_get_bootmode_reg(); + } else { + reg = readl(&crp_base->boot_mode_usr); + } if (reg >> BOOT_MODE_ALT_SHIFT) reg >>= BOOT_MODE_ALT_SHIFT; @@ -56,12 +61,18 @@ static u8 versal_get_bootmode(void) static u32 versal_multi_boot(void) { u8 bootmode = versal_get_bootmode(); + u32 reg = 0; /* Mostly workaround for QEMU CI pipeline */ if (bootmode == JTAG_MODE) return 0; - return readl(0xF1110004); + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) + reg = zynqmp_pm_get_pmc_multi_boot_reg(); + else + reg = readl(PMC_MULTI_BOOT_REG); + + return reg & PMC_MULTI_BOOT_MASK; } int board_init(void) @@ -272,6 +283,7 @@ static int boot_targets_setup(void) env_targets ? env_targets : ""); env_set("boot_targets", new_targets); + free(new_targets); } return 0; @@ -395,7 +407,7 @@ void configure_capsule_updates(void) ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); - memset(buf, 0, sizeof(buf)); + memset(buf, 0, DFU_ALT_BUF_LEN); multiboot = env_get_hex("multiboot", multiboot); diff --git a/board/xilinx/versal/cmds.c b/board/xilinx/versal/cmds.c deleted file mode 100644 index c78793573e8..00000000000 --- a/board/xilinx/versal/cmds.c +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * (C) Copyright 2020 Xilinx, Inc. - * Michal Simek <michal.simek@amd.com> - */ - -#include <cpu_func.h> -#include <command.h> -#include <log.h> -#include <memalign.h> -#include <versalpl.h> -#include <vsprintf.h> -#include <zynqmp_firmware.h> - -static int do_versal_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc, - char * const argv[]) -{ - u32 buf_lo, buf_hi; - u32 ret_payload[PAYLOAD_ARG_CNT]; - ulong addr, *pdi_buf; - size_t len; - int ret; - - if (argc != cmdtp->maxargs) { - debug("pdi_load: incorrect parameters passed\n"); - return CMD_RET_USAGE; - } - - addr = simple_strtol(argv[2], NULL, 16); - if (!addr) { - debug("pdi_load: zero pdi_data address\n"); - return CMD_RET_USAGE; - } - - len = hextoul(argv[3], NULL); - if (!len) { - debug("pdi_load: zero size\n"); - return CMD_RET_USAGE; - } - - pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN); - if ((ulong)addr != (ulong)pdi_buf) { - memcpy((void *)pdi_buf, (void *)addr, len); - debug("Pdi addr:0x%lx aligned to 0x%lx\n", - addr, (ulong)pdi_buf); - } - - flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len); - - buf_lo = lower_32_bits((ulong)pdi_buf); - buf_hi = upper_32_bits((ulong)pdi_buf); - - ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, - buf_hi, 0, ret_payload); - if (ret) - printf("PDI load failed with err: 0x%08x\n", ret); - - return ret; -} - -static struct cmd_tbl cmd_versal_sub[] = { - U_BOOT_CMD_MKENT(loadpdi, 4, 1, do_versal_load_pdi, "", ""), -}; - -/** - * do_versal - Handle the "versal" command-line command - * @cmdtp: Command data struct pointer - * @flag: Command flag - * @argc: Command-line argument count - * @argv: Array of command-line arguments - * - * Processes the versal specific commands - * - * Return: return 0 on success, Error value if command fails. - * CMD_RET_USAGE incase of incorrect/missing parameters. - */ -static int do_versal(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - struct cmd_tbl *c; - int ret = CMD_RET_USAGE; - - if (argc < 2) - return CMD_RET_USAGE; - - c = find_cmd_tbl(argv[1], &cmd_versal_sub[0], - ARRAY_SIZE(cmd_versal_sub)); - if (c) - ret = c->cmd(c, flag, argc, argv); - - return cmd_process_error(c, ret); -} - -U_BOOT_LONGHELP(versal, - "loadpdi addr len - Load pdi image\n" - "load pdi image at ddr address 'addr' with pdi image size 'len'\n"); - -U_BOOT_CMD(versal, 4, 1, do_versal, - "versal sub-system", - versal_help_text -); diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 5efef61fa8f..04dee1b8269 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -175,7 +175,7 @@ void configure_capsule_updates(void) { ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); - memset(buf, 0, sizeof(buf)); + memset(buf, 0, DFU_ALT_BUF_LEN); switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { #if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 33205d4cf1d..735ef3cd1be 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -668,7 +668,7 @@ void configure_capsule_updates(void) ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); - memset(buf, 0, sizeof(buf)); + memset(buf, 0, DFU_ALT_BUF_LEN); multiboot = multi_boot(); if (multiboot < 0) diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env index 75b604a1f76..89f48c03586 100644 --- a/board/xilinx/zynqmp/zynqmp_kria.env +++ b/board/xilinx/zynqmp/zynqmp_kria.env @@ -42,7 +42,7 @@ script_offset_f=0x3e80000 script_size_f=0x80000 scriptaddr=0x20000000 usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boot_part; fi -preboot=setenv boot_targets; setenv modeboot; run board_setup +preboot=setenv boot_targets; setenv modeboot; run board_setup; usb start usb_pgood_delay=1000 # SOM specific boot methods diff --git a/cmd/bootefi.c b/cmd/bootefi.c index dce8285b047..cea6d356ee6 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -38,6 +38,9 @@ static efi_status_t bootefi_run_prepare(const char *load_options_path, if (ret != EFI_SUCCESS) return ret; + (*image_objp)->auth_status = EFI_IMAGE_AUTH_PASSED; + (*image_objp)->entry = efi_selftest; + /* Transfer environment variable as load options */ return efi_env_set_load_options((efi_handle_t)*image_objp, load_options_path, @@ -106,8 +109,8 @@ static int do_efi_selftest(void) return CMD_RET_FAILURE; /* Execute the test */ - ret = EFI_CALL(efi_selftest(&image_obj->header, &systab)); - free(loaded_image_info->load_options); + ret = do_bootefi_exec(&image_obj->header, + loaded_image_info->load_options); efi_free_pool(test_device_path); efi_free_pool(test_image_path); if (ret != EFI_SUCCESS) diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c index e08b6ba4a5d..629bf1b82c7 100644 --- a/cmd/eficonfig.c +++ b/cmd/eficonfig.c @@ -2283,26 +2283,11 @@ static efi_status_t eficonfig_init(void) { efi_status_t ret = EFI_SUCCESS; static bool init; - struct efi_handler *handler; unsigned long columns, rows; if (!init) { - ret = efi_search_protocol(efi_root, &efi_guid_text_input_protocol, &handler); - if (ret != EFI_SUCCESS) - return ret; - - ret = efi_protocol_open(handler, (void **)&cin, efi_root, NULL, - EFI_OPEN_PROTOCOL_GET_PROTOCOL); - if (ret != EFI_SUCCESS) - return ret; - ret = efi_search_protocol(efi_root, &efi_guid_text_output_protocol, &handler); - if (ret != EFI_SUCCESS) - return ret; - - ret = efi_protocol_open(handler, (void **)&cout, efi_root, NULL, - EFI_OPEN_PROTOCOL_GET_PROTOCOL); - if (ret != EFI_SUCCESS) - return ret; + cout = systab.con_out; + cin = systab.con_in; cout->query_mode(cout, cout->mode->mode, &columns, &rows); avail_row = rows - (EFICONFIG_MENU_HEADER_ROW_NUM + diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c index 5e4ffc40d72..6b7d9ee061d 100644 --- a/cmd/mvebu/bubt.c +++ b/cmd/mvebu/bubt.c @@ -931,7 +931,7 @@ static int check_image_header(void) size = le32_to_cpu(hdr->blocksize); if (hdr->blockid == 0x78) { /* SATA id */ - struct blk_desc *blk_dev = IS_ENABLED(BLK) ? blk_get_devnum_by_uclass_id(UCLASS_SCSI, 0) : NULL; + struct blk_desc *blk_dev = IS_ENABLED(CONFIG_BLK) ? blk_get_devnum_by_uclass_id(UCLASS_SCSI, 0) : NULL; unsigned long blksz = blk_dev ? blk_dev->blksz : 512; offset *= blksz; } diff --git a/common/board_f.c b/common/board_f.c index e4e17dd717e..bff465d9cb2 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -477,6 +477,13 @@ static int reserve_trace(void) static int reserve_uboot(void) { + /* + * This should be the first place GD_FLG_SKIP_RELOC is read from. + * Set GD_FLG_SKIP_RELOC flag if CONFIG_SKIP_RELOCATE is enabled. + */ + if (CONFIG_IS_ENABLED(SKIP_RELOCATE)) + gd->flags |= GD_FLG_SKIP_RELOC; + if (!(gd->flags & GD_FLG_SKIP_RELOC)) { /* * reserve memory for U-Boot code, data & bss diff --git a/common/spl/Kconfig b/common/spl/Kconfig index c08045f9c8d..3282e08a754 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -537,6 +537,7 @@ if SPL_SYS_MMCSD_RAW_MODE choice prompt "Method for locating next phase of boot (e.g. U-Boot)" + default SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR if MVEBU_SPL_BOOT_DEVICE_MMC config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR bool "MMC raw mode: by sector" diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 12c4cb96815..2cfebac53df 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -35,9 +35,10 @@ CONFIG_PCI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_BOOTCOMMAND=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;" CONFIG_LOGLEVEL=7 CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/amd_versal2_mini_defconfig b/configs/amd_versal2_mini_defconfig index b6571186030..d224583f56a 100644 --- a/configs/amd_versal2_mini_defconfig +++ b/configs/amd_versal2_mini_defconfig @@ -13,12 +13,9 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF20000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" CONFIG_SYS_LOAD_ADDR=0xBBF80000 -CONFIG_DEBUG_UART_BASE=0xf1920000 -CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set -CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 # CONFIG_EXPERT is not set @@ -71,9 +68,6 @@ CONFIG_NO_NET=y # CONFIG_INPUT is not set # CONFIG_MMC is not set # CONFIG_POWER is not set -CONFIG_DEBUG_UART_PL011=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y # CONFIG_GZIP is not set diff --git a/configs/amd_versal2_mini_emmc_defconfig b/configs/amd_versal2_mini_emmc_defconfig index da3eebe3fdf..3afc6cb2736 100644 --- a/configs/amd_versal2_mini_emmc_defconfig +++ b/configs/amd_versal2_mini_emmc_defconfig @@ -10,11 +10,8 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" CONFIG_SYS_LOAD_ADDR=0x8000000 -CONFIG_DEBUG_UART_BASE=0xf1920000 -CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_XILINX_MINI=y # CONFIG_PSCI_RESET is not set -CONFIG_DEBUG_UART=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_EFI_LOADER is not set @@ -60,9 +57,6 @@ CONFIG_NO_NET=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_DEBUG_UART_PL011=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y CONFIG_FAT_WRITE=y diff --git a/configs/amd_versal2_mini_ospi_defconfig b/configs/amd_versal2_mini_ospi_defconfig index 8b9c44017eb..54328e85784 100644 --- a/configs/amd_versal2_mini_ospi_defconfig +++ b/configs/amd_versal2_mini_ospi_defconfig @@ -13,12 +13,9 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF20000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" CONFIG_SYS_LOAD_ADDR=0xBBF80000 -CONFIG_DEBUG_UART_BASE=0xf1920000 -CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set -CONFIG_DEBUG_UART=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_LEGACY_IMAGE_FORMAT is not set @@ -72,9 +69,6 @@ CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MT35XU=y # CONFIG_POWER is not set -CONFIG_DEBUG_UART_PL011=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y CONFIG_SPI=y diff --git a/configs/amd_versal2_mini_qspi_defconfig b/configs/amd_versal2_mini_qspi_defconfig index e17ca865725..48fb7ae0e7f 100644 --- a/configs/amd_versal2_mini_qspi_defconfig +++ b/configs/amd_versal2_mini_qspi_defconfig @@ -13,12 +13,9 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF20000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" CONFIG_SYS_LOAD_ADDR=0xBBF80000 -CONFIG_DEBUG_UART_BASE=0xf1920000 -CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set -CONFIG_DEBUG_UART=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_LEGACY_IMAGE_FORMAT is not set @@ -65,9 +62,6 @@ CONFIG_NO_NET=y # CONFIG_INPUT is not set # CONFIG_MMC is not set # CONFIG_POWER is not set -CONFIG_DEBUG_UART_PL011=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y CONFIG_SPI=y diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 9911caa0e46..6ec7dd317fd 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -3,17 +3,15 @@ CONFIG_COUNTER_FREQUENCY=375000 CONFIG_POSITION_INDEPENDENT=y CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 CONFIG_ARCH_VERSAL2=y -CONFIG_TEXT_BASE=0x8000000 +CONFIG_TEXT_BASE=0x40000000 CONFIG_SYS_MALLOC_F_LEN=0x100000 +CONFIG_NR_DRAM_BANKS=36 CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-virt" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SYS_BOOTM_LEN=0x6400000 CONFIG_SYS_LOAD_ADDR=0x8000000 -CONFIG_DEBUG_UART_BASE=0xf1920000 -CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_CMD_FRU=y -CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_REMAKE_ELF=y @@ -28,6 +26,7 @@ CONFIG_SYS_PBSIZE=2073 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CLOCKS=y CONFIG_SYS_PROMPT="versal2> " +CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y @@ -64,8 +63,9 @@ CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_BOARD=y -CONFIG_DTB_RESELECT=y -CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y @@ -75,6 +75,8 @@ CONFIG_CLK_CCF=y CONFIG_CLK_SCMI=y CONFIG_DFU_RAM=y CONFIG_ARM_FFA_TRANSPORT=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_VERSALPL=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_I2C_MUX=y @@ -82,6 +84,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MAILBOX=y CONFIG_ZYNQMP_IPI=y CONFIG_MISC=y +CONFIG_NVMEM=y CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y @@ -113,11 +116,10 @@ CONFIG_PHY_GIGE=y CONFIG_XILINX_AXIEMAC=y CONFIG_ZYNQ_GEM=y CONFIG_POWER_DOMAIN=y +CONFIG_ZYNQMP_POWER_DOMAIN=y CONFIG_RESET_SCMI=y +CONFIG_RESET_ZYNQMP=y CONFIG_SCSI=y -CONFIG_DEBUG_UART_PL011=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y CONFIG_SOC_DEVICE=y diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig index f09b5b603a2..c74247e13db 100644 --- a/configs/an7581_evb_defconfig +++ b/configs/an7581_evb_defconfig @@ -76,3 +76,6 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_SHA512=y +CONFIG_AIROHA_ETH=y +CONFIG_MMC_MTK=y +CONFIG_AIROHA_SNFI_SPI=y diff --git a/configs/brcp150_defconfig b/configs/brcp150_defconfig new file mode 100644 index 00000000000..d619f71f37b --- /dev/null +++ b/configs/brcp150_defconfig @@ -0,0 +1,121 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="BuR" +CONFIG_SYS_CONFIG_NAME="brzynq" +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_ZYNQ=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SOURCE_FILE="env/brcp150" +CONFIG_SF_DEFAULT_SPEED=100000000 +CONFIG_SF_DEFAULT_MODE=0x3 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x20000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp150" +CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000 +# CONFIG_SPL_MMC is not set +CONFIG_SPL_STACK_R_ADDR=0x800000 +CONFIG_SPL_STACK=0xFFFFFE00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_SPL_SIZE_LIMIT=0x20000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x30000 +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000 +CONFIG_TARGET_ZYNQ_BR=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000 +CONFIG_SPL_LOAD_FIT_FULL=y +CONFIG_BOOTDELAY=0 +CONFIG_OF_ENV_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run b_default" +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set +CONFIG_SPL_CPU=y +CONFIG_SPL_FPGA=y +CONFIG_SPL_I2C=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_HUSH_PARSER=y +CONFIG_HUSH_MODERN_PARSER=y +CONFIG_SYS_PROMPT="-> " +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_MAY_FAIL=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_NET_RETRY_COUNT=10 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_MAX7320_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ZYNQ_HISPD_BROKEN=y +CONFIG_DM_MTD=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_PHY_TI_GENERIC=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_SHA256 is not set +CONFIG_SPL_CRC32=y +# CONFIG_SPL_SHA1 is not set diff --git a/configs/brcp170_defconfig b/configs/brcp170_defconfig new file mode 100644 index 00000000000..06cd64ad4bc --- /dev/null +++ b/configs/brcp170_defconfig @@ -0,0 +1,120 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="BuR" +CONFIG_SYS_CONFIG_NAME="brzynq" +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_ZYNQ=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SOURCE_FILE="env/brcp1" +CONFIG_SF_DEFAULT_SPEED=100000000 +CONFIG_SF_DEFAULT_MODE=0x3 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x20000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp170" +CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000 +# CONFIG_SPL_MMC is not set +CONFIG_SPL_STACK_R_ADDR=0x800000 +CONFIG_SPL_STACK=0xFFFFFE00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_SPL_SIZE_LIMIT=0x20000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x30000 +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000 +CONFIG_TARGET_ZYNQ_BR=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000 +CONFIG_SPL_LOAD_FIT_FULL=y +CONFIG_BOOTDELAY=0 +CONFIG_OF_ENV_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run b_default" +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set +CONFIG_SPL_CPU=y +CONFIG_SPL_I2C=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_HUSH_PARSER=y +CONFIG_HUSH_MODERN_PARSER=y +CONFIG_SYS_PROMPT="-> " +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_MAY_FAIL=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_NET_RETRY_COUNT=10 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_MAX7320_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ZYNQ_HISPD_BROKEN=y +CONFIG_DM_MTD=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_PHY_TI_GENERIC=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_SHA256 is not set +CONFIG_SPL_CRC32=y +# CONFIG_SPL_SHA1 is not set diff --git a/configs/brcp1_1r_defconfig b/configs/brcp1_1r_defconfig new file mode 100644 index 00000000000..ed2eb86545c --- /dev/null +++ b/configs/brcp1_1r_defconfig @@ -0,0 +1,120 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="BuR" +CONFIG_SYS_CONFIG_NAME="brzynq" +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_ZYNQ=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SOURCE_FILE="env/brcp1" +CONFIG_SF_DEFAULT_SPEED=100000000 +CONFIG_SF_DEFAULT_MODE=0x3 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x20000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_1r" +CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000 +# CONFIG_SPL_MMC is not set +CONFIG_SPL_STACK_R_ADDR=0x800000 +CONFIG_SPL_STACK=0xFFFFFE00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_SPL_SIZE_LIMIT=0x20000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x30000 +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000 +CONFIG_TARGET_ZYNQ_BR=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000 +CONFIG_SPL_LOAD_FIT_FULL=y +CONFIG_BOOTDELAY=0 +CONFIG_OF_ENV_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run b_default" +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set +CONFIG_SPL_CPU=y +CONFIG_SPL_I2C=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_HUSH_PARSER=y +CONFIG_HUSH_MODERN_PARSER=y +CONFIG_SYS_PROMPT="-> " +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_MAY_FAIL=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_NET_RETRY_COUNT=10 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_MAX7320_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ZYNQ_HISPD_BROKEN=y +CONFIG_DM_MTD=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_PHY_NATSEMI=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_SHA256 is not set +CONFIG_SPL_CRC32=y +# CONFIG_SPL_SHA1 is not set diff --git a/configs/brcp1_1r_switch_defconfig b/configs/brcp1_1r_switch_defconfig new file mode 100644 index 00000000000..38427da7b51 --- /dev/null +++ b/configs/brcp1_1r_switch_defconfig @@ -0,0 +1,121 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="BuR" +CONFIG_SYS_CONFIG_NAME="brzynq" +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_ZYNQ=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SOURCE_FILE="env/brcp1" +CONFIG_SF_DEFAULT_SPEED=100000000 +CONFIG_SF_DEFAULT_MODE=0x3 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x20000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_1r_switch" +CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000 +# CONFIG_SPL_MMC is not set +CONFIG_SPL_STACK_R_ADDR=0x800000 +CONFIG_SPL_STACK=0xFFFFFE00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_SPL_SIZE_LIMIT=0x20000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x30000 +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000 +CONFIG_TARGET_ZYNQ_BR=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000 +CONFIG_SPL_LOAD_FIT_FULL=y +CONFIG_BOOTDELAY=0 +CONFIG_OF_ENV_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run b_default" +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set +CONFIG_SPL_CPU=y +CONFIG_SPL_I2C=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_HUSH_PARSER=y +CONFIG_HUSH_MODERN_PARSER=y +CONFIG_SYS_PROMPT="-> " +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_MAY_FAIL=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_NET_RETRY_COUNT=10 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_MAX7320_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ZYNQ_HISPD_BROKEN=y +CONFIG_DM_MTD=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_FIXED=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_SHA256 is not set +CONFIG_SPL_CRC32=y +# CONFIG_SPL_SHA1 is not set diff --git a/configs/brcp1_2r_defconfig b/configs/brcp1_2r_defconfig new file mode 100644 index 00000000000..2bc8eab14a8 --- /dev/null +++ b/configs/brcp1_2r_defconfig @@ -0,0 +1,120 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="BuR" +CONFIG_SYS_CONFIG_NAME="brzynq" +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_ZYNQ=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SOURCE_FILE="env/brcp1" +CONFIG_SF_DEFAULT_SPEED=100000000 +CONFIG_SF_DEFAULT_MODE=0x3 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x20000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-brcp1_2r" +CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000 +# CONFIG_SPL_MMC is not set +CONFIG_SPL_STACK_R_ADDR=0x800000 +CONFIG_SPL_STACK=0xFFFFFE00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_SPL_SIZE_LIMIT=0x20000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x30000 +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000 +CONFIG_TARGET_ZYNQ_BR=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000 +CONFIG_SPL_LOAD_FIT_FULL=y +CONFIG_BOOTDELAY=0 +CONFIG_OF_ENV_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run b_default" +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set +CONFIG_SPL_CPU=y +CONFIG_SPL_I2C=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_HUSH_PARSER=y +CONFIG_HUSH_MODERN_PARSER=y +CONFIG_SYS_PROMPT="-> " +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_MAY_FAIL=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_NET_RETRY_COUNT=10 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_MAX7320_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ZYNQ_HISPD_BROKEN=y +CONFIG_DM_MTD=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_PHY_NATSEMI=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_SHA256 is not set +CONFIG_SPL_CRC32=y +# CONFIG_SPL_SHA1 is not set diff --git a/configs/brsmarc2_defconfig b/configs/brsmarc2_defconfig new file mode 100644 index 00000000000..0b57042424b --- /dev/null +++ b/configs/brsmarc2_defconfig @@ -0,0 +1,120 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="BuR" +CONFIG_SYS_CONFIG_NAME="brzynq" +CONFIG_SYS_L2CACHE_OFF=y +CONFIG_ARCH_ZYNQ=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SOURCE_FILE="env/brcp1" +CONFIG_SF_DEFAULT_SPEED=100000000 +CONFIG_SF_DEFAULT_MODE=0x3 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x20000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-brsmarc2" +CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10000 +# CONFIG_SPL_MMC is not set +CONFIG_SPL_STACK_R_ADDR=0x800000 +CONFIG_SPL_STACK=0xFFFFFE00 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x600000 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_SPL_SIZE_LIMIT=0x20000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x30000 +# CONFIG_SPL_FS_FAT is not set +# CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000 +CONFIG_TARGET_ZYNQ_BR=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x4000000 +CONFIG_SPL_LOAD_FIT_FULL=y +CONFIG_BOOTDELAY=0 +CONFIG_OF_ENV_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run b_default" +CONFIG_USE_PREBOOT=y +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_CLOCKS=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set +CONFIG_SPL_CPU=y +CONFIG_SPL_I2C=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_HUSH_PARSER=y +CONFIG_HUSH_MODERN_PARSER=y +CONFIG_SYS_PROMPT="-> " +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_MAY_FAIL=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_NET_RETRY_COUNT=10 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_MAX7320_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ZYNQ_HISPD_BROKEN=y +CONFIG_DM_MTD=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_PHY_NATSEMI=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_SHA256 is not set +CONFIG_SPL_CRC32=y +# CONFIG_SPL_SHA1 is not set diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index d9314ed1e15..4adf8cc84bd 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -61,7 +61,6 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_I2C_EEPROM=y CONFIG_SPL_I2C_EEPROM=y CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y diff --git a/configs/clearfog_sata_defconfig b/configs/clearfog_sata_defconfig index d5f90d06ca6..8154125b4ac 100644 --- a/configs/clearfog_sata_defconfig +++ b/configs/clearfog_sata_defconfig @@ -62,7 +62,6 @@ CONFIG_I2C_EEPROM=y CONFIG_SPL_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y diff --git a/configs/clearfog_spi_defconfig b/configs/clearfog_spi_defconfig index 8868c7fde5e..e9e3e8cdec4 100644 --- a/configs/clearfog_spi_defconfig +++ b/configs/clearfog_spi_defconfig @@ -62,7 +62,6 @@ CONFIG_I2C_EEPROM=y CONFIG_SPL_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index 6927e20abd1..3fb5f677ce8 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -61,7 +61,6 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_I2C_EEPROM=y CONFIG_SPL_I2C_EEPROM=y CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y diff --git a/configs/mvebu_espressobin_ultra-88f3720_defconfig b/configs/mvebu_espressobin_ultra-88f3720_defconfig index 6f1a66f5f1d..1cbeee8fcb7 100644 --- a/configs/mvebu_espressobin_ultra-88f3720_defconfig +++ b/configs/mvebu_espressobin_ultra-88f3720_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 8f327e5f2ab..4ac0a5d9b99 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_TEXT_BASE=0x80200000 +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=3 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000 @@ -31,6 +32,8 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BLOBLIST=y +CONFIG_BLOBLIST_FIXED=y +CONFIG_BLOBLIST_ADDR=0x7e000 CONFIG_BLOBLIST_SIZE=0x1000 CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_HANDOFF=y @@ -73,6 +76,8 @@ CONFIG_BOOTFILE="kernel.itb" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y @@ -82,6 +87,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MARVELL=y CONFIG_DWC_ETH_XGMAC=y CONFIG_RGMII=y CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/socfpga_agilex5_vab_defconfig b/configs/socfpga_agilex5_vab_defconfig new file mode 100644 index 00000000000..a5f4b335760 --- /dev/null +++ b/configs/socfpga_agilex5_vab_defconfig @@ -0,0 +1,3 @@ +#include <configs/socfpga_agilex5_defconfig> + +CONFIG_SOCFPGA_SECURE_VAB_AUTH=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index 6bfcaab37dc..1be8d892070 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -28,9 +28,9 @@ CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=0 -CONFIG_BOOTCOMMAND="if mmcinfo; then if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; fi; fi; run $modeboot" CONFIG_USE_PREBOOT=y CONFIG_SYS_PBSIZE=2077 +# CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x30000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set @@ -41,15 +41,25 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_SYS_MAXARGS=32 +# CONFIG_CMD_BOOTEFI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_SPL is not set CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_THOR_RESET_OFF=y +# CONFIG_CMD_SAVEENV is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y +# CONFIG_CMD_EFICONFIG is not set +CONFIG_CMD_SQUASHFS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:0x100000(qspi-boot-bin),-(qspi-rootfs)" +CONFIG_CMD_UBI=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -57,14 +67,18 @@ CONFIG_NO_NET=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_RAM=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000 -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQPL=y +CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_MTD=y +CONFIG_MTD_BLOCK=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI_BEB_LIMIT=0 +CONFIG_UBI_BLOCK=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_ARM_DCC=y CONFIG_ZYNQ_SERIAL=y @@ -80,3 +94,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +CONFIG_LZ4=y diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig index e1cdc186fb4..af9ce499169 100644 --- a/configs/xilinx_versal_mini_ospi_defconfig +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_LEN=0x2000 CONFIG_SYS_MALLOC_F_LEN=0x500 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFFFE00 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE1000 CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x80 # CONFIG_DM_GPIO is not set diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 1604b5915db..a82ccdc9a0c 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -74,6 +74,8 @@ CONFIG_SIMPLE_PM_BUS=y CONFIG_CLK_VERSAL=y CONFIG_DFU_RAM=y CONFIG_ARM_FFA_TRANSPORT=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_VERSALPL=y CONFIG_ZYNQ_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y @@ -121,7 +123,6 @@ CONFIG_ZYNQMP_POWER_DOMAIN=y CONFIG_RESET_ZYNQMP=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y -CONFIG_XILINX_UARTLITE=y CONFIG_SOC_DEVICE=y CONFIG_SOC_XILINX_VERSAL_NET=y CONFIG_SPI=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index baa4b8e412e..ba4519ce303 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -133,7 +133,6 @@ CONFIG_ZYNQMP_POWER_DOMAIN=y CONFIG_RESET_ZYNQMP=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y -CONFIG_XILINX_UARTLITE=y CONFIG_SOC_XILINX_VERSAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 1f8e8c348eb..ae79f101701 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -187,7 +187,6 @@ CONFIG_DM_RTC=y CONFIG_RTC_ZYNQMP=y CONFIG_SCSI=y CONFIG_ARM_DCC=y -CONFIG_XILINX_UARTLITE=y CONFIG_ZYNQ_SERIAL=y CONFIG_SOC_XILINX_ZYNQMP=y CONFIG_SPI=y @@ -228,3 +227,4 @@ CONFIG_PANIC_HANG=y CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y CONFIG_SPL_GZIP=y +CONFIG_TOOLS_MKFWUMDATA=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index abd1e1bb574..29aa5891b23 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -199,7 +199,6 @@ CONFIG_RTC_EMULATION=y CONFIG_RTC_ZYNQMP=y CONFIG_SCSI=y CONFIG_ARM_DCC=y -CONFIG_XILINX_UARTLITE=y CONFIG_ZYNQ_SERIAL=y CONFIG_SOC_XILINX_ZYNQMP=y CONFIG_SPI=y diff --git a/doc/board/ti/j722s_evm.rst b/doc/board/ti/j722s_evm.rst index e5a1be50c4f..edc29a4f9e4 100644 --- a/doc/board/ti/j722s_evm.rst +++ b/doc/board/ti/j722s_evm.rst @@ -74,7 +74,6 @@ Set the variables corresponding to this platform: $ export UBOOT_CFG_CORTEXA=j722s_evm_a53_defconfig $ export TFA_BOARD=lite $ export OPTEE_PLATFORM=k3-am62x - $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y" .. j722s_evm_rst_include_start_build_steps diff --git a/doc/develop/devicetree/dt_qemu.rst b/doc/develop/devicetree/dt_qemu.rst index 8ba2b225590..b452e2a997a 100644 --- a/doc/develop/devicetree/dt_qemu.rst +++ b/doc/develop/devicetree/dt_qemu.rst @@ -16,15 +16,22 @@ Obtaining the QEMU devicetree Where QEMU generates its own devicetree to pass to U-Boot you can use `-dtb u-boot.dtb` to force QEMU to use U-Boot's in-tree version. -To obtain the devicetree that qemu generates, add `-machine dumpdtb=qemu.dtb`, -e.g.:: - - qemu-system-arm -machine virt -machine dumpdtb=qemu.dtb - - qemu-system-aarch64 -machine virt -machine dumpdtb=qemu.dtb - - qemu-system-riscv64 -machine virt -machine dumpdtb=qemu.dtb - +To obtain the devicetree that QEMU generates, add `dumpdtb=qemu.dtb` to the +`-machine` argument, e.g. + +.. code-block:: bash + + qemu-system-aarch64 \ + -machine virt,gic-version=3,dumpdtb=qemu.dtb \ + -cpu cortex-a57 \ + -smp 4 \ + -memory 8G \ + -chardev socket,id=chrtpm,path=/tmp/mytpm1/swtpm-sock \ + -tpmdev emulator,id=tpm0,chardev=chrtpm \ + -device tpm-tis-device,tpmdev=tpm0 + +Except for the dumpdtb=qemu.dtb sub-parameter use the same qemu-system-<arch> +invocation that you would use to start U-Boot to to get a complete device-tree. Merging in U-Boot nodes/properties ---------------------------------- diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index cbbc2bad0eb..50948c00927 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -1,3 +1,5 @@ +.. |next_ver| replace:: v2025.07 + Release Cycle ============= @@ -53,13 +55,13 @@ Current Status * U-Boot v2025.04 was released on Monday, 07 April 2025. -* The Merge Window for the next release (v2025.07) is **open** until the -rc1 +* The Merge Window for the next release (|next_ver|) is **open** until the -rc1 release on Monday, 28 April 2025. * The next branch is now **closed** until the -rc2 release on Monday, 12 May 2025. -* Release "v2025.07" is scheduled for Monday, 07 July 2025. +* Release "|next_ver|" is scheduled for Monday, 07 July 2025. Future Releases --------------- @@ -69,15 +71,15 @@ Future Releases .. For the next scheduled release, release candidates were made on:: -.. * U-Boot v2025.07-rc1 was released on Mon 21 April 2025. +.. * U-Boot |next_ver|-rc1 was released on Mon 21 April 2025. -.. * U-Boot v2025.07-rc2 was released on Mon 12 May 2025. +.. * U-Boot |next_ver|-rc2 was released on Mon 12 May 2025. -.. * U-Boot v2025.07-rc3 was released on Mon 26 May 2025. +.. * U-Boot |next_ver|-rc3 was released on Mon 26 May 2025. -.. * U-Boot v2025.07-rc4 was released on Mon 09 June 2025. +.. * U-Boot |next_ver|-rc4 was released on Mon 09 June 2025. -.. * U-Boot v2025.07-rc5 was released on Mon 23 June 2025. +.. * U-Boot |next_ver|-rc5 was released on Mon 23 June 2025. Please note that the following dates are planned only and may be deviated from as needed. diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c index db9435db657..fc09dde3f9e 100644 --- a/drivers/ddr/altera/iossm_mailbox.c +++ b/drivers/ddr/altera/iossm_mailbox.c @@ -10,6 +10,7 @@ #include <asm/arch/base_addr_soc64.h> #include <asm/io.h> #include <linux/bitfield.h> +#include <linux/sizes.h> #include "iossm_mailbox.h" #define TIMEOUT_120000MS 120000 @@ -87,6 +88,7 @@ /* offset info of ECC_ENABLE_INTF */ #define INTF_ECC_ENABLE_TYPE_MASK GENMASK(1, 0) +#define INTF_ECC_TYPE_MASK BIT(8) /* cmd opcode BIST_MEM_INIT_START, BIST performed on full memory address range */ #define BIST_FULL_MEM BIT(6) @@ -96,6 +98,7 @@ /* offset info of ECC_ERR_STATUS */ #define ECC_ERR_COUNTER_MASK GENMASK(15, 0) +#define ECC_ERR_OVERFLOW_MASK GENMASK(31, 16) /* offset info of ECC_ERR_DATA */ #define ECC_ERR_IP_TYPE_MASK GENMASK(24, 22) @@ -104,9 +107,15 @@ #define ECC_ERR_TYPE_MASK GENMASK(9, 6) #define ECC_ERR_ADDR_UPPER_MASK GENMASK(5, 0) #define ECC_ERR_ADDR_LOWER_MASK GENMASK(31, 0) +#define ECC_FULL_ADDR_UPPER_MASK GENMASK(63, 32) +#define ECC_FULL_ADDR_LOWER_MASK GENMASK(31, 0) #define MAX_ECC_ERR_INFO_COUNT 16 +#define BIST_START_ADDR_SPACE_MASK GENMASK(5, 0) +#define BIST_START_ADDR_LOW_MASK GENMASK(31, 0) +#define BIST_START_ADDR_HIGH_MASK GENMASK(37, 32) + #define IO96B_MB_REQ_SETUP(v, w, x, y, z) \ usr_req.ip_type = v; \ usr_req.ip_id = w; \ @@ -161,6 +170,24 @@ struct ecc_err_info { u32 addr_lower; }; +struct ecc_overflow_error_desc { + int bit; + const char *msg; +}; + +static const struct ecc_overflow_error_desc ecc_overflow_errors[] = { + { 0, " - Single-bit error\n" }, + { 1, " - Multiple single-bit errors\n" }, + { 2, " - Double-bit error\n" }, + { 3, " - Multiple double-bit errors\n" }, + { 8, " - Single-bit error during ECC scrubbing\n" }, + { 9, " - Write link ECC single-bit error (LPDDR5 only)\n" }, + { 10, " - Write link ECC double-bit error (LPDDR5 only)\n" }, + { 11, " - Read link ECC single-bit error (LPDDR5 only)\n" }, + { 12, " - Read link ECC double-bit error (LPDDR5 only)\n" }, + { 13, " - RMW read link ECC double-bit error (LPDDR5 only)\n" }, +}; + static int is_ddr_csr_clkgen_locked(u8 io96b_pll) { int ret = 0; @@ -512,7 +539,7 @@ int get_mem_width_info(struct io96b_info *io96b_ctrl) { int i, j, ret = 0; u32 mem_width_info; - u16 memory_size, total_memory_size = 0; + phys_size_t memory_size, total_memory_size = 0; u32 mem_total_capacity_intf_offset[MAX_MEM_INTERFACE_SUPPORTED] = { IOSSM_MEM_TOTAL_CAPACITY_INTF0_OFFSET, @@ -526,8 +553,11 @@ int get_mem_width_info(struct io96b_info *io96b_ctrl) mem_width_info = readl(io96b_ctrl->io96b[i].io96b_csr_addr + mem_total_capacity_intf_offset[j]); - memory_size = memory_size + - FIELD_GET(INTF_CAPACITY_GBITS_MASK, mem_width_info); + io96b_ctrl->io96b[i].mb_ctrl.memory_size[j] = + FIELD_GET(INTF_CAPACITY_GBITS_MASK, mem_width_info) * SZ_1G / SZ_8; + + if (io96b_ctrl->io96b[i].mb_ctrl.memory_size[j] != 0) + memory_size += io96b_ctrl->io96b[i].mb_ctrl.memory_size[j]; } if (!memory_size) { @@ -536,8 +566,6 @@ int get_mem_width_info(struct io96b_info *io96b_ctrl) goto err; } - io96b_ctrl->io96b[i].size = memory_size; - total_memory_size = total_memory_size + memory_size; } @@ -556,7 +584,7 @@ int ecc_enable_status(struct io96b_info *io96b_ctrl) { int i, j, ret = 0; u32 ecc_enable_intf; - bool ecc_stat, ecc_stat_set = false; + bool ecc_status, ecc_status_set = false, inline_ecc = false; u32 ecc_enable_intf_offset[MAX_MEM_INTERFACE_SUPPORTED] = { IOSSM_ECC_ENABLE_INTF0_OFFSET, @@ -565,6 +593,7 @@ int ecc_enable_status(struct io96b_info *io96b_ctrl) /* Initialize ECC status */ io96b_ctrl->ecc_status = false; + io96b_ctrl->inline_ecc = false; /* Get and ensure all memory interface(s) same ECC status */ for (i = 0; i < io96b_ctrl->num_instance; i++) { @@ -572,15 +601,21 @@ int ecc_enable_status(struct io96b_info *io96b_ctrl) ecc_enable_intf = readl(io96b_ctrl->io96b[i].io96b_csr_addr + ecc_enable_intf_offset[j]); - ecc_stat = (FIELD_GET(INTF_ECC_ENABLE_TYPE_MASK, ecc_enable_intf) + ecc_status = (FIELD_GET(INTF_ECC_ENABLE_TYPE_MASK, ecc_enable_intf) == 0) ? false : true; + inline_ecc = FIELD_GET(INTF_ECC_TYPE_MASK, ecc_enable_intf); + + if (!ecc_status_set) { + io96b_ctrl->ecc_status = ecc_status; + + if (io96b_ctrl->ecc_status) + io96b_ctrl->inline_ecc = inline_ecc; - if (!ecc_stat_set) { - io96b_ctrl->ecc_status = ecc_stat; - ecc_stat_set = true; + ecc_status_set = true; } - if (ecc_stat != io96b_ctrl->ecc_status) { + if (ecc_status != io96b_ctrl->ecc_status || + (io96b_ctrl->ecc_status && inline_ecc != io96b_ctrl->inline_ecc)) { printf("%s: Mismatch DDR ECC status on IO96B_%d\n", __func__, i); ret = -EINVAL; @@ -614,16 +649,28 @@ bool ecc_interrupt_status(struct io96b_info *io96b_ctrl) { int i, j; u32 ecc_err_status; - u16 ecc_err_counter; + u16 ecc_err_counter, ecc_overflow_status; bool ecc_error_flag = false; /* Get ECC double-bit error status */ for (i = 0; i < io96b_ctrl->num_instance; i++) { ecc_err_status = readl(io96b_ctrl->io96b[i].io96b_csr_addr + IOSSM_ECC_ERR_STATUS_OFFSET); + ecc_err_counter = FIELD_GET(ECC_ERR_COUNTER_MASK, ecc_err_status); - debug("%s: ECC error number detected on IO96B_%d: %d\n", - __func__, i, ecc_err_counter); + log_err("%s: ECC error number detected on IO96B_%d: %d\n", + __func__, i, ecc_err_counter); + + ecc_overflow_status = FIELD_GET(ECC_ERR_OVERFLOW_MASK, ecc_err_status); + if (ecc_overflow_status != 0) { + log_err("ECC Error Overflow Flags:\n"); + + for (int i = 0; i < ARRAY_SIZE(ecc_overflow_errors); i++) { + if (ecc_overflow_status & BIT(ecc_overflow_errors[i].bit)) { + log_err("%s", ecc_overflow_errors[i].msg); + } + } + } if (ecc_err_counter != 0) { phys_addr_t address; @@ -647,15 +694,20 @@ bool ecc_interrupt_status(struct io96b_info *io96b_ctrl) ecc_err_data); err_info.addr_lower = readl(address + sizeof(u32)); - debug("%s: ECC double-bit error detected on IO96B_%d:\n", - __func__, i); - debug("- error info address :0x%llx\n", address); - debug("- error ip type: %d\n", err_info.ip_type); - debug("- error instance id: %d\n", err_info.instance_id); - debug("- error source id: %d\n", err_info.source_id); - debug("- error type: %d\n", err_info.err_type); - debug("- error address upper: 0x%x\n", err_info.addr_upper); - debug("- error address lower: 0x%x\n", err_info.addr_lower); + log_err(" %s: DDR ECC Error Detected on IO96B_%d number:%d\n", + __func__, i, j); + log_err(" - error info address :0x%llx\n", address); + log_err(" - error ip type: %d\n", err_info.ip_type); + log_err(" - error instance id: %d\n", err_info.instance_id); + log_err(" - error source id: %d\n", err_info.source_id); + log_err(" - error type: %s\n", + is_double_bit_error(err_info.err_type) ? + "Double-bit error" : "Single-bit error"); + log_err(" - error address: 0x%016llx\n", + (u64)FIELD_PREP(ECC_FULL_ADDR_UPPER_MASK, + err_info.addr_upper) | + FIELD_PREP(ECC_FULL_ADDR_LOWER_MASK, + err_info.addr_lower)); if (is_double_bit_error(err_info.err_type)) { if (!ecc_error_flag) @@ -668,12 +720,12 @@ bool ecc_interrupt_status(struct io96b_info *io96b_ctrl) } if (ecc_error_flag) - printf("\n%s: ECC double-bit error detected!\n", __func__); + log_err("\n%s: ECC double-bit error detected!\n", __func__); return ecc_error_flag; } -int bist_mem_init_start(struct io96b_info *io96b_ctrl) +int out_of_band_bist_mem_init_start(struct io96b_info *io96b_ctrl) { struct io96b_mb_req usr_req; struct io96b_mb_resp usr_resp; @@ -746,3 +798,126 @@ int bist_mem_init_start(struct io96b_info *io96b_ctrl) err: return ret; } + +int bist_mem_init_by_addr(struct io96b_info *io96b_ctrl, int inst_id, int intf_id, + phys_addr_t base_addr, phys_size_t size) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + int n, ret = 0; + bool bist_start, bist_success; + u32 mem_exp, mem_init_status_intf, start; + phys_size_t chunk_size; + + u32 mem_init_status_offset[MAX_MEM_INTERFACE_SUPPORTED] = { + IOSSM_MEM_INIT_STATUS_INTF0_OFFSET, + IOSSM_MEM_INIT_STATUS_INTF1_OFFSET + }; + + /* Check if size is a power of 2 */ + if (size == 0 || (size & (size - 1)) != 0) { + ret = -EINVAL; + goto err; + } + + mem_exp = 0; + chunk_size = size; + + while (chunk_size >>= 1) + mem_exp++; + + /* Start memory initialization BIST on the specified address range */ + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[inst_id].mb_ctrl.ip_type[intf_id], + io96b_ctrl->io96b[inst_id].mb_ctrl.ip_id[intf_id], + CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_START, 0); + + /* CMD_PARAM_0 bit[5:0] = mem_exp */ + /* CMD_PARAM_0 bit[6]: 0 - on the specified address range */ + usr_req.cmd_param[0] = FIELD_PREP(BIST_START_ADDR_SPACE_MASK, mem_exp); + /* Extract address fields START_ADDR[31:0] */ + usr_req.cmd_param[1] = FIELD_GET(BIST_START_ADDR_LOW_MASK, base_addr); + /* Extract address fields START_ADDR[37:32] */ + usr_req.cmd_param[2] = FIELD_GET(BIST_START_ADDR_HIGH_MASK, base_addr); + /* Initialize memory to all zeros */ + usr_req.cmd_param[3] = 0; + + bist_start = false; + bist_success = false; + + /* Send request to DDR controller */ + debug("%s:Initializing memory: Addr=0x%llx, Size=2^%u\n", __func__, + base_addr, mem_exp); + ret = io96b_mb_req(io96b_ctrl->io96b[inst_id].io96b_csr_addr, + usr_req, 0, &usr_resp); + if (ret) + goto err; + + bist_start = IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & BIT(0); + + if (!bist_start) { + printf("%s: Failed to initialize memory on IO96B_%d\n", __func__, + inst_id); + printf("%s: BIST_MEM_INIT_START Error code 0x%lx\n", __func__, + IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status)); + + ret = -EINVAL; + goto err; + } + + /* Polling for the initiated memory initialization BIST status */ + start = get_timer(0); + while (!bist_success) { + udelay(1); + + mem_init_status_intf = readl(io96b_ctrl->io96b[inst_id].io96b_csr_addr + + mem_init_status_offset[intf_id]); + + bist_success = FIELD_GET(INTF_BIST_STATUS_MASK, mem_init_status_intf); + + if (!bist_success && (get_timer(start) > TIMEOUT)) { + printf("%s: Timeout initialize memory on IO96B_%d\n", + __func__, inst_id); + printf("%s: BIST_MEM_INIT_STATUS Error code 0x%lx\n", + __func__, + IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status)); + + ret = -ETIMEDOUT; + goto err; + } + } + + debug("%s:DDR memory initializationat 0x%llx completed.\n", __func__, base_addr); + +err: + return ret; +} + +int inline_ecc_bist_mem_init(struct io96b_info *io96b_ctrl) +{ + int i, j, ret = 0; + + /* Memory initialization BIST performed on all memory interfaces */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + ret = bist_mem_init_by_addr(io96b_ctrl, i, j, 0, + io96b_ctrl->io96b[i].mb_ctrl.memory_size[j]); + if (ret) { + printf("Error: Memory init failed at Instance %d, Interface %d\n", + i, j); + goto err; + } + } + } + +err: + return ret; +} + +int bist_mem_init_start(struct io96b_info *io96b_ctrl) +{ + if (io96b_ctrl->inline_ecc) + return inline_ecc_bist_mem_init(io96b_ctrl); + else + return out_of_band_bist_mem_init_start(io96b_ctrl); +} diff --git a/drivers/ddr/altera/iossm_mailbox.h b/drivers/ddr/altera/iossm_mailbox.h index 6f794781d30..02d1db28e20 100644 --- a/drivers/ddr/altera/iossm_mailbox.h +++ b/drivers/ddr/altera/iossm_mailbox.h @@ -40,11 +40,13 @@ enum iossm_mailbox_cmd_opcode { * @num_mem_interface: Number of memory interfaces instantiated * @ip_type: IP type implemented on the IO96B * @ip_instance_id: IP identifier for every IP instance implemented on the IO96B + * @memory_size[2]: Memory size for every IP instance implemented on the IO96B */ struct io96b_mb_ctrl { u32 num_mem_interface; u32 ip_type[2]; u32 ip_id[2]; + phys_size_t memory_size[2]; }; /* CMD_REQ Register Definition */ @@ -53,6 +55,9 @@ struct io96b_mb_ctrl { #define CMD_TYPE_MASK GENMASK(23, 16) #define CMD_OPCODE_MASK GENMASK(15, 0) +/* Computes the Inline ECC data region size */ +#define CALC_INLINE_ECC_HW_SIZE(size) (((size) * 7) / 8) + /* * IOSSM mailbox request * @ip_type: IP type for the specified memory interface @@ -83,13 +88,11 @@ struct io96b_mb_resp { /* * IO96B instance specific information * - * @size: Memory size * @io96b_csr_addr: IO96B instance CSR address * @cal_status: IO96B instance calibration status * @mb_ctrl: IOSSM mailbox required information */ struct io96b_instance { - u16 size; phys_addr_t io96b_csr_addr; bool cal_status; struct io96b_mb_ctrl mb_ctrl; @@ -102,6 +105,7 @@ struct io96b_instance { * @overall_cal_status: Overall calibration status for all IO96B instance(s) * @ddr_type: DDR memory type * @ecc_status: ECC enable status (false = disabled, true = enabled) + * @inline_ecc: Inline ECC or Out of Band ECC (false = Out of Band ECC, true = Inline ECC) * @overall_size: Total DDR memory size * @io96b[]: IO96B instance specific information * @ckgen_lock: IO96B GEN PLL lock (false = not locked, true = locked) @@ -115,7 +119,8 @@ struct io96b_info { bool overall_cal_status; const char *ddr_type; bool ecc_status; - u16 overall_size; + bool inline_ecc; + phys_size_t overall_size; struct io96b_instance io96b[MAX_IO96B_SUPPORTED]; bool ckgen_lock; u8 num_port; diff --git a/drivers/ddr/altera/sdram_agilex5.c b/drivers/ddr/altera/sdram_agilex5.c index 801a6bbab46..ee66c72157a 100644 --- a/drivers/ddr/altera/sdram_agilex5.c +++ b/drivers/ddr/altera/sdram_agilex5.c @@ -291,7 +291,14 @@ int sdram_mmr_init_full(struct udevice *dev) goto err; } - hw_size = (phys_size_t)io96b_ctrl->overall_size * SZ_1G / SZ_8; + ret = ecc_enable_status(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get ECC enabled status\n"); + + goto err; + } + + hw_size = io96b_ctrl->overall_size; /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, @@ -303,6 +310,9 @@ int sdram_mmr_init_full(struct udevice *dev) goto err; } + if (io96b_ctrl->inline_ecc) + hw_size = CALC_INLINE_ECC_HW_SIZE(hw_size); + if (gd->ram_size > hw_size) { printf("DDR: Warning: DRAM size from device tree (%lld MiB) exceeds\n", gd->ram_size >> 20); @@ -355,13 +365,6 @@ int sdram_mmr_init_full(struct udevice *dev) printf("%s: %lld MiB\n", io96b_ctrl->ddr_type, gd->ram_size >> 20); - ret = ecc_enable_status(io96b_ctrl); - if (ret) { - printf("DDR: Failed to get ECC enabled status\n"); - - goto err; - } - /* Is HPS cold or warm reset? If yes, Skip full memory initialization if ECC * enabled to preserve memory content */ diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index c8c9211adce..27fbe80ed41 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -185,35 +185,51 @@ void sdram_init_ecc_bits(struct bd_info *bd) void sdram_size_check(struct bd_info *bd) { phys_size_t total_ram_check = 0; - phys_size_t ram_check = 0; - phys_addr_t start = 0; - phys_size_t size, remaining_size; int bank; /* Sanity check ensure correct SDRAM size specified */ debug("DDR: Running SDRAM size sanity check\n"); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + phys_size_t ram_check = 0; + phys_addr_t start = 0; + phys_size_t remaining_size; + start = bd->bi_dram[bank].start; remaining_size = bd->bi_dram[bank].size; + debug("Checking bank %d: start=0x%llx, size=0x%llx\n", + bank, start, remaining_size); + while (ram_check < bd->bi_dram[bank].size) { - size = min((phys_addr_t)SZ_1G, - (phys_addr_t)remaining_size); - - /* - * Ensure the size is power of two, this is requirement - * to run get_ram_size() / memory test - */ - if (size != 0 && ((size & (size - 1)) == 0)) { - ram_check += get_ram_size((void *) - (start + ram_check), size); - remaining_size = bd->bi_dram[bank].size - - ram_check; - } else { - puts("DDR: Memory test requires SDRAM size "); - puts("in power of two!\n"); + phys_size_t size, test_size, detected_size; + + size = min((phys_addr_t)SZ_1G, (phys_addr_t)remaining_size); + + if (size < SZ_8) { + puts("Invalid size: Memory size required to be multiple\n"); + puts("of 64-Bit word!\n"); hang(); } + + /* Adjust size to the nearest power of two to support get_ram_size() */ + test_size = SZ_8; + + while (test_size * 2 <= size) + test_size *= 2; + + debug("Testing memory at 0x%llx with size 0x%llx\n", + start + ram_check, test_size); + detected_size = get_ram_size((void *)(start + ram_check), test_size); + + if (detected_size != test_size) { + debug("Detected size 0x%llx doesn’t match the test size 0x%llx!\n", + detected_size, test_size); + puts("Memory testing failed!\n"); + hang(); + } + + ram_check += detected_size; + remaining_size = bd->bi_dram[bank].size - ram_check; } total_ram_check += ram_check; @@ -249,7 +265,7 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat) DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw)); - size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) & + size *= ((phys_size_t)2 << (hmc_ecc_readl(plat, DDRIOCTRL) & DDR_HMC_DDRIOCTRL_IOSIZE_MSK)); return size; diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 4b1b80d7abe..2940181e83e 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -5,6 +5,8 @@ * Copyright (C) 2018-2019 Xilinx, Inc. */ +#include <asm/arch/hardware.h> +#include <asm/io.h> #include <cpu_func.h> #include <dm.h> #include <dm/device_compat.h> @@ -169,6 +171,32 @@ unsigned int zynqmp_firmware_version(void) return pm_api_version; }; +#if defined(CONFIG_ARCH_VERSAL2) +int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value) +{ + *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_TX_RX_CFG_RDY); + return 0; +} + +int zynqmp_pm_ufs_sram_csr_read(u32 *value) +{ + *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR); + return 0; +} + +int zynqmp_pm_ufs_sram_csr_write(u32 *value) +{ + writel(*value, PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR); + return 0; +} + +int zynqmp_pm_ufs_cal_reg(u32 *value) +{ + *value = readl(PMXC_EFUSE_CACHE_BASE_ADDRESS + PMXC_UFS_CAL_1_OFFSET); + return 0; +} +#endif + int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value) { int ret; @@ -195,6 +223,52 @@ int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value) return ret; } +u32 zynqmp_pm_get_bootmode_reg(void) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_READ_REG); + if (ret) { + printf("%s: IOCTL_READ_REG is not supported failed with error code: %d\n" + , __func__, ret); + return 0; + } + + ret = xilinx_pm_request(PM_IOCTL, CRP_BOOT_MODE_REG_NODE, IOCTL_READ_REG, + CRP_BOOT_MODE_REG_OFFSET, 0, ret_payload); + if (ret) { + printf("%s: node 0x%x: get_bootmode 0x%x failed\n", + __func__, CRP_BOOT_MODE_REG_NODE, CRP_BOOT_MODE_REG_OFFSET); + return 0; + } + + return ret_payload[1]; +} + +u32 zynqmp_pm_get_pmc_multi_boot_reg(void) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_READ_REG); + if (ret) { + printf("%s: IOCTL_READ_REG is not supported failed with error code: %d\n" + , __func__, ret); + return 0; + } + + ret = xilinx_pm_request(PM_IOCTL, PM_REG_PMC_GLOBAL_NODE, IOCTL_READ_REG, + PMC_MULTI_BOOT_MODE_REG_OFFSET, 0, ret_payload); + if (ret) { + printf("%s: node 0x%x: get_bootmode 0x%x failed\n", + __func__, PM_REG_PMC_GLOBAL_NODE, PMC_MULTI_BOOT_MODE_REG_OFFSET); + return 0; + } + + return ret_payload[1]; +} + int zynqmp_pm_feature(const u32 api_id) { int ret; diff --git a/drivers/firmware/scmi/sandbox-scmi_devices.c b/drivers/firmware/scmi/sandbox-scmi_devices.c index 9f253b0fd40..96c2922b067 100644 --- a/drivers/firmware/scmi/sandbox-scmi_devices.c +++ b/drivers/firmware/scmi/sandbox-scmi_devices.c @@ -163,5 +163,4 @@ U_BOOT_DRIVER(sandbox_scmi_devices) = { .priv_auto = sizeof(struct sandbox_scmi_device_priv), .remove = sandbox_scmi_devices_remove, .probe = sandbox_scmi_devices_probe, - .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF, }; diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index ae06f0123a0..64fda3a307c 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -12,6 +12,10 @@ /* * Altera FPGA support */ +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#include <asm/arch/misc.h> +#endif #include <errno.h> #include <ACEX1K.h> #include <log.h> @@ -47,6 +51,43 @@ static const struct altera_fpga { #endif }; +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +int fpga_is_partial_data(int devnum, size_t img_len) +{ + /* + * The FPGA data (full or partial) is checked by + * the SDM hardware, for Intel SDM Mailbox based + * devices. Hence always return full bitstream. + * + * For Cyclone V and Arria 10 family, the bitstream + * type parameter is not handled by the driver. + */ + return 0; +} + +int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype) +{ + int ret_val; + int flags = 0; + + ret_val = fpga_load(devnum, (void *)fpgadata, size, bstype, flags); + + /* + * Enable the HPS to FPGA bridges when FPGA load is completed + * successfully. This is to ensure the FPGA is accessible + * by the HPS. + */ + if (!ret_val) { + printf("Enable FPGA bridges\n"); + do_bridge_reset(1, ~0); + } + + return ret_val; +} +#endif + static int altera_validate(Altera_desc *desc, const char *fn) { if (!desc) { diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index 1957e8dcaca..d691f135e89 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -41,8 +41,15 @@ static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize, buf_lo = lower_32_bits(bin_buf); buf_hi = upper_32_bits(bin_buf); - ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, - buf_hi, 0, ret_payload); + + if (desc->family == xilinx_versal2) { + ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_hi, + buf_lo, 0, ret_payload); + } else { + ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, + buf_hi, 0, ret_payload); + } + if (ret) printf("PL FPGA LOAD failed with err: 0x%08x\n", ret); diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 46e76385961..146bc621c7e 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -510,6 +510,15 @@ config SYS_I2C_OMAP24XX help Add support for the OMAP2+ I2C driver. +config SYS_I2C_OMAP24XX_REPEATED_START + bool "Enable I2C repeated start" + depends on SYS_I2C_OMAP24XX + default y if ARCH_K3 + help + Enable support for repeated start. Updates driver defaults to not + send a Stop condition and issue Repeated Start (Sr) for subsequent + i2c msgs. + config SYS_I2C_RCAR_I2C bool "Renesas R-Car I2C driver" depends on (RCAR_GEN2 || RCAR_64) && DM_I2C diff --git a/drivers/i2c/mtk_i2c.c b/drivers/i2c/mtk_i2c.c index 3450177741a..55381dbeced 100644 --- a/drivers/i2c/mtk_i2c.c +++ b/drivers/i2c/mtk_i2c.c @@ -143,7 +143,6 @@ static const uint mt_i2c_regs_v1[] = { [REG_RSV_DEBUG] = 0x44, [REG_HS] = 0x48, [REG_SOFTRESET] = 0x50, - [REG_SOFTRESET] = 0x50, [REG_DCM_EN] = 0x54, [REG_DEBUGSTAT] = 0x64, [REG_DEBUGCTRL] = 0x68, @@ -879,7 +878,7 @@ static const struct udevice_id mtk_i2c_ids[] = { }, { .compatible = "mediatek,mt8518-i2c", .data = (ulong)&mt8518_soc_data, - } + }, {} }; U_BOOT_DRIVER(mtk_i2c) = { diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index ebe472e20cd..a6361d3d17d 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -535,12 +535,16 @@ pr_exit: return res; } +#if !CONFIG_IS_ENABLED(DM_I2C) +/* + * The legacy I2C functions. These need to get removed once + * all users of this driver are converted to DM. + */ + /* * i2c_read: Function now uses a single I2C read transaction with bulk transfer * of the requested number of bytes (note that the 'i2c md' command - * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is - * defined in the board config header, this transaction shall be with - * Repeated Start (Sr) between the address and data phases; otherwise + * limits this to 16 bytes anyway). * Stop-Start (P-S) shall be used (some I2C chips do require a P-S). * The address (reg offset) may be 0, 1 or 2 bytes long. * Function now reads correctly from chips that return more than one @@ -608,16 +612,10 @@ static int __omap24_i2c_read(void __iomem *i2c_base, int ip_rev, int waitdelay, if (alen) { /* Must write reg offset first */ -#ifdef CONFIG_I2C_REPEATED_START - /* No stop bit, use Repeated Start (Sr) */ - omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | - I2C_CON_STT | I2C_CON_TRX, OMAP_I2C_CON_REG); -#else /* Stop - Start (P-S) */ omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP | I2C_CON_TRX, OMAP_I2C_CON_REG); -#endif /* Send register offset */ while (1) { status = wait_for_event(i2c_base, ip_rev, waitdelay); @@ -836,11 +834,6 @@ wr_exit: return i2c_error; } -#if !CONFIG_IS_ENABLED(DM_I2C) -/* - * The legacy I2C functions. These need to get removed once - * all users of this driver are converted to DM. - */ static void __iomem *omap24_get_base(struct i2c_adapter *adap) { switch (adap->hwadapnr) { @@ -971,28 +964,140 @@ U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe, #else /* CONFIG_DM_I2C */ +static int __omap24_i2c_xfer_msg(void __iomem *i2c_base, int ip_rev, int waitdelay, + uchar chip, uchar *buffer, int len, u16 i2c_con_reg) +{ + int i; + u16 status; + int i2c_error = 0; + int timeout = I2C_TIMEOUT; + + if (len < 0) { + printf("%s: data len < 0\n", __func__); + return -EINVAL; + } + + if (!buffer) { + printf("%s: NULL pointer passed\n", __func__); + return -EINVAL; + } + + if (!(i2c_con_reg & I2C_CON_EN)) { + printf("%s: I2C_CON_EN not set\n", __func__); + return -EINVAL; + } + + /* Set slave address */ + omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG); + /* Read/Write len bytes data */ + omap_i2c_write_reg(i2c_base, ip_rev, len, OMAP_I2C_CNT_REG); + /* Configure the I2C_CON register */ + omap_i2c_write_reg(i2c_base, ip_rev, i2c_con_reg, OMAP_I2C_CON_REG); + + /* read/write data bytewise */ + for (i = 0; i < len; i++) { + status = wait_for_event(i2c_base, ip_rev, waitdelay); + /* Ignore I2C_STAT_RRDY in transmitter mode */ + if (i2c_con_reg & I2C_CON_TRX) + status &= ~I2C_STAT_RRDY; + else + status &= ~I2C_STAT_XRDY; + + /* Try to identify bus that is not padconf'd for I2C */ + if (status == I2C_STAT_XRDY) { + i2c_error = -EREMOTEIO; + printf("%s: pads on bus probably not configured (status=0x%x)\n", + __func__, status); + goto xfer_exit; + } + if (status == 0 || (status & I2C_STAT_NACK)) { + i2c_error = -EREMOTEIO; + printf("%s: error waiting for ACK (status=0x%x)\n", + __func__, status); + goto xfer_exit; + } + if (status & I2C_STAT_XRDY) { + /* Transmit data */ + omap_i2c_write_reg(i2c_base, ip_rev, + buffer[i], OMAP_I2C_DATA_REG); + omap_i2c_write_reg(i2c_base, ip_rev, + I2C_STAT_XRDY, OMAP_I2C_STAT_REG); + } + if (status & I2C_STAT_RRDY) { + /* Receive data */ + *buffer++ = omap_i2c_read_reg(i2c_base, ip_rev, + OMAP_I2C_DATA_REG); + omap_i2c_write_reg(i2c_base, ip_rev, + I2C_STAT_RRDY, OMAP_I2C_STAT_REG); + } + } + + /* + * poll ARDY bit for making sure that last byte really has been + * transferred on the bus. + */ + do { + status = wait_for_event(i2c_base, ip_rev, waitdelay); + } while (!(status & I2C_STAT_ARDY) && timeout--); + if (timeout <= 0) { + printf("%s: timed out on last byte!\n", __func__); + i2c_error = -EREMOTEIO; + goto xfer_exit; + } else { + omap_i2c_write_reg(i2c_base, ip_rev, I2C_STAT_ARDY, OMAP_I2C_STAT_REG); + } + + /* If Stop bit set, flush FIFO. */ + if (i2c_con_reg & I2C_CON_STP) + goto xfer_exit; + + return 0; + +xfer_exit: + flush_fifo(i2c_base, ip_rev); + omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); + return i2c_error; +} + static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) { struct omap_i2c *priv = dev_get_priv(bus); int ret; + u16 i2c_con_reg = 0; - debug("i2c_xfer: %d messages\n", nmsgs); - for (; nmsgs > 0; nmsgs--, msg++) { - debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); - if (msg->flags & I2C_M_RD) { - ret = __omap24_i2c_read(priv->regs, priv->ip_rev, - priv->waitdelay, - msg->addr, 0, 0, msg->buf, - msg->len); - } else { - ret = __omap24_i2c_write(priv->regs, priv->ip_rev, - priv->waitdelay, - msg->addr, 0, 0, msg->buf, - msg->len); - } + debug("%s: %d messages\n", __func__, nmsgs); + for (int i = 0; i < nmsgs; i++, msg++) { + /* + * If previous msg sent a Stop or if this is the first msg + * Wait until bus not busy + */ + if ((i2c_con_reg & I2C_CON_STP) || (i == 0)) + if (wait_for_bb(priv->regs, priv->ip_rev, priv->waitdelay)) + return -EREMOTEIO; + + /* Set Controller mode with Start bit */ + i2c_con_reg = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT; + /* Set Transmitter/Receiver mode if it is a write/read msg */ + if (msg->flags & I2C_M_RD) + i2c_con_reg &= ~I2C_CON_TRX; + else + i2c_con_reg |= I2C_CON_TRX; + /* Send Stop condition (P) by default */ + if (!IS_ENABLED(CONFIG_SYS_I2C_OMAP24XX_REPEATED_START)) + i2c_con_reg |= I2C_CON_STP; + /* Send Stop if explicitly requested or if this is the last msg */ + if ((msg->flags & I2C_M_STOP) || (i == nmsgs - 1)) + i2c_con_reg |= I2C_CON_STP; + + debug("%s: chip=0x%x, len=0x%x, i2c_con_reg=0x%x\n", + __func__, msg->addr, msg->len, i2c_con_reg); + + ret = __omap24_i2c_xfer_msg(priv->regs, priv->ip_rev, priv->waitdelay, + msg->addr, msg->buf, msg->len, + i2c_con_reg); if (ret) { - debug("i2c_write: error sending\n"); - return -EREMOTEIO; + printf("%s: errored out at msg %d: %d\n", __func__, i, ret); + return ret; } } diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 3ea665d974d..38867f30a7e 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -871,7 +871,7 @@ config FTSDC010_SDIO config MMC_MTK bool "MediaTek SD/MMC Card Interface support" - depends on ARCH_MEDIATEK || ARCH_MTMIPS + depends on ARCH_MEDIATEK || ARCH_MTMIPS || ARCH_AIROHA depends on OF_CONTROL help This selects the MediaTek(R) Secure digital and Multimedia card Interface. diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index f5ddfbf4b83..3a1e7e18736 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -941,6 +941,19 @@ spinand_select_op_variant(struct spinand_device *spinand, return NULL; } +static int spinand_setup_slave(struct spinand_device *spinand, + const struct spinand_info *spinand_info) +{ + struct spi_slave *slave = spinand->slave; + struct udevice *bus = slave->dev->parent; + struct dm_spi_ops *ops = spi_get_ops(bus); + + if (!ops->setup_for_spinand) + return 0; + + return ops->setup_for_spinand(slave, spinand_info); +} + /** * spinand_match_and_init() - Try to find a match between a device ID and an * entry in a spinand_info table @@ -964,6 +977,7 @@ int spinand_match_and_init(struct spinand_device *spinand, u8 *id = spinand->id.data; struct nand_device *nand = spinand_to_nand(spinand); unsigned int i; + int ret; for (i = 0; i < table_size; i++) { const struct spinand_info *info = &table[i]; @@ -975,6 +989,10 @@ int spinand_match_and_init(struct spinand_device *spinand, if (memcmp(id + 1, info->devid.id, info->devid.len)) continue; + ret = spinand_setup_slave(spinand, info); + if (ret) + return ret; + nand->memorg = table[i].memorg; nand->eccreq = table[i].eccreq; spinand->eccinfo = table[i].eccinfo; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 3db784faedd..a0a7890bd26 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -122,6 +122,14 @@ config AG7XXX This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is present in the Atheros AR7xxx, AR9xxx and QCA9xxx MIPS chips. +config AIROHA_ETH + bool "Airoha Ethernet QDMA Driver" + depends on ARCH_AIROHA + select PHYLIB + select DM_RESET + help + This Driver support Airoha Ethernet QDMA Driver + Say Y to enable support for the Airoha Ethernet QDMA. config ALTERA_TSE bool "Altera Triple-Speed Ethernet MAC support" diff --git a/drivers/net/Makefile b/drivers/net/Makefile index d919d437c08..3244d39036d 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o +obj-$(CONFIG_AIROHA_ETH) += airoha_eth.o obj-$(CONFIG_ALTERA_TSE) += altera_tse.o obj-$(CONFIG_ASPEED_MDIO) += aspeed_mdio.o obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c new file mode 100644 index 00000000000..7e35e1fd41d --- /dev/null +++ b/drivers/net/airoha_eth.c @@ -0,0 +1,948 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Based on Linux airoha_eth.c majorly rewritten + * and simplified for U-Boot usage for single TX/RX ring. + * + * Copyright (c) 2024 AIROHA Inc + * Author: Lorenzo Bianconi <lorenzo@kernel.org> + * Christian Marangi <ansuelsmth@gmail.org> + */ + +#include <dm.h> +#include <dm/devres.h> +#include <mapmem.h> +#include <net.h> +#include <regmap.h> +#include <reset.h> +#include <syscon.h> +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/time.h> + +#define AIROHA_MAX_NUM_GDM_PORTS 1 +#define AIROHA_MAX_NUM_QDMA 1 +#define AIROHA_MAX_NUM_RSTS 3 +#define AIROHA_MAX_NUM_XSI_RSTS 4 + +#define AIROHA_MAX_PACKET_SIZE 2048 +#define AIROHA_NUM_TX_RING 1 +#define AIROHA_NUM_RX_RING 1 +#define AIROHA_NUM_TX_IRQ 1 +#define HW_DSCP_NUM 32 +#define IRQ_QUEUE_LEN 1 +#define TX_DSCP_NUM 16 +#define RX_DSCP_NUM PKTBUFSRX + +/* SCU */ +#define SCU_SHARE_FEMEM_SEL 0x958 + +/* SWITCH */ +#define SWITCH_MFC 0x10 +#define SWITCH_BC_FFP GENMASK(31, 24) +#define SWITCH_UNM_FFP GENMASK(23, 16) +#define SWITCH_UNU_FFP GENMASK(15, 8) +#define SWITCH_PMCR(_n) 0x3000 + ((_n) * 0x100) +#define SWITCH_IPG_CFG GENMASK(19, 18) +#define SWITCH_IPG_CFG_NORMAL FIELD_PREP(SWITCH_IPG_CFG, 0x0) +#define SWITCH_IPG_CFG_SHORT FIELD_PREP(SWITCH_IPG_CFG, 0x1) +#define SWITCH_IPG_CFG_SHRINK FIELD_PREP(SWITCH_IPG_CFG, 0x2) +#define SWITCH_MAC_MODE BIT(16) +#define SWITCH_FORCE_MODE BIT(15) +#define SWITCH_MAC_TX_EN BIT(14) +#define SWITCH_MAC_RX_EN BIT(13) +#define SWITCH_BKOFF_EN BIT(9) +#define SWITCH_BKPR_EN BIT(8) +#define SWITCH_FORCE_RX_FC BIT(5) +#define SWITCH_FORCE_TX_FC BIT(4) +#define SWITCH_FORCE_SPD GENMASK(3, 2) +#define SWITCH_FORCE_SPD_10 FIELD_PREP(SWITCH_FORCE_SPD, 0x0) +#define SWITCH_FORCE_SPD_100 FIELD_PREP(SWITCH_FORCE_SPD, 0x1) +#define SWITCH_FORCE_SPD_1000 FIELD_PREP(SWITCH_FORCE_SPD, 0x2) +#define SWITCH_FORCE_DPX BIT(1) +#define SWITCH_FORCE_LNK BIT(0) +#define SWITCH_SMACCR0 0x30e4 +#define SMACCR0_MAC2 GENMASK(31, 24) +#define SMACCR0_MAC3 GENMASK(23, 16) +#define SMACCR0_MAC4 GENMASK(15, 8) +#define SMACCR0_MAC5 GENMASK(7, 0) +#define SWITCH_SMACCR1 0x30e8 +#define SMACCR1_MAC0 GENMASK(15, 8) +#define SMACCR1_MAC1 GENMASK(7, 0) +#define SWITCH_PHY_POLL 0x7018 +#define SWITCH_PHY_AP_EN GENMASK(30, 24) +#define SWITCH_EEE_POLL_EN GENMASK(22, 16) +#define SWITCH_PHY_PRE_EN BIT(15) +#define SWITCH_PHY_END_ADDR GENMASK(12, 8) +#define SWITCH_PHY_ST_ADDR GENMASK(4, 0) + +/* FE */ +#define PSE_BASE 0x0100 +#define CSR_IFC_BASE 0x0200 +#define CDM1_BASE 0x0400 +#define GDM1_BASE 0x0500 +#define PPE1_BASE 0x0c00 + +#define CDM2_BASE 0x1400 +#define GDM2_BASE 0x1500 + +#define GDM3_BASE 0x1100 +#define GDM4_BASE 0x2500 + +#define GDM_BASE(_n) \ + ((_n) == 4 ? GDM4_BASE : \ + (_n) == 3 ? GDM3_BASE : \ + (_n) == 2 ? GDM2_BASE : GDM1_BASE) + +#define REG_GDM_FWD_CFG(_n) GDM_BASE(_n) +#define GDM_DROP_CRC_ERR BIT(23) +#define GDM_IP4_CKSUM BIT(22) +#define GDM_TCP_CKSUM BIT(21) +#define GDM_UDP_CKSUM BIT(20) +#define GDM_UCFQ_MASK GENMASK(15, 12) +#define GDM_BCFQ_MASK GENMASK(11, 8) +#define GDM_MCFQ_MASK GENMASK(7, 4) +#define GDM_OCFQ_MASK GENMASK(3, 0) + +/* QDMA */ +#define REG_QDMA_GLOBAL_CFG 0x0004 +#define GLOBAL_CFG_RX_2B_OFFSET_MASK BIT(31) +#define GLOBAL_CFG_DMA_PREFERENCE_MASK GENMASK(30, 29) +#define GLOBAL_CFG_CPU_TXR_RR_MASK BIT(28) +#define GLOBAL_CFG_DSCP_BYTE_SWAP_MASK BIT(27) +#define GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK BIT(26) +#define GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK BIT(25) +#define GLOBAL_CFG_OAM_MODIFY_MASK BIT(24) +#define GLOBAL_CFG_RESET_MASK BIT(23) +#define GLOBAL_CFG_RESET_DONE_MASK BIT(22) +#define GLOBAL_CFG_MULTICAST_EN_MASK BIT(21) +#define GLOBAL_CFG_IRQ1_EN_MASK BIT(20) +#define GLOBAL_CFG_IRQ0_EN_MASK BIT(19) +#define GLOBAL_CFG_LOOPCNT_EN_MASK BIT(18) +#define GLOBAL_CFG_RD_BYPASS_WR_MASK BIT(17) +#define GLOBAL_CFG_QDMA_LOOPBACK_MASK BIT(16) +#define GLOBAL_CFG_LPBK_RXQ_SEL_MASK GENMASK(13, 8) +#define GLOBAL_CFG_CHECK_DONE_MASK BIT(7) +#define GLOBAL_CFG_TX_WB_DONE_MASK BIT(6) +#define GLOBAL_CFG_MAX_ISSUE_NUM_MASK GENMASK(5, 4) +#define GLOBAL_CFG_RX_DMA_BUSY_MASK BIT(3) +#define GLOBAL_CFG_RX_DMA_EN_MASK BIT(2) +#define GLOBAL_CFG_TX_DMA_BUSY_MASK BIT(1) +#define GLOBAL_CFG_TX_DMA_EN_MASK BIT(0) + +#define REG_FWD_DSCP_BASE 0x0010 +#define REG_FWD_BUF_BASE 0x0014 + +#define REG_HW_FWD_DSCP_CFG 0x0018 +#define HW_FWD_DSCP_PAYLOAD_SIZE_MASK GENMASK(29, 28) +#define HW_FWD_DSCP_SCATTER_LEN_MASK GENMASK(17, 16) +#define HW_FWD_DSCP_MIN_SCATTER_LEN_MASK GENMASK(15, 0) + +#define REG_INT_STATUS(_n) \ + (((_n) == 4) ? 0x0730 : \ + ((_n) == 3) ? 0x0724 : \ + ((_n) == 2) ? 0x0720 : \ + ((_n) == 1) ? 0x0024 : 0x0020) + +#define REG_TX_IRQ_BASE(_n) ((_n) ? 0x0048 : 0x0050) + +#define REG_TX_IRQ_CFG(_n) ((_n) ? 0x004c : 0x0054) +#define TX_IRQ_THR_MASK GENMASK(27, 16) +#define TX_IRQ_DEPTH_MASK GENMASK(11, 0) + +#define REG_IRQ_CLEAR_LEN(_n) ((_n) ? 0x0064 : 0x0058) +#define IRQ_CLEAR_LEN_MASK GENMASK(7, 0) + +#define REG_TX_RING_BASE(_n) \ + (((_n) < 8) ? 0x0100 + ((_n) << 5) : 0x0b00 + (((_n) - 8) << 5)) + +#define REG_TX_CPU_IDX(_n) \ + (((_n) < 8) ? 0x0108 + ((_n) << 5) : 0x0b08 + (((_n) - 8) << 5)) + +#define TX_RING_CPU_IDX_MASK GENMASK(15, 0) + +#define REG_TX_DMA_IDX(_n) \ + (((_n) < 8) ? 0x010c + ((_n) << 5) : 0x0b0c + (((_n) - 8) << 5)) + +#define TX_RING_DMA_IDX_MASK GENMASK(15, 0) + +#define IRQ_RING_IDX_MASK GENMASK(20, 16) +#define IRQ_DESC_IDX_MASK GENMASK(15, 0) + +#define REG_RX_RING_BASE(_n) \ + (((_n) < 16) ? 0x0200 + ((_n) << 5) : 0x0e00 + (((_n) - 16) << 5)) + +#define REG_RX_RING_SIZE(_n) \ + (((_n) < 16) ? 0x0204 + ((_n) << 5) : 0x0e04 + (((_n) - 16) << 5)) + +#define RX_RING_THR_MASK GENMASK(31, 16) +#define RX_RING_SIZE_MASK GENMASK(15, 0) + +#define REG_RX_CPU_IDX(_n) \ + (((_n) < 16) ? 0x0208 + ((_n) << 5) : 0x0e08 + (((_n) - 16) << 5)) + +#define RX_RING_CPU_IDX_MASK GENMASK(15, 0) + +#define REG_RX_DMA_IDX(_n) \ + (((_n) < 16) ? 0x020c + ((_n) << 5) : 0x0e0c + (((_n) - 16) << 5)) + +#define REG_RX_DELAY_INT_IDX(_n) \ + (((_n) < 16) ? 0x0210 + ((_n) << 5) : 0x0e10 + (((_n) - 16) << 5)) + +#define RX_DELAY_INT_MASK GENMASK(15, 0) + +#define RX_RING_DMA_IDX_MASK GENMASK(15, 0) + +#define REG_LMGR_INIT_CFG 0x1000 +#define LMGR_INIT_START BIT(31) +#define LMGR_SRAM_MODE_MASK BIT(30) +#define HW_FWD_PKTSIZE_OVERHEAD_MASK GENMASK(27, 20) +#define HW_FWD_DESC_NUM_MASK GENMASK(16, 0) + +/* CTRL */ +#define QDMA_DESC_DONE_MASK BIT(31) +#define QDMA_DESC_DROP_MASK BIT(30) /* tx: drop - rx: overflow */ +#define QDMA_DESC_MORE_MASK BIT(29) /* more SG elements */ +#define QDMA_DESC_DEI_MASK BIT(25) +#define QDMA_DESC_NO_DROP_MASK BIT(24) +#define QDMA_DESC_LEN_MASK GENMASK(15, 0) +/* DATA */ +#define QDMA_DESC_NEXT_ID_MASK GENMASK(15, 0) +/* TX MSG0 */ +#define QDMA_ETH_TXMSG_MIC_IDX_MASK BIT(30) +#define QDMA_ETH_TXMSG_SP_TAG_MASK GENMASK(29, 14) +#define QDMA_ETH_TXMSG_ICO_MASK BIT(13) +#define QDMA_ETH_TXMSG_UCO_MASK BIT(12) +#define QDMA_ETH_TXMSG_TCO_MASK BIT(11) +#define QDMA_ETH_TXMSG_TSO_MASK BIT(10) +#define QDMA_ETH_TXMSG_FAST_MASK BIT(9) +#define QDMA_ETH_TXMSG_OAM_MASK BIT(8) +#define QDMA_ETH_TXMSG_CHAN_MASK GENMASK(7, 3) +#define QDMA_ETH_TXMSG_QUEUE_MASK GENMASK(2, 0) +/* TX MSG1 */ +#define QDMA_ETH_TXMSG_NO_DROP BIT(31) +#define QDMA_ETH_TXMSG_METER_MASK GENMASK(30, 24) /* 0x7f no meters */ +#define QDMA_ETH_TXMSG_FPORT_MASK GENMASK(23, 20) +#define QDMA_ETH_TXMSG_NBOQ_MASK GENMASK(19, 15) +#define QDMA_ETH_TXMSG_HWF_MASK BIT(14) +#define QDMA_ETH_TXMSG_HOP_MASK BIT(13) +#define QDMA_ETH_TXMSG_PTP_MASK BIT(12) +#define QDMA_ETH_TXMSG_ACNT_G1_MASK GENMASK(10, 6) /* 0x1f do not count */ +#define QDMA_ETH_TXMSG_ACNT_G0_MASK GENMASK(5, 0) /* 0x3f do not count */ + +/* RX MSG1 */ +#define QDMA_ETH_RXMSG_DEI_MASK BIT(31) +#define QDMA_ETH_RXMSG_IP6_MASK BIT(30) +#define QDMA_ETH_RXMSG_IP4_MASK BIT(29) +#define QDMA_ETH_RXMSG_IP4F_MASK BIT(28) +#define QDMA_ETH_RXMSG_L4_VALID_MASK BIT(27) +#define QDMA_ETH_RXMSG_L4F_MASK BIT(26) +#define QDMA_ETH_RXMSG_SPORT_MASK GENMASK(25, 21) +#define QDMA_ETH_RXMSG_CRSN_MASK GENMASK(20, 16) +#define QDMA_ETH_RXMSG_PPE_ENTRY_MASK GENMASK(15, 0) + +struct airoha_qdma_desc { + __le32 rsv; + __le32 ctrl; + __le32 addr; + __le32 data; + __le32 msg0; + __le32 msg1; + __le32 msg2; + __le32 msg3; +}; + +struct airoha_qdma_fwd_desc { + __le32 addr; + __le32 ctrl0; + __le32 ctrl1; + __le32 ctrl2; + __le32 msg0; + __le32 msg1; + __le32 rsv0; + __le32 rsv1; +}; + +struct airoha_queue { + struct airoha_qdma_desc *desc; + u16 head; + + int ndesc; +}; + +struct airoha_tx_irq_queue { + struct airoha_qdma *qdma; + + int size; + u32 *q; +}; + +struct airoha_qdma { + struct airoha_eth *eth; + void __iomem *regs; + + struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ]; + + struct airoha_queue q_tx[AIROHA_NUM_TX_RING]; + struct airoha_queue q_rx[AIROHA_NUM_RX_RING]; + + /* descriptor and packet buffers for qdma hw forward */ + struct { + void *desc; + void *q; + } hfwd; +}; + +struct airoha_gdm_port { + struct airoha_qdma *qdma; + int id; +}; + +struct airoha_eth { + void __iomem *fe_regs; + void __iomem *switch_regs; + + struct reset_ctl_bulk rsts; + struct reset_ctl_bulk xsi_rsts; + + struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA]; + struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS]; +}; + +static u32 airoha_rr(void __iomem *base, u32 offset) +{ + return readl(base + offset); +} + +static void airoha_wr(void __iomem *base, u32 offset, u32 val) +{ + writel(val, base + offset); +} + +static u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val) +{ + val |= (airoha_rr(base, offset) & ~mask); + airoha_wr(base, offset, val); + + return val; +} + +#define airoha_fe_rr(eth, offset) \ + airoha_rr((eth)->fe_regs, (offset)) +#define airoha_fe_wr(eth, offset, val) \ + airoha_wr((eth)->fe_regs, (offset), (val)) +#define airoha_fe_rmw(eth, offset, mask, val) \ + airoha_rmw((eth)->fe_regs, (offset), (mask), (val)) +#define airoha_fe_set(eth, offset, val) \ + airoha_rmw((eth)->fe_regs, (offset), 0, (val)) +#define airoha_fe_clear(eth, offset, val) \ + airoha_rmw((eth)->fe_regs, (offset), (val), 0) + +#define airoha_qdma_rr(qdma, offset) \ + airoha_rr((qdma)->regs, (offset)) +#define airoha_qdma_wr(qdma, offset, val) \ + airoha_wr((qdma)->regs, (offset), (val)) +#define airoha_qdma_rmw(qdma, offset, mask, val) \ + airoha_rmw((qdma)->regs, (offset), (mask), (val)) +#define airoha_qdma_set(qdma, offset, val) \ + airoha_rmw((qdma)->regs, (offset), 0, (val)) +#define airoha_qdma_clear(qdma, offset, val) \ + airoha_rmw((qdma)->regs, (offset), (val), 0) + +#define airoha_switch_wr(eth, offset, val) \ + airoha_wr((eth)->switch_regs, (offset), (val)) + +static void airoha_fe_maccr_init(struct airoha_eth *eth) +{ + int p; + + for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) { + /* Disable any kind of CRC drop or offload */ + airoha_fe_wr(eth, REG_GDM_FWD_CFG(p), 0); + } +} + +static int airoha_fe_init(struct airoha_eth *eth) +{ + airoha_fe_maccr_init(eth); + + return 0; +} + +static void airoha_qdma_reset_rx_desc(struct airoha_queue *q, int index, + uchar *rx_packet) +{ + struct airoha_qdma_desc *desc; + u32 val; + + desc = &q->desc[index]; + index = (index + 1) % q->ndesc; + + dma_map_single(rx_packet, PKTSIZE_ALIGN, DMA_TO_DEVICE); + + WRITE_ONCE(desc->msg0, cpu_to_le32(0)); + WRITE_ONCE(desc->msg1, cpu_to_le32(0)); + WRITE_ONCE(desc->msg2, cpu_to_le32(0)); + WRITE_ONCE(desc->msg3, cpu_to_le32(0)); + WRITE_ONCE(desc->addr, cpu_to_le32(virt_to_phys(rx_packet))); + WRITE_ONCE(desc->data, cpu_to_le32(index)); + val = FIELD_PREP(QDMA_DESC_LEN_MASK, PKTSIZE_ALIGN); + WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); + + dma_map_single(desc, sizeof(*desc), DMA_TO_DEVICE); +} + +static void airoha_qdma_init_rx_desc(struct airoha_queue *q) +{ + int i; + + for (i = 0; i < q->ndesc; i++) + airoha_qdma_reset_rx_desc(q, i, net_rx_packets[i]); +} + +static int airoha_qdma_init_rx_queue(struct airoha_queue *q, + struct airoha_qdma *qdma, int ndesc) +{ + int qid = q - &qdma->q_rx[0]; + unsigned long dma_addr; + + q->ndesc = ndesc; + q->head = 0; + + q->desc = dma_alloc_coherent(q->ndesc * sizeof(*q->desc), &dma_addr); + if (!q->desc) + return -ENOMEM; + + memset(q->desc, 0, q->ndesc * sizeof(*q->desc)); + dma_map_single(q->desc, q->ndesc * sizeof(*q->desc), DMA_TO_DEVICE); + + airoha_qdma_wr(qdma, REG_RX_RING_BASE(qid), dma_addr); + airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), + RX_RING_SIZE_MASK, + FIELD_PREP(RX_RING_SIZE_MASK, ndesc)); + + airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), RX_RING_THR_MASK, + FIELD_PREP(RX_RING_THR_MASK, 0)); + airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK, + FIELD_PREP(RX_RING_CPU_IDX_MASK, q->ndesc - 1)); + airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK, + FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head)); + + return 0; +} + +static int airoha_qdma_init_rx(struct airoha_qdma *qdma) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { + int err; + + err = airoha_qdma_init_rx_queue(&qdma->q_rx[i], qdma, + RX_DSCP_NUM); + if (err) + return err; + } + + return 0; +} + +static int airoha_qdma_init_tx_queue(struct airoha_queue *q, + struct airoha_qdma *qdma, int size) +{ + int qid = q - &qdma->q_tx[0]; + unsigned long dma_addr; + + q->ndesc = size; + q->head = 0; + + q->desc = dma_alloc_coherent(q->ndesc * sizeof(*q->desc), &dma_addr); + if (!q->desc) + return -ENOMEM; + + memset(q->desc, 0, q->ndesc * sizeof(*q->desc)); + dma_map_single(q->desc, q->ndesc * sizeof(*q->desc), DMA_TO_DEVICE); + + airoha_qdma_wr(qdma, REG_TX_RING_BASE(qid), dma_addr); + airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK, + FIELD_PREP(TX_RING_CPU_IDX_MASK, q->head)); + airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK, + FIELD_PREP(TX_RING_DMA_IDX_MASK, q->head)); + + return 0; +} + +static int airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue *irq_q, + struct airoha_qdma *qdma, int size) +{ + int id = irq_q - &qdma->q_tx_irq[0]; + unsigned long dma_addr; + + irq_q->q = dma_alloc_coherent(size * sizeof(u32), &dma_addr); + if (!irq_q->q) + return -ENOMEM; + + memset(irq_q->q, 0xffffffff, size * sizeof(u32)); + irq_q->size = size; + irq_q->qdma = qdma; + + dma_map_single(irq_q->q, size * sizeof(u32), DMA_TO_DEVICE); + + airoha_qdma_wr(qdma, REG_TX_IRQ_BASE(id), dma_addr); + airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_DEPTH_MASK, + FIELD_PREP(TX_IRQ_DEPTH_MASK, size)); + + return 0; +} + +static int airoha_qdma_init_tx(struct airoha_qdma *qdma) +{ + int i, err; + + for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { + err = airoha_qdma_tx_irq_init(&qdma->q_tx_irq[i], qdma, + IRQ_QUEUE_LEN); + if (err) + return err; + } + + for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { + err = airoha_qdma_init_tx_queue(&qdma->q_tx[i], qdma, + TX_DSCP_NUM); + if (err) + return err; + } + + return 0; +} + +static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma) +{ + unsigned long dma_addr; + u32 status; + int size; + + size = HW_DSCP_NUM * sizeof(struct airoha_qdma_fwd_desc); + qdma->hfwd.desc = dma_alloc_coherent(size, &dma_addr); + if (!qdma->hfwd.desc) + return -ENOMEM; + + memset(qdma->hfwd.desc, 0, size); + dma_map_single(qdma->hfwd.desc, size, DMA_TO_DEVICE); + + airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr); + + size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM; + qdma->hfwd.q = dma_alloc_coherent(size, &dma_addr); + if (!qdma->hfwd.q) + return -ENOMEM; + + memset(qdma->hfwd.q, 0, size); + dma_map_single(qdma->hfwd.q, size, DMA_TO_DEVICE); + + airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr); + + airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG, + HW_FWD_DSCP_PAYLOAD_SIZE_MASK | + HW_FWD_DSCP_MIN_SCATTER_LEN_MASK, + FIELD_PREP(HW_FWD_DSCP_PAYLOAD_SIZE_MASK, 0) | + FIELD_PREP(HW_FWD_DSCP_MIN_SCATTER_LEN_MASK, 1)); + airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG, + LMGR_INIT_START | LMGR_SRAM_MODE_MASK | + HW_FWD_DESC_NUM_MASK, + FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) | + LMGR_INIT_START); + + udelay(1000); + return read_poll_timeout(airoha_qdma_rr, status, + !(status & LMGR_INIT_START), USEC_PER_MSEC, + 30 * USEC_PER_MSEC, qdma, + REG_LMGR_INIT_CFG); +} + +static int airoha_qdma_hw_init(struct airoha_qdma *qdma) +{ + int i; + + /* clear pending irqs */ + for (i = 0; i < 2; i++) + airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff); + + airoha_qdma_wr(qdma, REG_QDMA_GLOBAL_CFG, + GLOBAL_CFG_CPU_TXR_RR_MASK | + GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK | + GLOBAL_CFG_IRQ0_EN_MASK | + GLOBAL_CFG_TX_WB_DONE_MASK | + FIELD_PREP(GLOBAL_CFG_MAX_ISSUE_NUM_MASK, 3)); + + /* disable qdma rx delay interrupt */ + for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { + if (!qdma->q_rx[i].ndesc) + continue; + + airoha_qdma_clear(qdma, REG_RX_DELAY_INT_IDX(i), + RX_DELAY_INT_MASK); + } + + return 0; +} + +static int airoha_qdma_init(struct udevice *dev, + struct airoha_eth *eth, + struct airoha_qdma *qdma) +{ + int err; + + qdma->eth = eth; + qdma->regs = dev_remap_addr_name(dev, "qdma0"); + if (IS_ERR(qdma->regs)) + return PTR_ERR(qdma->regs); + + err = airoha_qdma_init_rx(qdma); + if (err) + return err; + + err = airoha_qdma_init_tx(qdma); + if (err) + return err; + + err = airoha_qdma_init_hfwd_queues(qdma); + if (err) + return err; + + return airoha_qdma_hw_init(qdma); +} + +static int airoha_hw_init(struct udevice *dev, + struct airoha_eth *eth) +{ + int ret, i; + + /* disable xsi */ + ret = reset_assert_bulk(ð->xsi_rsts); + if (ret) + return ret; + + ret = reset_assert_bulk(ð->rsts); + if (ret) + return ret; + + mdelay(20); + + ret = reset_deassert_bulk(ð->rsts); + if (ret) + return ret; + + mdelay(20); + + ret = airoha_fe_init(eth); + if (ret) + return ret; + + for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { + ret = airoha_qdma_init(dev, eth, ð->qdma[i]); + if (ret) + return ret; + } + + return 0; +} + +static int airoha_switch_init(struct udevice *dev, struct airoha_eth *eth) +{ + ofnode switch_node; + fdt_addr_t addr; + + switch_node = ofnode_by_compatible(ofnode_null(), "airoha,en7581-switch"); + if (!ofnode_valid(switch_node)) + return -EINVAL; + + addr = ofnode_get_addr(switch_node); + if (addr == FDT_ADDR_T_NONE) + return -ENOMEM; + + /* Switch doesn't have a DEV, gets address and setup Flood and CPU port */ + eth->switch_regs = map_sysmem(addr, 0); + + /* Set FLOOD, no CPU switch register */ + airoha_switch_wr(eth, SWITCH_MFC, SWITCH_BC_FFP | SWITCH_UNM_FFP | + SWITCH_UNU_FFP); + + /* Set CPU 6 PMCR */ + airoha_switch_wr(eth, SWITCH_PMCR(6), + SWITCH_IPG_CFG_SHORT | SWITCH_MAC_MODE | + SWITCH_FORCE_MODE | SWITCH_MAC_TX_EN | + SWITCH_MAC_RX_EN | SWITCH_BKOFF_EN | SWITCH_BKPR_EN | + SWITCH_FORCE_RX_FC | SWITCH_FORCE_TX_FC | + SWITCH_FORCE_SPD_1000 | SWITCH_FORCE_DPX | + SWITCH_FORCE_LNK); + + /* Sideband signal error for Port 3, which need the auto polling */ + airoha_switch_wr(eth, SWITCH_PHY_POLL, + FIELD_PREP(SWITCH_PHY_AP_EN, 0x7f) | + FIELD_PREP(SWITCH_EEE_POLL_EN, 0x7f) | + SWITCH_PHY_PRE_EN | + FIELD_PREP(SWITCH_PHY_END_ADDR, 0xc) | + FIELD_PREP(SWITCH_PHY_ST_ADDR, 0x8)); + + return 0; +} + +static int airoha_eth_probe(struct udevice *dev) +{ + struct airoha_eth *eth = dev_get_priv(dev); + struct regmap *scu_regmap; + ofnode scu_node; + int ret; + + scu_node = ofnode_by_compatible(ofnode_null(), "airoha,en7581-scu"); + if (!ofnode_valid(scu_node)) + return -EINVAL; + + scu_regmap = syscon_node_to_regmap(scu_node); + if (IS_ERR(scu_regmap)) + return PTR_ERR(scu_regmap); + + /* It seems by default the FEMEM_SEL is set to Memory (0x1) + * preventing any access to any QDMA and FrameEngine register + * reporting all 0xdeadbeef (poor cow :( ) + */ + regmap_write(scu_regmap, SCU_SHARE_FEMEM_SEL, 0x0); + + eth->fe_regs = dev_remap_addr_name(dev, "fe"); + if (!eth->fe_regs) + return -ENOMEM; + + eth->rsts.resets = devm_kcalloc(dev, AIROHA_MAX_NUM_RSTS, + sizeof(struct reset_ctl), GFP_KERNEL); + if (!eth->rsts.resets) + return -ENOMEM; + eth->rsts.count = AIROHA_MAX_NUM_RSTS; + + eth->xsi_rsts.resets = devm_kcalloc(dev, AIROHA_MAX_NUM_XSI_RSTS, + sizeof(struct reset_ctl), GFP_KERNEL); + if (!eth->xsi_rsts.resets) + return -ENOMEM; + eth->xsi_rsts.count = AIROHA_MAX_NUM_XSI_RSTS; + + ret = reset_get_by_name(dev, "fe", ð->rsts.resets[0]); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "pdma", ð->rsts.resets[1]); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "qdma", ð->rsts.resets[2]); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "hsi0-mac", ð->xsi_rsts.resets[0]); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "hsi1-mac", ð->xsi_rsts.resets[1]); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "hsi-mac", ð->xsi_rsts.resets[2]); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "xfp-mac", ð->xsi_rsts.resets[3]); + if (ret) + return ret; + + ret = airoha_hw_init(dev, eth); + if (ret) + return ret; + + return airoha_switch_init(dev, eth); +} + +static int airoha_eth_init(struct udevice *dev) +{ + struct airoha_eth *eth = dev_get_priv(dev); + struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_queue *q; + int qid; + + qid = 0; + q = &qdma->q_rx[qid]; + + airoha_qdma_init_rx_desc(q); + + airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG, + GLOBAL_CFG_TX_DMA_EN_MASK | + GLOBAL_CFG_RX_DMA_EN_MASK); + + return 0; +} + +static void airoha_eth_stop(struct udevice *dev) +{ + struct airoha_eth *eth = dev_get_priv(dev); + struct airoha_qdma *qdma = ð->qdma[0]; + + airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG, + GLOBAL_CFG_TX_DMA_EN_MASK | + GLOBAL_CFG_RX_DMA_EN_MASK); +} + +static int airoha_eth_send(struct udevice *dev, void *packet, int length) +{ + struct airoha_eth *eth = dev_get_priv(dev); + struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_qdma_desc *desc; + struct airoha_queue *q; + dma_addr_t dma_addr; + u32 msg0, msg1; + int qid, index; + u8 fport; + u32 val; + int i; + + dma_addr = dma_map_single(packet, length, DMA_TO_DEVICE); + + qid = 0; + q = &qdma->q_tx[qid]; + desc = &q->desc[q->head]; + index = (q->head + 1) % q->ndesc; + + fport = 1; + + msg0 = 0; + msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) | + FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f); + + val = FIELD_PREP(QDMA_DESC_LEN_MASK, length); + WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); + WRITE_ONCE(desc->addr, cpu_to_le32(dma_addr)); + val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, index); + WRITE_ONCE(desc->data, cpu_to_le32(val)); + WRITE_ONCE(desc->msg0, cpu_to_le32(msg0)); + WRITE_ONCE(desc->msg1, cpu_to_le32(msg1)); + WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff)); + + dma_map_single(desc, sizeof(*desc), DMA_TO_DEVICE); + + airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK, + FIELD_PREP(TX_RING_CPU_IDX_MASK, index)); + + for (i = 0; i < 100; i++) { + dma_unmap_single(virt_to_phys(desc), sizeof(*desc), + DMA_FROM_DEVICE); + if (desc->ctrl & QDMA_DESC_DONE_MASK) + break; + + udelay(1); + } + + /* Return error if for some reason the descriptor never ACK */ + if (!(desc->ctrl & QDMA_DESC_DONE_MASK)) + return -EAGAIN; + + q->head = index; + airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(0), + IRQ_CLEAR_LEN_MASK, 1); + + return 0; +} + +static int airoha_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct airoha_eth *eth = dev_get_priv(dev); + struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_qdma_desc *desc; + struct airoha_queue *q; + u16 length; + int qid; + + qid = 0; + q = &qdma->q_rx[qid]; + desc = &q->desc[q->head]; + + dma_unmap_single(virt_to_phys(desc), sizeof(*desc), + DMA_FROM_DEVICE); + + if (!(desc->ctrl & QDMA_DESC_DONE_MASK)) + return -EAGAIN; + + length = FIELD_GET(QDMA_DESC_LEN_MASK, desc->ctrl); + dma_unmap_single(desc->addr, length, + DMA_FROM_DEVICE); + + *packetp = phys_to_virt(desc->addr); + + return length; +} + +static int arht_eth_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct airoha_eth *eth = dev_get_priv(dev); + struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_queue *q; + int qid; + + if (!packet) + return 0; + + qid = 0; + q = &qdma->q_rx[qid]; + + dma_map_single(packet, length, DMA_TO_DEVICE); + + airoha_qdma_reset_rx_desc(q, q->head, packet); + + airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK, + FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head)); + q->head = (q->head + 1) % q->ndesc; + + return 0; +} + +static int arht_eth_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct airoha_eth *eth = dev_get_priv(dev); + unsigned char *mac = pdata->enetaddr; + u32 macaddr_lsb, macaddr_msb; + + macaddr_lsb = FIELD_PREP(SMACCR0_MAC2, mac[2]) | + FIELD_PREP(SMACCR0_MAC3, mac[3]) | + FIELD_PREP(SMACCR0_MAC4, mac[4]) | + FIELD_PREP(SMACCR0_MAC5, mac[5]); + macaddr_msb = FIELD_PREP(SMACCR1_MAC1, mac[1]) | + FIELD_PREP(SMACCR1_MAC0, mac[0]); + + /* Set MAC for Switch */ + airoha_switch_wr(eth, SWITCH_SMACCR0, macaddr_lsb); + airoha_switch_wr(eth, SWITCH_SMACCR1, macaddr_msb); + + return 0; +} + +static const struct udevice_id airoha_eth_ids[] = { + { .compatible = "airoha,en7581-eth" }, +}; + +static const struct eth_ops airoha_eth_ops = { + .start = airoha_eth_init, + .stop = airoha_eth_stop, + .send = airoha_eth_send, + .recv = airoha_eth_recv, + .free_pkt = arht_eth_free_pkt, + .write_hwaddr = arht_eth_write_hwaddr, +}; + +U_BOOT_DRIVER(airoha_eth) = { + .name = "airoha-eth", + .id = UCLASS_ETH, + .of_match = airoha_eth_ids, + .probe = airoha_eth_probe, + .ops = &airoha_eth_ops, + .priv_auto = sizeof(struct airoha_eth), + .plat_auto = sizeof(struct eth_pdata), +}; diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c index a6e5f9ed036..938bd8cbc9f 100644 --- a/drivers/power/domain/power-domain-uclass.c +++ b/drivers/power/domain/power-domain-uclass.c @@ -12,10 +12,6 @@ #include <power-domain-uclass.h> #include <dm/device-internal.h> -struct power_domain_priv { - int on_count; -}; - static inline struct power_domain_ops *power_domain_dev_ops(struct udevice *dev) { return (struct power_domain_ops *)dev->driver->ops; @@ -111,49 +107,22 @@ int power_domain_free(struct power_domain *power_domain) return ops->rfree ? ops->rfree(power_domain) : 0; } -int power_domain_on_lowlevel(struct power_domain *power_domain) +int power_domain_on(struct power_domain *power_domain) { - struct power_domain_priv *priv = dev_get_uclass_priv(power_domain->dev); struct power_domain_ops *ops = power_domain_dev_ops(power_domain->dev); - int ret; debug("%s(power_domain=%p)\n", __func__, power_domain); - if (priv->on_count++ > 0) - return -EALREADY; - - ret = ops->on ? ops->on(power_domain) : 0; - if (ret) { - priv->on_count--; - return ret; - } - - return 0; + return ops->on ? ops->on(power_domain) : 0; } -int power_domain_off_lowlevel(struct power_domain *power_domain) +int power_domain_off(struct power_domain *power_domain) { - struct power_domain_priv *priv = dev_get_uclass_priv(power_domain->dev); struct power_domain_ops *ops = power_domain_dev_ops(power_domain->dev); - int ret; debug("%s(power_domain=%p)\n", __func__, power_domain); - if (priv->on_count <= 0) { - debug("Power domain %s already off.\n", power_domain->dev->name); - return -EALREADY; - } - - if (priv->on_count-- > 1) - return -EBUSY; - - ret = ops->off ? ops->off(power_domain) : 0; - if (ret) { - priv->on_count++; - return ret; - } - - return 0; + return ops->off ? ops->off(power_domain) : 0; } #if CONFIG_IS_ENABLED(OF_REAL) @@ -211,5 +180,4 @@ int dev_power_domain_off(struct udevice *dev) UCLASS_DRIVER(power_domain) = { .id = UCLASS_POWER_DOMAIN, .name = "power_domain", - .per_device_auto = sizeof(struct power_domain_priv), }; diff --git a/drivers/power/domain/sandbox-power-domain-test.c b/drivers/power/domain/sandbox-power-domain-test.c index 5b530974e94..08c15ef342b 100644 --- a/drivers/power/domain/sandbox-power-domain-test.c +++ b/drivers/power/domain/sandbox-power-domain-test.c @@ -51,5 +51,4 @@ U_BOOT_DRIVER(sandbox_power_domain_test) = { .id = UCLASS_MISC, .of_match = sandbox_power_domain_test_ids, .priv_auto = sizeof(struct sandbox_power_domain_test), - .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF, }; diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 76d108080d9..e57729f0ef9 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -23,6 +23,7 @@ #include <linux/bitops.h> #include <linux/io.h> #include <linux/sizes.h> +#include <linux/kconfig.h> #define BANK_INCREMENT 4 #define NR_BANKS 8 @@ -114,6 +115,8 @@ static int socfpga_reset_remove(struct udevice *dev) if (socfpga_reset_keep_enabled()) { puts("Deasserting all peripheral resets\n"); writel(0, data->modrst_base + 4); + if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_ARRIA10)) + writel(0, data->modrst_base + 8); } return 0; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 84130524c2d..589b526381f 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -519,6 +519,8 @@ config DEBUG_UART_BASE default 0x0 if DEBUG_UART_SANDBOX default 0xff000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP default 0xe0000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ + default 0xff000000 if DEBUG_UART_PL011 && ARCH_VERSAL + default 0xf1920000 if DEBUG_UART_PL011 && (ARCH_VERSAL_NET || ARCH_VERSAL2) help This is the base address of your UART for memory-mapped UARTs. @@ -554,6 +556,7 @@ config DEBUG_UART_CLOCK default 0 if DEBUG_MVEBU_A3700_UART default 100000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP default 50000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ + default 100000000 if DEBUG_UART_PL011 && (ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) help The UART input clock determines the speed of the internal UART circuitry. The baud rate is derived from this by dividing the input diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f475f341c9c..a3513f0a3ef 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -59,6 +59,15 @@ config ADI_SPI3 Enable the ADI (Analog Devices) SPI controller driver. This driver enables the support for SC5XX spi controller. +config AIROHA_SNFI_SPI + bool "Airoha SPI memory controller driver" + depends on SPI_MEM + help + Enable the Airoha SPI memory controller driver. This driver is + originally based on the Airoha SNFI IP core. It can only be + used to access SPI memory devices like SPI-NOR or SPI-NAND on + platforms embedding this IP core, like AN7581. + config ALTERA_SPI bool "Altera SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 21895d46429..da91b18b6ed 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o endif obj-$(CONFIG_ADI_SPI3) += adi_spi3.o +obj-$(CONFIG_AIROHA_SNFI_SPI) += airoha_snfi_spi.o obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_APPLE_SPI) += apple_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o diff --git a/drivers/spi/airoha_snfi_spi.c b/drivers/spi/airoha_snfi_spi.c new file mode 100644 index 00000000000..3ea25b293d1 --- /dev/null +++ b/drivers/spi/airoha_snfi_spi.c @@ -0,0 +1,718 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 AIROHA Inc + * + * Based on spi-airoha-snfi.c on Linux + * + * Author: Lorenzo Bianconi <lorenzo@kernel.org> + * Author: Ray Liu <ray.liu@airoha.com> + */ + +#include <asm/unaligned.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <linux/bitfield.h> +#include <linux/dma-mapping.h> +#include <linux/mtd/spinand.h> +#include <linux/time.h> +#include <regmap.h> +#include <spi.h> +#include <spi-mem.h> + +/* SPI */ +#define REG_SPI_CTRL_READ_MODE 0x0000 +#define REG_SPI_CTRL_READ_IDLE_EN 0x0004 +#define REG_SPI_CTRL_SIDLY 0x0008 +#define REG_SPI_CTRL_CSHEXT 0x000c +#define REG_SPI_CTRL_CSLEXT 0x0010 + +#define REG_SPI_CTRL_MTX_MODE_TOG 0x0014 +#define SPI_CTRL_MTX_MODE_TOG GENMASK(3, 0) + +#define REG_SPI_CTRL_RDCTL_FSM 0x0018 +#define SPI_CTRL_RDCTL_FSM GENMASK(3, 0) + +#define REG_SPI_CTRL_MACMUX_SEL 0x001c + +#define REG_SPI_CTRL_MANUAL_EN 0x0020 +#define SPI_CTRL_MANUAL_EN BIT(0) + +#define REG_SPI_CTRL_OPFIFO_EMPTY 0x0024 +#define SPI_CTRL_OPFIFO_EMPTY BIT(0) + +#define REG_SPI_CTRL_OPFIFO_WDATA 0x0028 +#define SPI_CTRL_OPFIFO_LEN GENMASK(8, 0) +#define SPI_CTRL_OPFIFO_OP GENMASK(13, 9) + +#define REG_SPI_CTRL_OPFIFO_FULL 0x002c +#define SPI_CTRL_OPFIFO_FULL BIT(0) + +#define REG_SPI_CTRL_OPFIFO_WR 0x0030 +#define SPI_CTRL_OPFIFO_WR BIT(0) + +#define REG_SPI_CTRL_DFIFO_FULL 0x0034 +#define SPI_CTRL_DFIFO_FULL BIT(0) + +#define REG_SPI_CTRL_DFIFO_WDATA 0x0038 +#define SPI_CTRL_DFIFO_WDATA GENMASK(7, 0) + +#define REG_SPI_CTRL_DFIFO_EMPTY 0x003c +#define SPI_CTRL_DFIFO_EMPTY BIT(0) + +#define REG_SPI_CTRL_DFIFO_RD 0x0040 +#define SPI_CTRL_DFIFO_RD BIT(0) + +#define REG_SPI_CTRL_DFIFO_RDATA 0x0044 +#define SPI_CTRL_DFIFO_RDATA GENMASK(7, 0) + +#define REG_SPI_CTRL_DUMMY 0x0080 +#define SPI_CTRL_CTRL_DUMMY GENMASK(3, 0) + +#define REG_SPI_CTRL_PROBE_SEL 0x0088 +#define REG_SPI_CTRL_INTERRUPT 0x0090 +#define REG_SPI_CTRL_INTERRUPT_EN 0x0094 +#define REG_SPI_CTRL_SI_CK_SEL 0x009c +#define REG_SPI_CTRL_SW_CFGNANDADDR_VAL 0x010c +#define REG_SPI_CTRL_SW_CFGNANDADDR_EN 0x0110 +#define REG_SPI_CTRL_SFC_STRAP 0x0114 + +#define REG_SPI_CTRL_NFI2SPI_EN 0x0130 +#define SPI_CTRL_NFI2SPI_EN BIT(0) + +/* NFI2SPI */ +#define REG_SPI_NFI_CNFG 0x0000 +#define SPI_NFI_DMA_MODE BIT(0) +#define SPI_NFI_READ_MODE BIT(1) +#define SPI_NFI_DMA_BURST_EN BIT(2) +#define SPI_NFI_HW_ECC_EN BIT(8) +#define SPI_NFI_AUTO_FDM_EN BIT(9) +#define SPI_NFI_OPMODE GENMASK(14, 12) + +#define REG_SPI_NFI_PAGEFMT 0x0004 +#define SPI_NFI_PAGE_SIZE GENMASK(1, 0) +#define SPI_NFI_SPARE_SIZE GENMASK(5, 4) + +#define REG_SPI_NFI_CON 0x0008 +#define SPI_NFI_FIFO_FLUSH BIT(0) +#define SPI_NFI_RST BIT(1) +#define SPI_NFI_RD_TRIG BIT(8) +#define SPI_NFI_WR_TRIG BIT(9) +#define SPI_NFI_SEC_NUM GENMASK(15, 12) + +#define REG_SPI_NFI_INTR_EN 0x0010 +#define SPI_NFI_RD_DONE_EN BIT(0) +#define SPI_NFI_WR_DONE_EN BIT(1) +#define SPI_NFI_RST_DONE_EN BIT(2) +#define SPI_NFI_ERASE_DONE_EN BIT(3) +#define SPI_NFI_BUSY_RETURN_EN BIT(4) +#define SPI_NFI_ACCESS_LOCK_EN BIT(5) +#define SPI_NFI_AHB_DONE_EN BIT(6) +#define SPI_NFI_ALL_IRQ_EN \ + (SPI_NFI_RD_DONE_EN | SPI_NFI_WR_DONE_EN | \ + SPI_NFI_RST_DONE_EN | SPI_NFI_ERASE_DONE_EN | \ + SPI_NFI_BUSY_RETURN_EN | SPI_NFI_ACCESS_LOCK_EN | \ + SPI_NFI_AHB_DONE_EN) + +#define REG_SPI_NFI_INTR 0x0014 +#define SPI_NFI_AHB_DONE BIT(6) + +#define REG_SPI_NFI_CMD 0x0020 + +#define REG_SPI_NFI_ADDR_NOB 0x0030 +#define SPI_NFI_ROW_ADDR_NOB GENMASK(6, 4) + +#define REG_SPI_NFI_STA 0x0060 +#define REG_SPI_NFI_FIFOSTA 0x0064 +#define REG_SPI_NFI_STRADDR 0x0080 +#define REG_SPI_NFI_FDM0L 0x00a0 +#define REG_SPI_NFI_FDM0M 0x00a4 +#define REG_SPI_NFI_FDM7L 0x00d8 +#define REG_SPI_NFI_FDM7M 0x00dc +#define REG_SPI_NFI_FIFODATA0 0x0190 +#define REG_SPI_NFI_FIFODATA1 0x0194 +#define REG_SPI_NFI_FIFODATA2 0x0198 +#define REG_SPI_NFI_FIFODATA3 0x019c +#define REG_SPI_NFI_MASTERSTA 0x0224 + +#define REG_SPI_NFI_SECCUS_SIZE 0x022c +#define SPI_NFI_CUS_SEC_SIZE GENMASK(12, 0) +#define SPI_NFI_CUS_SEC_SIZE_EN BIT(16) + +#define REG_SPI_NFI_RD_CTL2 0x0510 +#define REG_SPI_NFI_RD_CTL3 0x0514 + +#define REG_SPI_NFI_PG_CTL1 0x0524 +#define SPI_NFI_PG_LOAD_CMD GENMASK(15, 8) + +#define REG_SPI_NFI_PG_CTL2 0x0528 +#define REG_SPI_NFI_NOR_PROG_ADDR 0x052c +#define REG_SPI_NFI_NOR_RD_ADDR 0x0534 + +#define REG_SPI_NFI_SNF_MISC_CTL 0x0538 +#define SPI_NFI_DATA_READ_WR_MODE GENMASK(18, 16) + +#define REG_SPI_NFI_SNF_MISC_CTL2 0x053c +#define SPI_NFI_READ_DATA_BYTE_NUM GENMASK(12, 0) +#define SPI_NFI_PROG_LOAD_BYTE_NUM GENMASK(28, 16) + +#define REG_SPI_NFI_SNF_STA_CTL1 0x0550 +#define SPI_NFI_READ_FROM_CACHE_DONE BIT(25) +#define SPI_NFI_LOAD_TO_CACHE_DONE BIT(26) + +#define REG_SPI_NFI_SNF_STA_CTL2 0x0554 + +#define REG_SPI_NFI_SNF_NFI_CNFG 0x055c +#define SPI_NFI_SPI_MODE BIT(0) + +/* SPI NAND Protocol OP */ +#define SPI_NAND_OP_GET_FEATURE 0x0f +#define SPI_NAND_OP_SET_FEATURE 0x1f +#define SPI_NAND_OP_PAGE_READ 0x13 +#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE 0x03 +#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST 0x0b +#define SPI_NAND_OP_READ_FROM_CACHE_DUAL 0x3b +#define SPI_NAND_OP_READ_FROM_CACHE_QUAD 0x6b +#define SPI_NAND_OP_WRITE_ENABLE 0x06 +#define SPI_NAND_OP_WRITE_DISABLE 0x04 +#define SPI_NAND_OP_PROGRAM_LOAD_SINGLE 0x02 +#define SPI_NAND_OP_PROGRAM_LOAD_QUAD 0x32 +#define SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE 0x84 +#define SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD 0x34 +#define SPI_NAND_OP_PROGRAM_EXECUTE 0x10 +#define SPI_NAND_OP_READ_ID 0x9f +#define SPI_NAND_OP_BLOCK_ERASE 0xd8 +#define SPI_NAND_OP_RESET 0xff +#define SPI_NAND_OP_DIE_SELECT 0xc2 + +#define SPI_NAND_CACHE_SIZE (SZ_4K + SZ_256) +#define SPI_MAX_TRANSFER_SIZE 511 + +enum airoha_snand_mode { + SPI_MODE_AUTO, + SPI_MODE_MANUAL, + SPI_MODE_DMA, +}; + +enum airoha_snand_cs { + SPI_CHIP_SEL_HIGH, + SPI_CHIP_SEL_LOW, +}; + +struct airoha_snand_priv { + struct regmap *regmap_ctrl; + struct regmap *regmap_nfi; + struct clk *spi_clk; + + struct { + size_t page_size; + size_t sec_size; + u8 sec_num; + u8 spare_size; + } nfi_cfg; +}; + +static int airoha_snand_set_fifo_op(struct airoha_snand_priv *priv, + u8 op_cmd, int op_len) +{ + int err; + u32 val; + + err = regmap_write(priv->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WDATA, + FIELD_PREP(SPI_CTRL_OPFIFO_LEN, op_len) | + FIELD_PREP(SPI_CTRL_OPFIFO_OP, op_cmd)); + if (err) + return err; + + err = regmap_read_poll_timeout(priv->regmap_ctrl, + REG_SPI_CTRL_OPFIFO_FULL, + val, !(val & SPI_CTRL_OPFIFO_FULL), + 0, 250 * USEC_PER_MSEC); + if (err) + return err; + + err = regmap_write(priv->regmap_ctrl, REG_SPI_CTRL_OPFIFO_WR, + SPI_CTRL_OPFIFO_WR); + if (err) + return err; + + return regmap_read_poll_timeout(priv->regmap_ctrl, + REG_SPI_CTRL_OPFIFO_EMPTY, + val, (val & SPI_CTRL_OPFIFO_EMPTY), + 0, 250 * USEC_PER_MSEC); +} + +static int airoha_snand_set_cs(struct airoha_snand_priv *priv, u8 cs) +{ + return airoha_snand_set_fifo_op(priv, cs, sizeof(cs)); +} + +static int airoha_snand_write_data_to_fifo(struct airoha_snand_priv *priv, + const u8 *data, int len) +{ + int i; + + for (i = 0; i < len; i++) { + int err; + u32 val; + + /* 1. Wait until dfifo is not full */ + err = regmap_read_poll_timeout(priv->regmap_ctrl, + REG_SPI_CTRL_DFIFO_FULL, val, + !(val & SPI_CTRL_DFIFO_FULL), + 0, 250 * USEC_PER_MSEC); + if (err) + return err; + + /* 2. Write data to register DFIFO_WDATA */ + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_DFIFO_WDATA, + FIELD_PREP(SPI_CTRL_DFIFO_WDATA, data[i])); + if (err) + return err; + + /* 3. Wait until dfifo is not full */ + err = regmap_read_poll_timeout(priv->regmap_ctrl, + REG_SPI_CTRL_DFIFO_FULL, val, + !(val & SPI_CTRL_DFIFO_FULL), + 0, 250 * USEC_PER_MSEC); + if (err) + return err; + } + + return 0; +} + +static int airoha_snand_read_data_from_fifo(struct airoha_snand_priv *priv, + u8 *ptr, int len) +{ + int i; + + for (i = 0; i < len; i++) { + int err; + u32 val; + + /* 1. wait until dfifo is not empty */ + err = regmap_read_poll_timeout(priv->regmap_ctrl, + REG_SPI_CTRL_DFIFO_EMPTY, val, + !(val & SPI_CTRL_DFIFO_EMPTY), + 0, 250 * USEC_PER_MSEC); + if (err) + return err; + + /* 2. read from dfifo to register DFIFO_RDATA */ + err = regmap_read(priv->regmap_ctrl, + REG_SPI_CTRL_DFIFO_RDATA, &val); + if (err) + return err; + + ptr[i] = FIELD_GET(SPI_CTRL_DFIFO_RDATA, val); + /* 3. enable register DFIFO_RD to read next byte */ + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_DFIFO_RD, SPI_CTRL_DFIFO_RD); + if (err) + return err; + } + + return 0; +} + +static int airoha_snand_set_mode(struct airoha_snand_priv *priv, + enum airoha_snand_mode mode) +{ + int err; + + switch (mode) { + case SPI_MODE_MANUAL: { + u32 val; + + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_NFI2SPI_EN, 0); + if (err) + return err; + + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_READ_IDLE_EN, 0); + if (err) + return err; + + err = regmap_read_poll_timeout(priv->regmap_ctrl, + REG_SPI_CTRL_RDCTL_FSM, val, + !(val & SPI_CTRL_RDCTL_FSM), + 0, 250 * USEC_PER_MSEC); + if (err) + return err; + + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_MTX_MODE_TOG, 9); + if (err) + return err; + + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_MANUAL_EN, SPI_CTRL_MANUAL_EN); + if (err) + return err; + break; + } + case SPI_MODE_DMA: + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_NFI2SPI_EN, + SPI_CTRL_MANUAL_EN); + if (err < 0) + return err; + + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_MTX_MODE_TOG, 0x0); + if (err < 0) + return err; + + err = regmap_write(priv->regmap_ctrl, + REG_SPI_CTRL_MANUAL_EN, 0x0); + if (err < 0) + return err; + break; + case SPI_MODE_AUTO: + default: + break; + } + + return regmap_write(priv->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0); +} + +static int airoha_snand_write_data(struct airoha_snand_priv *priv, u8 cmd, + const u8 *data, int len) +{ + int i, data_len; + + for (i = 0; i < len; i += data_len) { + int err; + + data_len = min(len - i, SPI_MAX_TRANSFER_SIZE); + err = airoha_snand_set_fifo_op(priv, cmd, data_len); + if (err) + return err; + + err = airoha_snand_write_data_to_fifo(priv, &data[i], + data_len); + if (err < 0) + return err; + } + + return 0; +} + +static int airoha_snand_read_data(struct airoha_snand_priv *priv, u8 *data, + int len) +{ + int i, data_len; + + for (i = 0; i < len; i += data_len) { + int err; + + data_len = min(len - i, SPI_MAX_TRANSFER_SIZE); + err = airoha_snand_set_fifo_op(priv, 0xc, data_len); + if (err) + return err; + + err = airoha_snand_read_data_from_fifo(priv, &data[i], + data_len); + if (err < 0) + return err; + } + + return 0; +} + +static int airoha_snand_nfi_init(struct airoha_snand_priv *priv) +{ + int err; + + /* switch to SNFI mode */ + err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_SNF_NFI_CNFG, + SPI_NFI_SPI_MODE); + if (err) + return err; + + /* Enable DMA */ + return regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_INTR_EN, + SPI_NFI_ALL_IRQ_EN, SPI_NFI_AHB_DONE_EN); +} + +static int airoha_snand_nfi_config(struct airoha_snand_priv *priv) +{ + int err; + u32 val; + + err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CON, + SPI_NFI_FIFO_FLUSH | SPI_NFI_RST); + if (err) + return err; + + /* auto FDM */ + err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG, + SPI_NFI_AUTO_FDM_EN); + if (err) + return err; + + /* HW ECC */ + err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG, + SPI_NFI_HW_ECC_EN); + if (err) + return err; + + /* DMA Burst */ + err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG, + SPI_NFI_DMA_BURST_EN); + if (err) + return err; + + /* page format */ + switch (priv->nfi_cfg.spare_size) { + case 26: + val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x1); + break; + case 27: + val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x2); + break; + case 28: + val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x3); + break; + default: + val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x0); + break; + } + + err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_PAGEFMT, + SPI_NFI_SPARE_SIZE, val); + if (err) + return err; + + switch (priv->nfi_cfg.page_size) { + case 2048: + val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x1); + break; + case 4096: + val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x2); + break; + default: + val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x0); + break; + } + + err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_PAGEFMT, + SPI_NFI_PAGE_SIZE, val); + if (err) + return err; + + /* sec num */ + val = FIELD_PREP(SPI_NFI_SEC_NUM, priv->nfi_cfg.sec_num); + err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON, + SPI_NFI_SEC_NUM, val); + if (err) + return err; + + /* enable cust sec size */ + err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE, + SPI_NFI_CUS_SEC_SIZE_EN); + if (err) + return err; + + /* set cust sec size */ + val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, priv->nfi_cfg.sec_size); + return regmap_update_bits(priv->regmap_nfi, + REG_SPI_NFI_SECCUS_SIZE, + SPI_NFI_CUS_SEC_SIZE, val); +} + +static int airoha_snand_adjust_op_size(struct spi_slave *slave, + struct spi_mem_op *op) +{ + size_t max_len; + + max_len = 1 + op->addr.nbytes + op->dummy.nbytes; + if (max_len >= 160) + return -EOPNOTSUPP; + + if (op->data.nbytes > 160 - max_len) + op->data.nbytes = 160 - max_len; + + return 0; +} + +static bool airoha_snand_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + if (!spi_mem_default_supports_op(slave, op)) + return false; + + if (op->cmd.buswidth != 1) + return false; + + return (!op->addr.nbytes || op->addr.buswidth == 1) && + (!op->dummy.nbytes || op->dummy.buswidth == 1) && + (!op->data.nbytes || op->data.buswidth == 1); +} + +static int airoha_snand_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + u8 data[8], cmd, opcode = op->cmd.opcode; + struct udevice *bus = slave->dev->parent; + struct airoha_snand_priv *priv; + int i, err; + + priv = dev_get_priv(bus); + + /* switch to manual mode */ + err = airoha_snand_set_mode(priv, SPI_MODE_MANUAL); + if (err < 0) + return err; + + err = airoha_snand_set_cs(priv, SPI_CHIP_SEL_LOW); + if (err < 0) + return err; + + /* opcode */ + err = airoha_snand_write_data(priv, 0x8, &opcode, sizeof(opcode)); + if (err) + return err; + + /* addr part */ + cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8; + put_unaligned_be64(op->addr.val, data); + + for (i = ARRAY_SIZE(data) - op->addr.nbytes; + i < ARRAY_SIZE(data); i++) { + err = airoha_snand_write_data(priv, cmd, &data[i], + sizeof(data[0])); + if (err) + return err; + } + + /* dummy */ + data[0] = 0xff; + for (i = 0; i < op->dummy.nbytes; i++) { + err = airoha_snand_write_data(priv, 0x8, &data[0], + sizeof(data[0])); + if (err) + return err; + } + + /* data */ + if (op->data.dir == SPI_MEM_DATA_IN) { + err = airoha_snand_read_data(priv, op->data.buf.in, + op->data.nbytes); + if (err) + return err; + } else { + err = airoha_snand_write_data(priv, 0x8, op->data.buf.out, + op->data.nbytes); + if (err) + return err; + } + + return airoha_snand_set_cs(priv, SPI_CHIP_SEL_HIGH); +} + +static int airoha_snand_probe(struct udevice *dev) +{ + struct airoha_snand_priv *priv = dev_get_priv(dev); + int ret; + + ret = regmap_init_mem_index(dev_ofnode(dev), &priv->regmap_ctrl, 0); + if (ret) { + dev_err(dev, "failed to init spi ctrl regmap\n"); + return ret; + } + + ret = regmap_init_mem_index(dev_ofnode(dev), &priv->regmap_nfi, 1); + if (ret) { + dev_err(dev, "failed to init spi nfi regmap\n"); + return ret; + } + + priv->spi_clk = devm_clk_get(dev, "spi"); + if (IS_ERR(priv->spi_clk)) { + dev_err(dev, "unable to get spi clk\n"); + return PTR_ERR(priv->regmap_ctrl); + } + clk_enable(priv->spi_clk); + + return airoha_snand_nfi_init(priv); +} + +static int airoha_snand_nfi_set_speed(struct udevice *bus, uint speed) +{ + struct airoha_snand_priv *priv = dev_get_priv(bus); + int ret; + + ret = clk_set_rate(priv->spi_clk, speed); + if (ret < 0) + return ret; + + return 0; +} + +static int airoha_snand_nfi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +static int airoha_snand_nfi_setup(struct spi_slave *slave, + const struct spinand_info *spinand_info) +{ + struct udevice *bus = slave->dev->parent; + struct airoha_snand_priv *priv; + u32 sec_size, sec_num; + int pagesize, oobsize; + + priv = dev_get_priv(bus); + + pagesize = spinand_info->memorg.pagesize; + oobsize = spinand_info->memorg.oobsize; + + if (pagesize == 2 * 1024) + sec_num = 4; + else if (pagesize == 4 * 1024) + sec_num = 8; + else + sec_num = 1; + + sec_size = (pagesize + oobsize) / sec_num; + + /* init default value */ + priv->nfi_cfg.sec_size = sec_size; + priv->nfi_cfg.sec_num = sec_num; + priv->nfi_cfg.page_size = round_down(sec_size * sec_num, 1024); + priv->nfi_cfg.spare_size = 16; + + return airoha_snand_nfi_config(priv); +} + +static const struct spi_controller_mem_ops airoha_snand_mem_ops = { + .adjust_op_size = airoha_snand_adjust_op_size, + .supports_op = airoha_snand_supports_op, + .exec_op = airoha_snand_exec_op, +}; + +static const struct dm_spi_ops airoha_snfi_spi_ops = { + .mem_ops = &airoha_snand_mem_ops, + .set_speed = airoha_snand_nfi_set_speed, + .set_mode = airoha_snand_nfi_set_mode, + .setup_for_spinand = airoha_snand_nfi_setup, +}; + +static const struct udevice_id airoha_snand_ids[] = { + { .compatible = "airoha,en7581-snand" }, + { } +}; + +U_BOOT_DRIVER(airoha_snfi_spi) = { + .name = "airoha-snfi-spi", + .id = UCLASS_SPI, + .of_match = airoha_snand_ids, + .ops = &airoha_snfi_spi_ops, + .priv_auto = sizeof(struct airoha_snand_priv), + .probe = airoha_snand_probe, +}; diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index 816916de16d..fbeb0c6a85c 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -204,3 +204,22 @@ void cadence_qspi_apb_enable_linear_mode(bool enable) ~VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL); } } + +int cadence_device_reset(struct udevice *bus) +{ + struct cadence_spi_priv *priv = dev_get_priv(bus); + u32 reg; + + reg = readl(priv->regbase + CQSPI_REG_CONFIG); + reg |= CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK; + writel(reg, priv->regbase + CQSPI_REG_CONFIG); + + writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG); + udelay(5); + writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG); + udelay(150); + writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG); + udelay(1200); + + return 0; +} diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 623904ecdad..a78c00db4ff 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -33,6 +33,11 @@ __weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, return 0; } +__weak int cadence_device_reset(struct udevice *dev) +{ + return 0; +} + __weak int cadence_qspi_flash_reset(struct udevice *dev) { return 0; @@ -251,6 +256,9 @@ static int cadence_spi_probe(struct udevice *bus) priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz); + if (device_is_compatible(bus, "amd,versal2-ospi")) + return cadence_device_reset(bus); + /* Reset ospi flash device */ return cadence_qspi_flash_reset(bus); @@ -452,6 +460,7 @@ static const struct dm_spi_ops cadence_spi_ops = { static const struct udevice_id cadence_spi_ids[] = { { .compatible = "cdns,qspi-nor" }, { .compatible = "ti,am654-ospi" }, + { .compatible = "amd,versal2-ospi" }, { } }; diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 1f9125cd239..731b6527cf3 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -45,6 +45,8 @@ #define CQSPI_REG_CONFIG_CLK_POL BIT(1) #define CQSPI_REG_CONFIG_CLK_PHA BIT(2) #define CQSPI_REG_CONFIG_PHY_ENABLE_MASK BIT(3) +#define CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK BIT(5) +#define CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK BIT(6) #define CQSPI_REG_CONFIG_DIRECT BIT(7) #define CQSPI_REG_CONFIG_DECODE BIT(9) #define CQSPI_REG_CONFIG_ENBL_DMA BIT(15) @@ -310,5 +312,6 @@ int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg); int cadence_qspi_flash_reset(struct udevice *dev); ofnode cadence_qspi_get_subnode(struct udevice *dev); void cadence_qspi_apb_enable_linear_mode(bool enable); +int cadence_device_reset(struct udevice *dev); #endif /* __CADENCE_QSPI_H__ */ diff --git a/drivers/ufs/ufs-amd-versal2.c b/drivers/ufs/ufs-amd-versal2.c index bfd844e4193..1c5ed538370 100644 --- a/drivers/ufs/ufs-amd-versal2.c +++ b/drivers/ufs/ufs-amd-versal2.c @@ -19,8 +19,6 @@ #include "ufshcd-dwc.h" #include "ufshci-dwc.h" -#define VERSAL2_UFS_DEVICE_ID 4 - #define SRAM_CSR_INIT_DONE_MASK BIT(0) #define SRAM_CSR_EXT_LD_DONE_MASK BIT(1) #define SRAM_CSR_BYPASS_MASK BIT(2) @@ -32,19 +30,12 @@ #define TIMEOUT_MICROSEC 1000000L -#define IOCTL_UFS_TXRX_CFGRDY_GET 40 -#define IOCTL_UFS_SRAM_CSR_SEL 41 - -#define PM_UFS_SRAM_CSR_WRITE 0 -#define PM_UFS_SRAM_CSR_READ 1 - struct ufs_versal2_priv { struct ufs_hba *hba; struct reset_ctl *rstc; struct reset_ctl *rstphy; u32 phy_mode; u32 host_clk; - u32 pd_dev_id; u8 attcompval0; u8 attcompval1; u8 ctlecompval0; @@ -102,41 +93,6 @@ static int ufs_versal2_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val) return 0; } -int versal2_pm_ufs_get_txrx_cfgrdy(u32 node_id, u32 *value) -{ - u32 ret_payload[PAYLOAD_ARG_CNT]; - int ret; - - if (!value) - return -EINVAL; - - ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_TXRX_CFGRDY_GET, - 0, 0, ret_payload); - *value = ret_payload[1]; - - return ret; -} - -int versal2_pm_ufs_sram_csr_sel(u32 node_id, u32 type, u32 *value) -{ - u32 ret_payload[PAYLOAD_ARG_CNT]; - int ret; - - if (!value) - return -EINVAL; - - if (type == PM_UFS_SRAM_CSR_READ) { - ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_SRAM_CSR_SEL, - type, 0, ret_payload); - *value = ret_payload[1]; - } else { - ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_SRAM_CSR_SEL, - type, *value, 0); - } - - return ret; -} - static int ufs_versal2_enable_phy(struct ufs_hba *hba) { u32 offset, reg; @@ -281,7 +237,7 @@ static int ufs_versal2_phy_init(struct ufs_hba *hba) time_left = TIMEOUT_MICROSEC; do { time_left--; - ret = versal2_pm_ufs_get_txrx_cfgrdy(priv->pd_dev_id, ®); + ret = zynqmp_pm_ufs_get_txrx_cfgrdy(®); if (ret) return ret; @@ -312,8 +268,7 @@ static int ufs_versal2_phy_init(struct ufs_hba *hba) time_left = TIMEOUT_MICROSEC; do { time_left--; - ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id, - PM_UFS_SRAM_CSR_READ, ®); + ret = zynqmp_pm_ufs_sram_csr_read(®); if (ret) return ret; @@ -341,10 +296,10 @@ static int ufs_versal2_init(struct ufs_hba *hba) struct ufs_versal2_priv *priv = dev_get_priv(hba->dev); struct clk clk; unsigned long core_clk_rate = 0; + u32 cal; int ret = 0; priv->phy_mode = UFSHCD_DWC_PHY_MODE_ROM; - priv->pd_dev_id = VERSAL2_UFS_DEVICE_ID; ret = clk_get_by_name(hba->dev, "core_clk", &clk); if (ret) { @@ -371,6 +326,15 @@ static int ufs_versal2_init(struct ufs_hba *hba) return PTR_ERR(priv->rstphy); } + ret = zynqmp_pm_ufs_cal_reg(&cal); + if (ret) + return ret; + + priv->attcompval0 = (u8)cal; + priv->attcompval1 = (u8)(cal >> 8); + priv->ctlecompval0 = (u8)(cal >> 16); + priv->ctlecompval1 = (u8)(cal >> 24); + return ret; } @@ -397,8 +361,7 @@ static int ufs_versal2_hce_enable_notify(struct ufs_hba *hba, return ret; } - ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id, - PM_UFS_SRAM_CSR_READ, &sram_csr); + ret = zynqmp_pm_ufs_sram_csr_read(&sram_csr); if (ret) return ret; @@ -410,8 +373,7 @@ static int ufs_versal2_hce_enable_notify(struct ufs_hba *hba, return -EINVAL; } - ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id, - PM_UFS_SRAM_CSR_WRITE, &sram_csr); + ret = zynqmp_pm_ufs_sram_csr_write(&sram_csr); if (ret) return ret; diff --git a/env/Kconfig b/env/Kconfig index 4438f0b392c..9507aeed12a 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -485,7 +485,7 @@ config ENV_FAT_DEVICE_AND_PART string "Device and partition for where to store the environemt in FAT" depends on ENV_IS_IN_FAT default "0:1" if TI_COMMON_CMD_OPTIONS - default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET + default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 default ":auto" if ARCH_SUNXI default "0" if ARCH_AT91 help diff --git a/fs/exfat/io.c b/fs/exfat/io.c index 81e82829c72..c56f5675987 100644 --- a/fs/exfat/io.c +++ b/fs/exfat/io.c @@ -597,15 +597,13 @@ ssize_t exfat_generic_pwrite(struct exfat* ef, struct exfat_node* node, } #ifdef __UBOOT__ +#define PATH_MAX FS_DIRENT_NAME_LEN + struct exfat_dir_stream { + char dirname[PATH_MAX]; struct fs_dir_stream fs_dirs; struct fs_dirent dirent; - - struct exfat_node* node; - struct exfat_iterator it; - /* State tracker flags for emulated . and .. dirents */ - bool dot; - bool dotdot; + int offset; }; int exfat_fs_probe(struct blk_desc *fs_dev_desc, @@ -626,8 +624,6 @@ error: return ret; } -#define PATH_MAX FS_DIRENT_NAME_LEN - /* Adapted from uclibc 1.0.35 */ static char *exfat_realpath(const char *path, char got_path[]) { @@ -721,31 +717,31 @@ int exfat_lookup_realpath(struct exfat* ef, struct exfat_node** node, int exfat_fs_opendir(const char *filename, struct fs_dir_stream **dirsp) { struct exfat_dir_stream *dirs; + struct exfat_node *dnode; int err; - dirs = calloc(1, sizeof(*dirs)); - if (!dirs) - return -ENOMEM; - - err = exfat_lookup_realpath(&ctxt.ef, &dirs->node, filename); + err = exfat_lookup_realpath(&ctxt.ef, &dnode, filename); if (err) - goto err_out; + return err; - if (!(dirs->node->attrib & EXFAT_ATTRIB_DIR)) { + if (!(dnode->attrib & EXFAT_ATTRIB_DIR)) err = -ENOTDIR; - goto err_out; - } - err = exfat_opendir(&ctxt.ef, dirs->node, &dirs->it); + exfat_put_node(&ctxt.ef, dnode); + if (err) - goto err_out; + return err; + + dirs = calloc(1, sizeof(*dirs)); + if (!dirs) + return -ENOMEM; + + strcpy(dirs->dirname, filename); + dirs->offset = -1; *dirsp = &dirs->fs_dirs; return 0; -err_out: - free(dirs); - return err; } int exfat_fs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp) @@ -753,50 +749,77 @@ int exfat_fs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp) struct exfat_dir_stream *dirs = container_of(fs_dirs, struct exfat_dir_stream, fs_dirs); struct fs_dirent *dent = &dirs->dirent; - struct exfat_node* node; + struct exfat_node *dnode, *node; + struct exfat_iterator it; + int offset = 0; + int err; + + err = exfat_lookup_realpath(&ctxt.ef, &dnode, dirs->dirname); + if (err) + return err; + + if (!(dnode->attrib & EXFAT_ATTRIB_DIR)) { + err = -ENOTDIR; + goto err_out; + } /* Emulate current directory ./ */ - if (!dirs->dot) { - dirs->dot = true; + if (dirs->offset == -1) { + dirs->offset++; snprintf(dent->name, FS_DIRENT_NAME_LEN, "."); dent->type = FS_DT_DIR; *dentp = dent; - return 0; + goto err_out; } /* Emulate parent directory ../ */ - if (!dirs->dotdot) { - dirs->dotdot = true; + if (dirs->offset == 0) { + dirs->offset++; snprintf(dent->name, FS_DIRENT_NAME_LEN, ".."); dent->type = FS_DT_DIR; *dentp = dent; - return 0; + goto err_out; } + err = exfat_opendir(&ctxt.ef, dnode, &it); + if (err) + goto err_out; + + *dentp = NULL; + /* Read actual directory content */ - node = exfat_readdir(&dirs->it); - if (!node) { /* No more content, reset . and .. emulation */ - dirs->dot = false; - dirs->dotdot = false; - return 1; - } + while ((node = exfat_readdir(&it))) { + if (dirs->offset != ++offset) { + exfat_put_node(&ctxt.ef, node); + continue; + } - exfat_get_name(node, dent->name); - if (node->attrib & EXFAT_ATTRIB_DIR) { - dent->type = FS_DT_DIR; - } else { - dent->type = FS_DT_REG; - dent->size = node->size; + exfat_get_name(node, dent->name); + if (node->attrib & EXFAT_ATTRIB_DIR) { + dent->type = FS_DT_DIR; + } else { + dent->type = FS_DT_REG; + dent->size = node->size; + } + exfat_put_node(&ctxt.ef, node); + *dentp = dent; + dirs->offset++; + break; } - *dentp = dent; + exfat_closedir(&ctxt.ef, &it); - return 0; +err_out: + exfat_put_node(&ctxt.ef, dnode); + return err; } void exfat_fs_closedir(struct fs_dir_stream *fs_dirs) { - free(fs_dirs); + struct exfat_dir_stream *dirs = + container_of(fs_dirs, struct exfat_dir_stream, fs_dirs); + + free(dirs); } int exfat_fs_ls(const char *dirname) @@ -852,11 +875,11 @@ int exfat_fs_exists(const char *filename) err = exfat_lookup_realpath(&ctxt.ef, &node, filename); if (err) - return err; + return 0; exfat_put_node(&ctxt.ef, node); - return 0; + return 1; } int exfat_fs_size(const char *filename, loff_t *size) @@ -898,9 +921,7 @@ int exfat_fs_read(const char *filename, void *buf, loff_t offset, loff_t len, *actread = sz; - exfat_put_node(&ctxt.ef, node); - - return exfat_flush_node(&ctxt.ef, node); + err = exfat_flush_node(&ctxt.ef, node); exit: exfat_put_node(&ctxt.ef, node); return err; @@ -992,6 +1013,11 @@ exit: return err; } +int exfat_fs_rename(const char *old_path, const char *new_path) +{ + return exfat_rename(&ctxt.ef, old_path, new_path); +} + void exfat_fs_close(void) { exfat_unmount(&ctxt.ef); diff --git a/fs/exfat/lookup.c b/fs/exfat/lookup.c index 9867aab95f3..1d9aae9e036 100644 --- a/fs/exfat/lookup.c +++ b/fs/exfat/lookup.c @@ -218,8 +218,9 @@ int exfat_split(struct exfat* ef, struct exfat_node** parent, exfat_put_node(ef, *parent); *parent = *node; } +#ifndef __UBOOT__ exfat_bug("impossible"); -#ifdef __UBOOT__ +#else return 0; #endif } @@ -401,6 +401,7 @@ static struct fstype_info fstypes[] = { .ln = fs_ln_unsupported, .unlink = exfat_fs_unlink, .mkdir = exfat_fs_mkdir, + .rename = exfat_fs_rename, }, #endif { diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c index 7c364686f14..2dcdd60f683 100644 --- a/fs/squashfs/sqfs.c +++ b/fs/squashfs/sqfs.c @@ -949,7 +949,7 @@ static int sqfs_opendir_nest(const char *filename, struct fs_dir_stream **dirsp) goto out; } - token_list = malloc(token_count * sizeof(char *)); + token_list = calloc(token_count, sizeof(char *)); if (!token_list) { ret = -EINVAL; goto out; @@ -987,9 +987,11 @@ static int sqfs_opendir_nest(const char *filename, struct fs_dir_stream **dirsp) *dirsp = (struct fs_dir_stream *)dirs; out: - for (j = 0; j < token_count; j++) - free(token_list[j]); - free(token_list); + if (token_list) { + for (j = 0; j < token_count; j++) + free(token_list[j]); + free(token_list); + } free(pos_list); free(path); if (ret) { diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 19d3c72a6f1..cf43fc05025 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -138,11 +138,10 @@ "setenv fdtfile am335x-evm.dtb; fi; " \ "if test $board_name = A335X_SK; then " \ "setenv fdtfile am335x-evmsk.dtb; fi; " \ - "if test $board_name = A335_ICE; then " \ - "setenv fdtfile am335x-icev2.dtb; " \ - "if test $ice_mii = mii; then " \ - "setenv pxe_label_override Pruss; fi;" \ - "fi; " \ + "if test $board_name = A335_ICE && test $ice_mii = rmii; then " \ + "setenv fdtfile am335x-icev2.dtb; fi; " \ + "if test $board_name = A335_ICE && test $ice_mii = mii; then " \ + "setenv fdtfile am335x-icev2-prueth.dtb; fi; " \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "init_console=" \ diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h index 6a40bbdf3a7..1ade6adfa0b 100644 --- a/include/configs/amd_versal2.h +++ b/include/configs/amd_versal2.h @@ -105,6 +105,14 @@ #define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ "jtag " +#define BOOT_TARGET_DEVICES_UFS(func) func(UFS, ufs, 0) + +#define BOOTENV_DEV_UFS(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel "=" #devtypel " init " #instance "; scsi scan;\0" + +#define BOOTENV_DEV_NAME_UFS(devtypeu, devtypel, instance) \ + "ufs " + #define BOOT_TARGET_DEVICES_DFU_USB(func) func(DFU_USB, dfu_usb, 0) #define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \ @@ -117,11 +125,19 @@ #define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \ "" +#if defined(CONFIG_USB_STORAGE) +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_JTAG(func) \ BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_UFS(func) \ BOOT_TARGET_DEVICES_XSPI(func) \ BOOT_TARGET_DEVICES_DFU_USB(func) \ + BOOT_TARGET_DEVICES_USB(func) \ BOOT_TARGET_DEVICES_PXE(func) \ BOOT_TARGET_DEVICES_DHCP(func) diff --git a/include/configs/brzynq.h b/include/configs/brzynq.h new file mode 100644 index 00000000000..e2ebb2f1004 --- /dev/null +++ b/include/configs/brzynq.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Config file for BR Zynq board + * + * Copyright (C) 2024 + * B&R Industrial Automation GmbH - http://www.br-automation.com/ + */ + +#ifndef __CONFIG_BRZYNQ_H__ +#define __CONFIG_BRZYNQ_H__ + +/* Increase PHY_ANEG_TIMEOUT since the FPGA needs some setup time */ +#if IS_ENABLED(CONFIG_SPL_FPGA) +#define PHY_ANEG_TIMEOUT 8000 +#endif + +/* Use top mapped SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CFG_SYS_INIT_RAM_SIZE 0x2000 + +#endif /* __CONFIG_BRZYNQ_H__ */ diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index 06276175455..5530d36339c 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -9,75 +9,67 @@ #ifndef __CONFIG_TOPIC_MIAMI_H #define __CONFIG_TOPIC_MIAMI_H -/* Speed up boot time by ignoring the environment which we never used */ +#ifndef CONFIG_XPL_BUILD -#include "zynq-common.h" +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif -/* Fixup settings */ +#ifdef CONFIG_CMD_USB +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif -/* Setup proper boot sequences for Miami boards */ +#if defined(CONFIG_ZYNQ_QSPI) +# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) +#else +# define BOOT_TARGET_DEVICES_QSPI(func) +#endif -#if defined(CONFIG_USB_HOST) -# define EXTRA_ENV_USB \ - "usbreset=i2c dev 1 && i2c mw 41 1 ff && i2c mw 41 3 fe && "\ - "i2c mw 41 1 fe && i2c mw 41 1 ff\0" \ - "usbboot=run usbreset && if usb start; then " \ - "echo Booting from USB... && " \ - "if load usb 0 0x1900000 ${bootscript}; then "\ - "source 0x1900000; fi; " \ - "load usb 0 ${kernel_addr} ${kernel_image} && " \ - "load usb 0 ${devicetree_addr} ${devicetree_image} && " \ - "load usb 0 ${ramdisk_load_address} ${ramdisk_image} && " \ - "bootm ${kernel_addr} ${ramdisk_load_address} "\ - "${devicetree_addr}; " \ - "fi\0" - /* Note that addresses here should match the addresses in the env */ -# define DFU_ALT_INFO \ - "dfu_alt_info=" \ - "uImage ram 0x2080000 0x500000;" \ - "devicetree.dtb ram 0x2000000 0x20000;" \ - "uramdisk.image.gz ram 0x4000000 0x10000000\0" \ - "dfu_ram=run usbreset && dfu 0 ram 0\0" \ - "thor_ram=run usbreset && thordown 0 ram 0\0" +#ifdef CONFIG_CMD_UBIFS +# define BOOT_TARGET_DEVICES_UBIFS(func) func(UBIFS, ubifs, 0, qspi-rootfs, qspi-rootfs) #else -# define EXTRA_ENV_USB +# define BOOT_TARGET_DEVICES_UBIFS(func) #endif -#undef CFG_EXTRA_ENV_SETTINGS +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_qspi=sf probe && " \ + "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + "qspi " + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_UBIFS(func) \ + BOOT_TARGET_DEVICES_QSPI(func) + +#include <config_distro_bootcmd.h> + +#endif /* CONFIG_XPL_BUILD */ + +/* Default environment */ +#ifndef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ - "kernel_image=uImage\0" \ - "kernel_addr=0x2080000\0" \ - "ramdisk_image=uramdisk.image.gz\0" \ - "ramdisk_load_address=0x4000000\0" \ - "devicetree_image=devicetree.dtb\0" \ - "devicetree_addr=0x2000000\0" \ - "bitstream_image=fpga.bin\0" \ - "bootscript=autorun.scr\0" \ - "loadbit_addr=0x100000\0" \ - "loadbootenv_addr=0x2000000\0" \ - "kernel_size=0x440000\0" \ - "devicetree_size=0x10000\0" \ - "boot_size=0xF00000\0" \ - "fdt_high=0x20000000\0" \ - "initrd_high=0x20000000\0" \ - "mmc_loadbit=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \ - "mmcinfo && " \ - "load mmc 0 ${loadbit_addr} ${bitstream_image} && " \ - "fpga load 0 ${loadbit_addr} ${filesize}\0" \ - "qspiboot=echo Booting from QSPI flash... && " \ - "sf probe && " \ - "sf read ${devicetree_addr} 0xA0000 ${devicetree_size} && " \ - "sf read ${kernel_addr} 0xC0000 ${kernel_size} && " \ - "bootm ${kernel_addr} - ${devicetree_addr}\0" \ - "sdboot=if mmcinfo; then " \ - "setenv bootargs console=ttyPS0,115200 " \ - "root=/dev/mmcblk0p2 rw rootfstype=ext4 " \ - "rootwait quiet ; " \ - "load mmc 0 ${kernel_addr} ${kernel_image}&& " \ - "load mmc 0 ${devicetree_addr} ${devicetree_image}&& " \ - "bootm ${kernel_addr} - ${devicetree_addr}; " \ - "fi\0" \ - EXTRA_ENV_USB \ - DFU_ALT_INFO + "scriptaddr=0x3000000\0" \ + "script_offset_f=0xf0000\0" \ + "script_size_f=0x10000\0" \ + "fdt_addr_r=0x1f00000\0" \ + "pxefile_addr_r=0x2000000\0" \ + "kernel_addr_r=0x2000000\0" \ + "ramdisk_addr_r=0x3100000\0" \ + BOOTENV +#endif + +#include "zynq-common.h" + +/* Detect RAM size */ +#define CFG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_SIZE 0x40000000 #endif /* __CONFIG_TOPIC_MIAMI_H */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 93ae5891a07..94273d0deb9 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -46,7 +46,10 @@ #ifdef CONFIG_XPL_BUILD #define BOOTENV -#else +#endif + +/* Only use this section if no BOOTENV has been configured yet */ +#ifndef BOOTENV #ifdef CONFIG_CMD_MMC #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) @@ -167,7 +170,8 @@ BOOT_TARGET_DEVICES_DHCP(func) #include <config_distro_bootcmd.h> -#endif /* CONFIG_XPL_BUILD */ + +#endif /* BOOTENV */ /* Default environment */ #ifndef CFG_EXTRA_ENV_SETTINGS diff --git a/include/exfat.h b/include/exfat.h index 7e43beeb348..75fce5b6566 100644 --- a/include/exfat.h +++ b/include/exfat.h @@ -20,5 +20,6 @@ int exfat_fs_unlink(const char *filename); int exfat_fs_mkdir(const char *dirname); int exfat_fs_write(const char *filename, void *buf, loff_t offset, loff_t len, loff_t *actwrite); +int exfat_fs_rename(const char *old_path, const char *new_path); #endif /* _EXFAT_H */ diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h index a54eff43add..6455335bae4 100644 --- a/include/linux/intel-smc.h +++ b/include/linux/intel-smc.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2017-2018, Intel Corporation + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #ifndef __INTEL_SMC_H @@ -482,10 +483,16 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) * Call register usage: * a0 INTEL_SIP_SMC_HPS_SET_BRIDGES * a1 Set bridges status: - * 0 - Disable - * 1 - Enable - * a2-7 not used - * + * Bit 0: 0 - Disable, 1 - Enable + * Bit 1: 1 - Has mask value in a2 + * a2 Mask value + * Bit 0: soc2fpga + * Bit 1: lwhps2fpga + * Bit 2: fpga2soc + * Bit 3: f2sdram0 (For Stratix 10 only) + * Bit 4: f2sdram1 (For Stratix 10 only) + * Bit 5: f2sdram2 (For Stratix 10 only) + * a3-7 not used * Return status * a0 INTEL_SIP_SMC_STATUS_OK */ diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 13b5a52f8b9..6fe6fd520a4 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -17,7 +17,7 @@ #include <linux/spi/spi.h> #include <linux/spi/spi-mem.h> #else -#include <spi.h> +#include <linux/bitops.h> #include <spi-mem.h> #include <linux/mtd/nand.h> #endif diff --git a/include/power-domain.h b/include/power-domain.h index ad33dea76ce..18525073e5e 100644 --- a/include/power-domain.h +++ b/include/power-domain.h @@ -147,82 +147,38 @@ static inline int power_domain_free(struct power_domain *power_domain) #endif /** - * power_domain_on_lowlevel - Enable power to a power domain (with refcounting) + * power_domain_on - Enable power to a power domain. * * @power_domain: A power domain struct that was previously successfully * requested by power_domain_get(). - * Return: 0 if the transition has been performed correctly, - * -EALREADY if the domain is already on, - * a negative error code otherwise. + * Return: 0 if OK, or a negative error code. */ #if CONFIG_IS_ENABLED(POWER_DOMAIN) -int power_domain_on_lowlevel(struct power_domain *power_domain); +int power_domain_on(struct power_domain *power_domain); #else -static inline int power_domain_on_lowlevel(struct power_domain *power_domain) +static inline int power_domain_on(struct power_domain *power_domain) { return -ENOSYS; } #endif /** - * power_domain_on - Enable power to a power domain (ignores the actual state - * of the power domain) - * - * @power_domain: A power domain struct that was previously successfully - * requested by power_domain_get(). - * Return: a negative error code upon error during the transition, 0 otherwise. - */ -static inline int power_domain_on(struct power_domain *power_domain) -{ - int ret; - - ret = power_domain_on_lowlevel(power_domain); - if (ret == -EALREADY) - ret = 0; - - return ret; -} - -/** - * power_domain_off_lowlevel - Disable power to a power domain (with refcounting) + * power_domain_off - Disable power to a power domain. * * @power_domain: A power domain struct that was previously successfully * requested by power_domain_get(). - * Return: 0 if the transition has been performed correctly, - * -EALREADY if the domain is already off, - * -EBUSY if another device is keeping the domain on (but the refcounter - * is decremented), - * a negative error code otherwise. + * Return: 0 if OK, or a negative error code. */ #if CONFIG_IS_ENABLED(POWER_DOMAIN) -int power_domain_off_lowlevel(struct power_domain *power_domain); +int power_domain_off(struct power_domain *power_domain); #else -static inline int power_domain_off_lowlevel(struct power_domain *power_domain) +static inline int power_domain_off(struct power_domain *power_domain) { return -ENOSYS; } #endif /** - * power_domain_off - Disable power to a power domain (ignores the actual state - * of the power domain) - * - * @power_domain: A power domain struct that was previously successfully - * requested by power_domain_get(). - * Return: a negative error code upon error during the transition, 0 otherwise. - */ -static inline int power_domain_off(struct power_domain *power_domain) -{ - int ret; - - ret = power_domain_off_lowlevel(power_domain); - if (ret == -EALREADY || ret == -EBUSY) - ret = 0; - - return ret; -} - -/** * dev_power_domain_on - Enable power domains for a device . * * @dev: The client device. diff --git a/include/regmap.h b/include/regmap.h index 22b043408ac..8c6f7c1c9b1 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -362,6 +362,34 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, int regmap_update_bits(struct regmap *map, uint offset, uint mask, uint val); /** + * regmap_set_bits() - Set bits to a regmap + * + * @map: Regmap to write bits to + * @offset: Offset in the regmap to write to + * @bits: Bits to set to the regmap at the specified offset + * + * Return: 0 if OK, -ve on error + */ +static inline int regmap_set_bits(struct regmap *map, uint offset, uint bits) +{ + return regmap_update_bits(map, offset, bits, bits); +} + +/** + * regmap_clear_bits() - Clear bits to a regmap + * + * @map: Regmap to write bits to + * @offset: Offset in the regmap to write to + * @bits: Bits to clear to the regmap at the specified offset + * + * Return: 0 if OK, -ve on error + */ +static inline int regmap_clear_bits(struct regmap *map, uint offset, uint bits) +{ + return regmap_update_bits(map, offset, bits, 0); +} + +/** * regmap_init_mem() - Set up a new register map that uses memory access * * @node: Device node that uses this map diff --git a/include/spi.h b/include/spi.h index 6944773b596..2783200d663 100644 --- a/include/spi.h +++ b/include/spi.h @@ -11,6 +11,8 @@ #include <linux/bitops.h> +struct spinand_info; + /* SPI mode flags */ #define SPI_CPHA BIT(0) /* clock phase (1 = SPI_CLOCK_PHASE_SECOND) */ #define SPI_CPOL BIT(1) /* clock polarity (1 = SPI_POLARITY_HIGH) */ @@ -537,6 +539,16 @@ struct dm_spi_ops { */ int (*get_mmap)(struct udevice *dev, ulong *map_basep, uint *map_sizep, uint *offsetp); + + /** + * setup_for_spinand() - Setup the SPI for attached SPI NAND + * + * @dev: The SPI flash slave device + * @spinand_info: The SPI NAND info to configure for + * @return 0 if OK, -ve value on error + */ + int (*setup_for_spinand)(struct spi_slave *slave, + const struct spinand_info *spinand_info); }; struct dm_spi_emul_ops { diff --git a/include/xilinx.h b/include/xilinx.h index e4e29797988..c54d6dc1453 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -34,6 +34,8 @@ typedef enum { /* typedef xilinx_family */ xilinx_zynq, /* Zynq Family */ xilinx_zynqmp, /* ZynqMP Family */ xilinx_versal, /* Versal Family */ + xilinx_versal_net, /* Versal NET Family */ + xilinx_versal2, /* Versal Gen 2 Family */ max_xilinx_type /* insert all new types before this */ } xilinx_family; /* end, typedef xilinx_family */ diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 73198a6a6ea..dc06abc52fc 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -457,6 +457,12 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); int zynqmp_mmio_read(const u32 address, u32 *value); int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); int zynqmp_pm_feature(const u32 api_id); +u32 zynqmp_pm_get_bootmode_reg(void); +int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value); +int zynqmp_pm_ufs_sram_csr_read(u32 *value); +int zynqmp_pm_ufs_sram_csr_write(u32 *value); +int zynqmp_pm_ufs_cal_reg(u32 *value); +u32 zynqmp_pm_get_pmc_multi_boot_reg(void); /* Type of Config Object */ #define PM_CONFIG_OBJECT_TYPE_BASE 0x1U @@ -500,4 +506,10 @@ struct zynqmp_ipi_msg { u32 *buf; }; +#define CRP_BOOT_MODE_REG_NODE 0x30000001 +#define CRP_BOOT_MODE_REG_OFFSET 0x200 + +#define PM_REG_PMC_GLOBAL_NODE 0x30000004 +#define PMC_MULTI_BOOT_MODE_REG_OFFSET 0x4 + #endif /* _ZYNQMP_FIRMWARE_H_ */ diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile index 17fbfad116f..d78bf7d6191 100644 --- a/lib/efi_selftest/Makefile +++ b/lib/efi_selftest/Makefile @@ -51,6 +51,7 @@ efi_selftest_variables_runtime.o \ efi_selftest_watchdog.o obj-$(CONFIG_EFI_ECPT) += efi_selftest_ecpt.o +obj-$(CONFIG_ARM64) += efi_selftest_el.o obj-$(CONFIG_NETDEVICES) += efi_selftest_snp.o obj-$(CONFIG_EFI_HTTP_PROTOCOL) += efi_selftest_http.o obj-$(CONFIG_EFI_HTTP_PROTOCOL) += efi_selftest_ipconfig.o diff --git a/lib/efi_selftest/efi_selftest_el.c b/lib/efi_selftest/efi_selftest_el.c new file mode 100644 index 00000000000..f9941caf22d --- /dev/null +++ b/lib/efi_selftest/efi_selftest_el.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Check current exception level on ARMv8. + */ +#include <efi_loader.h> +#include <efi_selftest.h> + +/** + * current_exception_level() + * + * Return: current exception level, 0 - 3 + */ +static unsigned int current_exception_level(void) +{ + unsigned long el; + + asm volatile ( + "MRS %0, CurrentEL" + : "=r" (el) : : ); + + return (el >> 2) & 0x3; +} + +/** + * execute() - execute test + * + * Check that the exception level is not EL3. + */ +static int execute(void) +{ + unsigned int el = current_exception_level(); + + efi_st_printf("Exception level EL%u\n", el); + if (el != 1 && el != 2) { + efi_st_error("EL1 or EL2 expected"); + return EFI_ST_FAILURE; + } + + return EFI_ST_SUCCESS; +} + +EFI_UNIT_TEST(el) = { + .name = "exception level", + .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT, + .execute = execute, +}; diff --git a/lib/uuid.c b/lib/uuid.c index 75658778044..6abbcf27b1f 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -67,8 +67,11 @@ static const struct { efi_guid_t guid; } list_guid[] = { #ifndef USE_HOSTCC +#if defined(CONFIG_PARTITION_TYPE_GUID) || defined(CONFIG_CMD_EFIDEBUG) || \ + defined(CONFIG_EFI) + {"EFI System Partition", PARTITION_SYSTEM_GUID}, +#endif #ifdef CONFIG_PARTITION_TYPE_GUID - {"system", PARTITION_SYSTEM_GUID}, {"mbr", LEGACY_MBR_PARTITION_GUID}, {"msft", PARTITION_MSFT_RESERVED_GUID}, {"data", PARTITION_BASIC_DATA_GUID}, @@ -182,10 +185,6 @@ static const struct { { "TCG2", EFI_TCG2_PROTOCOL_GUID, - }, - { - "System Partition", - PARTITION_SYSTEM_GUID }, { "Firmware Management", diff --git a/test/common/print.c b/test/common/print.c index e3711b10809..c48efc2783f 100644 --- a/test/common/print.c +++ b/test/common/print.c @@ -45,11 +45,11 @@ static int print_guid(struct unit_test_state *uts) sprintf(str, "%pUL", guid); ut_asserteq_str("04030201-0605-0807-090A-0B0C0D0E0F10", str); sprintf(str, "%pUs", guid_esp); - if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID)) { /* brace needed */ - ut_asserteq_str("system", str); - } else { + if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID) || + IS_ENABLED(CONFIG_CMD_EFIDEBUG) || IS_ENABLED(CONFIG_EFI)) + ut_asserteq_str("EFI System Partition", str); + else ut_asserteq_str("c12a7328-f81f-11d2-ba4b-00a0c93ec93b", str); - } ret = snprintf(str, 4, "%pUL", guid); ut_asserteq(0, str[3]); ut_asserteq(36, ret); diff --git a/test/dm/power-domain.c b/test/dm/power-domain.c index 8a95f6bdb90..896cf5b2ae9 100644 --- a/test/dm/power-domain.c +++ b/test/dm/power-domain.c @@ -27,7 +27,7 @@ static int dm_test_power_domain(struct unit_test_state *uts) ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "power-domain-test", &dev_test)); - ut_asserteq(0, sandbox_power_domain_query(dev_power_domain, + ut_asserteq(1, sandbox_power_domain_query(dev_power_domain, TEST_POWER_DOMAIN)); ut_assertok(sandbox_power_domain_test_get(dev_test)); diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py index c73fb4abbcb..0205048e73a 100644 --- a/test/py/tests/test_fs/conftest.py +++ b/test/py/tests/test_fs/conftest.py @@ -17,7 +17,7 @@ supported_fs_fat = ['fat12', 'fat16'] supported_fs_mkdir = ['fat12', 'fat16', 'fat32', 'exfat', 'fs_generic'] supported_fs_unlink = ['fat12', 'fat16', 'fat32', 'exfat', 'fs_generic'] supported_fs_symlink = ['ext4'] -supported_fs_rename = ['fat12', 'fat16', 'fat32'] +supported_fs_rename = ['fat12', 'fat16', 'fat32', 'exfat', 'fs_generic'] # # Filesystem test specific setup diff --git a/test/py/tests/test_fs/test_basic.py b/test/py/tests/test_fs/test_basic.py index 64a3b50f52a..88b163ce305 100644 --- a/test/py/tests/test_fs/test_basic.py +++ b/test/py/tests/test_fs/test_basic.py @@ -35,6 +35,19 @@ class TestFsBasic(object): '%sls host 0:0 invalid_d' % fs_cmd_prefix) assert('' == output) + with ubman.log.section('Test Case 1c - test -e'): + # Test Case 1 - test -e + output = ubman.run_command_list([ + 'host bind 0 %s' % fs_img, + 'test -e host 0:0 1MB.file && echo PASS']) + assert('PASS' in ''.join(output)) + + with ubman.log.section('Test Case 1d - test -e (invalid file)'): + # In addition, test with a nonexistent file to see if we crash. + output = ubman.run_command( + 'test -e host 0:0 2MB.file || echo PASS') + assert('PASS' in ''.join(output)) + def test_fs2(self, ubman, fs_obj_basic): """ Test Case 2 - size command for a small file diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index 5d051e005da..f4c832be8d3 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -531,7 +531,7 @@ class Toolchains: if arch == 'aarch64': arch = 'arm64' base = 'https://www.kernel.org/pub/tools/crosstool/files/bin' - versions = ['13.2.0', '12.2.0'] + versions = ['14.2.0', '13.2.0'] links = [] for version in versions: url = '%s/%s/%s/' % (base, arch, version) |