diff options
143 files changed, 1163 insertions, 3471 deletions
@@ -3,7 +3,7 @@ VERSION = 2025 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc3 +EXTRAVERSION = -rc4 NAME = # *DOCUMENTATION* @@ -21,7 +21,7 @@ include include/host_arch.h ifeq ("", "$(CROSS_COMPILE)") MK_ARCH="${shell uname -m}" else - MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(ccache\)\?[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}" + MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(ccache\)\{0,1\}[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}" endif unexport HOST_ARCH ifeq ("x86_64", $(MK_ARCH)) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 05542443dbc..12edd2ac22e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -190,7 +190,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ cn9130-crb-A.dtb \ cn9130-crb-B.dtb \ ac5-98dx35xx-rd.dtb \ - ac5-98dx35xx-atl-x240.dtb + ac5-98dx35xx-atl-x240.dtb \ + cn9130-atl-x250.dtb endif dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb diff --git a/arch/arm/dts/bcm47622.dtsi b/arch/arm/dts/bcm47622.dtsi deleted file mode 100644 index c016e12b737..00000000000 --- a/arch/arm/dts/bcm47622.dtsi +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - compatible = "brcm,bcm47622", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - CA7_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - CA7_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&CA7_0>, <&CA7_1>, - <&CA7_2>, <&CA7_3>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - cpu_off = <1>; - cpu_on = <2>; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x818000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1000 0x1000>, - <0x2000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm4912.dtsi b/arch/arm/dts/bcm4912.dtsi deleted file mode 100644 index 3d016c2ce67..00000000000 --- a/arch/arm/dts/bcm4912.dtsi +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - compatible = "brcm,bcm4912", "brcm,bcmbca"; - #address-cells = <2>; - #size-cells = <2>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - B53_0: cpu@0 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_1: cpu@1 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_2: cpu@2 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_3: cpu@3 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - - pmu: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&B53_0>, <&B53_1>, - <&B53_2>, <&B53_3>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x800000>; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm63146.dtsi b/arch/arm/dts/bcm63146.dtsi deleted file mode 100644 index 04de96bd0a0..00000000000 --- a/arch/arm/dts/bcm63146.dtsi +++ /dev/null @@ -1,110 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - compatible = "brcm,bcm63146", "brcm,bcmbca"; - #address-cells = <2>; - #size-cells = <2>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - B53_0: cpu@0 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_1: cpu@1 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - pmu: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&B53_0>, <&B53_1>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_HIGH)>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x800000>; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi deleted file mode 100644 index 4bed1f914a9..00000000000 --- a/arch/arm/dts/bcm63158.dtsi +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com> - * Copyright 2022 Broadcom Ltd. - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - compatible = "brcm,bcm63158", "brcm,bcmbca"; - #address-cells = <2>; - #size-cells = <2>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - B53_0: cpu@0 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_1: cpu@1 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_2: cpu@2 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_3: cpu@3 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - - pmu: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&B53_0>, <&B53_1>, - <&B53_2>, <&B53_3>; - }; - - clocks { - bootph-all; - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-mult = <2>; - clock-div = <1>; - }; - - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - - wdt_clk: wdt-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x800000>; - bootph-all; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - - leds: led-controller@800 { - compatible = "brcm,bcm6858-leds"; - reg = <0x800 0xe4>; - - status = "disabled"; - }; - - wdt1: watchdog@480 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x480 0x14>; - clocks = <&wdt_clk>; - }; - - wdt2: watchdog@4c0 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x4c0 0x14>; - clocks = <&wdt_clk>; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdt1>; - }; - - gpio0: gpio-controller@500 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x500 0x4>, - <0x520 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio1: gpio-controller@504 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x504 0x4>, - <0x524 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio2: gpio-controller@508 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x508 0x4>, - <0x528 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio3: gpio-controller@50c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x50c 0x4>, - <0x52c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio4: gpio-controller@510 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x510 0x4>, - <0x530 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio5: gpio-controller@514 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x514 0x4>, - <0x534 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio6: gpio-controller@518 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x518 0x4>, - <0x538 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio7: gpio-controller@51c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x51c 0x4>, - <0x53c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - hsspi: spi-controller@1000 { - compatible = "brcm,bcm6328-hsspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1000 0x600>; - clocks = <&hsspi_pll>, <&hsspi_pll>; - clock-names = "hsspi", "pll"; - spi-max-frequency = <100000000>; - num-cs = <8>; - - status = "disabled"; - }; - - nand: nand-controller@1800 { - compatible = "brcm,nand-bcm63158", - "brcm,brcmnand-v5.0", - "brcm,brcmnand"; - reg-names = "nand", "nand-int-base", "nand-cache"; - reg = <0x1800 0x180>, - <0x2000 0x10>, - <0x1c00 0x200>; - parameter-page-big-endian = <0>; - - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm63178.dtsi b/arch/arm/dts/bcm63178.dtsi deleted file mode 100644 index cbd094dde6d..00000000000 --- a/arch/arm/dts/bcm63178.dtsi +++ /dev/null @@ -1,120 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - compatible = "brcm,bcm63178", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&CA7_0>, <&CA7_1>, - <&CA7_2>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm6756.dtsi b/arch/arm/dts/bcm6756.dtsi deleted file mode 100644 index ce1b59faf80..00000000000 --- a/arch/arm/dts/bcm6756.dtsi +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - compatible = "brcm,bcm6756", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&CA7_0>, <&CA7_1>, - <&CA7_2>, <&CA7_3>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm6813.dtsi b/arch/arm/dts/bcm6813.dtsi deleted file mode 100644 index c3e6197be80..00000000000 --- a/arch/arm/dts/bcm6813.dtsi +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - compatible = "brcm,bcm6813", "brcm,bcmbca"; - #address-cells = <2>; - #size-cells = <2>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - B53_0: cpu@0 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_1: cpu@1 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_2: cpu@2 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_3: cpu@3 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - - pmu: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&B53_0>, <&B53_1>, - <&B53_2>, <&B53_3>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x800000>; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm6855.dtsi b/arch/arm/dts/bcm6855.dtsi deleted file mode 100644 index 10c003a57c9..00000000000 --- a/arch/arm/dts/bcm6855.dtsi +++ /dev/null @@ -1,257 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com> - * Copyright 2022 Broadcom Ltd. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - compatible = "brcm,bcm6855", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>; - }; - - clocks: clocks { - bootph-all; - - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-mult = <2>; - clock-div = <1>; - }; - - wdt_clk: wdt-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - bootph-all; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - - wdt1: watchdog@480 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x480 0x14>; - clocks = <&wdt_clk>; - }; - - wdt2: watchdog@4c0 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x4c0 0x14>; - clocks = <&wdt_clk>; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdt1>; - }; - - gpio0: gpio-controller@500 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x500 0x4>, - <0x520 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio1: gpio-controller@504 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x504 0x4>, - <0x524 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio2: gpio-controller@508 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x508 0x4>, - <0x528 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio3: gpio-controller@50c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x50c 0x4>, - <0x52c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio4: gpio-controller@510 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x510 0x4>, - <0x530 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio5: gpio-controller@514 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x514 0x4>, - <0x534 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio6: gpio-controller@518 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x518 0x4>, - <0x538 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio7: gpio-controller@51c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x51c 0x4>, - <0x53c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - nand: nand-controller@1800 { - compatible = "brcm,nand-bcm6753", - "brcm,brcmnand-v5.0", - "brcm,brcmnand"; - reg-names = "nand", "nand-int-base", "nand-cache"; - reg = <0x1800 0x180>, - <0x2000 0x10>, - <0x1c00 0x200>; - parameter-page-big-endian = <0>; - - status = "disabled"; - }; - - leds: led-controller@3000 { - compatible = "brcm,bcm6753-leds"; - reg = <0x3000 0x3480>; - - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm6856.dtsi b/arch/arm/dts/bcm6856.dtsi deleted file mode 100644 index 38c88f8399b..00000000000 --- a/arch/arm/dts/bcm6856.dtsi +++ /dev/null @@ -1,253 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com> - * Copyright 2022 Broadcom Ltd. - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - compatible = "brcm,bcm6856", "brcm,bcmbca"; - #address-cells = <2>; - #size-cells = <2>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - B53_0: cpu@0 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_1: cpu@1 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - pmu: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&B53_0>, <&B53_1>; - }; - - clocks: clocks { - bootph-all; - - periph_clk:periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-mult = <2>; - clock-div = <1>; - }; - - wdt_clk: wdt-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x1000 0x1000>, /* GICD */ - <0x2000 0x2000>, /* GICC */ - <0x4000 0x2000>, /* GICH */ - <0x6000 0x2000>; /* GICV */ - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_HIGH)>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x800000>; - bootph-all; - - uart0: serial@640 { - compatible = "brcm,bcm6345-uart"; - reg = <0x640 0x18>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&periph_clk>; - clock-names = "refclk"; - status = "disabled"; - }; - - wdt1: watchdog@480 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x480 0x14>; - clocks = <&wdt_clk>; - }; - - wdt2: watchdog@4c0 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x4c0 0x14>; - clocks = <&wdt_clk>; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdt1>; - }; - - leds: led-controller@800 { - compatible = "brcm,bcm6858-leds"; - reg = <0x800 0xe4>; - - status = "disabled"; - }; - - gpio0: gpio-controller@500 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x500 0x4>, - <0x520 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio1: gpio-controller@504 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x504 0x4>, - <0x524 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio2: gpio-controller@508 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x508 0x4>, - <0x528 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio3: gpio-controller@50c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x50c 0x4>, - <0x52c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio4: gpio-controller@510 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x510 0x4>, - <0x530 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio5: gpio-controller@514 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x514 0x4>, - <0x534 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio6: gpio-controller@518 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x518 0x4>, - <0x538 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio7: gpio-controller@51c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x51c 0x4>, - <0x53c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - hsspi: spi-controller@1000 { - compatible = "brcm,bcm6328-hsspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1000 0x600>; - clocks = <&hsspi_pll>, <&hsspi_pll>; - clock-names = "hsspi", "pll"; - spi-max-frequency = <100000000>; - num-cs = <8>; - - status = "disabled"; - }; - - nand: nand-controller@1800 { - compatible = "brcm,nand-bcm68360", - "brcm,brcmnand-v5.0", - "brcm,brcmnand"; - reg-names = "nand", "nand-int-base", "nand-cache"; - reg = <0x1800 0x180>, - <0x2000 0x10>, - <0x1c00 0x200>; - parameter-page-big-endian = <0>; - - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi deleted file mode 100644 index dc95047a265..00000000000 --- a/arch/arm/dts/bcm6858.dtsi +++ /dev/null @@ -1,272 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com> - * Copyright 2022 Broadcom Ltd. - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - compatible = "brcm,bcm6858", "brcm,bcmbca"; - #address-cells = <2>; - #size-cells = <2>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - B53_0: cpu@0 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_1: cpu@1 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_2: cpu@2 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_3: cpu@3 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - - pmu: pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&B53_0>, <&B53_1>, - <&B53_2>, <&B53_3>; - }; - - clocks { - bootph-all; - - periph_clk: periph_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-mult = <2>; - clock-div = <1>; - }; - - wdt_clk: wdt-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x1000 0x1000>, /* GICD */ - <0x2000 0x2000>, /* GICC */ - <0x4000 0x2000>, /* GICH */ - <0x6000 0x2000>; /* GICV */ - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_HIGH)>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x800000>; - bootph-all; - - uart0: serial@640 { - compatible = "brcm,bcm6345-uart"; - reg = <0x640 0x18>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&periph_clk>; - clock-names = "refclk"; - status = "disabled"; - }; - - leds: led-controller@800 { - compatible = "brcm,bcm6858-leds"; - reg = <0x800 0xe4>; - - status = "disabled"; - }; - - wdt1: watchdog@2780 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x2780 0x14>; - clocks = <&wdt_clk>; - }; - - wdt2: watchdog@27c0 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x27c0 0x14>; - clocks = <&wdt_clk>; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdt1>; - }; - - gpio0: gpio-controller@500 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x500 0x4>, - <0x520 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio1: gpio-controller@504 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x504 0x4>, - <0x524 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio2: gpio-controller@508 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x508 0x4>, - <0x528 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio3: gpio-controller@50c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x50c 0x4>, - <0x52c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio4: gpio-controller@510 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x510 0x4>, - <0x530 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio5: gpio-controller@514 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x514 0x4>, - <0x534 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio6: gpio-controller@518 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x518 0x4>, - <0x538 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio7: gpio-controller@51c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x51c 0x4>, - <0x53c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - hsspi: spi-controller@1000 { - compatible = "brcm,bcm6328-hsspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1000 0x600>; - clocks = <&hsspi_pll>, <&hsspi_pll>; - clock-names = "hsspi", "pll"; - spi-max-frequency = <100000000>; - num-cs = <8>; - - status = "disabled"; - }; - - nand: nand-controller@1800 { - compatible = "brcm,nand-bcm6858", - "brcm,brcmnand-v5.0", - "brcm,brcmnand"; - reg-names = "nand", "nand-int-base", "nand-cache"; - reg = <0x1800 0x180>, - <0x2000 0x10>, - <0x1c00 0x200>; - parameter-page-big-endian = <0>; - - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm6878.dtsi b/arch/arm/dts/bcm6878.dtsi deleted file mode 100644 index 1e8b5fa96c2..00000000000 --- a/arch/arm/dts/bcm6878.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - compatible = "brcm,bcm6878", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&CA7_0>, <&CA7_1>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_LEVEL_HIGH)>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm947622.dts b/arch/arm/dts/bcm947622.dts deleted file mode 100644 index 6f083724ab8..00000000000 --- a/arch/arm/dts/bcm947622.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm47622.dtsi" - -/ { - model = "Broadcom BCM947622 Reference Board"; - compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm94912.dts b/arch/arm/dts/bcm94912.dts deleted file mode 100644 index a3623e6f691..00000000000 --- a/arch/arm/dts/bcm94912.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm4912.dtsi" - -/ { - model = "Broadcom BCM94912 Reference Board"; - compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm963146.dts b/arch/arm/dts/bcm963146.dts deleted file mode 100644 index e39f1e6d477..00000000000 --- a/arch/arm/dts/bcm963146.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm63146.dtsi" - -/ { - model = "Broadcom BCM963146 Reference Board"; - compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm963158.dts b/arch/arm/dts/bcm963158.dts deleted file mode 100644 index eba07e0b1ca..00000000000 --- a/arch/arm/dts/bcm963158.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm63158.dtsi" - -/ { - model = "Broadcom BCM963158 Reference Board"; - compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm963178.dts b/arch/arm/dts/bcm963178.dts deleted file mode 100644 index fa096e9cde2..00000000000 --- a/arch/arm/dts/bcm963178.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm63178.dtsi" - -/ { - model = "Broadcom BCM963178 Reference Board"; - compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm96756.dts b/arch/arm/dts/bcm96756.dts deleted file mode 100644 index 9a4a87ba9c8..00000000000 --- a/arch/arm/dts/bcm96756.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6756.dtsi" - -/ { - model = "Broadcom BCM96756 Reference Board"; - compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm96813.dts b/arch/arm/dts/bcm96813.dts deleted file mode 100644 index af17091ae76..00000000000 --- a/arch/arm/dts/bcm96813.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6813.dtsi" - -/ { - model = "Broadcom BCM96813 Reference Board"; - compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm96855.dts b/arch/arm/dts/bcm96855.dts deleted file mode 100644 index e4e740c73e9..00000000000 --- a/arch/arm/dts/bcm96855.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6855.dtsi" - -/ { - model = "Broadcom BCM96855 Reference Board"; - compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm96856.dts b/arch/arm/dts/bcm96856.dts deleted file mode 100644 index 032aeb75c98..00000000000 --- a/arch/arm/dts/bcm96856.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6856.dtsi" - -/ { - model = "Broadcom BCM96856 Reference Board"; - compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm96858.dts b/arch/arm/dts/bcm96858.dts deleted file mode 100644 index 0cbf582f5d5..00000000000 --- a/arch/arm/dts/bcm96858.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6858.dtsi" - -/ { - model = "Broadcom BCM96858 Reference Board"; - compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm96878.dts b/arch/arm/dts/bcm96878.dts deleted file mode 100644 index 8fbc175cb45..00000000000 --- a/arch/arm/dts/bcm96878.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6878.dtsi" - -/ { - model = "Broadcom BCM96878 Reference Board"; - compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/cn9130-atl-x250.dts b/arch/arm/dts/cn9130-atl-x250.dts new file mode 100644 index 00000000000..f2c82da9d14 --- /dev/null +++ b/arch/arm/dts/cn9130-atl-x250.dts @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Allied Telesis Labs + */ + +#include "cn9130.dtsi" + +/ { + model = "Allied Telesis x250"; + compatible = "alliedtelesis,x250", + "marvell,cn9130", + "marvell,armada-ap806-quad", + "marvell,armada-ap806"; + + aliases { + serial0 = &uart0; + i2c0 = &cp0_i2c0; + i2c1 = &cp0_i2c1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + fault { + label = "fault:red"; + gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; +}; + +/* + * AP related configuration + */ +&ap_pinctl { + /* AP_MPP Pins: + * GPIO & NC [0-6,9-10,12] + * UART0 [11,19] + * UART1 [7,8] + * Note: The x250-28XTm PT1 units has the console port wired + * to the second uart pins (UART1). This was fixed in all + * subsequent models. + * Here we choose to configure the pin control for both + * uarts to cater for either unit. + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0 0 0 0 0 0 0 3 3 0 + 0 3 0 0 0 0 0 0 0 3 >; +}; + +&ap_gpio0 { + pp-reset { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-high; + line-name = "pp-reset"; + }; +}; + +/* + * CP related configuration + */ +&cp0_pinctl { + /* MPP Bus: + * [0-1] DEV + * [2-8] GPIO + * [9] DEV + * [10-12] GPIO + * [13] ND_RB + * [14] GPIO + * [15-28] DEV + * [29-30] GPIO + * [31] DEV + * [32-34] GPIO + * [35-36] I2C1 + * [37-38] I2C0 + * [39-55] GPIO + * [56-60] SPI + * [61-62] GPIO + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 1 1 0 0 0 0 0 0 0 1 + 0 0 0 2 0 1 1 1 1 1 + 1 1 1 1 1 1 1 1 1 0 + 0 1 0 0 0 2 2 2 2 0 + 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 6 6 6 6 + 6 0 0>; + + cp0_i2c0_pins: cp0-i2c-pins-0 { + marvell,pins = <37 38>; + marvell,function = <2>; + }; + + cp0_i2c0_gpio_pins: cp0-i2c-gpio-pins-0 { + marvell,pins = <37 38>; + marvell,function = <0>; + }; + + cp0_i2c1_pins: cp0-i2c-pins-1 { + marvell,pins = <35 36>; + marvell,function = <2>; + }; + + cp0_nand_pins: cp0-nand-pins { + marvell,pins = <0 1 9 15 16 17 18 19 20 21 22 23 24 25 26 27 28 31>; + marvell,function = <1>; + }; + + cp0_nand_rb: cp0-nand-rb { + marvell,pins = <13>; + marvell,function = <2>; + }; + + cp0_spi0_pins: cp0-spi-pins-0 { + marvell,pins = <56 57 58 59 60>; + marvell,function = <6>; + }; +}; + +&cp0_comphy { + phy0 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + + phy1 { + phy-type = <COMPHY_TYPE_IGNORE>; + }; + + phy2 { + phy-type = <COMPHY_TYPE_IGNORE>; + }; + + phy3 { + phy-type = <COMPHY_TYPE_IGNORE>; + }; + + phy4 { + phy-type = <COMPHY_TYPE_IGNORE>; + }; + + phy5 { + phy-type = <COMPHY_TYPE_IGNORE>; + }; +}; + +&cp0_pcie0 { + num-lanes = <1>; + /* non-prefetchable memory */ + ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>; + status = "disabled"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + clock-frequency = <200000000>; +}; + +&cp0_utmi0 { + status = "okay"; +}; + +&cp0_usb3_0 { + status = "okay"; +}; + +&cp0_spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_spi0_pins>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + }; +}; + +&cp0_nand { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_nand_pins &cp0_nand_rb>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-timing-mode = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@user { + reg = <0x00000000 0x10000000>; + label = "user"; + }; + }; +}; + +&cp0_gpio0 +{ + nand-protect { + gpio-hog; + gpios = <29 GPIO_ACTIVE_LOW>; + output-low; + line-name = "nand-protect"; + }; +}; + +&cp0_gpio1 +{ + usb-en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-en"; + }; + + phy-reset { + gpio-hog; + gpios = <21 GPIO_ACTIVE_LOW>; + output-high; + line-name = "phy-reset"; + }; +}; + +&cp0_i2c0 { + status = "okay"; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&cp0_i2c0_pins>; + pinctrl-1 = <&cp0_i2c0_gpio_pins>; + scl-gpios = <&cp0_gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&cp0_gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + mux@71 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9546"; + reg = <0x71>; + i2c-mux-idle-disconnect; + reset-gpios = <&cp0_gpio1 19 GPIO_ACTIVE_LOW>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hwmon@2e { + compatible = "adi,adt7476"; + reg = <0x2e>; + }; + + rtc@68 { + compatible = "adi,max31331"; + reg = <0x68>; + }; + }; + }; +}; + +&cp0_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c1_pins>; +}; diff --git a/arch/arm/dts/exynos850-e850-96-u-boot.dtsi b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi index 3aa5d8bb10d..6d7148f7264 100644 --- a/arch/arm/dts/exynos850-e850-96-u-boot.dtsi +++ b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi @@ -3,17 +3,6 @@ * Copyright (c) 2023 Linaro Ltd. */ -&soc { - /* TODO: Remove this node once it appears in upstream dts */ - trng: rng@12081400 { - compatible = "samsung,exynos850-trng"; - reg = <0x12081400 0x100>; - clocks = <&cmu_core CLK_GOUT_SSS_ACLK>, - <&cmu_core CLK_GOUT_SSS_PCLK>; - clock-names = "secss", "pclk"; - }; -}; - &pmu_system_controller { bootph-all; samsung,uart-debug-1; diff --git a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi index a235e088fa4..3a4f7d01b9e 100644 --- a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi @@ -16,6 +16,12 @@ dmo,ram-coding-gpios = <&gpio2 8 0>, <&gpio2 1 0>, <&gpio2 0 0>; }; + clk_pcie100: clk-pcie100 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; @@ -35,6 +41,15 @@ bootph-pre-ram; }; +&pcie_phy { + clocks = <&clk_pcie100>; +}; + +&pcie0 { + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk_pcie100>; +}; + &pinctrl_hog_sbc { bootph-pre-ram; }; @@ -77,6 +92,7 @@ &gpio2 { bootph-pre-ram; + bootph-some-ram; dsi-reset-hog { bootph-pre-ram; @@ -144,8 +160,17 @@ bootph-pre-ram; }; +&usbmisc1 { + bootph-pre-ram; +}; + +&usbphynop1 { + bootph-pre-ram; +}; + &usbotg1 { dr_mode = "peripheral"; + bootph-pre-ram; }; &usdhc2 { diff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi index 805b5f57955..1e82e718b8f 100644 --- a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi @@ -64,6 +64,7 @@ &gpio3 { bootph-pre-ram; + bootph-some-ram; bl-enable-hog { bootph-pre-ram; @@ -92,6 +93,7 @@ &gpio4 { bootph-pre-ram; + bootph-some-ram; dsi-reset-hog { bootph-pre-ram; diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi index c3704d789e8..531767cfdb2 100644 --- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi @@ -13,6 +13,14 @@ }; }; +&avb1 { + status = "disabled"; +}; + +&avb2 { + status = "disabled"; +}; + &rpc { flash@0 { spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index eb82d663204..eb82d663204 100755..100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi index ef0df769762..ef0df769762 100755..100644 --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index e6d8fe6a907..e6d8fe6a907 100755..100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts diff --git a/arch/arm/mach-bcmbca/bcm47622/Kconfig b/arch/arm/mach-bcmbca/bcm47622/Kconfig index bce30892e35..56ce280a1cd 100644 --- a/arch/arm/mach-bcmbca/bcm47622/Kconfig +++ b/arch/arm/mach-bcmbca/bcm47622/Kconfig @@ -8,6 +8,7 @@ if BCM47622 config TARGET_BCM947622 bool "Broadcom 47622 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm47622" diff --git a/arch/arm/mach-bcmbca/bcm4912/Kconfig b/arch/arm/mach-bcmbca/bcm4912/Kconfig index b8c14d1dc1a..9844ddeb8b8 100644 --- a/arch/arm/mach-bcmbca/bcm4912/Kconfig +++ b/arch/arm/mach-bcmbca/bcm4912/Kconfig @@ -8,6 +8,7 @@ if BCM4912 config TARGET_BCM94912 bool "Broadcom 4912 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm4912" diff --git a/arch/arm/mach-bcmbca/bcm63146/Kconfig b/arch/arm/mach-bcmbca/bcm63146/Kconfig index 690cbf1eb20..7c26742e474 100644 --- a/arch/arm/mach-bcmbca/bcm63146/Kconfig +++ b/arch/arm/mach-bcmbca/bcm63146/Kconfig @@ -8,6 +8,7 @@ if BCM63146 config TARGET_BCM963146 bool "Broadcom 63146 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm63146" diff --git a/arch/arm/mach-bcmbca/bcm63158/Kconfig b/arch/arm/mach-bcmbca/bcm63158/Kconfig index b77444369ec..6db7b36aa32 100644 --- a/arch/arm/mach-bcmbca/bcm63158/Kconfig +++ b/arch/arm/mach-bcmbca/bcm63158/Kconfig @@ -8,6 +8,7 @@ if BCM63158 config TARGET_BCM963158 bool "Broadcom 63158 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm63158" diff --git a/arch/arm/mach-bcmbca/bcm63178/Kconfig b/arch/arm/mach-bcmbca/bcm63178/Kconfig index 73ac46284b2..167acfff2c9 100644 --- a/arch/arm/mach-bcmbca/bcm63178/Kconfig +++ b/arch/arm/mach-bcmbca/bcm63178/Kconfig @@ -8,6 +8,7 @@ if BCM63178 config TARGET_BCM963178 bool "Broadcom 63178 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm63178" diff --git a/arch/arm/mach-bcmbca/bcm6756/Kconfig b/arch/arm/mach-bcmbca/bcm6756/Kconfig index c83dcd0f3e2..bbaa45eaab0 100644 --- a/arch/arm/mach-bcmbca/bcm6756/Kconfig +++ b/arch/arm/mach-bcmbca/bcm6756/Kconfig @@ -8,6 +8,7 @@ if BCM6756 config TARGET_BCM96756 bool "Broadcom 6756 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm6756" diff --git a/arch/arm/mach-bcmbca/bcm6813/Kconfig b/arch/arm/mach-bcmbca/bcm6813/Kconfig index 25a4221bef9..0cda69cb43e 100644 --- a/arch/arm/mach-bcmbca/bcm6813/Kconfig +++ b/arch/arm/mach-bcmbca/bcm6813/Kconfig @@ -8,6 +8,7 @@ if BCM6813 config TARGET_BCM96813 bool "Broadcom 6813 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm6813" diff --git a/arch/arm/mach-bcmbca/bcm6855/Kconfig b/arch/arm/mach-bcmbca/bcm6855/Kconfig index 78087c7dd59..31eaaed7ca2 100644 --- a/arch/arm/mach-bcmbca/bcm6855/Kconfig +++ b/arch/arm/mach-bcmbca/bcm6855/Kconfig @@ -8,6 +8,7 @@ if BCM6855 config TARGET_BCM96855 bool "Broadcom 6855 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm6855" diff --git a/arch/arm/mach-bcmbca/bcm6856/Kconfig b/arch/arm/mach-bcmbca/bcm6856/Kconfig index 6ac75cb8409..7b09a1577bb 100644 --- a/arch/arm/mach-bcmbca/bcm6856/Kconfig +++ b/arch/arm/mach-bcmbca/bcm6856/Kconfig @@ -8,6 +8,7 @@ if BCM6856 config TARGET_BCM96856 bool "Broadcom 6856 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm6856" diff --git a/arch/arm/mach-bcmbca/bcm6858/Kconfig b/arch/arm/mach-bcmbca/bcm6858/Kconfig index a6504bae1f1..d32107a17a8 100644 --- a/arch/arm/mach-bcmbca/bcm6858/Kconfig +++ b/arch/arm/mach-bcmbca/bcm6858/Kconfig @@ -8,6 +8,7 @@ if BCM6858 config TARGET_BCM96858 bool "Broadcom 6858 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm6858" diff --git a/arch/arm/mach-bcmbca/bcm6878/Kconfig b/arch/arm/mach-bcmbca/bcm6878/Kconfig index 43f8942c9b1..2365cfde6ec 100644 --- a/arch/arm/mach-bcmbca/bcm6878/Kconfig +++ b/arch/arm/mach-bcmbca/bcm6878/Kconfig @@ -8,6 +8,7 @@ if BCM6878 config TARGET_BCM96878 bool "Broadcom 6878 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm6878" diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index c1a1a333e6c..adb816982f8 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -215,9 +215,16 @@ config TARGET_X530 bool "Support Allied Telesis x530" select 88F6820 +config TARGET_X250 + bool "Support Allied Telesis x250" + select ARMADA_8K + imply SCSI + imply BOOTSTD_DEFAULTS + config TARGET_X240 bool "Support Allied Telesis x240" select ALLEYCAT_5 + imply BOOTSTD_DEFAULTS config TARGET_DB_XC3_24G4XG bool "Support DB-XC3-24G4XG" @@ -301,6 +308,7 @@ config SYS_BOARD default "theadorable" if TARGET_THEADORABLE default "a38x" if TARGET_CONTROLCENTERDC default "x530" if TARGET_X530 + default "x250" if TARGET_X250 default "x240" if TARGET_X240 default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 @@ -325,6 +333,7 @@ config SYS_CONFIG_NAME default "turris_mox" if TARGET_TURRIS_MOX default "controlcenterdc" if TARGET_CONTROLCENTERDC default "x530" if TARGET_X530 + default "x250" if TARGET_X250 default "x240" if TARGET_X240 default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 @@ -349,6 +358,7 @@ config SYS_VENDOR default "CZ.NIC" if TARGET_TURRIS_MOX default "gdsys" if TARGET_CONTROLCENTERDC default "alliedtelesis" if TARGET_X530 + default "alliedtelesis" if TARGET_X250 default "alliedtelesis" if TARGET_X240 default "mikrotik" if TARGET_CRS3XX_98DX3236 default "Marvell" if TARGET_MVEBU_ALLEYCAT5 diff --git a/arch/x86/cpu/intel_common/cpu_from_spl.c b/arch/x86/cpu/intel_common/cpu_from_spl.c index 5aad2ae7309..48b2ef253cb 100644 --- a/arch/x86/cpu/intel_common/cpu_from_spl.c +++ b/arch/x86/cpu/intel_common/cpu_from_spl.c @@ -24,7 +24,9 @@ int arch_cpu_init(void) int ret; #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB) - gd->arch.hob_list = handoff_get(); + struct spl_handoff *ho = gd->spl_handoff; + + gd->arch.hob_list = ho->arch.hob_list; #endif ret = x86_cpu_reinit_f(); diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c index 4c4c8334bdb..75fa8f9de7a 100644 --- a/arch/x86/lib/fsp2/fsp_dram.c +++ b/arch/x86/lib/fsp2/fsp_dram.c @@ -59,7 +59,7 @@ int dram_init(void) #endif } else { #if CONFIG_IS_ENABLED(HANDOFF) - struct spl_handoff *ho = handoff_get(); + struct spl_handoff *ho = gd->spl_handoff; if (!ho) { log_debug("No SPL handoff found\n"); @@ -82,7 +82,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return gd->ram_size; #if CONFIG_IS_ENABLED(HANDOFF) - struct spl_handoff *ho = handoff_get(); + struct spl_handoff *ho = gd->spl_handoff; log_debug("usable_ram_top = %lx\n", ho->arch.usable_ram_top); diff --git a/board/Marvell/sheevaplug/sheevaplug.env b/board/Marvell/sheevaplug/sheevaplug.env new file mode 100644 index 00000000000..bcd62dbeb73 --- /dev/null +++ b/board/Marvell/sheevaplug/sheevaplug.env @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2024 Tony Dinh <mibodhi@gmail.com> + * + * Environment variables configurations + */ + +kernel_addr_r=0x800000 +fdt_addr_r=0x2c00000 +ramdisk_addr_r=0x01100000 +scriptaddr=0x200000 +fdtfile=CONFIG_DEFAULT_DEVICE_TREE.dtb +mtdparts=CONFIG_MTDPARTS_DEFAULT +console=ttyS0,115200 + +/* Standard Boot */ +bootcmd= + bootflow scan -lb +failed= + echo CONFIG_SYS_BOARD boot failed - please check your image diff --git a/board/alliedtelesis/x250/MAINTAINERS b/board/alliedtelesis/x250/MAINTAINERS new file mode 100644 index 00000000000..8a74dbc68b6 --- /dev/null +++ b/board/alliedtelesis/x250/MAINTAINERS @@ -0,0 +1,7 @@ +X250 BOARD +M: Chris Packham <chris.packham@alliedtelesis.co.nz> +S: Maintained +F: board/alliedtelesis/x250/ +F: arch/arm/dts/cn9130-atl-x250.dts +F: include/configs/x250.h +F: configs/x250_defconfig diff --git a/board/alliedtelesis/x250/Makefile b/board/alliedtelesis/x250/Makefile new file mode 100644 index 00000000000..98e0ccedde4 --- /dev/null +++ b/board/alliedtelesis/x250/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Allied Telesis +# + +obj-y += x250.o diff --git a/board/alliedtelesis/x250/x250.c b/board/alliedtelesis/x250/x250.c new file mode 100644 index 00000000000..66c782698ff --- /dev/null +++ b/board/alliedtelesis/x250/x250.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <config.h> +#include <asm/global_data.h> +#include <linux/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define DEVICE_BUS_SYNC_CTRL 0xF27004C8 + +int board_init(void) +{ + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + + /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */ + writel(0x00004001, DEVICE_BUS_SYNC_CTRL); + + return 0; +} diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index cf998096e45..584b5455e97 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -16,8 +16,8 @@ config VEXPRESS64_BASE_MODEL select VIRTIO_BLK if VIRTIO_MMIO select VIRTIO_NET if VIRTIO_MMIO select DM_ETH if VIRTIO_NET + imply DM_RTC imply RTC_PL031 - select DM_RTC if RTC_PL031 imply EFI_SET_TIME if DM_RTC select LINUX_KERNEL_IMAGE_HEADER select POSITION_INDEPENDENT diff --git a/board/data_modul/common/common.c b/board/data_modul/common/common.c index b5f83908771..9e35dc5d6cb 100644 --- a/board/data_modul/common/common.c +++ b/board/data_modul/common/common.c @@ -47,6 +47,9 @@ u8 dmo_get_memcfg(void) "dmo,ram-coding-gpios", gpio, ARRAY_SIZE(gpio), GPIOD_IS_IN); + if (ret < 0) + return BIT(2) | BIT(0); + for (i = 0; i < ret; i++) memcfg |= !!dm_gpio_get_value(&(gpio[i])) << i; diff --git a/board/data_modul/imx8mm_edm_sbc/spl.c b/board/data_modul/imx8mm_edm_sbc/spl.c index 17aafd719c9..a9ef049652a 100644 --- a/board/data_modul/imx8mm_edm_sbc/spl.c +++ b/board/data_modul/imx8mm_edm_sbc/spl.c @@ -61,8 +61,10 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) { if (boot_dev_spl == MMC3_BOOT) return BOOT_DEVICE_MMC2; /* eMMC */ - else + else if (boot_dev_spl == MMC2_BOOT) return BOOT_DEVICE_MMC1; /* SD */ + else + return BOOT_DEVICE_BOARD; } void board_boot_order(u32 *spl_boot_list) @@ -76,7 +78,7 @@ void board_boot_order(u32 *spl_boot_list) else spl_boot_list[1] = BOOT_DEVICE_MMC1; /* SD */ - spl_boot_list[2] = BOOT_DEVICE_UART; /* YModem */ + spl_boot_list[2] = BOOT_DEVICE_BOARD; /* SDP */ spl_boot_list[3] = BOOT_DEVICE_NONE; } diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index 6095cb02b23..e0e18b4dfea 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -48,7 +48,7 @@ struct efi_fw_image fw_images[] = { }; struct efi_capsule_update_info update_info = { - .num_images = ARRAY_SIZE(fw_images) + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README index 0d80c6901fb..0d80c6901fb 100755..100644 --- a/board/freescale/t208xqds/README +++ b/board/freescale/t208xqds/README @@ -15,10 +15,8 @@ static int do_sb_handoff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { #if CONFIG_IS_ENABLED(HANDOFF) - struct spl_handoff *handoff = handoff_get(); - - if (handoff) - printf("SPL handoff magic %lx\n", handoff->arch.magic); + if (gd->spl_handoff) + printf("SPL handoff magic %lx\n", gd->spl_handoff->arch.magic); else printf("SPL handoff info not received\n"); diff --git a/common/board_f.c b/common/board_f.c index ebc934ab810..54c48d42ee9 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -305,6 +305,17 @@ static int setup_mon_len(void) return 0; } +static int setup_spl_handoff(void) +{ +#if CONFIG_IS_ENABLED(HANDOFF) + gd->spl_handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, + sizeof(struct spl_handoff)); + debug("Found SPL hand-off info %p\n", gd->spl_handoff); +#endif + + return 0; +} + __weak int arch_cpu_init(void) { return 0; @@ -873,6 +884,7 @@ static const init_fnc_t init_sequence_f[] = { initf_bootstage, /* uses its own timer, so does not need DM */ event_init, bloblist_maybe_init, + setup_spl_handoff, #if defined(CONFIG_CONSOLE_RECORD_INIT_F) console_record_init, #endif diff --git a/common/board_r.c b/common/board_r.c index ff9bce88dc9..23ebc41868c 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -152,6 +152,15 @@ static int initr_reloc_global_data(void) */ gd->env_addr += gd->reloc_off; #endif + + /* + * For CONFIG_OF_EMBED case the FDT is embedded into ELF, available by + * __dtb_dt_begin. After U-boot ELF self-relocation to RAM top address + * it is worth to update fdt_blob in global_data + */ + if (IS_ENABLED(CONFIG_OF_EMBED)) + gd->fdt_blob = dtb_dt_embedded(); + #ifdef CONFIG_EFI_LOADER /* * On the ARM architecture gd is mapped to a fixed register (r9 or x18). diff --git a/common/init/handoff.c b/common/init/handoff.c index 86c020ee0b9..a7cd065fb38 100644 --- a/common/init/handoff.c +++ b/common/init/handoff.c @@ -5,7 +5,6 @@ * Copyright 2018 Google, Inc */ -#include <bloblist.h> #include <handoff.h> #include <asm/global_data.h> @@ -39,14 +38,3 @@ void handoff_load_dram_banks(struct spl_handoff *ho) bd->bi_dram[i].size = ho->ram_bank[i].size; } } - -struct spl_handoff *handoff_get(void) -{ - struct spl_handoff *handoff; - - handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, - sizeof(struct spl_handoff)); - debug("Found SPL hand-off info %p\n", handoff); - - return handoff; -} diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 045fcac10a5..240543c9c7e 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -462,6 +462,7 @@ config SPL_CUSTOM_SYS_MALLOC_ADDR config SPL_SYS_MALLOC_SIZE hex "Size of the SPL malloc pool" depends on SPL_SYS_MALLOC + default 0x180000 if BIOSEMU && RISCV default 0x100000 config SPL_READ_ONLY diff --git a/configs/bcm947622_defconfig b/configs/bcm947622_defconfig index 71057f1dc04..566f9f2920f 100644 --- a/configs/bcm947622_defconfig +++ b/configs/bcm947622_defconfig @@ -8,7 +8,7 @@ CONFIG_TARGET_BCM947622=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm947622" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm947622" CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM47622" @@ -16,6 +16,12 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm94912_defconfig b/configs/bcm94912_defconfig index 5b6de30cd8b..46bbfb67980 100644 --- a/configs/bcm94912_defconfig +++ b/configs/bcm94912_defconfig @@ -9,13 +9,19 @@ CONFIG_TARGET_BCM94912=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm94912" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm94912" CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM4912" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm963146_defconfig b/configs/bcm963146_defconfig index 5033b069d7d..239a8a10fa5 100644 --- a/configs/bcm963146_defconfig +++ b/configs/bcm963146_defconfig @@ -9,13 +9,19 @@ CONFIG_TARGET_BCM963146=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm963146" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm963146" CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM63146" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm963158_defconfig b/configs/bcm963158_defconfig index c3010d97908..a6cfea6cd79 100644 --- a/configs/bcm963158_defconfig +++ b/configs/bcm963158_defconfig @@ -9,13 +9,19 @@ CONFIG_TARGET_BCM963158=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm963158" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm963158" CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM63158" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm963178_defconfig b/configs/bcm963178_defconfig index 1409febae14..95c9c8e396e 100644 --- a/configs/bcm963178_defconfig +++ b/configs/bcm963178_defconfig @@ -9,7 +9,7 @@ CONFIG_TARGET_BCM963178=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm963178" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm963178" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM63178" @@ -17,6 +17,12 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm96756_defconfig b/configs/bcm96756_defconfig index 96a9a311037..bfd309c25f5 100644 --- a/configs/bcm96756_defconfig +++ b/configs/bcm96756_defconfig @@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96756=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm96756" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96756" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM6756" @@ -17,6 +17,12 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm96813_defconfig b/configs/bcm96813_defconfig index eadcb6374c6..7f165231648 100644 --- a/configs/bcm96813_defconfig +++ b/configs/bcm96813_defconfig @@ -9,13 +9,19 @@ CONFIG_TARGET_BCM96813=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm96813" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96813" CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM6813" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm96855_defconfig b/configs/bcm96855_defconfig index 6ffae45faa2..342be0a0e17 100644 --- a/configs/bcm96855_defconfig +++ b/configs/bcm96855_defconfig @@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96855=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm96855" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96855" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM6855" @@ -17,6 +17,12 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm96856_defconfig b/configs/bcm96856_defconfig index f926b3770f0..5f22186966f 100644 --- a/configs/bcm96856_defconfig +++ b/configs/bcm96856_defconfig @@ -9,13 +9,19 @@ CONFIG_TARGET_BCM96856=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm96856" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96856" CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM6856" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm96858_defconfig b/configs/bcm96858_defconfig index cc6069fe794..682cb14e898 100644 --- a/configs/bcm96858_defconfig +++ b/configs/bcm96858_defconfig @@ -9,13 +9,19 @@ CONFIG_TARGET_BCM96858=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm96858" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96858" CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM6858" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm96878_defconfig b/configs/bcm96878_defconfig index 7d1cd6c944f..ad65187c30c 100644 --- a/configs/bcm96878_defconfig +++ b/configs/bcm96878_defconfig @@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96878=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm96878" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96878" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM6878" @@ -17,6 +17,12 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index 323e2f5d4c8..1ba02e0595f 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -33,7 +33,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:896k(u-boot),128k(u-boot-env),5m(kernel),-(rootfs)" diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index e35ca165d0f..941156750ac 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -33,7 +33,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),-(root)" diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig index 25e5be3ba7d..44e9b176827 100644 --- a/configs/ds414_defconfig +++ b/configs/ds414_defconfig @@ -49,7 +49,6 @@ CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_ENV_OVERWRITE=y diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig index 5797c6cb1f9..c36196c510c 100644 --- a/configs/e850-96_defconfig +++ b/configs/e850-96_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y +CONFIG_ARM_SMCCC=y CONFIG_ARCH_EXYNOS=y CONFIG_TEXT_BASE=0xf8800000 CONFIG_SYS_MALLOC_LEN=0x81f000 @@ -9,6 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000 CONFIG_DEFAULT_DEVICE_TREE="exynos/exynos850-e850-96" CONFIG_SYS_LOAD_ADDR=0x80000000 +# CONFIG_PSCI_RESET is not set CONFIG_ANDROID_BOOT_IMAGE=y # CONFIG_AUTOBOOT is not set # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index af758fcc431..add4a24a31d 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),6M(uImage),-(root)" diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index 0fab4c38e0e..540b9184b38 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:896K(uboot),128K(uboot_env),-@1M(root)" diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index 9d195e1cf2d..6ee40e380b2 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x80000@0x0(uboot),0x20000@0x80000(uboot_env),-@0xa0000(rootfs)" diff --git a/configs/imx8m_data_modul.config b/configs/imx8m_data_modul.config new file mode 100644 index 00000000000..2164c754915 --- /dev/null +++ b/configs/imx8m_data_modul.config @@ -0,0 +1,221 @@ +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_INPUT is not set +# CONFIG_SPI_FLASH_UNLOCK_ALL is not set +# CONFIG_SPL_DM_USB is not set +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_ARCH_IMX8M=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_ARM=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset" +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_BKOPS_ENABLE=y +CONFIG_CMD_BOOTCOUNT=y +CONFIG_CMD_BTRFS=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_CAT=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_FS_UUID=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +CONFIG_CMD_KASLRSEED=y +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MBR=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y +CONFIG_CMD_PART=y +CONFIG_CMD_PING=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_PXE=y +CONFIG_CMD_READ=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_SMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_UUID=y +CONFIG_CMD_WGET=y +CONFIG_CMD_XXD=y +CONFIG_CONSOLE_MUX=y +CONFIG_CRC32_VERIFY=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x30880000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DFU_MMC=y +CONFIG_DFU_MTD=y +CONFIG_DFU_RAM=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_TIMEOUT=y +CONFIG_DM_ETH_PHY=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MDIO=y +CONFIG_DM_MTD=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_DM_RTC=y +CONFIG_DM_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_THERMAL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_OFFSET=0xFFFC0000 +CONFIG_ENV_OFFSET_REDUND=0xFFFC0000 +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FEC_MXC=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_FSL_CAAM=y +CONFIG_FSL_USDHC=y +CONFIG_GPIO_HOG=y +CONFIG_HASH_VERIFY=y +CONFIG_HUSH_PARSER=y +CONFIG_I2C_EEPROM=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX_BOOTAUX=y +CONFIG_IMX_TMU=y +CONFIG_IMX_WATCHDOG=y +CONFIG_IPV6=y +CONFIG_IP_DEFRAG=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_MII=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_SPEED_MODE_SET=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MTD=y +CONFIG_MTDIDS_DEFAULT="nor0=flash@0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)" +CONFIG_MXC_GPIO=y +CONFIG_MXC_SPI=y +CONFIG_MXC_UART=y +CONFIG_NETCONSOLE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_OF_CONTROL=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_PHY_ANEG_TIMEOUT=20000 +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_BROADCOM=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_PROT_TCP_SACK=y +CONFIG_REGMAP=y +CONFIG_RGMII=y +CONFIG_RTC_M41T62=y +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SHA1SUM_VERIFY=y +CONFIG_SPI=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPL=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_GPIO=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_I2C=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_PINCTRL=y +CONFIG_SPL_POWER=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_SYSRESET=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYSCON=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 +CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 +CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y +CONFIG_SYS_BOOTM_LEN=0x8000000 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 +CONFIG_SYS_EEPROM_SIZE=16384 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_SYS_MONITOR_LEN=1048576 +CONFIG_SYS_PBSIZE=2081 +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_TFTP_TSIZE=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_FUNCTION_ACM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Data Modul" +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_HUB_USB251XB=y +CONFIG_USB_STORAGE=y +CONFIG_USE_BOOTARGS=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_USE_PREBOOT=y +CONFIG_VERSION_VARIABLE=y diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index 105fbfb4d9b..66cb1331ded 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -1,242 +1,39 @@ +#include <configs/imx8m_data_modul.config> + CONFIG_ARM=y CONFIG_ARCH_IMX8M=y -CONFIG_TEXT_BASE=0x40200000 -CONFIG_SYS_MALLOC_LEN=0x1000000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SF_DEFAULT_SPEED=50000000 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_OFFSET=0xFFFC0000 -CONFIG_IMX_CONFIG="board/data_modul/imx8mm_edm_sbc/imximage.cfg" -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mm-data-modul-edm-sbc" CONFIG_TARGET_IMX8MM_DATA_MODUL_EDM_SBC=y -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_DM_RESET=y -CONFIG_SYS_MONITOR_LEN=1048576 -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 -CONFIG_SPL_STACK=0x920000 -CONFIG_SPL_TEXT_BASE=0x7E1000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 -CONFIG_SYS_BOOTM_LEN=0x8000000 -CONFIG_SYS_LOAD_ADDR=0x60000000 -CONFIG_SPL=y -CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y -CONFIG_ENV_OFFSET_REDUND=0xFFFC0000 -CONFIG_IMX_BOOTAUX=y -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_FIT=y -CONFIG_FIT_EXTERNAL_OFFSET=0x3000 -CONFIG_SPL_LOAD_FIT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_USE_BOOTARGS=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset" -CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="run dmo_preboot" -CONFIG_DEFAULT_FDT_FILE="imx8mm-data-modul-edm-sbc.dtb" -CONFIG_SYS_CBSIZE=2048 -CONFIG_SYS_PBSIZE=2074 -CONFIG_CONSOLE_MUX=y -CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_LATE_INIT=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_SPL_LEGACY_IMAGE_FORMAT=y -CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 -CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 -CONFIG_SPL_I2C=y -CONFIG_SPL_POWER=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_WATCHDOG=y -CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="u-boot=> " -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_EXPORTENV is not set -CONFIG_CMD_ERASEENV=y -CONFIG_CRC32_VERIFY=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_SIZE=16384 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 -CONFIG_CMD_MD5SUM=y -CONFIG_MD5SUM_VERIFY=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_SHA1SUM=y -CONFIG_SHA1SUM_VERIFY=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FUSE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_GPT_RENAME=y -CONFIG_CMD_I2C=y -CONFIG_CMD_LSBLK=y -CONFIG_CMD_MBR=y -CONFIG_CMD_MMC=y -CONFIG_CMD_BKOPS_ENABLE=y -CONFIG_MMC_SPEED_MODE_SET=y -CONFIG_CMD_MTD=y -CONFIG_CMD_PART=y -CONFIG_CMD_READ=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_SDP=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_CAT=y -CONFIG_CMD_XXD=y -CONFIG_CMD_DHCP6=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_WGET=y -CONFIG_CMD_PXE=y -CONFIG_CMD_BOOTCOUNT=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_GETTIME=y -CONFIG_CMD_KASLRSEED=y -CONFIG_CMD_SYSBOOT=y -CONFIG_CMD_UUID=y -CONFIG_CMD_PMIC=y -CONFIG_CMD_REGULATOR=y -CONFIG_CMD_SMC=y -CONFIG_HASH_VERIFY=y -CONFIG_CMD_BTRFS=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_FS_UUID=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y -CONFIG_MTDIDS_DEFAULT="nor0=flash@0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)" -CONFIG_PARTITION_TYPE_GUID=y -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_IP_DEFRAG=y -CONFIG_TFTP_TSIZE=y -CONFIG_PROT_TCP_SACK=y -CONFIG_IPV6=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_REGMAP=y -CONFIG_SYSCON=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 -CONFIG_SPL_CLK_COMPOSITE_CCF=y -CONFIG_CLK_COMPOSITE_CCF=y -CONFIG_SPL_CLK_IMX8MM=y +CONFIG_CI_UDC=y CONFIG_CLK_IMX8MM=y -CONFIG_FSL_CAAM=y -CONFIG_DFU_TFTP=y -CONFIG_DFU_TIMEOUT=y -CONFIG_DFU_MMC=y -CONFIG_DFU_MTD=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x42800000 -CONFIG_FASTBOOT_BUF_SIZE=0x20000000 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_GPIO_HOG=y -CONFIG_MXC_GPIO=y -CONFIG_DM_I2C=y -# CONFIG_INPUT is not set -CONFIG_USB_HUB_USB251XB=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_MMC_IO_VOLTAGE=y -CONFIG_SPL_MMC_IO_VOLTAGE=y -CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS400_ES_SUPPORT=y -CONFIG_MMC_HS400_SUPPORT=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_DM_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_SFDP_SUPPORT=y -# CONFIG_SPI_FLASH_UNLOCK_ALL is not set -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_PHYLIB=y -CONFIG_PHY_ANEG_TIMEOUT=20000 -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_DM_MDIO=y -CONFIG_DM_ETH_PHY=y -CONFIG_FEC_MXC=y -CONFIG_RGMII=y -CONFIG_MII=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_IMX8M=y -CONFIG_POWER_DOMAIN=y -CONFIG_IMX8M_POWER_DOMAIN=y -CONFIG_DM_PMIC=y +CONFIG_CMD_PCI=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-data-modul-edm-sbc" +CONFIG_DEFAULT_FDT_FILE="imx8mm-data-modul-edm-sbc.dtb" CONFIG_DM_PMIC_BD71837=y -CONFIG_SPL_DM_PMIC_BD71837=y -CONFIG_DM_REGULATOR=y -CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_BD71837=y +CONFIG_IMX_CONFIG="board/data_modul/imx8mm_edm_sbc/imximage.cfg" +CONFIG_NVME_PCI=y +CONFIG_PCI=y +CONFIG_PCIE_DW_IMX=y +CONFIG_PHY=y +CONFIG_PHYLIB=y +CONFIG_PHY_IMX8M_PCIE=y +CONFIG_PREBOOT="run dmo_preboot" +CONFIG_SDP_LOADADDR=0x60000000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_CLK_IMX8MM=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 +CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_SPL_DM_REGULATOR_BD71837=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_DM_RNG=y -CONFIG_DM_RTC=y -CONFIG_RTC_M41T62=y -CONFIG_DM_SERIAL=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_MXC_SPI=y -CONFIG_SYSRESET=y -CONFIG_SPL_SYSRESET=y -CONFIG_SYSRESET_PSCI=y -CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_TMU=y -CONFIG_USB=y -# CONFIG_SPL_DM_USB is not set -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Data Modul" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y -CONFIG_USB_FUNCTION_ACM=y -CONFIG_IMX_WATCHDOG=y +CONFIG_SPL_DM_USB=y +CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y +CONFIG_SPL_LEGACY_IMAGE_FORMAT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SYS_LOAD_ADDR=0x60000000 diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig index f809d23d6d2..ea8109bf049 100644 --- a/configs/imx8mp_data_modul_edm_sbc_defconfig +++ b/configs/imx8mp_data_modul_edm_sbc_defconfig @@ -1,271 +1,54 @@ +#include <configs/imx8m_data_modul.config> + CONFIG_ARM=y CONFIG_ARCH_IMX8M=y -CONFIG_TEXT_BASE=0x40200000 -CONFIG_SYS_MALLOC_LEN=0x1000000 -CONFIG_SYS_MALLOC_F_LEN=0x18000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SF_DEFAULT_SPEED=50000000 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_OFFSET=0xFFFC0000 -CONFIG_DM_GPIO=y -CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mp-data-modul-edm-sbc" CONFIG_TARGET_IMX8MP_DATA_MODUL_EDM_SBC=y -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_DM_RESET=y -CONFIG_SYS_MONITOR_LEN=1048576 -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 -CONFIG_SPL_STACK=0x96fc00 -CONFIG_SPL_TEXT_BASE=0x920000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x96fc00 -CONFIG_SPL_BSS_MAX_SIZE=0x400 -CONFIG_SYS_BOOTM_LEN=0x8000000 -CONFIG_SYS_LOAD_ADDR=0x50000000 -CONFIG_SPL=y -CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y -CONFIG_DEBUG_UART_BASE=0x30880000 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_ENV_OFFSET_REDUND=0xFFFC0000 -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI=y -CONFIG_IMX_BOOTAUX=y -CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 -CONFIG_DEBUG_UART=y -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_FIT=y -CONFIG_FIT_EXTERNAL_OFFSET=0x3000 -CONFIG_SPL_LOAD_FIT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_USE_BOOTARGS=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset" -CONFIG_USE_PREBOOT=y +CONFIG_CLK_IMX8MP=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-data-modul-edm-sbc" CONFIG_DEFAULT_FDT_FILE="imx8mp-data-modul-edm-sbc.dtb" -CONFIG_SYS_CBSIZE=2048 -CONFIG_SYS_PBSIZE=2081 -CONFIG_CONSOLE_MUX=y -CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_MAX_SIZE=0x25000 -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_BOOTROM_SUPPORT=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 -CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 -CONFIG_SPL_I2C=y -CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_POWER=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000 -CONFIG_SPL_WATCHDOG=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="u-boot=> " -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_EXPORTENV is not set -CONFIG_CMD_ERASEENV=y -CONFIG_CRC32_VERIFY=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_SIZE=16384 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 -CONFIG_CMD_MD5SUM=y -CONFIG_MD5SUM_VERIFY=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_SHA1SUM=y -CONFIG_SHA1SUM_VERIFY=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FUSE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_GPT_RENAME=y -CONFIG_CMD_I2C=y -CONFIG_CMD_LSBLK=y -CONFIG_CMD_MBR=y -CONFIG_CMD_MMC=y -CONFIG_CMD_BKOPS_ENABLE=y -CONFIG_MMC_SPEED_MODE_SET=y -CONFIG_CMD_MTD=y -CONFIG_CMD_PART=y -CONFIG_CMD_READ=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_SDP=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_CAT=y -CONFIG_CMD_XXD=y -CONFIG_CMD_DHCP6=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_WGET=y -CONFIG_CMD_PXE=y -CONFIG_CMD_BOOTCOUNT=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_GETTIME=y -CONFIG_CMD_KASLRSEED=y -CONFIG_CMD_SYSBOOT=y -CONFIG_CMD_UUID=y -CONFIG_CMD_PMIC=y -CONFIG_CMD_REGULATOR=y -CONFIG_CMD_SMC=y -CONFIG_HASH_VERIFY=y -CONFIG_CMD_BTRFS=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_FS_UUID=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y -CONFIG_MTDIDS_DEFAULT="nor0=flash@0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)" -CONFIG_PARTITION_TYPE_GUID=y -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_DM_USB_GADGET=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y CONFIG_ENV_IS_NOWHERE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_IP_DEFRAG=y -CONFIG_TFTP_TSIZE=y -CONFIG_PROT_TCP_SACK=y -CONFIG_IPV6=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_REGMAP=y -CONFIG_SYSCON=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 -CONFIG_SPL_CLK_COMPOSITE_CCF=y -CONFIG_CLK_COMPOSITE_CCF=y -CONFIG_SPL_CLK_IMX8MP=y -CONFIG_CLK_IMX8MP=y -CONFIG_FSL_CAAM=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y CONFIG_IMX8M_DRAM_INLINE_ECC=y -CONFIG_DFU_TFTP=y -CONFIG_DFU_TIMEOUT=y -CONFIG_DFU_MMC=y -CONFIG_DFU_MTD=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x42800000 -CONFIG_FASTBOOT_BUF_SIZE=0x20000000 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_GPIO_HOG=y -CONFIG_SPL_GPIO_HOG=y -CONFIG_MXC_GPIO=y -CONFIG_DM_I2C=y -# CONFIG_INPUT is not set CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y -CONFIG_USB_HUB_USB251XB=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_MMC_IO_VOLTAGE=y -CONFIG_SPL_MMC_IO_VOLTAGE=y -CONFIG_MMC_UHS_SUPPORT=y -CONFIG_SPL_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS400_ES_SUPPORT=y -CONFIG_MMC_HS400_SUPPORT=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_DM_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_SFDP_SUPPORT=y -# CONFIG_SPI_FLASH_UNLOCK_ALL is not set -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_PHY_ANEG_TIMEOUT=20000 -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y +CONFIG_PHY_IMX8MQ_USB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_DM_MDIO=y -CONFIG_DM_ETH_PHY=y -CONFIG_DWC_ETH_QOS=y -CONFIG_DWC_ETH_QOS_IMX=y -CONFIG_FEC_MXC=y -CONFIG_RGMII=y -CONFIG_MII=y -CONFIG_PHY_IMX8MQ_USB=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_IMX8M=y -CONFIG_POWER_DOMAIN=y -CONFIG_IMX8M_POWER_DOMAIN=y -CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y -CONFIG_DM_PMIC=y -CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL_BSS_START_ADDR=0x96fc00 +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000 CONFIG_SPL_DM_PMIC_PCA9450=y -CONFIG_DM_REGULATOR=y -CONFIG_SPL_DM_REGULATOR=y -CONFIG_DM_REGULATOR_PCA9450=y CONFIG_SPL_DM_REGULATOR_PCA9450=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_DM_RNG=y -CONFIG_DM_RTC=y -CONFIG_RTC_M41T62=y -CONFIG_DM_SERIAL=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_MXC_SPI=y -CONFIG_SYSRESET=y -CONFIG_SPL_SYSRESET=y -CONFIG_SYSRESET_PSCI=y -CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_TMU=y -CONFIG_USB=y -# CONFIG_SPL_DM_USB is not set -CONFIG_DM_USB_GADGET=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y -CONFIG_USB_EHCI_HCD=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_GPIO_HOG=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_STACK=0x96fc00 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_SYS_LOAD_ADDR=0x50000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000 CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Data Modul" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_USB_FUNCTION_ACM=y CONFIG_USB_ETHER=y +CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETH_CDC=y -CONFIG_IMX_WATCHDOG=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_XHCI_HCD=y diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index 783879d4eec..ca70ee96379 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xa0000@0x0(uboot),0x010000@0xa0000(env),0x500000@0xc0000(uimage),0x1a40000@0x5c0000(rootfs)" @@ -66,5 +65,3 @@ CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_NAND=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index f6718350d58..9a42c391556 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -30,7 +30,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(root)" diff --git a/configs/nsa325_defconfig b/configs/nsa325_defconfig index c4235eecfb5..ab9316340d8 100644 --- a/configs/nsa325_defconfig +++ b/configs/nsa325_defconfig @@ -42,7 +42,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_SNTP=y CONFIG_CMD_DNS=y # CONFIG_CMD_BLOCK_CACHE is not set -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x100000(uboot),0x80000(stock_uboot_env),0x80000(key_store),0x80000(info),0xA00000(etc),0xA00000(kernel_1),0x2FC0000(rootfs1),0xA00000(kernel_2),0x2FC0000(rootfs2)" @@ -73,6 +72,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y CONFIG_USB_EHCI_HCD=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_NAND=y CONFIG_UBIFS_SILENCE_MSG=y diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 0b0cf176324..43b0dac5efd 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -71,8 +71,8 @@ CONFIG_CMD_RTC=y CONFIG_CMD_SMC=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_MULTI_DTB_FIT=y CONFIG_OF_OVERLAY_LIST="ti/k3-am6xx-phycore-disable-spi-nor ti/k3-am6xx-phycore-disable-rtc ti/k3-am6xx-phycore-disable-eth-phy ti/k3-am6xx-phycore-qspi-nor" +CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index 50103f375a1..50c92925506 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -32,7 +32,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1M(u-boot),4M(uImage),32M(rootfs),-(data)" diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig index fb8036a75e1..03b4fd9b2fc 100644 --- a/configs/pogo_v4_defconfig +++ b/configs/pogo_v4_defconfig @@ -41,7 +41,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_SNTP=y CONFIG_CMD_DNS=y # CONFIG_CMD_BLOCK_CACHE is not set -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:2M(u-boot),3M(uImage),3M(uImage2),8M(failsafe),112M(root)" @@ -73,6 +72,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y CONFIG_USB_EHCI_HCD=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_NAND=y CONFIG_UBIFS_SILENCE_MSG=y diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 30f7b1c773f..cd94315f176 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -129,4 +129,3 @@ CONFIG_VIDEO_FONT_16X32=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_NO_FB_CLEAR=y CONFIG_VIDEO_SIMPLE=y -CONFIG_HEXDUMP=y diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 8dffb91e93b..06ac6fed3bc 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -3,7 +3,6 @@ CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_QEMU=y CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index cc4f4540fd5..e164407d494 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -3,7 +3,6 @@ CONFIG_ARM_SMCCC=y CONFIG_ARCH_QEMU=y CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 9ac40b9e571..a7f6c73ecba 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -16,16 +16,14 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-sheevaplug" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_IDENT_STRING="\nMarvell-Sheevaplug" +CONFIG_LTO=y CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=524288 +CONFIG_BOOTSTD_FULL=y CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; bootm 0x6400000;" CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set @@ -35,19 +33,10 @@ CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)" CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y @@ -68,6 +57,5 @@ CONFIG_DM_RTC=y CONFIG_RTC_MV=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_LZMA=y CONFIG_BZIP2=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 058e5fab683..4fed7eda948 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -42,6 +42,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_SPI_LOAD=y +CONFIG_CMD_ERASEENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_PWM=y @@ -58,6 +59,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x54 CONFIG_SPI_FLASH_ISSI=y CONFIG_E1000=y CONFIG_NVME_PCI=y +CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PCIE_DW_SIFIVE=y CONFIG_SCSI=y CONFIG_USB=y diff --git a/configs/x240_defconfig b/configs/x240_defconfig index f930d28de2d..ff64916204c 100644 --- a/configs/x240_defconfig +++ b/configs/x240_defconfig @@ -27,16 +27,12 @@ CONFIG_CMD_PCI=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_REGULATOR=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_IPV6=y CONFIG_CLK=y CONFIG_CLK_MVEBU=y CONFIG_GPIO_HOG=y @@ -74,7 +70,6 @@ CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y @@ -83,3 +78,4 @@ CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y # CONFIG_FAT_WRITE is not set # CONFIG_SMBIOS is not set +# CONFIG_TOOLS_MKEFICAPSULE is not set diff --git a/configs/x250_defconfig b/configs/x250_defconfig new file mode 100644 index 00000000000..dffe85bd6eb --- /dev/null +++ b/configs/x250_defconfig @@ -0,0 +1,104 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_MVEBU=y +CONFIG_TEXT_BASE=0x00000000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 +CONFIG_TARGET_X250=y +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0xf80000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="cn9130-atl-x250" +CONFIG_SYS_LOAD_ADDR=0x10000000 +CONFIG_DEBUG_UART_BASE=0xf0512000 +CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd" +CONFIG_USE_PREBOOT=y +CONFIG_SPL_SILENT_CONSOLE=y +CONFIG_TPL_SILENT_CONSOLE=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_UBI=y +CONFIG_MAC_PARTITION=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ARP_TIMEOUT=200 +CONFIG_NET_RETRY_COUNT=50 +CONFIG_IPV6=y +CONFIG_SYS_64BIT_LBA=y +CONFIG_GPIO_HOG=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +# CONFIG_INPUT is not set +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +# CONFIG_MMC is not set +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_NAND_PXA3XX=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_MVPP2=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_MVEBU=y +CONFIG_PHY=y +CONFIG_MVEBU_COMPHY_SUPPORT=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_8K=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_RTC_MAX313XX=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_KIRKWOOD_SPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +# CONFIG_TOOLS_MKEFICAPSULE is not set diff --git a/configs/x530_defconfig b/configs/x530_defconfig index 89612be631e..815370c90ec 100644 --- a/configs/x530_defconfig +++ b/configs/x530_defconfig @@ -65,6 +65,7 @@ CONFIG_CMD_UBI=y CONFIG_ENV_OVERWRITE=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 +CONFIG_IPV6=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y @@ -95,3 +96,4 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_WDT=y CONFIG_WDT_ORION=y CONFIG_SPL_TINY_MEMSET=y +# CONFIG_TOOLS_MKEFICAPSULE is not set diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index c742c2f8e20..9f9252b18d2 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -73,7 +73,7 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2025.01-rc3 was released on Mon 25 November 2024. -.. * U-Boot v2025.01-rc4 was released on Mon 09 December 2024. +* U-Boot v2025.01-rc4 was released on Mon 09 December 2024. .. * U-Boot v2025.01-rc5 was released on Mon 23 December 2024. diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index c8735d869cf..3c5340df8ee 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -69,7 +69,15 @@ static int rzg2l_cpg_clk_set(struct clk *clk, bool enable) dev_dbg(clk->dev, "%s %s clock %u\n", enable ? "enable" : "disable", is_mod_clk(clk->id) ? "module" : "core", cpg_clk_id); + if (!is_mod_clk(clk->id)) { + /* + * Non-module clocks are always on. Ignore attempts to enable + * them and reject attempts to disable them. + */ + if (enable) + return 0; + dev_err(clk->dev, "ID %lu is not a module clock\n", clk->id); return -EINVAL; } diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 155ea8d6353..6e87db18be0 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -8,7 +8,6 @@ #include <dm.h> #include <dt-structs.h> #include <errno.h> -#include <handoff.h> #include <log.h> #include <malloc.h> #include <mapmem.h> @@ -1468,7 +1467,7 @@ static int rk3399_clk_probe(struct udevice *dev) init_clocks = true; #elif CONFIG_IS_ENABLED(HANDOFF) if (!(gd->flags & GD_FLG_RELOC)) { - if (!handoff_get()) + if (!(gd->spl_handoff)) init_clocks = true; } #endif diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c index 93cbd598e02..9c2ce65a4e5 100644 --- a/drivers/fastboot/fb_getvar.c +++ b/drivers/fastboot/fb_getvar.c @@ -230,7 +230,8 @@ static void __maybe_unused getvar_partition_type(char *part_name, char *response if (r >= 0) { r = fs_set_blk_dev_with_part(dev_desc, r); if (r < 0) - fastboot_fail("failed to set partition", response); + /* If we don't know then just default to raw */ + fastboot_okay("raw", response); else fastboot_okay(fs_get_type_name(), response); } diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index c345fc1f1fb..609bdffbf77 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -133,36 +133,12 @@ config NAND_BRCMNAND_6368 help Enable support for broadcom nand driver on bcm6368. -config NAND_BRCMNAND_6753 - bool "Support Broadcom NAND controller on bcm6753" - depends on NAND_BRCMNAND && BCM6855 - help - Enable support for broadcom nand driver on bcm6753. - -config NAND_BRCMNAND_68360 - bool "Support Broadcom NAND controller on bcm68360" - depends on NAND_BRCMNAND && BCM6856 - help - Enable support for broadcom nand driver on bcm68360. - config NAND_BRCMNAND_6838 bool "Support Broadcom NAND controller on bcm6838" depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838 help Enable support for broadcom nand driver on bcm6838. -config NAND_BRCMNAND_6858 - bool "Support Broadcom NAND controller on bcm6858" - depends on NAND_BRCMNAND && BCM6858 - help - Enable support for broadcom nand driver on bcm6858. - -config NAND_BRCMNAND_63158 - bool "Support Broadcom NAND controller on bcm63158" - depends on NAND_BRCMNAND && BCM63158 - help - Enable support for broadcom nand driver on bcm63158. - config NAND_BRCMNAND_IPROC bool "Support Broadcom NAND controller on the iproc family" depends on NAND_BRCMNAND diff --git a/drivers/mtd/nand/raw/brcmnand/Makefile b/drivers/mtd/nand/raw/brcmnand/Makefile index 24d0d568449..4fba5c1c7e3 100644 --- a/drivers/mtd/nand/raw/brcmnand/Makefile +++ b/drivers/mtd/nand/raw/brcmnand/Makefile @@ -1,11 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_NAND_BRCMNAND_6368) += bcm6368_nand.o -obj-$(CONFIG_NAND_BRCMNAND_63158) += bcm63158_nand.o -obj-$(CONFIG_NAND_BRCMNAND_6753) += bcm6753_nand.o -obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o -obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o obj-$(CONFIG_NAND_BRCMNAND_BCMBCA) += bcmbca_nand.o obj-$(CONFIG_NAND_BRCMNAND_IPROC) += iproc_nand.o obj-$(CONFIG_NAND_BRCMNAND) += brcmnand.o diff --git a/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c deleted file mode 100644 index 3f59fbbbb8f..00000000000 --- a/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include <asm/io.h> -#include <memalign.h> -#include <nand.h> -#include <linux/bitops.h> -#include <linux/err.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/ioport.h> -#include <dm.h> -#include <linux/printk.h> - -#include "brcmnand.h" - -struct bcm63158_nand_soc { - struct brcmnand_soc soc; - void __iomem *base; -}; - -#define BCM63158_NAND_INT 0x00 -#define BCM63158_NAND_STATUS_SHIFT 0 -#define BCM63158_NAND_STATUS_MASK (0xfff << BCM63158_NAND_STATUS_SHIFT) - -#define BCM63158_NAND_INT_EN 0x04 -#define BCM63158_NAND_ENABLE_SHIFT 0 -#define BCM63158_NAND_ENABLE_MASK (0xffff << BCM63158_NAND_ENABLE_SHIFT) - -enum { - BCM63158_NP_READ = BIT(0), - BCM63158_BLOCK_ERASE = BIT(1), - BCM63158_COPY_BACK = BIT(2), - BCM63158_PAGE_PGM = BIT(3), - BCM63158_CTRL_READY = BIT(4), - BCM63158_DEV_RBPIN = BIT(5), - BCM63158_ECC_ERR_UNC = BIT(6), - BCM63158_ECC_ERR_CORR = BIT(7), -}; - -static bool bcm63158_nand_intc_ack(struct brcmnand_soc *soc) -{ - struct bcm63158_nand_soc *priv = - container_of(soc, struct bcm63158_nand_soc, soc); - void __iomem *mmio = priv->base + BCM63158_NAND_INT; - u32 val = brcmnand_readl(mmio); - - if (val & (BCM63158_CTRL_READY << BCM63158_NAND_STATUS_SHIFT)) { - /* Ack interrupt */ - val &= ~BCM63158_NAND_STATUS_MASK; - val |= BCM63158_CTRL_READY << BCM63158_NAND_STATUS_SHIFT; - brcmnand_writel(val, mmio); - return true; - } - - return false; -} - -static void bcm63158_nand_intc_set(struct brcmnand_soc *soc, bool en) -{ - struct bcm63158_nand_soc *priv = - container_of(soc, struct bcm63158_nand_soc, soc); - void __iomem *mmio = priv->base + BCM63158_NAND_INT_EN; - u32 val = brcmnand_readl(mmio); - - /* Don't ack any interrupts */ - val &= ~BCM63158_NAND_STATUS_MASK; - - if (en) - val |= BCM63158_CTRL_READY << BCM63158_NAND_ENABLE_SHIFT; - else - val &= ~(BCM63158_CTRL_READY << BCM63158_NAND_ENABLE_SHIFT); - - brcmnand_writel(val, mmio); -} - -static int bcm63158_nand_probe(struct udevice *dev) -{ - struct udevice *pdev = dev; - struct bcm63158_nand_soc *priv = dev_get_priv(dev); - struct brcmnand_soc *soc; - struct resource res; - - soc = &priv->soc; - - dev_read_resource_byname(pdev, "nand-int-base", &res); - priv->base = devm_ioremap(dev, res.start, resource_size(&res)); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - - soc->ctlrdy_ack = bcm63158_nand_intc_ack; - soc->ctlrdy_set_enabled = bcm63158_nand_intc_set; - - /* Disable and ack all interrupts */ - brcmnand_writel(0, priv->base + BCM63158_NAND_INT_EN); - brcmnand_writel(0, priv->base + BCM63158_NAND_INT); - - return brcmnand_probe(pdev, soc); -} - -static const struct udevice_id bcm63158_nand_dt_ids[] = { - { - .compatible = "brcm,nand-bcm63158", - }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(bcm63158_nand) = { - .name = "bcm63158-nand", - .id = UCLASS_MTD, - .of_match = bcm63158_nand_dt_ids, - .probe = bcm63158_nand_probe, - .priv_auto = sizeof(struct bcm63158_nand_soc), -}; - -void board_nand_init(void) -{ - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_MTD, - DM_DRIVER_GET(bcm63158_nand), &dev); - if (ret && ret != -ENODEV) - pr_err("Failed to initialize %s. (error %d)\n", dev->name, - ret); -} diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c deleted file mode 100644 index a101222a28f..00000000000 --- a/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include <asm/io.h> -#include <memalign.h> -#include <nand.h> -#include <linux/bitops.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/ioport.h> -#include <dm.h> - -#include "brcmnand.h" - -struct bcm6753_nand_soc { - struct brcmnand_soc soc; - void __iomem *base; -}; - -#define BCM6753_NAND_INT 0x00 -#define BCM6753_NAND_STATUS_SHIFT 0 -#define BCM6753_NAND_STATUS_MASK (0xfff << BCM6753_NAND_STATUS_SHIFT) - -#define BCM6753_NAND_INT_EN 0x04 -#define BCM6753_NAND_ENABLE_SHIFT 0 -#define BCM6753_NAND_ENABLE_MASK (0xffff << BCM6753_NAND_ENABLE_SHIFT) - -enum { - BCM6753_NP_READ = BIT(0), - BCM6753_BLOCK_ERASE = BIT(1), - BCM6753_COPY_BACK = BIT(2), - BCM6753_PAGE_PGM = BIT(3), - BCM6753_CTRL_READY = BIT(4), - BCM6753_DEV_RBPIN = BIT(5), - BCM6753_ECC_ERR_UNC = BIT(6), - BCM6753_ECC_ERR_CORR = BIT(7), -}; - -static bool bcm6753_nand_intc_ack(struct brcmnand_soc *soc) -{ - struct bcm6753_nand_soc *priv = - container_of(soc, struct bcm6753_nand_soc, soc); - void __iomem *mmio = priv->base + BCM6753_NAND_INT; - u32 val = brcmnand_readl(mmio); - - if (val & (BCM6753_CTRL_READY << BCM6753_NAND_STATUS_SHIFT)) { - /* Ack interrupt */ - val &= ~BCM6753_NAND_STATUS_MASK; - val |= BCM6753_CTRL_READY << BCM6753_NAND_STATUS_SHIFT; - brcmnand_writel(val, mmio); - return true; - } - - return false; -} - -static void bcm6753_nand_intc_set(struct brcmnand_soc *soc, bool en) -{ - struct bcm6753_nand_soc *priv = - container_of(soc, struct bcm6753_nand_soc, soc); - void __iomem *mmio = priv->base + BCM6753_NAND_INT_EN; - u32 val = brcmnand_readl(mmio); - - /* Don't ack any interrupts */ - val &= ~BCM6753_NAND_STATUS_MASK; - - if (en) - val |= BCM6753_CTRL_READY << BCM6753_NAND_ENABLE_SHIFT; - else - val &= ~(BCM6753_CTRL_READY << BCM6753_NAND_ENABLE_SHIFT); - - brcmnand_writel(val, mmio); -} - -static int bcm6753_nand_probe(struct udevice *dev) -{ - struct udevice *pdev = dev; - struct bcm6753_nand_soc *priv = dev_get_priv(dev); - struct brcmnand_soc *soc; - struct resource res; - - soc = &priv->soc; - - dev_read_resource_byname(pdev, "nand-int-base", &res); - priv->base = devm_ioremap(dev, res.start, resource_size(&res)); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - - soc->ctlrdy_ack = bcm6753_nand_intc_ack; - soc->ctlrdy_set_enabled = bcm6753_nand_intc_set; - - /* Disable and ack all interrupts */ - brcmnand_writel(0, priv->base + BCM6753_NAND_INT_EN); - brcmnand_writel(0, priv->base + BCM6753_NAND_INT); - - return brcmnand_probe(pdev, soc); -} - -static const struct udevice_id bcm6753_nand_dt_ids[] = { - { - .compatible = "brcm,nand-bcm6753", - }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(bcm6753_nand) = { - .name = "bcm6753-nand", - .id = UCLASS_MTD, - .of_match = bcm6753_nand_dt_ids, - .probe = bcm6753_nand_probe, - .priv_auto = sizeof(struct bcm6753_nand_soc), -}; - -void board_nand_init(void) -{ - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_MTD, - DM_DRIVER_GET(bcm6753_nand), &dev); - if (ret && ret != -ENODEV) - pr_err("Failed to initialize %s. (error %d)\n", dev->name, - ret); -} diff --git a/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c deleted file mode 100644 index 385642d0c09..00000000000 --- a/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include <asm/io.h> -#include <memalign.h> -#include <nand.h> -#include <linux/bitops.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/ioport.h> -#include <dm.h> -#include <linux/printk.h> - -#include "brcmnand.h" - -struct bcm68360_nand_soc { - struct brcmnand_soc soc; - void __iomem *base; -}; - -#define BCM68360_NAND_INT 0x00 -#define BCM68360_NAND_STATUS_SHIFT 0 -#define BCM68360_NAND_STATUS_MASK (0xfff << BCM68360_NAND_STATUS_SHIFT) - -#define BCM68360_NAND_INT_EN 0x04 -#define BCM68360_NAND_ENABLE_SHIFT 0 -#define BCM68360_NAND_ENABLE_MASK (0xffff << BCM68360_NAND_ENABLE_SHIFT) - -enum { - BCM68360_NP_READ = BIT(0), - BCM68360_BLOCK_ERASE = BIT(1), - BCM68360_COPY_BACK = BIT(2), - BCM68360_PAGE_PGM = BIT(3), - BCM68360_CTRL_READY = BIT(4), - BCM68360_DEV_RBPIN = BIT(5), - BCM68360_ECC_ERR_UNC = BIT(6), - BCM68360_ECC_ERR_CORR = BIT(7), -}; - -static bool bcm68360_nand_intc_ack(struct brcmnand_soc *soc) -{ - struct bcm68360_nand_soc *priv = - container_of(soc, struct bcm68360_nand_soc, soc); - void __iomem *mmio = priv->base + BCM68360_NAND_INT; - u32 val = brcmnand_readl(mmio); - - if (val & (BCM68360_CTRL_READY << BCM68360_NAND_STATUS_SHIFT)) { - /* Ack interrupt */ - val &= ~BCM68360_NAND_STATUS_MASK; - val |= BCM68360_CTRL_READY << BCM68360_NAND_STATUS_SHIFT; - brcmnand_writel(val, mmio); - return true; - } - - return false; -} - -static void bcm68360_nand_intc_set(struct brcmnand_soc *soc, bool en) -{ - struct bcm68360_nand_soc *priv = - container_of(soc, struct bcm68360_nand_soc, soc); - void __iomem *mmio = priv->base + BCM68360_NAND_INT_EN; - u32 val = brcmnand_readl(mmio); - - /* Don't ack any interrupts */ - val &= ~BCM68360_NAND_STATUS_MASK; - - if (en) - val |= BCM68360_CTRL_READY << BCM68360_NAND_ENABLE_SHIFT; - else - val &= ~(BCM68360_CTRL_READY << BCM68360_NAND_ENABLE_SHIFT); - - brcmnand_writel(val, mmio); -} - -static int bcm68360_nand_probe(struct udevice *dev) -{ - struct udevice *pdev = dev; - struct bcm68360_nand_soc *priv = dev_get_priv(dev); - struct brcmnand_soc *soc; - struct resource res; - - soc = &priv->soc; - - dev_read_resource_byname(pdev, "nand-int-base", &res); - priv->base = devm_ioremap(dev, res.start, resource_size(&res)); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - - soc->ctlrdy_ack = bcm68360_nand_intc_ack; - soc->ctlrdy_set_enabled = bcm68360_nand_intc_set; - - /* Disable and ack all interrupts */ - brcmnand_writel(0, priv->base + BCM68360_NAND_INT_EN); - brcmnand_writel(0, priv->base + BCM68360_NAND_INT); - - return brcmnand_probe(pdev, soc); -} - -static const struct udevice_id bcm68360_nand_dt_ids[] = { - { - .compatible = "brcm,nand-bcm68360", - }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(bcm68360_nand) = { - .name = "bcm68360-nand", - .id = UCLASS_MTD, - .of_match = bcm68360_nand_dt_ids, - .probe = bcm68360_nand_probe, - .priv_auto = sizeof(struct bcm68360_nand_soc), -}; - -void board_nand_init(void) -{ - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_MTD, - DM_DRIVER_GET(bcm68360_nand), &dev); - if (ret && ret != -ENODEV) - pr_err("Failed to initialize %s. (error %d)\n", dev->name, - ret); -} diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c deleted file mode 100644 index 564c678c9ef..00000000000 --- a/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include <asm/io.h> -#include <memalign.h> -#include <nand.h> -#include <linux/bitops.h> -#include <linux/err.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/ioport.h> -#include <dm.h> -#include <linux/printk.h> - -#include "brcmnand.h" - -struct bcm6858_nand_soc { - struct brcmnand_soc soc; - void __iomem *base; -}; - -#define BCM6858_NAND_INT 0x00 -#define BCM6858_NAND_STATUS_SHIFT 0 -#define BCM6858_NAND_STATUS_MASK (0xfff << BCM6858_NAND_STATUS_SHIFT) - -#define BCM6858_NAND_INT_EN 0x04 -#define BCM6858_NAND_ENABLE_SHIFT 0 -#define BCM6858_NAND_ENABLE_MASK (0xffff << BCM6858_NAND_ENABLE_SHIFT) - -enum { - BCM6858_NP_READ = BIT(0), - BCM6858_BLOCK_ERASE = BIT(1), - BCM6858_COPY_BACK = BIT(2), - BCM6858_PAGE_PGM = BIT(3), - BCM6858_CTRL_READY = BIT(4), - BCM6858_DEV_RBPIN = BIT(5), - BCM6858_ECC_ERR_UNC = BIT(6), - BCM6858_ECC_ERR_CORR = BIT(7), -}; - -static bool bcm6858_nand_intc_ack(struct brcmnand_soc *soc) -{ - struct bcm6858_nand_soc *priv = - container_of(soc, struct bcm6858_nand_soc, soc); - void __iomem *mmio = priv->base + BCM6858_NAND_INT; - u32 val = brcmnand_readl(mmio); - - if (val & (BCM6858_CTRL_READY << BCM6858_NAND_STATUS_SHIFT)) { - /* Ack interrupt */ - val &= ~BCM6858_NAND_STATUS_MASK; - val |= BCM6858_CTRL_READY << BCM6858_NAND_STATUS_SHIFT; - brcmnand_writel(val, mmio); - return true; - } - - return false; -} - -static void bcm6858_nand_intc_set(struct brcmnand_soc *soc, bool en) -{ - struct bcm6858_nand_soc *priv = - container_of(soc, struct bcm6858_nand_soc, soc); - void __iomem *mmio = priv->base + BCM6858_NAND_INT_EN; - u32 val = brcmnand_readl(mmio); - - /* Don't ack any interrupts */ - val &= ~BCM6858_NAND_STATUS_MASK; - - if (en) - val |= BCM6858_CTRL_READY << BCM6858_NAND_ENABLE_SHIFT; - else - val &= ~(BCM6858_CTRL_READY << BCM6858_NAND_ENABLE_SHIFT); - - brcmnand_writel(val, mmio); -} - -static int bcm6858_nand_probe(struct udevice *dev) -{ - struct udevice *pdev = dev; - struct bcm6858_nand_soc *priv = dev_get_priv(dev); - struct brcmnand_soc *soc; - struct resource res; - - soc = &priv->soc; - - dev_read_resource_byname(pdev, "nand-int-base", &res); - priv->base = devm_ioremap(dev, res.start, resource_size(&res)); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - - soc->ctlrdy_ack = bcm6858_nand_intc_ack; - soc->ctlrdy_set_enabled = bcm6858_nand_intc_set; - - /* Disable and ack all interrupts */ - brcmnand_writel(0, priv->base + BCM6858_NAND_INT_EN); - brcmnand_writel(0, priv->base + BCM6858_NAND_INT); - - return brcmnand_probe(pdev, soc); -} - -static const struct udevice_id bcm6858_nand_dt_ids[] = { - { - .compatible = "brcm,nand-bcm6858", - }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(bcm6858_nand) = { - .name = "bcm6858-nand", - .id = UCLASS_MTD, - .of_match = bcm6858_nand_dt_ids, - .probe = bcm6858_nand_probe, - .priv_auto = sizeof(struct bcm6858_nand_soc), -}; - -void board_nand_init(void) -{ - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_MTD, - DM_DRIVER_GET(bcm6858_nand), &dev); - if (ret && ret != -ENODEV) - pr_err("Failed to initialize %s. (error %d)\n", dev->name, - ret); -} diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 749553c9df9..ef492e6db32 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -1071,8 +1071,8 @@ static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl, if ((val & mask) == expected_val) return 0; - dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", - expected_val, val & mask); + dev_err(ctrl->dev, "timeout on status poll (expected %x got %x)\n", + expected_val, val & mask); return -ETIMEDOUT; } @@ -2032,7 +2032,7 @@ try_dmaread: return err; } - dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n", + dev_err(ctrl->dev, "uncorrectable error at 0x%llx\n", (unsigned long long)err_addr); mtd->ecc_stats.failed++; /* NAND layer expects zero on ECC errors */ @@ -2793,9 +2793,17 @@ int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc) nand_hw_control_init(&ctrl->controller); INIT_LIST_HEAD(&ctrl->host_list); +#ifdef CONFIG_NAND_BRCMNAND_BCMBCA + /* + * BCMBCA platform does not use non-linux parameter-page-big-endian dts property, + * param page data is little endian + */ + ctrl->parameter_page_big_endian = 0; +#else /* Is parameter page in big endian ? */ ctrl->parameter_page_big_endian = dev_read_u32_default(dev, "parameter-page-big-endian", 1); +#endif /* NAND register range */ #ifndef __UBOOT__ diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index f1401d2f6ed..231764e60b5 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -649,7 +649,6 @@ static const struct eth_ops ravb_ops = { int ravb_of_to_plat(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); - const fdt32_t *cell; pdata->iobase = dev_read_addr(dev); @@ -657,10 +656,7 @@ int ravb_of_to_plat(struct udevice *dev) if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) return -EINVAL; - pdata->max_speed = 1000; - cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL); - if (cell) - pdata->max_speed = fdt32_to_cpu(*cell); + pdata->max_speed = dev_read_u32_default(dev, "max-speed", 1000); sprintf(bb_miiphy_buses[0].name, dev->name); diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c b/drivers/pinctrl/exynos/pinctrl-exynos.c index b393127c642..b37282fa9d6 100644 --- a/drivers/pinctrl/exynos/pinctrl-exynos.c +++ b/drivers/pinctrl/exynos/pinctrl-exynos.c @@ -114,8 +114,8 @@ static void exynos_pinctrl_set_pincfg(unsigned long reg_base, u32 pin_num, int exynos_pinctrl_set_state(struct udevice *dev, struct udevice *config) { struct exynos_pinctrl_priv *priv = dev_get_priv(dev); - unsigned int count, idx; - unsigned int pinvals[PINCFG_TYPE_NUM]; + int count; + unsigned int idx, pinvals[PINCFG_TYPE_NUM]; /* * refer to the following document for the pinctrl bindings diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c b/drivers/pinctrl/renesas/rzg2l-pfc.c index e88ec1c1837..3c751e9473a 100644 --- a/drivers/pinctrl/renesas/rzg2l-pfc.c +++ b/drivers/pinctrl/renesas/rzg2l-pfc.c @@ -180,7 +180,7 @@ static const u32 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN), RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), @@ -189,7 +189,7 @@ static const u32 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN), RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), @@ -381,7 +381,7 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector, } switch (param) { - case PIN_CONFIG_INPUT_ENABLE: { + case PIN_CONFIG_INPUT_ENABLE: if (!(cfg & PIN_CFG_IEN)) { dev_err(dev, "pin does not support IEN\n"); return -EINVAL; @@ -391,21 +391,12 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector, port_offset, pin, argument); rzg2l_rmw_pin_config(data, IEN(port_offset), pin, IEN_MASK, !!argument); break; - } case PIN_CONFIG_POWER_SOURCE: { - u32 pwr_reg = 0x0; + bool support_2500 = false; + u32 pwr_reg; + u32 value; - /* argument is in mV */ - if (argument != 1800 && argument != 3300) { - dev_err(dev, "Invalid mV %u\n", argument); - return -EINVAL; - } - - /* - * TODO: PIN_CFG_IO_VMC_ETH0 & PIN_CFG_IO_VMC_ETH1 will be - * handled when the RZ/G2L Ethernet driver is added. - */ if (cfg & PIN_CFG_IO_VMC_SD0) { dev_dbg(dev, "port off %u:%u set SD_CH 0 PVDD=%u\n", port_offset, pin, argument); @@ -418,13 +409,68 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector, dev_dbg(dev, "port off %u:%u set QSPI PVDD=%u\n", port_offset, pin, argument); pwr_reg = QSPI; + } else if (cfg & PIN_CFG_IO_VMC_ETH0) { + dev_dbg(dev, "port off %u:%u set ETH0 PVDD=%u\n", + port_offset, pin, argument); + pwr_reg = ETH_POC(0); + support_2500 = true; + } else if (cfg & PIN_CFG_IO_VMC_ETH1) { + dev_dbg(dev, "port off %u:%u set ETH1 PVDD=%u\n", + port_offset, pin, argument); + pwr_reg = ETH_POC(1); + support_2500 = true; } else { - dev_dbg(dev, "pin power source is not selectable\n"); + dev_dbg(dev, "port off %u:%u PVDD is not selectable\n", + port_offset, pin); + return -EINVAL; + } + + /* argument is in mV */ + switch (argument) { + case 1800: + value = PVDD_1800; + break; + case 3300: + value = PVDD_3300; + break; + case 2500: + if (support_2500) { + value = PVDD_2500; + break; + } + fallthrough; + default: + dev_err(dev, "Invalid mV %u\n", argument); return -EINVAL; } - writel((argument == 1800) ? PVDD_1800 : PVDD_3300, - data->base + pwr_reg); + writel(value, data->base + pwr_reg); + break; + } + + case PIN_CONFIG_OUTPUT_ENABLE: { + u8 ch; + + if (!(cfg & PIN_CFG_OEN)) { + dev_err(dev, "pin does not support OEN\n"); + return -EINVAL; + } + + /* + * We can determine which Ethernet interface we're dealing with from + * the caps. + */ + if (cfg & PIN_CFG_IO_VMC_ETH0) + ch = 0; + else /* PIN_CFG_IO_VMC_ETH1 */ + ch = 1; + + dev_dbg(dev, "set ETH%u TXC OEN=%u\n", ch, argument); + if (argument) + clrbits_8(data->base + ETH_MODE, BIT(ch)); + else + setbits_8(data->base + ETH_MODE, BIT(ch)); + break; } @@ -521,6 +567,7 @@ static int rzg2l_get_pin_muxing(struct udevice *dev, unsigned int selector, static const struct pinconf_param rzg2l_pinconf_params[] = { { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 }, { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 /* mV */ }, }; diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index decd0802c84..09567eb9dbb 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -9,6 +9,7 @@ #include <errno.h> #include <dm.h> #include <log.h> +#include <dm/device_compat.h> #include <dm/uclass-internal.h> #include <linux/delay.h> #include <power/pmic.h> @@ -43,8 +44,7 @@ static void regulator_set_value_ramp_delay(struct udevice *dev, int old_uV, { int delay = DIV_ROUND_UP(abs(new_uV - old_uV), ramp_delay); - debug("regulator %s: delay %u us (%d uV -> %d uV)\n", dev->name, delay, - old_uV, new_uV); + dev_dbg(dev, "delay %u us (%d uV -> %d uV)\n", delay, old_uV, new_uV); udelay(delay); } @@ -263,7 +263,7 @@ int regulator_get_by_platname(const char *plat_name, struct udevice **devp) for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; ret = uclass_find_next_device(&dev)) { if (ret) { - debug("regulator %s, ret=%d\n", dev->name, ret); + dev_dbg(dev, "ret=%d\n", ret); continue; } @@ -439,16 +439,15 @@ static int regulator_post_bind(struct udevice *dev) /* Regulator's mandatory constraint */ uc_pdata->name = dev_read_string(dev, property); if (!uc_pdata->name) { - debug("%s: dev '%s' has no property '%s'\n", - __func__, dev->name, property); + dev_dbg(dev, "has no property '%s'\n", property); uc_pdata->name = dev_read_name(dev); if (!uc_pdata->name) return -EINVAL; } if (!regulator_name_is_unique(dev, uc_pdata->name)) { - debug("'%s' of dev: '%s', has nonunique value: '%s\n", - property, dev->name, uc_pdata->name); + dev_err(dev, "'%s' has nonunique value: '%s\n", + property, uc_pdata->name); return -EINVAL; } diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 7fc53a6d61e..9c2d1398247 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -203,6 +203,7 @@ config RTC_RX8025 config RTC_PL031 bool "Enable ARM AMBA PL031 RTC driver" + depends on DM_RTC help The ARM PrimeCell Real Time Clock (PL031) is an optional SoC peripheral based on the Advanced Microcontroller Bus Architecture diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index bbe03cfff1f..4bff75da759 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -649,12 +649,30 @@ static void flip_ep0_direction(void) } } +/* + * This function explicitly sets the address, without the "USBADRA" (advance) + * feature, which is not supported by older versions of the controller. + */ +static void ci_set_address(struct ci_udc *udc, u8 address) +{ + DBG("%s %x\n", __func__, address); + writel(address << 25, &udc->devaddr); +} + static void handle_ep_complete(struct ci_ep *ci_ep) { struct ept_queue_item *item, *next_td; int num, in, len, j; struct ci_req *ci_req; + /* Set the device address that was previously sent by SET_ADDRESS */ + if (controller.next_device_address != 0) { + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + + ci_set_address(udc, controller.next_device_address); + controller.next_device_address = 0; + } + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; item = ci_get_qtd(num, in); @@ -783,7 +801,7 @@ static void handle_setup(void) * write address delayed (will take effect * after the next IN txn) */ - writel((r.wValue << 25) | (1 << 24), &udc->devaddr); + controller.next_device_address = r.wValue; req->length = 0; usb_ep_queue(controller.gadget.ep0, req, 0); return; @@ -814,6 +832,9 @@ static void stop_activity(void) int i, num, in; struct ept_queue_head *head; struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + + ci_set_address(udc, 0); + writel(readl(&udc->epcomp), &udc->epcomp); #ifdef CONFIG_CI_UDC_HAS_HOSTPC writel(readl(&udc->epsetupstat), &udc->epsetupstat); @@ -934,6 +955,7 @@ static int ci_pullup(struct usb_gadget *gadget, int is_on) struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; if (is_on) { /* RESET */ + controller.next_device_address = 0; writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd); udelay(200); diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h index bea2f9f3fe3..807f2084c1e 100644 --- a/drivers/usb/gadget/ci_udc.h +++ b/drivers/usb/gadget/ci_udc.h @@ -105,6 +105,7 @@ struct ci_drv { struct ept_queue_head *epts; uint8_t *items_mem; struct ci_ep ep[NUM_ENDPOINTS]; + u8 next_device_address; }; struct ept_queue_head { diff --git a/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi index 014cf1805fb..21fe194a576 100644 --- a/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi +++ b/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi @@ -124,7 +124,6 @@ }; mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - bootph-all; pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 26277b93976..789adf2c3f9 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -400,6 +400,12 @@ struct global_data { */ struct bloblist_hdr *bloblist; #endif +#if CONFIG_IS_ENABLED(HANDOFF) + /** + * @spl_handoff: SPL hand-off information + */ + struct spl_handoff *spl_handoff; +#endif #if defined(CONFIG_TRANSLATION_OFFSET) /** * @translation_offset: optional translation offset diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index d323f84ac7a..57ecb5e2190 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -34,7 +34,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_EXTRA_ENV_SETTINGS \ - "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \ + "altbootcmd=run bootcmd\0" \ "bootlimit=3\0" \ "devtype=mmc\0" \ "devpart=1\0" \ diff --git a/include/configs/imx8mp_data_modul_edm_sbc.h b/include/configs/imx8mp_data_modul_edm_sbc.h index f953847ce05..de5bdd30e18 100644 --- a/include/configs/imx8mp_data_modul_edm_sbc.h +++ b/include/configs/imx8mp_data_modul_edm_sbc.h @@ -24,7 +24,7 @@ #define FEC_QUIRK_ENET_MAC #define CFG_EXTRA_ENV_SETTINGS \ - "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \ + "altbootcmd=run bootcmd\0" \ "bootlimit=3\0" \ "devtype=mmc\0" \ "devpart=1\0" \ diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 4e0b3c663c7..0a5f23e4c88 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -12,13 +12,4 @@ #include "mv-common.h" -/* - * Environment variables configurations - */ -#define CFG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 mtdparts=" CONFIG_MTDPARTS_DEFAULT \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" - #endif /* _CONFIG_SHEEVAPLUG_H */ diff --git a/include/configs/x240.h b/include/configs/x240.h index 3601df588d5..05241f33d74 100644 --- a/include/configs/x240.h +++ b/include/configs/x240.h @@ -11,22 +11,14 @@ /* additions for new ARM relocation support */ #define CFG_SYS_SDRAM_BASE 0x200000000 -#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400, 460800, 921600 } - /* Default Env vars */ - -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) \ - func(DHCP, dhcp, na) - -#include <config_distro_bootcmd.h> +#define BOOT_TARGETS "usb dhcp" #define CFG_EXTRA_ENV_SETTINGS \ - BOOTENV \ "kernel_addr_r=0x202000000\0" \ "fdt_addr_r=0x201000000\0" \ "ramdisk_addr_r=0x206000000\0" \ + "boot_targets=" BOOT_TARGETS "\0" \ "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" /* diff --git a/include/configs/x250.h b/include/configs/x250.h new file mode 100644 index 00000000000..39f523fa6c4 --- /dev/null +++ b/include/configs/x250.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 Allied Telesis + */ + +#ifndef __X250_H_ +#define __X250_H_ + +/* + * High Level Configuration Options (easy to change) + */ +#define CFG_SYS_TCLK 250000000 /* 250MHz */ + +/* additions for new ARM relocation support */ +#define CFG_SYS_SDRAM_BASE 0x00000000 + +#define BOOT_TARGETS "usb scsi pxe dhcp" + +#define CFG_EXTRA_ENV_SETTINGS \ + "scriptaddr=0x6d00000\0" \ + "pxefile_addr_r=0x6e00000\0" \ + "fdt_addr_r=0x6f00000\0" \ + "kernel_addr_r=0x7000000\0" \ + "ramdisk_addr_r=0xa000000\0" \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "boot_targets=" BOOT_TARGETS "\0" + +#endif /* __X250_H_ */ diff --git a/include/configs/x530.h b/include/configs/x530.h index 982b1292873..c7bfd1de17c 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -18,30 +18,14 @@ #define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - /* NAND */ #define BBT_CUSTOM_SCAN #define BBT_CUSTOM_SCAN_PAGE 0 #define BBT_CUSTOM_SCAN_POSITION 2048 -/* SPI NOR flash default params, used by sf commands */ - #define MTDPARTS_MTDOOPS "errlog" -/* Partition support */ - -/* Additional FS support/configuration */ - -/* Environment in SPI NOR flash */ - -/* NAND */ - #include <asm/arch/config.h> /* Keep device tree and initrd in low memory so the kernel can access them */ diff --git a/include/handoff.h b/include/handoff.h index 0072ea832f8..c0ae7b19a75 100644 --- a/include/handoff.h +++ b/include/handoff.h @@ -32,13 +32,6 @@ void handoff_load_dram_size(struct spl_handoff *ho); void handoff_load_dram_banks(struct spl_handoff *ho); /** - * handoff_get() - Get the SPL handoff information - * - * Return: Pointer to SPL handoff if received, else NULL - */ -struct spl_handoff *handoff_get(void); - -/** * handoff_arch_save() - Save arch-specific info into the handoff area * * This is defined to an empty function by default, but arch-specific code can diff --git a/include/renesas/rzg2l-pfc.h b/include/renesas/rzg2l-pfc.h index 2df17ece2a3..0c94487754d 100644 --- a/include/renesas/rzg2l-pfc.h +++ b/include/renesas/rzg2l-pfc.h @@ -22,6 +22,7 @@ #define PIN_CFG_FILONOFF BIT(10) #define PIN_CFG_FILNUM BIT(11) #define PIN_CFG_FILCLKSEL BIT(12) +#define PIN_CFG_OEN BIT(13) #define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \ PIN_CFG_SR | \ @@ -77,9 +78,12 @@ #define IEN(n) (0x1800 + (n) * 8) #define PWPR 0x3014 #define SD_CH(n) (0x3000 + (n) * 4) +#define ETH_POC(ch) (0x300c + (ch) * 4) #define QSPI 0x3008 +#define ETH_MODE 0x3018 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ +#define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ #define PWPR_B0WI BIT(7) /* Bit Write Disable */ diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h index c98b1a58088..2a52e169051 100644 --- a/include/u-boot/md5.h +++ b/include/u-boot/md5.h @@ -6,7 +6,9 @@ #ifndef _MD5_H #define _MD5_H -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#include <linux/kconfig.h> + +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) #include <mbedtls/md5.h> #endif #include "compiler.h" @@ -14,7 +16,7 @@ #define MD5_SUM_LEN 16 #define MD5_DEF_CHUNK_SZ 0x10000 -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) typedef mbedtls_md5_context MD5Context; #else typedef struct MD5Context { diff --git a/include/u-boot/sha1.h b/include/u-boot/sha1.h index 2fca7f1be16..dd66258bbe9 100644 --- a/include/u-boot/sha1.h +++ b/include/u-boot/sha1.h @@ -14,9 +14,10 @@ #ifndef _SHA1_H #define _SHA1_H +#include <linux/kconfig.h> #include <linux/types.h> -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) /* * FIXME: * MbedTLS define the members of "mbedtls_sha256_context" as private, @@ -47,7 +48,7 @@ extern "C" { extern const uint8_t sha1_der_prefix[]; -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) typedef mbedtls_sha1_context sha1_context; #else /** diff --git a/include/u-boot/sha256.h b/include/u-boot/sha256.h index b58d5b58d39..44a9b528b48 100644 --- a/include/u-boot/sha256.h +++ b/include/u-boot/sha256.h @@ -1,9 +1,10 @@ #ifndef _SHA256_H #define _SHA256_H +#include <linux/kconfig.h> #include <linux/types.h> -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) /* * FIXME: * MbedTLS define the members of "mbedtls_sha256_context" as private, @@ -27,7 +28,7 @@ extern const uint8_t sha256_der_prefix[]; /* Reset watchdog each time we process this many bytes */ #define CHUNKSZ_SHA256 (64 * 1024) -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) typedef mbedtls_sha256_context sha256_context; #else typedef struct { diff --git a/include/u-boot/sha512.h b/include/u-boot/sha512.h index 7e10f590a1d..92660d93357 100644 --- a/include/u-boot/sha512.h +++ b/include/u-boot/sha512.h @@ -1,9 +1,10 @@ #ifndef _SHA512_H #define _SHA512_H +#include <linux/kconfig.h> #include <linux/types.h> -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) #include <mbedtls/sha512.h> #endif @@ -16,7 +17,7 @@ #define CHUNKSZ_SHA384 (16 * 1024) #define CHUNKSZ_SHA512 (16 * 1024) -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) typedef mbedtls_sha512_context sha384_context; typedef mbedtls_sha512_context sha512_context; #else diff --git a/lib/Makefile b/lib/Makefile index dbcfa87ebd6..d24ed629732 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -97,7 +97,7 @@ obj-$(CONFIG_LIBAVB) += libavb/ obj-$(CONFIG_$(PHASE_)OF_LIBFDT) += libfdt/ obj-$(CONFIG_$(PHASE_)OF_REAL) += fdtdec_common.o fdtdec.o -obj-$(CONFIG_MBEDTLS_LIB) += mbedtls/ +obj-$(CONFIG_$(XPL_)MBEDTLS_LIB) += mbedtls/ obj-$(CONFIG_NET_LWIP) += lwip/ diff --git a/lib/binman.c b/lib/binman.c index 93d85548116..9047f5275f3 100644 --- a/lib/binman.c +++ b/lib/binman.c @@ -137,7 +137,6 @@ int binman_init(void) { int ret; - return 0; binman = malloc(sizeof(struct binman_info)); if (!binman) return log_msg_ret("space for binman", -ENOMEM); diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c index 6650c2b8071..112775daf4c 100644 --- a/lib/efi_loader/efi_firmware.c +++ b/lib/efi_loader/efi_firmware.c @@ -281,6 +281,10 @@ static efi_status_t efi_gen_capsule_guids(void) } for (i = 0; i < update_info.num_images; i++) { + if (!fw_array[i].fw_name) { + log_err("fw_name is not defined. Not generating capsule GUIDs\n"); + return EFI_INVALID_PARAMETER; + } gen_v5_guid(&namespace, &fw_array[i].image_type_id, compatible, strlen(compatible), diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index e493934c713..edd7da7d8c6 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -814,7 +814,16 @@ static void add_u_boot_and_runtime(void) { unsigned long runtime_start, runtime_end, runtime_pages; unsigned long runtime_mask = EFI_PAGE_MASK; - + unsigned long uboot_start, uboot_pages; + unsigned long uboot_stack_size = CONFIG_STACK_SIZE; + + /* Add U-Boot */ + uboot_start = ((uintptr_t)map_sysmem(gd->start_addr_sp, 0) - + uboot_stack_size) & ~EFI_PAGE_MASK; + uboot_pages = ((uintptr_t)map_sysmem(gd->ram_top - 1, 0) - + uboot_start + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT; + efi_add_memory_map_pg(uboot_start, uboot_pages, EFI_BOOT_SERVICES_CODE, + false); #if defined(__aarch64__) /* * Runtime Services must be 64KiB aligned according to the diff --git a/lib/lmb.c b/lib/lmb.c index 14b9b8466ff..b03237bc06c 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -201,15 +201,6 @@ static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base, phys_addr_t rgnbase = rgn[i].base; phys_size_t rgnsize = rgn[i].size; phys_size_t rgnflags = rgn[i].flags; - phys_addr_t end = base + size - 1; - phys_addr_t rgnend = rgnbase + rgnsize - 1; - if (rgnbase <= base && end <= rgnend) { - if (flags == rgnflags) - /* Already have this region, so we're done */ - return 0; - else - return -1; /* regions with new flags */ - } ret = lmb_addrs_adjacent(base, size, rgnbase, rgnsize); if (ret > 0) { @@ -615,6 +606,7 @@ static __maybe_unused void lmb_reserve_common_spl(void) void lmb_add_memory(void) { int i; + phys_addr_t bank_end; phys_size_t size; u64 ram_top = gd->ram_top; struct bd_info *bd = gd->bd; @@ -628,6 +620,8 @@ void lmb_add_memory(void) for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { size = bd->bi_dram[i].size; + bank_end = bd->bi_dram[i].start + size; + if (size) { lmb_add(bd->bi_dram[i].start, size); @@ -639,6 +633,9 @@ void lmb_add_memory(void) if (bd->bi_dram[i].start >= ram_top) lmb_reserve_flags(bd->bi_dram[i].start, size, LMB_NOOVERWRITE); + else if (bank_end > ram_top) + lmb_reserve_flags(ram_top, bank_end - ram_top, + LMB_NOOVERWRITE); } } } diff --git a/lib/lwip/Makefile b/lib/lwip/Makefile index 19e5c6897f5..fe2b64c9acc 100644 --- a/lib/lwip/Makefile +++ b/lib/lwip/Makefile @@ -54,5 +54,5 @@ obj-y += \ lwip/src/core/udp.o \ lwip/src/netif/ethernet.o -obj-$(CONFIG_MBEDTLS_LIB_TLS) += lwip/src/apps/altcp_tls/altcp_tls_mbedtls.o \ +obj-$(CONFIG_$(XPL_)MBEDTLS_LIB_TLS) += lwip/src/apps/altcp_tls/altcp_tls_mbedtls.o \ lwip/src/apps/altcp_tls/altcp_tls_mbedtls_mem.o diff --git a/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c b/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c index 6643b05ee94..46421588fef 100644 --- a/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c +++ b/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c @@ -692,7 +692,9 @@ altcp_tls_set_session(struct altcp_pcb *conn, struct altcp_tls_session *session) if (session && conn && conn->state) { altcp_mbedtls_state_t *state = (altcp_mbedtls_state_t *)conn->state; int ret = -1; +#ifdef MBEDTLS_HAVE_TIME if (session->data.MBEDTLS_PRIVATE(start)) +#endif ret = mbedtls_ssl_set_session(&state->ssl_context, &session->data); return ret < 0 ? ERR_VAL : ERR_OK; } diff --git a/lib/lwip/u-boot/lwipopts.h b/lib/lwip/u-boot/lwipopts.h index 88d6faf327a..edac74ff7a2 100644 --- a/lib/lwip/u-boot/lwipopts.h +++ b/lib/lwip/u-boot/lwipopts.h @@ -5,6 +5,8 @@ #ifndef LWIP_UBOOT_LWIPOPTS_H #define LWIP_UBOOT_LWIPOPTS_H +#include <linux/kconfig.h> + #if defined(CONFIG_LWIP_DEBUG) #define LWIP_DEBUG 1 #define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL @@ -154,7 +156,7 @@ #define MEMP_MEM_INIT 1 #define MEM_LIBC_MALLOC 1 -#if defined(CONFIG_MBEDTLS_LIB_TLS) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_TLS) #define LWIP_ALTCP 1 #define LWIP_ALTCP_TLS 1 #define LWIP_ALTCP_TLS_MBEDTLS 1 diff --git a/lib/mbedtls/mbedtls_def_config.h b/lib/mbedtls/mbedtls_def_config.h index d27f017d084..1d2314e90e4 100644 --- a/lib/mbedtls/mbedtls_def_config.h +++ b/lib/mbedtls/mbedtls_def_config.h @@ -92,9 +92,6 @@ /* Generic options */ #define MBEDTLS_ENTROPY_HARDWARE_ALT -#define MBEDTLS_HAVE_TIME -#define MBEDTLS_PLATFORM_MS_TIME_ALT -#define MBEDTLS_PLATFORM_TIME_MACRO rtc_mktime #define MBEDTLS_PLATFORM_C #define MBEDTLS_SSL_CLI_C #define MBEDTLS_SSL_TLS_C diff --git a/lib/md5.c b/lib/md5.c index 2d8977b2e85..e3eab8a9149 100644 --- a/lib/md5.c +++ b/lib/md5.c @@ -272,14 +272,16 @@ md5_wd(const unsigned char *input, unsigned int len, unsigned char output[16], unsigned int chunk_sz) { MD5Context context; -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) const unsigned char *end, *curr; int chunk; #endif MD5Init(&context); -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) curr = input; end = input + len; while (curr < end) { diff --git a/lib/sha1.c b/lib/sha1.c index a9d6497c4ce..be502c6126b 100644 --- a/lib/sha1.c +++ b/lib/sha1.c @@ -312,14 +312,16 @@ void sha1_csum_wd(const unsigned char *input, unsigned int ilen, unsigned char *output, unsigned int chunk_sz) { sha1_context ctx; -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) const unsigned char *end, *curr; int chunk; #endif sha1_starts (&ctx); -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) curr = input; end = input + ilen; while (curr < end) { diff --git a/lib/sha256.c b/lib/sha256.c index 329802fd827..fb195d988f1 100644 --- a/lib/sha256.c +++ b/lib/sha256.c @@ -273,7 +273,8 @@ void sha256_csum_wd(const unsigned char *input, unsigned int ilen, unsigned char *output, unsigned int chunk_sz) { sha256_context ctx; -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) const unsigned char *end; unsigned char *curr; int chunk; @@ -281,7 +282,8 @@ void sha256_csum_wd(const unsigned char *input, unsigned int ilen, sha256_starts(&ctx); -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) curr = (unsigned char *)input; end = input + ilen; while (curr < end) { diff --git a/lib/sha512.c b/lib/sha512.c index ea555ff33eb..0e75c1a943b 100644 --- a/lib/sha512.c +++ b/lib/sha512.c @@ -288,7 +288,8 @@ void sha384_csum_wd(const unsigned char *input, unsigned int ilen, unsigned char *output, unsigned int chunk_sz) { sha512_context ctx; -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) const unsigned char *end; unsigned char *curr; int chunk; @@ -296,7 +297,8 @@ void sha384_csum_wd(const unsigned char *input, unsigned int ilen, sha384_starts(&ctx); -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) curr = (unsigned char *)input; end = input + ilen; while (curr < end) { @@ -351,7 +353,8 @@ void sha512_csum_wd(const unsigned char *input, unsigned int ilen, unsigned char *output, unsigned int chunk_sz) { sha512_context ctx; -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) const unsigned char *end; unsigned char *curr; int chunk; @@ -359,7 +362,8 @@ void sha512_csum_wd(const unsigned char *input, unsigned int ilen, sha512_starts(&ctx); -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) curr = (unsigned char *)input; end = input + ilen; while (curr < end) { diff --git a/net/lwip/wget.c b/net/lwip/wget.c index c23f0640ec6..b76f6c0f1d9 100644 --- a/net/lwip/wget.c +++ b/net/lwip/wget.c @@ -180,7 +180,7 @@ static int parse_legacy_arg(char *arg, char *nurl, size_t rem) if (rem < n) return -1; - strlcpy(p, server, n); + strncpy(p, server, n); p += n; rem -= n; if (rem < 1) @@ -191,7 +191,7 @@ static int parse_legacy_arg(char *arg, char *nurl, size_t rem) n = strlen(path); if (rem < n) return -1; - strlcpy(p, path, n); + strncpy(p, path, n); p += n; rem -= n; if (rem < 1) diff --git a/test/cmd/wget.c b/test/cmd/wget.c index fe26fee54c9..7570c065a10 100644 --- a/test/cmd/wget.c +++ b/test/cmd/wget.c @@ -19,7 +19,7 @@ #include <dm/test.h> #include <dm/device-internal.h> #include <dm/uclass-internal.h> -#include <test/lib.h> +#include <test/cmd.h> #include <test/test.h> #include <test/ut.h> @@ -206,6 +206,10 @@ static int sb_http_handler(struct udevice *dev, void *packet, static int net_test_wget(struct unit_test_state *uts) { + char *prev_ethact = env_get("ethact"); + char *prev_ethrotate = env_get("ethrotate"); + char *prev_loadaddr = env_get("loadaddr"); + sandbox_eth_set_tx_handler(0, sb_http_handler); sandbox_eth_set_priv(0, uts); @@ -223,6 +227,10 @@ static int net_test_wget(struct unit_test_state *uts) ut_assert_nextline("md5 for 00020000 ... 0002001f ==> 234af48e94b0085060249ecb5942ab57"); ut_assert_console_end(); + env_set("ethact", prev_ethact); + env_set("ethrotate", prev_ethrotate); + env_set("loadaddr", prev_loadaddr); + return 0; } -LIB_TEST(net_test_wget, UTF_CONSOLE); +CMD_TEST(net_test_wget, UTF_CONSOLE); diff --git a/test/lib/lmb.c b/test/lib/lmb.c index c917115b7b6..0bd29e2a4fe 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -529,6 +529,26 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) ret = lmb_add(ram, ram_size); ut_asserteq(ret, 0); + /* Try to allocate a page twice */ + b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NONE); + ut_asserteq(b, alloc_addr_a); + b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); + ut_asserteq(b, 0); + b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NONE); + ut_asserteq(b, alloc_addr_a); + b = lmb_alloc_addr_flags(alloc_addr_a, 0x2000, LMB_NONE); + ut_asserteq(b, alloc_addr_a); + ret = lmb_free(alloc_addr_a, 0x2000); + ut_asserteq(ret, 0); + b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); + ut_asserteq(b, alloc_addr_a); + b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NONE); + ut_asserteq(b, 0); + b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); + ut_asserteq(b, 0); + ret = lmb_free(alloc_addr_a, 0x1000); + ut_asserteq(ret, 0); + /* reserve 3 blocks */ ret = lmb_reserve(alloc_addr_a, 0x10000); ut_asserteq(ret, 0); @@ -734,7 +754,7 @@ static int lib_test_lmb_flags(struct unit_test_state *uts) /* reserve again, same flag */ ret = lmb_reserve_flags(0x40010000, 0x10000, LMB_NOMAP); - ut_asserteq(ret, 0); + ut_asserteq(ret, -1L); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000, 0, 0, 0, 0); |