diff options
354 files changed, 9660 insertions, 7076 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 4ecf76eaa0b..c577a724c82 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -2,7 +2,7 @@ variables: windows_vm: windows-2022 ubuntu_vm: ubuntu-24.04 macos_vm: macOS-14 - ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240808-21Aug2024 + ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240808-03Dec2024 # Add '-u 0' options for Azure pipelines, otherwise we get "permission # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # since our $(ci_runner_image) user is not root. @@ -245,8 +245,6 @@ stages: ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py ln -s travis-ci /tmp/uboot-test-hooks/bin/\`hostname\` ln -s travis-ci /tmp/uboot-test-hooks/py/\`hostname\` - grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ; export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; @@ -268,8 +266,8 @@ stages: fi pip install -r tools/buildman/requirements.txt tools/buildman/buildman -o \${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board \${TEST_PY_BD} \${OVERRIDE} - cp ~/grub_x86.efi \${UBOOT_TRAVIS_BUILD_DIR}/ - cp ~/grub_x64.efi \${UBOOT_TRAVIS_BUILD_DIR}/ + cp /opt/grub/grub_x86.efi \${UBOOT_TRAVIS_BUILD_DIR}/ + cp /opt/grub/grub_x64.efi \${UBOOT_TRAVIS_BUILD_DIR}/ cp /opt/grub/grubriscv64.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi cp /opt/grub/grubaa64.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi cp /opt/grub/grubarm.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2164ad79a72..57037e243ec 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -4,6 +4,7 @@ variables: DEFAULT_TAG: "" MIRROR_DOCKER: docker.io SJG_LAB: "" + PLATFORM: linux/amd64,linux/arm64 default: tags: @@ -11,7 +12,7 @@ default: # Grab our configured image. The source for this is found # in the u-boot tree at tools/docker/Dockerfile -image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240808-21Aug2024 +image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240808-03Dec2024 # We run some tests in different order, to catch some failures quicker. stages: @@ -34,8 +35,6 @@ stages: - ln -s conf.qemu_arm64_na /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname` - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname` - - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ; export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; @@ -62,8 +61,8 @@ stages: fi - tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board ${TEST_PY_BD} ${OVERRIDE} - - cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/ - - cp ~/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/ + - cp /opt/grub/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/ + - cp /opt/grub/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/ - cp /opt/grub/grubriscv64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv64.efi - cp /opt/grub/grubaa64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi - cp /opt/grub/grubarm.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi @@ -595,27 +595,6 @@ config SYS_MEM_TOP_HIDE WARNING: Please make sure that this value is a multiple of the OS page size. -config SYS_HAS_SRAM - bool - default y if TARGET_PIC32MZDASK - default y if TARGET_DEVKIT8000 - help - Enable this to allow support for the on board SRAM. - SRAM base address is controlled by CONFIG_SYS_SRAM_BASE. - SRAM size is controlled by CONFIG_SYS_SRAM_SIZE. - -config SYS_SRAM_BASE - hex - default 0x80000000 if TARGET_PIC32MZDASK - default 0x40200000 if TARGET_DEVKIT8000 - default 0x0 - -config SYS_SRAM_SIZE - hex - default 0x00080000 if TARGET_PIC32MZDASK - default 0x10000 if TARGET_DEVKIT8000 - default 0x0 - config SYS_MONITOR_LEN int "Maximum size in bytes reserved for U-Boot in memory" default 1048576 if X86 @@ -765,10 +744,15 @@ choice config NO_NET bool "No networking support" + help + Do not include networking support config NET bool "Legacy U-Boot networking stack" imply NETDEVICES + help + Include networking support with U-Boot's internal implementation of + the TCP/IP protocol stack. config NET_LWIP bool "Use lwIP for networking stack" diff --git a/MAINTAINERS b/MAINTAINERS index bd2c49429a1..ba31f86feb6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -860,6 +860,7 @@ M: Michal Simek <michal.simek@amd.com> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-zynqmp/ +F: drivers/bootcount/bootcount_zynqmp.c F: drivers/clk/clk_zynqmp.c F: driver/firmware/firmware-zynqmp.c F: drivers/fpga/zynqpl.c @@ -1735,6 +1736,11 @@ S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-ubi.git F: drivers/mtd/ubi/ +UFETCH +M: Caleb Connolly <caleb.connolly@linaro.org> +S: Maintained +F: cmd/ufetch.c + UFS M: Neil Armstrong <neil.armstrong@linaro.org> M: Bhupesh Sharma <bhupesh.linux@gmail.com> @@ -3,7 +3,7 @@ VERSION = 2025 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* @@ -1149,13 +1149,6 @@ ifeq ($(CONFIG_OF_EMBED)$(CONFIG_EFI_APP),y) @echo >&2 "See doc/develop/devicetree/control.rst for more info." @echo >&2 "====================================================" endif -ifneq ($(CONFIG_SPL_FIT_GENERATOR),) - @echo >&2 "===================== WARNING ======================" - @echo >&2 "This board uses CONFIG_SPL_FIT_GENERATOR. Please migrate" - @echo >&2 "to binman instead, to avoid the proliferation of" - @echo >&2 "arch-specific scripts with no tests." - @echo >&2 "====================================================" -endif $(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\ $(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG)) $(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY)) @@ -1392,12 +1385,21 @@ endif default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE)) endif +binman_dtb := $(shell echo $(CONFIG_BINMAN_DTB)) +ifeq ($(strip $(binman_dtb)),) +ifeq ($(CONFIG_OF_EMBED),y) +binman_dtb = ./dts/dt.dtb +else +binman_dtb = ./u-boot.dtb +endif +endif + quiet_cmd_binman = BINMAN $@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \ $(foreach f,$(BINMAN_TOOLPATHS),--toolpath $(f)) \ --toolpath $(objtree)/tools \ $(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \ - build -u -d u-boot.dtb -O . -m \ + build -u -d $(binman_dtb) -O . -m \ --allow-missing --fake-ext-blobs \ $(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \ -I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \ @@ -1427,17 +1429,6 @@ OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE $(call if_changed,objcopy) -# Boards with more complex image requirements can provide an .its source file -# or a generator script -# NOTE: Please do not use this. We are migrating away from Makefile rules to use -# binman instead. -ifneq ($(CONFIG_USE_SPL_FIT_GENERATOR),) -U_BOOT_ITS := u-boot.its -$(U_BOOT_ITS): $(U_BOOT_ITS_DEPS) FORCE - $(srctree)/$(CONFIG_SPL_FIT_GENERATOR) \ - $(patsubst %,$(dt_dir)/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@ -endif - ifdef CONFIG_SPL_LOAD_FIT MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c index 3a04a9f691c..2c1ab043af6 100644 --- a/api/api_platform-powerpc.c +++ b/api/api_platform-powerpc.c @@ -43,7 +43,6 @@ int platform_sys_info(struct sys_info *si) platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM); platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH); - platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM); return 1; } diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7282c4123b0..ea414fe376a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1177,7 +1177,6 @@ config ARCH_SUNXI select SUNXI_GPIO select SYS_NS16550 select SYS_THUMB_BUILD if !ARM64 - select USB if DISTRO_DEFAULTS select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST select SPL_USE_TINY_PRINTF if SPL @@ -1203,6 +1202,7 @@ config ARCH_SUNXI imply SYSRESET imply SYSRESET_WATCHDOG imply SYSRESET_WATCHDOG_AUTO + imply USB imply USB_GADGET imply WDT @@ -1324,6 +1324,7 @@ config ARCH_ZYNQMP_R5 config ARCH_ZYNQMP bool "Xilinx ZynqMP based platform" select ARM64 + select BINMAN select CLK select DM select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index e6be6359c5d..5d6953ffedd 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -825,7 +825,7 @@ void dcache_enable(void) void dcache_disable(void) { - uint32_t sctlr; + unsigned long sctlr; sctlr = get_sctlr(); diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c index d568efa427a..82ecf02f4b0 100644 --- a/arch/arm/cpu/armv8/cpu.c +++ b/arch/arm/cpu/armv8/cpu.c @@ -94,3 +94,8 @@ void armv8_setup_psci(void) secure_ram_addr(psci_arch_init)(); } #endif + +void allow_unaligned(void) +{ + set_sctlr(get_sctlr() & ~CR_A); +} diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 042282f3723..cfa358613c4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -274,6 +274,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-mini-qspi-x1-stacked.dtb \ zynqmp-mini-qspi-x2-single.dtb \ zynqmp-mini-qspi-x2-stacked.dtb \ + zynqmp-binman-mini.dtb \ zynqmp-sc-revB.dtb \ zynqmp-sc-revC.dtb \ zynqmp-sm-k24-revA.dtb \ @@ -319,6 +320,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-02-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-03-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-04-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-05-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-binman.dtb zynqmp-sc-vek280-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vek280-revA.dtbo zynqmp-sc-vek280-revB-dtbs := zynqmp-sc-revC.dtb zynqmp-sc-vek280-revB.dtbo @@ -369,6 +371,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kv-g-revB.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kv-g-revB.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kr-g-revB.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kr-g-revB.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-binman-som.dtb dtb-$(CONFIG_ARCH_VERSAL) += \ versal-mini.dtb \ @@ -935,8 +938,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ fsl-imx8qxp-mek.dtb \ - imx8-deneb.dtb \ - imx8-giedi.dtb + imx8-capricorn-cxg3.dtb \ dtb-$(CONFIG_ARCH_IMX8ULP) += \ imx8ulp-evk.dtb diff --git a/arch/arm/dts/imx8-capricorn-cxg3.dts b/arch/arm/dts/imx8-capricorn-cxg3.dts new file mode 100644 index 00000000000..2f8597579f3 --- /dev/null +++ b/arch/arm/dts/imx8-capricorn-cxg3.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Siemens AG + */ + +#include "imx8-capricorn.dtsi" + +/ { + model = "Siemens CXG3"; + + leds_default: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + run { + label = "run"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + flt { + label = "flt"; + gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + svc { + label = "svc"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com1_tx { + label = "com1-tx"; + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com1_rx { + label = "com1-rx"; + gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com2_tx { + label = "com2-tx"; + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com2_rx { + label = "com2-rx"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + cloud { + label = "cloud"; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + wlan { + label = "wlan"; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + apps { + label = "apps"; + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg2 { + label = "dbg2"; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg3 { + label = "dbg3"; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg4 { + label = "dbg4"; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + }; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_gpio_keys>; + + muxcgrp: imx8qxp-som { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021 + SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 0x06000021 + SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x06000021 + SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x06000021 + SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x06000021 + SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x06000021 + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 + SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x06000021 + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021 + >; + }; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x06000021 + >; + }; +}; diff --git a/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi b/arch/arm/dts/imx8-capricorn-u-boot.dtsi index cba56188f86..ad5309bd969 100644 --- a/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi +++ b/arch/arm/dts/imx8-capricorn-u-boot.dtsi @@ -6,130 +6,133 @@ #include "imx8qxp-u-boot.dtsi" &{/imx8qx-pm} { + bootph-all; +}; - bootph-pre-ram; +&A35_0 { + bootph-all; }; &mu { - bootph-pre-ram; + bootph-all; }; &clk { - bootph-pre-ram; + bootph-all; }; &iomuxc { - bootph-pre-ram; + bootph-all; }; &pd_lsio { - bootph-pre-ram; + bootph-all; }; &pd_lsio_gpio0 { - bootph-pre-ram; + bootph-all; }; &pd_lsio_gpio1 { - bootph-pre-ram; + bootph-all; }; &pd_lsio_gpio2 { - bootph-pre-ram; + bootph-all; }; &pd_lsio_gpio3 { - bootph-pre-ram; + bootph-all; }; &pd_lsio_gpio4 { - bootph-pre-ram; + bootph-all; }; &pd_lsio_gpio5 { - bootph-pre-ram; + bootph-all; }; &pd_lsio_gpio6 { - bootph-pre-ram; + bootph-all; }; &pd_lsio_gpio7 { - bootph-pre-ram; + bootph-all; }; &pd_dma { - bootph-pre-ram; + bootph-all; }; &pd_dma_lpuart0 { - bootph-pre-ram; + bootph-all; }; &pd_dma_lpuart2 { - bootph-pre-ram; + bootph-all; }; &pd_conn { - bootph-pre-ram; + bootph-all; }; &pd_conn_sdch0 { - bootph-pre-ram; + bootph-all; }; &pd_conn_sdch1 { - bootph-pre-ram; + bootph-all; }; &pd_conn_sdch2 { - bootph-pre-ram; + bootph-all; }; &gpio0 { - bootph-pre-ram; + bootph-all; }; &gpio1 { - bootph-pre-ram; + bootph-all; }; &gpio2 { - bootph-pre-ram; + bootph-all; }; &gpio3 { - bootph-pre-ram; + bootph-all; }; &gpio4 { - bootph-pre-ram; + bootph-all; }; &gpio5 { - bootph-pre-ram; + bootph-all; }; &gpio6 { - bootph-pre-ram; + bootph-all; }; &gpio7 { - bootph-pre-ram; + bootph-all; }; &lpuart0 { - bootph-pre-ram; + bootph-all; }; &lpuart2 { - bootph-pre-ram; + bootph-all; }; &usdhc1 { - bootph-pre-ram; + bootph-all; }; &usdhc2 { - bootph-pre-ram; + bootph-all; }; diff --git a/arch/arm/dts/imx8qxp-capricorn.dtsi b/arch/arm/dts/imx8-capricorn.dtsi index db5653ea1ff..3734a9d21f1 100644 --- a/arch/arm/dts/imx8qxp-capricorn.dtsi +++ b/arch/arm/dts/imx8-capricorn.dtsi @@ -9,124 +9,25 @@ /dts-v1/; #include "fsl-imx8qxp.dtsi" -#include "imx8qxp-capricorn-u-boot.dtsi" +#include "imx8-capricorn-u-boot.dtsi" / { - model = "Siemens Giedi"; - compatible = "siemens,capricorn", "fsl,imx8qxp"; - chosen { bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200"; stdout-path = &lpuart2; }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - run { - label = "run"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - flt { - label = "flt"; - gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - svc { - label = "svc"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - com1_tx { - label = "com1-tx"; - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - com1_rx { - label = "com1-rx"; - gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - com2_tx { - label = "com2-tx"; - gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - com2_rx { - label = "com2-rx"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - cloud { - label = "cloud"; - gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - wlan { - label = "wlan"; - gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - dbg1 { - label = "dbg1"; - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - dbg2 { - label = "dbg2"; - gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - dbg3 { - label = "dbg3"; - gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - dbg4 { - label = "dbg4"; - gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; + /* create device for u-boot wdt command */ + scu-wdt { + compatible = "siemens,scu-wdt"; }; + }; &iomuxc { pinctrl-names = "default"; muxcgrp: imx8qxp-som { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021 - SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 0x06000021 - SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x06000021 - SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x06000021 - SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x06000021 - SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x06000021 - SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021 - SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021 - SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x06000021 - SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 - SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x06000021 - SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 - SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021 - >; - }; - pinctrl_lpi2c0: lpi2c0grp { fsl,pins = < SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x0C000020 diff --git a/arch/arm/dts/imx8-deneb.dts b/arch/arm/dts/imx8-deneb.dts deleted file mode 100644 index 04c764aa941..00000000000 --- a/arch/arm/dts/imx8-deneb.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 Siemens AG - */ - -#include "imx8qxp-capricorn.dtsi" - -/ { - model = "Siemens Deneb"; -}; diff --git a/arch/arm/dts/imx8-giedi.dts b/arch/arm/dts/imx8-giedi.dts deleted file mode 100644 index 0dbfef2ee97..00000000000 --- a/arch/arm/dts/imx8-giedi.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 Siemens AG - */ - -#include "imx8qxp-capricorn.dtsi" - -/ { - model = "Siemens Giedi"; -}; diff --git a/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi b/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi index 516e52e1f5d..512dbc9ee86 100644 --- a/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi @@ -14,6 +14,10 @@ }; }; +&pinctrl_i2c1 { + bootph-pre-ram; +}; + &pinctrl_uart3 { bootph-pre-ram; }; @@ -54,6 +58,10 @@ bootph-pre-ram; }; +&i2c1 { + bootph-pre-ram; +}; + &uart3 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index 6875c6d44ff..6d80d856365 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -68,6 +68,11 @@ bootph-all; }; +&osc_32k { + bootph-pre-ram; + bootph-all; +}; + #ifdef CONFIG_FSL_CAAM &sec_jr0 { bootph-pre-ram; diff --git a/arch/arm/dts/imx8qxp-u-boot.dtsi b/arch/arm/dts/imx8qxp-u-boot.dtsi index 62791c34c77..8058caae9ba 100644 --- a/arch/arm/dts/imx8qxp-u-boot.dtsi +++ b/arch/arm/dts/imx8qxp-u-boot.dtsi @@ -120,6 +120,7 @@ }; }; +#ifdef CONFIG_XPL_BUILD imx-boot { filename = "flash.bin"; pad-byte = <0x00>; @@ -130,4 +131,5 @@ type = "blob-ext"; }; }; +#endif }; diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi index 6897c91f4d9..0c3ca2961c9 100644 --- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi +++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi @@ -2,15 +2,22 @@ /* * Copyright (C) 2023 PHYTEC Messtechnik GmbH * Christoph Stoidner <c.stoidner@phytec.de> + * Copyright (C) 2024 PHYTEC Messtechnik GmbH * * Product homepage: - * phyBOARD-Segin carrier board is reused for the i.MX93 design. - * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ + https://www.phytec.de/produkte/system-on-modules/phycore-imx-91-93/ */ #include "imx93-u-boot.dtsi" / { + /* + * The phyCORE-i.MX93 u-boot uses the imx93-phyboard-segin.dts as + * reference, but does only make use of its SoM (phyCORE) contained + * periphery. + */ + model = "PHYTEC phyCORE-i.MX93"; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog3>; @@ -139,6 +146,13 @@ &usdhc1 { bootph-pre-ram; bootph-some-ram; + /* + * Remove pinctrl assignments once they are added to imx93-phycore-som.dtsi + */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; }; &usdhc2 { @@ -215,6 +229,48 @@ MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e >; }; + + /* + * Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz once they + * are added to imx93-phycore-som.dtsi + */ + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + bootph-pre-ram; + bootph-some-ram; + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + bootph-pre-ram; + bootph-some-ram; + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; }; &lpi2c3 { @@ -305,4 +361,13 @@ }; }; }; + + eeprom@50 { + bootph-pre-ram; + bootph-some-ram; + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <&buck4>; + }; }; diff --git a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi index 4b8d73a92d6..4ca05f32f0b 100644 --- a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi @@ -109,10 +109,6 @@ bootph-all; }; -&ospi0 { - status = "disabled"; -}; - &ospi1 { status = "disabled"; }; diff --git a/arch/arm/dts/k3-am68-sk-r5-base-board.dts b/arch/arm/dts/k3-am68-sk-r5-base-board.dts index 3b2d7af2e52..b61d22b3b4b 100644 --- a/arch/arm/dts/k3-am68-sk-r5-base-board.dts +++ b/arch/arm/dts/k3-am68-sk-r5-base-board.dts @@ -10,3 +10,8 @@ #include "k3-j721s2-ddr.dtsi" #include "k3-am68-sk-base-board-u-boot.dtsi" #include "k3-j721s2-r5.dtsi" + +&wkup_vtm0 { + bootph-pre-ram; + vdd-supply-2 = <&tps62873a>; +}; diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index 69bf9993077..5fc4a39c8c4 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -23,11 +23,12 @@ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>, <&k3_clks 202 2>; - clock-names = "gtc", "core"; - assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>; - assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>; - assigned-clock-rates = <2000000000>, <200000000>; + clocks = <&k3_clks 61 1>, <&k3_clks 202 2>, <&k3_clks 4 1> ; + clock-names = "gtc", "core", "msmc"; + assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 4 1>, + <&k3_clks 323 0>; + assigned-clock-parents= <0>, <0>, <0>, <&k3_clks 323 2>; + assigned-clock-rates = <2000000000>, <200000000>, <1000000000>; ti,sci = <&dmsc>; ti,sci-proc-id = <32>; ti,sci-host-id = <10>; diff --git a/arch/arm/dts/k3-j784s4-r5.dtsi b/arch/arm/dts/k3-j784s4-r5.dtsi index b377a47ed22..a1394115b8b 100644 --- a/arch/arm/dts/k3-j784s4-r5.dtsi +++ b/arch/arm/dts/k3-j784s4-r5.dtsi @@ -107,3 +107,9 @@ &mcu_udmap { ti,sci = <&dm_tifs>; }; + +&wkup_vtm0 { + bootph-pre-ram; + vdd-supply-2 = <&tps62873a>; +}; + diff --git a/arch/arm/dts/meson-a1.dtsi b/arch/arm/dts/meson-a1.dtsi deleted file mode 100644 index 648e7f49424..00000000000 --- a/arch/arm/dts/meson-a1.dtsi +++ /dev/null @@ -1,518 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ - -#include <dt-bindings/clock/amlogic,a1-pll-clkc.h> -#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h> -#include <dt-bindings/gpio/meson-a1-gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/power/meson-a1-power.h> -#include <dt-bindings/reset/amlogic,meson-a1-reset.h> - -/ { - compatible = "amlogic,a1"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - efuse: efuse { - compatible = "amlogic,meson-gxbb-efuse"; - clocks = <&clkc_periphs CLKID_OTP>; - #address-cells = <1>; - #size-cells = <1>; - secure-monitor = <&sm>; - power-domains = <&pwrc PWRC_OTP_ID>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x0 0x800000>; - alignment = <0x0 0x400000>; - linux,cma-default; - }; - }; - - sm: secure-monitor { - compatible = "amlogic,meson-gxbb-sm"; - - pwrc: power-controller { - compatible = "amlogic,meson-a1-pwrc"; - #power-domain-cells = <1>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - spifc: spi@fd000400 { - compatible = "amlogic,a1-spifc"; - reg = <0x0 0xfd000400 0x0 0x290>; - clocks = <&clkc_periphs CLKID_SPIFC>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&pwrc PWRC_SPIFC_ID>; - status = "disabled"; - }; - - apb: bus@fe000000 { - compatible = "simple-bus"; - reg = <0x0 0xfe000000 0x0 0x1000000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; - - reset: reset-controller@0 { - compatible = "amlogic,meson-a1-reset"; - reg = <0x0 0x0 0x0 0x8c>; - #reset-cells = <1>; - }; - - periphs_pinctrl: pinctrl@400 { - compatible = "amlogic,meson-a1-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@400 { - reg = <0x0 0x0400 0x0 0x003c>, - <0x0 0x0480 0x0 0x0118>; - reg-names = "mux", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&periphs_pinctrl 0 0 62>; - }; - - i2c0_f11_pins: i2c0-f11 { - mux { - groups = "i2c0_sck_f11", - "i2c0_sda_f12"; - function = "i2c0"; - bias-pull-up; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_f9_pins: i2c0-f9 { - mux { - groups = "i2c0_sck_f9", - "i2c0_sda_f10"; - function = "i2c0"; - bias-pull-up; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_x_pins: i2c1-x { - mux { - groups = "i2c1_sck_x", - "i2c1_sda_x"; - function = "i2c1"; - bias-pull-up; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_a_pins: i2c1-a { - mux { - groups = "i2c1_sck_a", - "i2c1_sda_a"; - function = "i2c1"; - bias-pull-up; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_x0_pins: i2c2-x0 { - mux { - groups = "i2c2_sck_x0", - "i2c2_sda_x1"; - function = "i2c2"; - bias-pull-up; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_x15_pins: i2c2-x15 { - mux { - groups = "i2c2_sck_x15", - "i2c2_sda_x16"; - function = "i2c2"; - bias-pull-up; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_a4_pins: i2c2-a4 { - mux { - groups = "i2c2_sck_a4", - "i2c2_sda_a5"; - function = "i2c2"; - bias-pull-up; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_a8_pins: i2c2-a8 { - mux { - groups = "i2c2_sck_a8", - "i2c2_sda_a9"; - function = "i2c2"; - bias-pull-up; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_x_pins: i2c3-x { - mux { - groups = "i2c3_sck_x", - "i2c3_sda_x"; - function = "i2c3"; - bias-pull-up; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_f_pins: i2c3-f { - mux { - groups = "i2c3_sck_f", - "i2c3_sda_f"; - function = "i2c3"; - bias-pull-up; - drive-strength-microamp = <3000>; - }; - }; - - uart_a_pins: uart-a { - mux { - groups = "uart_a_tx", - "uart_a_rx"; - function = "uart_a"; - }; - }; - - uart_a_cts_rts_pins: uart-a-cts-rts { - mux { - groups = "uart_a_cts", - "uart_a_rts"; - function = "uart_a"; - bias-pull-down; - }; - }; - - sdio_pins: sdio { - mux0 { - groups = "sdcard_d0_x", - "sdcard_d1_x", - "sdcard_d2_x", - "sdcard_d3_x", - "sdcard_cmd_x"; - function = "sdcard"; - bias-pull-up; - }; - - mux1 { - groups = "sdcard_clk_x"; - function = "sdcard"; - bias-disable; - }; - }; - - sdio_clk_gate_pins: sdio-clk-gate { - mux { - groups = "sdcard_clk_x"; - function = "sdcard"; - bias-pull-down; - }; - }; - - spifc_pins: spifc { - mux { - groups = "spif_mo", - "spif_mi", - "spif_clk", - "spif_cs", - "spif_hold_n", - "spif_wp_n"; - function = "spif"; - }; - }; - }; - - gpio_intc: interrupt-controller@440 { - compatible = "amlogic,meson-a1-gpio-intc", - "amlogic,meson-gpio-intc"; - reg = <0x0 0x0440 0x0 0x14>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = - <49 50 51 52 53 54 55 56>; - }; - - clkc_periphs: clock-controller@800 { - compatible = "amlogic,a1-peripherals-clkc"; - reg = <0 0x800 0 0x104>; - #clock-cells = <1>; - clocks = <&clkc_pll CLKID_FCLK_DIV2>, - <&clkc_pll CLKID_FCLK_DIV3>, - <&clkc_pll CLKID_FCLK_DIV5>, - <&clkc_pll CLKID_FCLK_DIV7>, - <&clkc_pll CLKID_HIFI_PLL>, - <&xtal>; - clock-names = "fclk_div2", "fclk_div3", - "fclk_div5", "fclk_div7", - "hifi_pll", "xtal"; - }; - - i2c0: i2c@1400 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1400 0x0 0x20>; - interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc_periphs CLKID_I2C_M_A>; - power-domains = <&pwrc PWRC_I2C_ID>; - }; - - uart_AO: serial@1c00 { - compatible = "amlogic,meson-a1-uart", - "amlogic,meson-ao-uart"; - reg = <0x0 0x1c00 0x0 0x18>; - interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&xtal>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_AO_B: serial@2000 { - compatible = "amlogic,meson-a1-uart", - "amlogic,meson-ao-uart"; - reg = <0x0 0x2000 0x0 0x18>; - interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&xtal>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - saradc: adc@2c00 { - compatible = "amlogic,meson-g12a-saradc", - "amlogic,meson-saradc"; - reg = <0x0 0x2c00 0x0 0x48>; - #io-channel-cells = <1>; - power-domains = <&pwrc PWRC_I2C_ID>; - interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, - <&clkc_periphs CLKID_SARADC_EN>, - <&clkc_periphs CLKID_SARADC>, - <&clkc_periphs CLKID_SARADC_SEL>; - clock-names = "clkin", "core", - "adc_clk", "adc_sel"; - status = "disabled"; - }; - - i2c1: i2c@5c00 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x5c00 0x0 0x20>; - interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc_periphs CLKID_I2C_M_B>; - power-domains = <&pwrc PWRC_I2C_ID>; - }; - - i2c2: i2c@6800 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x6800 0x0 0x20>; - interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc_periphs CLKID_I2C_M_C>; - power-domains = <&pwrc PWRC_I2C_ID>; - }; - - i2c3: i2c@6c00 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x6c00 0x0 0x20>; - interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc_periphs CLKID_I2C_M_D>; - power-domains = <&pwrc PWRC_I2C_ID>; - }; - - usb2_phy1: phy@4000 { - compatible = "amlogic,a1-usb2-phy"; - clocks = <&clkc_periphs CLKID_USB_PHY_IN>; - clock-names = "xtal"; - reg = <0x0 0x4000 0x0 0x60>; - resets = <&reset RESET_USBPHY>; - reset-names = "phy"; - #phy-cells = <0>; - power-domains = <&pwrc PWRC_USB_ID>; - }; - - hwrng: rng@5118 { - compatible = "amlogic,meson-rng"; - reg = <0x0 0x5118 0x0 0x4>; - power-domains = <&pwrc PWRC_OTP_ID>; - }; - - sec_AO: ao-secure@5a20 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x5a20 0x0 0x140>; - amlogic,has-chip-id; - }; - - clkc_pll: pll-clock-controller@7c80 { - compatible = "amlogic,a1-pll-clkc"; - reg = <0 0x7c80 0 0x18c>; - #clock-cells = <1>; - clocks = <&clkc_periphs CLKID_FIXPLL_IN>, - <&clkc_periphs CLKID_HIFIPLL_IN>; - clock-names = "fixpll_in", "hifipll_in"; - }; - - sd_emmc: sd@10000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0x10000 0x0 0x800>; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc_periphs CLKID_SD_EMMC_A>, - <&clkc_periphs CLKID_SD_EMMC>, - <&clkc_pll CLKID_FCLK_DIV2>; - clock-names = "core", - "clkin0", - "clkin1"; - assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>; - assigned-clock-parents = <&xtal>; - resets = <&reset RESET_SD_EMMC_A>; - power-domains = <&pwrc PWRC_SD_EMMC_ID>; - status = "disabled"; - }; - }; - - usb: usb@fe004400 { - status = "disabled"; - compatible = "amlogic,meson-a1-usb-ctrl"; - reg = <0x0 0xfe004400 0x0 0xa0>; - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc_periphs CLKID_USB_CTRL>, - <&clkc_periphs CLKID_USB_BUS>, - <&clkc_periphs CLKID_USB_CTRL_IN>; - clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl"; - resets = <&reset RESET_USBCTRL>; - reset-name = "usb_ctrl"; - - dr_mode = "otg"; - - phys = <&usb2_phy1>; - phy-names = "usb2-phy1"; - - dwc3: usb@ff400000 { - compatible = "snps,dwc3"; - reg = <0x0 0xff400000 0x0 0x100000>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - snps,dis_u2_susphy_quirk; - snps,quirk-frame-length-adjustment = <0x20>; - snps,parkmode-disable-ss-quirk; - }; - - dwc2: usb@ff500000 { - compatible = "amlogic,meson-a1-usb", "snps,dwc2"; - reg = <0x0 0xff500000 0x0 0x40000>; - interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb2_phy1>; - phy-names = "usb2-phy"; - clocks = <&clkc_periphs CLKID_USB_PHY>; - clock-names = "otg"; - dr_mode = "peripheral"; - g-rx-fifo-size = <192>; - g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 16 16 16>; - }; - }; - - gic: interrupt-controller@ff901000 { - compatible = "arm,gic-400"; - reg = <0x0 0xff901000 0x0 0x1000>, - <0x0 0xff902000 0x0 0x2000>, - <0x0 0xff904000 0x0 0x2000>, - <0x0 0xff906000 0x0 0x2000>; - interrupt-controller; - interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; -}; diff --git a/arch/arm/dts/zynqmp-binman-mini.dts b/arch/arm/dts/zynqmp-binman-mini.dts new file mode 100644 index 00000000000..8f3d18ef394 --- /dev/null +++ b/arch/arm/dts/zynqmp-binman-mini.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2024, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; + +#include "zynqmp-u-boot.dtsi" diff --git a/arch/arm/dts/zynqmp-binman-som.dts b/arch/arm/dts/zynqmp-binman-som.dts new file mode 100644 index 00000000000..3d9d8476c98 --- /dev/null +++ b/arch/arm/dts/zynqmp-binman-som.dts @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP SOMs (k24/k26) + * + * (C) Copyright 2024, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <config.h> + +/dts-v1/; +/ { + binman: binman { + multiple-images; + fit-dtb.blob { + filename = "fit-dtb.blob"; + pad-byte = <0>; + fit { + fit,align = <0x8>; + fit,external-offset = <0x0>; + description = "DTBs for SOMs+CCs"; + fit,fdt-list-val = "zynqmp-smk-k26-revA", "zynqmp-smk-k26-revA-sck-kr-g-revA", + "zynqmp-smk-k26-revA-sck-kr-g-revB", "zynqmp-smk-k26-revA-sck-kv-g-revA", + "zynqmp-smk-k26-revA-sck-kv-g-revB", "zynqmp-sm-k26-revA-sck-kv-g-revA", + "zynqmp-sm-k26-revA-sck-kv-g-revB", "zynqmp-sm-k26-revA-sck-kr-g-revB", + "zynqmp-smk-k24-revA-sck-kd-g-revA", "zynqmp-smk-k24-revA-sck-kv-g-revB", + "zynqmp-smk-k24-revA-sck-kr-g-revB", "zynqmp-sm-k24-revA-sck-kd-g-revA", + "zynqmp-sm-k24-revA-sck-kv-g-revB", "zynqmp-sm-k24-revA-sck-kr-g-revB"; + + images { + @fdt-SEQ { + description = "NAME"; + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + hash-1 { + algo = "md5"; + }; + }; + }; + configurations { + default = "conf-1"; + conf-1 { + description = "SOM itself"; + fdt = "fdt-1"; + }; + conf-2 { + description = "zynqmp-smk-k26-.*-sck-kr-g-revA"; + fdt = "fdt-2"; + }; + conf-3 { + description = "zynqmp-smk-k26-.*-sck-kr-g-.*"; + fdt = "fdt-3"; + }; + conf-4 { + description = "zynqmp-smk-k26-.*-sck-kv-g-rev[AZ]"; + fdt = "fdt-4"; + }; + conf-5 { + description = "zynqmp-smk-k26-.*-sck-kv-g-.*"; + fdt = "fdt-5"; + }; + conf-6 { + description = "zynqmp-sm-k26-.*-sck-kv-g-rev[AZ]"; + fdt = "fdt-6"; + }; + conf-7 { + description = "zynqmp-sm-k26-.*-sck-kv-g-.*"; + fdt = "fdt-7"; + }; + conf-8 { + description = "zynqmp-sm-k26-.*-sck-kr-g-.*"; + fdt = "fdt-8"; + }; + conf-9 { + description = "zynqmp-smk-k24-.*-sck-kd-g-.*"; + fdt = "fdt-9"; + }; + conf-10 { + description = "zynqmp-smk-k24-.*-sck-kv-g-.*"; + fdt = "fdt-10"; + }; + conf-11 { + description = "zynqmp-smk-k24-.*-sck-kr-g-.*"; + fdt = "fdt-11"; + }; + conf-12 { + description = "zynqmp-sm-k24-.*-sck-kd-g-.*"; + fdt = "fdt-12"; + }; + conf-13 { + description = "zynqmp-sm-k24-.*-sck-kv-g-.*"; + fdt = "fdt-13"; + }; + conf-14 { + description = "zynqmp-sm-k24-.*-sck-kr-g-.*"; + fdt = "fdt-14"; + }; + }; + }; + }; + + /* u-boot.itb generation in a static way */ + itb { + filename = "u-boot.itb"; + pad-byte = <0>; + + fit { + description = "Configuration for Xilinx ZynqMP SoC"; + fit,align = <0x8>; + fit,external-offset = <0x0>; + images { + uboot { + description = "U-Boot (64-bit)"; + type = "firmware"; + os = "u-boot"; + arch = "arm64"; + compression = "none"; + load = /bits/ 64 <CONFIG_TEXT_BASE>; + entry = /bits/ 64 <CONFIG_TEXT_BASE>; + hash { + algo = "md5"; + }; + u-boot-nodtb { + }; + }; + atf { + description = "Trusted Firmware-A"; + type = "firmware"; + os = "arm-trusted-firmware"; + arch = "arm64"; + compression = "none"; + load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + hash { + algo = "md5"; + }; + atf-bl31 { + optional; + }; + }; + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + tee-os { + optional; + }; + }; + fdt { + description = "Multi DTB fit image"; + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + load = <0x0 0x100000>; + hash { + algo = "md5"; + }; + fdt-blob { + filename = "fit-dtb.blob"; + type = "blob-ext"; + }; + }; + }; + configurations { + default = "conf-1"; + conf-1 { + description = "Multi DTB with TF-A/TEE"; + firmware = "atf"; + loadables = "tee", "uboot", "fdt"; + }; + }; + }; + }; + + /* boot.bin generated with version string inside */ + bootimage { + filename = "boot.bin"; + pad-byte = <0>; + + blob-ext@1 { + offset = <0x0>; + filename = "spl/boot.bin"; + }; + /* Optional version string at offset 0x70 */ + blob-ext@2 { + offset = <0x70>; + filename = "version.bin"; + overlap; + optional; + }; + /* Optional version string at offset 0x94 */ + blob-ext@3 { + offset = <0x94>; + filename = "version.bin"; + overlap; + optional; + }; + }; + +#ifdef CONFIG_SYS_SPI_U_BOOT_OFFS + /* Full QSPI image for recovery app */ + image { + filename = "qspi.bin"; + pad-byte = <0>; + + blob-ext@1 { + offset = <0x0>; + filename = "boot.bin"; + }; + blob-ext@2 { + offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; + filename = "u-boot.itb"; + }; + fdtmap { + }; + }; +#endif + }; +}; diff --git a/arch/arm/dts/zynqmp-binman.dts b/arch/arm/dts/zynqmp-binman.dts new file mode 100644 index 00000000000..675f6bf51eb --- /dev/null +++ b/arch/arm/dts/zynqmp-binman.dts @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP platforms + * + * (C) Copyright 2024, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <config.h> + +/dts-v1/; +/ { + binman: binman { + multiple-images; + + /* u-boot.itb generation in a static way */ + itb { + filename = "u-boot.itb"; + pad-byte = <0>; + + fit { + description = "Configuration for Xilinx ZynqMP SoC"; + fit,align = <0x8>; + fit,external-offset = <0x0>; + fit,fdt-list = "of-list"; + images { + uboot { + description = "U-Boot (64-bit)"; + type = "firmware"; + os = "u-boot"; + arch = "arm64"; + compression = "none"; + load = /bits/ 64 <CONFIG_TEXT_BASE>; + entry = /bits/ 64 <CONFIG_TEXT_BASE>; + hash { + algo = "md5"; + }; + u-boot-nodtb { + }; + }; + atf { + description = "Trusted Firmware-A"; + type = "firmware"; + os = "arm-trusted-firmware"; + arch = "arm64"; + compression = "none"; + load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + hash { + algo = "md5"; + }; + atf-bl31 { + optional; + }; + }; + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + tee-os { + optional; + }; + }; + @fdt-SEQ { + description = "NAME"; + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + load = <0x0 0x100000>; + hash-1 { + algo = "md5"; + }; + }; + }; + configurations { + default = "@conf-DEFAULT-SEQ"; + @conf-SEQ { + description = "NAME"; + firmware = "atf"; + loadables = "tee", "uboot"; + fdt = "fdt-SEQ"; + }; + }; + }; + }; + + itb-single { + filename = "u-boot-single.itb"; + pad-byte = <0>; + + fit { + description = "Configuration for Xilinx ZynqMP SoC"; + fit,align = <0x8>; + fit,external-offset = <0x0>; + fit,fdt-list = "of-list"; + images { + uboot { + description = "U-Boot (64-bit)"; + type = "firmware"; + os = "u-boot"; + arch = "arm64"; + compression = "none"; + load = /bits/ 64 <CONFIG_TEXT_BASE>; + entry = /bits/ 64 <CONFIG_TEXT_BASE>; + hash { + algo = "md5"; + }; + u-boot-nodtb { + }; + }; + atf { + description = "Trusted Firmware-A"; + type = "firmware"; + os = "arm-trusted-firmware"; + arch = "arm64"; + compression = "none"; + load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + hash { + algo = "md5"; + }; + atf-bl31 { + optional; + }; + }; + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + tee-os { + optional; + }; + }; + fdt { + description = "DT"; + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + load = <0x0 0x100000>; + uboot-fdt-blob { + filename = "u-boot.dtb"; + type = "blob-ext"; + }; + hash-1 { + algo = "md5"; + }; + + }; + }; + configurations { + default = "conf-1"; + conf-1 { + description = "Single DT"; + firmware = "atf"; + loadables = "tee", "uboot"; + fdt = "fdt"; + }; + }; + }; + }; + +#ifdef CONFIG_SYS_SPI_U_BOOT_OFFS + /* QSPI image for testing QSPI boot mode */ + image { + filename = "qspi.bin"; + pad-byte = <0>; + + blob-ext@1 { + offset = <0x0>; + filename = "spl/boot.bin"; + }; + blob-ext@2 { + offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; + filename = "u-boot.itb"; + }; + fdtmap { + }; + }; + + image-single { + filename = "qspi-single.bin"; + pad-byte = <0>; + + blob-ext@1 { + offset = <0x0>; + filename = "spl/boot.bin"; + }; + blob-ext@2 { + offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; + filename = "u-boot-single.itb"; + }; + fdtmap { + }; + }; +#endif + }; +}; diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index dd4569e7bd9..60d1b1acf9a 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -70,6 +70,22 @@ clocks = <&zynqmp_clk ACPU>; }; +&cpu0_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + +&cpu1_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + +&cpu2_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + +&cpu3_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + &fpd_dma_chan1 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts index 1af3f643567..c4f70581695 100644 --- a/arch/arm/dts/zynqmp-sc-revB.dts +++ b/arch/arm/dts/zynqmp-sc-revB.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP Generic System Controller * * (C) Copyright 2021 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2024, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -80,7 +80,7 @@ pwm-fan { compatible = "pwm-fan"; status = "okay"; - pwms = <&ttc0 2 40000 1>; + pwms = <&ttc0 2 40000 0>; }; }; diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 4de29d5d3ff..d56e863ce1c 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -80,7 +80,10 @@ "", ""; }; - /* usb5744@2d */ + hub: usb-hub@2d { /* u36 */ + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; }; /* USB 3.0 */ @@ -99,18 +102,6 @@ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; -#if 0 - usbhub0: usb-hub { /* u36 */ - i2c-bus = <&i2c1>; - compatible = "microchip,usb5744"; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; - }; - - usb2244: usb-sd { /* u41 */ - compatible = "microchip,usb2244"; - reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_0 { @@ -118,6 +109,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; }; &gem1 { /* mdio mio50/51 */ diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 6349a0e1087..9d0c0c2885d 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -105,11 +105,19 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; + hub_1: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; }; usbhub_i2c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + hub_2: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; }; /* Bus 2/3 are not connected */ }; @@ -145,18 +153,6 @@ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; -#if 0 - usbhub0: usb-hub { /* u43 */ - i2c-bus = <&usbhub_i2c0>; - compatible = "microchip,usb5744"; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; - }; - - usb2244: usb-sd { /* u38 */ - compatible = "microchip,usb2244"; - reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_0 { @@ -164,6 +160,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; }; &usb1 { /* mio64 - mio75 */ @@ -174,13 +190,6 @@ phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; -#if 0 - usbhub1: usb-hub { /* u84 */ - i2c-bus = <&usbhub_i2c1>; - compatible = "microchip,usb5744"; - reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_1 { @@ -188,6 +197,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub1_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub1_3_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub1_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub1_2_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; }; &gem0 { /* mdio mio50/51 */ diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index b0d737d3caf..0d915d496ca 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -117,11 +117,19 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; + hub_1: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; }; usbhub_i2c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + hub_2: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; }; /* Bus 2/3 are not connected */ }; @@ -165,18 +173,6 @@ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; -#if 0 - usbhub0: usb-hub { /* u43 */ - i2c-bus = <&usbhub_i2c0>; - compatible = "microchip,usb5744"; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; - }; - - usb2244: usb-sd { /* u38 */ - compatible = "microchip,usb2244"; - reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_0 { @@ -184,6 +180,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; }; &usb1 { /* mio64 - mio75 */ @@ -194,14 +210,6 @@ phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; assigned-clock-rates = <250000000>, <20000000>; - -#if 0 - usbhub1: usb-hub { /* u84 */ - i2c-bus = <&usbhub_i2c1>; - compatible = "microchip,usb5744"; - reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_1 { @@ -209,6 +217,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub1_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub1_3_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub1_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub1_2_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; }; &gem0 { /* mdio mio50/51 */ diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 561b546e37f..a98a888d138 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -129,12 +129,6 @@ pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; -#if 0 - usbhub: usb5744 { /* u43 */ - compatible = "microchip,usb5744"; - reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_0 { @@ -142,6 +136,24 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; }; &sdhci1 { /* on CC with tuned parameters */ diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 64683e0ccbb..7490efea98b 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -92,7 +92,10 @@ label = "ina260-u14"; reg = <0x40>; }; - /* u43 - 0x2d - USB hub */ + hub: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ }; @@ -131,14 +134,6 @@ phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; assigned-clock-rates = <250000000>, <20000000>; -#if 0 - usb5744: usb-hub { /* u43 */ - status = "okay"; - compatible = "microchip,usb5744"; - i2c-bus = <&i2c1>; - reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - }; -#endif }; &dwc3_0 { @@ -146,6 +141,26 @@ dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; }; &sdhci1 { /* on CC with tuned parameters */ diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 8056f6b176e..620f5185cc4 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A * * (C) Copyright 2020 - 2021, Xilinx, Inc. - * (C) Copyright 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -387,6 +387,7 @@ &rtc { status = "okay"; + calibration = <0x7fff>; }; &lpd_dma_chan1 { diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts index 719a4e49b57..b804abe89d1 100644 --- a/arch/arm/dts/zynqmp-smk-k26-revA.dts +++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A * * (C) Copyright 2020 - 2021, Xilinx, Inc. - * (C) Copyright 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ diff --git a/arch/arm/dts/zynqmp-u-boot.dtsi b/arch/arm/dts/zynqmp-u-boot.dtsi new file mode 100644 index 00000000000..9a7527ed5a1 --- /dev/null +++ b/arch/arm/dts/zynqmp-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2024, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/ { + binman: binman { + }; +}; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 3132fa533b8..dd63d22f45e 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -960,6 +960,7 @@ &pcie { status = "okay"; + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; }; &psgtr { diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index 095c972f132..b75b2a796eb 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -15,8 +15,7 @@ / { model = "ZynqMP ZCU1275 RevA"; - compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", - "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 6a29f610153..70ca5e6379f 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -168,8 +168,8 @@ bootph-all; }; - pmu: pmu { - compatible = "arm,armv8-pmuv3"; + pmu { + compatible = "arm,cortex-a53-pmu"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, @@ -441,6 +441,34 @@ }; }; + cpu0_debug: debug@fec10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfec10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; + + cpu1_debug: debug@fed10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfed10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + }; + + cpu2_debug: debug@fee10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfee10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + }; + + cpu3_debug: debug@fef10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfef10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + }; + /* GDMA */ fpd_dma_chan1: dma-controller@fd500000 { status = "disabled"; @@ -885,7 +913,6 @@ power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */ - /* dma-coherent; */ }; sdhci0: mmc@ff160000 { @@ -1065,9 +1092,9 @@ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ref"; /* iommus = <&smmu 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; - clock-names = "ref"; snps,resume-hs-terminations; /* dma-coherent; */ }; @@ -1097,9 +1124,9 @@ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ref"; /* iommus = <&smmu 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; - clock-names = "ref"; snps,resume-hs-terminations; /* dma-coherent; */ }; @@ -1176,11 +1203,14 @@ "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; resets = <&zynqmp_reset ZYNQMP_RESET_DP>; - dma-names = "vid0", "vid1", "vid2", "gfx0"; + dma-names = "vid0", "vid1", "vid2", "gfx0", + "aud0", "aud1"; dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, - <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; + <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>, + <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO0>, + <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO1>; ports { #address-cells = <1>; diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 52f6c9b934d..dbf9ab43e28 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -171,7 +171,7 @@ static inline unsigned int current_el(void) return 3 & (el >> 2); } -static inline unsigned int get_sctlr(void) +static inline unsigned long get_sctlr(void) { unsigned int el; unsigned long val; diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 192c120a7d2..974cbfe8400 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -73,11 +73,10 @@ static void announce_and_cleanup(int fake) * Call remove function of all devices with a removal flag set. * This may be useful for last-stage operations, like cancelling * of DMA operation or releasing device internal buffers. + * dm_remove_devices_active() ensures that vital devices are removed in + * a second round. */ - dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL); - - /* Remove all active vital devices next */ - dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); + dm_remove_devices_active(); cleanup_before_linux(); } diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index 1e7dc10e170..9cf60378c11 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -16,8 +16,8 @@ choice config ASPEED_AST2500 bool "Support Aspeed AST2500 SoC" - depends on DM_RESET select CPU_ARM1176 + select DM_RESET help The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU. It is used as Board Management Controller on many server boards, diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c index 05390c16f3a..0c5a82ed094 100644 --- a/arch/arm/mach-aspeed/ast2600/spl.c +++ b/arch/arm/mach-aspeed/ast2600/spl.c @@ -45,10 +45,10 @@ u32 spl_boot_device(void) } /* boot from UART has higher priority */ - if (scu->hwstrap2 & SCU_HWSTRAP2_BOOT_UART) + if (readl(&scu->hwstrap2) & SCU_HWSTRAP2_BOOT_UART) return BOOT_DEVICE_UART; - if (scu->hwstrap1 & SCU_HWSTRAP1_BOOT_EMMC) + if (readl(&scu->hwstrap1) & SCU_HWSTRAP1_BOOT_EMMC) return BOOT_DEVICE_MMC1; out: diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 59d11b3179e..9a43beda6fa 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -54,15 +54,8 @@ config TARGET_COLIBRI_IMX8X select BOARD_LATE_INIT select IMX8QXP -config TARGET_DENEB - bool "Support i.MX8QXP Capricorn Deneb board" - select BINMAN - select BOARD_LATE_INIT - select FACTORYSET - select IMX8QXP - -config TARGET_GIEDI - bool "Support i.MX8QXP Capricorn Giedi board" +config TARGET_CAPRICORN + bool "Support i.MX8QXP Capricorn board" select BINMAN select BOARD_LATE_INIT select FACTORYSET diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 5c1054138fc..2465e31d738 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -45,6 +45,8 @@ config TARGET_PHYCORE_IMX93 bool "phycore_imx93" select IMX93 select IMX9_LPDDR4X + select OF_BOARD_FIXUP + select OF_BOARD_SETUP endchoice diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 21e0e7dd1e8..6837ac82b05 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -634,7 +634,7 @@ static int low_drive_freq_update(void *blob) return 0; } -#ifdef CONFIG_OF_BOARD_FIXUP +#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93) #ifndef CONFIG_XPL_BUILD int board_fix_fdt(void *fdt) { diff --git a/arch/arm/mach-k3/am62x/Kconfig b/arch/arm/mach-k3/am62x/Kconfig index 8b0cdd74f4f..81199ada3a1 100644 --- a/arch/arm/mach-k3/am62x/Kconfig +++ b/arch/arm/mach-k3/am62x/Kconfig @@ -42,6 +42,7 @@ config TARGET_PHYCORE_AM62X_R5 select SPL_RAM select K3_DDRSS select BINMAN + select PHYTEC_K3_DDR_PATCH imply SYS_K3_SPL_ATF config TARGET_VERDIN_AM62_A53 diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c index e9ed8cb267c..805b28af8e4 100644 --- a/arch/arm/mach-k3/j721e/j721e_init.c +++ b/arch/arm/mach-k3/j721e/j721e_init.c @@ -19,6 +19,7 @@ #include <fdtdec.h> #include <mmc.h> #include <remoteproc.h> +#include <k3-avs.h> #include "../sysfw-loader.h" #include "../common.h" @@ -39,6 +40,12 @@ #define NB_THREADMAP_BIT0 BIT(0) #define NB_THREADMAP_BIT1 BIT(1) +/* TISCI DEV ID for A72, MSMC Clock */ +#define DEV_A72SS0_CORE0_0_ID 202 +#define DEV_A72SS0_CORE0_0_ARM_CLK_CLK_ID 2 +#define DEV_A72SS0_CORE0_ID 4 +#define DEV_A72SS0_CORE0_MSMC_CLK_ID 1 + #ifdef CONFIG_K3_LOAD_SYSFW struct fwl_data cbass_hc_cfg0_fwls[] = { #if defined(CONFIG_TARGET_J721E_R5_EVM) @@ -147,6 +154,78 @@ static void setup_navss_nb(void) writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP); } +#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0) +static int get_clock_index_by_dev_id(ofnode node, u32 dev_id, u32 clk_id) +{ + ofnode clknode; + int count, i; + struct ofnode_phandle_args phandle_args; + + clknode = ofnode_by_compatible(ofnode_null(), "ti,k2g-sci-clk"); + if (!ofnode_valid(clknode)) { + printf("%s: clock-controller not found\n", __func__); + return -ENODEV; + } + + count = ofnode_count_phandle_with_args(node, "assigned-clocks", "#clock-cells", 0); + for (i = 0; i < count; i++) { + if (ofnode_parse_phandle_with_args(node, "assigned-clocks", + "#clock-cells", 0, i, &phandle_args)) { + printf("%s: Could not parse assigned-clocks at index %d\n", __func__, i); + continue; + } + if (ofnode_equal(clknode, phandle_args.node) && + phandle_args.args[0] == dev_id && phandle_args.args[1] == clk_id) + return i; + } + return -1; +} + +static int fdt_fixup_a72ss_clock_frequency(void) +{ + int index, size; + u32 *rates; + ofnode node; + + node = ofnode_by_compatible(ofnode_null(), "ti,am654-rproc"); + if (!ofnode_valid(node)) { + printf("%s: A72 not found\n", __func__); + return -ENODEV; + } + + rates = fdt_getprop_w(ofnode_to_fdt(node), ofnode_to_offset(node), + "assigned-clock-rates", &size); + if (!rates) { + printf("%s: Wrong A72 assigned-clocks-rates configuration\n", __func__); + return -1; + } + + /* Update A72 Clock Frequency to OPP_LOW spec */ + index = get_clock_index_by_dev_id(node, + DEV_A72SS0_CORE0_0_ID, + DEV_A72SS0_CORE0_0_ARM_CLK_CLK_ID); + if (index < 0 || index >= (size / sizeof(u32))) { + printf("%s: Wrong A72 assigned-clocks configuration\n", __func__); + return -1; + } + rates[index] = cpu_to_fdt32(1000000000); + printf("Changed A72 CPU frequency to %dHz in DT\n", 1000000000); + + /* Update MSMC Clock Frequency to OPP_LOW spec */ + index = get_clock_index_by_dev_id(node, + DEV_A72SS0_CORE0_ID, + DEV_A72SS0_CORE0_MSMC_CLK_ID); + if (index < 0 || index >= (size / sizeof(u32))) { + printf("%s: Wrong A72 assigned-clocks configuration\n", __func__); + return -1; + } + rates[index] = cpu_to_fdt32(500000000); + printf("Changed MSMC frequency to %dHz in DT\n", 500000000); + + return 0; +} +#endif + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -301,8 +380,19 @@ void board_init_f(ulong dummy) #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs), &dev); - if (ret) + if (ret) { printf("AVS init failed: %d\n", ret); + } else if (IS_ENABLED(CONFIG_K3_OPP_LOW)) { + ret = k3_avs_check_opp(dev, J721E_VDD_MPU, AM6_OPP_LOW); + if (ret) { + printf("OPP_LOW: k3_avs_check_opp failed: %d\n", ret); + } else { + ret = fdt_fixup_a72ss_clock_frequency(); + if (ret) + printf("OPP_LOW: fdt_fixup_a72ss_clock_frequency failed: %d\n", + ret); + } + } #endif #if defined(CONFIG_K3_J721E_DDRSS) diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c index 07b5d7d7504..8a41cd3bb50 100644 --- a/arch/arm/mach-k3/j784s4/j784s4_init.c +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c @@ -233,9 +233,19 @@ void k3_mem_init(void) void board_init_f(ulong dummy) { + struct udevice *dev; + int ret; + k3_spl_init(); k3_mem_init(); + if (IS_ENABLED(CONFIG_CPU_V7R) && IS_ENABLED(CONFIG_K3_AVS0)) { + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs), + &dev); + if (ret) + printf("AVS init failed: %d\n", ret); + } + if (IS_ENABLED(CONFIG_CPU_V7R)) setup_navss_nb(); diff --git a/arch/arm/mach-k3/r5/Kconfig b/arch/arm/mach-k3/r5/Kconfig index 878087fbf56..12335880e10 100644 --- a/arch/arm/mach-k3/r5/Kconfig +++ b/arch/arm/mach-k3/r5/Kconfig @@ -1,6 +1,13 @@ config K3_LOAD_SYSFW bool +config K3_OPP_LOW + depends on ARCH_K3 && K3_AVS0 + bool "Enable OPP_LOW on supported TI K3 SoCs" + help + Enabling this will allow Socs with the proper efuse to run at a lower + MPU core voltage and adjust frequency according to SoC TRM + config K3_QOS bool "Enable Quality of Service (QoS) Settings for TI K3 SoCs" default y if SOC_K3_AM62A7 diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 536960b83c3..976c0e35fce 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -11,6 +11,9 @@ config SYS_VENDOR Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will be used as the custom board directory. +config SYS_MALLOC_LEN + default 0x10000000 + config SYS_MALLOC_F_LEN default 0x2000 @@ -20,6 +23,9 @@ config SPL_SYS_MALLOC_F config SPL_SYS_MALLOC_F_LEN default 0x2000 +config SYS_MALLOC_LEN + default 0x800000 + config LNX_KRNL_IMG_TEXT_OFFSET_BASE default 0x80000000 diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 7a4495c8108..343e825c6fd 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -3,4 +3,5 @@ # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> obj-y += board.o +obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += capsule_update.o obj-$(CONFIG_OF_LIVE) += of_fixup.o diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 2ab2ceb5138..75a880f093c 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -6,7 +6,9 @@ * Author: Caleb Connolly <caleb.connolly@linaro.org> */ -#include "time.h" +#define LOG_CATEGORY LOGC_BOARD +#define pr_fmt(fmt) "QCOM: " fmt + #include <asm/armv8/mmu.h> #include <asm/gpio.h> #include <asm/io.h> @@ -29,6 +31,7 @@ #include <fdt_support.h> #include <usb.h> #include <sort.h> +#include <time.h> #include "qcom-priv.h" @@ -448,6 +451,9 @@ int board_late_init(void) configure_env(); qcom_late_init(); + /* Configure the dfu_string for capsule updates */ + qcom_configure_capsule_updates(); + return 0; } diff --git a/arch/arm/mach-snapdragon/capsule_update.c b/arch/arm/mach-snapdragon/capsule_update.c new file mode 100644 index 00000000000..bf75a9a1b24 --- /dev/null +++ b/arch/arm/mach-snapdragon/capsule_update.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Capsule update support for Qualcomm boards. + * + * Copyright (c) 2024 Linaro Ltd. + * Author: Caleb Connolly <caleb.connolly@linaro.org> + */ + +#define pr_fmt(fmt) "QCOM-FMP: " fmt + +#include <dm/device.h> +#include <dm/uclass.h> +#include <efi.h> +#include <efi_loader.h> +#include <malloc.h> +#include <scsi.h> +#include <part.h> +#include <linux/err.h> + +#include "qcom-priv.h" + +/* + * NOTE: for now this implementation only supports the rb3gen2. Supporting other + * boards that boot in different ways (e.g. chainloaded from ABL) will require + * additional complexity to properly create the dfu string and fw_images array. + */ + +/* + * To handle different variants like chainloaded U-Boot here we'll need to + * build the fw_images array dynamically at runtime. It looks like + * mach-rockchip is a good example for how to do this. + * Detecting which image types a board uses is TBD, hence for now we only + * support the one new board that runs U-Boot as its primary bootloader. + */ +struct efi_fw_image fw_images[] = { + { + /* U-Boot flashed to the uefi_X partition (e.g. rb3gen2) */ + .fw_name = u"UBOOT_UEFI_PARTITION", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + /* Filled in by configure_dfu_string() */ + .dfu_string = NULL, + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + +/* LSB first */ +struct part_slot_status { + u16: 2; + u16 active : 1; + u16: 3; + u16 successful : 1; + u16 unbootable : 1; + u16 tries_remaining : 4; +}; + +static int find_boot_partition(const char *partname, struct blk_desc *blk_dev, char *name) +{ + int ret; + int partnum; + struct disk_partition info; + struct part_slot_status *slot_status; + + for (partnum = 1;; partnum++) { + ret = part_get_info(blk_dev, partnum, &info); + if (ret) + return ret; + + slot_status = (struct part_slot_status *)&info.type_flags; + log_io("%16s: Active: %1d, Successful: %1d, Unbootable: %1d, Tries left: %1d\n", + info.name, slot_status->active, + slot_status->successful, slot_status->unbootable, + slot_status->tries_remaining); + /* + * FIXME: eventually we'll want to find the active/inactive variant of the partition + * but on the rb3gen2 these values might all be 0 + */ + if (!strncmp(info.name, partname, strlen(partname))) { + log_debug("Found active %s partition: '%s'!\n", partname, info.name); + strlcpy(name, info.name, sizeof(info.name)); + return partnum; + } + } + + return -1; +} + +/** + * qcom_configure_capsule_updates() - Configure the DFU string for capsule updates + * + * U-Boot is flashed to the boot partition on Qualcomm boards. In most cases there + * are two boot partitions, boot_a and boot_b. As we don't currently support doing + * full A/B updates, we only support updating the currently active boot partition. + * + * So we need to find the current slot suffix and the associated boot partition. + * We do this by looking for the boot partition that has the 'active' flag set + * in the GPT partition vendor attribute bits. + */ +void qcom_configure_capsule_updates(void) +{ + struct blk_desc *desc; + int ret = 0, partnum = -1, devnum; + static char dfu_string[32] = { 0 }; + char name[32]; /* GPT partition name */ + char *partname = "uefi_a"; + struct udevice *dev = NULL; + + if (IS_ENABLED(CONFIG_SCSI)) { + /* Scan for SCSI devices */ + ret = scsi_scan(false); + if (ret) { + debug("Failed to scan SCSI devices: %d\n", ret); + return; + } + } + + uclass_foreach_dev_probe(UCLASS_BLK, dev) { + if (device_get_uclass_id(dev) != UCLASS_BLK) + continue; + + desc = dev_get_uclass_plat(dev); + if (!desc || desc->part_type == PART_TYPE_UNKNOWN) + continue; + devnum = desc->devnum; + partnum = find_boot_partition(partname, desc, + name); + if (partnum >= 0) + break; + } + + if (partnum < 0) { + log_err("Failed to find boot partition\n"); + return; + } + + switch (desc->uclass_id) { + case UCLASS_SCSI: + snprintf(dfu_string, 32, "scsi %d=u-boot.bin part %d", devnum, partnum); + break; + case UCLASS_MMC: + snprintf(dfu_string, 32, "mmc 0=u-boot.bin part %d %d", devnum, partnum); + break; + default: + debug("Unsupported storage uclass: %d\n", desc->uclass_id); + return; + } + log_debug("boot partition is %s, DFU string: '%s'\n", name, dfu_string); + + update_info.dfu_string = dfu_string; +} diff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h index 0a7ed5eff8b..74d39197b89 100644 --- a/arch/arm/mach-snapdragon/qcom-priv.h +++ b/arch/arm/mach-snapdragon/qcom-priv.h @@ -3,6 +3,12 @@ #ifndef __QCOM_PRIV_H__ #define __QCOM_PRIV_H__ +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) +void qcom_configure_capsule_updates(void); +#else +void qcom_configure_capsule_updates(void) {} +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + #if CONFIG_IS_ENABLED(OF_LIVE) /** * qcom_of_fixup_nodes() - Fixup Qualcomm DT nodes diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index aea13622b68..92d61e84319 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -132,6 +132,20 @@ config SPL_ZYNQMP_RESTORE_JTAG even if no eFuses were burnt. This option restores the interface if possible. +config BL31_LOAD_ADDR + hex "Load address of BL31 image (mostly TF-A)" + default 0xfffea000 + help + The load address for the BL31 image. This value is used to build the + FIT image header that places BL31 in memory where it will run. + +config BL32_LOAD_ADDR + hex "Load address of BL32 image (mostly secure OS)" + default 0 + help + The load address for the BL32 image. This value is used to build the + FIT image header that places BL32 in memory where it will run. + config ZYNQ_SDHCI_MAX_FREQ default 200000000 diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index 49e449ebd61..3c372bd6dcf 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -188,6 +188,8 @@ struct pmu_regs { u32 gen_storage4; /* 0x40 */ u32 reserved1[1]; u32 gen_storage6; /* 0x48 */ + u32 reserved2[3]; + u32 pers_gen_storage2; /* 0x58 */ }; #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR) diff --git a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh deleted file mode 100755 index cdecb1c1d35..00000000000 --- a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh +++ /dev/null @@ -1,240 +0,0 @@ -#!/bin/sh -# SPDX-License-Identifier: GPL-2.0+ -# -# script to generate FIT image source for Xilinx ZynqMP boards with -# ARM Trusted Firmware and multiple device trees (given on the command line) -# -# usage: $0 <dt_name> [<dt_name> [<dt_name] ...] - -BL33="u-boot-nodtb.bin" -[ -z "$BL31" ] && BL31="bl31.bin" -BL31_ELF="${BL31%.*}.elf" -[ -f ${BL31_ELF} ] && ATF_LOAD_ADDR=`${CROSS_COMPILE}readelf -l "${BL31_ELF}" | \ -awk '/Entry point/ { print $3 }'` - -[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0xfffea000" -ATF_LOAD_ADDR_LOW=`printf 0x%x $((ATF_LOAD_ADDR & 0xffffffff))` -ATF_LOAD_ADDR_HIGH=`printf 0x%x $((ATF_LOAD_ADDR >> 32))` - -[ -z "$BL32" ] && BL32="tee.bin" -BL32_ELF="${BL32%.*}.elf" -[ -f ${BL32_ELF} ] && TEE_LOAD_ADDR=`${CROSS_COMPILE}readelf -l "${BL32_ELF}" | \ -awk '/Entry point/ { print $3 }'` - -[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0x60000000" -TEE_LOAD_ADDR_LOW=`printf 0x%x $((TEE_LOAD_ADDR & 0xffffffff))` -TEE_LOAD_ADDR_HIGH=`printf 0x%x $((TEE_LOAD_ADDR >> 32))` - -if [ -z "$BL33_LOAD_ADDR" ];then - BL33_LOAD_ADDR=`awk '/CONFIG_TEXT_BASE/ { print $3 }' include/generated/autoconf.h` -fi -BL33_LOAD_ADDR_LOW=`printf 0x%x $((BL33_LOAD_ADDR & 0xffffffff))` -BL33_LOAD_ADDR_HIGH=`printf 0x%x $((BL33_LOAD_ADDR >> 32))` - -DTB_LOAD_ADDR=`awk '/CONFIG_XILINX_OF_BOARD_DTB_ADDR/ { print $3 }' include/generated/autoconf.h` -if [ ! -z "$DTB_LOAD_ADDR" ]; then - DTB_LOAD_ADDR_LOW=`printf 0x%x $((DTB_LOAD_ADDR & 0xffffffff))` - DTB_LOAD_ADDR_HIGH=`printf 0x%x $((DTB_LOAD_ADDR >> 32))` - DTB_LOAD="load = <$DTB_LOAD_ADDR_HIGH $DTB_LOAD_ADDR_LOW>;" -else - DTB_LOAD="" -fi - -if [ -z "$*" ]; then - DT=arch/arm/dts/${DEVICE_TREE}.dtb -else - DT=$* -fi - -if [ ! -f $BL31 ]; then - echo "WARNING: BL31 file $BL31 NOT found, U-Boot will run in EL3" >&2 - BL31=/dev/null -fi - -cat << __HEADER_EOF -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) - -/dts-v1/; - -/ { - description = "Configuration for Xilinx ZynqMP SoC"; - - images { - uboot { - description = "U-Boot (64-bit)"; - data = /incbin/("$BL33"); - type = "firmware"; - os = "u-boot"; - arch = "arm64"; - compression = "none"; - load = <$BL33_LOAD_ADDR_HIGH $BL33_LOAD_ADDR_LOW>; - entry = <$BL33_LOAD_ADDR_HIGH $BL33_LOAD_ADDR_LOW>; - hash { - algo = "md5"; - }; - }; -__HEADER_EOF - -if [ -f $BL31 ]; then -cat << __ATF - atf { - description = "Trusted Firmware-A"; - data = /incbin/("$BL31"); - type = "firmware"; - os = "arm-trusted-firmware"; - arch = "arm64"; - compression = "none"; - load = <$ATF_LOAD_ADDR_HIGH $ATF_LOAD_ADDR_LOW>; - entry = <$ATF_LOAD_ADDR_HIGH $ATF_LOAD_ADDR_LOW>; - hash { - algo = "md5"; - }; - }; -__ATF -fi - -if [ -f $BL32 ]; then -cat << __TEE - tee { - description = "TEE firmware"; - data = /incbin/("$BL32"); - type = "firmware"; - os = "tee"; - arch = "arm64"; - compression = "none"; - load = <$TEE_LOAD_ADDR_HIGH $TEE_LOAD_ADDR_LOW>; - entry = <$TEE_LOAD_ADDR_HIGH $TEE_LOAD_ADDR_LOW>; - hash { - algo = "md5"; - }; - }; -__TEE -fi - -MULTI_DTB=`awk '/CONFIG_MULTI_DTB_FIT / { print $3 }' include/generated/autoconf.h` - -if [ 1"$MULTI_DTB" -eq 11 ]; then - cat << __FDT_IMAGE_EOF - fdt_1 { - description = "Multi DTB fit image"; - data = /incbin/("fit-dtb.blob"); - type = "flat_dt"; - arch = "arm64"; - compression = "none"; - $DTB_LOAD - hash { - algo = "md5"; - }; - }; - }; - configurations { - default = "config_1"; -__FDT_IMAGE_EOF - -if [ ! -f $BL31 ]; then -cat << __CONF_SECTION1_EOF - config_1 { - description = "Multi DTB without TF-A"; - firmware = "uboot"; - loadables = "fdt_1"; - }; -__CONF_SECTION1_EOF -else -if [ -f $BL32 ]; then -cat << __CONF_SECTION1_EOF - config_1 { - description = "Multi DTB with TF-A and TEE"; - firmware = "atf"; - loadables = "uboot", "tee", "fdt_1"; - }; -__CONF_SECTION1_EOF -else -cat << __CONF_SECTION1_EOF - config_1 { - description = "Multi DTB with TF-A"; - firmware = "atf"; - loadables = "uboot", "fdt_1"; - }; -__CONF_SECTION1_EOF -fi -fi - -cat << __ITS_EOF - }; -}; -__ITS_EOF - -else - -DEFAULT=1 -cnt=1 -for dtname in $DT -do - cat << __FDT_IMAGE_EOF - fdt_$cnt { - description = "$(basename $dtname .dtb)"; - data = /incbin/("$dtname"); - type = "flat_dt"; - arch = "arm64"; - compression = "none"; - $DTB_LOAD - hash { - algo = "md5"; - }; - }; -__FDT_IMAGE_EOF - -[ "x$(basename $dtname .dtb)" = "x${DEVICE_TREE}" ] && DEFAULT=$cnt - -cnt=$((cnt+1)) -done - -cat << __CONF_HEADER_EOF - }; - configurations { - default = "config_$DEFAULT"; - -__CONF_HEADER_EOF - -cnt=1 -for dtname in $DT -do -if [ ! -f $BL31 ]; then -cat << __CONF_SECTION1_EOF - config_$cnt { - description = "$(basename $dtname .dtb)"; - firmware = "uboot"; - fdt = "fdt_$cnt"; - }; -__CONF_SECTION1_EOF -else -if [ -f $BL32 ]; then -cat << __CONF_SECTION1_EOF - config_$cnt { - description = "$(basename $dtname .dtb)"; - firmware = "atf"; - loadables = "uboot", "tee"; - fdt = "fdt_$cnt"; - }; -__CONF_SECTION1_EOF -else -cat << __CONF_SECTION1_EOF - config_$cnt { - description = "$(basename $dtname .dtb)"; - firmware = "atf"; - loadables = "uboot"; - fdt = "fdt_$cnt"; - }; -__CONF_SECTION1_EOF -fi -fi - -cnt=$((cnt+1)) -done - -cat << __ITS_EOF - }; -}; -__ITS_EOF - -fi diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 6e6da8008f4..448bc532867 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -352,7 +352,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) */ flush_dcache_all(); - if (!strncmp(argv[1], "lockstep", 8)) { + if (!strcmp(argv[1], "lockstep") || !strcmp(argv[1], "0")) { if (nr != ZYNQMP_CORE_RPU0) { printf("Lockstep mode should run on ZYNQMP_CORE_RPU0\n"); return 1; @@ -369,7 +369,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) dcache_enable(); set_r5_halt_mode(nr, RELEASE, LOCK); mark_r5_used(nr, LOCK); - } else if (!strncmp(argv[1], "split", 5)) { + } else if (!strcmp(argv[1], "split") || !strcmp(argv[1], "1")) { printf("R5 split mode\n"); set_r5_reset(nr, SPLIT); set_r5_tcm_mode(SPLIT); diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 82502972eec..76c610bcee0 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -57,7 +57,7 @@ static void announce_and_cleanup(int fake) * This may be useful for last-stage operations, like cancelling * of DMA operation or releasing device internal buffers. */ - dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); + dm_remove_devices_active(); cleanup_before_linux(); } diff --git a/arch/sandbox/cpu/cache.c b/arch/sandbox/cpu/cache.c index c8a5e64214b..96b3da47e8e 100644 --- a/arch/sandbox/cpu/cache.c +++ b/arch/sandbox/cpu/cache.c @@ -4,12 +4,18 @@ */ #include <cpu_func.h> +#include <mapmem.h> #include <asm/state.h> void flush_cache(unsigned long addr, unsigned long size) { + void *ptr; + + ptr = map_sysmem(addr, size); + /* Clang uses (char *) parameters, GCC (void *) */ - __builtin___clear_cache((void *)addr, (void *)(addr + size)); + __builtin___clear_cache(map_sysmem(addr, size), ptr + size); + unmap_sysmem(ptr); } void invalidate_icache_all(void) diff --git a/arch/sandbox/dts/other.dts b/arch/sandbox/dts/other.dts index 395a7923228..515d6348b3f 100644 --- a/arch/sandbox/dts/other.dts +++ b/arch/sandbox/dts/other.dts @@ -8,13 +8,15 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> + / { compatible = "sandbox-other"; #address-cells = <1>; #size-cells = <1>; node { - target = <&target 3 4>; + other-phandle = <&target>; subnode { compatible = "sandbox-other2"; @@ -25,9 +27,34 @@ }; }; + other-a-test { + other-test-gpios = <&other_gpio_a 1>, <&other_gpio_a 4>, + <&other_gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>, + <0>, <&other_gpio_a 12>; + other-phandle-value = <&other_gpio_c 10>, <0xFFFFFFFF 20>, <&other_gpio_a 30>; + other-phandle-nodes = <&other_phandle_node_1>, <&other_phandle_node_2>; + }; + + other_gpio_a: other-gpio-a { + #gpio-cells = <1>; + }; + + other_gpio_b: other-gpio-b { + #gpio-cells = <5>; + }; + + other_gpio_c: other-gpio-c { + #gpio-cells = <2>; + }; + + other_phandle_node_1: other-phandle-node-1 { + }; + + other_phandle_node_2: other-phandle-node-2 { + }; + target: target { compatible = "sandbox-other2"; - #gpio-cells = <2>; str-prop = "other"; reg = <0x8000 0x100>; status = "disabled"; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index dee280184b1..ae52b375ccb 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -44,6 +44,7 @@ mmc5 = "/mmc5"; mmc6 = "/mmc6"; mmc7 = "/mmc7"; + mmc8 = "/mmc8"; pci0 = &pci0; pci1 = &pci1; pci2 = &pci2; @@ -101,11 +102,12 @@ bootscr-ram-offset = /bits/ 64 <0x12345678>; bootscr-flash-offset = /bits/ 64 <0>; bootscr-flash-size = /bits/ 64 <0x2000>; - boot-led = "sandbox:green"; - activity-led = "sandbox:red"; + boot-led = <&sandbox_led_green>; + activity-led = <&sandbox_led_red>; testing-bool; testing-int = <123>; testing-str = "testing"; + testing-phandle = <&phandle_node_1>; }; }; @@ -296,6 +298,12 @@ compatible = "sandbox,dsi-host"; }; + phandle_node_1: phandle-node-1 { + }; + + phandle_node_2: phandle-node-2 { + }; + a-test { reg = <0 1>; compatible = "denx,u-boot-fdt-test"; @@ -334,6 +342,7 @@ interrupts-extended = <&irq 3 0>; acpi,name = "GHIJ"; phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>; + phandle-nodes = <&phandle_node_1>, <&phandle_node_2>; mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>, <&muxcontroller0 2>, <&muxcontroller0 3>, @@ -980,12 +989,12 @@ leds { compatible = "gpio-leds"; - iracibble { + sandbox_led_red: iracibble { gpios = <&gpio_a 1 0>; label = "sandbox:red"; }; - martinet { + sandbox_led_green: martinet { gpios = <&gpio_a 2 0>; label = "sandbox:green"; }; @@ -1138,13 +1147,20 @@ filename = "mmc6.img"; }; - /* This is used for Android tests */ + /* This is used for Android boot image v4 tests */ mmc7 { status = "disabled"; compatible = "sandbox,mmc"; filename = "mmc7.img"; }; + /* This is used for Android boot image v2 tests. */ + mmc8 { + status = "disabled"; + compatible = "sandbox,mmc"; + filename = "mmc8.img"; + }; + pch { compatible = "sandbox,pch"; }; diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 55f581836df..0f79a5d5495 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -49,7 +49,7 @@ void bootm_announce_and_cleanup(void) * This may be useful for last-stage operations, like cancelling * of DMA operation or releasing device internal buffers. */ - dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); + dm_remove_devices_active(); } #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL) diff --git a/board/armltd/total_compute/MAINTAINERS b/board/armltd/total_compute/MAINTAINERS index 3dc1cd188ab..92486f4193d 100644 --- a/board/armltd/total_compute/MAINTAINERS +++ b/board/armltd/total_compute/MAINTAINERS @@ -1,5 +1,5 @@ TOTAL_COMPUTE BOARD -M: Usama Arif <usama.arif@arm.com> +M: Ben Horgan <ben.horgan@arm.com> S: Maintained F: board/armltd/total_compute/ F: include/configs/total_compute.h diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index b85fd806cba..1adee9a461f 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -281,7 +281,7 @@ int board_eth_init(struct bd_info *bis) setup_iomux_enet(); #ifdef CONFIG_FEC_MXC - bus = fec_get_miibus(base, -1); + bus = fec_get_miibus(NULL, base, -1); if (!bus) return -EINVAL; /* scan phy 4,5,6,7 */ diff --git a/board/coreboot/coreboot/sysinfo.c b/board/coreboot/coreboot/sysinfo.c index e0bdc7a5a88..d6b19530023 100644 --- a/board/coreboot/coreboot/sysinfo.c +++ b/board/coreboot/coreboot/sysinfo.c @@ -24,21 +24,21 @@ static int cb_get_str(struct udevice *dev, int id, size_t size, char *val) const char *str = NULL; switch (id) { - case SYSINFO_ID_BOARD_MODEL: + case SYSID_BOARD_MODEL: if (priv->t1) str = smbios_string(priv->system, priv->t1->product_name); break; - case SYSINFO_ID_BOARD_MANUFACTURER: + case SYSID_BOARD_MANUFACTURER: if (priv->t1) str = smbios_string(priv->system, priv->t1->manufacturer); break; - case SYSINFO_ID_PRIOR_STAGE_VERSION: + case SYSID_PRIOR_STAGE_VERSION: if (priv->t0) str = smbios_string(priv->bios, priv->t0->bios_ver); break; - case SYSINFO_ID_PRIOR_STAGE_DATE: + case SYSID_PRIOR_STAGE_DATE: if (priv->t0) str = smbios_string(priv->bios, priv->t0->bios_release_date); diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index 3443dc91885..db96534857c 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -151,8 +151,8 @@ static int coral_get_str(struct udevice *dev, int id, size_t size, char *val) return -ENOSYS; switch (id) { - case SYSINFO_ID_SMBIOS_SYSTEM_VERSION: - case SYSINFO_ID_SMBIOS_BASEBOARD_VERSION: { + case SYSID_SM_SYSTEM_VERSION: + case SYSID_SM_BASEBOARD_VERSION: { ret = get_skuconfig(dev); if (ret < 0) @@ -162,7 +162,7 @@ static int coral_get_str(struct udevice *dev, int id, size_t size, char *val) sprintf(val, "rev%d", ret); break; } - case SYSINFO_ID_BOARD_MODEL: { + case SYSID_BOARD_MODEL: { int mem_config, sku_config; const char *model; diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index f394ace786a..bc5511707ac 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -19,6 +19,14 @@ config PHYTEC_IMX8M_SOM_DETECTION Support of I2C EEPROM based SoM detection. Supported for PHYTEC i.MX8MM/i.MX8MP boards +config PHYTEC_IMX93_SOM_DETECTION + bool "Support SoM detection for i.MX93 PHYTEC platforms" + depends on ARCH_IMX9 && PHYTEC_SOM_DETECTION + default y + help + Support of I2C EEPROM based SoM detection. Supported + for PHYTEC i.MX93 based boards + config PHYTEC_AM62_SOM_DETECTION bool "Support SoM detection for AM62x PHYTEC platforms" depends on (TARGET_PHYCORE_AM62X_A53 || TARGET_PHYCORE_AM62X_R5) && \ diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index cd78f7686fe..8126f7356e1 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -10,3 +10,4 @@ endif obj-y += phytec_som_detection.o phytec_som_detection_blocks.o obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/ obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o +obj-$(CONFIG_ARCH_IMX9) += imx93_som_detection.o diff --git a/board/phytec/common/imx93_som_detection.c b/board/phytec/common/imx93_som_detection.c new file mode 100644 index 00000000000..eb9574d43b5 --- /dev/null +++ b/board/phytec/common/imx93_som_detection.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser <primoz.fiser@norik.com> + */ + +#include <asm/arch/sys_proto.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <i2c.h> +#include <u-boot/crc.h> + +#include "imx93_som_detection.h" + +extern struct phytec_eeprom_data eeprom_data; + +#if IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) + +/* Check if the SoM is actually one of the following products: + * - i.MX93 + * + * Returns 0 in case it's a known SoM. Otherwise, returns 1. + */ +u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data) +{ + u8 som; + + if (!data) + data = &eeprom_data; + + /* Early API revisions are not supported */ + if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2) + return 1; + + som = data->payload.data.data_api2.som_no; + debug("%s: som id: %u\n", __func__, som); + + if (som == PHYTEC_IMX93_SOM && is_imx93()) + return 0; + + pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__); + return 1; +} + +/* + * Filter PHYTEC i.MX93 SoM options by option index + * + * Returns: + * - option value + * - PHYTEC_EEPROM_INVAL when the data is invalid + * + */ +u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, + enum phytec_imx93_option_index idx) +{ + char *opt; + u8 opt_id; + + if (!data) + data = &eeprom_data; + + if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL; + + opt = phytec_get_opt(data); + if (opt) + opt_id = PHYTEC_GET_OPTION(opt[idx]); + else + opt_id = PHYTEC_EEPROM_INVAL; + + debug("%s: opt[%d] id: %u\n", __func__, idx, opt_id); + return opt_id; +} + +/* + * Filter PHYTEC i.MX93 SoM voltage + * + * Returns: + * - PHYTEC_IMX93_VOLTAGE_1V8 or PHYTEC_IMX93_VOLTAGE_3V3 + * - PHYTEC_EEPROM_INVAL when the data is invalid + * + */ +enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage(struct phytec_eeprom_data *data) +{ + u8 option = phytec_imx93_get_opt(data, PHYTEC_IMX93_OPT_FEAT); + + if (option == PHYTEC_EEPROM_INVAL) + return PHYTEC_IMX93_VOLTAGE_INVALID; + return (option & 0x01) ? PHYTEC_IMX93_VOLTAGE_1V8 : PHYTEC_IMX93_VOLTAGE_3V3; +} + +#else + +inline u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data) +{ + return 1; +} + +inline u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, + enum phytec_imx93_option_index idx) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage + (struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) */ diff --git a/board/phytec/common/imx93_som_detection.h b/board/phytec/common/imx93_som_detection.h new file mode 100644 index 00000000000..a0803b47cbe --- /dev/null +++ b/board/phytec/common/imx93_som_detection.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser <primoz.fiser@norik.com> + */ + +#ifndef _PHYTEC_IMX93_SOM_DETECTION_H +#define _PHYTEC_IMX93_SOM_DETECTION_H + +#include "phytec_som_detection.h" + +#define PHYTEC_IMX93_SOM 77 + +enum phytec_imx93_option_index { + PHYTEC_IMX93_OPT_DDR = 0, + PHYTEC_IMX93_OPT_EMMC = 1, + PHYTEC_IMX93_OPT_CPU = 2, + PHYTEC_IMX93_OPT_FREQ = 3, + PHYTEC_IMX93_OPT_NPU = 4, + PHYTEC_IMX93_OPT_DISP = 5, + PHYTEC_IMX93_OPT_ETH = 6, + PHYTEC_IMX93_OPT_FEAT = 7, + PHYTEC_IMX93_OPT_TEMP = 8, + PHYTEC_IMX93_OPT_BOOT = 9, + PHYTEC_IMX93_OPT_LED = 10, + PHYTEC_IMX93_OPT_EEPROM = 11, +}; + +enum phytec_imx93_voltage { + PHYTEC_IMX93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL, + PHYTEC_IMX93_VOLTAGE_3V3 = 0, + PHYTEC_IMX93_VOLTAGE_1V8 = 1, +}; + +enum phytec_imx93_ddr_eeprom_code { + PHYTEC_IMX93_DDR_INVALID = PHYTEC_EEPROM_INVAL, + PHYTEC_IMX93_LPDDR4X_512MB = 0, + PHYTEC_IMX93_LPDDR4X_1GB = 1, + PHYTEC_IMX93_LPDDR4X_2GB = 2, + PHYTEC_IMX93_LPDDR4_512MB = 3, + PHYTEC_IMX93_LPDDR4_1GB = 4, + PHYTEC_IMX93_LPDDR4_2GB = 5, +}; + +u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, + enum phytec_imx93_option_index idx); +enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage + (struct phytec_eeprom_data *data); + +#endif /* _PHYTEC_IMX93_SOM_DETECTION_H */ diff --git a/board/phytec/common/k3/Kconfig b/board/phytec/common/k3/Kconfig new file mode 100644 index 00000000000..282f4b79742 --- /dev/null +++ b/board/phytec/common/k3/Kconfig @@ -0,0 +1,5 @@ +config PHYTEC_K3_DDR_PATCH + bool "Patch DDR timings on PHYTEC K3 SoMs" + help + Allow to override default DDR timings prior to + DDRSS driver probing. diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile index 40e91a43e99..6861c70e17e 100644 --- a/board/phytec/common/k3/Makefile +++ b/board/phytec/common/k3/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y += board.o -obj-$(CONFIG_K3_DDRSS) += k3_ddrss_patch.o +obj-$(CONFIG_PHYTEC_K3_DDR_PATCH) += k3_ddrss_patch.o diff --git a/board/phytec/phycore_am62x/Kconfig b/board/phytec/phycore_am62x/Kconfig index 7c179ef0078..ecee5873c0c 100644 --- a/board/phytec/phycore_am62x/Kconfig +++ b/board/phytec/phycore_am62x/Kconfig @@ -33,6 +33,7 @@ config SPL_LDSCRIPT default "arch/arm/mach-omap2/u-boot-spl.lds" source "board/phytec/common/Kconfig" +source "board/phytec/common/k3/Kconfig" endif diff --git a/board/phytec/phycore_imx8mm/Kconfig b/board/phytec/phycore_imx8mm/Kconfig index 25e4bf2f836..06449128ba8 100644 --- a/board/phytec/phycore_imx8mm/Kconfig +++ b/board/phytec/phycore_imx8mm/Kconfig @@ -12,4 +12,5 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg" +source "board/phytec/common/Kconfig" endif diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index 8d858590a39..faff064779c 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -17,8 +17,13 @@ #include <log.h> #include <spl.h> +#include "../common/imx8m_som_detection.h" + DECLARE_GLOBAL_DATA_PTR; +#define EEPROM_ADDR 0x51 +#define EEPROM_ADDR_FALLBACK 0x59 + int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { @@ -39,6 +44,18 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) static void spl_dram_init(void) { + int ret; + + ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR, + EEPROM_ADDR_FALLBACK); + if (ret) + goto out; + + ret = phytec_imx8m_detect(NULL); + if (!ret) + phytec_print_som_info(NULL); + +out: ddr_init(&dram_timing); } diff --git a/board/phytec/phycore_imx93/Kconfig b/board/phytec/phycore_imx93/Kconfig index a70104cb798..09f26e89e33 100644 --- a/board/phytec/phycore_imx93/Kconfig +++ b/board/phytec/phycore_imx93/Kconfig @@ -10,4 +10,32 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "phycore_imx93" +config PHYCORE_IMX93_RAM_TYPE_FIX + bool "Set phyCORE-i.MX93 RAM type and size fix instead of detecting" + default false + help + RAM type and size is being automatically detected with the help + of the PHYTEC EEPROM introspection data. + Set RAM type to a fix value instead. + +choice + prompt "phyCORE-i.MX93 RAM type" + depends on PHYCORE_IMX93_RAM_TYPE_FIX + default PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB + +config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB + bool "LPDDR4X 1GB RAM" + help + Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB + for phyCORE-i.MX93. + +config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB + bool "LPDDR4X 2GB RAM" + help + Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB + for phyCORE-i.MX93. + +endchoice + +source "board/phytec/common/Kconfig" endif diff --git a/board/phytec/phycore_imx93/MAINTAINERS b/board/phytec/phycore_imx93/MAINTAINERS index 9e91a29dc31..718f89a084a 100644 --- a/board/phytec/phycore_imx93/MAINTAINERS +++ b/board/phytec/phycore_imx93/MAINTAINERS @@ -1,10 +1,13 @@ phyCORE-i.MX93 -M: Mathieu Othacehe <m.othacehe@gmail.com> +M: Mathieu Othacehe <m.othacehe@gmail.com> +R: Christoph Stoidner <c.stoidner@phytec.de> W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ S: Maintained F: arch/arm/dts/imx93-phyboard-segin.dts F: arch/arm/dts/imx93-phycore-som.dtsi F: arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi F: board/phytec/phycore_imx93/ -F: configs/imx93-phyboard-segin_defconfig +F: board/phytec/common/imx93_som_detection.c +F: board/phytec/common/imx93_som_detection.h +F: configs/imx93-phycore_defconfig F: include/configs/phycore_imx93.h diff --git a/board/phytec/phycore_imx93/lpddr4_timing.c b/board/phytec/phycore_imx93/lpddr4_timing.c index 2111972a40e..f1261f6a92a 100644 --- a/board/phytec/phycore_imx93/lpddr4_timing.c +++ b/board/phytec/phycore_imx93/lpddr4_timing.c @@ -1,24 +1,24 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2023 NXP - * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Copyright 2024 NXP + * Copyright (C) 2024 PHYTEC Messtechnik GmbH * Christoph Stoidner <c.stoidner@phytec.de> * - * Code generated with DDR Tool v1.0.0. + * Code generated with DDR Tool v3.1.0_7.4. */ #include <linux/kernel.h> #include <asm/arch/ddr.h> +/* Initialize DDRC registers */ static struct dram_cfg_param ddr_ddrc_cfg[] = { - /** Initialize DDRC registers **/ {0x4e300110, 0x44100001}, {0x4e300000, 0x8000bf}, {0x4e300008, 0x0}, {0x4e300080, 0x80000412}, {0x4e300084, 0x0}, {0x4e300114, 0x1002}, - {0x4e300260, 0x4080}, + {0x4e300260, 0x80}, {0x4e300f04, 0x80}, {0x4e300800, 0x43b30002}, {0x4e300804, 0x1f1f1f1f}, @@ -31,18 +31,17 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x4e301254, 0x0}, {0x4e301258, 0x0}, {0x4e30125c, 0x0}, - }; /* dram fsp cfg */ static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { { { - {0x4e300100, 0x24A0421B}, + {0x4e300100, 0x24A0321B}, {0x4e300104, 0xF8EE001B}, - {0x4e300108, 0x2F263233}, - {0x4e30010C, 0x0005E18B}, - {0x4e300124, 0x1C770000}, + {0x4e300108, 0x2F2E3233}, + {0x4e30010C, 0x0005C18B}, + {0x4e300124, 0x1C790000}, {0x4e300160, 0x00009102}, {0x4e30016C, 0x35F00000}, {0x4e300170, 0x8B0B0608}, @@ -50,21 +49,73 @@ static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { {0x4e300254, 0x00FE00FE}, {0x4e300258, 0x00000008}, {0x4e30025C, 0x00000400}, - {0x4e300300, 0x224F2215}, + {0x4e300300, 0x224F2213}, {0x4e300304, 0x00FE2213}, - {0x4e300308, 0x0A3C0E3C}, + {0x4e300308, 0x0A380E3D}, }, { {0x01, 0xE4}, {0x02, 0x36}, - {0x03, 0xF2}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x11}, + {0x03, 0x22}, + {0x0b, 0x44}, + {0x0c, 0x1E}, + {0x0e, 0x12}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x124F2100}, + {0x4e300104, 0xF877000E}, + {0x4e300108, 0x1816E4AA}, + {0x4e30010C, 0x005101E6}, + {0x4e300124, 0x0E3C0000}, + {0x4e300160, 0x00009101}, + {0x4e30016C, 0x30900000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000014}, + {0x4e300254, 0x007B007B}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xB4}, + {0x02, 0x1B}, + {0x03, 0x22}, + {0x0b, 0x44}, + {0x0c, 0x1E}, + {0x0e, 0x12}, {0x16, 0x04}, }, 0, }, + { + { + {0x4e300100, 0x00051000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E620A48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009100}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00240024}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x22}, + {0x0b, 0x44}, + {0x0c, 0x1E}, + {0x0e, 0x12}, + {0x16, 0x04}, + }, + 1, + }, }; @@ -90,25 +141,65 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { {0x1015f, 0x5ff}, {0x1105f, 0x5ff}, {0x1115f, 0x5ff}, + {0x11005f, 0x5ff}, + {0x11015f, 0x5ff}, + {0x11105f, 0x5ff}, + {0x11115f, 0x5ff}, + {0x21005f, 0x5ff}, + {0x21015f, 0x5ff}, + {0x21105f, 0x5ff}, + {0x21115f, 0x5ff}, {0x55, 0x1ff}, {0x1055, 0x1ff}, {0x2055, 0x1ff}, {0x200c5, 0x19}, + {0x1200c5, 0xb}, + {0x2200c5, 0x7}, {0x2002e, 0x2}, + {0x12002e, 0x2}, + {0x22002e, 0x2}, {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, {0x20024, 0x1e3}, {0x2003a, 0x2}, {0x2007d, 0x212}, {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, {0x1004d, 0x600}, {0x1014d, 0x600}, {0x1104d, 0x600}, {0x1114d, 0x600}, - {0x10049, 0xe00}, - {0x10149, 0xe00}, - {0x11049, 0xe00}, - {0x11149, 0xe00}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0x604}, + {0x10149, 0x604}, + {0x11049, 0x604}, + {0x11149, 0x604}, + {0x110049, 0x604}, + {0x110149, 0x604}, + {0x111049, 0x604}, + {0x111149, 0x604}, + {0x210049, 0x604}, + {0x210149, 0x604}, + {0x211049, 0x604}, + {0x211149, 0x604}, {0x43, 0x60}, {0x1043, 0x60}, {0x2043, 0x60}, @@ -117,14 +208,30 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { {0x20050, 0x0}, {0x2009b, 0x2}, {0x20008, 0x3a5}, + {0x120008, 0x1d3}, + {0x220008, 0x9c}, {0x20088, 0x9}, - {0x200b2, 0x10c}, + {0x200b2, 0x104}, {0x10043, 0x5a1}, {0x10143, 0x5a1}, {0x11043, 0x5a1}, {0x11143, 0x5a1}, + {0x1200b2, 0x104}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x104}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, {0x200f0, 0x600}, {0x200f1, 0x0}, {0x200f2, 0x4444}, @@ -133,42 +240,83 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { {0x200f5, 0x0}, {0x200f6, 0x0}, {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, {0x20025, 0x0}, - {0x2002d, 0x1}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, {0x2002c, 0x0}, {0x20021, 0x0}, {0x200c7, 0x21}, {0x1200c7, 0x21}, {0x200ca, 0x24}, {0x1200ca, 0x24}, - }; -/* ddr phy trained csr */ +/* PHY trained csr */ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { {0x1005f, 0x0}, {0x1015f, 0x0}, {0x1105f, 0x0}, {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, {0x55, 0x0}, {0x1055, 0x0}, {0x2055, 0x0}, {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, {0x20024, 0x0}, {0x2003a, 0x0}, {0x2007d, 0x0}, {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, {0x1004d, 0x0}, {0x1014d, 0x0}, {0x1104d, 0x0}, {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, {0x10049, 0x0}, {0x10149, 0x0}, {0x11049, 0x0}, {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, {0x43, 0x0}, {0x1043, 0x0}, {0x2043, 0x0}, @@ -177,14 +325,30 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { {0x20050, 0x0}, {0x2009b, 0x0}, {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, {0x20088, 0x0}, {0x200b2, 0x0}, {0x10043, 0x0}, {0x10143, 0x0}, {0x11043, 0x0}, {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, {0x200f0, 0x0}, {0x200f1, 0x0}, {0x200f2, 0x0}, @@ -193,8 +357,12 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { {0x200f5, 0x0}, {0x200f6, 0x0}, {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, {0x20025, 0x0}, {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, {0x2002c, 0x0}, {0xd0000, 0x0}, {0x90000, 0x0}, @@ -682,6 +850,14 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { {0x2000c, 0x0}, {0x2000d, 0x0}, {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, {0x9000c, 0x0}, {0x9000d, 0x0}, {0x9000e, 0x0}, @@ -692,12 +868,26 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { {0x90013, 0x0}, {0x20010, 0x0}, {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, {0x40080, 0x0}, {0x40081, 0x0}, {0x40082, 0x0}, {0x40083, 0x0}, {0x40084, 0x0}, {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, {0x400fd, 0x0}, {0x400f1, 0x0}, {0x10011, 0x0}, @@ -866,6 +1056,160 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { {0x90207, 0x0}, {0x90208, 0x0}, {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, {0x20077, 0x0}, {0x20072, 0x0}, {0x20073, 0x0}, @@ -888,7 +1232,6 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { {0x11640, 0x0}, {0x11740, 0x0}, {0x11840, 0x0}, - }; /* P0 message block parameter for training firmware */ @@ -896,7 +1239,7 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = { {0xd0000, 0x0}, {0x54003, 0xe94}, {0x54004, 0x4}, - {0x54006, 0x15}, + {0x54006, 0x14}, {0x54008, 0x131f}, {0x54009, 0xc8}, {0x5400b, 0x4}, @@ -904,26 +1247,102 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = { {0x5400f, 0x100}, {0x54012, 0x110}, {0x54019, 0x36e4}, - {0x5401a, 0xf2}, - {0x5401b, 0x1146}, - {0x5401c, 0x1108}, + {0x5401a, 0x22}, + {0x5401b, 0x1e44}, + {0x5401c, 0x1208}, {0x5401e, 0x4}, {0x5401f, 0x36e4}, - {0x54020, 0xf2}, - {0x54021, 0x1146}, - {0x54022, 0x1108}, + {0x54020, 0x22}, + {0x54021, 0x1e44}, + {0x54022, 0x1208}, {0x54024, 0x4}, {0x54032, 0xe400}, - {0x54033, 0xf236}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x11}, + {0x54033, 0x2236}, + {0x54034, 0x4400}, + {0x54035, 0x81e}, + {0x54036, 0x12}, {0x54037, 0x400}, {0x54038, 0xe400}, - {0x54039, 0xf236}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x11}, + {0x54039, 0x2236}, + {0x5403a, 0x4400}, + {0x5403b, 0x81e}, + {0x5403c, 0x12}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x74a}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x1bb4}, + {0x5401a, 0x22}, + {0x5401b, 0x1e44}, + {0x5401c, 0x1208}, + {0x5401e, 0x4}, + {0x5401f, 0x1bb4}, + {0x54020, 0x22}, + {0x54021, 0x1e44}, + {0x54022, 0x1208}, + {0x54024, 0x4}, + {0x54032, 0xb400}, + {0x54033, 0x221b}, + {0x54034, 0x4400}, + {0x54035, 0x81e}, + {0x54036, 0x12}, + {0x54037, 0x400}, + {0x54038, 0xb400}, + {0x54039, 0x221b}, + {0x5403a, 0x4400}, + {0x5403b, 0x81e}, + {0x5403c, 0x12}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x22}, + {0x5401b, 0x1e44}, + {0x5401c, 0x1200}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x22}, + {0x54021, 0x1e44}, + {0x54022, 0x1200}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x2209}, + {0x54034, 0x4400}, + {0x54035, 0x1e}, + {0x54036, 0x12}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x2209}, + {0x5403a, 0x4400}, + {0x5403b, 0x1e}, + {0x5403c, 0x12}, {0x5403d, 0x400}, {0xd0000, 0x1} }; @@ -933,7 +1352,7 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { {0xd0000, 0x0}, {0x54003, 0xe94}, {0x54004, 0x4}, - {0x54006, 0x15}, + {0x54006, 0x14}, {0x54008, 0x61}, {0x54009, 0xc8}, {0x5400b, 0x4}, @@ -942,26 +1361,26 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { {0x54010, 0x2080}, {0x54012, 0x110}, {0x54019, 0x36e4}, - {0x5401a, 0xf2}, - {0x5401b, 0x1146}, - {0x5401c, 0x1108}, + {0x5401a, 0x22}, + {0x5401b, 0x1e44}, + {0x5401c, 0x1208}, {0x5401e, 0x4}, {0x5401f, 0x36e4}, - {0x54020, 0xf2}, - {0x54021, 0x1146}, - {0x54022, 0x1108}, + {0x54020, 0x22}, + {0x54021, 0x1e44}, + {0x54022, 0x1208}, {0x54024, 0x4}, {0x54032, 0xe400}, - {0x54033, 0xf236}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x11}, + {0x54033, 0x2236}, + {0x54034, 0x4400}, + {0x54035, 0x81e}, + {0x54036, 0x12}, {0x54037, 0x400}, {0x54038, 0xe400}, - {0x54039, 0xf236}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x11}, + {0x54039, 0x2236}, + {0x5403a, 0x4400}, + {0x5403b, 0x81e}, + {0x5403c, 0x12}, {0x5403d, 0x400}, {0xd0000, 0x1} }; @@ -1451,10 +1870,18 @@ static struct dram_cfg_param ddr_phy_pie[] = { {0x400d7, 0x20b}, {0x2003a, 0x2}, {0x200be, 0x3}, - {0x2000b, 0x75}, + {0x2000b, 0x41a}, {0x2000c, 0xe9}, {0x2000d, 0x91c}, {0x2000e, 0x2c}, + {0x12000b, 0x20d}, + {0x12000c, 0x74}, + {0x12000d, 0x48e}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, {0x9000c, 0x0}, {0x9000d, 0x173}, {0x9000e, 0x60}, @@ -1465,12 +1892,26 @@ static struct dram_cfg_param ddr_phy_pie[] = { {0x90013, 0x6152}, {0x20010, 0x5a}, {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, {0x40080, 0xe0}, {0x40081, 0x12}, {0x40082, 0xe0}, {0x40083, 0x12}, {0x40084, 0xe0}, {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, {0x400fd, 0xf}, {0x400f1, 0xe}, {0x10011, 0x1}, @@ -1505,7 +1946,6 @@ static struct dram_cfg_param ddr_phy_pie[] = { {0x20088, 0x19}, {0xc0080, 0x0}, {0xd0000, 0x1}, - }; static struct dram_fsp_msg ddr_dram_fsp_msg[] = { @@ -1515,9 +1955,21 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, { /* P0 3733mts 2D */ .drate = 3733, @@ -1525,7 +1977,6 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg = ddr_fsp0_2d_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), }, - }; /* ddr timing config params */ @@ -1540,7 +1991,227 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3733, }, + .fsp_table = { 3733, 1866, 625, }, .fsp_cfg = ddr_dram_fsp_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), }; + +void set_dram_timings_2gb_lpddr4x(void) +{ + /* Initialize DDRC registers */ + dram_timing.ddrc_cfg[1].val = 0x8000ff; + dram_timing.ddrc_cfg[3].val = 0x80000512; + + /* dram fsp cfg */ + dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x24AB321B; + dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x2F2EE233; + dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x015B015B; + dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x015B2213; + dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20; + dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x13; + + dram_timing.fsp_cfg[1].ddrc_cfg[0].val = 0x12552100; + dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x1816B4AA; + dram_timing.fsp_cfg[1].ddrc_cfg[9].val = 0x00AA00AA; + dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20; + dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x13; + + dram_timing.fsp_cfg[2].ddrc_cfg[0].val = 0x00061000; + dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E62FA48; + dram_timing.fsp_cfg[2].ddrc_cfg[9].val = 0x00340034; + dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20; + dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x13; + + /* P0 message block parameter for training firmware */ + dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044; + dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1308; + dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044; + dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1308; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820; + dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x13; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820; + dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x13; + + /* P1 message block parameter for training firmware */ + dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044; + dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1308; + dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044; + dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1308; + dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820; + dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x13; + dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820; + dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x13; + + /* P2 message block parameter for training firmware */ + dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044; + dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1300; + dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044; + dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1300; + dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20; + dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x13; + dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20; + dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x13; + + /* P0 2D message block parameter for training firmware */ + dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044; + dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1308; + dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044; + dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1308; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820; + dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x13; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820; + dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x13; +} + +/* Generated with DDR Tool v3.3.0_7.8-d1cdb7d3 */ +void set_dram_timings_1gb_lpddr4x_900mhz(void) +{ + /* Initialize DDRC registers */ + dram_timing.ddrc_cfg[6].val = 0x4080; + + /* dram fsp cfg */ + dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x124F2100; + dram_timing.fsp_cfg[0].ddrc_cfg[1].val = 0xF877000E; + dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x181AE4AA; + dram_timing.fsp_cfg[0].ddrc_cfg[3].val = 0x005101E6; + dram_timing.fsp_cfg[0].ddrc_cfg[4].val = 0x0E3C0000; + dram_timing.fsp_cfg[0].ddrc_cfg[5].val = 0x00009101; + dram_timing.fsp_cfg[0].ddrc_cfg[6].val = 0x30900000; + dram_timing.fsp_cfg[0].ddrc_cfg[7].val = 0x8A0A0508; + dram_timing.fsp_cfg[0].ddrc_cfg[8].val = 0x00000014; + dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x007B007B; + dram_timing.fsp_cfg[0].ddrc_cfg[12].val = 0x1128110B; + dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x007B140A; + dram_timing.fsp_cfg[0].ddrc_cfg[14].val = 0x0620071E; + dram_timing.fsp_cfg[0].mr_cfg[0].val = 0xB4; + dram_timing.fsp_cfg[0].mr_cfg[1].val = 0x1B; + dram_timing.fsp_cfg[0].mr_cfg[2].val = 0xE2; + dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20; + dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x15; + + dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x181AE4AA; + dram_timing.fsp_cfg[1].mr_cfg[2].val = 0xE2; + dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20; + dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x15; + + dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E660A48; + dram_timing.fsp_cfg[2].mr_cfg[2].val = 0xE2; + dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20; + dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x15; + + /* PHY Initialize Configuration */ + dram_timing.ddrphy_cfg[31].val = 0xb; + dram_timing.ddrphy_cfg[86].val = 0x1d3; + dram_timing.ddrphy_cfg[90].val = 0x10c; + dram_timing.ddrphy_cfg[95].val = 0x10c; + dram_timing.ddrphy_cfg[100].val = 0x10c; + dram_timing.ddrphy_cfg[122].val = 0x1; + /** + * NOTE: + * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array members 119 + * (reg=0x1004a, val=0x500) and 120 (reg=0x1104a, val=0x500) are not + * present in the ddr_ddrphy_cfg array. However they were present in array + * generated with previous DDR Tool v3.1.0_7.4. We simply set both values + * to default value of 0x400 (read with dwc_ddrphy_apb_rd()) here to avoid + * any negative side-effects. + */ + dram_timing.ddrphy_cfg[119].val = 0x400; + dram_timing.ddrphy_cfg[120].val = 0x400; + + /** + * NOTE: + * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array members 101 + * (reg=0x1004a, val=0x0) and 120 (reg=0x1104a, val=0x0) are not present + * in the ddr_ddrphy_trained_csr array. However they were present in array + * generated with previous DDR Tool v3.1.0_7.4. We simply set both values + * to default 0x0 (like all other ddrphy_trained_csr values) here to avoid + * any negative side-effects. + */ + /* PHY trained csr */ + dram_timing.ddrphy_trained_csr[101].val = 0x0; + dram_timing.ddrphy_trained_csr[102].val = 0x0; + + /* P0 message block parameter for training firmware */ + dram_timing.fsp_msg[0].fsp_cfg[1].val = 0x74a; + dram_timing.fsp_msg[0].fsp_cfg[3].val = 0x15; + dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x1bb4; + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xe2; + dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044; + dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1508; + dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x1bb4; + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xe2; + dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044; + dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1508; + dram_timing.fsp_msg[0].fsp_cfg[20].val = 0xb400; + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0xe21b; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820; + dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x15; + dram_timing.fsp_msg[0].fsp_cfg[26].val = 0xb400; + dram_timing.fsp_msg[0].fsp_cfg[27].val = 0xe21b; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820; + dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x15; + + /* P1 message block parameter for training firmware */ + dram_timing.fsp_msg[1].fsp_cfg[4].val = 0x15; + dram_timing.fsp_msg[1].fsp_cfg[12].val = 0xe2; + dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044; + dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1508; + dram_timing.fsp_msg[1].fsp_cfg[17].val = 0xe2; + dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044; + dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1508; + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0xe21b; + dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820; + dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x15; + dram_timing.fsp_msg[1].fsp_cfg[28].val = 0xe21b; + dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820; + dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x15; + + /* P2 message block parameter for training firmware */ + dram_timing.fsp_msg[2].fsp_cfg[4].val = 0x15; + dram_timing.fsp_msg[2].fsp_cfg[12].val = 0xe2; + dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044; + dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1500; + dram_timing.fsp_msg[2].fsp_cfg[17].val = 0xe2; + dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044; + dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1500; + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0xe209; + dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20; + dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x15; + dram_timing.fsp_msg[2].fsp_cfg[28].val = 0xe209; + dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20; + dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x15; + + /* P0 2D message block parameter for training firmware */ + dram_timing.fsp_msg[3].fsp_cfg[1].val = 0x74a; + dram_timing.fsp_msg[3].fsp_cfg[3].val = 0x15; + dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x1bb4; + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xe2; + dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044; + dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1508; + dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x1bb4; + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xe2; + dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044; + dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1508; + dram_timing.fsp_msg[3].fsp_cfg[21].val = 0xb400; + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0xe21b; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820; + dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x15; + dram_timing.fsp_msg[3].fsp_cfg[27].val = 0xb400; + dram_timing.fsp_msg[3].fsp_cfg[28].val = 0xe21b; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820; + dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x15; + + /* DRAM PHY init engine image */ + dram_timing.ddrphy_pie[483].val = 0x20d; + dram_timing.ddrphy_pie[484].val = 0x74; + dram_timing.ddrphy_pie[485].val = 0x48e; + + /* P0 3733mts 1D */ + dram_timing.fsp_msg[0].drate = 1866; + + /* P0 1866mts 2D */ + dram_timing.fsp_msg[3].drate = 1866; + + /* ddr timing config params */ + dram_timing.fsp_table[0] = 1866; +} diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c index 085c8e195a6..a55795e0603 100644 --- a/board/phytec/phycore_imx93/phycore-imx93.c +++ b/board/phytec/phycore_imx93/phycore-imx93.c @@ -3,6 +3,7 @@ * Copyright (C) 2023 PHYTEC Messtechnik GmbH * Author: Christoph Stoidner <c.stoidner@phytec.de> * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> + * Copyright (C) 2024 PHYTEC Messtechnik GmbH */ #include <asm/arch-imx9/ccm_regs.h> @@ -12,11 +13,21 @@ #include <asm/global_data.h> #include <asm/mach-imx/boot_mode.h> #include <env.h> +#include <fdt_support.h> + +#include "../common/imx93_som_detection.h" DECLARE_GLOBAL_DATA_PTR; +#define EEPROM_ADDR 0x50 + int board_init(void) { + int ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR); + + if (ret) + printf("%s: EEPROM data init failed\n", __func__); + return 0; } @@ -40,3 +51,43 @@ int board_late_init(void) return 0; } + +static void emmc_fixup(void *blob, struct phytec_eeprom_data *data) +{ + enum phytec_imx93_voltage voltage = phytec_imx93_get_voltage(data); + int offset; + + if (voltage == PHYTEC_IMX93_VOLTAGE_INVALID) + goto err; + + if (voltage == PHYTEC_IMX93_VOLTAGE_1V8) { + offset = fdt_node_offset_by_compat_reg(blob, "fsl,imx93-usdhc", + 0x42850000); + if (offset) + fdt_delprop(blob, offset, "no-1-8-v"); + else + goto err; + } + + return; +err: + printf("Could not detect eMMC VDD-IO. Fall back to default.\n"); +} + +int board_fix_fdt(void *blob) +{ + struct phytec_eeprom_data data; + + phytec_eeprom_data_setup(&data, 2, EEPROM_ADDR); + + emmc_fixup(blob, &data); + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + emmc_fixup(blob, NULL); + + return 0; +} diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c index 17a8736c73f..a4d2aaac320 100644 --- a/board/phytec/phycore_imx93/spl.c +++ b/board/phytec/phycore_imx93/spl.c @@ -3,6 +3,7 @@ * Copyright (C) 2023 PHYTEC Messtechnik GmbH * Author: Christoph Stoidner <c.stoidner@phytec.de> * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> + * Copyright (C) 2024 PHYTEC Messtechnik GmbH */ #include <asm/arch/clock.h> @@ -20,6 +21,8 @@ #include <power/pca9450.h> #include <spl.h> +#include "../common/imx93_som_detection.h" + DECLARE_GLOBAL_DATA_PTR; /* @@ -27,6 +30,13 @@ DECLARE_GLOBAL_DATA_PTR; * when pca9451a support is added. */ #define PCA9450_REG_PWRCTRL_TOFF_DEB BIT(5) +#define EEPROM_ADDR 0x50 + +/* + * Prototypes of automatically generated ram config file + */ +void set_dram_timings_2gb_lpddr4x(void); +void set_dram_timings_1gb_lpddr4x_900mhz(void); int spl_board_boot_device(enum boot_device boot_dev_spl) { @@ -46,6 +56,44 @@ void spl_board_init(void) void spl_dram_init(void) { + int ret; + enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID; + + /* NOTE: In SPL lpi2c3 is mapped to bus 0 */ + ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR); + if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) + goto out; + + ret = phytec_imx93_detect(NULL); + if (!ret) + phytec_print_som_info(NULL); + + if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB)) + ddr_opt = PHYTEC_IMX93_LPDDR4X_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB)) + ddr_opt = PHYTEC_IMX93_LPDDR4X_2GB; + } else { + ddr_opt = phytec_imx93_get_opt(NULL, PHYTEC_IMX93_OPT_DDR); + } + + switch (ddr_opt) { + case PHYTEC_IMX93_LPDDR4X_1GB: + if (is_voltage_mode(VOLT_LOW_DRIVE)) + set_dram_timings_1gb_lpddr4x_900mhz(); + break; + case PHYTEC_IMX93_LPDDR4X_2GB: + set_dram_timings_2gb_lpddr4x(); + break; + default: + goto out; + } + ddr_init(&dram_timing); + return; +out: + puts("Could not detect correct RAM type and size. Fall back to default.\n"); + if (is_voltage_mode(VOLT_LOW_DRIVE)) + set_dram_timings_1gb_lpddr4x_900mhz(); ddr_init(&dram_timing); } diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig index c5a28ff0220..fe230971e97 100644 --- a/board/siemens/capricorn/Kconfig +++ b/board/siemens/capricorn/Kconfig @@ -1,4 +1,5 @@ -if TARGET_GIEDI +if TARGET_CAPRICORN + config SYS_BOARD default "capricorn" @@ -7,24 +8,18 @@ config SYS_VENDOR default "siemens" config SYS_CONFIG_NAME - default "giedi" + default "capricorn-common" config IMX_CONFIG default "board/siemens/capricorn/imximage.cfg" -endif -if TARGET_DENEB - -config SYS_BOARD - default "capricorn" - -config SYS_VENDOR - default "siemens" +endif -config SYS_CONFIG_NAME - default "deneb" -config IMX_CONFIG - default "board/siemens/capricorn/imximage.cfg" +config SPL_CMT + bool "Enable Siemens SPL RAM test" + depends on SPL + help + Enable SIemens SPL RAM test. -endif +source "board/siemens/common/Kconfig" diff --git a/board/siemens/capricorn/MAINTAINERS b/board/siemens/capricorn/MAINTAINERS index b4c52032cc9..5f467aa9b6e 100644 --- a/board/siemens/capricorn/MAINTAINERS +++ b/board/siemens/capricorn/MAINTAINERS @@ -1,10 +1,12 @@ CAPRICORN BOARD +M: Alexander Sverdlin <alexander.sverdlin@siemens.com> M: Anatolij Gustschin <agust@denx.de> +M: Heiko Schocher <hs@denx.de> +M: Walter Schweizer <walter.schweizer@siemens.com> S: Maintained +F: arch/arm/dts/imx8-capricorn-cxg3.dts +F: arch/arm/dts/imx8-capricorn-u-boot.dtsi +F: arch/arm/dts/imx8-capricorn.dtsi F: board/siemens/capricorn/ +F: configs/capricorn_cxg3_defconfig F: include/configs/capricorn-common.h -F: include/configs/deneb.h -F: include/configs/giedi.h -F: include/configs/siemens-env-common.h -F: configs/deneb_defconfig -F: configs/giedi_defconfig diff --git a/board/siemens/capricorn/Makefile b/board/siemens/capricorn/Makefile index e8a24c448b9..a03d54ef3b3 100644 --- a/board/siemens/capricorn/Makefile +++ b/board/siemens/capricorn/Makefile @@ -8,6 +8,8 @@ obj-y += ../common/eeprom.o ifdef CONFIG_XPL_BUILD obj-y += spl.o +obj-$(CONFIG_SPL_CMT) += spl_memory_test.o else obj-y += ../common/factoryset.o +obj-$(CONFIG_DDR_SI_TEST) += ../common/ddr_si_test.o endif diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index ad474d9baa0..390a7b0d841 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -26,6 +26,7 @@ #include <asm/arch-imx8/clock.h> #endif #include <linux/delay.h> +#include "../common/board.h" #include "../common/eeprom.h" #include "../common/factoryset.h" @@ -63,8 +64,7 @@ int board_early_init_f(void) sc_pm_clock_rate_t rate = SC_80MHZ; int ret; - ret = sc_pm_setup_uart(SC_R_UART_0, rate); - ret |= sc_pm_setup_uart(SC_R_UART_2, rate); + ret = sc_pm_setup_uart(SC_R_UART_2, rate); if (ret) return ret; @@ -73,6 +73,40 @@ int board_early_init_f(void) return 0; } +#ifndef CONFIG_XPL_BUILD +void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size) +{ + sc_faddr_t addr_start, addr_end; + sc_faddr_t sdram_1_size, sdram_2_size; + sc_err_t sc_err; + + sc_err = sc_rm_get_memreg_info(-1, 6, &addr_start, &addr_end); + if (sc_err == SC_ERR_NONE) { + if (addr_end < 0x100000000) { + /* only lower RAM available */ + sdram_1_size = (addr_end + 1) - PHYS_SDRAM_1; + sdram_2_size = 0; + } else { + /* lower RAM (2 GB) und upper RAM available */ + sdram_1_size = SZ_2G; + sdram_2_size = (addr_end + 1) - PHYS_SDRAM_2; + } + } else { + /* Get default in case it would fail */ + sdram_1_size = PHYS_SDRAM_1_SIZE; + sdram_2_size = PHYS_SDRAM_2_SIZE; + } + + *phys_sdram_1_start = PHYS_SDRAM_1; + *phys_sdram_1_size = sdram_1_size; + *phys_sdram_2_start = PHYS_SDRAM_2; + *phys_sdram_2_size = sdram_2_size; +} +#endif /* ! CONFIG_XPL_BUILD */ + #define ENET_PHY_RESET IMX_GPIO_NR(0, 3) #define ENET_TEST_1 IMX_GPIO_NR(0, 8) #define ENET_TEST_2 IMX_GPIO_NR(0, 9) @@ -271,11 +305,7 @@ int checkboard(void) { puts("Board: Capricorn\n"); - /* - * Running build_info() doesn't work with current SCFW blob. - * Uncomment below call when new blob is available. - */ - /*build_info();*/ + build_info(); print_bootinfo(); return 0; @@ -283,6 +313,32 @@ int checkboard(void) int board_init(void) { + struct chip_data eeprom_data = {}; + char module_name[16]; + int ret; + + ret = siemens_ee_setup(); + if (ret) { + printf("'siemens_ee_setup' failed, ret: %d\n", ret); + goto skip; + } + + /* Get module name from EEPROM */ + siemens_ee_read_data(SIEMENS_EE_ADDR_DDR3, module_name, + sizeof(module_name)); + printf("CPU module: %s\n", module_name); + + ret = siemens_ee_read_data(SIEMENS_EE_ADDR_CHIP, + (uchar *)&eeprom_data, + sizeof(eeprom_data)); + if (ret) { + printf("'siemens_ee_read_data' failed, ret: %d\n", ret); + goto skip; + } + + printf("HW Version: %s\n", eeprom_data.shwver); +skip: + setup_fec(); return 0; } diff --git a/board/siemens/capricorn/imximage.cfg b/board/siemens/capricorn/imximage.cfg index 4350e2967cc..7fd3fb8b72e 100644 --- a/board/siemens/capricorn/imximage.cfg +++ b/board/siemens/capricorn/imximage.cfg @@ -9,13 +9,24 @@ /* Boot from SD, sector size 0x400 */ BOOT_FROM sd + +/* skip DCD data, as firmware initializes the RAM */ +DCD_SKIP true + /* SoC type IMX8QX */ SOC_TYPE IMX8QX -/* Append seco container image */ -APPEND ahab-container.img +/* + * Append seco container image, + * use same name as in arch/arm/dts/imx8qxp-u-boot.dtsi + */ +APPEND mx8qxc0-ahab-container.img /* Create the 2nd container */ CONTAINER -/* Add scfw image with exec attribute */ -IMAGE SCU capricorn-scfw-tcm.bin -/* Add ATF image with exec attribute */ +/* + * Add scfw image with exec attribute + * use same name as in arch/arm/dts/imx8qxp-u-boot.dtsi + */ +IMAGE SCU mx8qx-mek-scfw-tcm.bin + +/* Add SPL image with exec attribute */ IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/siemens/capricorn/spl.c b/board/siemens/capricorn/spl.c index 696b5ebd340..5865cde80b4 100644 --- a/board/siemens/capricorn/spl.c +++ b/board/siemens/capricorn/spl.c @@ -15,12 +15,31 @@ #include <dm/uclass-internal.h> #include <dm/device-internal.h> +#include <firmware/imx/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <asm/gpio.h> +#include <asm/arch/sys_proto.h> +#include "spl_memory_test.h" + DECLARE_GLOBAL_DATA_PTR; +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define USDHC2_SD_PWR IMX_GPIO_NR(4, 19) +static iomux_cfg_t usdhc2_sd_pwr[] = { + SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + void spl_board_init(void) { struct udevice *dev; + uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev); + uclass_find_first_device(UCLASS_MISC, &dev); for (; dev; uclass_find_next_device(&dev)) { @@ -34,8 +53,32 @@ void spl_board_init(void) timer_init(); + imx8_iomux_setup_multiple_pads(usdhc2_sd_pwr, ARRAY_SIZE(usdhc2_sd_pwr)); + gpio_direction_output(USDHC2_SD_PWR, 0); + preloader_console_init(); + + puts("Normal Boot\n"); + +#if IS_ENABLED(CONFIG_SPL_CMT) + spl_siemens_memory_full_test(); +#endif +} + +void spl_board_prepare_for_boot(void) +{ + imx8_power_off_pd_devices(NULL, 0); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; } +#endif void board_init_f(ulong dummy) { diff --git a/board/siemens/capricorn/spl_memory_test.c b/board/siemens/capricorn/spl_memory_test.c new file mode 100644 index 00000000000..84c97e7853c --- /dev/null +++ b/board/siemens/capricorn/spl_memory_test.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright Siemens AG 2020 + * + * SPL Full Memory Test + * - memory test through the full DDR area + * - refresh over temperature torture (write all, read all) + * + * Remark: + * This test has ran properly with the definition of the RAM sizes in board + * headers. Since these headers are removed it's necessary to set the correct + * values to PHYS_SDRAM_1_SIZE & PHYS_SDRAM_2_SIZE before to recompile. + * + * An alternative is to refactor the code to get the size info from system + * controller + */ + +#include <init.h> +#include <log.h> + +/* ----- Defines ----- */ +#define CHECK_LOWER_UPPER + +#define LEVEL2_PRINT 0x0FFFFFFF + +/* use 0x7FFF0000 for shorter loop test */ +#define BASE_OFFSET 0x00000000 + +/* ----- Types ----- */ +struct ct_t { + unsigned long *start; + unsigned long *end; +}; + +/* ----- Variables ----- */ +static struct ct_t ct; +static unsigned long error_counter; + +static void print_parameters(void) +{ + printf("\nstart addr: %p\n", ct.start); + printf("end addr : %p\n", ct.end); +} + +static void run_test(void) +{ + /* moved full test in one void */ + unsigned long *address; /* 512 */ + unsigned long ebyte1; + unsigned long ebyte2; + unsigned int i; + unsigned long rpattern; + + for (i = 0; i <= 255; i++) { + memset(&ebyte1, i, sizeof(ebyte1)); + ebyte2 = ~ebyte1; + printf("LWord: %016lx #LWord: %016lx\n", ebyte1, ebyte2); + + /* write all bytes -> duration ~ 150 s */ + for (address = ct.start; address <= ct.end; address++) { +#ifdef LEVEL2_PRINT + if (((unsigned long)address & LEVEL2_PRINT) == 0) + printf("write to %p - %p\n", address, + (void *)((unsigned long)address + + LEVEL2_PRINT)); +#endif + *address = ebyte1; + address++; + *address = ebyte2; + } + + /* check all bytes */ + for (address = ct.start; address <= ct.end; address++) { +#ifdef LEVEL2_PRINT + if (((unsigned long)address & LEVEL2_PRINT) == 0) + printf("check from %p - %p\n", address, + (void *)((unsigned long)address + + LEVEL2_PRINT)); +#endif + + rpattern = *address; + if (rpattern != ebyte1) { + error_counter++; + printf("Error! Read: %016lX Wrote: %016lX Address: %p\n", + rpattern, ebyte1, address); + } + + address++; + rpattern = *address; + if (rpattern != ebyte2) { + error_counter++; + printf("Error! Read: %016lX Wrote: %016lX Address: %p\n", + rpattern, ebyte2, address); + } + } + } +} + +#ifdef CHECK_LOWER_UPPER +void test_lower_upper(void) +{ + /* + * write different values at the same address of both memory areas + * and check them + */ +#define TEST_ADDRESS 0x12345670UL +#define LOWER_ADDRESS (PHYS_SDRAM_1 + TEST_ADDRESS) +#define UPPER_ADDRESS (PHYS_SDRAM_2 + TEST_ADDRESS) +#define LOWER_VALUE 0x0011223344556677 +#define UPPER_VALUE 0x89ab89abffeeddcc + + *(unsigned long *)LOWER_ADDRESS = LOWER_VALUE; + *(unsigned long *)UPPER_ADDRESS = UPPER_VALUE; + + puts("\nlower-upper memory area test\n"); + printf("write %016lx to lower address %010lx\n", LOWER_VALUE, + LOWER_ADDRESS); + printf("write %016lx to upper address %010lx\n", UPPER_VALUE, + UPPER_ADDRESS); + printf("read %016lx from lower address %010lx\n", + *(unsigned long *)LOWER_ADDRESS, LOWER_ADDRESS); + printf("read %016lx from upper address %010lx\n", + *(unsigned long *)UPPER_ADDRESS, UPPER_ADDRESS); +} +#endif + +void spl_siemens_memory_full_test(void) +{ + unsigned long loopc = 0; + + puts("\nSPL: memory cell test\n"); + +#ifdef CHECK_LOWER_UPPER + if (PHYS_SDRAM_2_SIZE != 0) + test_lower_upper(); +#endif + + while (true) { + /* imx8x has 2 memory areas up to 2 GB */ + + /* 1st memory area @ 0x80000000 */ + ct.start = (unsigned long *)(PHYS_SDRAM_1 + BASE_OFFSET); + ct.end = (unsigned long *)(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - 1); + print_parameters(); + run_test(); + + /* 2nd memory area @ 0x880000000 */ + if (PHYS_SDRAM_2_SIZE != 0) { + ct.start = (unsigned long *)(PHYS_SDRAM_2 + BASE_OFFSET); + ct.end = (unsigned long *)(PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE - 1); + print_parameters(); + run_test(); + } + + loopc++; + printf("loop: %ld, errors: %ld\n\n", loopc, error_counter); + }; +} diff --git a/board/siemens/capricorn/spl_memory_test.h b/board/siemens/capricorn/spl_memory_test.h new file mode 100644 index 00000000000..28df284b6d5 --- /dev/null +++ b/board/siemens/capricorn/spl_memory_test.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright Siemens AG 2020 + * + */ + +void spl_siemens_memory_full_test(void); diff --git a/board/siemens/common/Kconfig b/board/siemens/common/Kconfig index 131439fcfea..4ae12b1c973 100644 --- a/board/siemens/common/Kconfig +++ b/board/siemens/common/Kconfig @@ -1,2 +1,6 @@ config FACTORYSET bool + +config DDR_SI_TEST + bool "DDR signal integrity test implementations" + default y diff --git a/board/siemens/common/board.h b/board/siemens/common/board.h new file mode 100644 index 00000000000..db34bc78711 --- /dev/null +++ b/board/siemens/common/board.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Common board functions for siemens based boards + * (C) Copyright 2022 Siemens Schweiz AG + */ + +#ifndef __COMMON_BOARD_H +#define __COMMON_BOARD_H + +/* + * Chip data + * Offset in EEPROM: 0x120 - 0x14F + * + * ----------------------------------------------------------------------------------- + * | Address range | Content | + * ----------------------------------------------------------------------------------- + * | 0x120 - 0x123 | Magic Number - 0x43484950 (4 byte) | + * ----------------------------------------------------------------------------------- + * | 0x124 - 0x133 | Device Nomenclature (15 + 1 byte) | + * ----------------------------------------------------------------------------------- + * | 0x134 - 0x13A | HW Version of the form "v00.00" (6 + 1 byte) | + * | | - First 2 digits: Layout revision (starting from 1) | + * | | - Last 2 digits: Assembly variant revision (starting from 1) | + * ----------------------------------------------------------------------------------- + * | 0x13B - 0x13F | Flash Size in Gibit (4 + 1 byte) | + * ----------------------------------------------------------------------------------- + * | 0x140 - 0x144 | Ram Size in Gibit (4 + 1 byte) | + * ----------------------------------------------------------------------------------- + * | 0x145 - 0x14F | Sequence number, equals DMC-code (10 + 1 byte) [OBSOLETE] | + * ----------------------------------------------------------------------------------- + */ + +#define MAGIC_CHIP 0x50494843 +#define EEPROM_CHIP_OFFSET 0x120 + +struct chip_data { + unsigned int magic; + char sdevname[16]; + char shwver[7]; + char flash_size[5]; + char ram_size[5]; +}; + +#endif /* __COMMON_BOARD_H */ diff --git a/board/siemens/common/ddr_si_test.c b/board/siemens/common/ddr_si_test.c new file mode 100644 index 00000000000..c1f523eb3f4 --- /dev/null +++ b/board/siemens/common/ddr_si_test.c @@ -0,0 +1,348 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright Siemens AG 2023 + * + * DDR signal integrity test + * Check signals on DDR lines + * - signals must be as fast as possible and generate long burst + * - signals must be unidirectional (to DDR or from DDR only) + * + * Set pattern: define 2^n 32-bit patterns (up to 4) + * Addresses: must be multiple of 16 to avoid checks in loops + * Test functions + * - write: write pattern to memory area for iteration times + * - read: write pattern once to memory area, read for iteration times + */ + +#include <command.h> +#include <exports.h> +#include <time.h> +#if CONFIG_IS_ENABLED(AM33XX) +#include <asm/arch-am33xx/hardware_am33xx.h> +#include <asm/arch-am33xx/cpu.h> +#include <asm/io.h> +#endif + +/* enable some print for debugging */ +#ifdef PR_DEBUG + #define PDEBUG(fmt, args...) printf(fmt, ## args) +#else + #define PDEBUG(fmt, args...) +#endif + +/* define 4 32-bit patterns */ +#define MAX_PTN_SIZE (128) +#define PTN_ARRAY_SIZE (MAX_PTN_SIZE / (8 * sizeof(u32))) + +/* define test direction */ +#define DIR_READ 0 +#define DIR_WRITE 1 + +static union { + u64 l[2]; + u32 s[4]; + } test_pattern; +static int num_ptn32; + +#if CONFIG_IS_ENABLED(AM33XX) +static inline void wdt_disable(void) +{ + struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + + writel(0xAAAA, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x5555, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; +} + +static inline void wdt_enable(void) +{ + struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + + writel(0xBBBB, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x4444, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; +} +#else /* ! */ +static inline void wdt_disable(void) {} + +static inline void wdt_enable(void) {} +#endif /* CONFIG_IS_ENABLED(AM33XX) */ + +static int do_ddr_set_ptn(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int i, n; + + if (argc < 1) + return CMD_RET_USAGE; + + /* number of patterns: 2 exponent */ + n = argc - 1; + if (n > PTN_ARRAY_SIZE || (n & (n - 1))) + return CMD_RET_USAGE; + num_ptn32 = n; + + /* get patterns */ + for (i = 0; i < n; i++) + test_pattern.s[i] = simple_strtoul(argv[i + 1], NULL, 0); + + printf("Test pattern set\n"); + + return CMD_RET_SUCCESS; +} + +static int do_ddr_show_ptn(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (!num_ptn32) { + printf("No pattern available\n"); + } else { + u32 *buf = test_pattern.s; + int len = num_ptn32; + int i; + + printf("Pattern: "); + for (i = 0 ; i < len; i++) + printf("0x%08X ", *buf++); + + printf("\n"); + } + + return CMD_RET_SUCCESS; +} + +static void ddr_read32(u64 start_addr, u64 n_word, unsigned long iter) +{ + while (iter--) { + register volatile u32 *addr = (u32 *)start_addr; + register u64 count = n_word; + + while (count) { + (void)*addr++; + PDEBUG("Read 0x%08X from 0x%p\n", val, addr - 1); + count--; + } + } +} + +static void ddr_read64(u64 start_addr, u64 n_word, unsigned long iter) +{ + while (iter--) { + register volatile u64 *addr = (u64 *)start_addr; + register u64 count = n_word; + + if (num_ptn32 == 4) + count *= 2; + + /* + * 64 & 128 bit pattern. Increase the nummber of read + * commands in the loop to generate longer burst signal + */ + while (count) { + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + /* + * underflow cannot happen since n_word = end - + * start, end & start addresses are checked to be + * multiple of 16 + */ + count -= 8; + } + } +} + +static void ddr_write32(u64 start_addr, u64 n_word, unsigned long iter) +{ + while (iter--) { + register u32 *addr = (u32 *)start_addr; + register u32 ptn = *test_pattern.s; + register u64 count = n_word; + + while (count) { + PDEBUG("Write 0x%08X to 0x%p\n", ptn, addr); + *addr++ = ptn; + count--; + } + } +} + +static void ddr_write64(u64 start_addr, u64 n_word, unsigned long iter) +{ + while (iter--) { + register u64 *addr = (u64 *)start_addr; + register u64 ptnA = test_pattern.l[0]; + register u64 ptnB = test_pattern.l[1]; + register u64 count = n_word; + + if (num_ptn32 == 2) + ptnB = ptnA; + else + count *= 2; + + /* + * 64 & 128 bit pattern. Increase the nummber of write + * commands in the loop to generate longer burst signal + */ + while (count) { + PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr); + *addr++ = ptnA; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr); + *addr++ = ptnB; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr); + *addr++ = ptnA; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr); + *addr++ = ptnB; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr); + *addr++ = ptnA; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr); + *addr++ = ptnB; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr); + *addr++ = ptnA; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr); + *addr++ = ptnB; + /* + * underflow cannot happen since n_word = end - + * start, end & start addresses are checked to be + * multiple of 16 + */ + count -= 8; + } + } +} + +static int do_ddr_si_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + u64 start_addr, end_addr, n_word; + u64 ts_start, ts_end; + unsigned long iteration, wr_iter; + int direction, i; + + if (argc < 3 || argc > 4) + return CMD_RET_USAGE; + + /* get arguments */ + direction = strcmp(argv[0], "read") ? DIR_WRITE : DIR_READ; + start_addr = simple_strtoul(argv[1], NULL, 0); + end_addr = simple_strtoul(argv[2], NULL, 0); + iteration = simple_strtoul(argv[3], NULL, 10); + + n_word = (end_addr - start_addr) / (num_ptn32 * 4); + printf("\nDDR signal integrity %s test: start\n", argv[0]); + /* checks */ + if (start_addr & 0xF) { + printf("ERROR: start_address should be 16 bytes aligned\n\n"); + return CMD_RET_USAGE; + } + + if (end_addr & 0xF) { + printf("ERROR: end_address should be 16 bytes aligned\n\n"); + return CMD_RET_USAGE; + } + + if (start_addr >= end_addr) { + printf("ERROR: end_address is not bigger than start_address\n\n"); + return CMD_RET_USAGE; + } + + if (!iteration) { + printf("ERROR: no iteration specified\n\n"); + return CMD_RET_USAGE; + } + + if (!num_ptn32) { + printf("ERROR: no test pattern specified\n\n"); + return CMD_RET_USAGE; + } + + /* print parameters */ + printf("start_address = 0x%016llX\n", start_addr); + printf("end_address = 0x%016llX\n", end_addr); + printf("iterations = %lu\n", iteration); + + /* print pattern */ + printf("test pattern 0x"); + for (i = 0; i < num_ptn32; i++) + printf("%08X", test_pattern.s[i]); + + printf("\n"); + + wdt_disable(); + + /* writing */ + printf("Writing..\n"); + ts_start = get_timer_us(0); + + if (direction == DIR_READ) + wr_iter = 1; + else + wr_iter = iteration; + + if (num_ptn32 == 1) + ddr_write32(start_addr, n_word, wr_iter); + else + ddr_write64(start_addr, n_word, wr_iter); + + ts_end = get_timer_us(0); + + /* reading */ + if (direction == DIR_READ) { + printf("Reading..\n"); + /* we need read time, just overwrite */ + ts_start = get_timer_us(0); + + if (num_ptn32 == 1) + ddr_read32(start_addr, n_word, iteration); + else + ddr_read64(start_addr, n_word, iteration); + + ts_end = get_timer_us(0); + } + + wdt_enable(); + + /* print stats */ + printf("DONE."); + printf(" Bytes=%llu ", n_word * num_ptn32 * 4 * iteration); + printf(" Time=%llu us ", ts_end - ts_start); + printf("\nDDR signal integrity %s test: end\n", argv[0]); + + return CMD_RET_SUCCESS; +} + +static char ddr_si_help_text[] = + "- DDR signal integrity test\n\n" + "ddr_si setptn <pattern> [<pattern>] : set [1,2,4] 32-bit patterns\n" + "ddr_si showptn : show patterns\n" + "ddr_si read <start> <end> <iterations> : run test for reading\n" + "ddr_si write <start> <end> <iterations> : run test for writing\n" + "\nWith\n" + "\t<pattern>: 32-bit pattern in hex format\n" + "\t<start>: test start address in hex format\n" + "\t<end>: test end address in hex format\n" + "\t<iterations>: number of iterations\n"; + +U_BOOT_CMD_WITH_SUBCMDS(ddr_si, "DDR si test", ddr_si_help_text, + U_BOOT_SUBCMD_MKENT(setptn, 5, 0, do_ddr_set_ptn), + U_BOOT_SUBCMD_MKENT(showptn, 1, 0, do_ddr_show_ptn), + U_BOOT_SUBCMD_MKENT(read, 4, 0, do_ddr_si_test), + U_BOOT_SUBCMD_MKENT(write, 4, 0, do_ddr_si_test)); diff --git a/board/siemens/draco/board.h b/board/siemens/draco/board.h index 935f340a8f2..77f35a6ab7b 100644 --- a/board/siemens/draco/board.h +++ b/board/siemens/draco/board.h @@ -11,6 +11,8 @@ #ifndef _BOARD_DRACO_H_ #define _BOARD_DRACO_H_ +#include "../common/board.h" + #define PARGS(x) #x , /* Parameter Name */ \ settings.ddr3.x, /* EEPROM Value */ \ ddr3_default.x, /* Default Value */ \ @@ -18,8 +20,6 @@ #define PRINTARGS(y) printf("%-20s, %8x, %8x, %4d\n", PARGS(y)) -#define MAGIC_CHIP 0x50494843 - /* Automatic generated definition */ /* Wed, 16 Apr 2014 16:50:41 +0200 */ /* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */ @@ -43,12 +43,6 @@ struct ddr3_data { char manu_marking[32]; /* "default \0" */ }; -struct chip_data { - unsigned int magic; - char sdevname[16]; - char shwver[7]; -}; - struct draco_baseboard_id { struct ddr3_data ddr3; struct chip_data chip; diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index e9269ef5353..b543bf8c1fb 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -385,7 +385,7 @@ static int find_ethernet_phy(void) int phy_addr = -ENOENT; #ifdef CONFIG_FEC_MXC - bus = fec_get_miibus(ENET_BASE_ADDR, -1); + bus = fec_get_miibus(NULL, ENET_BASE_ADDR, -1); if (!bus) return -ENOENT; diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index a6b45cdab81..3badeebd149 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -193,7 +193,7 @@ static int tdx_get_str(struct udevice *dev, int id, size_t size, char *val) int ret = -ENOTSUPP; switch (id) { - case SYSINFO_ID_BOARD_MODEL: + case SYSID_BOARD_MODEL: snprintf(val, size, "Toradex %04d %s %s", tdx_hw_tag.prodid, diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 0ff8440e6e0..f7152d6ee6d 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -40,6 +40,15 @@ config XILINX_PS_INIT_FILE endif +config XILINX_MINI + bool "Mini configuration" + depends on ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 + help + This option disables features which are not needed for Mini U-Boot + configurations. Mini U-Boot is running in EL3 mostly on size contrained + systems. It's purpose is to program non volatile memories or running + initial memory tests. + config XILINX_OF_BOARD_DTB_ADDR hex "Default DTB pickup address" default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 38dd80533fa..a12dccd4c51 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -19,6 +19,7 @@ #include <i2c.h> #include <linux/sizes.h> #include <malloc.h> +#include <memtop.h> #include <mtd_node.h> #include "board.h" #include <dm.h> @@ -676,3 +677,31 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } #endif + +#ifndef CONFIG_XILINX_MINI + +#ifndef MMU_SECTION_SIZE +#define MMU_SECTION_SIZE (1 * 1024 * 1024) +#endif + +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + phys_size_t size; + phys_addr_t reg; + + if (!total_size) + return gd->ram_top; + + if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8)) + panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob); + + size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE); + reg = get_mem_top(gd->ram_base, gd->ram_size, size, + (void *)gd->fdt_blob); + if (!reg) + reg = gd->ram_top - size; + + return reg + size; +} + +#endif diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 39474674cca..fd5c6ced795 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -12,12 +12,15 @@ #include <env_internal.h> #include <log.h> #include <malloc.h> +#include <memalign.h> +#include <mmc.h> #include <time.h> #include <asm/cache.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> +#include <linux/sizes.h> #include <dm/device.h> #include <dm/uclass.h> #include <versalpl.h> @@ -301,9 +304,11 @@ int dram_init(void) return 0; } +#if !CONFIG_IS_ENABLED(SYSRESET) void reset_cpu(void) { } +#endif #if defined(CONFIG_ENV_IS_NOWHERE) enum env_location env_get_location(enum env_operation op, int prio) @@ -336,3 +341,41 @@ enum env_location env_get_location(enum env_operation op, int prio) } } #endif + +#if defined(CONFIG_SET_DFU_ALT_INFO) + +#define DFU_ALT_BUF_LEN SZ_1K + +void set_dfu_alt_info(char *interface, char *devstr) +{ + int bootseq = 0, len = 0; + u32 bootmode = versal_get_bootmode(); + + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); + + if (env_get("dfu_alt_info")) + return; + + memset(buf, 0, sizeof(buf)); + + switch (bootmode) { + case EMMC_MODE: + case SD_MODE: + case SD1_LSHFT_MODE: + case SD_MODE1: + bootseq = mmc_get_env_dev(); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, "mmc %d=boot", + bootseq); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, ".bin fat %d 1", + bootseq); + break; + default: + return; + } + + env_set("dfu_alt_info", buf); + puts("DFU alt info setting: done\n"); +} +#endif diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env index 927f398c3c3..ff3a0924de7 100644 --- a/board/xilinx/zynqmp/zynqmp_kria.env +++ b/board/xilinx/zynqmp/zynqmp_kria.env @@ -77,6 +77,7 @@ tpm_kv260=if test ${card1_rev} = A -o ${card1_rev} = B -o ${card1_rev} = Y -o ${ tpm_kd240=if test ${card1_rev} = A; then run tpm_reset; fi board_setup=\ +rtc dev 0; \ zynqmp mmio_write 0xFFCA0010 0xfff 0; \ if test ${card1_name} = SCK-KV-G; then run kv260_setup; run tpm_kv260; fi;\ if test ${card1_name} = SCK-KR-G; then run kr260_setup; run tpm_reset; fi;\ diff --git a/boot/Kconfig b/boot/Kconfig index 7dd30a030e3..99dcedcc840 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -283,21 +283,6 @@ config SPL_FIT_IMAGE_POST_PROCESS injected into the FIT creation (i.e. the blobs would have been pre- processed before being added to the FIT image). -config USE_SPL_FIT_GENERATOR - bool "Use a script to generate the .its script" - depends on SPL_FIT - default y if SPL_FIT && ARCH_ZYNQMP - -config SPL_FIT_GENERATOR - string ".its file generator script for U-Boot FIT image" - depends on USE_SPL_FIT_GENERATOR - default "arch/arm/mach-zynqmp/mkimage_fit_atf.sh" if SPL_LOAD_FIT && ARCH_ZYNQMP - help - Specifies a (platform specific) script file to generate the FIT - source file used to build the U-Boot FIT image file. This gets - passed a list of supported device tree file stub names to - include in the generated image. - if VPL config VPL_FIT @@ -500,7 +485,6 @@ config BOOTMETH_ANDROID bool "Bootdev support for Android" depends on X86 || ARM || SANDBOX depends on CMDLINE - select ANDROID_AB select ANDROID_BOOT_IMAGE select CMD_BCB imply CMD_FASTBOOT diff --git a/boot/bootmeth_android.c b/boot/bootmeth_android.c index 19b1f2c377b..3a5144aaa3b 100644 --- a/boot/bootmeth_android.c +++ b/boot/bootmeth_android.c @@ -29,6 +29,7 @@ #define BCB_PART_NAME "misc" #define BOOT_PART_NAME "boot" #define VENDOR_BOOT_PART_NAME "vendor_boot" +#define SLOT_LEN 2 /** * struct android_priv - Private data @@ -42,8 +43,10 @@ */ struct android_priv { enum android_boot_mode boot_mode; - char slot[2]; + char *slot; u32 header_version; + u32 boot_img_size; + u32 vendor_boot_img_size; }; static int android_check(struct udevice *dev, struct bootflow_iter *iter) @@ -71,7 +74,11 @@ static int scan_boot_part(struct udevice *blk, struct android_priv *priv) char *buf; int ret; - sprintf(partname, BOOT_PART_NAME "_%s", priv->slot); + if (priv->slot) + sprintf(partname, BOOT_PART_NAME "_%s", priv->slot); + else + sprintf(partname, BOOT_PART_NAME); + ret = part_get_info_by_name(desc, partname, &partition); if (ret < 0) return log_msg_ret("part info", ret); @@ -93,7 +100,13 @@ static int scan_boot_part(struct udevice *blk, struct android_priv *priv) return log_msg_ret("header", -ENOENT); } + if (!android_image_get_bootimg_size(buf, &priv->boot_img_size)) { + free(buf); + return log_msg_ret("get bootimg size", -EINVAL); + } + priv->header_version = ((struct andr_boot_img_hdr_v0 *)buf)->header_version; + free(buf); return 0; @@ -108,7 +121,11 @@ static int scan_vendor_boot_part(struct udevice *blk, struct android_priv *priv) char *buf; int ret; - sprintf(partname, VENDOR_BOOT_PART_NAME "_%s", priv->slot); + if (priv->slot) + sprintf(partname, VENDOR_BOOT_PART_NAME "_%s", priv->slot); + else + sprintf(partname, VENDOR_BOOT_PART_NAME); + ret = part_get_info_by_name(desc, partname, &partition); if (ret < 0) return log_msg_ret("part info", ret); @@ -129,6 +146,12 @@ static int scan_vendor_boot_part(struct udevice *blk, struct android_priv *priv) free(buf); return log_msg_ret("header", -ENOENT); } + + if (!android_image_get_vendor_bootimg_size(buf, &priv->vendor_boot_img_size)) { + free(buf); + return log_msg_ret("get vendor bootimg size", -EINVAL); + } + free(buf); return 0; @@ -142,6 +165,11 @@ static int android_read_slot_from_bcb(struct bootflow *bflow, bool decrement) char slot_suffix[3]; int ret; + if (!CONFIG_IS_ENABLED(ANDROID_AB)) { + priv->slot = NULL; + return 0; + } + ret = part_get_info_by_name(desc, BCB_PART_NAME, &misc); if (ret < 0) return log_msg_ret("part", ret); @@ -150,6 +178,7 @@ static int android_read_slot_from_bcb(struct bootflow *bflow, bool decrement) if (ret < 0) return log_msg_ret("slot", ret); + priv->slot = malloc(SLOT_LEN); priv->slot[0] = BOOT_SLOT_NAME(ret); priv->slot[1] = '\0'; @@ -259,16 +288,12 @@ static int android_read_bootflow(struct udevice *dev, struct bootflow *bflow) goto free_priv; } - if (priv->header_version != 4) { - log_debug("only boot.img v4 is supported %u\n", priv->header_version); - ret = -EINVAL; - goto free_priv; - } - - ret = scan_vendor_boot_part(bflow->blk, priv); - if (ret < 0) { - log_debug("scan vendor_boot failed: err=%d\n", ret); - goto free_priv; + if (priv->header_version >= 3) { + ret = scan_vendor_boot_part(bflow->blk, priv); + if (ret < 0) { + log_debug("scan vendor_boot failed: err=%d\n", ret); + goto free_priv; + } } /* @@ -278,7 +303,7 @@ static int android_read_bootflow(struct udevice *dev, struct bootflow *bflow) configure_serialno(bflow); configure_bootloader_version(bflow); - if (priv->boot_mode == ANDROID_BOOT_MODE_NORMAL) { + if (priv->boot_mode == ANDROID_BOOT_MODE_NORMAL && priv->slot) { ret = bootflow_cmdline_set_arg(bflow, "androidboot.force_normal_boot", "1", false); if (ret < 0) { @@ -319,28 +344,44 @@ static int android_read_file(struct udevice *dev, struct bootflow *bflow, * @blk: Block device to read * @name: Partition name to read * @slot: Nul-terminated slot suffixed to partition name ("a\0" or "b\0") + * @image_size: Image size in bytes used when reading the partition * @addr: Address where the partition content is loaded into * Return: 0 if OK, negative errno on failure. */ static int read_slotted_partition(struct blk_desc *desc, const char *const name, - const char slot[2], ulong addr) + const char slot[2], ulong image_size, ulong addr) { struct disk_partition partition; char partname[PART_NAME_LEN]; + size_t partname_len; + ulong num_blks = DIV_ROUND_UP(image_size, desc->blksz); int ret; u32 n; - /* Ensure name fits in partname it should be: <name>_<slot>\0 */ - if (strlen(name) > (PART_NAME_LEN - 2 - 1)) + /* + * Ensure name fits in partname. + * For A/B, it should be <name>_<slot>\0 + * For non A/B, it should be <name>\0 + */ + if (CONFIG_IS_ENABLED(ANDROID_AB)) + partname_len = PART_NAME_LEN - 2 - 1; + else + partname_len = PART_NAME_LEN - 1; + + if (strlen(name) > partname_len) return log_msg_ret("name too long", -EINVAL); - sprintf(partname, "%s_%s", name, slot); + if (slot) + sprintf(partname, "%s_%s", name, slot); + else + sprintf(partname, "%s", name); + ret = part_get_info_by_name(desc, partname, &partition); if (ret < 0) return log_msg_ret("part", ret); - n = blk_dread(desc, partition.start, partition.size, map_sysmem(addr, 0)); - if (n < partition.size) + n = blk_dread(desc, partition.start, num_blks, map_sysmem(addr, 0)); + if (n < num_blks) return log_msg_ret("part read", -EIO); return 0; @@ -386,7 +427,7 @@ static int run_avb_verification(struct bootflow *bflow) AvbSlotVerifyData *out_data; enum avb_boot_state boot_state; char *extra_args; - char slot_suffix[3]; + char slot_suffix[3] = ""; bool unlocked = false; int ret; @@ -394,7 +435,8 @@ static int run_avb_verification(struct bootflow *bflow) if (!avb_ops) return log_msg_ret("avb ops", -ENOMEM); - sprintf(slot_suffix, "_%s", priv->slot); + if (priv->slot) + sprintf(slot_suffix, "_%s", priv->slot); ret = avb_ops->read_is_device_unlocked(avb_ops, &unlocked); if (ret != AVB_IO_RESULT_OK) @@ -472,16 +514,22 @@ static int boot_android_normal(struct bootflow *bflow) if (ret < 0) return log_msg_ret("read slot", ret); - ret = read_slotted_partition(desc, "boot", priv->slot, loadaddr); + ret = read_slotted_partition(desc, "boot", priv->slot, priv->boot_img_size, + loadaddr); if (ret < 0) return log_msg_ret("read boot", ret); - ret = read_slotted_partition(desc, "vendor_boot", priv->slot, vloadaddr); - if (ret < 0) - return log_msg_ret("read vendor_boot", ret); - + if (priv->header_version >= 3) { + ret = read_slotted_partition(desc, "vendor_boot", priv->slot, + priv->vendor_boot_img_size, vloadaddr); + if (ret < 0) + return log_msg_ret("read vendor_boot", ret); + set_avendor_bootimg_addr(vloadaddr); + } set_abootimg_addr(loadaddr); - set_avendor_bootimg_addr(vloadaddr); + + if (priv->slot) + free(priv->slot); ret = bootm_boot_start(loadaddr, bflow->cmdline); diff --git a/boot/bootmeth_extlinux.c b/boot/bootmeth_extlinux.c index be8fbf4df63..c6ae6dffcb7 100644 --- a/boot/bootmeth_extlinux.c +++ b/boot/bootmeth_extlinux.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_BOOTSTD +#include <asm/cache.h> #include <bootdev.h> #include <bootflow.h> #include <bootmeth.h> @@ -159,7 +160,7 @@ static int extlinux_read_bootflow(struct udevice *dev, struct bootflow *bflow) return log_msg_ret("try", ret); size = bflow->size; - ret = bootmeth_alloc_file(bflow, 0x10000, 1); + ret = bootmeth_alloc_file(bflow, 0x10000, ARCH_DMA_MINALIGN); if (ret) return log_msg_ret("read", ret); diff --git a/boot/image-android.c b/boot/image-android.c index cd01278f211..93b54bf8d79 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -178,6 +178,51 @@ static void android_boot_image_v0_v1_v2_parse_hdr(const struct andr_boot_img_hdr data->boot_img_total_size = end - (ulong)hdr; } +bool android_image_get_bootimg_size(const void *hdr, u32 *boot_img_size) +{ + struct andr_image_data data; + + if (!hdr || !boot_img_size) { + printf("hdr or boot_img_size can't be NULL\n"); + return false; + } + + if (!is_android_boot_image_header(hdr)) { + printf("Incorrect boot image header\n"); + return false; + } + + if (((struct andr_boot_img_hdr_v0 *)hdr)->header_version <= 2) + android_boot_image_v0_v1_v2_parse_hdr(hdr, &data); + else + android_boot_image_v3_v4_parse_hdr(hdr, &data); + + *boot_img_size = data.boot_img_total_size; + + return true; +} + +bool android_image_get_vendor_bootimg_size(const void *hdr, u32 *vendor_boot_img_size) +{ + struct andr_image_data data; + + if (!hdr || !vendor_boot_img_size) { + printf("hdr or vendor_boot_img_size can't be NULL\n"); + return false; + } + + if (!is_android_vendor_boot_image_header(hdr)) { + printf("Incorrect vendor boot image header\n"); + return false; + } + + android_vendor_boot_image_v3_v4_parse_hdr(hdr, &data); + + *vendor_boot_img_size = data.vendor_boot_img_total_size; + + return true; +} + bool android_image_get_data(const void *boot_hdr, const void *vendor_boot_hdr, struct andr_image_data *data) { diff --git a/boot/image-board.c b/boot/image-board.c index 1757e5816d8..b726bd6b303 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -624,9 +624,10 @@ int boot_get_fpga(struct bootm_headers *images) void *buf; int conf_noffset; int fit_img_result; - const char *uname, *name; + const char *uname, *name, *compatible; int err; int devnum = 0; /* TODO support multi fpga platforms */ + int flags = 0; if (!IS_ENABLED(CONFIG_FPGA)) return -ENOSYS; @@ -674,20 +675,29 @@ int boot_get_fpga(struct bootm_headers *images) return fit_img_result; } + conf_noffset = fit_image_get_node(buf, uname); + compatible = fdt_getprop(buf, conf_noffset, "compatible", NULL); + if (!compatible) { + printf("'fpga' image without 'compatible' property\n"); + } else { + if (CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)) + flags = fpga_compatible2flag(devnum, compatible); + } + if (!fpga_is_partial_data(devnum, img_len)) { name = "full"; err = fpga_loadbitstream(devnum, (char *)img_data, img_len, BIT_FULL); if (err) err = fpga_load(devnum, (const void *)img_data, - img_len, BIT_FULL, 0); + img_len, BIT_FULL, flags); } else { name = "partial"; err = fpga_loadbitstream(devnum, (char *)img_data, img_len, BIT_PARTIAL); if (err) err = fpga_load(devnum, (const void *)img_data, - img_len, BIT_PARTIAL, 0); + img_len, BIT_PARTIAL, flags); } if (err) diff --git a/cmd/Kconfig b/cmd/Kconfig index b2d0348fe30..4936a70f3ef 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -176,6 +176,13 @@ config CMD_CPU internal name) and clock frequency. Other information may be available depending on the CPU driver. +config CMD_UFETCH + bool "U-Boot fetch" + depends on BLK + help + Fetch utility for U-Boot (akin to neofetch). Prints information + about U-Boot and the board it is running on in a pleasing format. + config CMD_FWU_METADATA bool "fwu metadata read" depends on FWU_MULTI_BANK_UPDATE @@ -2016,7 +2023,9 @@ config CMD_PING6 config CMD_CDP bool "cdp" help - Perform CDP network configuration + The cdp command is used to announce the U-Boot device in the network + and to retrieve configuration data including the VLAN id using the + proprietary Cisco Discovery Protocol (CDP). config CMD_SNTP bool "sntp" @@ -2115,11 +2124,8 @@ config CMD_TFTPBOOT config CMD_WGET bool "wget" - depends on CMD_NET default y if SANDBOX - select PROT_TCP if NET - select PROT_TCP_LWIP if NET_LWIP - select PROT_DNS_LWIP if NET_LWIP + select WGET help wget is a simple command to download kernel, or other files, from a http server over TCP. diff --git a/cmd/Makefile b/cmd/Makefile index d1f369deec0..1e6d3128c8c 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_CMD_CPU) += cpu.o obj-$(CONFIG_CMD_DATE) += date.o obj-$(CONFIG_CMD_DEMO) += demo.o obj-$(CONFIG_CMD_DM) += dm.o +obj-$(CONFIG_CMD_UFETCH) += ufetch.o obj-$(CONFIG_CMD_SOUND) += sound.o ifdef CONFIG_POST obj-$(CONFIG_CMD_DIAG) += diag.o diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 4c0e2adabc3..ae9e1923eac 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -140,10 +140,6 @@ static int bdinfo_print_all(struct bd_info *bd) #endif bdinfo_print_num_l("boot_params", (ulong)bd->bi_boot_params); print_bi_dram(bd); - if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) { - bdinfo_print_num_l("sramstart", (ulong)bd->bi_sramstart); - bdinfo_print_num_l("sramsize", (ulong)bd->bi_sramsize); - } bdinfo_print_num_l("flashstart", (ulong)bd->bi_flashstart); bdinfo_print_num_l("flashsize", (ulong)bd->bi_flashsize); bdinfo_print_num_l("flashoffset", (ulong)bd->bi_flashoffset); diff --git a/cmd/net-lwip.c b/cmd/net-lwip.c index 6f5fc743030..0fd446ecb20 100644 --- a/cmd/net-lwip.c +++ b/cmd/net-lwip.c @@ -27,6 +27,9 @@ U_BOOT_CMD(dns, 3, 1, do_dns, "lookup the IP of a hostname", #endif #if defined(CONFIG_CMD_WGET) -U_BOOT_CMD(wget, 3, 1, do_wget, "boot image via network using HTTP protocol", - "[loadAddress] URL"); +U_BOOT_CMD(wget, 3, 1, do_wget, + "boot image via network using HTTP/HTTPS protocol", + "[loadAddress] url\n" + "wget [loadAddress] [host:]path" +); #endif diff --git a/cmd/net.c b/cmd/net.c index c90578e1b9f..79525f73a51 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -196,6 +196,8 @@ U_BOOT_CMD( #if defined(CONFIG_CMD_WGET) static int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { + wget_info = &default_wget_info; + return netboot_common(WGET, cmdtp, argc, argv); } diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 392f90f8698..1f259801293 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -523,6 +523,9 @@ static int do_env_default(struct cmd_tbl *cmdtp, int flag, case 'f': /* force */ env_flag |= H_FORCE; break; + case 'k': + env_flag |= H_NOCLEAR; + break; default: return cmd_usage(cmdtp); } @@ -1133,8 +1136,9 @@ U_BOOT_LONGHELP(env, #if defined(CONFIG_CMD_ENV_CALLBACK) "callbacks - print callbacks and their associated variables\nenv " #endif - "default [-f] -a - [forcibly] reset default environment\n" - "env default [-f] var [...] - [forcibly] reset variable(s) to their default values\n" + "default [-k] [-f] -a - [forcibly] reset default environment\n" + "env default [-k] [-f] var [...] - [forcibly] reset variable(s) to their default values\n" + " \"-k\": keep variables not defined in default environment\n" "env delete [-f] var [...] - [forcibly] delete variable(s)\n" #if defined(CONFIG_CMD_EDITENV) "env edit name - edit environment variable\n" diff --git a/cmd/ufetch.c b/cmd/ufetch.c new file mode 100644 index 00000000000..0b825d7e8c7 --- /dev/null +++ b/cmd/ufetch.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Small "fetch" utility for U-Boot */ + +#ifdef CONFIG_ARM64 +#include <asm/system.h> +#endif +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <display_options.h> +#include <mmc.h> +#include <time.h> +#include <asm/global_data.h> +#include <cli.h> +#include <command.h> +#include <dm/ofnode.h> +#include <env.h> +#include <rand.h> +#include <vsprintf.h> +#include <linux/delay.h> +#include <linux/kernel.h> +#include <version.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define LINE_WIDTH 40 +#define BLUE "\033[38;5;4m" +#define YELLOW "\033[38;5;11m" +#define BOLD "\033[1m" +#define RESET "\033[0m" +static const char * const logo_lines[] = { + BLUE BOLD " ......::...... ", + BLUE BOLD " ...::::::::::::::::::... ", + BLUE BOLD " ..::::::::::::::::::::::::::.. ", + BLUE BOLD " .::::.:::::::::::::::...::::.::::. ", + BLUE BOLD " .::::::::::::::::::::..::::::::::::::. ", + BLUE BOLD " .::.:::::::::::::::::::" YELLOW "=*%#*" BLUE "::::::::::.::. ", + BLUE BOLD " .:::::::::::::::::....." YELLOW "*%%*-" BLUE ":....::::::::::. ", + BLUE BOLD " .:.:::...:::::::::.:-" YELLOW "===##*---==-" BLUE "::::::::::.:. ", + BLUE BOLD " .::::..::::........" YELLOW "-***#****###****-" BLUE "...::::::.:. ", + BLUE BOLD " ::.:.-" YELLOW "+***+=" BLUE "::-" YELLOW "=+**#%%%%%%%%%%%%###*= " BLUE "-::...::::. ", + BLUE BOLD ".:.::-" YELLOW "*****###%%%%%%%%%%%%%%%%%%%%%%%%%%#*=" BLUE ":..:::: ", + BLUE BOLD ".::" YELLOW "##" BLUE ":" YELLOW "***#%%%%%%#####%%%%%%%####%%%%%####%%%*" BLUE "-.::. ", + BLUE BOLD ":.:" YELLOW "#%" BLUE "::" YELLOW "*%%%%%%%#*****##%%%#*****##%%##*****#%%+" BLUE ".::.", + BLUE BOLD ".::" YELLOW "**==#%%%%%%%##****#%%%%##****#%%%%#****###%%" BLUE ":.. ", + BLUE BOLD "..:" YELLOW "#%" BLUE "::" YELLOW "*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%#%%%%%+ " BLUE ".:.", + BLUE BOLD " ::" YELLOW "##" BLUE ":" YELLOW "+**#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%* " BLUE "-.:: ", + BLUE BOLD " ..::-" YELLOW "#****#%#%%%%%%%%%%%%%%%%%%%%%%%%%%#*=" BLUE "-..::. ", + BLUE BOLD " ...:=" YELLOW "*****=" BLUE "::-" YELLOW "=+**###%%%%%%%%###**+= " BLUE "--:...::: ", + BLUE BOLD " .::.::--:........::::::--::::::......::::::. ", + BLUE BOLD " .::.....::::::::::...........:::::::::.::. ", + BLUE BOLD " .::::::::::::::::::::::::::::::::::::. ", + BLUE BOLD " .::::.::::::::::::::::::::::.::::. ", + BLUE BOLD " ..::::::::::::::::::::::::::.. ", + BLUE BOLD " ...::::::::::::::::::... ", + BLUE BOLD " ......::...... ", +}; + +enum output_lines { + FIRST, + SECOND, + KERNEL, + SYSINFO, + HOST, + UPTIME, + IP, + CMDS, + CONSOLES, + FEATURES, + RELOCATION, + CORES, + MEMORY, + STORAGE, + + /* Up to 10 storage devices... Should be enough for anyone right? */ + _LAST_LINE = (STORAGE + 10), +#define LAST_LINE (_LAST_LINE - 1UL) +}; + +/* + * TODO/ideas: + * - Refactor to not use a for loop + * - Handle multiple network interfaces + * - Include stats about number of bound/probed devices + * - Show U-Boot's size and malloc usage, fdt size, etc. + */ + + +static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int num_lines = max(LAST_LINE + 1, ARRAY_SIZE(logo_lines)); + const char *model, *compatible; + char *ipaddr; + int n_cmds, n_cpus = 0, ret, compatlen; + size_t size; + ofnode np; + struct udevice *dev; + struct blk_desc *desc; + bool skip_ascii = false; + + if (argc > 1 && strcmp(argv[1], "-n") == 0) { + skip_ascii = true; + num_lines = LAST_LINE; + } + + for (int line = 0; line < num_lines; line++) { + if (!skip_ascii) { + if (line < ARRAY_SIZE(logo_lines)) + printf("%s ", logo_lines[line]); + else + printf("%*c ", LINE_WIDTH, ' '); + } + switch (line) { + case FIRST: + compatible = ofnode_read_string(ofnode_root(), "compatible"); + if (!compatible) + compatible = "unknown"; + printf(RESET "%s\n", compatible); + compatlen = strlen(compatible); + break; + case SECOND: + for (int j = 0; j < compatlen; j++) + putc('-'); + putc('\n'); + break; + case KERNEL: + printf("Kernel:" RESET " %s\n", U_BOOT_VERSION); + break; + case SYSINFO: + printf("Config:" RESET " %s_defconfig\n", CONFIG_SYS_CONFIG_NAME); + break; + case HOST: + model = ofnode_read_string(ofnode_root(), "model"); + if (model) + printf("Host:" RESET " %s\n", model); + break; + case UPTIME: + printf("Uptime:" RESET " %ld seconds\n", get_timer(0) / 1000); + break; + case IP: + ipaddr = env_get("ipaddr"); + if (!ipaddr) + ipaddr = "none"; + printf("IP Address:" RESET " %s", ipaddr); + ipaddr = env_get("ipv6addr"); + if (ipaddr) + printf(", %s\n", ipaddr); + else + putc('\n'); + break; + case CMDS: + n_cmds = ll_entry_count(struct cmd_tbl, cmd); + printf("Commands:" RESET " %d (help)\n", n_cmds); + break; + case CONSOLES: + printf("Consoles:" RESET " %s", env_get("stdout")); + if (gd->baudrate) + printf(" (%d baud)", gd->baudrate); + putc('\n'); + break; + case FEATURES: + printf("Features:" RESET " "); + if (IS_ENABLED(CONFIG_NET)) + printf("Net"); + if (IS_ENABLED(CONFIG_EFI_LOADER)) + printf(", EFI"); + if (IS_ENABLED(CONFIG_CMD_CAT)) + printf(", cat :3"); +#ifdef CONFIG_ARM64 + switch (current_el()) { + case 2: + printf(", VMs"); + break; + case 3: + printf(", full control!"); + break; + } +#endif + printf("\n"); + break; + case RELOCATION: + if (gd->flags & GD_FLG_SKIP_RELOC) + printf("Relocated:" RESET " no\n"); + else + printf("Relocated:" RESET " to %#011lx\n", gd->relocaddr); + break; + case CORES: + ofnode_for_each_subnode(np, ofnode_path("/cpus")) { + if (ofnode_name_eq(np, "cpu")) + n_cpus++; + } + printf("CPU:" RESET " %d (1 in use)\n", n_cpus); + break; + case MEMORY: + for (int j = 0; j < CONFIG_NR_DRAM_BANKS && gd->bd->bi_dram[j].size; j++) + size += gd->bd->bi_dram[j].size; + printf("Memory:" RESET " "); + print_size(size, "\n"); + break; + case STORAGE: + default: + ret = uclass_find_device_by_seq(UCLASS_BLK, line - STORAGE, &dev); + if (!ret && dev) { + desc = dev_get_uclass_plat(dev); + size = desc->lba * desc->blksz; + printf("%4s %d: " RESET, blk_get_uclass_name(desc->uclass_id), + desc->lun); + if (size) + print_size(size, ""); + else + printf("No media"); + } else if (ret == -ENODEV && (skip_ascii || line > ARRAY_SIZE(logo_lines))) { + break; + } + printf("\n"); + } + } + + printf(RESET "\n\n"); + + return 0; +} + +U_BOOT_CMD(ufetch, 2, 1, do_ufetch, + "U-Boot fetch utility", + "Print information about your device.\n" + " -n Don't print the ASCII logo" +); diff --git a/common/Makefile b/common/Makefile index 2ee5ef9cc6e..35991562a12 100644 --- a/common/Makefile +++ b/common/Makefile @@ -7,6 +7,7 @@ ifndef CONFIG_XPL_BUILD obj-y += init/ obj-y += main.o +obj-y += memtop.o obj-y += exports.o obj-y += cli_getch.o cli_simple.o cli_readline.o obj-$(CONFIG_HUSH_OLD_PARSER) += cli_hush.o diff --git a/common/board_f.c b/common/board_f.c index 98dc2591e1d..ebc934ab810 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -637,13 +637,6 @@ __weak int arch_setup_bdinfo(void) int setup_bdinfo(void) { - struct bd_info *bd = gd->bd; - - if (IS_ENABLED(CONFIG_SYS_HAS_SRAM)) { - bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ - bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ - } - return arch_setup_bdinfo(); } diff --git a/common/board_info.c b/common/board_info.c index 33c260b404e..dc26e1a33dd 100644 --- a/common/board_info.c +++ b/common/board_info.c @@ -18,9 +18,9 @@ static const struct to_show { const char *name; enum sysinfo_id id; } to_show[] = { - { "Manufacturer", SYSINFO_ID_BOARD_MANUFACTURER}, - { "Prior-stage version", SYSINFO_ID_PRIOR_STAGE_VERSION }, - { "Prior-stage date", SYSINFO_ID_PRIOR_STAGE_DATE }, + { "Manufacturer", SYSID_BOARD_MANUFACTURER}, + { "Prior-stage version", SYSID_PRIOR_STAGE_VERSION }, + { "Prior-stage date", SYSID_PRIOR_STAGE_DATE }, { /* sentinel */ } }; @@ -39,7 +39,7 @@ static int try_sysinfo(void) if (ret) return ret; - ret = sysinfo_get_str(dev, SYSINFO_ID_BOARD_MODEL, sizeof(str), str); + ret = sysinfo_get_str(dev, SYSID_BOARD_MODEL, sizeof(str), str); if (ret) return ret; printf("Model: %s\n", str); diff --git a/common/board_r.c b/common/board_r.c index 62228a723e1..ff9bce88dc9 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -287,13 +287,10 @@ static int initr_announce(void) return 0; } -static int initr_binman(void) +static int __maybe_unused initr_binman(void) { int ret; - if (!CONFIG_IS_ENABLED(BINMAN_FDT)) - return 0; - ret = binman_init(); if (ret) printf("binman_init failed:%d\n", ret); @@ -635,7 +632,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_EFI_LOADER efi_memory_init, #endif +#ifdef CONFIG_BINMAN_FDT initr_binman, +#endif #ifdef CONFIG_FSP_VERSION2 arch_fsp_init_r, #endif diff --git a/common/console.c b/common/console.c index 22224701e45..863ac6aa9dc 100644 --- a/common/console.c +++ b/common/console.c @@ -745,11 +745,7 @@ void puts(const char *s) } if (IS_ENABLED(CONFIG_DEBUG_UART) && !(gd->flags & GD_FLG_SERIAL_READY)) { - while (*s) { - int ch = *s++; - - printch(ch); - } + printascii(s); return; } diff --git a/common/memtop.c b/common/memtop.c new file mode 100644 index 00000000000..841d89e0799 --- /dev/null +++ b/common/memtop.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024, Linaro Limited + */ + +#include <fdt_support.h> +#include <fdtdec.h> +#include <memtop.h> + +#include <asm/types.h> + +#define MEM_RGN_COUNT 16 + +struct region { + phys_addr_t base; + phys_size_t size; +}; + +struct mem_region { + struct region rgn[MEM_RGN_COUNT]; + uint count; +}; + +static void add_mem_region(struct mem_region *mem_rgn, phys_addr_t base, + phys_size_t size) +{ + long i; + + for (i = mem_rgn->count; i >= 0; i--) { + if (i && base < mem_rgn->rgn[i - 1].base) { + mem_rgn->rgn[i] = mem_rgn->rgn[i - 1]; + } else { + mem_rgn->rgn[i].base = base; + mem_rgn->rgn[i].size = size; + break; + } + } + + mem_rgn->count++; +} + +static void mem_regions_init(struct mem_region *mem) +{ + uint i; + + mem->count = 0; + for (i = 0; i < MEM_RGN_COUNT; i++) { + mem->rgn[i].base = 0; + mem->rgn[i].size = 0; + } +} + +static int fdt_add_reserved_regions(struct mem_region *free_mem, + struct mem_region *reserved_mem, + void *fdt_blob) +{ + u64 addr, size; + int i, total, ret; + int nodeoffset, subnode; + struct fdt_resource res; + + if (fdt_check_header(fdt_blob) != 0) + return -1; + + /* process memreserve sections */ + total = fdt_num_mem_rsv(fdt_blob); + assert_noisy(total < MEM_RGN_COUNT); + for (i = 0; i < total; i++) { + if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0) + continue; + add_mem_region(reserved_mem, addr, size); + } + + i = 0; + /* process reserved-memory */ + nodeoffset = fdt_subnode_offset(fdt_blob, 0, "reserved-memory"); + if (nodeoffset >= 0) { + subnode = fdt_first_subnode(fdt_blob, nodeoffset); + while (subnode >= 0) { + /* check if this subnode has a reg property */ + ret = fdt_get_resource(fdt_blob, subnode, "reg", 0, + &res); + if (!ret && fdtdec_get_is_enabled(fdt_blob, subnode)) { + addr = res.start; + size = res.end - res.start + 1; + assert_noisy(i < MEM_RGN_COUNT); + add_mem_region(reserved_mem, addr, size); + } + + subnode = fdt_next_subnode(fdt_blob, subnode); + ++i; + } + } + + return 0; +} + +static long addrs_overlap(phys_addr_t base1, phys_size_t size1, + phys_addr_t base2, phys_size_t size2) +{ + const phys_addr_t base1_end = base1 + size1 - 1; + const phys_addr_t base2_end = base2 + size2 - 1; + + return ((base1 <= base2_end) && (base2 <= base1_end)); +} + +static long region_overlap_check(struct mem_region *mem_rgn, phys_addr_t base, + phys_size_t size) +{ + unsigned long i; + struct region *rgn = mem_rgn->rgn; + + for (i = 0; i < mem_rgn->count; i++) { + phys_addr_t rgnbase = rgn[i].base; + phys_size_t rgnsize = rgn[i].size; + + if (addrs_overlap(base, size, rgnbase, rgnsize)) + break; + } + + return (i < mem_rgn->count) ? i : -1; +} + +static int find_ram_top(struct mem_region *free_mem, + struct mem_region *reserved_mem, phys_size_t size) +{ + long i, rgn; + phys_addr_t base = 0; + phys_addr_t res_base; + + for (i = free_mem->count - 1; i >= 0; i--) { + phys_addr_t rgnbase = free_mem->rgn[i].base; + phys_size_t rgnsize = free_mem->rgn[i].size; + + if (rgnsize < size) + continue; + + base = rgnbase + rgnsize - size; + while (base && rgnbase <= base) { + rgn = region_overlap_check(reserved_mem, base, size); + if (rgn < 0) + return base; + + res_base = reserved_mem->rgn[rgn].base; + if (res_base < size) + break; + base = res_base - size; + } + } + + return 0; +} + +phys_addr_t get_mem_top(phys_addr_t ram_start, phys_size_t ram_size, + phys_size_t size, void *fdt) +{ + int i; + struct mem_region free_mem; + struct mem_region reserved_mem; + + mem_regions_init(&free_mem); + mem_regions_init(&reserved_mem); + + add_mem_region(&free_mem, ram_start, ram_size); + + i = fdt_add_reserved_regions(&free_mem, &reserved_mem, fdt); + if (i < 0) + return 0; + + return find_ram_top(&free_mem, &reserved_mem, size); +} diff --git a/common/usb_onboard_hub.c b/common/usb_onboard_hub.c index 68a04ac0412..6f28036e095 100644 --- a/common/usb_onboard_hub.c +++ b/common/usb_onboard_hub.c @@ -7,37 +7,203 @@ * Mostly inspired by Linux kernel v6.1 onboard_usb_hub driver */ +#include <asm/gpio.h> #include <dm.h> #include <dm/device_compat.h> +#include <i2c.h> +#include <linux/delay.h> #include <power/regulator.h> +#define USB5744_COMMAND_ATTACH 0x0056 +#define USB5744_COMMAND_ATTACH_LSB 0xAA +#define USB5744_CONFIG_REG_ACCESS 0x0037 +#define USB5744_CONFIG_REG_ACCESS_LSB 0x99 + struct onboard_hub { struct udevice *vdd; + struct gpio_desc *reset_gpio; +}; + +struct onboard_hub_data { + unsigned long reset_us; + unsigned long power_on_delay_us; + int (*init)(struct udevice *dev); }; +static int usb5744_i2c_init(struct udevice *dev) +{ + /* + * Prevent the MCU from the putting the HUB in suspend mode through register write. + * The BYPASS_UDC_SUSPEND bit (Bit 3) of the RuntimeFlags2 register at address + * 0x411D controls this aspect of the hub. + * Format to write to hub registers via SMBus- 2D 00 00 05 00 01 41 1D 08 + * Byte 0: Address of slave 2D + * Byte 1: Memory address 00 + * Byte 2: Memory address 00 + * Byte 3: Number of bytes to write to memory + * Byte 4: Write configuration register (00) + * Byte 5: Write the number of data bytes (01- 1 data byte) + * Byte 6: LSB of register address 0x41 + * Byte 7: MSB of register address 0x1D + * Byte 8: value to be written to the register + */ + u8 data_buf[8] = {0x0, 0x5, 0x0, 0x1, 0x41, 0x1D, 0x08}; + u8 config_reg_access_buf = USB5744_CONFIG_REG_ACCESS; + struct udevice *i2c_bus = NULL, *i2c_dev; + struct ofnode_phandle_args phandle; + u8 buf = USB5744_COMMAND_ATTACH; + struct dm_i2c_chip *i2c_chip; + int ret, slave_addr; + + ret = dev_read_phandle_with_args(dev, "i2c-bus", NULL, 0, 0, &phandle); + if (ret) { + dev_err(dev, "i2c-bus not specified\n"); + return ret; + } + + ret = device_get_global_by_ofnode(ofnode_get_parent(phandle.node), &i2c_bus); + if (ret) { + dev_err(dev, "Failed to get i2c node, err: %d\n", ret); + return ret; + } + + ret = ofnode_read_u32(phandle.node, "reg", &slave_addr); + if (ret) + return ret; + + ret = i2c_get_chip(i2c_bus, slave_addr, 1, &i2c_dev); + if (ret) { + dev_err(dev, "%s: can't find i2c chip device for addr 0x%x\n", __func__, + slave_addr); + return ret; + } + + i2c_chip = dev_get_parent_plat(i2c_dev); + if (!i2c_chip) { + dev_err(dev, "parent platform data not found\n"); + return -EINVAL; + } + + i2c_chip->flags &= ~DM_I2C_CHIP_WR_ADDRESS; + /* SMBus write command */ + ret = dm_i2c_write(i2c_dev, 0, (uint8_t *)&data_buf, 8); + if (ret) { + dev_err(dev, "data_buf i2c_write failed, err:%d\n", ret); + return ret; + } + + /* Configuration register access command */ + ret = dm_i2c_write(i2c_dev, USB5744_CONFIG_REG_ACCESS_LSB, + &config_reg_access_buf, 2); + if (ret) { + dev_err(dev, "config_reg_access i2c_write failed, err: %d\n", ret); + return ret; + } + + /* USB Attach with SMBus */ + ret = dm_i2c_write(i2c_dev, USB5744_COMMAND_ATTACH_LSB, &buf, 2); + if (ret) { + dev_err(dev, "usb_attach i2c_write failed, err: %d\n", ret); + return ret; + } + + return 0; +} + +int usb_onboard_hub_reset(struct udevice *dev) +{ + struct onboard_hub_data *data = + (struct onboard_hub_data *)dev_get_driver_data(dev); + struct onboard_hub *hub = dev_get_priv(dev); + int ret; + + hub->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_IS_OUT); + + /* property is optional, don't return error! */ + if (!hub->reset_gpio) + return 0; + + ret = dm_gpio_set_value(hub->reset_gpio, 1); + if (ret) + return ret; + + udelay(data->reset_us); + + ret = dm_gpio_set_value(hub->reset_gpio, 0); + if (ret) + return ret; + + udelay(data->power_on_delay_us); + + return 0; +} + static int usb_onboard_hub_probe(struct udevice *dev) { + struct onboard_hub_data *data = + (struct onboard_hub_data *)dev_get_driver_data(dev); struct onboard_hub *hub = dev_get_priv(dev); int ret; ret = device_get_supply_regulator(dev, "vdd-supply", &hub->vdd); - if (ret) { + if (ret && ret != -ENOENT) { dev_err(dev, "can't get vdd-supply: %d\n", ret); return ret; } - ret = regulator_set_enable_if_allowed(hub->vdd, true); + if (hub->vdd) { + ret = regulator_set_enable_if_allowed(hub->vdd, true); + if (ret && ret != -ENOSYS) { + dev_err(dev, "can't enable vdd-supply: %d\n", ret); + return ret; + } + } + + ret = usb_onboard_hub_reset(dev); if (ret) - dev_err(dev, "can't enable vdd-supply: %d\n", ret); + return ret; + if (data->init) { + ret = data->init(dev); + if (ret) { + dev_err(dev, "onboard i2c init failed: %d\n", ret); + goto err; + } + } + return 0; +err: + dm_gpio_set_value(hub->reset_gpio, 0); return ret; } +static int usb_onboard_hub_bind(struct udevice *dev) +{ + struct ofnode_phandle_args phandle; + const void *fdt = gd->fdt_blob; + int ret, off; + + ret = dev_read_phandle_with_args(dev, "peer-hub", NULL, 0, 0, &phandle); + if (ret) { + dev_err(dev, "peer-hub not specified\n"); + return ret; + } + + off = ofnode_to_offset(phandle.node); + ret = fdt_node_check_compatible(fdt, off, "usb424,5744"); + if (!ret) + return 0; + + return -ENODEV; +} + static int usb_onboard_hub_remove(struct udevice *dev) { struct onboard_hub *hub = dev_get_priv(dev); int ret; + if (hub->reset_gpio) + dm_gpio_free(hub->reset_gpio->dev, hub->reset_gpio); + ret = regulator_set_enable_if_allowed(hub->vdd, false); if (ret) dev_err(dev, "can't disable vdd-supply: %d\n", ret); @@ -45,15 +211,34 @@ static int usb_onboard_hub_remove(struct udevice *dev) return ret; } +static const struct onboard_hub_data usb2514_data = { + .power_on_delay_us = 500, + .reset_us = 1, +}; + +static const struct onboard_hub_data usb5744_data = { + .init = usb5744_i2c_init, + .power_on_delay_us = 1000, + .reset_us = 5, +}; + static const struct udevice_id usb_onboard_hub_ids[] = { /* Use generic usbVID,PID dt-bindings (usb-device.yaml) */ - { .compatible = "usb424,2514" }, /* USB2514B USB 2.0 */ - { } + { .compatible = "usb424,2514", /* USB2514B USB 2.0 */ + .data = (ulong)&usb2514_data, + }, { + .compatible = "usb424,2744", /* USB2744 USB 2.0 */ + .data = (ulong)&usb5744_data, + }, { + .compatible = "usb424,5744", /* USB5744 USB 3.0 */ + .data = (ulong)&usb5744_data, + } }; U_BOOT_DRIVER(usb_onboard_hub) = { .name = "usb_onboard_hub", .id = UCLASS_USB_HUB, + .bind = usb_onboard_hub_bind, .probe = usb_onboard_hub_probe, .remove = usb_onboard_hub_remove, .of_match = usb_onboard_hub_ids, diff --git a/configs/am62x_a53_android.config b/configs/am62x_a53_android.config index adbe2b8e126..2aca51e3a10 100644 --- a/configs/am62x_a53_android.config +++ b/configs/am62x_a53_android.config @@ -11,6 +11,7 @@ CONFIG_RANDOM_UUID=y # Needed for FASTBOOT_CMD_OEM_FORMAT CONFIG_FASTBOOT_CMD_OEM_FORMAT=y # Enable Android boot flow CONFIG_BOOTMETH_ANDROID=y +CONFIG_ANDROID_AB=y CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x08000000 CONFIG_AVB_VERIFY=y diff --git a/configs/am68_sk_r5_defconfig b/configs/am68_sk_r5_defconfig index f4800ef1b8a..81fa58743da 100644 --- a/configs/am68_sk_r5_defconfig +++ b/configs/am68_sk_r5_defconfig @@ -5,10 +5,11 @@ CONFIG_ARCH_K3=y CONFIG_SOC_K3_J721S2=y CONFIG_TARGET_J721S2_R5_EVM=y -CONFIG_K3_AVS0=n CONFIG_DM_REGULATOR_TPS65941=n CONFIG_PMIC_TPS65941=n +CONFIG_SPL_DM_REGULATOR_TPS6287X=y + CONFIG_DEFAULT_DEVICE_TREE="k3-am68-sk-r5-base-board" CONFIG_SPL_OF_LIST="k3-am68-sk-r5-base-board" CONFIG_OF_LIST="k3-am68-sk-r5-base-board" diff --git a/configs/amd_versal2_mini_defconfig b/configs/amd_versal2_mini_defconfig index ea22541bfba..4c902e4dde4 100644 --- a/configs/amd_versal2_mini_defconfig +++ b/configs/amd_versal2_mini_defconfig @@ -15,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" CONFIG_SYS_LOAD_ADDR=0xBBF80000 CONFIG_DEBUG_UART_BASE=0xf1920000 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_DEBUG_UART=y diff --git a/configs/amd_versal2_mini_emmc_defconfig b/configs/amd_versal2_mini_emmc_defconfig index 6d4b261606f..da3eebe3fdf 100644 --- a/configs/amd_versal2_mini_emmc_defconfig +++ b/configs/amd_versal2_mini_emmc_defconfig @@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_DEBUG_UART_BASE=0xf1920000 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_XILINX_MINI=y # CONFIG_PSCI_RESET is not set CONFIG_DEBUG_UART=y # CONFIG_EXPERT is not set diff --git a/configs/amd_versal2_mini_ospi_defconfig b/configs/amd_versal2_mini_ospi_defconfig index 71bd6677838..d881cd42bff 100644 --- a/configs/amd_versal2_mini_ospi_defconfig +++ b/configs/amd_versal2_mini_ospi_defconfig @@ -15,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" CONFIG_SYS_LOAD_ADDR=0xBBF80000 CONFIG_DEBUG_UART_BASE=0xf1920000 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_DEBUG_UART=y diff --git a/configs/amd_versal2_mini_qspi_defconfig b/configs/amd_versal2_mini_qspi_defconfig index 3947604a783..eb63f060c1b 100644 --- a/configs/amd_versal2_mini_qspi_defconfig +++ b/configs/amd_versal2_mini_qspi_defconfig @@ -15,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" CONFIG_SYS_LOAD_ADDR=0xBBF80000 CONFIG_DEBUG_UART_BASE=0xf1920000 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_DEBUG_UART=y diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 08e607700c2..b4aebf3e9fb 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -130,6 +130,8 @@ CONFIG_CADENCE_QSPI=y CONFIG_CADENCE_OSPI_VERSAL=y CONFIG_ZYNQ_SPI=y CONFIG_ZYNQMP_GQSPI=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y @@ -151,3 +153,4 @@ CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y CONFIG_TPM=y +# CONFIG_OPTEE_LIB is not set diff --git a/configs/deneb_defconfig b/configs/capricorn_cxg3_defconfig index 98841bb8771..276445528a9 100644 --- a/configs/deneb_defconfig +++ b/configs/capricorn_cxg3_defconfig @@ -10,10 +10,11 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 +CONFIG_ENV_OFFSET=0x200000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8-deneb" -CONFIG_TARGET_DENEB=y +CONFIG_DEFAULT_DEVICE_TREE="imx8-capricorn-cxg3" +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_TARGET_CAPRICORN=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y @@ -25,7 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x2000 +CONFIG_ENV_OFFSET_REDUND=0x202000 CONFIG_IDENT_STRING=" ##v01.06" CONFIG_REMAKE_ELF=y # CONFIG_EFI_LOADER is not set @@ -55,9 +56,10 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x3000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x4000 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y @@ -112,10 +114,13 @@ CONFIG_PHYLIB=y CONFIG_MV88E61XX_SWITCH=y CONFIG_MV88E61XX_CPU_PORT=5 CONFIG_MV88E61XX_PHY_PORTS=0x7 +CONFIG_DM_ETH_PHY=y CONFIG_FEC_MXC_SHARE_MDIO=y CONFIG_FEC_MXC_MDIO_BASE=0x5B050000 CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_PHY=y +CONFIG_NOP_PHY=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8=y @@ -129,5 +134,7 @@ CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y CONFIG_IMX_SCU_THERMAL=y -# CONFIG_SPL_WDT is not set +# CONFIG_WATCHDOG is not set +CONFIG_WDT=y +CONFIG_WDT_SIEMENS_PMIC=y CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig deleted file mode 100644 index af9c7a4aed6..00000000000 --- a/configs/giedi_defconfig +++ /dev/null @@ -1,133 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_IMX8=y -CONFIG_TEXT_BASE=0x80020000 -CONFIG_SYS_MALLOC_LEN=0x2800000 -CONFIG_SYS_MALLOC_F_LEN=0x4000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=3 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8-giedi" -CONFIG_TARGET_GIEDI=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK=0x13e000 -CONFIG_SPL_TEXT_BASE=0x100000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x128000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 -CONFIG_SYS_BOOTM_LEN=0x800000 -CONFIG_SYS_LOAD_ADDR=0x80280000 -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x2000 -CONFIG_IDENT_STRING=" ##v01.07" -CONFIG_REMAKE_ELF=y -# CONFIG_EFI_LOADER is not set -CONFIG_FIT=y -CONFIG_FIT_EXTERNAL_OFFSET=0x3000 -CONFIG_BOOTDELAY=3 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n" -CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" -CONFIG_AUTOBOOT_KEYED_CTRLC=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;" -CONFIG_SYS_CBSIZE=2048 -CONFIG_SYS_PBSIZE=2073 -CONFIG_LOG=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_BOARD_INIT=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set -CONFIG_SPL_LOAD_IMX_CONTAINER=y -CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg" -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x3000 -CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 -CONFIG_SPL_POWER_DOMAIN=y -CONFIG_SPL_WATCHDOG=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="U-Boot# " -CONFIG_CMD_CPU=y -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set -CONFIG_CMD_CLK=y -CONFIG_CMD_DM=y -CONFIG_CMD_FUSE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_READ=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_MMC_ENV_PART=2 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="eth1" -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_ENV=y -CONFIG_SPL_CLK=y -CONFIG_CLK_IMX8=y -CONFIG_CPU=y -CONFIG_MXC_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_IMX_LPI2C=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_MMC_IO_VOLTAGE=y -CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS400_SUPPORT=y -CONFIG_FSL_USDHC=y -CONFIG_PHYLIB=y -CONFIG_MV88E61XX_SWITCH=y -CONFIG_MV88E61XX_CPU_PORT=5 -CONFIG_MV88E61XX_PHY_PORTS=0x7 -CONFIG_FEC_MXC_SHARE_MDIO=y -CONFIG_FEC_MXC_MDIO_BASE=0x5B050000 -CONFIG_FEC_MXC=y -CONFIG_MII=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_IMX8=y -CONFIG_POWER_DOMAIN=y -CONFIG_IMX8_POWER_DOMAIN=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_DM_REGULATOR_GPIO=y -CONFIG_DM_SERIAL=y -CONFIG_FSL_LPUART=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_SCU_THERMAL=y -# CONFIG_SPL_WDT is not set -CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/imx93-phyboard-segin_defconfig b/configs/imx93-phycore_defconfig index 309262c4303..cf9800118ac 100644 --- a/configs/imx93-phyboard-segin_defconfig +++ b/configs/imx93-phycore_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x20000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_ENV_SOURCE_FILE="phycore_imx93" CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x700000 @@ -31,6 +32,7 @@ CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_REMAKE_ELF=y +# CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;" diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index f036a6fd46b..217759e5d1b 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -102,6 +102,7 @@ CONFIG_K3_SEC_PROXY=y CONFIG_FS_LOADER=y CONFIG_SPL_FS_LOADER=y CONFIG_K3_AVS0=y +# CONFIG_K3_OPP_LOW is not set CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index 3f1f66de017..61a44bf079e 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -145,3 +145,7 @@ CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_PANIC_HANG=y CONFIG_LIB_RATIONAL=y CONFIG_SPL_LIB_RATIONAL=y +CONFIG_K3_AVS0=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR_TPS6287X=y diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig index de5357c45cb..a078c5d363a 100644 --- a/configs/khadas-vim3_android_ab_defconfig +++ b/configs/khadas-vim3_android_ab_defconfig @@ -24,6 +24,12 @@ CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y +CONFIG_BOOTMETH_ANDROID=y +# CONFIG_BOOTMETH_EXTLINUX is not set +# CONFIG_BOOTMETH_EXTLINUX_PXE is not set +# CONFIG_BOOTMETH_EFILOADER is not set +# CONFIG_BOOTMETH_EFI_BOOTMGR is not set +# CONFIG_BOOTMETH_VBE is not set CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set @@ -35,7 +41,6 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y # CONFIG_CMD_IMI is not set -CONFIG_CMD_BCB=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig index a0d9c423c3c..b77a44ce859 100644 --- a/configs/khadas-vim3_android_defconfig +++ b/configs/khadas-vim3_android_defconfig @@ -24,6 +24,12 @@ CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y +CONFIG_BOOTMETH_ANDROID=y +# CONFIG_BOOTMETH_EXTLINUX is not set +# CONFIG_BOOTMETH_EXTLINUX_PXE is not set +# CONFIG_BOOTMETH_EFILOADER is not set +# CONFIG_BOOTMETH_EFI_BOOTMGR is not set +# CONFIG_BOOTMETH_VBE is not set CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set @@ -34,7 +40,6 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y # CONFIG_CMD_IMI is not set -CONFIG_CMD_BCB=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig index 4d7b90f2300..43db61056ba 100644 --- a/configs/khadas-vim3l_android_ab_defconfig +++ b/configs/khadas-vim3l_android_ab_defconfig @@ -24,6 +24,12 @@ CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y +CONFIG_BOOTMETH_ANDROID=y +# CONFIG_BOOTMETH_EXTLINUX is not set +# CONFIG_BOOTMETH_EXTLINUX_PXE is not set +# CONFIG_BOOTMETH_EFILOADER is not set +# CONFIG_BOOTMETH_EFI_BOOTMGR is not set +# CONFIG_BOOTMETH_VBE is not set CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set @@ -35,7 +41,6 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y # CONFIG_CMD_IMI is not set -CONFIG_CMD_BCB=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig index 4ec27262cdc..32d57a5b909 100644 --- a/configs/khadas-vim3l_android_defconfig +++ b/configs/khadas-vim3l_android_defconfig @@ -24,6 +24,12 @@ CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y +CONFIG_BOOTMETH_ANDROID=y +# CONFIG_BOOTMETH_EXTLINUX is not set +# CONFIG_BOOTMETH_EXTLINUX_PXE is not set +# CONFIG_BOOTMETH_EFILOADER is not set +# CONFIG_BOOTMETH_EFI_BOOTMGR is not set +# CONFIG_BOOTMETH_VBE is not set CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set @@ -34,7 +40,6 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y # CONFIG_CMD_IMI is not set -CONFIG_CMD_BCB=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index a9d595c214f..2e618d81544 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -47,7 +47,6 @@ CONFIG_CMD_SAVES=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y -CONFIG_CMD_JFFS2=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 5e59efe5649..c24580430f2 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -11,6 +11,7 @@ CONFIG_ENV_OFFSET=0x3C0000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phyboard-polis-rdk" CONFIG_TARGET_PHYCORE_IMX8MM=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y diff --git a/configs/qcm6490_defconfig b/configs/qcm6490_defconfig index 5ddc5ab3ef8..ba26924da16 100644 --- a/configs/qcm6490_defconfig +++ b/configs/qcm6490_defconfig @@ -19,3 +19,9 @@ CONFIG_TEXT_BASE=0x9fc00000 CONFIG_REMAKE_ELF=y CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs6490-rb3gen2" + +# Enable capsule updates +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_IGNORE_OSINDICATIONS=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index ea0dd3e5801..30f7b1c773f 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -21,12 +21,14 @@ CONFIG_LOG_DEFAULT_LEVEL=4 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_EEPROM=y CONFIG_SYS_I2C_EEPROM_BUS=2 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 # CONFIG_CMD_BIND is not set CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -34,6 +36,7 @@ CONFIG_CMD_UFS=y CONFIG_CMD_USB=y CONFIG_CMD_CAT=y CONFIG_CMD_BMP=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_LOG=y CONFIG_OF_LIVE=y @@ -52,6 +55,9 @@ CONFIG_CLK_QCOM_SM8250=y CONFIG_CLK_QCOM_SM8550=y CONFIG_CLK_QCOM_SM8650=y CONFIG_CLK_QCOM_SC7280=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SCSI=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x200000 CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_DM_I2C=y @@ -77,10 +83,12 @@ CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_QCOM=y CONFIG_RGMII=y CONFIG_PHY=y +CONFIG_PHY_QCOM_QMP_UFS=y CONFIG_PHY_QCOM_QUSB2=y CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y CONFIG_PHY_QCOM_SNPS_EUSB2=y CONFIG_PINCTRL=y +CONFIG_PINCONF=y CONFIG_PINCTRL_QCOM_APQ8016=y CONFIG_PINCTRL_QCOM_APQ8096=y CONFIG_PINCTRL_QCOM_QCM2290=y @@ -114,6 +122,7 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_UFS=y +CONFIG_QCOM_UFS=y CONFIG_VIDEO=y # CONFIG_VIDEO_FONT_8X16 is not set CONFIG_VIDEO_FONT_16X32=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 718e4a8283c..af56571f0d0 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -50,7 +50,9 @@ CONFIG_LOG_DEFAULT_LEVEL=6 CONFIG_LOGF_FUNC=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_STACKPROTECTOR=y +CONFIG_ANDROID_AB=y CONFIG_CMD_CPU=y +CONFIG_CMD_UFETCH=y CONFIG_CMD_LICENSE=y CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTM_PRE_LOAD=y diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 1c70d1d4b70..20f89ae6796 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -32,6 +32,7 @@ CONFIG_CMODEL_MEDANY=y CONFIG_RISCV_SMODE=y # CONFIG_OF_BOARD_FIXUP is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y CONFIG_FIT=y CONFIG_BOOTSTD_DEFAULTS=y CONFIG_BOOTSTAGE=y diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index 7388a787386..ac3815bffde 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -12,6 +12,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe0000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-mini" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_MEMTEST_START=0x00000000 diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig index a36e40dfbb3..21f241e07b1 100644 --- a/configs/xilinx_versal_mini_emmc0_defconfig +++ b/configs/xilinx_versal_mini_emmc0_defconfig @@ -12,6 +12,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc0" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y # CONFIG_PSCI_RESET is not set # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig index 3ae2115212a..6cb654c7a4b 100644 --- a/configs/xilinx_versal_mini_emmc1_defconfig +++ b/configs/xilinx_versal_mini_emmc1_defconfig @@ -12,6 +12,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc1" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y # CONFIG_PSCI_RESET is not set # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig index d0ea2b6aebd..c2a5624911a 100644 --- a/configs/xilinx_versal_mini_ospi_defconfig +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -13,6 +13,7 @@ CONFIG_ENV_SIZE=0x80 # CONFIG_DM_GPIO is not set CONFIG_DEFAULT_DEVICE_TREE="versal-mini-ospi-single" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_VERSAL_NO_DDR=y # CONFIG_PSCI_RESET is not set diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig index ef6eec075d0..4d23b353409 100644 --- a/configs/xilinx_versal_mini_qspi_defconfig +++ b/configs/xilinx_versal_mini_qspi_defconfig @@ -11,6 +11,7 @@ CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-qspi-single" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_VERSAL_NO_DDR=y # CONFIG_PSCI_RESET is not set diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig index 1640dfaff9e..e489f7018c9 100644 --- a/configs/xilinx_versal_net_mini_defconfig +++ b/configs/xilinx_versal_net_mini_defconfig @@ -14,6 +14,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF10000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini" CONFIG_SYS_LOAD_ADDR=0xBBF00000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_MEMTEST_START=0x00000000 diff --git a/configs/xilinx_versal_net_mini_emmc_defconfig b/configs/xilinx_versal_net_mini_emmc_defconfig index 4c6159a4df1..ab201566407 100644 --- a/configs/xilinx_versal_net_mini_emmc_defconfig +++ b/configs/xilinx_versal_net_mini_emmc_defconfig @@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-emmc" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y # CONFIG_PSCI_RESET is not set # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig index 071eeb8197b..f5864b5b826 100644 --- a/configs/xilinx_versal_net_mini_ospi_defconfig +++ b/configs/xilinx_versal_net_mini_ospi_defconfig @@ -13,6 +13,7 @@ CONFIG_ENV_SIZE=0x80 # CONFIG_DM_GPIO is not set CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-ospi-single" CONFIG_SYS_LOAD_ADDR=0xBBF80000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_LTO=y diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig index 227c45df28c..8453be5a590 100644 --- a/configs/xilinx_versal_net_mini_qspi_defconfig +++ b/configs/xilinx_versal_net_mini_qspi_defconfig @@ -11,6 +11,7 @@ CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-qspi-single" CONFIG_SYS_LOAD_ADDR=0xBBF80000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_LTO=y diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index a9320debdcf..30d79ab8c8c 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -133,6 +133,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_CADENCE_OSPI_VERSAL=y CONFIG_ZYNQ_SPI=y CONFIG_ZYNQMP_GQSPI=y +CONFIG_SPI_STACKED_PARALLEL=y CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index f220cc02542..c8f166c1221 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -4,6 +4,7 @@ CONFIG_POSITION_INDEPENDENT=y CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 CONFIG_ARCH_VERSAL=y CONFIG_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x100000 CONFIG_NR_DRAM_BANKS=36 CONFIG_SF_DEFAULT_SPEED=30000000 @@ -18,6 +19,10 @@ CONFIG_DEFINE_TCM_OCM_MMAP=y CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_REMAKE_ELF=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_ON_DISK_EARLY=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_EFI_HTTP_BOOT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -76,6 +81,7 @@ CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SIMPLE_PM_BUS=y CONFIG_CLK_VERSAL=y CONFIG_DFU_TIMEOUT=y +CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000 CONFIG_ARM_FFA_TRANSPORT=y @@ -99,11 +105,14 @@ CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000 CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set @@ -136,6 +145,9 @@ CONFIG_CQSPI_REF_CLK=200000000 CONFIG_CADENCE_OSPI_VERSAL=y CONFIG_ZYNQ_SPI=y CONFIG_ZYNQMP_GQSPI=y +CONFIG_SPI_STACKED_PARALLEL=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index e00b3864f90..ed3d1019485 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -146,6 +146,7 @@ CONFIG_ARM_DCC=y CONFIG_ZYNQ_SERIAL=y CONFIG_ZYNQ_SPI=y CONFIG_ZYNQ_QSPI=y +CONFIG_SPI_STACKED_PARALLEL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 5757a0c9be9..8fb66f7cb08 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -47,6 +47,7 @@ CONFIG_SYS_PBSIZE=2073 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_BINMAN_SYMBOLS is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_FS_LOAD_KERNEL_NAME="" CONFIG_SPL_FS_LOAD_ARGS_NAME="" @@ -187,7 +188,6 @@ CONFIG_DM_PWM=y CONFIG_PWM_CADENCE_TTC=y CONFIG_RESET_ZYNQMP=y CONFIG_DM_RTC=y -CONFIG_RTC_EMULATION=y CONFIG_RTC_ZYNQMP=y CONFIG_SCSI=y CONFIG_ARM_DCC=y @@ -208,6 +208,7 @@ CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y +CONFIG_USB_ONBOARD_HUB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_GADGET=y @@ -224,6 +225,8 @@ CONFIG_VIDEO_ZYNQMP_DPSUB=y CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y +# CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-som.dtb" CONFIG_PANIC_HANG=y CONFIG_TPM=y CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index 7aab69c9e46..396c876c7e6 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -9,6 +9,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe0000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 @@ -59,6 +60,8 @@ CONFIG_NO_NET=y # CONFIG_DM_MAILBOX is not set # CONFIG_MMC is not set CONFIG_ARM_DCC=y +# CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-mini.dtb" CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index c56b1e830d6..c19f79f4d1d 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_SPL=y +CONFIG_XILINX_MINI=y CONFIG_REMAKE_ELF=y # CONFIG_MP is not set # CONFIG_EFI_LOADER is not set @@ -28,6 +29,7 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_BINMAN_SYMBOLS is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y @@ -73,6 +75,8 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_ARM_DCC=y +# CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-mini.dtb" CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index a8dbf0056da..459e0294715 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x600 CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_SPL=y +CONFIG_XILINX_MINI=y CONFIG_REMAKE_ELF=y # CONFIG_MP is not set # CONFIG_EFI_LOADER is not set @@ -28,6 +29,7 @@ CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_BINMAN_SYMBOLS is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y @@ -73,6 +75,8 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_ARM_DCC=y +# CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-mini.dtb" CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index ba8f02c5b11..0a5cfd8dccb 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y CONFIG_REMAKE_ELF=y # CONFIG_MP is not set # CONFIG_EFI_LOADER is not set @@ -59,6 +60,8 @@ CONFIG_NAND_ARASAN=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SYS_NAND_MAX_CHIPS=2 CONFIG_ARM_DCC=y +# CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-mini.dtb" CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig index a8a0055f2e5..4c399fd76b9 100644 --- a/configs/xilinx_zynqmp_mini_nand_single_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig @@ -10,6 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40000 CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_XILINX_MINI=y CONFIG_REMAKE_ELF=y # CONFIG_MP is not set # CONFIG_EFI_LOADER is not set @@ -58,6 +59,8 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ARASAN=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_ARM_DCC=y +# CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-mini.dtb" CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index c08b10c6944..9d785413a8e 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_SPL=y # CONFIG_SPL_FS_FAT is not set # CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_ZYNQMP_NO_DDR=y # CONFIG_PSCI_RESET is not set @@ -31,6 +32,7 @@ CONFIG_LOGLEVEL=0 # CONFIG_BOARD_LATE_INIT is not set CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_BINMAN_SYMBOLS is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y @@ -91,6 +93,8 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_ARM_DCC=y CONFIG_SPI=y CONFIG_ZYNQMP_GQSPI=y +# CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-mini.dtb" CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index f3d83a2a475..09f487acf0d 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -41,6 +41,7 @@ CONFIG_SYS_PBSIZE=2073 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_BINMAN_SYMBOLS is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y @@ -210,6 +211,7 @@ CONFIG_SOC_XILINX_ZYNQMP=y CONFIG_SPI=y CONFIG_ZYNQ_SPI=y CONFIG_ZYNQMP_GQSPI=y +CONFIG_SPI_STACKED_PARALLEL=y CONFIG_SYSRESET=y CONFIG_SYSRESET_CMD_POWEROFF=y CONFIG_SYSRESET_PSCI=y @@ -240,6 +242,8 @@ CONFIG_BMP_32BPP=y CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y +# CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman.dtb" CONFIG_PANIC_HANG=y CONFIG_TPM=y CONFIG_SPL_GZIP=y diff --git a/disk/part_efi.c b/disk/part_efi.c index bdcfcba5d51..932d058c184 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -292,6 +292,7 @@ static int __maybe_unused part_get_info_efi(struct blk_desc *desc, int part, print_efiname(&gpt_pte[part - 1])); strcpy((char *)info->type, "U-Boot"); info->bootable = get_bootable(&gpt_pte[part - 1]); + info->type_flags = gpt_pte[part - 1].attributes.fields.type_guid_specific; if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) { uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, (char *)disk_partition_uuid(info), diff --git a/doc/README.TPL b/doc/README.TPL deleted file mode 100644 index 95b466e4af9..00000000000 --- a/doc/README.TPL +++ /dev/null @@ -1,49 +0,0 @@ -Generic TPL framework -===================== - -Overview --------- - -TPL---Third Program Loader. - -Due to the SPL on some boards(powerpc mpc85xx) has a size limit and cannot -be compatible with all the external device(e.g. DDR). So add a tertiary -program loader (TPL) to enable a loader stub loaded by the code from the -SPL. It loads the final uboot image into DDR, then jump to it to begin -execution. Now, only the powerpc mpc85xx has this requirement and will -implemente it. - -Keep consistent with SPL, with this framework almost all source files for a -board can be reused. No code duplication or symlinking is necessary anymore. - -How it works ------------- - -There has been a directory $(srctree)/spl which contains only a Makefile. The -Makefile is shared by SPL and TPL. - -The object files are built separately for SPL/TPL and placed in the -directory spl/tpl. The final binaries which are generated are -u-boot-{spl|tpl}, u-boot-{spl|tpl}.bin and u-boot-{spl|tpl}.map. - -During the TPL build a variable named CONFIG_TPL_BUILD is exported in the -make environment and also appended to CPPFLAGS with -DCONFIG_TPL_BUILD. - -The SPL options are shared by SPL and TPL, the board config file should -determine which SPL options to choose based on whether CONFIG_TPL_BUILD -is set. Source files can be compiled for TPL with options chosen in the -board config file. - -TPL use a small device tree (u-boot-tpl.dtb), containing only the nodes with -the pre-relocation properties: 'bootph-all' and 'bootph-pre-sram' -(see doc/develop/spl.rst for details). - -For example: - -spl/Makefile: -LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/libcommon.o - -CONFIG_SPL_LIBCOMMON_SUPPORT is defined in board config file: -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#endif diff --git a/doc/board/phytec/imx93-phyboard-segin.rst b/doc/board/phytec/imx93-phycore.rst index ce17fbec78d..bd110a3ebee 100644 --- a/doc/board/phytec/imx93-phyboard-segin.rst +++ b/doc/board/phytec/imx93-phycore.rst @@ -1,9 +1,9 @@ .. SPDX-License-Identifier: GPL-2.0+ -phyBOARD-Segin-i.MX93 -===================== +phyCORE-i.MX 93 +=============== -U-Boot for the phyBOARD-Segin-i.MX93. +U-Boot for the phyCORE-i.MX 93. Quick Start ----------- @@ -51,7 +51,7 @@ Build U-Boot .. code-block:: bash - $ make imx93-phyboard-segin_defconfig + $ make imx93-phycore_defconfig $ make Burn the flash.bin to MicroSD card offset 32KB: diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst index 99848a9e958..fa306974645 100644 --- a/doc/board/phytec/index.rst +++ b/doc/board/phytec/index.rst @@ -7,7 +7,7 @@ PHYTEC :maxdepth: 2 imx8mm-phygate-tauri-l - imx93-phyboard-segin + imx93-phycore phycore-am62x phycore-am64x phycore-imx8mm diff --git a/doc/build/docker.rst b/doc/build/docker.rst index 45659b3b89d..5896dd5ac4a 100644 --- a/doc/build/docker.rst +++ b/doc/build/docker.rst @@ -1,11 +1,30 @@ GitLab CI / U-Boot runner container =================================== -In order to have a reproducible and portable build environment for CI we use a container for building in. This means that developers can also reproduce the CI environment, to a large degree at least, locally. This file is located in the tools/docker directory. To build the image yourself +In order to have a reproducible and portable build environment for CI we use a container for building in. This means that developers can also reproduce the CI environment, to a large degree at least, locally. This file is located in the tools/docker directory. + +The docker image supports both amd64 and arm64. Ensure that the +'docker-buildx' Debian package is installed (or the equivalent on another +distribution). + +You will need a multi-platform container, otherwise this error is shown:: + + ERROR: Multi-platform build is not supported for the docker driver. + Switch to a different driver, or turn on the containerd image store, and try again. + +You can add one with:: + + sudo docker buildx create --name multiarch --driver docker-container --use + +Building is supported on both amd64 (i.e. 64-bit x86) and arm64 machines. While +both amd64 and arm64 happen in parallel, the non-native part will take +considerably longer as it must use QEMU to emulate the foreign code. + +To build the image yourself:: .. code-block:: bash - sudo docker build -t your-namespace:your-tag . + sudo docker buildx build --platform linux/arm64/v8,linux/amd64 -t your-namespace:your-tag . Or to use an existing container diff --git a/doc/develop/environment.rst b/doc/develop/environment.rst index e1783462bb0..e46cd39d601 100644 --- a/doc/develop/environment.rst +++ b/doc/develop/environment.rst @@ -18,8 +18,8 @@ The callbacks are named and associated with a function using the U_BOOT_ENV_CALLBACK macro in your board or driver code. These callbacks are associated with variables in one of two ways. The -static list can be added to by defining CFG_ENV_CALLBACK_LIST_STATIC -in the board configuration to a string that defines a list of +static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC +in the board defconfig via menuconfig to a string that defines a list of associations. The list must be in the following format:: entry = variable_name[:callback_name] diff --git a/doc/develop/index.rst b/doc/develop/index.rst index 30f7fdb8847..d9f2a838207 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -13,6 +13,7 @@ General codingstyle designprinciples docstyle + kconfig memory patman process diff --git a/doc/README.kconfig b/doc/develop/kconfig.rst index 808cf56e59c..227074dc497 100644 --- a/doc/README.kconfig +++ b/doc/develop/kconfig.rst @@ -1,3 +1,5 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + Kconfig in U-Boot ================= @@ -5,22 +7,20 @@ This document describes the configuration infrastructure of U-Boot. The conventional configuration was replaced by Kconfig at v2014.10-rc1 release. - Language Specification ---------------------- -Kconfig originates in Linux Kernel. -See the file "Documentation/kbuild/kconfig*.txt" in your Linux Kernel -source directory for a basic specification of Kconfig. - +The Kconfig configuration language originates in Linux kernel. +See the Linux document +`Kconfig Language <https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html>`_ +for a description of Kconfig. Difference from Linux's Kconfig ------------------------------- Here are some worth-mentioning configuration targets. -- silentoldconfig - +silentoldconfig This target updates .config, include/generated/autoconf.h and include/configs/* as in Linux. In U-Boot, it also does the following for the compatibility with the old configuration system: @@ -33,31 +33,26 @@ Here are some worth-mentioning configuration targets. * create tpl/include/autoconf.mk (TPL only) If we could completely switch to Kconfig in a long run - (i.e. remove all the include/configs/*.h), those additional processings + (i.e. remove all the include/configs/\*.h), those additional processings above would be removed. -- defconfig - +defconfig In U-Boot, "make defconfig" is a shorthand of "make sandbox_defconfig" -- <board>_defconfig - +<board>_defconfig Now it works as in Linux. - The prefixes such as "+S:" in *_defconfig are deprecated. + The prefixes such as "+S:" in \*_defconfig are deprecated. You can simply remove the prefixes. Do not add them for new boards. -- <board>_config - +<board>_config This does not exist in Linux's Kconfig. "make <board>_config" works the same as "make <board>_defconfig". Prior to Kconfig, in U-Boot, "make <board>_config" was used for the configuration. It is still supported for backward compatibility, so we do not need to update the distro recipes. - The other configuration targets work as in Linux Kernel. - Migration steps to Kconfig -------------------------- @@ -84,68 +79,79 @@ Configuration file for use in makefiles When adding a new CONFIG macro, it is highly recommended to add it to Kconfig rather than to a header file. - Conversion from boards.cfg to Kconfig ------------------------------------- Prior to Kconfig, boards.cfg was a primary database that contained Arch, CPU, -SoC, etc. of all the supported boards. It was deleted when switching to -Kconfig. Each field of boards.cfg was converted as follows: - - Status -> "S:" entry of MAINTAINERS - Arch -> CONFIG_SYS_ARCH defined by Kconfig - CPU -> CONFIG_SYS_CPU defined by Kconfig - SoC -> CONFIG_SYS_SOC defined by Kconfig - Vendor -> CONFIG_SYS_VENDOR defined by Kconfig - Board -> CONFIG_SYS_BOARD defined by Kconfig - Target -> File name of defconfig (configs/<target>_defconfig) - Maintainers -> "M:" entry of MAINTAINERS - +SoC, etc. of all the supported boards. It was deleted when switching to +Kconfig. Each field of boards.cfg was converted as follows: + +=========== ==================================================== +From To +=========== ==================================================== +Arch CONFIG_SYS_ARCH defined by Kconfig +Board CONFIG_SYS_BOARD defined by Kconfig +CPU CONFIG_SYS_CPU defined by Kconfig +Maintainers "M:" entry of MAINTAINERS +SoC CONFIG_SYS_SOC defined by Kconfig +Status "S:" entry of MAINTAINERS +Target File name of defconfig (configs/<target>\_defconfig) +Vendor CONFIG_SYS_VENDOR defined by Kconfig +=========== ==================================================== Tips to add/remove boards ------------------------- When adding a new board, the following steps are generally needed: - [1] Add a header file include/configs/<target>.h - [2] Make sure to define necessary CONFIG_SYS_* in Kconfig: - Define CONFIG_SYS_CPU="cpu" to compile arch/<arch>/cpu/<cpu> - Define CONFIG_SYS_SOC="soc" to compile arch/<arch>/cpu/<cpu>/<soc> - Define CONFIG_SYS_VENDOR="vendor" to compile board/<vendor>/common/* - and board/<vendor>/<board>/* - Define CONFIG_SYS_BOARD="board" to compile board/<board>/* - (or board/<vendor>/<board>/* if CONFIG_SYS_VENDOR is defined) - Define CONFIG_SYS_CONFIG_NAME="target" to include - include/configs/<target>.h - [3] Add a new entry to the board select menu in Kconfig. - The board select menu is located in arch/<arch>/Kconfig or - arch/<arch>/*/Kconfig. - [4] Add a MAINTAINERS file - It is generally placed at board/<board>/MAINTAINERS or - board/<vendor>/<board>/MAINTAINERS - [5] Add configs/<target>_defconfig +1. Add a header file include/configs/<target>.h + +2. Make sure to define necessary CONFIG_SYS_* in Kconfig: + + * Define CONFIG_SYS_CPU="cpu" to compile arch/<arch>/cpu/<cpu> + * Define CONFIG_SYS_SOC="soc" to compile arch/<arch>/cpu/<cpu>/<soc> + * Define CONFIG_SYS_VENDOR="vendor" to compile board/<vendor>/common/\* + and board/<vendor>/<board>/\* + * Define CONFIG_SYS_BOARD="board" to compile board/<board>/\* + (or board/<vendor>/<board>/* if CONFIG_SYS_VENDOR is defined) + Define CONFIG_SYS_CONFIG_NAME="target" to include + include/configs/<target>.h + +3. Add a new entry to the board select menu in Kconfig. + The board select menu is located in arch/<arch>/Kconfig or + arch/<arch>/\*/Kconfig. + +4. Add a MAINTAINERS file + It is generally placed at board/<board>/MAINTAINERS or + board/<vendor>/<board>/MAINTAINERS + +5. Add configs/<target>_defconfig When removing an obsolete board, the following steps are generally needed: - [1] Remove configs/<target>_defconfig - [2] Remove include/configs/<target>.h if it is not used by any other boards - [3] Remove board/<vendor>/<board>/* or board/<board>/* if it is not used - by any other boards - [4] Update MAINTAINERS if necessary - [5] Remove the unused entry from the board select menu in Kconfig - [6] Add an entry to doc/README.scrapyard +1. Remove configs/<target>_defconfig + +2. Remove include/configs/<target>.h if it is not used by any other boards + +3. Remove board/<vendor>/<board>/\* or board/<board>/\* if it is not used + by any other boards + +4. Update MAINTAINERS if necessary + +5. Remove the unused entry from the board select menu in Kconfig +6. Add an entry to doc/README.scrapyard TODO ---- -- In the pre-Kconfig, a single board had multiple entries in the boards.cfg - file with differences in the option fields. The corresponding defconfig - files were auto-generated when switching to Kconfig. Now we have too many - defconfig files compared with the number of the supported boards. It is +* In the pre-Kconfig, a single board had multiple entries in the boards.cfg + file with differences in the option fields. The corresponding defconfig + files were auto-generated when switching to Kconfig. Now we have too many + defconfig files compared with the number of the supported boards. It is recommended to have only one defconfig per board and allow users to select the config options. -- Move the config macros in header files to Kconfig. When we move at least +* Move the config macros in header files to Kconfig. When we move at least macros used in makefiles, we can drop include/autoconfig.mk, which makes the build scripts much simpler. diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 1548d2634ff..c742c2f8e20 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -71,7 +71,7 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2025.01-rc2 was released on Mon 11 November 2024. -.. * U-Boot v2025.01-rc3 was released on Mon 25 November 2024. +* U-Boot v2025.01-rc3 was released on Mon 25 November 2024. .. * U-Boot v2025.01-rc4 was released on Mon 09 December 2024. diff --git a/doc/usage/cmd/wget.rst b/doc/usage/cmd/wget.rst index b8ca35bb140..48bedf1e845 100644 --- a/doc/usage/cmd/wget.rst +++ b/doc/usage/cmd/wget.rst @@ -11,29 +11,54 @@ Synopsis :: - wget address [[hostIPaddr:]path] + wget [address] [host:]path + wget [address] url # lwIP only + Description ----------- -The wget command is used to download a file from an HTTP server. +The wget command is used to download a file from an HTTP(S) server. +In order to use HTTPS you will need to compile wget with lwIP support. + +Legacy syntax +~~~~~~~~~~~~~ + +The legacy syntax is supported by the legacy network stack (CONFIG_NET=y) +as well as by the lwIP base network stack (CONFIG_NET_LWIP=y). It supports HTTP +only. -wget command will use HTTP over TCP to download files from an HTTP server. By default the destination port is 80 and the source port is pseudo-random. -The environment variable *httpdstp* can be used to set the destination port. +On the legacy nework stack the environment variable *httpdstp* can be used to +set the destination port address memory address for the data downloaded -hostIPaddr - IP address of the HTTP server, defaults to the value of environment - variable *serverip* +host + IP address (or host name if `CONFIG_CMD_DNS` is enabled) of the HTTP + server, defaults to the value of environment variable *serverip*. path path of the file to be downloaded. -Example -------- +New syntax (lwIP only) +~~~~~~~~~~~~~~~~~~~~~~ + +In addition to the syntax described above, wget accepts URLs if the network +stack is lwIP. + +address + memory address for the data downloaded + +url + HTTP or HTTPS URL, that is: http[s]://<host>[:<port>]/<path>. + +Examples +-------- + +Example with the legacy network stack +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In the example the following steps are executed: @@ -52,13 +77,42 @@ In the example the following steps are executed: HTTP/1.0 302 Found Packets received 4, Transfer Successful +Example with lwIP +~~~~~~~~~~~~~~~~~ + +In the example the following steps are executed: + +* setup client network address +* download a file from the HTTPS server + +:: + + => dhcp + DHCP client bound to address 10.0.2.15 (3 ms) + => wget https://download.rockylinux.org/pub/rocky/9/isos/aarch64/Rocky-9.4-aarch64-minimal.iso + ########################################################################## + ########################################################################## + ########################################################################## + [...] + 1694892032 bytes transferred in 492181 ms (3.3 MiB/s) + Bytes transferred = 1694892032 (65060000 hex) + Configuration ------------- The command is only available if CONFIG_CMD_WGET=y. +To enable lwIP support set CONFIG_NET_LWIP=y. + +TCP Selective Acknowledgments in the legacy network stack can be enabled via +CONFIG_PROT_TCP_SACK=y. This will improve the download speed. Selective +Acknowledgments are enabled by default with lwIP. + +.. note:: -TCP Selective Acknowledgments can be enabled via CONFIG_PROT_TCP_SACK=y. -This will improve the download speed. + U-Boot currently has no way to verify certificates for HTTPS. + A place to store the root CA certificates is needed, and then MBed TLS would + need to walk the entire chain. Therefore, man-in-the middle attacks are + possible and HTTPS should not be relied upon for payload authentication. Return value ------------ diff --git a/doc/usage/dfu.rst b/doc/usage/dfu.rst index 8cc09c308d8..af805514b26 100644 --- a/doc/usage/dfu.rst +++ b/doc/usage/dfu.rst @@ -22,6 +22,7 @@ U-Boot implements this DFU capability (CONFIG_DFU) with the command dfu Today the supported DFU backends are: - MMC (RAW or FAT / EXT2 / EXT3 / EXT4 file system / SKIP / SCRIPT) +- SCSI (UFS, RAW partition, FAT / EXT2 / EXT3 / EXT4 file system / SKIP / SCRIPT) - NAND - RAM - SF (serial flash) @@ -51,6 +52,7 @@ The following configuration options are relevant to device firmware upgrade: * CONFIG_DFU_MTD * CONFIG_DFU_NAND * CONFIG_DFU_RAM +* CONFIG_DFU_SCSI * CONFIG_DFU_SF * CONFIG_DFU_SF_PART * CONFIG_DFU_TIMEOUT @@ -167,6 +169,36 @@ mmc Please note that this means the user will be able to execute any arbitrary commands just like in the u-boot's shell. +scsi + for UFS storage:: + + dfu 0 scsi <dev> + + each element in *dfu_alt_info* being + + * <name> raw <offset> <size> raw access to SCSI LUN + * <name> part <part_id> raw access to partition + * <name> fat <part_id> file in FAT partition + * <name> ext4 <part_id> file in EXT4 partition + * <name> skip 0 0 ignore flashed data + * <name> script 0 0 execute commands in shell + + with + + size + is the size of the access area (hexadecimal without "0x") + or 0 which means whole device + partid + is the GPT or DOS partition index. + dev + is the SCSI LU (Logical Unit) index (decimal only) + + A value of environment variable *dfu_alt_info* for UFS could be:: + + u-boot part 4;bl2 raw 0x1e 0x1d + + See mmc section above for details on the skip and script types. + nand raw slc nand device:: @@ -278,6 +310,7 @@ alternate list separated by '&' with the same format for each <alt>:: mmc <dev>=<alt1>;....;<altN> nand <dev>=<alt1>;....;<altN> ram <dev>=<alt1>;....;<altN> + scsi <dev>=<alt1>;....;<altN> sf <dev>=<alt1>;....;<altN> mtd <dev>=<alt1>;....;<altN> virt <dev>=<alt1>;....;<altN> diff --git a/doc/usage/fit/howto.rst b/doc/usage/fit/howto.rst index 280eff724f6..675c9aa5bb0 100644 --- a/doc/usage/fit/howto.rst +++ b/doc/usage/fit/howto.rst @@ -57,10 +57,6 @@ own subnode under the /images node, which should then be referenced from one or multiple /configurations subnodes. The required images must be enumerated in the "loadables" property as a list of strings. -CONFIG_SPL_FIT_GENERATOR can point to a script which generates this image source -file during the build process. It gets passed a list of device tree files (taken -from the CONFIG_OF_LIST symbol). - The SPL also records to a DT all additional images (called loadables) which are loaded. The information about loadables locations is passed via the DT node with fit-images name. diff --git a/drivers/bios_emulator/biosemui.h b/drivers/bios_emulator/biosemui.h index 954cd883158..739a17cae5f 100644 --- a/drivers/bios_emulator/biosemui.h +++ b/drivers/bios_emulator/biosemui.h @@ -128,6 +128,7 @@ typedef struct { u32 finalVal; } BE_portInfo; +#if defined(X86EMU_RAW_IO) #define PM_inpb(port) inb(port) #define PM_inpw(port) inw(port) #define PM_inpd(port) inl(port) @@ -135,6 +136,46 @@ typedef struct { #define PM_outpw(port, val) outw(val, port) #define PM_outpd(port, val) outl(val, port) +#else + +/* + * Until the emulator code is fixed, at least print warnings. + */ + +static inline u8 PM_inpb(u16 port) +{ + printf("x86 port 0x%x read attempt, returning 0\n", port); + return 0; +} + +static inline u16 PM_inpw(u16 port) +{ + printf("x86 port 0x%x read attempt, returning 0\n", port); + return 0; +} + +static inline u32 PM_inpd(u16 port) +{ + printf("x86 port 0x%x read attempt, returning 0\n", port); + return 0; +} + +static inline void PM_outpb(u16 port, u8 val) +{ + printf("x86 port 0x%x write attempt, ignoring\n", port); +} + +static inline void PM_outpw(u16 port, u16 val) +{ + printf("x86 port 0x%x write attempt, ignoring\n", port); +} + +static inline void PM_outpd(u16 port, u32 val) +{ + printf("x86 port 0x%x write attempt, ignoring\n", port); +} +#endif + #define LOG_inpb(port) PM_inpb(port) #define LOG_inpw(port) PM_inpw(port) #define LOG_inpd(port) PM_inpd(port) diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c index b426dc3bc45..c63cf3d26b5 100644 --- a/drivers/bios_emulator/x86emu/debug.c +++ b/drivers/bios_emulator/x86emu/debug.c @@ -38,6 +38,8 @@ ****************************************************************************/ #include <stdarg.h> +#include <string.h> +#include <vsprintf.h> #include <linux/ctype.h> #include <linux/printk.h> #include "x86emu/x86emui.h" diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index fa6d8e71281..0080d2a165c 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -164,6 +164,13 @@ config DM_BOOTCOUNT_SYSCON Accessing the backend is done using the regmap interface. +config DM_BOOTCOUNT_ZYNQMP + bool "Support ZynqMP PMUFW as a backing store for bootcount" + depends on ARCH_ZYNQMP + help + Enable support for the bootcount API by utilising the Persistent + Global General Storage Register 2 of the PMU. + endmenu endif diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile index 245f8796337..0cf79e428d6 100644 --- a/drivers/bootcount/Makefile +++ b/drivers/bootcount/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_DM_BOOTCOUNT_I2C_EEPROM) += i2c-eeprom.o obj-$(CONFIG_DM_BOOTCOUNT_I2C) += bootcount_dm_i2c.o obj-$(CONFIG_DM_BOOTCOUNT_SPI_FLASH) += spi-flash.o obj-$(CONFIG_DM_BOOTCOUNT_SYSCON) += bootcount_syscon.o +obj-$(CONFIG_DM_BOOTCOUNT_ZYNQMP) += bootcount_zynqmp.o diff --git a/drivers/bootcount/bootcount_zynqmp.c b/drivers/bootcount/bootcount_zynqmp.c new file mode 100644 index 00000000000..bc0984e2d26 --- /dev/null +++ b/drivers/bootcount/bootcount_zynqmp.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +// SPDX-FileCopyrightText: 2024 CERN (home.cern) + +#include <bootcount.h> +#include <dm.h> +#include <stdio.h> +#include <zynqmp_firmware.h> +#include <asm/arch/hardware.h> +#include <dm/platdata.h> + +static int bootcount_zynqmp_set(struct udevice *dev, const u32 val) +{ + int ret; + + ret = zynqmp_mmio_write((ulong)&pmu_base->pers_gen_storage2, 0xFF, val); + if (ret) + pr_info("%s write fail\n", __func__); + + return ret; +} + +static int bootcount_zynqmp_get(struct udevice *dev, u32 *val) +{ + int ret; + + *val = 0; + ret = zynqmp_mmio_read((ulong)&pmu_base->pers_gen_storage2, val); + if (ret) + pr_info("%s read fail\n", __func__); + + return ret; +} + +U_BOOT_DRVINFO(bootcount_zynqmp) = { + .name = "bootcount_zynqmp", +}; + +static const struct bootcount_ops bootcount_zynqmp_ops = { + .get = bootcount_zynqmp_get, + .set = bootcount_zynqmp_set, +}; + +U_BOOT_DRIVER(bootcount_zynqmp) = { + .name = "bootcount_zynqmp", + .id = UCLASS_BOOTCOUNT, + .ops = &bootcount_zynqmp_ops, +}; diff --git a/drivers/button/Kconfig b/drivers/button/Kconfig index 3918b05ae03..6cae16fcc8b 100644 --- a/drivers/button/Kconfig +++ b/drivers/button/Kconfig @@ -9,6 +9,17 @@ config BUTTON can provide access to board-specific buttons. Use of the device tree for configuration is encouraged. +config BUTTON_REMAP_PHONE_KEYS + bool "Remap phone keys for navigation" + depends on BUTTON + help + Enable remapping of phone keys to navigation keys. This is useful for + devices with phone keys that are not used in U-Boot. The phone keys + are remapped to the following navigation keys: + - Volume up: Up + - Volume down: Down + - Power: Enter + config BUTTON_ADC bool "Button adc" depends on BUTTON diff --git a/drivers/button/button-gpio.c b/drivers/button/button-gpio.c index 43b82d98aeb..31b85c8150e 100644 --- a/drivers/button/button-gpio.c +++ b/drivers/button/button-gpio.c @@ -20,6 +20,9 @@ static enum button_state_t button_gpio_get_state(struct udevice *dev) struct button_gpio_priv *priv = dev_get_priv(dev); int ret; + if (!priv) + return -ENODATA; + if (!dm_gpio_is_valid(&priv->gpio)) return -EREMOTEIO; ret = dm_gpio_get_value(&priv->gpio); @@ -32,6 +35,8 @@ static enum button_state_t button_gpio_get_state(struct udevice *dev) static int button_gpio_get_code(struct udevice *dev) { struct button_gpio_priv *priv = dev_get_priv(dev); + if (!priv) + return -ENODATA; int code = priv->linux_code; if (!code) @@ -51,7 +56,7 @@ static int button_gpio_probe(struct udevice *dev) return 0; ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio, GPIOD_IS_IN); - if (ret) + if (ret || !dm_gpio_is_valid(&priv->gpio)) return ret; ret = dev_read_u32(dev, "linux,code", &priv->linux_code); @@ -98,6 +103,8 @@ static int button_gpio_bind(struct udevice *parent) return ret; uc_plat = dev_get_uclass_plat(dev); uc_plat->label = label; + debug("Button '%s' bound to driver '%s'\n", label, + dev->driver->name); } return 0; diff --git a/drivers/button/button-uclass.c b/drivers/button/button-uclass.c index cda243389df..729983d5870 100644 --- a/drivers/button/button-uclass.c +++ b/drivers/button/button-uclass.c @@ -10,6 +10,7 @@ #include <button.h> #include <dm.h> #include <dm/uclass-internal.h> +#include <dt-bindings/input/linux-event-codes.h> int button_get_by_label(const char *label, struct udevice **devp) { @@ -37,14 +38,33 @@ enum button_state_t button_get_state(struct udevice *dev) return ops->get_state(dev); } +static int button_remap_phone_keys(int code) +{ + switch (code) { + case KEY_VOLUMEUP: + return KEY_UP; + case KEY_VOLUMEDOWN: + return KEY_DOWN; + case KEY_POWER: + return KEY_ENTER; + default: + return code; + } +} + int button_get_code(struct udevice *dev) { struct button_ops *ops = button_get_ops(dev); + int code; if (!ops->get_code) return -ENOSYS; - return ops->get_code(dev); + code = ops->get_code(dev); + if (CONFIG_IS_ENABLED(BUTTON_REMAP_PHONE_KEYS)) + return button_remap_phone_keys(code); + else + return code; } UCLASS_DRIVER(button) = { diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c index 77acd766262..b11e36202c1 100644 --- a/drivers/core/of_access.c +++ b/drivers/core/of_access.c @@ -666,11 +666,12 @@ int of_property_read_string_helper(const struct device_node *np, return i <= 0 ? -ENODATA : i; } -static int __of_parse_phandle_with_args(const struct device_node *np, - const char *list_name, - const char *cells_name, - int cell_count, int index, - struct of_phandle_args *out_args) +static int __of_root_parse_phandle_with_args(struct device_node *root, + const struct device_node *np, + const char *list_name, + const char *cells_name, + int cell_count, int index, + struct of_phandle_args *out_args) { const __be32 *list, *list_end; int rc = 0, cur_index = 0; @@ -706,7 +707,7 @@ static int __of_parse_phandle_with_args(const struct device_node *np, * below. */ if (cells_name || cur_index == index) { - node = of_find_node_by_phandle(NULL, phandle); + node = of_find_node_by_phandle(root, phandle); if (!node) { dm_warn("%s: could not find phandle\n", np->full_name); @@ -783,39 +784,65 @@ static int __of_parse_phandle_with_args(const struct device_node *np, return rc; } -struct device_node *of_parse_phandle(const struct device_node *np, - const char *phandle_name, int index) +struct device_node *of_root_parse_phandle(struct device_node *root, + const struct device_node *np, + const char *phandle_name, int index) { struct of_phandle_args args; if (index < 0) return NULL; - if (__of_parse_phandle_with_args(np, phandle_name, NULL, 0, index, - &args)) + if (__of_root_parse_phandle_with_args(root, np, phandle_name, NULL, 0, + index, &args)) return NULL; return args.np; } +int of_root_parse_phandle_with_args(struct device_node *root, + const struct device_node *np, + const char *list_name, const char *cells_name, + int cell_count, int index, + struct of_phandle_args *out_args) +{ + if (index < 0) + return -EINVAL; + + return __of_root_parse_phandle_with_args(root, np, list_name, cells_name, + cell_count, index, out_args); +} + +int of_root_count_phandle_with_args(struct device_node *root, + const struct device_node *np, + const char *list_name, const char *cells_name, + int cell_count) +{ + return __of_root_parse_phandle_with_args(root, np, list_name, cells_name, + cell_count, -1, NULL); +} + +struct device_node *of_parse_phandle(const struct device_node *np, + const char *phandle_name, int index) +{ + return of_root_parse_phandle(NULL, np, phandle_name, index); +} + int of_parse_phandle_with_args(const struct device_node *np, const char *list_name, const char *cells_name, int cell_count, int index, struct of_phandle_args *out_args) { - if (index < 0) - return -EINVAL; - - return __of_parse_phandle_with_args(np, list_name, cells_name, - cell_count, index, out_args); + return of_root_parse_phandle_with_args(NULL, np, list_name, cells_name, + cell_count, index, out_args); } int of_count_phandle_with_args(const struct device_node *np, const char *list_name, const char *cells_name, int cell_count) { - return __of_parse_phandle_with_args(np, list_name, cells_name, - cell_count, -1, NULL); + return of_root_count_phandle_with_args(NULL, np, list_name, cells_name, + cell_count); } static void of_alias_add(struct alias_prop *ap, struct device_node *np, diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 950895e72a9..c8161827d1c 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -879,11 +879,69 @@ int ofnode_read_string_list(ofnode node, const char *property, return count; } -static void ofnode_from_fdtdec_phandle_args(struct fdtdec_phandle_args *in, +ofnode ofnode_parse_phandle(ofnode node, const char *phandle_name, + int index) +{ + ofnode phandle; + + if (ofnode_is_np(node)) { + struct device_node *np; + + np = of_parse_phandle(ofnode_to_np(node), phandle_name, + index); + if (!np) + return ofnode_null(); + + phandle = np_to_ofnode(np); + } else { + struct fdtdec_phandle_args args; + + if (fdtdec_parse_phandle_with_args(ofnode_to_fdt(node), + ofnode_to_offset(node), + phandle_name, NULL, + 0, index, &args)) + return ofnode_null(); + + phandle = offset_to_ofnode(args.node); + } + + return phandle; +} + +ofnode oftree_parse_phandle(oftree tree, ofnode node, const char *phandle_name, + int index) +{ + ofnode phandle; + + if (ofnode_is_np(node)) { + struct device_node *np; + + np = of_root_parse_phandle(tree.np, ofnode_to_np(node), + phandle_name, index); + if (!np) + return ofnode_null(); + + phandle = np_to_ofnode(np); + } else { + struct fdtdec_phandle_args args; + + if (fdtdec_parse_phandle_with_args(tree.fdt, + ofnode_to_offset(node), + phandle_name, NULL, + 0, index, &args)) + return ofnode_null(); + + phandle = noffset_to_ofnode(node, args.node); + } + + return phandle; +} + +static void ofnode_from_fdtdec_phandle_args(ofnode node, struct fdtdec_phandle_args *in, struct ofnode_phandle_args *out) { assert(OF_MAX_PHANDLE_ARGS == MAX_PHANDLE_ARGS); - out->node = offset_to_ofnode(in->node); + out->node = noffset_to_ofnode(node, in->node); out->args_count = in->args_count; memcpy(out->args, in->args, sizeof(out->args)); } @@ -923,7 +981,40 @@ int ofnode_parse_phandle_with_args(ofnode node, const char *list_name, cell_count, index, &args); if (ret) return ret; - ofnode_from_fdtdec_phandle_args(&args, out_args); + ofnode_from_fdtdec_phandle_args(node, &args, out_args); + } + + return 0; +} + +int oftree_parse_phandle_with_args(oftree tree, ofnode node, const char *list_name, + const char *cells_name, int cell_count, + int index, + struct ofnode_phandle_args *out_args) +{ + if (ofnode_is_np(node)) { + struct of_phandle_args args; + int ret; + + ret = of_root_parse_phandle_with_args(tree.np, + ofnode_to_np(node), + list_name, cells_name, + cell_count, index, + &args); + if (ret) + return ret; + ofnode_from_of_phandle_args(&args, out_args); + } else { + struct fdtdec_phandle_args args; + int ret; + + ret = fdtdec_parse_phandle_with_args(tree.fdt, + ofnode_to_offset(node), + list_name, cells_name, + cell_count, index, &args); + if (ret) + return ret; + ofnode_from_fdtdec_phandle_args(node, &args, out_args); } return 0; @@ -941,6 +1032,18 @@ int ofnode_count_phandle_with_args(ofnode node, const char *list_name, cell_count, -1, NULL); } +int oftree_count_phandle_with_args(oftree tree, ofnode node, const char *list_name, + const char *cells_name, int cell_count) +{ + if (ofnode_is_np(node)) + return of_root_count_phandle_with_args(tree.np, ofnode_to_np(node), + list_name, cells_name, cell_count); + else + return fdtdec_parse_phandle_with_args(tree.fdt, + ofnode_to_offset(node), list_name, cells_name, + cell_count, -1, NULL); +} + ofnode ofnode_path(const char *path) { if (of_live_active()) @@ -1768,6 +1871,21 @@ const char *ofnode_options_read_str(const char *prop_name) return ofnode_read_string(uboot, prop_name); } +int ofnode_options_get_by_phandle(const char *prop_name, ofnode *nodep) +{ + ofnode uboot; + + uboot = ofnode_path("/options/u-boot"); + if (!ofnode_valid(uboot)) + return -EINVAL; + + *nodep = ofnode_parse_phandle(uboot, prop_name, 0); + if (!ofnode_valid(*nodep)) + return -EINVAL; + + return 0; +} + int ofnode_read_bootscript_address(u64 *bootscr_address, u64 *bootscr_offset) { int ret; diff --git a/drivers/core/root.c b/drivers/core/root.c index 7a714f5478a..c7fb58285ca 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -147,6 +147,13 @@ int dm_remove_devices_flags(uint flags) return 0; } + +void dm_remove_devices_active(void) +{ + /* Remove non-vital devices first */ + device_remove(dm_root(), DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL); + device_remove(dm_root(), DM_REMOVE_ACTIVE_ALL); +} #endif int dm_scan_plat(bool pre_reloc_only) diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 604386bb734..e33b0056d0b 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -89,6 +89,13 @@ config DFU_VIRT used at board level to manage specific behavior (OTP update for example). +config DFU_SCSI + bool "SCSI flash back end for DFU" + help + This option enables using DFU to read and write to SCSI devices + used at board level to manage specific behavior + (OTP update for example). + config SET_DFU_ALT_INFO bool "Dynamic set of DFU alternate information" help diff --git a/drivers/dfu/Makefile b/drivers/dfu/Makefile index 05d7cc61caa..6e1ab1c2ea5 100644 --- a/drivers/dfu/Makefile +++ b/drivers/dfu/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_$(XPL_)DFU_RAM) += dfu_ram.o obj-$(CONFIG_$(XPL_)DFU_SF) += dfu_sf.o obj-$(CONFIG_$(XPL_)DFU_WRITE_ALT) += dfu_alt.o obj-$(CONFIG_$(XPL_)DFU_VIRT) += dfu_virt.o +obj-$(CONFIG_$(XPL_)DFU_SCSI) += dfu_scsi.o diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 7a4d7ba2a7f..756569217bb 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -564,6 +564,9 @@ static int dfu_fill_entity(struct dfu_entity *dfu, char *s, int alt, } else if (strcmp(interface, "virt") == 0) { if (dfu_fill_entity_virt(dfu, devstr, argv, argc)) return -1; + } else if (strcmp(interface, "scsi") == 0) { + if (dfu_fill_entity_scsi(dfu, devstr, argv, argc)) + return -1; } else { printf("%s: Device %s not (yet) supported!\n", __func__, interface); @@ -660,7 +663,7 @@ int dfu_config_entities(char *env, char *interface, char *devstr) const char *dfu_get_dev_type(enum dfu_device_type t) { const char *const dev_t[] = {NULL, "eMMC", "OneNAND", "NAND", "RAM", - "SF", "MTD", "VIRT"}; + "SF", "MTD", "VIRT", "SCSI"}; return dev_t[t]; } diff --git a/drivers/dfu/dfu_scsi.c b/drivers/dfu/dfu_scsi.c new file mode 100644 index 00000000000..9f95194784c --- /dev/null +++ b/drivers/dfu/dfu_scsi.c @@ -0,0 +1,435 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DFU SCSI backend (based on MMC backend). + * + * Copyright (C) 2012 Samsung Electronics + * author: Lukasz Majewski <l.majewski@samsung.com> + * Copyright (C) 2024 Linaro Ltd. + */ + +#include <log.h> +#include <malloc.h> +#include <errno.h> +#include <div64.h> +#include <dfu.h> +#include <ext4fs.h> +#include <fat.h> +#include <scsi.h> +#include <part.h> +#include <command.h> +#include <linux/printk.h> + +static unsigned char *dfu_file_buf; +static u64 dfu_file_buf_len; +static u64 dfu_file_buf_offset; + +#define scsi_get_blk_desc(dev) ((struct blk_desc *)dev_get_uclass_plat(dev)) + +#define find_scsi_device(dev_num, scsi) blk_get_device(UCLASS_SCSI, dev_num, scsi) + +static int scsi_block_op(enum dfu_op op, struct dfu_entity *dfu, u64 offset, void *buf, long *len) +{ + struct udevice *scsi; + u32 blk_start, blk_count, n = 0; + int ret; + + ret = find_scsi_device(dfu->data.scsi.lun, &scsi); + if (ret < 0) { + pr_err("Device scsi %d - not found!", dfu->data.scsi.lun); + return -ENODEV; + } + + /* + * We must ensure that we work in lba_blk_size chunks, so ALIGN + * this value. + */ + *len = ALIGN(*len, dfu->data.scsi.lba_blk_size); + + blk_start = dfu->data.scsi.lba_start + (u32)lldiv(offset, dfu->data.scsi.lba_blk_size); + blk_count = *len / dfu->data.scsi.lba_blk_size; + if (blk_start + blk_count > dfu->data.scsi.lba_start + dfu->data.scsi.lba_size) { + puts("Request would exceed designated area!\n"); + return -EINVAL; + } + + debug("%s: %s dev: %d start: %d cnt: %d buf: 0x%p\n", __func__, + op == DFU_OP_READ ? "scsi READ" : "scsi WRITE", dfu->data.scsi.lun, blk_start, + blk_count, buf); + switch (op) { + case DFU_OP_READ: + n = blk_dread(scsi_get_blk_desc(scsi), blk_start, blk_count, buf); + break; + case DFU_OP_WRITE: + n = blk_dwrite(scsi_get_blk_desc(scsi), blk_start, blk_count, buf); + break; + default: + pr_err("Operation not supported\n"); + } + + if (n != blk_count) { + pr_err("scsi block operation failed"); + return -EIO; + } + + return 0; +} + +static int scsi_file_op(enum dfu_op op, struct dfu_entity *dfu, u64 offset, void *buf, u64 *len) +{ + char dev_part_str[8]; + int ret; + int fstype; + loff_t size = 0; + + switch (dfu->layout) { + case DFU_FS_FAT: + fstype = FS_TYPE_FAT; + break; + case DFU_FS_EXT4: + fstype = FS_TYPE_EXT; + break; + case DFU_SKIP: + return 0; + default: + printf("%s: Layout (%s) not (yet) supported!\n", __func__, + dfu_get_layout(dfu->layout)); + return -1; + } + + snprintf(dev_part_str, sizeof(dev_part_str), "%d:%d", dfu->data.scsi.dev, + dfu->data.scsi.part); + + ret = fs_set_blk_dev("scsi", dev_part_str, fstype); + if (ret) { + puts("dfu: fs_set_blk_dev error!\n"); + return ret; + } + + switch (op) { + case DFU_OP_READ: + ret = fs_read(dfu->name, (size_t)buf, offset, *len, &size); + if (ret) { + puts("dfu: fs_read error!\n"); + return ret; + } + *len = size; + break; + case DFU_OP_WRITE: + ret = fs_write(dfu->name, (size_t)buf, offset, *len, &size); + if (ret) { + puts("dfu: fs_write error!\n"); + return ret; + } + break; + case DFU_OP_SIZE: + ret = fs_size(dfu->name, &size); + if (ret) { + puts("dfu: fs_size error!\n"); + return ret; + } + *len = size; + break; + default: + return -1; + } + + return ret; +} + +static int scsi_file_buf_write(struct dfu_entity *dfu, u64 offset, void *buf, long *len) +{ + int ret = 0; + + if (offset == 0) { + dfu_file_buf_len = 0; + dfu_file_buf_offset = 0; + } + + /* Add to the current buffer. */ + if (dfu_file_buf_len + *len > CONFIG_SYS_DFU_MAX_FILE_SIZE) + *len = CONFIG_SYS_DFU_MAX_FILE_SIZE - dfu_file_buf_len; + memcpy(dfu_file_buf + dfu_file_buf_len, buf, *len); + dfu_file_buf_len += *len; + + if (dfu_file_buf_len == CONFIG_SYS_DFU_MAX_FILE_SIZE) { + ret = scsi_file_op(DFU_OP_WRITE, dfu, dfu_file_buf_offset, dfu_file_buf, + &dfu_file_buf_len); + dfu_file_buf_offset += dfu_file_buf_len; + dfu_file_buf_len = 0; + } + + return ret; +} + +static int scsi_file_buf_write_finish(struct dfu_entity *dfu) +{ + int ret = scsi_file_op(DFU_OP_WRITE, dfu, dfu_file_buf_offset, dfu_file_buf, + &dfu_file_buf_len); + + /* Now that we're done */ + dfu_file_buf_len = 0; + dfu_file_buf_offset = 0; + + return ret; +} + +int dfu_write_medium_scsi(struct dfu_entity *dfu, u64 offset, void *buf, long *len) +{ + int ret = -1; + + switch (dfu->layout) { + case DFU_RAW_ADDR: + ret = scsi_block_op(DFU_OP_WRITE, dfu, offset, buf, len); + break; + case DFU_FS_FAT: + case DFU_FS_EXT4: + ret = scsi_file_buf_write(dfu, offset, buf, len); + break; + case DFU_SCRIPT: + ret = run_command_list(buf, *len, 0); + break; + case DFU_SKIP: + ret = 0; + break; + default: + printf("%s: Layout (%s) not (yet) supported!\n", __func__, + dfu_get_layout(dfu->layout)); + } + + return ret; +} + +int dfu_flush_medium_scsi(struct dfu_entity *dfu) +{ + int ret = 0; + + switch (dfu->layout) { + case DFU_FS_FAT: + case DFU_FS_EXT4: + ret = scsi_file_buf_write_finish(dfu); + break; + case DFU_SCRIPT: + /* script may have changed the dfu_alt_info */ + dfu_reinit_needed = true; + break; + case DFU_RAW_ADDR: + case DFU_SKIP: + break; + default: + printf("%s: Layout (%s) not (yet) supported!\n", __func__, + dfu_get_layout(dfu->layout)); + } + + return ret; +} + +int dfu_get_medium_size_scsi(struct dfu_entity *dfu, u64 *size) +{ + int ret; + + switch (dfu->layout) { + case DFU_RAW_ADDR: + *size = dfu->data.scsi.lba_size * dfu->data.scsi.lba_blk_size; + return 0; + case DFU_FS_FAT: + case DFU_FS_EXT4: + ret = scsi_file_op(DFU_OP_SIZE, dfu, 0, NULL, size); + if (ret < 0) + return ret; + return 0; + case DFU_SCRIPT: + case DFU_SKIP: + return 0; + default: + printf("%s: Layout (%s) not (yet) supported!\n", __func__, + dfu_get_layout(dfu->layout)); + return -1; + } +} + +static int scsi_file_buf_read(struct dfu_entity *dfu, u64 offset, void *buf, long *len) +{ + int ret; + + if (offset == 0 || offset >= dfu_file_buf_offset + dfu_file_buf_len || + offset + *len < dfu_file_buf_offset) { + u64 file_len = CONFIG_SYS_DFU_MAX_FILE_SIZE; + + ret = scsi_file_op(DFU_OP_READ, dfu, offset, dfu_file_buf, &file_len); + if (ret < 0) + return ret; + dfu_file_buf_len = file_len; + dfu_file_buf_offset = offset; + } + if (offset + *len > dfu_file_buf_offset + dfu_file_buf_len) + return -EINVAL; + + /* Add to the current buffer. */ + memcpy(buf, dfu_file_buf + offset - dfu_file_buf_offset, *len); + + return 0; +} + +int dfu_read_medium_scsi(struct dfu_entity *dfu, u64 offset, void *buf, long *len) +{ + int ret = -1; + + switch (dfu->layout) { + case DFU_RAW_ADDR: + ret = scsi_block_op(DFU_OP_READ, dfu, offset, buf, len); + break; + case DFU_FS_FAT: + case DFU_FS_EXT4: + ret = scsi_file_buf_read(dfu, offset, buf, len); + break; + default: + printf("%s: Layout (%s) not (yet) supported!\n", __func__, + dfu_get_layout(dfu->layout)); + } + + return ret; +} + +void dfu_free_entity_scsi(struct dfu_entity *dfu) +{ + if (dfu_file_buf) { + free(dfu_file_buf); + dfu_file_buf = NULL; + } +} + +/* + * @param s Parameter string containing space-separated arguments: + * 1st: + * raw (raw read/write) + * fat (files) + * ext4 (^) + * part (partition image) + * 2nd and 3rd: + * lba_start and lba_size, for raw write + * scsi_dev and scsi_part, for filesystems and part + */ +int dfu_fill_entity_scsi(struct dfu_entity *dfu, char *devstr, char **argv, int argc) +{ + const char *entity_type; + ssize_t second_arg; + ssize_t third_arg = -1; + struct udevice *scsi; + struct blk_desc *blk_dev; + int ret; + char *s; + + if (argc < 2) { + pr_err("Need at least one argument\n"); + return -EINVAL; + } + + dfu->data.scsi.lun = dectoul(devstr, &s); + if (*s) + return -EINVAL; + + entity_type = argv[0]; + /* + * Base 0 means we'll accept (prefixed with 0x or 0) base 16, 8, + * with default 10. + */ + second_arg = simple_strtol(argv[1], &s, 0); + if (*s) + return -EINVAL; + if (argc >= 3) { + third_arg = simple_strtoul(argv[2], &s, 0); + if (*s) + return -EINVAL; + } + + if (scsi_scan(false)) { + pr_err("Couldn't init scsi device.\n"); + return -ENODEV; + } + + ret = find_scsi_device(dfu->data.scsi.lun, &scsi); + if (ret < 0) { + pr_err("Couldn't find scsi device no. %d.\n", dfu->data.scsi.lun); + return -ENODEV; + } + + blk_dev = scsi_get_blk_desc(scsi); + if (!blk_dev) { + pr_err("Couldn't get block device for scsi device no. %d.\n", dfu->data.scsi.lun); + return -ENODEV; + } + + /* if it's NOT a raw write */ + if (strcmp(entity_type, "raw")) { + dfu->data.scsi.dev = (second_arg != -1) ? second_arg : dfu->data.scsi.lun; + dfu->data.scsi.part = third_arg; + } + + if (!strcmp(entity_type, "raw")) { + dfu->layout = DFU_RAW_ADDR; + dfu->data.scsi.lba_start = second_arg; + if (third_arg < 0) { + pr_err("raw requires two arguments\n"); + return -EINVAL; + } + dfu->data.scsi.lba_size = third_arg; + dfu->data.scsi.lba_blk_size = blk_dev->blksz; + + /* + * In case the size is zero (i.e. scsi raw 0x10 0), + * assume the user intends to use whole device. + */ + if (third_arg == 0) + dfu->data.scsi.lba_size = blk_dev->lba; + + } else if (!strcmp(entity_type, "part")) { + struct disk_partition partinfo; + int scsipart = second_arg; + + if (third_arg >= 0) { + pr_err("part only accepts one argument\n"); + return -EINVAL; + } + + if (part_get_info(blk_dev, scsipart, &partinfo) != 0) { + pr_err("Couldn't find part #%d on scsi device #%d\n", scsipart, + dfu->data.scsi.lun); + return -ENODEV; + } + + dfu->layout = DFU_RAW_ADDR; + dfu->data.scsi.lba_start = partinfo.start; + dfu->data.scsi.lba_size = partinfo.size; + dfu->data.scsi.lba_blk_size = partinfo.blksz; + } else if (!strcmp(entity_type, "fat")) { + dfu->layout = DFU_FS_FAT; + } else if (!strcmp(entity_type, "ext4")) { + dfu->layout = DFU_FS_EXT4; + } else if (!strcmp(entity_type, "skip")) { + dfu->layout = DFU_SKIP; + } else if (!strcmp(entity_type, "script")) { + dfu->layout = DFU_SCRIPT; + } else { + pr_err("Memory layout (%s) not supported!\n", entity_type); + return -ENODEV; + } + + dfu->dev_type = DFU_DEV_SCSI; + dfu->get_medium_size = dfu_get_medium_size_scsi; + dfu->read_medium = dfu_read_medium_scsi; + dfu->write_medium = dfu_write_medium_scsi; + dfu->flush_medium = dfu_flush_medium_scsi; + dfu->inited = 0; + dfu->free_entity = dfu_free_entity_scsi; + + /* Check if file buffer is ready */ + if (!dfu_file_buf) { + dfu_file_buf = memalign(CONFIG_SYS_CACHELINE_SIZE, CONFIG_SYS_DFU_MAX_FILE_SIZE); + if (!dfu_file_buf) { + pr_err("Could not memalign 0x%x bytes\n", CONFIG_SYS_DFU_MAX_FILE_SIZE); + return -ENOMEM; + } + } + + return 0; +} diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index 50a69815907..76fcd3fb930 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -219,6 +219,44 @@ static bool at91_get_port_output(struct at91_port *at91_port, int offset) val = readl(&at91_port->osr); return val & mask; } + +static bool at91_is_port_gpio(struct at91_port *at91_port, int offset) +{ + u32 mask, val; + + mask = 1 << offset; + val = readl(&at91_port->psr); + return !!(val & mask); +} + +static void at91_set_port_multi_drive(struct at91_port *at91_port, int offset, int is_on) +{ + u32 mask; + + mask = 1 << offset; + if (is_on) + writel(mask, &at91_port->mder); + else + writel(mask, &at91_port->mddr); +} + +static bool at91_get_port_multi_drive(struct at91_port *at91_port, int offset) +{ + u32 mask, val; + + mask = 1 << offset; + val = readl(&at91_port->mdsr); + return !!(val & mask); +} + +static bool at91_get_port_pullup(struct at91_port *at91_port, int offset) +{ + u32 mask, val; + + mask = 1 << offset; + val = readl(&at91_port->pusr); + return !(val & mask); +} #endif static void at91_set_port_input(struct at91_port *at91_port, int offset, @@ -549,13 +587,68 @@ static int at91_gpio_get_function(struct udevice *dev, unsigned offset) { struct at91_port_priv *port = dev_get_priv(dev); - /* GPIOF_FUNC is not implemented yet */ + if (!at91_is_port_gpio(port->regs, offset)) + return GPIOF_FUNC; + if (at91_get_port_output(port->regs, offset)) return GPIOF_OUTPUT; else return GPIOF_INPUT; } +static int at91_gpio_set_flags(struct udevice *dev, unsigned int offset, + ulong flags) +{ + struct at91_port_priv *port = dev_get_priv(dev); + ulong supported_mask; + + supported_mask = GPIOD_OPEN_DRAIN | GPIOD_MASK_DIR | GPIOD_PULL_UP; + if (flags & ~supported_mask) + return -ENOTSUPP; + + if (flags & GPIOD_IS_OUT) { + if (flags & GPIOD_OPEN_DRAIN) + at91_set_port_multi_drive(port->regs, offset, true); + else + at91_set_port_multi_drive(port->regs, offset, false); + + at91_set_port_output(port->regs, offset, flags & GPIOD_IS_OUT_ACTIVE); + + } else if (flags & GPIOD_IS_IN) { + at91_set_port_input(port->regs, offset, false); + } + if (flags & GPIOD_PULL_UP) + at91_set_port_pullup(port->regs, offset, true); + + return 0; +} + +static int at91_gpio_get_flags(struct udevice *dev, unsigned int offset, + ulong *flagsp) +{ + struct at91_port_priv *port = dev_get_priv(dev); + ulong dir_flags = 0; + + if (at91_get_port_output(port->regs, offset)) { + dir_flags |= GPIOD_IS_OUT; + + if (at91_get_port_multi_drive(port->regs, offset)) + dir_flags |= GPIOD_OPEN_DRAIN; + + if (at91_get_port_value(port->regs, offset)) + dir_flags |= GPIOD_IS_OUT_ACTIVE; + } else { + dir_flags |= GPIOD_IS_IN; + } + + if (at91_get_port_pullup(port->regs, offset)) + dir_flags |= GPIOD_PULL_UP; + + *flagsp = dir_flags; + + return 0; +} + static const char *at91_get_bank_name(uint32_t base_addr) { switch (base_addr) { @@ -584,6 +677,8 @@ static const struct dm_gpio_ops gpio_at91_ops = { .get_value = at91_gpio_get_value, .set_value = at91_gpio_set_value, .get_function = at91_gpio_get_function, + .set_flags = at91_gpio_set_flags, + .get_flags = at91_gpio_get_flags, }; static int at91_gpio_probe(struct udevice *dev) diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 0213271e3a6..da929c33447 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -705,6 +705,9 @@ static int _dm_gpio_set_flags(struct gpio_desc *desc, ulong flags) if (ops->set_flags) { ret = ops->set_flags(dev, desc->offset, flags); } else { + if (flags & GPIOD_MASK_PULL) + return -EINVAL; + if (flags & GPIOD_IS_OUT) { bool value = flags & GPIOD_IS_OUT_ACTIVE; diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index f2ef4e5ce14..cd9f3926ac4 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -69,6 +69,17 @@ #define REG_EN_CTL 0x46 #define REG_EN_CTL_ENABLE (1 << 7) +/** + * pmic_gpio_match_data - platform specific configuration + * + * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them. + * This is a workaround for an unknown bug on some platforms where trying to write the + * GPIO configuration registers causes the board to hang. + */ +enum pmic_gpio_quirks { + QCOM_PMIC_QUIRK_READONLY = (1 << 0), +}; + struct qcom_pmic_gpio_data { uint32_t pid; /* Peripheral ID on SPMI bus */ bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */ @@ -117,8 +128,13 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned int offset, { struct qcom_pmic_gpio_data *plat = dev_get_plat(dev); uint32_t gpio_base = plat->pid + REG_OFFSET(offset); + ulong quirks = dev_get_driver_data(dev); int ret = 0; + /* Some PMICs don't like their GPIOs being configured */ + if (quirks & QCOM_PMIC_QUIRK_READONLY) + return 0; + /* Disable the GPIO */ ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, REG_EN_CTL_ENABLE, 0); @@ -262,6 +278,7 @@ static int qcom_gpio_bind(struct udevice *dev) { struct qcom_pmic_gpio_data *plat = dev_get_plat(dev); + ulong quirks = dev_get_driver_data(dev); struct udevice *child; struct driver *drv; int ret; @@ -275,7 +292,7 @@ static int qcom_gpio_bind(struct udevice *dev) /* Bind the GPIO driver as a child of the PMIC. */ ret = device_bind_with_driver_data(dev, drv, dev->name, - 0, dev_ofnode(dev), &child); + quirks, dev_ofnode(dev), &child); if (ret) return log_msg_ret("bind", ret); @@ -348,7 +365,7 @@ static const struct udevice_id qcom_gpio_ids[] = { { .compatible = "qcom,pms405-gpio" }, { .compatible = "qcom,pm6125-gpio" }, { .compatible = "qcom,pm8150-gpio" }, - { .compatible = "qcom,pm8550-gpio" }, + { .compatible = "qcom,pm8550-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, { } }; diff --git a/drivers/iommu/apple_dart.c b/drivers/iommu/apple_dart.c index 3e9e7819e51..bfd4ad20105 100644 --- a/drivers/iommu/apple_dart.c +++ b/drivers/iommu/apple_dart.c @@ -322,5 +322,5 @@ U_BOOT_DRIVER(apple_dart) = { .ops = &apple_dart_ops, .probe = apple_dart_probe, .remove = apple_dart_remove, - .flags = DM_FLAG_OS_PREPARE + .flags = DM_FLAG_OS_PREPARE | DM_FLAG_VITAL }; diff --git a/drivers/iommu/qcom-hyp-smmu.c b/drivers/iommu/qcom-hyp-smmu.c index 1b5a09bb7b3..c1b95bc8b8c 100644 --- a/drivers/iommu/qcom-hyp-smmu.c +++ b/drivers/iommu/qcom-hyp-smmu.c @@ -91,6 +91,8 @@ struct qcom_smmu_priv { phys_addr_t base; struct list_head devices; struct udevice *dev; + /* SMMU is not needed when running in EL2 */ + bool disable; /* Read-once config */ int num_cb; @@ -134,7 +136,7 @@ static int get_stream_id(struct udevice *dev) int count = ofnode_parse_phandle_with_args(node, "iommus", "#iommu-cells", 0, 0, &args); - if (count < 0 || args.args[0] == 0) { + if (count < 0) { printf("Error: %s: iommus property not found or wrong number of cells\n", __func__); return -EINVAL; @@ -277,6 +279,9 @@ static int qcom_smmu_connect(struct udevice *dev) if (WARN_ON(!priv)) return -EINVAL; + if (priv->disable) + return 0; + mdev = alloc_dev(dev); if (IS_ERR(mdev) && PTR_ERR(mdev) != -EEXIST) { printf("%s: %s Couldn't create mmu context\n", __func__, @@ -348,6 +353,8 @@ static int qcom_smmu_probe(struct udevice *dev) priv->base = dev_read_addr(dev); INIT_LIST_HEAD(&priv->devices); + priv->disable = current_el() > 1; + /* Read SMMU config */ val = gr0_readl(priv, ARM_SMMU_GR0_ID0); priv->num_smr = FIELD_GET(ARM_SMMU_ID0_NUMSMRG, val); diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c index 05e09909b7d..760750568c0 100644 --- a/drivers/led/led-uclass.c +++ b/drivers/led/led-uclass.c @@ -232,16 +232,24 @@ int led_activity_blink(void) #endif #endif +static const char *led_get_label(ofnode node) +{ + const char *label; + + label = ofnode_read_string(node, "label"); + if (!label && !ofnode_read_string(node, "compatible")) + label = ofnode_get_name(node); + + return label; +} + static int led_post_bind(struct udevice *dev) { struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev); const char *default_state; if (!uc_plat->label) - uc_plat->label = dev_read_string(dev, "label"); - - if (!uc_plat->label && !dev_read_string(dev, "compatible")) - uc_plat->label = ofnode_get_name(dev_ofnode(dev)); + uc_plat->label = led_get_label(dev_ofnode(dev)); uc_plat->default_state = LEDST_COUNT; @@ -300,15 +308,21 @@ static int led_post_probe(struct udevice *dev) static int led_init(struct uclass *uc) { struct led_uc_priv *priv = uclass_get_priv(uc); + ofnode led_node; + int ret; #ifdef CONFIG_LED_BOOT - priv->boot_led_label = ofnode_options_read_str("boot-led"); - priv->boot_led_period = ofnode_options_read_int("boot-led-period", 250); + ret = ofnode_options_get_by_phandle("boot-led", &led_node); + if (!ret) + priv->boot_led_label = led_get_label(led_node); + priv->boot_led_period = ofnode_options_read_int("boot-led-period-ms", 250); #endif #ifdef CONFIG_LED_ACTIVITY - priv->activity_led_label = ofnode_options_read_str("activity-led"); - priv->activity_led_period = ofnode_options_read_int("activity-led-period", + ret = ofnode_options_get_by_phandle("activity-led", &led_node); + if (!ret) + priv->activity_led_label = led_get_label(led_node); + priv->activity_led_period = ofnode_options_read_int("activity-led-period-ms", 250); #endif diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c index 10f0173d805..3cb38aa28ad 100644 --- a/drivers/misc/i2c_eeprom.c +++ b/drivers/misc/i2c_eeprom.c @@ -264,6 +264,13 @@ static const struct i2c_eeprom_drv_data atmel24c256_data = { .offset_len = 2, }; +static const struct i2c_eeprom_drv_data st24256e_wlp_data = { + .size = 64, + .pagesize = 64, + .addr_offset_mask = 0, + .offset_len = 2, +}; + static const struct i2c_eeprom_drv_data atmel24c512_data = { .size = 65536, .pagesize = 64, @@ -287,6 +294,7 @@ static const struct udevice_id i2c_eeprom_std_ids[] = { { .compatible = "atmel,24c128", (ulong)&atmel24c128_data }, { .compatible = "atmel,24c256", (ulong)&atmel24c256_data }, { .compatible = "atmel,24c512", (ulong)&atmel24c512_data }, + { .compatible = "st,24256e-wl", (ulong)&st24256e_wlp_data }, { } }; diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 591d71b096a..a40c8badf9a 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -951,6 +951,26 @@ int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window) return ret; } +int sc_timer_control_siemens_pmic_wdog(sc_ipc_t ipc, u8 cmd) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (u8)TIMER_FUNC_CTRL_SIEMENS_PMIC_WDOG; + RPC_U8(&msg, 0U) = (u8)cmd; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: res:%d\n", __func__, RPC_R8(&msg)); + + return ret; +} + int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr) { diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index 99a18a109b7..0774e0a4c9e 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -121,6 +121,11 @@ static int k3_avs_program_voltage(struct k3_avs_privdata *priv, if (!vd->supply) return -ENODEV; + if (!volt) { + dev_err(priv->dev, "No efuse found for opp_%d\n", opp_id); + return -EINVAL; + } + vd->opp = opp_id; vd->flags |= VD_FLAG_INIT_DONE; @@ -193,6 +198,33 @@ static int match_opp(struct vd_data *vd, u32 freq) } /** + * k3_check_opp: Check for presence of opp efuse + * @dev: AVS device + * @vdd_id: voltage domain ID + * @opp_id: opp id to check if voltage is present + * + * Checks to see if an opp has voltage. k3_avs probe will populate + * voltage data if efuse is present. Returns 0 if data is valid. + */ +int k3_avs_check_opp(struct udevice *dev, int vdd_id, int opp_id) +{ + struct k3_avs_privdata *priv = dev_get_priv(dev); + struct vd_data *vd; + int volt; + + vd = get_vd(priv, vdd_id); + if (!vd) + return -EINVAL; + + volt = vd->opps[opp_id].volt; + if (volt) + return 0; + + printf("No efuse found for opp_%d\n", opp_id); + return -EINVAL; +} + +/** * k3_avs_notify_freq: Notify clock rate change towards AVS subsystem * @dev_id: Device ID for the clock to be changed * @clk_id: Clock ID for the clock to be changed @@ -501,6 +533,10 @@ static struct vd_data j721e_vd_data[] = { .dev_id = 202, /* J721E_DEV_A72SS0_CORE0 */ .clk_id = 2, /* ARM clock */ .opps = { + [AM6_OPP_LOW] = { + .volt = 0, /* voltage TBD after OPP fuse reading */ + .freq = 1000000000, + }, [AM6_OPP_NOM] = { .volt = 880000, /* TBD in DM */ .freq = 2000000000, diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 4e5c932c071..27bb7052fca 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -15,6 +15,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <linux/bitops.h> +#include <power/regulator.h> /* Non-standard registers needed for SDHCI startup */ #define SDCC_MCI_POWER 0x0 @@ -43,6 +44,7 @@ struct msm_sdhc { struct sdhci_host host; void *base; struct clk_bulk clks; + struct udevice *vqmmc; }; struct msm_sdhc_variant_info { @@ -163,6 +165,16 @@ static int msm_sdc_probe(struct udevice *dev) if (ret) return ret; + /* Get the vqmmc regulator and enable it if available */ + device_get_supply_regulator(dev, "vqmmc-supply", &prv->vqmmc); + if (prv->vqmmc) { + ret = regulator_set_enable_if_allowed(prv->vqmmc, true); + if (ret) { + printf("Failed to enable the VQMMC regulator\n"); + return ret; + } + } + var_info = (void *)dev_get_driver_data(dev); if (!var_info->mci_removed) { ret = msm_sdc_mci_init(prv); diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index 817fab4ca36..25f187a2eec 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -2205,7 +2205,6 @@ static const struct udevice_id atmel_nand_controller_of_ids[] = { static int atmel_nand_controller_probe(struct udevice *dev) { const struct atmel_nand_controller_caps *caps; - struct udevice *pmecc_dev; caps = (struct atmel_nand_controller_caps *)dev_get_driver_data(dev); if (!caps) { @@ -2213,12 +2212,6 @@ static int atmel_nand_controller_probe(struct udevice *dev) return -EINVAL; } - /* Probe pmecc driver */ - if (uclass_get_device(UCLASS_MTD, 1, &pmecc_dev)) { - printf("%s: get device fail\n", __func__); - return -EINVAL; - } - return caps->ops->probe(dev, caps); } diff --git a/drivers/mtd/nand/raw/atmel/pmecc.c b/drivers/mtd/nand/raw/atmel/pmecc.c index 51f6bd2e65b..e500a0fe3f8 100644 --- a/drivers/mtd/nand/raw/atmel/pmecc.c +++ b/drivers/mtd/nand/raw/atmel/pmecc.c @@ -913,6 +913,7 @@ struct atmel_pmecc *devm_atmel_pmecc_get(struct udevice *userdev) ret = ofnode_parse_phandle_with_args(userdev->node_, "ecc-engine", NULL, 0, 0, &args); + /* Probe pmecc driver */ ret = uclass_get_device_by_ofnode(UCLASS_MTD, args.node, &pdev); if (ret) return NULL; diff --git a/drivers/mtd/ubispl/ubispl.c b/drivers/mtd/ubispl/ubispl.c index 90a7c4c6f9e..9face5fae15 100644 --- a/drivers/mtd/ubispl/ubispl.c +++ b/drivers/mtd/ubispl/ubispl.c @@ -113,7 +113,7 @@ static int vtbl_check(struct ubi_scan_info *ubi, crc = crc32(UBI_CRC32_INIT, &vtbl[i], UBI_VTBL_RECORD_SIZE_CRC); if (be32_to_cpu(vtbl[i].crc) != crc) { - ubi_err("bad CRC at record %u: %#08x, not %#08x", + ubi_err("bad CRC at record %u: #%08x, not #%08x", i, crc, be32_to_cpu(vtbl[i].crc)); ubi_dump_vtbl_record(&vtbl[i], i); return 1; diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index d6d5cb52fdd..eca681b16d1 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -160,7 +160,7 @@ static int fec_get_clk_rate(void *udev, int idx) } } -static void fec_mii_setspeed(struct ethernet_regs *eth) +static void fec_mii_setspeed(struct udevice *dev, struct ethernet_regs *eth) { /* * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock @@ -182,7 +182,7 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) u32 hold; int ret; - ret = fec_get_clk_rate(NULL, 0); + ret = fec_get_clk_rate(dev, 0); if (ret < 0) { printf("Can't find FEC0 clk rate: %d\n", ret); return; @@ -581,7 +581,7 @@ static int fecmxc_init(struct udevice *dev) fec_reg_setup(fec); if (fec->xcv_type != SEVENWIRE) - fec_mii_setspeed(fec->bus->priv); + fec_mii_setspeed(dev, fec->bus->priv); /* Set Opcode/Pause Duration Register */ writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ @@ -996,7 +996,7 @@ static void fec_free_descs(struct fec_priv *fec) free(fec->tbd_base); } -struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) +struct mii_dev *fec_get_miibus(struct udevice *dev, ulong base_addr, int dev_id) { struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; struct mii_dev *bus; @@ -1018,7 +1018,7 @@ struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) free(bus); return NULL; } - fec_mii_setspeed(eth); + fec_mii_setspeed(dev, eth); return bus; } @@ -1354,10 +1354,10 @@ static int fecmxc_probe(struct udevice *dev) if (!bus) { dm_mii_bus = false; #ifdef CONFIG_FEC_MXC_MDIO_BASE - bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, + bus = fec_get_miibus(dev, (ulong)CONFIG_FEC_MXC_MDIO_BASE, dev_seq(dev)); #else - bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev)); + bus = fec_get_miibus(dev, (ulong)priv->eth, dev_seq(dev)); #endif } if (!bus) { diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c index 8908a34df54..5c90d60e7d1 100644 --- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c @@ -84,12 +84,6 @@ enum qphy_reg_layout { QPHY_LAYOUT_SIZE }; -static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, - [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, - [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, -}; - static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START, [QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS, @@ -189,6 +183,29 @@ static const struct qmp_ufs_init_tbl sdm845_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; +static const struct qmp_ufs_init_tbl sm8150_ufsphy_hs_g4_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75), +}; + +static const struct qmp_ufs_init_tbl sm8150_ufsphy_hs_g4_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), +}; + static const struct qmp_ufs_init_tbl sm8150_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), @@ -461,6 +478,112 @@ static const struct qmp_ufs_init_tbl sm8650_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e), }; + +static const struct qmp_ufs_init_tbl sc7280_ufsphy_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), +}; + +static const struct qmp_ufs_init_tbl sc7280_ufsphy_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), +}; + +static const struct qmp_ufs_init_tbl sc7280_ufsphy_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), +}; + +static const struct qmp_ufs_init_tbl sc7280_ufsphy_hs_g4_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f), +}; + struct qmp_ufs_offsets { u16 serdes; u16 pcs; @@ -623,6 +746,44 @@ static const struct qmp_ufs_cfg sdm845_ufsphy_cfg = { .no_pcs_sw_reset = true, }; +static const struct qmp_ufs_cfg sm8150_ufsphy_cfg = { + .lanes = 2, + + .offsets = &qmp_ufs_offsets, + + .tbls = { + .serdes = sm8150_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx = sm8150_ufsphy_tx, + .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), + .rx = sm8150_ufsphy_rx, + .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs = sm8150_ufsphy_pcs, + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), + }, + .tbls_hs_b = { + .serdes = sm8150_ufsphy_hs_b_serdes, + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), + }, + .tbls_hs_g4 = { + .tx = sm8150_ufsphy_hs_g4_tx, + .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), + .rx = sm8150_ufsphy_hs_g4_rx, + .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx), + .pcs = sm8150_ufsphy_hs_g4_pcs, + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), + }, + .clk_list = sdm845_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list = qmp_ufs_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_ufs_vreg_l), + .reset_list = qmp_ufs_reset_l, + .num_resets = ARRAY_SIZE(qmp_ufs_reset_l), + .regs = ufsphy_v4_regs_layout, + + .no_pcs_sw_reset = false, +}; + static const struct qmp_ufs_cfg sm8250_ufsphy_cfg = { .lanes = 2, @@ -713,6 +874,41 @@ static const struct qmp_ufs_cfg sm8650_ufsphy_cfg = { .no_pcs_sw_reset = false, }; + +static const struct qmp_ufs_cfg sc7280_ufsphy_cfg = { + .lanes = 2, + + .offsets = &qmp_ufs_offsets, + + .tbls = { + .serdes = sm8150_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx = sc7280_ufsphy_tx, + .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx), + .rx = sc7280_ufsphy_rx, + .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx), + .pcs = sc7280_ufsphy_pcs, + .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs), + }, + .tbls_hs_b = { + .serdes = sm8150_ufsphy_hs_b_serdes, + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), + }, + .tbls_hs_g4 = { + .tx = sm8250_ufsphy_hs_g4_tx, + .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), + .rx = sc7280_ufsphy_hs_g4_rx, + .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx), + .pcs = sm8150_ufsphy_hs_g4_pcs, + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), + }, + .clk_list = sdm845_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list = qmp_ufs_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_ufs_vreg_l), + .regs = ufsphy_v4_regs_layout, +}; + static void qmp_ufs_configure_lane(void __iomem *base, const struct qmp_ufs_init_tbl tbl[], int num, @@ -1100,9 +1296,11 @@ static struct phy_ops qmp_ufs_ops = { static const struct udevice_id qmp_ufs_ids[] = { { .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg }, + { .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg }, { .compatible = "qcom,sm8250-qmp-ufs-phy", .data = (ulong)&sm8250_ufsphy_cfg }, { .compatible = "qcom,sm8550-qmp-ufs-phy", .data = (ulong)&sm8550_ufsphy_cfg }, { .compatible = "qcom,sm8650-qmp-ufs-phy", .data = (ulong)&sm8650_ufsphy_cfg }, + { .compatible = "qcom,sc7280-qmp-ufs-phy", .data = (ulong)&sc7280_ufsphy_cfg, }, { } }; diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 525b6d5b79f..6e9202b9579 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -216,9 +216,6 @@ static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss) req_type = readl(ddrss->ddrss_ctrl_mmr + CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10) & 0x03; - debug("%s: received freq change req: req type = %d, req no. = %d, instance = %d\n", - __func__, req_type, counter, ddrss->instance); - if (req_type == 1) clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); else if (req_type == 2) @@ -245,8 +242,6 @@ static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd) { struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance; - debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n"); - switch (ddrss->dram_class) { case DENALI_CTL_0_DRAM_CLASS_DDR4: break; diff --git a/drivers/remoteproc/rproc-elf-loader.c b/drivers/remoteproc/rproc-elf-loader.c index ab1836b3f07..0b3941b7798 100644 --- a/drivers/remoteproc/rproc-elf-loader.c +++ b/drivers/remoteproc/rproc-elf-loader.c @@ -6,6 +6,7 @@ #include <dm.h> #include <elf.h> #include <log.h> +#include <mapmem.h> #include <remoteproc.h> #include <asm/cache.h> #include <dm/device_compat.h> @@ -180,6 +181,7 @@ int rproc_elf32_load_image(struct udevice *dev, unsigned long addr, ulong size) for (i = 0; i < ehdr->e_phnum; i++, phdr++) { void *dst = (void *)(uintptr_t)phdr->p_paddr; void *src = (void *)addr + phdr->p_offset; + ulong dst_addr; if (phdr->p_type != PT_LOAD) continue; @@ -195,10 +197,11 @@ int rproc_elf32_load_image(struct udevice *dev, unsigned long addr, ulong size) if (phdr->p_filesz != phdr->p_memsz) memset(dst + phdr->p_filesz, 0x00, phdr->p_memsz - phdr->p_filesz); - flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN), - roundup((unsigned long)dst + phdr->p_filesz, + dst_addr = map_to_sysmem(dst); + flush_cache(rounddown(dst_addr, ARCH_DMA_MINALIGN), + roundup(dst_addr + phdr->p_filesz, ARCH_DMA_MINALIGN) - - rounddown((unsigned long)dst, ARCH_DMA_MINALIGN)); + rounddown(dst_addr, ARCH_DMA_MINALIGN)); } return 0; @@ -377,6 +380,7 @@ int rproc_elf32_load_rsc_table(struct udevice *dev, ulong fw_addr, const struct dm_rproc_ops *ops; Elf32_Shdr *shdr; void *src, *dst; + ulong dst_addr; shdr = rproc_elf32_find_rsc_table(dev, fw_addr, fw_size); if (!shdr) @@ -398,10 +402,10 @@ int rproc_elf32_load_rsc_table(struct udevice *dev, ulong fw_addr, (ulong)dst, *rsc_size); memcpy(dst, src, *rsc_size); - flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN), - roundup((unsigned long)dst + *rsc_size, - ARCH_DMA_MINALIGN) - - rounddown((unsigned long)dst, ARCH_DMA_MINALIGN)); + dst_addr = map_to_sysmem(dst); + flush_cache(rounddown(dst_addr, ARCH_DMA_MINALIGN), + roundup(dst_addr + *rsc_size, ARCH_DMA_MINALIGN) - + rounddown(dst_addr, ARCH_DMA_MINALIGN)); return 0; } diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index 222f828f54e..dcf28c75596 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -125,49 +125,8 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv) return 0; } -#if defined(CONFIG_DM_GPIO) -int cadence_qspi_versal_flash_reset(struct udevice *dev) -{ - struct gpio_desc gpio; - u32 reset_gpio; - int ret; - - /* request gpio and set direction as output set to 1 */ - ret = gpio_request_by_name(dev, "reset-gpios", 0, &gpio, - GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); - if (ret) { - printf("%s: unable to reset ospi flash device", __func__); - return ret; - } - - reset_gpio = PMIO_NODE_ID_BASE + gpio.offset; - - /* Request for pin */ - xilinx_pm_request(PM_PINCTRL_REQUEST, reset_gpio, 0, 0, 0, NULL); - - /* Enable hysteresis in cmos receiver */ - xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio, - PM_PINCTRL_CONFIG_SCHMITT_CMOS, - PM_PINCTRL_INPUT_TYPE_SCHMITT, 0, NULL); - - /* Disable Tri-state */ - xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio, - PM_PINCTRL_CONFIG_TRI_STATE, - PM_PINCTRL_TRI_STATE_DISABLE, 0, NULL); - udelay(1); - - /* Set value 0 to pin */ - dm_gpio_set_value(&gpio, 0); - udelay(1); - - /* Set value 1 to pin */ - dm_gpio_set_value(&gpio, 1); - udelay(1); - - return 0; -} -#else -int cadence_qspi_versal_flash_reset(struct udevice *dev) +#if !CONFIG_IS_ENABLED(DM_GPIO) +int cadence_qspi_flash_reset(struct udevice *dev) { /* CRP WPROT */ writel(0, WPROT_CRP); diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 9c466f8695e..623904ecdad 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -33,7 +33,7 @@ __weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, return 0; } -__weak int cadence_qspi_versal_flash_reset(struct udevice *dev) +__weak int cadence_qspi_flash_reset(struct udevice *dev) { return 0; } @@ -251,15 +251,10 @@ static int cadence_spi_probe(struct udevice *bus) priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz); - /* Versal and Versal-NET use spi calibration to set read delay */ - if (CONFIG_IS_ENABLED(ARCH_VERSAL) || - CONFIG_IS_ENABLED(ARCH_VERSAL_NET) || - CONFIG_IS_ENABLED(ARCH_VERSAL2)) - if (priv->read_delay >= 0) - priv->read_delay = -1; - /* Reset ospi flash device */ - return cadence_qspi_versal_flash_reset(bus); + return cadence_qspi_flash_reset(bus); + + return 0; } static int cadence_spi_remove(struct udevice *dev) diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 36b7d383aa9..d6049753740 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -446,7 +446,7 @@ int _spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, slave = dev_get_parent_priv(dev); bus_data = dev_get_uclass_priv(bus); -#if CONFIG_IS_ENABLED(SPI_ADVANCE) +#if CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL) if ((dev_read_bool(dev, "parallel-memories")) && !slave->multi_cs_cap) { dev_err(dev, "controller doesn't support multi CS\n"); return -EINVAL; @@ -515,7 +515,7 @@ int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat) int mode = 0; int value; -#if CONFIG_IS_ENABLED(SPI_ADVANCE) +#if CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL) int ret; ret = dev_read_u32_array(dev, "reg", plat->cs, SPI_CS_CNT_MAX); diff --git a/drivers/sysinfo/gazerbeam.h b/drivers/sysinfo/gazerbeam.h index 6bf3c0098d1..047f365436f 100644 --- a/drivers/sysinfo/gazerbeam.h +++ b/drivers/sysinfo/gazerbeam.h @@ -8,8 +8,8 @@ #include <sysinfo.h> enum { - BOARD_HWVERSION = SYSINFO_ID_BOARD_MODEL, - BOARD_MULTICHANNEL = SYSINFO_ID_USER, + BOARD_HWVERSION = SYSID_BOARD_MODEL, + BOARD_MULTICHANNEL = SYSID_USER, BOARD_VARIANT }; diff --git a/drivers/sysinfo/gpio.c b/drivers/sysinfo/gpio.c index aaca318419b..66d2a913087 100644 --- a/drivers/sysinfo/gpio.c +++ b/drivers/sysinfo/gpio.c @@ -38,7 +38,7 @@ static int sysinfo_gpio_get_int(struct udevice *dev, int id, int *val) struct sysinfo_gpio_priv *priv = dev_get_priv(dev); switch (id) { - case SYSINFO_ID_BOARD_MODEL: + case SYSID_BOARD_MODEL: *val = priv->revision; return 0; default: @@ -51,7 +51,7 @@ static int sysinfo_gpio_get_str(struct udevice *dev, int id, size_t size, char * struct sysinfo_gpio_priv *priv = dev_get_priv(dev); switch (id) { - case SYSINFO_ID_BOARD_MODEL: { + case SYSID_BOARD_MODEL: { const char *name = NULL; int i, ret; u32 revision; diff --git a/drivers/sysinfo/rcar3.c b/drivers/sysinfo/rcar3.c index 37e2cccd9af..2994df9ab1c 100644 --- a/drivers/sysinfo/rcar3.c +++ b/drivers/sysinfo/rcar3.c @@ -46,7 +46,7 @@ static int sysinfo_rcar_get_str(struct udevice *dev, int id, size_t size, char * struct sysinfo_rcar_priv *priv = dev_get_priv(dev); switch (id) { - case SYSINFO_ID_BOARD_MODEL: + case SYSID_BOARD_MODEL: strncpy(val, priv->boardmodel, size); val[size - 1] = '\0'; return 0; diff --git a/drivers/sysinfo/sandbox.h b/drivers/sysinfo/sandbox.h index d9c5804c26a..a7cbac0ce18 100644 --- a/drivers/sysinfo/sandbox.h +++ b/drivers/sysinfo/sandbox.h @@ -5,7 +5,7 @@ */ enum { - BOOL_CALLED_DETECT = SYSINFO_ID_USER, + BOOL_CALLED_DETECT = SYSID_USER, INT_TEST1, INT_TEST2, STR_VACATIONSPOT, diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c index 4bd3b9d10dc..69d3073b669 100644 --- a/drivers/usb/eth/asix88179.c +++ b/drivers/usb/eth/asix88179.c @@ -173,9 +173,10 @@ #define USB_BULK_SEND_TIMEOUT 5000 #define USB_BULK_RECV_TIMEOUT 5000 -#define AX_RX_URB_SIZE 1024 * 0x12 +#define AX_RX_URB_SIZE 1024 * 0x1a #define BLK_FRAME_SIZE 0x200 #define PHY_CONNECT_TIMEOUT 5000 +#define PHY_RESET_TIMEOUT 500 #define TIMEOUT_RESOLUTION 50 /* ms */ @@ -192,10 +193,10 @@ static const struct { unsigned char ctrl, timer_l, timer_h, size, ifg; } AX88179_BULKIN_SIZE[] = { - {7, 0x4f, 0, 0x02, 0xff}, - {7, 0x20, 3, 0x03, 0xff}, - {7, 0xae, 7, 0x04, 0xff}, - {7, 0xcc, 0x4c, 0x04, 8}, + {7, 0x4f, 0, 0x12, 0xff}, + {7, 0x20, 3, 0x16, 0xff}, + {7, 0xae, 7, 0x18, 0xff}, + {7, 0xcc, 0x4c, 0x18, 8}, }; /* driver private */ @@ -285,6 +286,26 @@ static int asix_write_mac(struct ueth_data *dev, uint8_t *enetaddr) return ret; } +static int asix_reset_phy(struct ueth_data *dev) +{ + u16 bmcr; + u32 t; + + /* Reset the PHY */ + bmcr = BMCR_RESET; + asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_BMCR, 2, &bmcr); + + for (t = 0; t < PHY_RESET_TIMEOUT; t += TIMEOUT_RESOLUTION) { + asix_read_cmd(dev, AX_ACCESS_PHY, 0x03, MII_BMCR, 2, &bmcr); + if (!(bmcr & BMCR_RESET)) + return 0; + mdelay(TIMEOUT_RESOLUTION); + } + + debug("Reset PHY timeout\n"); + return -ETIMEDOUT; +} + static int asix_basic_reset(struct ueth_data *dev, struct asix_private *dev_priv) { @@ -311,7 +332,7 @@ static int asix_basic_reset(struct ueth_data *dev, memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); - dev_priv->rx_urb_size = 128 * 20; + dev_priv->rx_urb_size = 1024 * 20; /* Water Level configuration */ *tmp = 0x34; @@ -344,14 +365,22 @@ static int asix_basic_reset(struct ueth_data *dev, AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN; asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16); + asix_reset_phy(dev); + u16 adv = 0; - adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK | - ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP; + adv = ADVERTISE_ALL | ADVERTISE_CSMA | + ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP; asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv); adv = ADVERTISE_1000FULL; asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv); + /* Restart auto-negotiation */ + u16 bmcr = 0; + asix_read_cmd(dev, AX_ACCESS_PHY, 0x03, MII_BMCR, 2, &bmcr); + bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; + asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_BMCR, 2, &bmcr); + return 0; } diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 0e45f0a0922..b39b2546e5c 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -351,6 +351,13 @@ config WDT_SBSA In the single stage mode, when the timeout is reached, your system will be reset by WS1. The first signal (WS0) is ignored. +config WDT_SIEMENS_PMIC + bool "Enable PMIC Watchdog Timer support for Siemens platforms" + depends on ARCH_IMX8 && WDT + help + Select this to enable the PMIC watchdog driver controlled via + IMX8 SCU API found on Siemens platforms. + config WDT_SL28CPLD bool "sl28cpld watchdog timer support" depends on WDT && SL28CPLD diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 0b107c008f7..9b6b1a8e8ad 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o +obj-$(CONFIG_WDT_SIEMENS_PMIC) += siemens_pmic_wdt.o obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o obj-$(CONFIG_WDT_SP805) += sp805_wdt.o obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o diff --git a/drivers/watchdog/siemens_pmic_wdt.c b/drivers/watchdog/siemens_pmic_wdt.c new file mode 100644 index 00000000000..87e817bb5b2 --- /dev/null +++ b/drivers/watchdog/siemens_pmic_wdt.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Driver for a PMIC watchdog timer controlled via Siemens SCU firmware + * extensions. Only useful on some Siemens i.MX8-based platforms as + * special NXP SCFW is needed which provides the needed SCU API. + * + * Copyright (C) 2024 Siemens AG + */ + +#include <dm.h> +#include <wdt.h> +#include <firmware/imx/sci/sci.h> + +/* watchdog commands */ +#define CMD_START_WDT 0x55 +#define CMD_STOP_WDT 0x45 +#define CMD_PING_WDT 0x35 + +static int scu_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + /* start external watchdog via Timer API */ + return sc_timer_control_siemens_pmic_wdog(-1, CMD_START_WDT); +} + +static int scu_wdt_stop(struct udevice *dev) +{ + /* stop external watchdog via Timer API */ + return sc_timer_control_siemens_pmic_wdog(-1, CMD_STOP_WDT); +} + +static int scu_wdt_reset(struct udevice *dev) +{ + return sc_timer_control_siemens_pmic_wdog(-1, CMD_PING_WDT); +} + +static int scu_wdt_probe(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + return 0; +} + +static const struct wdt_ops scu_wdt_ops = { + .reset = scu_wdt_reset, + .start = scu_wdt_start, + .stop = scu_wdt_stop, +}; + +static const struct udevice_id scu_wdt_ids[] = { + { .compatible = "siemens,scu-wdt" }, + { } +}; + +U_BOOT_DRIVER(scu_wdt) = { + .name = "scu_wdt", + .id = UCLASS_WDT, + .of_match = scu_wdt_ids, + .probe = scu_wdt_probe, + .ops = &scu_wdt_ops, +}; diff --git a/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi index 21fe194a576..014cf1805fb 100644 --- a/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi +++ b/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi @@ -124,6 +124,7 @@ }; mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + bootph-all; pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ diff --git a/env/Kconfig b/env/Kconfig index 031cf58186a..aaf0b1fe9ac 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -21,6 +21,19 @@ config ENV_SOURCE_FILE environment is assumed to come from the ad-hoc CFG_EXTRA_ENV_SETTINGS #define +config ENV_CALLBACK_LIST_STATIC + string "Static callbacks list" + default "" + help + The environment callbacks are associated with variables in a + static list. Define this list in the following format: + + entry = variable_name[:callback_name] + list = entry[,list] + + If the callback name is not specified, then the callback is deleted. + Spaces are also allowed anywhere in the list. + config SAVEENV def_bool y if CMD_SAVEENV @@ -23,6 +23,7 @@ #include <time.h> #include <ubifs_uboot.h> #include <btrfs.h> +#include <asm/cache.h> #include <asm/global_data.h> #include <asm/io.h> #include <div64.h> @@ -1001,6 +1002,9 @@ int fs_read_alloc(const char *fname, ulong size, uint align, void **bufp) char *buf; int ret; + if (!align) + align = ARCH_DMA_MINALIGN; + buf = memalign(align, size + 1); if (!buf) return log_msg_ret("buf", -ENOMEM); diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 70303acd558..8c619c1b74a 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -30,8 +30,6 @@ struct bd_info { unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ #ifdef CONFIG_ARM unsigned long bi_arm_freq; /* arm frequency */ unsigned long bi_dsp_freq; /* dsp core frequency */ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 1f61b2b6af6..4d95f3fd79b 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -95,7 +95,9 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 -/* DDR3 board total DDR is 1 GB */ +/* Set default values to the smallest DDR we have in capricorn modules + * Use it in case the system controller would return an error + */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ diff --git a/include/configs/deneb.h b/include/configs/deneb.h deleted file mode 100644 index f155bb8bf50..00000000000 --- a/include/configs/deneb.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 Siemens AG - * - */ - -#ifndef __DENEB_H -#define __DENEB_H - -#include "capricorn-common.h" - -/* DDR3 board total DDR is 2 GB */ -#undef PHYS_SDRAM_1_SIZE -#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ - -#endif /* __DENEB_H */ diff --git a/include/configs/khadas-vim3_android.h b/include/configs/khadas-vim3_android.h index fc89efb4c36..551ab51c881 100644 --- a/include/configs/khadas-vim3_android.h +++ b/include/configs/khadas-vim3_android.h @@ -24,7 +24,7 @@ "name=boot_a,size=64M,bootable,uuid=${uuid_gpt_boot_a};" \ "name=boot_b,size=64M,bootable,uuid=${uuid_gpt_boot_b};" \ "name=super,size=3072M,uuid=${uuid_gpt_super};" \ - "name=userdata,size=11282M,uuid=${uuid_gpt_userdata};" \ + "name=userdata,size=11218M,uuid=${uuid_gpt_userdata};" \ "name=rootfs,size=-,uuid=" ROOT_UUID #else #define PARTS_DEFAULT \ @@ -37,14 +37,31 @@ "name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \ "name=cache,size=256M,uuid=${uuid_gpt_cache};" \ "name=super,size=1792M,uuid=${uuid_gpt_super};" \ - "name=userdata,size=12786M,uuid=${uuid_gpt_userdata};" \ + "name=userdata,size=12722M,uuid=${uuid_gpt_userdata};" \ "name=rootfs,size=-,uuid=" ROOT_UUID #endif -#define EXTRA_ANDROID_ENV_SETTINGS \ - "board=vim3\0" \ - "board_name=vim3\0" \ +#define CFG_EXTRA_ENV_SETTINGS \ + "board=vim3\0" \ + "board_name=vim3\0" \ + "bootmeths=android\0" \ + "bootcmd=bootflow scan\0" \ + "adtb_idx=3\0" \ + "partitions=" PARTS_DEFAULT "\0" \ + "mmcdev=2\0" \ + "fastboot_raw_partition_bootloader=0x1 0xfff mmcpart 1\0" \ + "fastboot_raw_partition_bootenv=0x0 0xfff mmcpart 2\0" \ + "stdin=" STDIN_CFG "\0" \ + "stdout=" STDOUT_CFG "\0" \ + "stderr=" STDOUT_CFG "\0" \ + "dtboaddr=0x08200000\0" \ + "loadaddr=0x01080000\0" \ + "fdt_addr_r=0x01000000\0" \ + "scriptaddr=0x08000000\0" \ + "kernel_addr_r=0x01080000\0" \ + "pxefile_addr_r=0x01080000\0" \ + "ramdisk_addr_r=0x13000000\0" \ -#include <configs/meson64_android.h> +#include <configs/meson64.h> #endif /* __CONFIG_H */ diff --git a/include/configs/khadas-vim3l_android.h b/include/configs/khadas-vim3l_android.h index 5b2aed1cf62..1869249e7c9 100644 --- a/include/configs/khadas-vim3l_android.h +++ b/include/configs/khadas-vim3l_android.h @@ -24,7 +24,7 @@ "name=boot_a,size=64M,bootable,uuid=${uuid_gpt_boot_a};" \ "name=boot_b,size=64M,bootable,uuid=${uuid_gpt_boot_b};" \ "name=super,size=3072M,uuid=${uuid_gpt_super};" \ - "name=userdata,size=11282M,uuid=${uuid_gpt_userdata};" \ + "name=userdata,size=11218M,uuid=${uuid_gpt_userdata};" \ "name=rootfs,size=-,uuid=" ROOT_UUID #else #define PARTS_DEFAULT \ @@ -37,14 +37,31 @@ "name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \ "name=cache,size=256M,uuid=${uuid_gpt_cache};" \ "name=super,size=1792M,uuid=${uuid_gpt_super};" \ - "name=userdata,size=12786M,uuid=${uuid_gpt_userdata};" \ + "name=userdata,size=12722M,uuid=${uuid_gpt_userdata};" \ "name=rootfs,size=-,uuid=" ROOT_UUID #endif -#define EXTRA_ANDROID_ENV_SETTINGS \ - "board=vim3l\0" \ - "board_name=vim3l\0" \ +#define CFG_EXTRA_ENV_SETTINGS \ + "board=vim3l\0" \ + "board_name=vim3l\0" \ + "bootmeths=android\0" \ + "bootcmd=bootflow scan\0" \ + "adtb_idx=2\0" \ + "partitions=" PARTS_DEFAULT "\0" \ + "mmcdev=2\0" \ + "fastboot_raw_partition_bootloader=0x1 0xfff mmcpart 1\0" \ + "fastboot_raw_partition_bootenv=0x0 0xfff mmcpart 2\0" \ + "stdin=" STDIN_CFG "\0" \ + "stdout=" STDOUT_CFG "\0" \ + "stderr=" STDOUT_CFG "\0" \ + "dtboaddr=0x08200000\0" \ + "loadaddr=0x01080000\0" \ + "fdt_addr_r=0x01000000\0" \ + "scriptaddr=0x08000000\0" \ + "kernel_addr_r=0x01080000\0" \ + "pxefile_addr_r=0x01080000\0" \ + "ramdisk_addr_r=0x13000000\0" \ -#include <configs/meson64_android.h> +#include <configs/meson64.h> #endif /* __CONFIG_H */ diff --git a/include/configs/meson64_android.h b/include/configs/meson64_android.h index 77364bbf9cf..d6ef0a83a68 100644 --- a/include/configs/meson64_android.h +++ b/include/configs/meson64_android.h @@ -104,12 +104,6 @@ "elif test $board_name = sei610; then " \ "echo \" Reading DTB for sei610...\"; " \ "setenv dtb_index 1;" \ - "elif test $board_name = vim3l; then " \ - "echo \" Reading DTB for vim3l...\"; " \ - "setenv dtb_index 2;" \ - "elif test $board_name = vim3; then " \ - "echo \" Reading DTB for vim3...\"; " \ - "setenv dtb_index 3;" \ "else " \ "echo Error: Android boot is not supported for $board_name; " \ "exit; " \ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 6740ab2be3e..3bcc4c48dc8 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -82,7 +82,7 @@ "nor0=flash-0\0"\ "mtdparts=mtdparts=flash-0:"\ "256k(u-boot),256k(env),3m(kernel),"\ - "1m(romfs),1m(cramfs),-(jffs2)\0"\ + "1m(romfs),1m(cramfs),-(fs)\0"\ "nc=setenv stdout nc;"\ "setenv stdin nc\0" \ "serial=setenv stdout serial;"\ diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 0ae4fc55a97..8de930eab54 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -19,8 +19,11 @@ */ /* Initial RAM for temporary stack, global data */ #define CFG_SYS_INIT_RAM_SIZE 0x10000 +#define CFG_SYS_SRAM_BASE 0x80000000 +#define CFG_SYS_SRAM_SIZE 0x00080000 + #define CFG_SYS_INIT_RAM_ADDR \ - (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE) + (CFG_SYS_SRAM_BASE + CFG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE) /* SDRAM Configuration (for final code, data, stack, heap) */ #define CFG_SYS_SDRAM_BASE 0x88000000 diff --git a/include/configs/qcom.h b/include/configs/qcom.h index 5b5ebbd844d..9b41ab9e982 100644 --- a/include/configs/qcom.h +++ b/include/configs/qcom.h @@ -11,4 +11,9 @@ #define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +// 2a5aa852-b856-4d97-baa9-5c5f4421551f +#define QUALCOMM_UBOOT_BOOT_IMAGE_GUID \ + EFI_GUID(0x2a5aa852, 0xb856, 0x4d97, 0xba, 0xa9, \ + 0x5c, 0x5f, 0x44, 0x21, 0x55, 0x1f) + #endif diff --git a/include/dfu.h b/include/dfu.h index e25588c33cb..12f9dfcdfcd 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -24,6 +24,7 @@ enum dfu_device_type { DFU_DEV_SF, DFU_DEV_MTD, DFU_DEV_VIRT, + DFU_DEV_SCSI, }; enum dfu_layout { @@ -99,6 +100,19 @@ struct virt_internal_data { int dev_num; }; +struct scsi_internal_data { + int lun; + + /* RAW programming */ + unsigned int lba_start; + unsigned int lba_size; + unsigned int lba_blk_size; + + /* FAT/EXT */ + unsigned int dev; // Always 0??? + unsigned int part; +}; + #if defined(CONFIG_DFU_NAME_MAX_SIZE) #define DFU_NAME_SIZE CONFIG_DFU_NAME_MAX_SIZE #else @@ -126,6 +140,7 @@ struct dfu_entity { struct ram_internal_data ram; struct sf_internal_data sf; struct virt_internal_data virt; + struct scsi_internal_data scsi; } data; int (*get_medium_size)(struct dfu_entity *dfu, u64 *size); @@ -516,6 +531,18 @@ static inline int dfu_fill_entity_virt(struct dfu_entity *dfu, char *devstr, } #endif +#if CONFIG_IS_ENABLED(DFU_SCSI) +int dfu_fill_entity_scsi(struct dfu_entity *dfu, char *devstr, + char **argv, int argc); +#else +static inline int dfu_fill_entity_scsi(struct dfu_entity *dfu, char *devstr, + char **argv, int argc) +{ + puts("SCSI support not available!\n"); + return -1; +} +#endif + extern bool dfu_reinit_needed; extern bool dfu_alt_info_changed; diff --git a/include/dm/of_access.h b/include/dm/of_access.h index de740d44674..44143a5a391 100644 --- a/include/dm/of_access.h +++ b/include/dm/of_access.h @@ -454,6 +454,92 @@ static inline int of_property_count_strings(const struct device_node *np, } /** + * of_root_parse_phandle - Resolve a phandle property to a device_node pointer + * from a root node + * @root: Pointer to root device tree node (default root node if NULL) + * @np: Pointer to device node holding phandle property + * @phandle_name: Name of property holding a phandle value + * @index: For properties holding a table of phandles, this is the index into + * the table + * + * Return: + * the device_node pointer with refcount incremented. Use + * of_node_put() on it when done. + */ +struct device_node *of_root_parse_phandle(struct device_node *root, + const struct device_node *np, + const char *phandle_name, int index); + +/** + * of_root_parse_phandle_with_args() - Find a node pointed by phandle in a list + * from a root node + * + * @root: pointer to root device tree node (default root node if NULL) + * @np: pointer to a device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cells_count: Cell count to use if @cells_name is NULL + * @index: index of a phandle to parse out + * @out_args: optional pointer to output arguments structure (will be filled) + * Return: + * 0 on success (with @out_args filled out if not NULL), -ENOENT if + * @list_name does not exist, -EINVAL if a phandle was not found, + * @cells_name could not be found, the arguments were truncated or there + * were too many arguments. + * + * This function is useful to parse lists of phandles and their arguments. + * Returns 0 on success and fills out_args, on error returns appropriate + * errno value. + * + * Caller is responsible to call of_node_put() on the returned out_args->np + * pointer. + * + * Example: + * + * .. code-block:: + * + * phandle1: node1 { + * #list-cells = <2>; + * }; + * phandle2: node2 { + * #list-cells = <1>; + * }; + * node3 { + * list = <&phandle1 1 2 &phandle2 3>; + * }; + * + * To get a device_node of the `node2' node you may call this: + * of_root_parse_phandle_with_args(node3, "list", "#list-cells", 1, &args); + */ +int of_root_parse_phandle_with_args(struct device_node *root, + const struct device_node *np, + const char *list_name, const char *cells_name, + int cells_count, int index, + struct of_phandle_args *out_args); + +/** + * of_root_count_phandle_with_args() - Count the number of phandle in a list + * from a root node + * + * @root: pointer to root device tree node (default root node if NULL) + * @np: pointer to a device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cells_count: Cell count to use if @cells_name is NULL + * Return: + * number of phandle found, -ENOENT if @list_name does not exist, + * -EINVAL if a phandle was not found, @cells_name could not be found, + * the arguments were truncated or there were too many arguments. + * + * Returns number of phandle found on success, on error returns appropriate + * errno value. + */ +int of_root_count_phandle_with_args(struct device_node *root, + const struct device_node *np, + const char *list_name, const char *cells_name, + int cells_count); + +/** * of_parse_phandle - Resolve a phandle property to a device_node pointer * @np: Pointer to device node holding phandle property * @phandle_name: Name of property holding a phandle value diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 0787758926f..890f0e6cf40 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -848,6 +848,18 @@ int ofnode_read_string_list(ofnode node, const char *property, const char ***listp); /** + * ofnode_parse_phandle() - Resolve a phandle property to an ofnode + * + * @node: node to check + * @phandle_name: Name of property holding a phandle value + * @index: For properties holding a table of phandles, this is the index into + * the table + * Return: ofnode that the phandle points to or ofnode_null() on error. + */ +ofnode ofnode_parse_phandle(ofnode node, const char *phandle_name, + int index); + +/** * ofnode_parse_phandle_with_args() - Find a node pointed by phandle in a list * * This function is useful to parse lists of phandles and their arguments. @@ -910,6 +922,86 @@ int ofnode_count_phandle_with_args(ofnode node, const char *list_name, const char *cells_name, int cell_count); /** + * oftree_parse_phandle() - Resolve a phandle property to an ofnode + * from a root node + * + * @tree: device tree to use + * @node: node to check + * @phandle_name: Name of property holding a phandle value + * @index: For properties holding a table of phandles, this is the index into + * the table + * Return: ofnode that the phandle points to or ofnode_null() on error. + */ +ofnode oftree_parse_phandle(oftree tree, ofnode node, const char *phandle_name, + int index); + +/** + * oftree_parse_phandle_with_args() - Find a node pointed by phandle in a list + * from a root node + * + * This function is useful to parse lists of phandles and their arguments. + * Returns 0 on success and fills out_args, on error returns appropriate + * errno value. + * + * Caller is responsible to call of_node_put() on the returned out_args->np + * pointer. + * + * Example: + * + * .. code-block:: + * + * phandle1: node1 { + * #list-cells = <2>; + * }; + * phandle2: node2 { + * #list-cells = <1>; + * }; + * node3 { + * list = <&phandle1 1 2 &phandle2 3>; + * }; + * + * To get a device_node of the `node2' node you may call this: + * oftree_parse_phandle_with_args(node3, "list", "#list-cells", 0, 1, &args); + * + * @tree: device tree to use + * @node: device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cell_count: Cell count to use if @cells_name is NULL + * @index: index of a phandle to parse out + * @out_args: optional pointer to output arguments structure (will be filled) + * Return: + * 0 on success (with @out_args filled out if not NULL), -ENOENT if + * @list_name does not exist, -EINVAL if a phandle was not found, + * @cells_name could not be found, the arguments were truncated or there + * were too many arguments. + */ +int oftree_parse_phandle_with_args(oftree tree, ofnode node, const char *list_name, + const char *cells_name, int cell_count, + int index, + struct ofnode_phandle_args *out_args); + +/** + * oftree_count_phandle_with_args() - Count number of phandle in a list + * from a root node + * + * This function is useful to count phandles into a list. + * Returns number of phandle on success, on error returns appropriate + * errno value. + * + * @tree: device tree to use + * @node: device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @cell_count: Cell count to use if @cells_name is NULL + * Return: + * number of phandle on success, -ENOENT if @list_name does not exist, + * -EINVAL if a phandle was not found, @cells_name could not be found. + */ +int oftree_count_phandle_with_args(oftree tree, ofnode node, const char *list_name, + const char *cells_name, int cell_count); + +/** * ofnode_path() - find a node by full path * * This uses the control FDT. @@ -1629,6 +1721,21 @@ int ofnode_options_read_int(const char *prop_name, int default_val); const char *ofnode_options_read_str(const char *prop_name); /** + * ofnode_options_get_by_phandle() - Get a ofnode from phandle from the U-Boot options + * + * This reads a property from the /options/u-boot/ node of the devicetree. + * + * This only works with the control FDT. + * + * See dtschema/schemas/options/u-boot.yaml in dt-schema project for bindings + * + * @prop_name: property name to look up + * @nodep: pointer to ofnode where node is stored + * Return: 0, if found, or negative error if not + */ +int ofnode_options_get_by_phandle(const char *prop_name, ofnode *nodep); + +/** * ofnode_read_bootscript_address() - Read bootscr-address or bootscr-ram-offset * * @bootscr_address: pointer to 64bit address where bootscr-address property value diff --git a/include/dm/root.h b/include/dm/root.h index b2f30a842f5..5651b868c8b 100644 --- a/include/dm/root.h +++ b/include/dm/root.h @@ -167,8 +167,18 @@ int dm_uninit(void); * Return: 0 if OK, -ve on error */ int dm_remove_devices_flags(uint flags); + +/** + * dm_remove_devices_active - Call remove function of all active drivers heeding + * device dependencies as far as know, i.e. removing + * devices marked with DM_FLAG_VITAL last. + * + * All active devices will be removed + */ +void dm_remove_devices_active(void); #else static inline int dm_remove_devices_flags(uint flags) { return 0; } +static inline void dm_remove_devices_active(void) { } #endif /** diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h deleted file mode 100644 index 06f198ee762..00000000000 --- a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h +++ /dev/null @@ -1,168 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Jian Hu <jian.hu@amlogic.com> - * - * Copyright (c) 2023, SberDevices. All Rights Reserved. - * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> - */ - -#ifndef __A1_PERIPHERALS_CLKC_H -#define __A1_PERIPHERALS_CLKC_H - -#define CLKID_XTAL_IN 0 -#define CLKID_FIXPLL_IN 1 -#define CLKID_USB_PHY_IN 2 -#define CLKID_USB_CTRL_IN 3 -#define CLKID_HIFIPLL_IN 4 -#define CLKID_SYSPLL_IN 5 -#define CLKID_DDS_IN 6 -#define CLKID_SYS 7 -#define CLKID_CLKTREE 8 -#define CLKID_RESET_CTRL 9 -#define CLKID_ANALOG_CTRL 10 -#define CLKID_PWR_CTRL 11 -#define CLKID_PAD_CTRL 12 -#define CLKID_SYS_CTRL 13 -#define CLKID_TEMP_SENSOR 14 -#define CLKID_AM2AXI_DIV 15 -#define CLKID_SPICC_B 16 -#define CLKID_SPICC_A 17 -#define CLKID_MSR 18 -#define CLKID_AUDIO 19 -#define CLKID_JTAG_CTRL 20 -#define CLKID_SARADC_EN 21 -#define CLKID_PWM_EF 22 -#define CLKID_PWM_CD 23 -#define CLKID_PWM_AB 24 -#define CLKID_CEC 25 -#define CLKID_I2C_S 26 -#define CLKID_IR_CTRL 27 -#define CLKID_I2C_M_D 28 -#define CLKID_I2C_M_C 29 -#define CLKID_I2C_M_B 30 -#define CLKID_I2C_M_A 31 -#define CLKID_ACODEC 32 -#define CLKID_OTP 33 -#define CLKID_SD_EMMC_A 34 -#define CLKID_USB_PHY 35 -#define CLKID_USB_CTRL 36 -#define CLKID_SYS_DSPB 37 -#define CLKID_SYS_DSPA 38 -#define CLKID_DMA 39 -#define CLKID_IRQ_CTRL 40 -#define CLKID_NIC 41 -#define CLKID_GIC 42 -#define CLKID_UART_C 43 -#define CLKID_UART_B 44 -#define CLKID_UART_A 45 -#define CLKID_SYS_PSRAM 46 -#define CLKID_RSA 47 -#define CLKID_CORESIGHT 48 -#define CLKID_AM2AXI_VAD 49 -#define CLKID_AUDIO_VAD 50 -#define CLKID_AXI_DMC 51 -#define CLKID_AXI_PSRAM 52 -#define CLKID_RAMB 53 -#define CLKID_RAMA 54 -#define CLKID_AXI_SPIFC 55 -#define CLKID_AXI_NIC 56 -#define CLKID_AXI_DMA 57 -#define CLKID_CPU_CTRL 58 -#define CLKID_ROM 59 -#define CLKID_PROC_I2C 60 -#define CLKID_DSPA_SEL 61 -#define CLKID_DSPB_SEL 62 -#define CLKID_DSPA_EN 63 -#define CLKID_DSPA_EN_NIC 64 -#define CLKID_DSPB_EN 65 -#define CLKID_DSPB_EN_NIC 66 -#define CLKID_RTC 67 -#define CLKID_CECA_32K 68 -#define CLKID_CECB_32K 69 -#define CLKID_24M 70 -#define CLKID_12M 71 -#define CLKID_FCLK_DIV2_DIVN 72 -#define CLKID_GEN 73 -#define CLKID_SARADC_SEL 74 -#define CLKID_SARADC 75 -#define CLKID_PWM_A 76 -#define CLKID_PWM_B 77 -#define CLKID_PWM_C 78 -#define CLKID_PWM_D 79 -#define CLKID_PWM_E 80 -#define CLKID_PWM_F 81 -#define CLKID_SPICC 82 -#define CLKID_TS 83 -#define CLKID_SPIFC 84 -#define CLKID_USB_BUS 85 -#define CLKID_SD_EMMC 86 -#define CLKID_PSRAM 87 -#define CLKID_DMC 88 -#define CLKID_SYS_A_SEL 89 -#define CLKID_SYS_A_DIV 90 -#define CLKID_SYS_A 91 -#define CLKID_SYS_B_SEL 92 -#define CLKID_SYS_B_DIV 93 -#define CLKID_SYS_B 94 -#define CLKID_DSPA_A_SEL 95 -#define CLKID_DSPA_A_DIV 96 -#define CLKID_DSPA_A 97 -#define CLKID_DSPA_B_SEL 98 -#define CLKID_DSPA_B_DIV 99 -#define CLKID_DSPA_B 100 -#define CLKID_DSPB_A_SEL 101 -#define CLKID_DSPB_A_DIV 102 -#define CLKID_DSPB_A 103 -#define CLKID_DSPB_B_SEL 104 -#define CLKID_DSPB_B_DIV 105 -#define CLKID_DSPB_B 106 -#define CLKID_RTC_32K_IN 107 -#define CLKID_RTC_32K_DIV 108 -#define CLKID_RTC_32K_XTAL 109 -#define CLKID_RTC_32K_SEL 110 -#define CLKID_CECB_32K_IN 111 -#define CLKID_CECB_32K_DIV 112 -#define CLKID_CECB_32K_SEL_PRE 113 -#define CLKID_CECB_32K_SEL 114 -#define CLKID_CECA_32K_IN 115 -#define CLKID_CECA_32K_DIV 116 -#define CLKID_CECA_32K_SEL_PRE 117 -#define CLKID_CECA_32K_SEL 118 -#define CLKID_DIV2_PRE 119 -#define CLKID_24M_DIV2 120 -#define CLKID_GEN_SEL 121 -#define CLKID_GEN_DIV 122 -#define CLKID_SARADC_DIV 123 -#define CLKID_PWM_A_SEL 124 -#define CLKID_PWM_A_DIV 125 -#define CLKID_PWM_B_SEL 126 -#define CLKID_PWM_B_DIV 127 -#define CLKID_PWM_C_SEL 128 -#define CLKID_PWM_C_DIV 129 -#define CLKID_PWM_D_SEL 130 -#define CLKID_PWM_D_DIV 131 -#define CLKID_PWM_E_SEL 132 -#define CLKID_PWM_E_DIV 133 -#define CLKID_PWM_F_SEL 134 -#define CLKID_PWM_F_DIV 135 -#define CLKID_SPICC_SEL 136 -#define CLKID_SPICC_DIV 137 -#define CLKID_SPICC_SEL2 138 -#define CLKID_TS_DIV 139 -#define CLKID_SPIFC_SEL 140 -#define CLKID_SPIFC_DIV 141 -#define CLKID_SPIFC_SEL2 142 -#define CLKID_USB_BUS_SEL 143 -#define CLKID_USB_BUS_DIV 144 -#define CLKID_SD_EMMC_SEL 145 -#define CLKID_SD_EMMC_DIV 146 -#define CLKID_SD_EMMC_SEL2 147 -#define CLKID_PSRAM_SEL 148 -#define CLKID_PSRAM_DIV 149 -#define CLKID_PSRAM_SEL2 150 -#define CLKID_DMC_SEL 151 -#define CLKID_DMC_DIV 152 -#define CLKID_DMC_SEL2 153 - -#endif /* __A1_PERIPHERALS_CLKC_H */ diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h deleted file mode 100644 index 2b660c0f2c9..00000000000 --- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Jian Hu <jian.hu@amlogic.com> - * - * Copyright (c) 2023, SberDevices. All Rights Reserved. - * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> - */ - -#ifndef __A1_PLL_CLKC_H -#define __A1_PLL_CLKC_H - -#define CLKID_FIXED_PLL_DCO 0 -#define CLKID_FIXED_PLL 1 -#define CLKID_FCLK_DIV2_DIV 2 -#define CLKID_FCLK_DIV3_DIV 3 -#define CLKID_FCLK_DIV5_DIV 4 -#define CLKID_FCLK_DIV7_DIV 5 -#define CLKID_FCLK_DIV2 6 -#define CLKID_FCLK_DIV3 7 -#define CLKID_FCLK_DIV5 8 -#define CLKID_FCLK_DIV7 9 -#define CLKID_HIFI_PLL 10 - -#endif /* __A1_PLL_CLKC_H */ diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h deleted file mode 100644 index f561f5c5ef8..00000000000 --- a/include/dt-bindings/clock/axg-audio-clkc.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (c) 2018 Baylibre SAS. - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -#ifndef __AXG_AUDIO_CLKC_BINDINGS_H -#define __AXG_AUDIO_CLKC_BINDINGS_H - -#define AUD_CLKID_DDR_ARB 29 -#define AUD_CLKID_PDM 30 -#define AUD_CLKID_TDMIN_A 31 -#define AUD_CLKID_TDMIN_B 32 -#define AUD_CLKID_TDMIN_C 33 -#define AUD_CLKID_TDMIN_LB 34 -#define AUD_CLKID_TDMOUT_A 35 -#define AUD_CLKID_TDMOUT_B 36 -#define AUD_CLKID_TDMOUT_C 37 -#define AUD_CLKID_FRDDR_A 38 -#define AUD_CLKID_FRDDR_B 39 -#define AUD_CLKID_FRDDR_C 40 -#define AUD_CLKID_TODDR_A 41 -#define AUD_CLKID_TODDR_B 42 -#define AUD_CLKID_TODDR_C 43 -#define AUD_CLKID_LOOPBACK 44 -#define AUD_CLKID_SPDIFIN 45 -#define AUD_CLKID_SPDIFOUT 46 -#define AUD_CLKID_RESAMPLE 47 -#define AUD_CLKID_POWER_DETECT 48 -#define AUD_CLKID_MST_A_MCLK 49 -#define AUD_CLKID_MST_B_MCLK 50 -#define AUD_CLKID_MST_C_MCLK 51 -#define AUD_CLKID_MST_D_MCLK 52 -#define AUD_CLKID_MST_E_MCLK 53 -#define AUD_CLKID_MST_F_MCLK 54 -#define AUD_CLKID_SPDIFOUT_CLK 55 -#define AUD_CLKID_SPDIFIN_CLK 56 -#define AUD_CLKID_PDM_DCLK 57 -#define AUD_CLKID_PDM_SYSCLK 58 -#define AUD_CLKID_MST_A_SCLK 79 -#define AUD_CLKID_MST_B_SCLK 80 -#define AUD_CLKID_MST_C_SCLK 81 -#define AUD_CLKID_MST_D_SCLK 82 -#define AUD_CLKID_MST_E_SCLK 83 -#define AUD_CLKID_MST_F_SCLK 84 -#define AUD_CLKID_MST_A_LRCLK 86 -#define AUD_CLKID_MST_B_LRCLK 87 -#define AUD_CLKID_MST_C_LRCLK 88 -#define AUD_CLKID_MST_D_LRCLK 89 -#define AUD_CLKID_MST_E_LRCLK 90 -#define AUD_CLKID_MST_F_LRCLK 91 -#define AUD_CLKID_TDMIN_A_SCLK_SEL 116 -#define AUD_CLKID_TDMIN_B_SCLK_SEL 117 -#define AUD_CLKID_TDMIN_C_SCLK_SEL 118 -#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119 -#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120 -#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121 -#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122 -#define AUD_CLKID_TDMIN_A_SCLK 123 -#define AUD_CLKID_TDMIN_B_SCLK 124 -#define AUD_CLKID_TDMIN_C_SCLK 125 -#define AUD_CLKID_TDMIN_LB_SCLK 126 -#define AUD_CLKID_TDMOUT_A_SCLK 127 -#define AUD_CLKID_TDMOUT_B_SCLK 128 -#define AUD_CLKID_TDMOUT_C_SCLK 129 -#define AUD_CLKID_TDMIN_A_LRCLK 130 -#define AUD_CLKID_TDMIN_B_LRCLK 131 -#define AUD_CLKID_TDMIN_C_LRCLK 132 -#define AUD_CLKID_TDMIN_LB_LRCLK 133 -#define AUD_CLKID_TDMOUT_A_LRCLK 134 -#define AUD_CLKID_TDMOUT_B_LRCLK 135 -#define AUD_CLKID_TDMOUT_C_LRCLK 136 -#define AUD_CLKID_SPDIFOUT_B 151 -#define AUD_CLKID_SPDIFOUT_B_CLK 152 -#define AUD_CLKID_TDM_MCLK_PAD0 155 -#define AUD_CLKID_TDM_MCLK_PAD1 156 -#define AUD_CLKID_TDM_LRCLK_PAD0 157 -#define AUD_CLKID_TDM_LRCLK_PAD1 158 -#define AUD_CLKID_TDM_LRCLK_PAD2 159 -#define AUD_CLKID_TDM_SCLK_PAD0 160 -#define AUD_CLKID_TDM_SCLK_PAD1 161 -#define AUD_CLKID_TDM_SCLK_PAD2 162 -#define AUD_CLKID_TOP 163 -#define AUD_CLKID_TORAM 164 -#define AUD_CLKID_EQDRC 165 -#define AUD_CLKID_RESAMPLE_B 166 -#define AUD_CLKID_TOVAD 167 -#define AUD_CLKID_LOCKER 168 -#define AUD_CLKID_SPDIFIN_LB 169 -#define AUD_CLKID_FRDDR_D 170 -#define AUD_CLKID_TODDR_D 171 -#define AUD_CLKID_LOOPBACK_B 172 - -#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h deleted file mode 100644 index 93752ea107e..00000000000 --- a/include/dt-bindings/clock/axg-clkc.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Meson-AXG clock tree IDs - * - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - */ - -#ifndef __AXG_CLKC_H -#define __AXG_CLKC_H - -#define CLKID_SYS_PLL 0 -#define CLKID_FIXED_PLL 1 -#define CLKID_FCLK_DIV2 2 -#define CLKID_FCLK_DIV3 3 -#define CLKID_FCLK_DIV4 4 -#define CLKID_FCLK_DIV5 5 -#define CLKID_FCLK_DIV7 6 -#define CLKID_GP0_PLL 7 -#define CLKID_CLK81 10 -#define CLKID_MPLL0 11 -#define CLKID_MPLL1 12 -#define CLKID_MPLL2 13 -#define CLKID_MPLL3 14 -#define CLKID_DDR 15 -#define CLKID_AUDIO_LOCKER 16 -#define CLKID_MIPI_DSI_HOST 17 -#define CLKID_ISA 18 -#define CLKID_PL301 19 -#define CLKID_PERIPHS 20 -#define CLKID_SPICC0 21 -#define CLKID_I2C 22 -#define CLKID_RNG0 23 -#define CLKID_UART0 24 -#define CLKID_MIPI_DSI_PHY 25 -#define CLKID_SPICC1 26 -#define CLKID_PCIE_A 27 -#define CLKID_PCIE_B 28 -#define CLKID_HIU_IFACE 29 -#define CLKID_ASSIST_MISC 30 -#define CLKID_SD_EMMC_B 31 -#define CLKID_SD_EMMC_C 32 -#define CLKID_DMA 33 -#define CLKID_SPI 34 -#define CLKID_AUDIO 35 -#define CLKID_ETH 36 -#define CLKID_UART1 37 -#define CLKID_G2D 38 -#define CLKID_USB0 39 -#define CLKID_USB1 40 -#define CLKID_RESET 41 -#define CLKID_USB 42 -#define CLKID_AHB_ARB0 43 -#define CLKID_EFUSE 44 -#define CLKID_BOOT_ROM 45 -#define CLKID_AHB_DATA_BUS 46 -#define CLKID_AHB_CTRL_BUS 47 -#define CLKID_USB1_DDR_BRIDGE 48 -#define CLKID_USB0_DDR_BRIDGE 49 -#define CLKID_MMC_PCLK 50 -#define CLKID_VPU_INTR 51 -#define CLKID_SEC_AHB_AHB3_BRIDGE 52 -#define CLKID_GIC 53 -#define CLKID_AO_MEDIA_CPU 54 -#define CLKID_AO_AHB_SRAM 55 -#define CLKID_AO_AHB_BUS 56 -#define CLKID_AO_IFACE 57 -#define CLKID_AO_I2C 58 -#define CLKID_SD_EMMC_B_CLK0 59 -#define CLKID_SD_EMMC_C_CLK0 60 -#define CLKID_HIFI_PLL 69 -#define CLKID_PCIE_CML_EN0 79 -#define CLKID_PCIE_CML_EN1 80 -#define CLKID_GEN_CLK 84 -#define CLKID_VPU_0_SEL 92 -#define CLKID_VPU_0 93 -#define CLKID_VPU_1_SEL 95 -#define CLKID_VPU_1 96 -#define CLKID_VPU 97 -#define CLKID_VAPB_0_SEL 99 -#define CLKID_VAPB_0 100 -#define CLKID_VAPB_1_SEL 102 -#define CLKID_VAPB_1 103 -#define CLKID_VAPB_SEL 104 -#define CLKID_VAPB 105 -#define CLKID_VCLK 106 -#define CLKID_VCLK2 107 -#define CLKID_VCLK_DIV1 122 -#define CLKID_VCLK_DIV2 123 -#define CLKID_VCLK_DIV4 124 -#define CLKID_VCLK_DIV6 125 -#define CLKID_VCLK_DIV12 126 -#define CLKID_VCLK2_DIV1 127 -#define CLKID_VCLK2_DIV2 128 -#define CLKID_VCLK2_DIV4 129 -#define CLKID_VCLK2_DIV6 130 -#define CLKID_VCLK2_DIV12 131 -#define CLKID_CTS_ENCL 133 -#define CLKID_VDIN_MEAS 136 - -#endif /* __AXG_CLKC_H */ diff --git a/include/dt-bindings/clock/qcom,camcc-sdm845.h b/include/dt-bindings/clock/qcom,camcc-sdm845.h deleted file mode 100644 index 4f7a2d2320b..00000000000 --- a/include/dt-bindings/clock/qcom,camcc-sdm845.h +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H - -/* CAM_CC clock registers */ -#define CAM_CC_BPS_AHB_CLK 0 -#define CAM_CC_BPS_AREG_CLK 1 -#define CAM_CC_BPS_AXI_CLK 2 -#define CAM_CC_BPS_CLK 3 -#define CAM_CC_BPS_CLK_SRC 4 -#define CAM_CC_CAMNOC_ATB_CLK 5 -#define CAM_CC_CAMNOC_AXI_CLK 6 -#define CAM_CC_CCI_CLK 7 -#define CAM_CC_CCI_CLK_SRC 8 -#define CAM_CC_CPAS_AHB_CLK 9 -#define CAM_CC_CPHY_RX_CLK_SRC 10 -#define CAM_CC_CSI0PHYTIMER_CLK 11 -#define CAM_CC_CSI0PHYTIMER_CLK_SRC 12 -#define CAM_CC_CSI1PHYTIMER_CLK 13 -#define CAM_CC_CSI1PHYTIMER_CLK_SRC 14 -#define CAM_CC_CSI2PHYTIMER_CLK 15 -#define CAM_CC_CSI2PHYTIMER_CLK_SRC 16 -#define CAM_CC_CSI3PHYTIMER_CLK 17 -#define CAM_CC_CSI3PHYTIMER_CLK_SRC 18 -#define CAM_CC_CSIPHY0_CLK 19 -#define CAM_CC_CSIPHY1_CLK 20 -#define CAM_CC_CSIPHY2_CLK 21 -#define CAM_CC_CSIPHY3_CLK 22 -#define CAM_CC_FAST_AHB_CLK_SRC 23 -#define CAM_CC_FD_CORE_CLK 24 -#define CAM_CC_FD_CORE_CLK_SRC 25 -#define CAM_CC_FD_CORE_UAR_CLK 26 -#define CAM_CC_ICP_APB_CLK 27 -#define CAM_CC_ICP_ATB_CLK 28 -#define CAM_CC_ICP_CLK 29 -#define CAM_CC_ICP_CLK_SRC 30 -#define CAM_CC_ICP_CTI_CLK 31 -#define CAM_CC_ICP_TS_CLK 32 -#define CAM_CC_IFE_0_AXI_CLK 33 -#define CAM_CC_IFE_0_CLK 34 -#define CAM_CC_IFE_0_CLK_SRC 35 -#define CAM_CC_IFE_0_CPHY_RX_CLK 36 -#define CAM_CC_IFE_0_CSID_CLK 37 -#define CAM_CC_IFE_0_CSID_CLK_SRC 38 -#define CAM_CC_IFE_0_DSP_CLK 39 -#define CAM_CC_IFE_1_AXI_CLK 40 -#define CAM_CC_IFE_1_CLK 41 -#define CAM_CC_IFE_1_CLK_SRC 42 -#define CAM_CC_IFE_1_CPHY_RX_CLK 43 -#define CAM_CC_IFE_1_CSID_CLK 44 -#define CAM_CC_IFE_1_CSID_CLK_SRC 45 -#define CAM_CC_IFE_1_DSP_CLK 46 -#define CAM_CC_IFE_LITE_CLK 47 -#define CAM_CC_IFE_LITE_CLK_SRC 48 -#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49 -#define CAM_CC_IFE_LITE_CSID_CLK 50 -#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51 -#define CAM_CC_IPE_0_AHB_CLK 52 -#define CAM_CC_IPE_0_AREG_CLK 53 -#define CAM_CC_IPE_0_AXI_CLK 54 -#define CAM_CC_IPE_0_CLK 55 -#define CAM_CC_IPE_0_CLK_SRC 56 -#define CAM_CC_IPE_1_AHB_CLK 57 -#define CAM_CC_IPE_1_AREG_CLK 58 -#define CAM_CC_IPE_1_AXI_CLK 59 -#define CAM_CC_IPE_1_CLK 60 -#define CAM_CC_IPE_1_CLK_SRC 61 -#define CAM_CC_JPEG_CLK 62 -#define CAM_CC_JPEG_CLK_SRC 63 -#define CAM_CC_LRME_CLK 64 -#define CAM_CC_LRME_CLK_SRC 65 -#define CAM_CC_MCLK0_CLK 66 -#define CAM_CC_MCLK0_CLK_SRC 67 -#define CAM_CC_MCLK1_CLK 68 -#define CAM_CC_MCLK1_CLK_SRC 69 -#define CAM_CC_MCLK2_CLK 70 -#define CAM_CC_MCLK2_CLK_SRC 71 -#define CAM_CC_MCLK3_CLK 72 -#define CAM_CC_MCLK3_CLK_SRC 73 -#define CAM_CC_PLL0 74 -#define CAM_CC_PLL0_OUT_EVEN 75 -#define CAM_CC_PLL1 76 -#define CAM_CC_PLL1_OUT_EVEN 77 -#define CAM_CC_PLL2 78 -#define CAM_CC_PLL2_OUT_EVEN 79 -#define CAM_CC_PLL3 80 -#define CAM_CC_PLL3_OUT_EVEN 81 -#define CAM_CC_SLOW_AHB_CLK_SRC 82 -#define CAM_CC_SOC_AHB_CLK 83 -#define CAM_CC_SYS_TMR_CLK 84 - -/* CAM_CC Resets */ -#define TITAN_CAM_CC_CCI_BCR 0 -#define TITAN_CAM_CC_CPAS_BCR 1 -#define TITAN_CAM_CC_CSI0PHY_BCR 2 -#define TITAN_CAM_CC_CSI1PHY_BCR 3 -#define TITAN_CAM_CC_CSI2PHY_BCR 4 -#define TITAN_CAM_CC_MCLK0_BCR 5 -#define TITAN_CAM_CC_MCLK1_BCR 6 -#define TITAN_CAM_CC_MCLK2_BCR 7 -#define TITAN_CAM_CC_MCLK3_BCR 8 -#define TITAN_CAM_CC_TITAN_TOP_BCR 9 - -/* CAM_CC GDSCRs */ -#define BPS_GDSC 0 -#define IPE_0_GDSC 1 -#define IPE_1_GDSC 2 -#define IFE_0_GDSC 3 -#define IFE_1_GDSC 4 -#define TITAN_TOP_GDSC 5 - -#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h deleted file mode 100644 index 4016fd1d5b4..00000000000 --- a/include/dt-bindings/clock/qcom,dispcc-sdm845.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H - -/* DISP_CC clock registers */ -#define DISP_CC_MDSS_AHB_CLK 0 -#define DISP_CC_MDSS_AXI_CLK 1 -#define DISP_CC_MDSS_BYTE0_CLK 2 -#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 -#define DISP_CC_MDSS_BYTE0_INTF_CLK 4 -#define DISP_CC_MDSS_BYTE1_CLK 5 -#define DISP_CC_MDSS_BYTE1_CLK_SRC 6 -#define DISP_CC_MDSS_BYTE1_INTF_CLK 7 -#define DISP_CC_MDSS_ESC0_CLK 8 -#define DISP_CC_MDSS_ESC0_CLK_SRC 9 -#define DISP_CC_MDSS_ESC1_CLK 10 -#define DISP_CC_MDSS_ESC1_CLK_SRC 11 -#define DISP_CC_MDSS_MDP_CLK 12 -#define DISP_CC_MDSS_MDP_CLK_SRC 13 -#define DISP_CC_MDSS_MDP_LUT_CLK 14 -#define DISP_CC_MDSS_PCLK0_CLK 15 -#define DISP_CC_MDSS_PCLK0_CLK_SRC 16 -#define DISP_CC_MDSS_PCLK1_CLK 17 -#define DISP_CC_MDSS_PCLK1_CLK_SRC 18 -#define DISP_CC_MDSS_ROT_CLK 19 -#define DISP_CC_MDSS_ROT_CLK_SRC 20 -#define DISP_CC_MDSS_RSCC_AHB_CLK 21 -#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22 -#define DISP_CC_MDSS_VSYNC_CLK 23 -#define DISP_CC_MDSS_VSYNC_CLK_SRC 24 -#define DISP_CC_PLL0 25 -#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26 -#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27 -#define DISP_CC_MDSS_DP_AUX_CLK 28 -#define DISP_CC_MDSS_DP_AUX_CLK_SRC 29 -#define DISP_CC_MDSS_DP_CRYPTO_CLK 30 -#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 31 -#define DISP_CC_MDSS_DP_LINK_CLK 32 -#define DISP_CC_MDSS_DP_LINK_CLK_SRC 33 -#define DISP_CC_MDSS_DP_LINK_INTF_CLK 34 -#define DISP_CC_MDSS_DP_PIXEL1_CLK 35 -#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 36 -#define DISP_CC_MDSS_DP_PIXEL_CLK 37 -#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 38 - -/* DISP_CC Reset */ -#define DISP_CC_MDSS_RSCC_BCR 0 - -/* DISP_CC GDSCR */ -#define MDSS_GDSC 0 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h deleted file mode 100644 index 56303440618..00000000000 --- a/include/dt-bindings/clock/qcom,gcc-msm8916.h +++ /dev/null @@ -1,179 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2015 Linaro Limited - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H -#define _DT_BINDINGS_CLK_MSM_GCC_8916_H - -#define GPLL0 0 -#define GPLL0_VOTE 1 -#define BIMC_PLL 2 -#define BIMC_PLL_VOTE 3 -#define GPLL1 4 -#define GPLL1_VOTE 5 -#define GPLL2 6 -#define GPLL2_VOTE 7 -#define PCNOC_BFDCD_CLK_SRC 8 -#define SYSTEM_NOC_BFDCD_CLK_SRC 9 -#define CAMSS_AHB_CLK_SRC 10 -#define APSS_AHB_CLK_SRC 11 -#define CSI0_CLK_SRC 12 -#define CSI1_CLK_SRC 13 -#define GFX3D_CLK_SRC 14 -#define VFE0_CLK_SRC 15 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27 -#define BLSP1_UART1_APPS_CLK_SRC 28 -#define BLSP1_UART2_APPS_CLK_SRC 29 -#define CCI_CLK_SRC 30 -#define CAMSS_GP0_CLK_SRC 31 -#define CAMSS_GP1_CLK_SRC 32 -#define JPEG0_CLK_SRC 33 -#define MCLK0_CLK_SRC 34 -#define MCLK1_CLK_SRC 35 -#define CSI0PHYTIMER_CLK_SRC 36 -#define CSI1PHYTIMER_CLK_SRC 37 -#define CPP_CLK_SRC 38 -#define CRYPTO_CLK_SRC 39 -#define GP1_CLK_SRC 40 -#define GP2_CLK_SRC 41 -#define GP3_CLK_SRC 42 -#define BYTE0_CLK_SRC 43 -#define ESC0_CLK_SRC 44 -#define MDP_CLK_SRC 45 -#define PCLK0_CLK_SRC 46 -#define VSYNC_CLK_SRC 47 -#define PDM2_CLK_SRC 48 -#define SDCC1_APPS_CLK_SRC 49 -#define SDCC2_APPS_CLK_SRC 50 -#define APSS_TCU_CLK_SRC 51 -#define USB_HS_SYSTEM_CLK_SRC 52 -#define VCODEC0_CLK_SRC 53 -#define GCC_BLSP1_AHB_CLK 54 -#define GCC_BLSP1_SLEEP_CLK 55 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67 -#define GCC_BLSP1_UART1_APPS_CLK 68 -#define GCC_BLSP1_UART2_APPS_CLK 69 -#define GCC_BOOT_ROM_AHB_CLK 70 -#define GCC_CAMSS_CCI_AHB_CLK 71 -#define GCC_CAMSS_CCI_CLK 72 -#define GCC_CAMSS_CSI0_AHB_CLK 73 -#define GCC_CAMSS_CSI0_CLK 74 -#define GCC_CAMSS_CSI0PHY_CLK 75 -#define GCC_CAMSS_CSI0PIX_CLK 76 -#define GCC_CAMSS_CSI0RDI_CLK 77 -#define GCC_CAMSS_CSI1_AHB_CLK 78 -#define GCC_CAMSS_CSI1_CLK 79 -#define GCC_CAMSS_CSI1PHY_CLK 80 -#define GCC_CAMSS_CSI1PIX_CLK 81 -#define GCC_CAMSS_CSI1RDI_CLK 82 -#define GCC_CAMSS_CSI_VFE0_CLK 83 -#define GCC_CAMSS_GP0_CLK 84 -#define GCC_CAMSS_GP1_CLK 85 -#define GCC_CAMSS_ISPIF_AHB_CLK 86 -#define GCC_CAMSS_JPEG0_CLK 87 -#define GCC_CAMSS_JPEG_AHB_CLK 88 -#define GCC_CAMSS_JPEG_AXI_CLK 89 -#define GCC_CAMSS_MCLK0_CLK 90 -#define GCC_CAMSS_MCLK1_CLK 91 -#define GCC_CAMSS_MICRO_AHB_CLK 92 -#define GCC_CAMSS_CSI0PHYTIMER_CLK 93 -#define GCC_CAMSS_CSI1PHYTIMER_CLK 94 -#define GCC_CAMSS_AHB_CLK 95 -#define GCC_CAMSS_TOP_AHB_CLK 96 -#define GCC_CAMSS_CPP_AHB_CLK 97 -#define GCC_CAMSS_CPP_CLK 98 -#define GCC_CAMSS_VFE0_CLK 99 -#define GCC_CAMSS_VFE_AHB_CLK 100 -#define GCC_CAMSS_VFE_AXI_CLK 101 -#define GCC_CRYPTO_AHB_CLK 102 -#define GCC_CRYPTO_AXI_CLK 103 -#define GCC_CRYPTO_CLK 104 -#define GCC_OXILI_GMEM_CLK 105 -#define GCC_GP1_CLK 106 -#define GCC_GP2_CLK 107 -#define GCC_GP3_CLK 108 -#define GCC_MDSS_AHB_CLK 109 -#define GCC_MDSS_AXI_CLK 110 -#define GCC_MDSS_BYTE0_CLK 111 -#define GCC_MDSS_ESC0_CLK 112 -#define GCC_MDSS_MDP_CLK 113 -#define GCC_MDSS_PCLK0_CLK 114 -#define GCC_MDSS_VSYNC_CLK 115 -#define GCC_MSS_CFG_AHB_CLK 116 -#define GCC_OXILI_AHB_CLK 117 -#define GCC_OXILI_GFX3D_CLK 118 -#define GCC_PDM2_CLK 119 -#define GCC_PDM_AHB_CLK 120 -#define GCC_PRNG_AHB_CLK 121 -#define GCC_SDCC1_AHB_CLK 122 -#define GCC_SDCC1_APPS_CLK 123 -#define GCC_SDCC2_AHB_CLK 124 -#define GCC_SDCC2_APPS_CLK 125 -#define GCC_GTCU_AHB_CLK 126 -#define GCC_JPEG_TBU_CLK 127 -#define GCC_MDP_TBU_CLK 128 -#define GCC_SMMU_CFG_CLK 129 -#define GCC_VENUS_TBU_CLK 130 -#define GCC_VFE_TBU_CLK 131 -#define GCC_USB2A_PHY_SLEEP_CLK 132 -#define GCC_USB_HS_AHB_CLK 133 -#define GCC_USB_HS_SYSTEM_CLK 134 -#define GCC_VENUS0_AHB_CLK 135 -#define GCC_VENUS0_AXI_CLK 136 -#define GCC_VENUS0_VCODEC0_CLK 137 -#define BIMC_DDR_CLK_SRC 138 -#define GCC_APSS_TCU_CLK 139 -#define GCC_GFX_TCU_CLK 140 -#define BIMC_GPU_CLK_SRC 141 -#define GCC_BIMC_GFX_CLK 142 -#define GCC_BIMC_GPU_CLK 143 -#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144 -#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145 -#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146 -#define ULTAUDIO_XO_CLK_SRC 147 -#define ULTAUDIO_AHBFABRIC_CLK_SRC 148 -#define CODEC_DIGCODEC_CLK_SRC 149 -#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150 -#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151 -#define GCC_ULTAUDIO_AVSYNC_XO_CLK 152 -#define GCC_ULTAUDIO_STC_XO_CLK 153 -#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154 -#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155 -#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156 -#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157 -#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158 -#define GCC_CODEC_DIGCODEC_CLK 159 -#define GCC_MSS_Q6_BIMC_AXI_CLK 160 - -/* Indexes for GDSCs */ -#define BIMC_GDSC 0 -#define VENUS_GDSC 1 -#define MDSS_GDSC 2 -#define JPEG_GDSC 3 -#define VFE_GDSC 4 -#define OXILI_GDSC 5 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h deleted file mode 100644 index de5c36c7800..00000000000 --- a/include/dt-bindings/clock/qcom,gcc-msm8996.h +++ /dev/null @@ -1,361 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H -#define _DT_BINDINGS_CLK_MSM_GCC_8996_H - -#define GPLL0_EARLY 0 -#define GPLL0 1 -#define GPLL1_EARLY 2 -#define GPLL1 3 -#define GPLL2_EARLY 4 -#define GPLL2 5 -#define GPLL3_EARLY 6 -#define GPLL3 7 -#define GPLL4_EARLY 8 -#define GPLL4 9 -#define SYSTEM_NOC_CLK_SRC 10 -/* U-Boot: KConfig check in CI erroneously picks this up, it's unused - * anyway so comment it out for now - */ -//#define CONFIG _NOC_CLK_SRC 11 -#define PERIPH_NOC_CLK_SRC 12 -#define MMSS_BIMC_GFX_CLK_SRC 13 -#define USB30_MASTER_CLK_SRC 14 -#define USB30_MOCK_UTMI_CLK_SRC 15 -#define USB3_PHY_AUX_CLK_SRC 16 -#define USB20_MASTER_CLK_SRC 17 -#define USB20_MOCK_UTMI_CLK_SRC 18 -#define SDCC1_APPS_CLK_SRC 19 -#define SDCC1_ICE_CORE_CLK_SRC 20 -#define SDCC2_APPS_CLK_SRC 21 -#define SDCC3_APPS_CLK_SRC 22 -#define SDCC4_APPS_CLK_SRC 23 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 24 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 25 -#define BLSP1_UART1_APPS_CLK_SRC 26 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 28 -#define BLSP1_UART2_APPS_CLK_SRC 29 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 30 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 -#define BLSP1_UART3_APPS_CLK_SRC 32 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 33 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 34 -#define BLSP1_UART4_APPS_CLK_SRC 35 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 37 -#define BLSP1_UART5_APPS_CLK_SRC 38 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 39 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 40 -#define BLSP1_UART6_APPS_CLK_SRC 41 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 42 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 43 -#define BLSP2_UART1_APPS_CLK_SRC 44 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 46 -#define BLSP2_UART2_APPS_CLK_SRC 47 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 48 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 -#define BLSP2_UART3_APPS_CLK_SRC 50 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 51 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 52 -#define BLSP2_UART4_APPS_CLK_SRC 53 -#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 -#define BLSP2_QUP5_I2C_APPS_CLK_SRC 55 -#define BLSP2_UART5_APPS_CLK_SRC 56 -#define BLSP2_QUP6_SPI_APPS_CLK_SRC 57 -#define BLSP2_QUP6_I2C_APPS_CLK_SRC 58 -#define BLSP2_UART6_APPS_CLK_SRC 59 -#define PDM2_CLK_SRC 60 -#define TSIF_REF_CLK_SRC 61 -#define CE1_CLK_SRC 62 -#define GCC_SLEEP_CLK_SRC 63 -#define BIMC_CLK_SRC 64 -#define HMSS_AHB_CLK_SRC 65 -#define BIMC_HMSS_AXI_CLK_SRC 66 -#define HMSS_RBCPR_CLK_SRC 67 -#define HMSS_GPLL0_CLK_SRC 68 -#define GP1_CLK_SRC 69 -#define GP2_CLK_SRC 70 -#define GP3_CLK_SRC 71 -#define PCIE_AUX_CLK_SRC 72 -#define UFS_AXI_CLK_SRC 73 -#define UFS_ICE_CORE_CLK_SRC 74 -#define QSPI_SER_CLK_SRC 75 -#define GCC_SYS_NOC_AXI_CLK 76 -#define GCC_SYS_NOC_HMSS_AHB_CLK 77 -#define GCC_SNOC_CNOC_AHB_CLK 78 -#define GCC_SNOC_PNOC_AHB_CLK 79 -#define GCC_SYS_NOC_AT_CLK 80 -#define GCC_SYS_NOC_USB3_AXI_CLK 81 -#define GCC_SYS_NOC_UFS_AXI_CLK 82 -#define GCC_CFG_NOC_AHB_CLK 83 -#define GCC_PERIPH_NOC_AHB_CLK 84 -#define GCC_PERIPH_NOC_USB20_AHB_CLK 85 -#define GCC_TIC_CLK 86 -#define GCC_IMEM_AXI_CLK 87 -#define GCC_MMSS_SYS_NOC_AXI_CLK 88 -#define GCC_MMSS_NOC_CFG_AHB_CLK 89 -#define GCC_MMSS_BIMC_GFX_CLK 90 -#define GCC_USB30_MASTER_CLK 91 -#define GCC_USB30_SLEEP_CLK 92 -#define GCC_USB30_MOCK_UTMI_CLK 93 -#define GCC_USB3_PHY_AUX_CLK 94 -#define GCC_USB3_PHY_PIPE_CLK 95 -#define GCC_USB20_MASTER_CLK 96 -#define GCC_USB20_SLEEP_CLK 97 -#define GCC_USB20_MOCK_UTMI_CLK 98 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99 -#define GCC_SDCC1_APPS_CLK 100 -#define GCC_SDCC1_AHB_CLK 101 -#define GCC_SDCC1_ICE_CORE_CLK 102 -#define GCC_SDCC2_APPS_CLK 103 -#define GCC_SDCC2_AHB_CLK 104 -#define GCC_SDCC3_APPS_CLK 105 -#define GCC_SDCC3_AHB_CLK 106 -#define GCC_SDCC4_APPS_CLK 107 -#define GCC_SDCC4_AHB_CLK 108 -#define GCC_BLSP1_AHB_CLK 109 -#define GCC_BLSP1_SLEEP_CLK 110 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 111 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 112 -#define GCC_BLSP1_UART1_APPS_CLK 113 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 114 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 115 -#define GCC_BLSP1_UART2_APPS_CLK 116 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 117 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 118 -#define GCC_BLSP1_UART3_APPS_CLK 119 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 120 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 121 -#define GCC_BLSP1_UART4_APPS_CLK 122 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 123 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 124 -#define GCC_BLSP1_UART5_APPS_CLK 125 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 126 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 127 -#define GCC_BLSP1_UART6_APPS_CLK 128 -#define GCC_BLSP2_AHB_CLK 129 -#define GCC_BLSP2_SLEEP_CLK 130 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 131 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 132 -#define GCC_BLSP2_UART1_APPS_CLK 133 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 134 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 135 -#define GCC_BLSP2_UART2_APPS_CLK 136 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 137 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 138 -#define GCC_BLSP2_UART3_APPS_CLK 139 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 140 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 141 -#define GCC_BLSP2_UART4_APPS_CLK 142 -#define GCC_BLSP2_QUP5_SPI_APPS_CLK 143 -#define GCC_BLSP2_QUP5_I2C_APPS_CLK 144 -#define GCC_BLSP2_UART5_APPS_CLK 145 -#define GCC_BLSP2_QUP6_SPI_APPS_CLK 146 -#define GCC_BLSP2_QUP6_I2C_APPS_CLK 147 -#define GCC_BLSP2_UART6_APPS_CLK 148 -#define GCC_PDM_AHB_CLK 149 -#define GCC_PDM_XO4_CLK 150 -#define GCC_PDM2_CLK 151 -#define GCC_PRNG_AHB_CLK 152 -#define GCC_TSIF_AHB_CLK 153 -#define GCC_TSIF_REF_CLK 154 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 155 -#define GCC_TCSR_AHB_CLK 156 -#define GCC_BOOT_ROM_AHB_CLK 157 -#define GCC_MSG_RAM_AHB_CLK 158 -#define GCC_TLMM_AHB_CLK 159 -#define GCC_TLMM_CLK 160 -#define GCC_MPM_AHB_CLK 161 -#define GCC_SPMI_SER_CLK 162 -#define GCC_SPMI_CNOC_AHB_CLK 163 -#define GCC_CE1_CLK 164 -#define GCC_CE1_AXI_CLK 165 -#define GCC_CE1_AHB_CLK 166 -#define GCC_BIMC_HMSS_AXI_CLK 167 -#define GCC_BIMC_GFX_CLK 168 -#define GCC_HMSS_AHB_CLK 169 -#define GCC_HMSS_SLV_AXI_CLK 170 -#define GCC_HMSS_MSTR_AXI_CLK 171 -#define GCC_HMSS_RBCPR_CLK 172 -#define GCC_GP1_CLK 173 -#define GCC_GP2_CLK 174 -#define GCC_GP3_CLK 175 -#define GCC_PCIE_0_SLV_AXI_CLK 176 -#define GCC_PCIE_0_MSTR_AXI_CLK 177 -#define GCC_PCIE_0_CFG_AHB_CLK 178 -#define GCC_PCIE_0_AUX_CLK 179 -#define GCC_PCIE_0_PIPE_CLK 180 -#define GCC_PCIE_1_SLV_AXI_CLK 181 -#define GCC_PCIE_1_MSTR_AXI_CLK 182 -#define GCC_PCIE_1_CFG_AHB_CLK 183 -#define GCC_PCIE_1_AUX_CLK 184 -#define GCC_PCIE_1_PIPE_CLK 185 -#define GCC_PCIE_2_SLV_AXI_CLK 186 -#define GCC_PCIE_2_MSTR_AXI_CLK 187 -#define GCC_PCIE_2_CFG_AHB_CLK 188 -#define GCC_PCIE_2_AUX_CLK 189 -#define GCC_PCIE_2_PIPE_CLK 190 -#define GCC_PCIE_PHY_CFG_AHB_CLK 191 -#define GCC_PCIE_PHY_AUX_CLK 192 -#define GCC_UFS_AXI_CLK 193 -#define GCC_UFS_AHB_CLK 194 -#define GCC_UFS_TX_CFG_CLK 195 -#define GCC_UFS_RX_CFG_CLK 196 -#define GCC_UFS_TX_SYMBOL_0_CLK 197 -#define GCC_UFS_RX_SYMBOL_0_CLK 198 -#define GCC_UFS_RX_SYMBOL_1_CLK 199 -#define GCC_UFS_UNIPRO_CORE_CLK 200 -#define GCC_UFS_ICE_CORE_CLK 201 -#define GCC_UFS_SYS_CLK_CORE_CLK 202 -#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203 -#define GCC_AGGRE0_SNOC_AXI_CLK 204 -#define GCC_AGGRE0_CNOC_AHB_CLK 205 -#define GCC_SMMU_AGGRE0_AXI_CLK 206 -#define GCC_SMMU_AGGRE0_AHB_CLK 207 -#define GCC_AGGRE1_PNOC_AHB_CLK 208 -#define GCC_AGGRE2_UFS_AXI_CLK 209 -#define GCC_AGGRE2_USB3_AXI_CLK 210 -#define GCC_QSPI_AHB_CLK 211 -#define GCC_QSPI_SER_CLK 212 -#define GCC_USB3_CLKREF_CLK 213 -#define GCC_HDMI_CLKREF_CLK 214 -#define GCC_UFS_CLKREF_CLK 215 -#define GCC_PCIE_CLKREF_CLK 216 -#define GCC_RX2_USB2_CLKREF_CLK 217 -#define GCC_RX1_USB2_CLKREF_CLK 218 -#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219 -#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220 -#define GCC_EDP_CLKREF_CLK 221 -#define GCC_MSS_CFG_AHB_CLK 222 -#define GCC_MSS_Q6_BIMC_AXI_CLK 223 -#define GCC_MSS_SNOC_AXI_CLK 224 -#define GCC_MSS_MNOC_BIMC_AXI_CLK 225 -#define GCC_DCC_AHB_CLK 226 -#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227 -#define GCC_MMSS_GPLL0_DIV_CLK 228 -#define GCC_MSS_GPLL0_DIV_CLK 229 - -#define GCC_SYSTEM_NOC_BCR 0 -#define GCC_CONFIG_NOC_BCR 1 -#define GCC_PERIPH_NOC_BCR 2 -#define GCC_IMEM_BCR 3 -#define GCC_MMSS_BCR 4 -#define GCC_PIMEM_BCR 5 -#define GCC_QDSS_BCR 6 -#define GCC_USB_30_BCR 7 -#define GCC_USB_20_BCR 8 -#define GCC_QUSB2PHY_PRIM_BCR 9 -#define GCC_QUSB2PHY_SEC_BCR 10 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 11 -#define GCC_SDCC1_BCR 12 -#define GCC_SDCC2_BCR 13 -#define GCC_SDCC3_BCR 14 -#define GCC_SDCC4_BCR 15 -#define GCC_BLSP1_BCR 16 -#define GCC_BLSP1_QUP1_BCR 17 -#define GCC_BLSP1_UART1_BCR 18 -#define GCC_BLSP1_QUP2_BCR 19 -#define GCC_BLSP1_UART2_BCR 20 -#define GCC_BLSP1_QUP3_BCR 21 -#define GCC_BLSP1_UART3_BCR 22 -#define GCC_BLSP1_QUP4_BCR 23 -#define GCC_BLSP1_UART4_BCR 24 -#define GCC_BLSP1_QUP5_BCR 25 -#define GCC_BLSP1_UART5_BCR 26 -#define GCC_BLSP1_QUP6_BCR 27 -#define GCC_BLSP1_UART6_BCR 28 -#define GCC_BLSP2_BCR 29 -#define GCC_BLSP2_QUP1_BCR 30 -#define GCC_BLSP2_UART1_BCR 31 -#define GCC_BLSP2_QUP2_BCR 32 -#define GCC_BLSP2_UART2_BCR 33 -#define GCC_BLSP2_QUP3_BCR 34 -#define GCC_BLSP2_UART3_BCR 35 -#define GCC_BLSP2_QUP4_BCR 36 -#define GCC_BLSP2_UART4_BCR 37 -#define GCC_BLSP2_QUP5_BCR 38 -#define GCC_BLSP2_UART5_BCR 39 -#define GCC_BLSP2_QUP6_BCR 40 -#define GCC_BLSP2_UART6_BCR 41 -#define GCC_PDM_BCR 42 -#define GCC_PRNG_BCR 43 -#define GCC_TSIF_BCR 44 -#define GCC_TCSR_BCR 45 -#define GCC_BOOT_ROM_BCR 46 -#define GCC_MSG_RAM_BCR 47 -#define GCC_TLMM_BCR 48 -#define GCC_MPM_BCR 49 -#define GCC_SEC_CTRL_BCR 50 -#define GCC_SPMI_BCR 51 -#define GCC_SPDM_BCR 52 -#define GCC_CE1_BCR 53 -#define GCC_BIMC_BCR 54 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 55 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 -#define GCC_SNOC_BUS_TIMEOUT1_BCR 57 -#define GCC_SNOC_BUS_TIMEOUT3_BCR 58 -#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59 -#define GCC_PNOC_BUS_TIMEOUT0_BCR 60 -#define GCC_PNOC_BUS_TIMEOUT1_BCR 61 -#define GCC_PNOC_BUS_TIMEOUT2_BCR 62 -#define GCC_PNOC_BUS_TIMEOUT3_BCR 63 -#define GCC_PNOC_BUS_TIMEOUT4_BCR 64 -#define GCC_CNOC_BUS_TIMEOUT0_BCR 65 -#define GCC_CNOC_BUS_TIMEOUT1_BCR 66 -#define GCC_CNOC_BUS_TIMEOUT2_BCR 67 -#define GCC_CNOC_BUS_TIMEOUT3_BCR 68 -#define GCC_CNOC_BUS_TIMEOUT4_BCR 69 -#define GCC_CNOC_BUS_TIMEOUT5_BCR 70 -#define GCC_CNOC_BUS_TIMEOUT6_BCR 71 -#define GCC_CNOC_BUS_TIMEOUT7_BCR 72 -#define GCC_CNOC_BUS_TIMEOUT8_BCR 73 -#define GCC_CNOC_BUS_TIMEOUT9_BCR 74 -#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75 -#define GCC_APB2JTAG_BCR 76 -#define GCC_RBCPR_CX_BCR 77 -#define GCC_RBCPR_MX_BCR 78 -#define GCC_PCIE_0_BCR 79 -#define GCC_PCIE_0_PHY_BCR 80 -#define GCC_PCIE_1_BCR 81 -#define GCC_PCIE_1_PHY_BCR 82 -#define GCC_PCIE_2_BCR 83 -#define GCC_PCIE_2_PHY_BCR 84 -#define GCC_PCIE_PHY_BCR 85 -#define GCC_DCD_BCR 86 -#define GCC_OBT_ODT_BCR 87 -#define GCC_UFS_BCR 88 -#define GCC_SSC_BCR 89 -#define GCC_VS_BCR 90 -#define GCC_AGGRE0_NOC_BCR 91 -#define GCC_AGGRE1_NOC_BCR 92 -#define GCC_AGGRE2_NOC_BCR 93 -#define GCC_DCC_BCR 94 -#define GCC_IPA_BCR 95 -#define GCC_QSPI_BCR 96 -#define GCC_SKL_BCR 97 -#define GCC_MSMPU_BCR 98 -#define GCC_MSS_Q6_BCR 99 -#define GCC_QREFS_VBG_CAL_BCR 100 -#define GCC_PCIE_PHY_COM_BCR 101 -#define GCC_PCIE_PHY_COM_NOCSR_BCR 102 -#define GCC_USB3_PHY_BCR 103 -#define GCC_USB3PHY_PHY_BCR 104 -#define GCC_MSS_RESTART 105 - -/* Indexes for GDSCs */ -#define AGGRE0_NOC_GDSC 0 -#define HLOS1_VOTE_AGGRE0_NOC_GDSC 1 -#define HLOS1_VOTE_LPASS_ADSP_GDSC 2 -#define HLOS1_VOTE_LPASS_CORE_GDSC 3 -#define USB30_GDSC 4 -#define PCIE0_GDSC 5 -#define PCIE1_GDSC 6 -#define PCIE2_GDSC 7 -#define UFS_GDSC 8 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h deleted file mode 100644 index bc305154334..00000000000 --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h +++ /dev/null @@ -1,180 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H -#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H - -#define GCC_APSS_AHB_CLK_SRC 0 -#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1 -#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10 -#define GCC_BLSP1_UART0_APPS_CLK_SRC 11 -#define GCC_BLSP1_UART1_APPS_CLK_SRC 12 -#define GCC_BLSP1_UART2_APPS_CLK_SRC 13 -#define GCC_BLSP1_UART3_APPS_CLK_SRC 14 -#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15 -#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16 -#define GCC_BLSP2_UART0_APPS_CLK_SRC 17 -#define GCC_BYTE0_CLK_SRC 18 -#define GCC_EMAC_CLK_SRC 19 -#define GCC_EMAC_PTP_CLK_SRC 20 -#define GCC_ESC0_CLK_SRC 21 -#define GCC_APSS_AHB_CLK 22 -#define GCC_APSS_AXI_CLK 23 -#define GCC_BIMC_APSS_AXI_CLK 24 -#define GCC_BIMC_GFX_CLK 25 -#define GCC_BIMC_MDSS_CLK 26 -#define GCC_BLSP1_AHB_CLK 27 -#define GCC_BLSP1_QUP0_I2C_APPS_CLK 28 -#define GCC_BLSP1_QUP0_SPI_APPS_CLK 29 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 30 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 31 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 32 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 33 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 34 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 35 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 36 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 37 -#define GCC_BLSP1_UART0_APPS_CLK 38 -#define GCC_BLSP1_UART1_APPS_CLK 39 -#define GCC_BLSP1_UART2_APPS_CLK 40 -#define GCC_BLSP1_UART3_APPS_CLK 41 -#define GCC_BLSP2_AHB_CLK 42 -#define GCC_BLSP2_QUP0_I2C_APPS_CLK 43 -#define GCC_BLSP2_QUP0_SPI_APPS_CLK 44 -#define GCC_BLSP2_UART0_APPS_CLK 45 -#define GCC_BOOT_ROM_AHB_CLK 46 -#define GCC_DCC_CLK 47 -#define GCC_GENI_IR_H_CLK 48 -#define GCC_ETH_AXI_CLK 49 -#define GCC_ETH_PTP_CLK 50 -#define GCC_ETH_RGMII_CLK 51 -#define GCC_ETH_SLAVE_AHB_CLK 52 -#define GCC_GENI_IR_S_CLK 53 -#define GCC_GP1_CLK 54 -#define GCC_GP2_CLK 55 -#define GCC_GP3_CLK 56 -#define GCC_MDSS_AHB_CLK 57 -#define GCC_MDSS_AXI_CLK 58 -#define GCC_MDSS_BYTE0_CLK 59 -#define GCC_MDSS_ESC0_CLK 60 -#define GCC_MDSS_HDMI_APP_CLK 61 -#define GCC_MDSS_HDMI_PCLK_CLK 62 -#define GCC_MDSS_MDP_CLK 63 -#define GCC_MDSS_PCLK0_CLK 64 -#define GCC_MDSS_VSYNC_CLK 65 -#define GCC_OXILI_AHB_CLK 66 -#define GCC_OXILI_GFX3D_CLK 67 -#define GCC_PCIE_0_AUX_CLK 68 -#define GCC_PCIE_0_CFG_AHB_CLK 69 -#define GCC_PCIE_0_MSTR_AXI_CLK 70 -#define GCC_PCIE_0_PIPE_CLK 71 -#define GCC_PCIE_0_SLV_AXI_CLK 72 -#define GCC_PCNOC_USB2_CLK 73 -#define GCC_PCNOC_USB3_CLK 74 -#define GCC_PDM2_CLK 75 -#define GCC_PDM_AHB_CLK 76 -#define GCC_VSYNC_CLK_SRC 77 -#define GCC_PRNG_AHB_CLK 78 -#define GCC_PWM0_XO512_CLK 79 -#define GCC_PWM1_XO512_CLK 80 -#define GCC_PWM2_XO512_CLK 81 -#define GCC_SDCC1_AHB_CLK 82 -#define GCC_SDCC1_APPS_CLK 83 -#define GCC_SDCC1_ICE_CORE_CLK 84 -#define GCC_SDCC2_AHB_CLK 85 -#define GCC_SDCC2_APPS_CLK 86 -#define GCC_SYS_NOC_USB3_CLK 87 -#define GCC_USB20_MOCK_UTMI_CLK 88 -#define GCC_USB2A_PHY_SLEEP_CLK 89 -#define GCC_USB30_MASTER_CLK 90 -#define GCC_USB30_MOCK_UTMI_CLK 91 -#define GCC_USB30_SLEEP_CLK 92 -#define GCC_USB3_PHY_AUX_CLK 93 -#define GCC_USB3_PHY_PIPE_CLK 94 -#define GCC_USB_HS_PHY_CFG_AHB_CLK 95 -#define GCC_USB_HS_SYSTEM_CLK 96 -#define GCC_GFX3D_CLK_SRC 97 -#define GCC_GP1_CLK_SRC 98 -#define GCC_GP2_CLK_SRC 99 -#define GCC_GP3_CLK_SRC 100 -#define GCC_GPLL0_OUT_MAIN 101 -#define GCC_GPLL1_OUT_MAIN 102 -#define GCC_GPLL3_OUT_MAIN 103 -#define GCC_GPLL4_OUT_MAIN 104 -#define GCC_HDMI_APP_CLK_SRC 105 -#define GCC_HDMI_PCLK_CLK_SRC 106 -#define GCC_MDP_CLK_SRC 107 -#define GCC_PCIE_0_AUX_CLK_SRC 108 -#define GCC_PCIE_0_PIPE_CLK_SRC 109 -#define GCC_PCLK0_CLK_SRC 110 -#define GCC_PDM2_CLK_SRC 111 -#define GCC_SDCC1_APPS_CLK_SRC 112 -#define GCC_SDCC1_ICE_CORE_CLK_SRC 113 -#define GCC_SDCC2_APPS_CLK_SRC 114 -#define GCC_USB20_MOCK_UTMI_CLK_SRC 115 -#define GCC_USB30_MASTER_CLK_SRC 116 -#define GCC_USB30_MOCK_UTMI_CLK_SRC 117 -#define GCC_USB3_PHY_AUX_CLK_SRC 118 -#define GCC_USB_HS_SYSTEM_CLK_SRC 119 -#define GCC_GPLL0_AO_CLK_SRC 120 -#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122 -#define GCC_GPLL0_AO_OUT_MAIN 123 -#define GCC_GPLL0_SLEEP_CLK_SRC 124 -#define GCC_GPLL6 125 -#define GCC_GPLL6_OUT_AUX 126 -#define GCC_MDSS_MDP_VOTE_CLK 127 -#define GCC_MDSS_ROTATOR_VOTE_CLK 128 -#define GCC_BIMC_GPU_CLK 129 -#define GCC_GTCU_AHB_CLK 130 -#define GCC_GFX_TCU_CLK 131 -#define GCC_GFX_TBU_CLK 132 -#define GCC_SMMU_CFG_CLK 133 -#define GCC_APSS_TCU_CLK 134 -#define GCC_CRYPTO_AHB_CLK 135 -#define GCC_CRYPTO_AXI_CLK 136 -#define GCC_CRYPTO_CLK 137 -#define GCC_MDP_TBU_CLK 138 -#define GCC_QDSS_DAP_CLK 139 -#define GCC_DCC_XO_CLK 140 -#define GCC_WCSS_Q6_AHB_CLK 141 -#define GCC_WCSS_Q6_AXIM_CLK 142 -#define GCC_CDSP_CFG_AHB_CLK 143 -#define GCC_BIMC_CDSP_CLK 144 -#define GCC_CDSP_TBU_CLK 145 -#define GCC_CDSP_BIMC_CLK_SRC 146 - -#define GCC_GENI_IR_BCR 0 -#define GCC_USB_HS_BCR 1 -#define GCC_USB2_HS_PHY_ONLY_BCR 2 -#define GCC_QUSB2_PHY_BCR 3 -#define GCC_USB_HS_PHY_CFG_AHB_BCR 4 -#define GCC_USB2A_PHY_BCR 5 -#define GCC_USB3_PHY_BCR 6 -#define GCC_USB_30_BCR 7 -#define GCC_USB3PHY_PHY_BCR 8 -#define GCC_PCIE_0_BCR 9 -#define GCC_PCIE_0_PHY_BCR 10 -#define GCC_PCIE_0_LINK_DOWN_BCR 11 -#define GCC_PCIEPHY_0_PHY_BCR 12 -#define GCC_EMAC_BCR 13 -#define GCC_CDSP_RESTART 14 -#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15 -#define GCC_PCIE_0_AHB_ARES 16 -#define GCC_PCIE_0_AXI_SLAVE_ARES 17 -#define GCC_PCIE_0_AXI_MASTER_ARES 18 -#define GCC_PCIE_0_CORE_STICKY_ARES 19 -#define GCC_PCIE_0_SLEEP_ARES 20 -#define GCC_PCIE_0_PIPE_ARES 21 -#define GCC_WDSP_RESTART 22 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h deleted file mode 100644 index 968fa65b9c4..00000000000 --- a/include/dt-bindings/clock/qcom,gcc-sdm845.h +++ /dev/null @@ -1,246 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H - -/* GCC clock registers */ -#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 -#define GCC_AGGRE_UFS_CARD_AXI_CLK 1 -#define GCC_AGGRE_UFS_PHY_AXI_CLK 2 -#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 -#define GCC_AGGRE_USB3_SEC_AXI_CLK 4 -#define GCC_BOOT_ROM_AHB_CLK 5 -#define GCC_CAMERA_AHB_CLK 6 -#define GCC_CAMERA_AXI_CLK 7 -#define GCC_CAMERA_XO_CLK 8 -#define GCC_CE1_AHB_CLK 9 -#define GCC_CE1_AXI_CLK 10 -#define GCC_CE1_CLK 11 -#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 -#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 -#define GCC_CPUSS_AHB_CLK 14 -#define GCC_CPUSS_AHB_CLK_SRC 15 -#define GCC_CPUSS_RBCPR_CLK 16 -#define GCC_CPUSS_RBCPR_CLK_SRC 17 -#define GCC_DDRSS_GPU_AXI_CLK 18 -#define GCC_DISP_AHB_CLK 19 -#define GCC_DISP_AXI_CLK 20 -#define GCC_DISP_GPLL0_CLK_SRC 21 -#define GCC_DISP_GPLL0_DIV_CLK_SRC 22 -#define GCC_DISP_XO_CLK 23 -#define GCC_GP1_CLK 24 -#define GCC_GP1_CLK_SRC 25 -#define GCC_GP2_CLK 26 -#define GCC_GP2_CLK_SRC 27 -#define GCC_GP3_CLK 28 -#define GCC_GP3_CLK_SRC 29 -#define GCC_GPU_CFG_AHB_CLK 30 -#define GCC_GPU_GPLL0_CLK_SRC 31 -#define GCC_GPU_GPLL0_DIV_CLK_SRC 32 -#define GCC_GPU_MEMNOC_GFX_CLK 33 -#define GCC_GPU_SNOC_DVM_GFX_CLK 34 -#define GCC_MSS_AXIS2_CLK 35 -#define GCC_MSS_CFG_AHB_CLK 36 -#define GCC_MSS_GPLL0_DIV_CLK_SRC 37 -#define GCC_MSS_MFAB_AXIS_CLK 38 -#define GCC_MSS_Q6_MEMNOC_AXI_CLK 39 -#define GCC_MSS_SNOC_AXI_CLK 40 -#define GCC_PCIE_0_AUX_CLK 41 -#define GCC_PCIE_0_AUX_CLK_SRC 42 -#define GCC_PCIE_0_CFG_AHB_CLK 43 -#define GCC_PCIE_0_CLKREF_CLK 44 -#define GCC_PCIE_0_MSTR_AXI_CLK 45 -#define GCC_PCIE_0_PIPE_CLK 46 -#define GCC_PCIE_0_SLV_AXI_CLK 47 -#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 -#define GCC_PCIE_1_AUX_CLK 49 -#define GCC_PCIE_1_AUX_CLK_SRC 50 -#define GCC_PCIE_1_CFG_AHB_CLK 51 -#define GCC_PCIE_1_CLKREF_CLK 52 -#define GCC_PCIE_1_MSTR_AXI_CLK 53 -#define GCC_PCIE_1_PIPE_CLK 54 -#define GCC_PCIE_1_SLV_AXI_CLK 55 -#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56 -#define GCC_PCIE_PHY_AUX_CLK 57 -#define GCC_PCIE_PHY_REFGEN_CLK 58 -#define GCC_PCIE_PHY_REFGEN_CLK_SRC 59 -#define GCC_PDM2_CLK 60 -#define GCC_PDM2_CLK_SRC 61 -#define GCC_PDM_AHB_CLK 62 -#define GCC_PDM_XO4_CLK 63 -#define GCC_PRNG_AHB_CLK 64 -#define GCC_QMIP_CAMERA_AHB_CLK 65 -#define GCC_QMIP_DISP_AHB_CLK 66 -#define GCC_QMIP_VIDEO_AHB_CLK 67 -#define GCC_QUPV3_WRAP0_S0_CLK 68 -#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69 -#define GCC_QUPV3_WRAP0_S1_CLK 70 -#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71 -#define GCC_QUPV3_WRAP0_S2_CLK 72 -#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73 -#define GCC_QUPV3_WRAP0_S3_CLK 74 -#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75 -#define GCC_QUPV3_WRAP0_S4_CLK 76 -#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77 -#define GCC_QUPV3_WRAP0_S5_CLK 78 -#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79 -#define GCC_QUPV3_WRAP0_S6_CLK 80 -#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81 -#define GCC_QUPV3_WRAP0_S7_CLK 82 -#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83 -#define GCC_QUPV3_WRAP1_S0_CLK 84 -#define GCC_QUPV3_WRAP1_S0_CLK_SRC 85 -#define GCC_QUPV3_WRAP1_S1_CLK 86 -#define GCC_QUPV3_WRAP1_S1_CLK_SRC 87 -#define GCC_QUPV3_WRAP1_S2_CLK 88 -#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89 -#define GCC_QUPV3_WRAP1_S3_CLK 90 -#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91 -#define GCC_QUPV3_WRAP1_S4_CLK 92 -#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93 -#define GCC_QUPV3_WRAP1_S5_CLK 94 -#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95 -#define GCC_QUPV3_WRAP1_S6_CLK 96 -#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97 -#define GCC_QUPV3_WRAP1_S7_CLK 98 -#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99 -#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100 -#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101 -#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102 -#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103 -#define GCC_SDCC2_AHB_CLK 104 -#define GCC_SDCC2_APPS_CLK 105 -#define GCC_SDCC2_APPS_CLK_SRC 106 -#define GCC_SDCC4_AHB_CLK 107 -#define GCC_SDCC4_APPS_CLK 108 -#define GCC_SDCC4_APPS_CLK_SRC 109 -#define GCC_SYS_NOC_CPUSS_AHB_CLK 110 -#define GCC_TSIF_AHB_CLK 111 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112 -#define GCC_TSIF_REF_CLK 113 -#define GCC_TSIF_REF_CLK_SRC 114 -#define GCC_UFS_CARD_AHB_CLK 115 -#define GCC_UFS_CARD_AXI_CLK 116 -#define GCC_UFS_CARD_AXI_CLK_SRC 117 -#define GCC_UFS_CARD_CLKREF_CLK 118 -#define GCC_UFS_CARD_ICE_CORE_CLK 119 -#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120 -#define GCC_UFS_CARD_PHY_AUX_CLK 121 -#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122 -#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123 -#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124 -#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127 -#define GCC_UFS_MEM_CLKREF_CLK 128 -#define GCC_UFS_PHY_AHB_CLK 129 -#define GCC_UFS_PHY_AXI_CLK 130 -#define GCC_UFS_PHY_AXI_CLK_SRC 131 -#define GCC_UFS_PHY_ICE_CORE_CLK 132 -#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133 -#define GCC_UFS_PHY_PHY_AUX_CLK 134 -#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135 -#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136 -#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137 -#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140 -#define GCC_USB30_PRIM_MASTER_CLK 141 -#define GCC_USB30_PRIM_MASTER_CLK_SRC 142 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144 -#define GCC_USB30_PRIM_SLEEP_CLK 145 -#define GCC_USB30_SEC_MASTER_CLK 146 -#define GCC_USB30_SEC_MASTER_CLK_SRC 147 -#define GCC_USB30_SEC_MOCK_UTMI_CLK 148 -#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149 -#define GCC_USB30_SEC_SLEEP_CLK 150 -#define GCC_USB3_PRIM_CLKREF_CLK 151 -#define GCC_USB3_PRIM_PHY_AUX_CLK 152 -#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153 -#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154 -#define GCC_USB3_PRIM_PHY_PIPE_CLK 155 -#define GCC_USB3_SEC_CLKREF_CLK 156 -#define GCC_USB3_SEC_PHY_AUX_CLK 157 -#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158 -#define GCC_USB3_SEC_PHY_PIPE_CLK 159 -#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161 -#define GCC_VIDEO_AHB_CLK 162 -#define GCC_VIDEO_AXI_CLK 163 -#define GCC_VIDEO_XO_CLK 164 -#define GPLL0 165 -#define GPLL0_OUT_EVEN 166 -#define GPLL0_OUT_MAIN 167 -#define GCC_GPU_IREF_CLK 168 -#define GCC_SDCC1_AHB_CLK 169 -#define GCC_SDCC1_APPS_CLK 170 -#define GCC_SDCC1_ICE_CORE_CLK 171 -#define GCC_SDCC1_APPS_CLK_SRC 172 -#define GCC_SDCC1_ICE_CORE_CLK_SRC 173 -#define GCC_APC_VS_CLK 174 -#define GCC_GPU_VS_CLK 175 -#define GCC_MSS_VS_CLK 176 -#define GCC_VDDA_VS_CLK 177 -#define GCC_VDDCX_VS_CLK 178 -#define GCC_VDDMX_VS_CLK 179 -#define GCC_VS_CTRL_AHB_CLK 180 -#define GCC_VS_CTRL_CLK 181 -#define GCC_VS_CTRL_CLK_SRC 182 -#define GCC_VSENSOR_CLK_SRC 183 -#define GPLL4 184 -#define GCC_CPUSS_DVM_BUS_CLK 185 -#define GCC_CPUSS_GNOC_CLK 186 -#define GCC_QSPI_CORE_CLK_SRC 187 -#define GCC_QSPI_CORE_CLK 188 -#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 -#define GCC_LPASS_Q6_AXI_CLK 190 -#define GCC_LPASS_SWAY_CLK 191 - -/* GCC Resets */ -#define GCC_MMSS_BCR 0 -#define GCC_PCIE_0_BCR 1 -#define GCC_PCIE_1_BCR 2 -#define GCC_PCIE_PHY_BCR 3 -#define GCC_PDM_BCR 4 -#define GCC_PRNG_BCR 5 -#define GCC_QUPV3_WRAPPER_0_BCR 6 -#define GCC_QUPV3_WRAPPER_1_BCR 7 -#define GCC_QUSB2PHY_PRIM_BCR 8 -#define GCC_QUSB2PHY_SEC_BCR 9 -#define GCC_SDCC2_BCR 10 -#define GCC_SDCC4_BCR 11 -#define GCC_TSIF_BCR 12 -#define GCC_UFS_CARD_BCR 13 -#define GCC_UFS_PHY_BCR 14 -#define GCC_USB30_PRIM_BCR 15 -#define GCC_USB30_SEC_BCR 16 -#define GCC_USB3_PHY_PRIM_BCR 17 -#define GCC_USB3PHY_PHY_PRIM_BCR 18 -#define GCC_USB3_DP_PHY_PRIM_BCR 19 -#define GCC_USB3_PHY_SEC_BCR 20 -#define GCC_USB3PHY_PHY_SEC_BCR 21 -#define GCC_USB3_DP_PHY_SEC_BCR 22 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 -#define GCC_PCIE_0_PHY_BCR 24 -#define GCC_PCIE_1_PHY_BCR 25 - -/* GCC GDSCRs */ -#define PCIE_0_GDSC 0 -#define PCIE_1_GDSC 1 -#define UFS_CARD_GDSC 2 -#define UFS_PHY_GDSC 3 -#define USB30_PRIM_GDSC 4 -#define USB30_SEC_GDSC 5 -#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6 -#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7 -#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8 -#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9 -#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10 -#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11 -#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12 - -#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sdm845.h b/include/dt-bindings/clock/qcom,gpucc-sdm845.h deleted file mode 100644 index 9690d901b50..00000000000 --- a/include/dt-bindings/clock/qcom,gpucc-sdm845.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H - -/* GPU_CC clock registers */ -#define GPU_CC_CX_GMU_CLK 0 -#define GPU_CC_CXO_CLK 1 -#define GPU_CC_GMU_CLK_SRC 2 -#define GPU_CC_PLL1 3 - -/* GPU_CC Resets */ -#define GPUCC_GPU_CC_CX_BCR 0 -#define GPUCC_GPU_CC_GMU_BCR 1 -#define GPUCC_GPU_CC_XO_BCR 2 - -/* GPU_CC GDSCRs */ -#define GPU_CX_GDSC 0 -#define GPU_GX_GDSC 1 - -#endif diff --git a/include/dt-bindings/clock/qcom,lpass-sdm845.h b/include/dt-bindings/clock/qcom,lpass-sdm845.h deleted file mode 100644 index 659050846f6..00000000000 --- a/include/dt-bindings/clock/qcom,lpass-sdm845.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H -#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H - -#define LPASS_Q6SS_AHBM_AON_CLK 0 -#define LPASS_Q6SS_AHBS_AON_CLK 1 -#define LPASS_QDSP6SS_XO_CLK 2 -#define LPASS_QDSP6SS_SLEEP_CLK 3 -#define LPASS_QDSP6SS_CORE_CLK 4 - -#endif diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/include/dt-bindings/clock/qcom,mmcc-msm8996.h deleted file mode 100644 index d51f9ac7056..00000000000 --- a/include/dt-bindings/clock/qcom,mmcc-msm8996.h +++ /dev/null @@ -1,295 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H -#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H - -#define MMPLL0_EARLY 0 -#define MMPLL0_PLL 1 -#define MMPLL1_EARLY 2 -#define MMPLL1_PLL 3 -#define MMPLL2_EARLY 4 -#define MMPLL2_PLL 5 -#define MMPLL3_EARLY 6 -#define MMPLL3_PLL 7 -#define MMPLL4_EARLY 8 -#define MMPLL4_PLL 9 -#define MMPLL5_EARLY 10 -#define MMPLL5_PLL 11 -#define MMPLL8_EARLY 12 -#define MMPLL8_PLL 13 -#define MMPLL9_EARLY 14 -#define MMPLL9_PLL 15 -#define AHB_CLK_SRC 16 -#define AXI_CLK_SRC 17 -#define MAXI_CLK_SRC 18 -#define DSA_CORE_CLK_SRC 19 -#define GFX3D_CLK_SRC 20 -#define RBBMTIMER_CLK_SRC 21 -#define ISENSE_CLK_SRC 22 -#define RBCPR_CLK_SRC 23 -#define VIDEO_CORE_CLK_SRC 24 -#define VIDEO_SUBCORE0_CLK_SRC 25 -#define VIDEO_SUBCORE1_CLK_SRC 26 -#define PCLK0_CLK_SRC 27 -#define PCLK1_CLK_SRC 28 -#define MDP_CLK_SRC 29 -#define EXTPCLK_CLK_SRC 30 -#define VSYNC_CLK_SRC 31 -#define HDMI_CLK_SRC 32 -#define BYTE0_CLK_SRC 33 -#define BYTE1_CLK_SRC 34 -#define ESC0_CLK_SRC 35 -#define ESC1_CLK_SRC 36 -#define CAMSS_GP0_CLK_SRC 37 -#define CAMSS_GP1_CLK_SRC 38 -#define MCLK0_CLK_SRC 39 -#define MCLK1_CLK_SRC 40 -#define MCLK2_CLK_SRC 41 -#define MCLK3_CLK_SRC 42 -#define CCI_CLK_SRC 43 -#define CSI0PHYTIMER_CLK_SRC 44 -#define CSI1PHYTIMER_CLK_SRC 45 -#define CSI2PHYTIMER_CLK_SRC 46 -#define CSIPHY0_3P_CLK_SRC 47 -#define CSIPHY1_3P_CLK_SRC 48 -#define CSIPHY2_3P_CLK_SRC 49 -#define JPEG0_CLK_SRC 50 -#define JPEG2_CLK_SRC 51 -#define JPEG_DMA_CLK_SRC 52 -#define VFE0_CLK_SRC 53 -#define VFE1_CLK_SRC 54 -#define CPP_CLK_SRC 55 -#define CSI0_CLK_SRC 56 -#define CSI1_CLK_SRC 57 -#define CSI2_CLK_SRC 58 -#define CSI3_CLK_SRC 59 -#define FD_CORE_CLK_SRC 60 -#define MMSS_CXO_CLK 61 -#define MMSS_SLEEPCLK_CLK 62 -#define MMSS_MMAGIC_AHB_CLK 63 -#define MMSS_MMAGIC_CFG_AHB_CLK 64 -#define MMSS_MISC_AHB_CLK 65 -#define MMSS_MISC_CXO_CLK 66 -#define MMSS_BTO_AHB_CLK 67 -#define MMSS_MMAGIC_AXI_CLK 68 -#define MMSS_S0_AXI_CLK 69 -#define MMSS_MMAGIC_MAXI_CLK 70 -#define DSA_CORE_CLK 71 -#define DSA_NOC_CFG_AHB_CLK 72 -#define MMAGIC_CAMSS_AXI_CLK 73 -#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 74 -#define THROTTLE_CAMSS_CXO_CLK 75 -#define THROTTLE_CAMSS_AHB_CLK 76 -#define THROTTLE_CAMSS_AXI_CLK 77 -#define SMMU_VFE_AHB_CLK 78 -#define SMMU_VFE_AXI_CLK 79 -#define SMMU_CPP_AHB_CLK 80 -#define SMMU_CPP_AXI_CLK 81 -#define SMMU_JPEG_AHB_CLK 82 -#define SMMU_JPEG_AXI_CLK 83 -#define MMAGIC_MDSS_AXI_CLK 84 -#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 85 -#define THROTTLE_MDSS_CXO_CLK 86 -#define THROTTLE_MDSS_AHB_CLK 87 -#define THROTTLE_MDSS_AXI_CLK 88 -#define SMMU_ROT_AHB_CLK 89 -#define SMMU_ROT_AXI_CLK 90 -#define SMMU_MDP_AHB_CLK 91 -#define SMMU_MDP_AXI_CLK 92 -#define MMAGIC_VIDEO_AXI_CLK 93 -#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 94 -#define THROTTLE_VIDEO_CXO_CLK 95 -#define THROTTLE_VIDEO_AHB_CLK 96 -#define THROTTLE_VIDEO_AXI_CLK 97 -#define SMMU_VIDEO_AHB_CLK 98 -#define SMMU_VIDEO_AXI_CLK 99 -#define MMAGIC_BIMC_AXI_CLK 100 -#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 101 -#define GPU_GX_GFX3D_CLK 102 -#define GPU_GX_RBBMTIMER_CLK 103 -#define GPU_AHB_CLK 104 -#define GPU_AON_ISENSE_CLK 105 -#define VMEM_MAXI_CLK 106 -#define VMEM_AHB_CLK 107 -#define MMSS_RBCPR_CLK 108 -#define MMSS_RBCPR_AHB_CLK 109 -#define VIDEO_CORE_CLK 110 -#define VIDEO_AXI_CLK 111 -#define VIDEO_MAXI_CLK 112 -#define VIDEO_AHB_CLK 113 -#define VIDEO_SUBCORE0_CLK 114 -#define VIDEO_SUBCORE1_CLK 115 -#define MDSS_AHB_CLK 116 -#define MDSS_HDMI_AHB_CLK 117 -#define MDSS_AXI_CLK 118 -#define MDSS_PCLK0_CLK 119 -#define MDSS_PCLK1_CLK 120 -#define MDSS_MDP_CLK 121 -#define MDSS_EXTPCLK_CLK 122 -#define MDSS_VSYNC_CLK 123 -#define MDSS_HDMI_CLK 124 -#define MDSS_BYTE0_CLK 125 -#define MDSS_BYTE1_CLK 126 -#define MDSS_ESC0_CLK 127 -#define MDSS_ESC1_CLK 128 -#define CAMSS_TOP_AHB_CLK 129 -#define CAMSS_AHB_CLK 130 -#define CAMSS_MICRO_AHB_CLK 131 -#define CAMSS_GP0_CLK 132 -#define CAMSS_GP1_CLK 133 -#define CAMSS_MCLK0_CLK 134 -#define CAMSS_MCLK1_CLK 135 -#define CAMSS_MCLK2_CLK 136 -#define CAMSS_MCLK3_CLK 137 -#define CAMSS_CCI_CLK 138 -#define CAMSS_CCI_AHB_CLK 139 -#define CAMSS_CSI0PHYTIMER_CLK 140 -#define CAMSS_CSI1PHYTIMER_CLK 141 -#define CAMSS_CSI2PHYTIMER_CLK 142 -#define CAMSS_CSIPHY0_3P_CLK 143 -#define CAMSS_CSIPHY1_3P_CLK 144 -#define CAMSS_CSIPHY2_3P_CLK 145 -#define CAMSS_JPEG0_CLK 146 -#define CAMSS_JPEG2_CLK 147 -#define CAMSS_JPEG_DMA_CLK 148 -#define CAMSS_JPEG_AHB_CLK 149 -#define CAMSS_JPEG_AXI_CLK 150 -#define CAMSS_VFE_AHB_CLK 151 -#define CAMSS_VFE_AXI_CLK 152 -#define CAMSS_VFE0_CLK 153 -#define CAMSS_VFE0_STREAM_CLK 154 -#define CAMSS_VFE0_AHB_CLK 155 -#define CAMSS_VFE1_CLK 156 -#define CAMSS_VFE1_STREAM_CLK 157 -#define CAMSS_VFE1_AHB_CLK 158 -#define CAMSS_CSI_VFE0_CLK 159 -#define CAMSS_CSI_VFE1_CLK 160 -#define CAMSS_CPP_VBIF_AHB_CLK 161 -#define CAMSS_CPP_AXI_CLK 162 -#define CAMSS_CPP_CLK 163 -#define CAMSS_CPP_AHB_CLK 164 -#define CAMSS_CSI0_CLK 165 -#define CAMSS_CSI0_AHB_CLK 166 -#define CAMSS_CSI0PHY_CLK 167 -#define CAMSS_CSI0RDI_CLK 168 -#define CAMSS_CSI0PIX_CLK 169 -#define CAMSS_CSI1_CLK 170 -#define CAMSS_CSI1_AHB_CLK 171 -#define CAMSS_CSI1PHY_CLK 172 -#define CAMSS_CSI1RDI_CLK 173 -#define CAMSS_CSI1PIX_CLK 174 -#define CAMSS_CSI2_CLK 175 -#define CAMSS_CSI2_AHB_CLK 176 -#define CAMSS_CSI2PHY_CLK 177 -#define CAMSS_CSI2RDI_CLK 178 -#define CAMSS_CSI2PIX_CLK 179 -#define CAMSS_CSI3_CLK 180 -#define CAMSS_CSI3_AHB_CLK 181 -#define CAMSS_CSI3PHY_CLK 182 -#define CAMSS_CSI3RDI_CLK 183 -#define CAMSS_CSI3PIX_CLK 184 -#define CAMSS_ISPIF_AHB_CLK 185 -#define FD_CORE_CLK 186 -#define FD_CORE_UAR_CLK 187 -#define FD_AHB_CLK 188 -#define MMSS_SPDM_CSI0_CLK 189 -#define MMSS_SPDM_JPEG_DMA_CLK 190 -#define MMSS_SPDM_CPP_CLK 191 -#define MMSS_SPDM_PCLK0_CLK 192 -#define MMSS_SPDM_AHB_CLK 193 -#define MMSS_SPDM_GFX3D_CLK 194 -#define MMSS_SPDM_PCLK1_CLK 195 -#define MMSS_SPDM_JPEG2_CLK 196 -#define MMSS_SPDM_DEBUG_CLK 197 -#define MMSS_SPDM_VFE1_CLK 198 -#define MMSS_SPDM_VFE0_CLK 199 -#define MMSS_SPDM_VIDEO_CORE_CLK 200 -#define MMSS_SPDM_AXI_CLK 201 -#define MMSS_SPDM_MDP_CLK 202 -#define MMSS_SPDM_JPEG0_CLK 203 -#define MMSS_SPDM_RM_AXI_CLK 204 -#define MMSS_SPDM_RM_MAXI_CLK 205 - -#define MMAGICAHB_BCR 0 -#define MMAGIC_CFG_BCR 1 -#define MISC_BCR 2 -#define BTO_BCR 3 -#define MMAGICAXI_BCR 4 -#define MMAGICMAXI_BCR 5 -#define DSA_BCR 6 -#define MMAGIC_CAMSS_BCR 7 -#define THROTTLE_CAMSS_BCR 8 -#define SMMU_VFE_BCR 9 -#define SMMU_CPP_BCR 10 -#define SMMU_JPEG_BCR 11 -#define MMAGIC_MDSS_BCR 12 -#define THROTTLE_MDSS_BCR 13 -#define SMMU_ROT_BCR 14 -#define SMMU_MDP_BCR 15 -#define MMAGIC_VIDEO_BCR 16 -#define THROTTLE_VIDEO_BCR 17 -#define SMMU_VIDEO_BCR 18 -#define MMAGIC_BIMC_BCR 19 -#define GPU_GX_BCR 20 -#define GPU_BCR 21 -#define GPU_AON_BCR 22 -#define VMEM_BCR 23 -#define MMSS_RBCPR_BCR 24 -#define VIDEO_BCR 25 -#define MDSS_BCR 26 -#define CAMSS_TOP_BCR 27 -#define CAMSS_AHB_BCR 28 -#define CAMSS_MICRO_BCR 29 -#define CAMSS_CCI_BCR 30 -#define CAMSS_PHY0_BCR 31 -#define CAMSS_PHY1_BCR 32 -#define CAMSS_PHY2_BCR 33 -#define CAMSS_CSIPHY0_3P_BCR 34 -#define CAMSS_CSIPHY1_3P_BCR 35 -#define CAMSS_CSIPHY2_3P_BCR 36 -#define CAMSS_JPEG_BCR 37 -#define CAMSS_VFE_BCR 38 -#define CAMSS_VFE0_BCR 39 -#define CAMSS_VFE1_BCR 40 -#define CAMSS_CSI_VFE0_BCR 41 -#define CAMSS_CSI_VFE1_BCR 42 -#define CAMSS_CPP_TOP_BCR 43 -#define CAMSS_CPP_BCR 44 -#define CAMSS_CSI0_BCR 45 -#define CAMSS_CSI0RDI_BCR 46 -#define CAMSS_CSI0PIX_BCR 47 -#define CAMSS_CSI1_BCR 48 -#define CAMSS_CSI1RDI_BCR 49 -#define CAMSS_CSI1PIX_BCR 50 -#define CAMSS_CSI2_BCR 51 -#define CAMSS_CSI2RDI_BCR 52 -#define CAMSS_CSI2PIX_BCR 53 -#define CAMSS_CSI3_BCR 54 -#define CAMSS_CSI3RDI_BCR 55 -#define CAMSS_CSI3PIX_BCR 56 -#define CAMSS_ISPIF_BCR 57 -#define FD_BCR 58 -#define MMSS_SPDM_RM_BCR 59 - -/* Indexes for GDSCs */ -#define MMAGIC_VIDEO_GDSC 0 -#define MMAGIC_MDSS_GDSC 1 -#define MMAGIC_CAMSS_GDSC 2 -#define GPU_GDSC 3 -#define VENUS_GDSC 4 -#define VENUS_CORE0_GDSC 5 -#define VENUS_CORE1_GDSC 6 -#define CAMSS_GDSC 7 -#define VFE0_GDSC 8 -#define VFE1_GDSC 9 -#define JPEG_GDSC 10 -#define CPP_GDSC 11 -#define FD_GDSC 12 -#define MDSS_GDSC 13 -#define GPU_GX_GDSC 14 -#define MMAGIC_BIMC_GDSC 15 - -#endif diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h deleted file mode 100644 index 46309c9953b..00000000000 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2015 Linaro Limited - */ - -#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H -#define _DT_BINDINGS_CLK_MSM_RPMCC_H - -/* RPM clocks */ -#define RPM_PXO_CLK 0 -#define RPM_PXO_A_CLK 1 -#define RPM_CXO_CLK 2 -#define RPM_CXO_A_CLK 3 -#define RPM_APPS_FABRIC_CLK 4 -#define RPM_APPS_FABRIC_A_CLK 5 -#define RPM_CFPB_CLK 6 -#define RPM_CFPB_A_CLK 7 -#define RPM_QDSS_CLK 8 -#define RPM_QDSS_A_CLK 9 -#define RPM_DAYTONA_FABRIC_CLK 10 -#define RPM_DAYTONA_FABRIC_A_CLK 11 -#define RPM_EBI1_CLK 12 -#define RPM_EBI1_A_CLK 13 -#define RPM_MM_FABRIC_CLK 14 -#define RPM_MM_FABRIC_A_CLK 15 -#define RPM_MMFPB_CLK 16 -#define RPM_MMFPB_A_CLK 17 -#define RPM_SYS_FABRIC_CLK 18 -#define RPM_SYS_FABRIC_A_CLK 19 -#define RPM_SFPB_CLK 20 -#define RPM_SFPB_A_CLK 21 -#define RPM_SMI_CLK 22 -#define RPM_SMI_A_CLK 23 -#define RPM_PLL4_CLK 24 -#define RPM_XO_D0 25 -#define RPM_XO_D1 26 -#define RPM_XO_A0 27 -#define RPM_XO_A1 28 -#define RPM_XO_A2 29 -#define RPM_NSS_FABRIC_0_CLK 30 -#define RPM_NSS_FABRIC_0_A_CLK 31 -#define RPM_NSS_FABRIC_1_CLK 32 -#define RPM_NSS_FABRIC_1_A_CLK 33 - -/* SMD RPM clocks */ -#define RPM_SMD_XO_CLK_SRC 0 -#define RPM_SMD_XO_A_CLK_SRC 1 -#define RPM_SMD_PCNOC_CLK 2 -#define RPM_SMD_PCNOC_A_CLK 3 -#define RPM_SMD_SNOC_CLK 4 -#define RPM_SMD_SNOC_A_CLK 5 -#define RPM_SMD_BIMC_CLK 6 -#define RPM_SMD_BIMC_A_CLK 7 -#define RPM_SMD_QDSS_CLK 8 -#define RPM_SMD_QDSS_A_CLK 9 -#define RPM_SMD_BB_CLK1 10 -#define RPM_SMD_BB_CLK1_A 11 -#define RPM_SMD_BB_CLK2 12 -#define RPM_SMD_BB_CLK2_A 13 -#define RPM_SMD_RF_CLK1 14 -#define RPM_SMD_RF_CLK1_A 15 -#define RPM_SMD_RF_CLK2 16 -#define RPM_SMD_RF_CLK2_A 17 -#define RPM_SMD_BB_CLK1_PIN 18 -#define RPM_SMD_BB_CLK1_A_PIN 19 -#define RPM_SMD_BB_CLK2_PIN 20 -#define RPM_SMD_BB_CLK2_A_PIN 21 -#define RPM_SMD_RF_CLK1_PIN 22 -#define RPM_SMD_RF_CLK1_A_PIN 23 -#define RPM_SMD_RF_CLK2_PIN 24 -#define RPM_SMD_RF_CLK2_A_PIN 25 -#define RPM_SMD_PNOC_CLK 26 -#define RPM_SMD_PNOC_A_CLK 27 -#define RPM_SMD_CNOC_CLK 28 -#define RPM_SMD_CNOC_A_CLK 29 -#define RPM_SMD_MMSSNOC_AHB_CLK 30 -#define RPM_SMD_MMSSNOC_AHB_A_CLK 31 -#define RPM_SMD_GFX3D_CLK_SRC 32 -#define RPM_SMD_GFX3D_A_CLK_SRC 33 -#define RPM_SMD_OCMEMGX_CLK 34 -#define RPM_SMD_OCMEMGX_A_CLK 35 -#define RPM_SMD_CXO_D0 36 -#define RPM_SMD_CXO_D0_A 37 -#define RPM_SMD_CXO_D1 38 -#define RPM_SMD_CXO_D1_A 39 -#define RPM_SMD_CXO_A0 40 -#define RPM_SMD_CXO_A0_A 41 -#define RPM_SMD_CXO_A1 42 -#define RPM_SMD_CXO_A1_A 43 -#define RPM_SMD_CXO_A2 44 -#define RPM_SMD_CXO_A2_A 45 -#define RPM_SMD_DIV_CLK1 46 -#define RPM_SMD_DIV_A_CLK1 47 -#define RPM_SMD_DIV_CLK2 48 -#define RPM_SMD_DIV_A_CLK2 49 -#define RPM_SMD_DIFF_CLK 50 -#define RPM_SMD_DIFF_A_CLK 51 -#define RPM_SMD_CXO_D0_PIN 52 -#define RPM_SMD_CXO_D0_A_PIN 53 -#define RPM_SMD_CXO_D1_PIN 54 -#define RPM_SMD_CXO_D1_A_PIN 55 -#define RPM_SMD_CXO_A0_PIN 56 -#define RPM_SMD_CXO_A0_A_PIN 57 -#define RPM_SMD_CXO_A1_PIN 58 -#define RPM_SMD_CXO_A1_A_PIN 59 -#define RPM_SMD_CXO_A2_PIN 60 -#define RPM_SMD_CXO_A2_A_PIN 61 -#define RPM_SMD_AGGR1_NOC_CLK 62 -#define RPM_SMD_AGGR1_NOC_A_CLK 63 -#define RPM_SMD_AGGR2_NOC_CLK 64 -#define RPM_SMD_AGGR2_NOC_A_CLK 65 -#define RPM_SMD_MMAXI_CLK 66 -#define RPM_SMD_MMAXI_A_CLK 67 -#define RPM_SMD_IPA_CLK 68 -#define RPM_SMD_IPA_A_CLK 69 -#define RPM_SMD_CE1_CLK 70 -#define RPM_SMD_CE1_A_CLK 71 -#define RPM_SMD_DIV_CLK3 72 -#define RPM_SMD_DIV_A_CLK3 73 -#define RPM_SMD_LN_BB_CLK 74 -#define RPM_SMD_LN_BB_A_CLK 75 -#define RPM_SMD_BIMC_GPU_CLK 76 -#define RPM_SMD_BIMC_GPU_A_CLK 77 -#define RPM_SMD_QPIC_CLK 78 -#define RPM_SMD_QPIC_CLK_A 79 -#define RPM_SMD_LN_BB_CLK1 80 -#define RPM_SMD_LN_BB_CLK1_A 81 -#define RPM_SMD_LN_BB_CLK2 82 -#define RPM_SMD_LN_BB_CLK2_A 83 -#define RPM_SMD_LN_BB_CLK3_PIN 84 -#define RPM_SMD_LN_BB_CLK3_A_PIN 85 -#define RPM_SMD_RF_CLK3 86 -#define RPM_SMD_RF_CLK3_A 87 -#define RPM_SMD_RF_CLK3_PIN 88 -#define RPM_SMD_RF_CLK3_A_PIN 89 -#define RPM_SMD_MMSSNOC_AXI_CLK 90 -#define RPM_SMD_MMSSNOC_AXI_CLK_A 91 -#define RPM_SMD_CNOC_PERIPH_CLK 92 -#define RPM_SMD_CNOC_PERIPH_A_CLK 93 -#define RPM_SMD_LN_BB_CLK3 94 -#define RPM_SMD_LN_BB_CLK3_A 95 -#define RPM_SMD_LN_BB_CLK1_PIN 96 -#define RPM_SMD_LN_BB_CLK1_A_PIN 97 -#define RPM_SMD_LN_BB_CLK2_PIN 98 -#define RPM_SMD_LN_BB_CLK2_A_PIN 99 -#define RPM_SMD_SYSMMNOC_CLK 100 -#define RPM_SMD_SYSMMNOC_A_CLK 101 -#define RPM_SMD_CE2_CLK 102 -#define RPM_SMD_CE2_A_CLK 103 -#define RPM_SMD_CE3_CLK 104 -#define RPM_SMD_CE3_A_CLK 105 -#define RPM_SMD_QUP_CLK 106 -#define RPM_SMD_QUP_A_CLK 107 -#define RPM_SMD_MMRT_CLK 108 -#define RPM_SMD_MMRT_A_CLK 109 -#define RPM_SMD_MMNRT_CLK 110 -#define RPM_SMD_MMNRT_A_CLK 111 -#define RPM_SMD_SNOC_PERIPH_CLK 112 -#define RPM_SMD_SNOC_PERIPH_A_CLK 113 -#define RPM_SMD_SNOC_LPASS_CLK 114 -#define RPM_SMD_SNOC_LPASS_A_CLK 115 -#define RPM_SMD_HWKM_CLK 116 -#define RPM_SMD_HWKM_A_CLK 117 -#define RPM_SMD_PKA_CLK 118 -#define RPM_SMD_PKA_A_CLK 119 -#define RPM_SMD_CPUSS_GNOC_CLK 120 -#define RPM_SMD_CPUSS_GNOC_A_CLK 121 -#define RPM_SMD_MSS_CFG_AHB_CLK 122 -#define RPM_SMD_MSS_CFG_AHB_A_CLK 123 -#define RPM_SMD_BIMC_FREQ_LOG 124 -#define RPM_SMD_LN_BB_CLK_PIN 125 -#define RPM_SMD_LN_BB_A_CLK_PIN 126 - -#endif diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h deleted file mode 100644 index bf5b59b1008..00000000000 --- a/include/dt-bindings/clock/qcom,rpmh.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */ - -#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H -#define _DT_BINDINGS_CLK_MSM_RPMH_H - -/* RPMh controlled clocks */ -#define RPMH_CXO_CLK 0 -#define RPMH_CXO_CLK_A 1 -#define RPMH_LN_BB_CLK2 2 -#define RPMH_LN_BB_CLK2_A 3 -#define RPMH_LN_BB_CLK3 4 -#define RPMH_LN_BB_CLK3_A 5 -#define RPMH_RF_CLK1 6 -#define RPMH_RF_CLK1_A 7 -#define RPMH_RF_CLK2 8 -#define RPMH_RF_CLK2_A 9 -#define RPMH_RF_CLK3 10 -#define RPMH_RF_CLK3_A 11 -#define RPMH_IPA_CLK 12 -#define RPMH_LN_BB_CLK1 13 -#define RPMH_LN_BB_CLK1_A 14 -#define RPMH_CE_CLK 15 -#define RPMH_QPIC_CLK 16 -#define RPMH_DIV_CLK1 17 -#define RPMH_DIV_CLK1_A 18 -#define RPMH_RF_CLK4 19 -#define RPMH_RF_CLK4_A 20 -#define RPMH_RF_CLK5 21 -#define RPMH_RF_CLK5_A 22 -#define RPMH_PKA_CLK 23 -#define RPMH_HWKM_CLK 24 -#define RPMH_QLINK_CLK 25 -#define RPMH_QLINK_CLK_A 26 - -#endif diff --git a/include/dt-bindings/clock/qcom,turingcc-qcs404.h b/include/dt-bindings/clock/qcom,turingcc-qcs404.h deleted file mode 100644 index 838faef57c6..00000000000 --- a/include/dt-bindings/clock/qcom,turingcc-qcs404.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019, Linaro Ltd - */ - -#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H -#define _DT_BINDINGS_CLK_TURING_QCS404_H - -#define TURING_Q6SS_Q6_AXIM_CLK 0 -#define TURING_Q6SS_AHBM_AON_CLK 1 -#define TURING_WRAPPER_AON_CLK 2 -#define TURING_Q6SS_AHBS_AON_CLK 3 -#define TURING_WRAPPER_QOS_AHBS_AON_CLK 4 - -#endif diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h deleted file mode 100644 index 1b868165e8c..00000000000 --- a/include/dt-bindings/clock/qcom,videocc-sdm845.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H -#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H - -/* VIDEO_CC clock registers */ -#define VIDEO_CC_APB_CLK 0 -#define VIDEO_CC_AT_CLK 1 -#define VIDEO_CC_QDSS_TRIG_CLK 2 -#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK 3 -#define VIDEO_CC_VCODEC0_AXI_CLK 4 -#define VIDEO_CC_VCODEC0_CORE_CLK 5 -#define VIDEO_CC_VCODEC1_AXI_CLK 6 -#define VIDEO_CC_VCODEC1_CORE_CLK 7 -#define VIDEO_CC_VENUS_AHB_CLK 8 -#define VIDEO_CC_VENUS_CLK_SRC 9 -#define VIDEO_CC_VENUS_CTL_AXI_CLK 10 -#define VIDEO_CC_VENUS_CTL_CORE_CLK 11 -#define VIDEO_PLL0 12 - -/* VIDEO_CC Resets */ -#define VIDEO_CC_VENUS_BCR 0 -#define VIDEO_CC_VCODEC0_BCR 1 -#define VIDEO_CC_VCODEC1_BCR 2 -#define VIDEO_CC_INTERFACE_BCR 3 - -/* VIDEO_CC GDSCRs */ -#define VENUS_GDSC 0 -#define VCODEC0_GDSC 1 -#define VCODEC1_GDSC 2 - -#endif diff --git a/include/dt-bindings/dma/qcom-gpi.h b/include/dt-bindings/dma/qcom-gpi.h deleted file mode 100644 index ebda2a37f52..00000000000 --- a/include/dt-bindings/dma/qcom-gpi.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ -/* Copyright (c) 2020, Linaro Ltd. */ - -#ifndef __DT_BINDINGS_DMA_QCOM_GPI_H__ -#define __DT_BINDINGS_DMA_QCOM_GPI_H__ - -#define QCOM_GPI_SPI 1 -#define QCOM_GPI_UART 2 -#define QCOM_GPI_I2C 3 - -#endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */ diff --git a/include/dt-bindings/firmware/qcom,scm.h b/include/dt-bindings/firmware/qcom,scm.h deleted file mode 100644 index 6de8b08e1e7..00000000000 --- a/include/dt-bindings/firmware/qcom,scm.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved. - * Copyright (C) 2015 Linaro Ltd. - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_FIRMWARE_QCOM_SCM_H -#define _DT_BINDINGS_FIRMWARE_QCOM_SCM_H - -#define QCOM_SCM_VMID_TZ 0x1 -#define QCOM_SCM_VMID_HLOS 0x3 -#define QCOM_SCM_VMID_SSC_Q6 0x5 -#define QCOM_SCM_VMID_ADSP_Q6 0x6 -#define QCOM_SCM_VMID_CP_TOUCH 0x8 -#define QCOM_SCM_VMID_CP_BITSTREAM 0x9 -#define QCOM_SCM_VMID_CP_PIXEL 0xA -#define QCOM_SCM_VMID_CP_NON_PIXEL 0xB -#define QCOM_SCM_VMID_CP_CAMERA 0xD -#define QCOM_SCM_VMID_HLOS_FREE 0xE -#define QCOM_SCM_VMID_MSS_MSA 0xF -#define QCOM_SCM_VMID_MSS_NONMSA 0x10 -#define QCOM_SCM_VMID_CP_SEC_DISPLAY 0x11 -#define QCOM_SCM_VMID_CP_APP 0x12 -#define QCOM_SCM_VMID_LPASS 0x16 -#define QCOM_SCM_VMID_WLAN 0x18 -#define QCOM_SCM_VMID_WLAN_CE 0x19 -#define QCOM_SCM_VMID_CP_SPSS_SP 0x1A -#define QCOM_SCM_VMID_CP_CAMERA_PREVIEW 0x1D -#define QCOM_SCM_VMID_CDSP 0x1E -#define QCOM_SCM_VMID_CP_SPSS_SP_SHARED 0x22 -#define QCOM_SCM_VMID_CP_SPSS_HLOS_SHARED 0x24 -#define QCOM_SCM_VMID_ADSP_HEAP 0x25 -#define QCOM_SCM_VMID_CP_CDSP 0x2A -#define QCOM_SCM_VMID_NAV 0x2B -#define QCOM_SCM_VMID_TVM 0x2D -#define QCOM_SCM_VMID_OEMVM 0x31 - -#endif diff --git a/include/dt-bindings/gpio/meson-a1-gpio.h b/include/dt-bindings/gpio/meson-a1-gpio.h deleted file mode 100644 index 40e57a5ff1d..00000000000 --- a/include/dt-bindings/gpio/meson-a1-gpio.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Qianggui Song <qianggui.song@amlogic.com> - */ - -#ifndef _DT_BINDINGS_MESON_A1_GPIO_H -#define _DT_BINDINGS_MESON_A1_GPIO_H - -#define GPIOP_0 0 -#define GPIOP_1 1 -#define GPIOP_2 2 -#define GPIOP_3 3 -#define GPIOP_4 4 -#define GPIOP_5 5 -#define GPIOP_6 6 -#define GPIOP_7 7 -#define GPIOP_8 8 -#define GPIOP_9 9 -#define GPIOP_10 10 -#define GPIOP_11 11 -#define GPIOP_12 12 -#define GPIOB_0 13 -#define GPIOB_1 14 -#define GPIOB_2 15 -#define GPIOB_3 16 -#define GPIOB_4 17 -#define GPIOB_5 18 -#define GPIOB_6 19 -#define GPIOX_0 20 -#define GPIOX_1 21 -#define GPIOX_2 22 -#define GPIOX_3 23 -#define GPIOX_4 24 -#define GPIOX_5 25 -#define GPIOX_6 26 -#define GPIOX_7 27 -#define GPIOX_8 28 -#define GPIOX_9 29 -#define GPIOX_10 30 -#define GPIOX_11 31 -#define GPIOX_12 32 -#define GPIOX_13 33 -#define GPIOX_14 34 -#define GPIOX_15 35 -#define GPIOX_16 36 -#define GPIOF_0 37 -#define GPIOF_1 38 -#define GPIOF_2 39 -#define GPIOF_3 40 -#define GPIOF_4 41 -#define GPIOF_5 42 -#define GPIOF_6 43 -#define GPIOF_7 44 -#define GPIOF_8 45 -#define GPIOF_9 46 -#define GPIOF_10 47 -#define GPIOF_11 48 -#define GPIOF_12 49 -#define GPIOA_0 50 -#define GPIOA_1 51 -#define GPIOA_2 52 -#define GPIOA_3 53 -#define GPIOA_4 54 -#define GPIOA_5 55 -#define GPIOA_6 56 -#define GPIOA_7 57 -#define GPIOA_8 58 -#define GPIOA_9 59 -#define GPIOA_10 60 -#define GPIOA_11 61 - -#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h deleted file mode 100644 index 08adfe25964..00000000000 --- a/include/dt-bindings/iio/qcom,spmi-vadc.h +++ /dev/null @@ -1,300 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_H - -/* Voltage ADC channels */ -#define VADC_USBIN 0x00 -#define VADC_DCIN 0x01 -#define VADC_VCHG_SNS 0x02 -#define VADC_SPARE1_03 0x03 -#define VADC_USB_ID_MV 0x04 -#define VADC_VCOIN 0x05 -#define VADC_VBAT_SNS 0x06 -#define VADC_VSYS 0x07 -#define VADC_DIE_TEMP 0x08 -#define VADC_REF_625MV 0x09 -#define VADC_REF_1250MV 0x0a -#define VADC_CHG_TEMP 0x0b -#define VADC_SPARE1 0x0c -#define VADC_SPARE2 0x0d -#define VADC_GND_REF 0x0e -#define VADC_VDD_VADC 0x0f - -#define VADC_P_MUX1_1_1 0x10 -#define VADC_P_MUX2_1_1 0x11 -#define VADC_P_MUX3_1_1 0x12 -#define VADC_P_MUX4_1_1 0x13 -#define VADC_P_MUX5_1_1 0x14 -#define VADC_P_MUX6_1_1 0x15 -#define VADC_P_MUX7_1_1 0x16 -#define VADC_P_MUX8_1_1 0x17 -#define VADC_P_MUX9_1_1 0x18 -#define VADC_P_MUX10_1_1 0x19 -#define VADC_P_MUX11_1_1 0x1a -#define VADC_P_MUX12_1_1 0x1b -#define VADC_P_MUX13_1_1 0x1c -#define VADC_P_MUX14_1_1 0x1d -#define VADC_P_MUX15_1_1 0x1e -#define VADC_P_MUX16_1_1 0x1f - -#define VADC_P_MUX1_1_3 0x20 -#define VADC_P_MUX2_1_3 0x21 -#define VADC_P_MUX3_1_3 0x22 -#define VADC_P_MUX4_1_3 0x23 -#define VADC_P_MUX5_1_3 0x24 -#define VADC_P_MUX6_1_3 0x25 -#define VADC_P_MUX7_1_3 0x26 -#define VADC_P_MUX8_1_3 0x27 -#define VADC_P_MUX9_1_3 0x28 -#define VADC_P_MUX10_1_3 0x29 -#define VADC_P_MUX11_1_3 0x2a -#define VADC_P_MUX12_1_3 0x2b -#define VADC_P_MUX13_1_3 0x2c -#define VADC_P_MUX14_1_3 0x2d -#define VADC_P_MUX15_1_3 0x2e -#define VADC_P_MUX16_1_3 0x2f - -#define VADC_LR_MUX1_BAT_THERM 0x30 -#define VADC_LR_MUX2_BAT_ID 0x31 -#define VADC_LR_MUX3_XO_THERM 0x32 -#define VADC_LR_MUX4_AMUX_THM1 0x33 -#define VADC_LR_MUX5_AMUX_THM2 0x34 -#define VADC_LR_MUX6_AMUX_THM3 0x35 -#define VADC_LR_MUX7_HW_ID 0x36 -#define VADC_LR_MUX8_AMUX_THM4 0x37 -#define VADC_LR_MUX9_AMUX_THM5 0x38 -#define VADC_LR_MUX10_USB_ID 0x39 -#define VADC_AMUX_PU1 0x3a -#define VADC_AMUX_PU2 0x3b -#define VADC_LR_MUX3_BUF_XO_THERM 0x3c - -#define VADC_LR_MUX1_PU1_BAT_THERM 0x70 -#define VADC_LR_MUX2_PU1_BAT_ID 0x71 -#define VADC_LR_MUX3_PU1_XO_THERM 0x72 -#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73 -#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74 -#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75 -#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76 -#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77 -#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78 -#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79 -#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c - -#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0 -#define VADC_LR_MUX2_PU2_BAT_ID 0xb1 -#define VADC_LR_MUX3_PU2_XO_THERM 0xb2 -#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3 -#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4 -#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5 -#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6 -#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7 -#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8 -#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9 -#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc - -#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0 -#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1 -#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2 -#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3 -#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4 -#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5 -#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6 -#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7 -#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8 -#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 -#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc - -/* ADC channels for SPMI PMIC5 */ - -#define ADC5_REF_GND 0x00 -#define ADC5_1P25VREF 0x01 -#define ADC5_VREF_VADC 0x02 -#define ADC5_VREF_VADC5_DIV_3 0x82 -#define ADC5_VPH_PWR 0x83 -#define ADC5_VBAT_SNS 0x84 -#define ADC5_VCOIN 0x85 -#define ADC5_DIE_TEMP 0x06 -#define ADC5_USB_IN_I 0x07 -#define ADC5_USB_IN_V_16 0x08 -#define ADC5_CHG_TEMP 0x09 -#define ADC5_BAT_THERM 0x0a -#define ADC5_BAT_ID 0x0b -#define ADC5_XO_THERM 0x0c -#define ADC5_AMUX_THM1 0x0d -#define ADC5_AMUX_THM2 0x0e -#define ADC5_AMUX_THM3 0x0f -#define ADC5_AMUX_THM4 0x10 -#define ADC5_AMUX_THM5 0x11 -#define ADC5_GPIO1 0x12 -#define ADC5_GPIO2 0x13 -#define ADC5_GPIO3 0x14 -#define ADC5_GPIO4 0x15 -#define ADC5_GPIO5 0x16 -#define ADC5_GPIO6 0x17 -#define ADC5_GPIO7 0x18 -#define ADC5_SBUx 0x99 -#define ADC5_MID_CHG_DIV6 0x1e -#define ADC5_OFF 0xff - -/* 30k pull-up1 */ -#define ADC5_BAT_THERM_30K_PU 0x2a -#define ADC5_BAT_ID_30K_PU 0x2b -#define ADC5_XO_THERM_30K_PU 0x2c -#define ADC5_AMUX_THM1_30K_PU 0x2d -#define ADC5_AMUX_THM2_30K_PU 0x2e -#define ADC5_AMUX_THM3_30K_PU 0x2f -#define ADC5_AMUX_THM4_30K_PU 0x30 -#define ADC5_AMUX_THM5_30K_PU 0x31 -#define ADC5_GPIO1_30K_PU 0x32 -#define ADC5_GPIO2_30K_PU 0x33 -#define ADC5_GPIO3_30K_PU 0x34 -#define ADC5_GPIO4_30K_PU 0x35 -#define ADC5_GPIO5_30K_PU 0x36 -#define ADC5_GPIO6_30K_PU 0x37 -#define ADC5_GPIO7_30K_PU 0x38 -#define ADC5_SBUx_30K_PU 0x39 - -/* 100k pull-up2 */ -#define ADC5_BAT_THERM_100K_PU 0x4a -#define ADC5_BAT_ID_100K_PU 0x4b -#define ADC5_XO_THERM_100K_PU 0x4c -#define ADC5_AMUX_THM1_100K_PU 0x4d -#define ADC5_AMUX_THM2_100K_PU 0x4e -#define ADC5_AMUX_THM3_100K_PU 0x4f -#define ADC5_AMUX_THM4_100K_PU 0x50 -#define ADC5_AMUX_THM5_100K_PU 0x51 -#define ADC5_GPIO1_100K_PU 0x52 -#define ADC5_GPIO2_100K_PU 0x53 -#define ADC5_GPIO3_100K_PU 0x54 -#define ADC5_GPIO4_100K_PU 0x55 -#define ADC5_GPIO5_100K_PU 0x56 -#define ADC5_GPIO6_100K_PU 0x57 -#define ADC5_GPIO7_100K_PU 0x58 -#define ADC5_SBUx_100K_PU 0x59 - -/* 400k pull-up3 */ -#define ADC5_BAT_THERM_400K_PU 0x6a -#define ADC5_BAT_ID_400K_PU 0x6b -#define ADC5_XO_THERM_400K_PU 0x6c -#define ADC5_AMUX_THM1_400K_PU 0x6d -#define ADC5_AMUX_THM2_400K_PU 0x6e -#define ADC5_AMUX_THM3_400K_PU 0x6f -#define ADC5_AMUX_THM4_400K_PU 0x70 -#define ADC5_AMUX_THM5_400K_PU 0x71 -#define ADC5_GPIO1_400K_PU 0x72 -#define ADC5_GPIO2_400K_PU 0x73 -#define ADC5_GPIO3_400K_PU 0x74 -#define ADC5_GPIO4_400K_PU 0x75 -#define ADC5_GPIO5_400K_PU 0x76 -#define ADC5_GPIO6_400K_PU 0x77 -#define ADC5_GPIO7_400K_PU 0x78 -#define ADC5_SBUx_400K_PU 0x79 - -/* 1/3 Divider */ -#define ADC5_GPIO1_DIV3 0x92 -#define ADC5_GPIO2_DIV3 0x93 -#define ADC5_GPIO3_DIV3 0x94 -#define ADC5_GPIO4_DIV3 0x95 -#define ADC5_GPIO5_DIV3 0x96 -#define ADC5_GPIO6_DIV3 0x97 -#define ADC5_GPIO7_DIV3 0x98 -#define ADC5_SBUx_DIV3 0x99 - -/* Current and combined current/voltage channels */ -#define ADC5_INT_EXT_ISENSE 0xa1 -#define ADC5_PARALLEL_ISENSE 0xa5 -#define ADC5_CUR_REPLICA_VDS 0xa7 -#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9 -#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab -#define ADC5_EXT_SENS_OFFSET 0xad - -#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0 -#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1 -#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2 -#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3 -#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4 -#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5 - -#define ADC5_MAX_CHANNEL 0xc0 - -/* ADC channels for ADC for PMIC7 */ - -#define ADC7_REF_GND 0x00 -#define ADC7_1P25VREF 0x01 -#define ADC7_VREF_VADC 0x02 -#define ADC7_DIE_TEMP 0x03 - -#define ADC7_AMUX_THM1 0x04 -#define ADC7_AMUX_THM2 0x05 -#define ADC7_AMUX_THM3 0x06 -#define ADC7_AMUX_THM4 0x07 -#define ADC7_AMUX_THM5 0x08 -#define ADC7_AMUX_THM6 0x09 -#define ADC7_GPIO1 0x0a -#define ADC7_GPIO2 0x0b -#define ADC7_GPIO3 0x0c -#define ADC7_GPIO4 0x0d - -#define ADC7_CHG_TEMP 0x10 -#define ADC7_USB_IN_V_16 0x11 -#define ADC7_VDC_16 0x12 -#define ADC7_CC1_ID 0x13 -#define ADC7_VREF_BAT_THERM 0x15 -#define ADC7_IIN_FB 0x17 - -/* 30k pull-up1 */ -#define ADC7_AMUX_THM1_30K_PU 0x24 -#define ADC7_AMUX_THM2_30K_PU 0x25 -#define ADC7_AMUX_THM3_30K_PU 0x26 -#define ADC7_AMUX_THM4_30K_PU 0x27 -#define ADC7_AMUX_THM5_30K_PU 0x28 -#define ADC7_AMUX_THM6_30K_PU 0x29 -#define ADC7_GPIO1_30K_PU 0x2a -#define ADC7_GPIO2_30K_PU 0x2b -#define ADC7_GPIO3_30K_PU 0x2c -#define ADC7_GPIO4_30K_PU 0x2d -#define ADC7_CC1_ID_30K_PU 0x33 - -/* 100k pull-up2 */ -#define ADC7_AMUX_THM1_100K_PU 0x44 -#define ADC7_AMUX_THM2_100K_PU 0x45 -#define ADC7_AMUX_THM3_100K_PU 0x46 -#define ADC7_AMUX_THM4_100K_PU 0x47 -#define ADC7_AMUX_THM5_100K_PU 0x48 -#define ADC7_AMUX_THM6_100K_PU 0x49 -#define ADC7_GPIO1_100K_PU 0x4a -#define ADC7_GPIO2_100K_PU 0x4b -#define ADC7_GPIO3_100K_PU 0x4c -#define ADC7_GPIO4_100K_PU 0x4d -#define ADC7_CC1_ID_100K_PU 0x53 - -/* 400k pull-up3 */ -#define ADC7_AMUX_THM1_400K_PU 0x64 -#define ADC7_AMUX_THM2_400K_PU 0x65 -#define ADC7_AMUX_THM3_400K_PU 0x66 -#define ADC7_AMUX_THM4_400K_PU 0x67 -#define ADC7_AMUX_THM5_400K_PU 0x68 -#define ADC7_AMUX_THM6_400K_PU 0x69 -#define ADC7_GPIO1_400K_PU 0x6a -#define ADC7_GPIO2_400K_PU 0x6b -#define ADC7_GPIO3_400K_PU 0x6c -#define ADC7_GPIO4_400K_PU 0x6d -#define ADC7_CC1_ID_400K_PU 0x73 - -/* 1/3 Divider */ -#define ADC7_GPIO1_DIV3 0x8a -#define ADC7_GPIO2_DIV3 0x8b -#define ADC7_GPIO3_DIV3 0x8c -#define ADC7_GPIO4_DIV3 0x8d - -#define ADC7_VPH_PWR 0x8e -#define ADC7_VBAT_SNS 0x8f - -#define ADC7_SBUx 0x94 -#define ADC7_VBAT_2S_MID 0x96 - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ diff --git a/include/dt-bindings/interconnect/qcom,msm8916.h b/include/dt-bindings/interconnect/qcom,msm8916.h deleted file mode 100644 index 359a75feb19..00000000000 --- a/include/dt-bindings/interconnect/qcom,msm8916.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm interconnect IDs - * - * Copyright (c) 2019, Linaro Ltd. - * Author: Georgi Djakov <georgi.djakov@linaro.org> - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H -#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8916_H - -#define BIMC_SNOC_SLV 0 -#define MASTER_JPEG 1 -#define MASTER_MDP_PORT0 2 -#define MASTER_QDSS_BAM 3 -#define MASTER_QDSS_ETR 4 -#define MASTER_SNOC_CFG 5 -#define MASTER_VFE 6 -#define MASTER_VIDEO_P0 7 -#define SNOC_MM_INT_0 8 -#define SNOC_MM_INT_1 9 -#define SNOC_MM_INT_2 10 -#define SNOC_MM_INT_BIMC 11 -#define PCNOC_SNOC_SLV 12 -#define SLAVE_APSS 13 -#define SLAVE_CATS_128 14 -#define SLAVE_OCMEM_64 15 -#define SLAVE_IMEM 16 -#define SLAVE_QDSS_STM 17 -#define SLAVE_SRVC_SNOC 18 -#define SNOC_BIMC_0_MAS 19 -#define SNOC_BIMC_1_MAS 20 -#define SNOC_INT_0 21 -#define SNOC_INT_1 22 -#define SNOC_INT_BIMC 23 -#define SNOC_PCNOC_MAS 24 -#define SNOC_QDSS_INT 25 - -#define BIMC_SNOC_MAS 0 -#define MASTER_AMPSS_M0 1 -#define MASTER_GRAPHICS_3D 2 -#define MASTER_TCU0 3 -#define MASTER_TCU1 4 -#define SLAVE_AMPSS_L2 5 -#define SLAVE_EBI_CH0 6 -#define SNOC_BIMC_0_SLV 7 -#define SNOC_BIMC_1_SLV 8 - -#define MASTER_BLSP_1 0 -#define MASTER_DEHR 1 -#define MASTER_LPASS 2 -#define MASTER_CRYPTO_CORE0 3 -#define MASTER_SDCC_1 4 -#define MASTER_SDCC_2 5 -#define MASTER_SPDM 6 -#define MASTER_USB_HS 7 -#define PCNOC_INT_0 8 -#define PCNOC_INT_1 9 -#define PCNOC_MAS_0 10 -#define PCNOC_MAS_1 11 -#define PCNOC_SLV_0 12 -#define PCNOC_SLV_1 13 -#define PCNOC_SLV_2 14 -#define PCNOC_SLV_3 15 -#define PCNOC_SLV_4 16 -#define PCNOC_SLV_8 17 -#define PCNOC_SLV_9 18 -#define PCNOC_SNOC_MAS 19 -#define SLAVE_BIMC_CFG 20 -#define SLAVE_BLSP_1 21 -#define SLAVE_BOOT_ROM 22 -#define SLAVE_CAMERA_CFG 23 -#define SLAVE_CLK_CTL 24 -#define SLAVE_CRYPTO_0_CFG 25 -#define SLAVE_DEHR_CFG 26 -#define SLAVE_DISPLAY_CFG 27 -#define SLAVE_GRAPHICS_3D_CFG 28 -#define SLAVE_IMEM_CFG 29 -#define SLAVE_LPASS 30 -#define SLAVE_MPM 31 -#define SLAVE_MSG_RAM 32 -#define SLAVE_MSS 33 -#define SLAVE_PDM 34 -#define SLAVE_PMIC_ARB 35 -#define SLAVE_PCNOC_CFG 36 -#define SLAVE_PRNG 37 -#define SLAVE_QDSS_CFG 38 -#define SLAVE_RBCPR_CFG 39 -#define SLAVE_SDCC_1 40 -#define SLAVE_SDCC_2 41 -#define SLAVE_SECURITY 42 -#define SLAVE_SNOC_CFG 43 -#define SLAVE_SPDM 44 -#define SLAVE_TCSR 45 -#define SLAVE_TLMM 46 -#define SLAVE_USB_HS 47 -#define SLAVE_VENUS_CFG 48 -#define SNOC_PCNOC_SLV 49 - -#endif diff --git a/include/dt-bindings/interconnect/qcom,msm8996-cbf.h b/include/dt-bindings/interconnect/qcom,msm8996-cbf.h deleted file mode 100644 index aac5e69f6bd..00000000000 --- a/include/dt-bindings/interconnect/qcom,msm8996-cbf.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (C) 2023 Linaro Ltd. All rights reserved. - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_CBF_H -#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_CBF_H - -#define MASTER_CBF_M4M 0 -#define SLAVE_CBF_M4M 1 - -#endif diff --git a/include/dt-bindings/interconnect/qcom,msm8996.h b/include/dt-bindings/interconnect/qcom,msm8996.h deleted file mode 100644 index a0b7c0ec7be..00000000000 --- a/include/dt-bindings/interconnect/qcom,msm8996.h +++ /dev/null @@ -1,163 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ -/* - * Qualcomm MSM8996 interconnect IDs - * - * Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com> - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H -#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H - -/* A0NOC */ -#define MASTER_PCIE_0 0 -#define MASTER_PCIE_1 1 -#define MASTER_PCIE_2 2 - -/* A1NOC */ -#define MASTER_CNOC_A1NOC 0 -#define MASTER_CRYPTO_CORE0 1 -#define MASTER_PNOC_A1NOC 2 - -/* A2NOC */ -#define MASTER_USB3 0 -#define MASTER_IPA 1 -#define MASTER_UFS 2 - -/* BIMC */ -#define MASTER_AMPSS_M0 0 -#define MASTER_GRAPHICS_3D 1 -#define MASTER_MNOC_BIMC 2 -#define MASTER_SNOC_BIMC 3 -#define SLAVE_EBI_CH0 4 -#define SLAVE_HMSS_L3 5 -#define SLAVE_BIMC_SNOC_0 6 -#define SLAVE_BIMC_SNOC_1 7 - -/* CNOC */ -#define MASTER_SNOC_CNOC 0 -#define MASTER_QDSS_DAP 1 -#define SLAVE_CNOC_A1NOC 2 -#define SLAVE_CLK_CTL 3 -#define SLAVE_TCSR 4 -#define SLAVE_TLMM 5 -#define SLAVE_CRYPTO_0_CFG 6 -#define SLAVE_MPM 7 -#define SLAVE_PIMEM_CFG 8 -#define SLAVE_IMEM_CFG 9 -#define SLAVE_MESSAGE_RAM 10 -#define SLAVE_BIMC_CFG 11 -#define SLAVE_PMIC_ARB 12 -#define SLAVE_PRNG 13 -#define SLAVE_DCC_CFG 14 -#define SLAVE_RBCPR_MX 15 -#define SLAVE_QDSS_CFG 16 -#define SLAVE_RBCPR_CX 17 -#define SLAVE_QDSS_RBCPR_APU 18 -#define SLAVE_CNOC_MNOC_CFG 19 -#define SLAVE_SNOC_CFG 20 -#define SLAVE_SNOC_MPU_CFG 21 -#define SLAVE_EBI1_PHY_CFG 22 -#define SLAVE_A0NOC_CFG 23 -#define SLAVE_PCIE_1_CFG 24 -#define SLAVE_PCIE_2_CFG 25 -#define SLAVE_PCIE_0_CFG 26 -#define SLAVE_PCIE20_AHB2PHY 27 -#define SLAVE_A0NOC_MPU_CFG 28 -#define SLAVE_UFS_CFG 29 -#define SLAVE_A1NOC_CFG 30 -#define SLAVE_A1NOC_MPU_CFG 31 -#define SLAVE_A2NOC_CFG 32 -#define SLAVE_A2NOC_MPU_CFG 33 -#define SLAVE_SSC_CFG 34 -#define SLAVE_A0NOC_SMMU_CFG 35 -#define SLAVE_A1NOC_SMMU_CFG 36 -#define SLAVE_A2NOC_SMMU_CFG 37 -#define SLAVE_LPASS_SMMU_CFG 38 -#define SLAVE_CNOC_MNOC_MMSS_CFG 39 - -/* MNOC */ -#define MASTER_CNOC_MNOC_CFG 0 -#define MASTER_CPP 1 -#define MASTER_JPEG 2 -#define MASTER_MDP_PORT0 3 -#define MASTER_MDP_PORT1 4 -#define MASTER_ROTATOR 5 -#define MASTER_VIDEO_P0 6 -#define MASTER_VFE 7 -#define MASTER_SNOC_VMEM 8 -#define MASTER_VIDEO_P0_OCMEM 9 -#define MASTER_CNOC_MNOC_MMSS_CFG 10 -#define SLAVE_MNOC_BIMC 11 -#define SLAVE_VMEM 12 -#define SLAVE_SERVICE_MNOC 13 -#define SLAVE_MMAGIC_CFG 14 -#define SLAVE_CPR_CFG 15 -#define SLAVE_MISC_CFG 16 -#define SLAVE_VENUS_THROTTLE_CFG 17 -#define SLAVE_VENUS_CFG 18 -#define SLAVE_VMEM_CFG 19 -#define SLAVE_DSA_CFG 20 -#define SLAVE_MMSS_CLK_CFG 21 -#define SLAVE_DSA_MPU_CFG 22 -#define SLAVE_MNOC_MPU_CFG 23 -#define SLAVE_DISPLAY_CFG 24 -#define SLAVE_DISPLAY_THROTTLE_CFG 25 -#define SLAVE_CAMERA_CFG 26 -#define SLAVE_CAMERA_THROTTLE_CFG 27 -#define SLAVE_GRAPHICS_3D_CFG 28 -#define SLAVE_SMMU_MDP_CFG 29 -#define SLAVE_SMMU_ROT_CFG 30 -#define SLAVE_SMMU_VENUS_CFG 31 -#define SLAVE_SMMU_CPP_CFG 32 -#define SLAVE_SMMU_JPEG_CFG 33 -#define SLAVE_SMMU_VFE_CFG 34 - -/* PNOC */ -#define MASTER_SNOC_PNOC 0 -#define MASTER_SDCC_1 1 -#define MASTER_SDCC_2 2 -#define MASTER_SDCC_4 3 -#define MASTER_USB_HS 4 -#define MASTER_BLSP_1 5 -#define MASTER_BLSP_2 6 -#define MASTER_TSIF 7 -#define SLAVE_PNOC_A1NOC 8 -#define SLAVE_USB_HS 9 -#define SLAVE_SDCC_2 10 -#define SLAVE_SDCC_4 11 -#define SLAVE_TSIF 12 -#define SLAVE_BLSP_2 13 -#define SLAVE_SDCC_1 14 -#define SLAVE_BLSP_1 15 -#define SLAVE_PDM 16 -#define SLAVE_AHB2PHY 17 - -/* SNOC */ -#define MASTER_HMSS 0 -#define MASTER_QDSS_BAM 1 -#define MASTER_SNOC_CFG 2 -#define MASTER_BIMC_SNOC_0 3 -#define MASTER_BIMC_SNOC_1 4 -#define MASTER_A0NOC_SNOC 5 -#define MASTER_A1NOC_SNOC 6 -#define MASTER_A2NOC_SNOC 7 -#define MASTER_QDSS_ETR 8 -#define SLAVE_A0NOC_SNOC 9 -#define SLAVE_A1NOC_SNOC 10 -#define SLAVE_A2NOC_SNOC 11 -#define SLAVE_HMSS 12 -#define SLAVE_LPASS 13 -#define SLAVE_USB3 14 -#define SLAVE_SNOC_BIMC 15 -#define SLAVE_SNOC_CNOC 16 -#define SLAVE_IMEM 17 -#define SLAVE_PIMEM 18 -#define SLAVE_SNOC_VMEM 19 -#define SLAVE_SNOC_PNOC 20 -#define SLAVE_QDSS_STM 21 -#define SLAVE_PCIE_0 22 -#define SLAVE_PCIE_1 23 -#define SLAVE_PCIE_2 24 -#define SLAVE_SERVICE_SNOC 25 - -#endif diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h deleted file mode 100644 index 61ef649ae56..00000000000 --- a/include/dt-bindings/interconnect/qcom,osm-l3.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 The Linux Foundation. All rights reserved. - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H -#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H - -#define MASTER_OSM_L3_APPS 0 -#define SLAVE_OSM_L3 1 - -#define MASTER_EPSS_L3_APPS 0 -#define SLAVE_EPSS_L3_SHARED 1 - -#endif diff --git a/include/dt-bindings/interconnect/qcom,sdm845.h b/include/dt-bindings/interconnect/qcom,sdm845.h deleted file mode 100644 index 67b500e2491..00000000000 --- a/include/dt-bindings/interconnect/qcom,sdm845.h +++ /dev/null @@ -1,150 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Qualcomm SDM845 interconnect IDs - * - * Copyright (c) 2018, Linaro Ltd. - * Author: Georgi Djakov <georgi.djakov@linaro.org> - */ - -#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H -#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H - -#define MASTER_A1NOC_CFG 0 -#define MASTER_TSIF 1 -#define MASTER_SDCC_2 2 -#define MASTER_SDCC_4 3 -#define MASTER_UFS_CARD 4 -#define MASTER_UFS_MEM 5 -#define MASTER_PCIE_0 6 -#define SLAVE_A1NOC_SNOC 7 -#define SLAVE_SERVICE_A1NOC 8 -#define SLAVE_ANOC_PCIE_A1NOC_SNOC 9 -#define MASTER_QUP_1 10 - -#define MASTER_A2NOC_CFG 0 -#define MASTER_QDSS_BAM 1 -#define MASTER_CNOC_A2NOC 2 -#define MASTER_CRYPTO 3 -#define MASTER_IPA 4 -#define MASTER_PCIE_1 5 -#define MASTER_QDSS_ETR 6 -#define MASTER_USB3_0 7 -#define MASTER_USB3_1 8 -#define SLAVE_A2NOC_SNOC 9 -#define SLAVE_ANOC_PCIE_SNOC 10 -#define SLAVE_SERVICE_A2NOC 11 -#define MASTER_QUP_2 12 - -#define MASTER_SPDM 0 -#define MASTER_TIC 1 -#define MASTER_SNOC_CNOC 2 -#define MASTER_QDSS_DAP 3 -#define SLAVE_A1NOC_CFG 4 -#define SLAVE_A2NOC_CFG 5 -#define SLAVE_AOP 6 -#define SLAVE_AOSS 7 -#define SLAVE_CAMERA_CFG 8 -#define SLAVE_CLK_CTL 9 -#define SLAVE_CDSP_CFG 10 -#define SLAVE_RBCPR_CX_CFG 11 -#define SLAVE_CRYPTO_0_CFG 12 -#define SLAVE_DCC_CFG 13 -#define SLAVE_CNOC_DDRSS 14 -#define SLAVE_DISPLAY_CFG 15 -#define SLAVE_GLM 16 -#define SLAVE_GFX3D_CFG 17 -#define SLAVE_IMEM_CFG 18 -#define SLAVE_IPA_CFG 19 -#define SLAVE_CNOC_MNOC_CFG 20 -#define SLAVE_PCIE_0_CFG 21 -#define SLAVE_PCIE_1_CFG 22 -#define SLAVE_PDM 23 -#define SLAVE_SOUTH_PHY_CFG 24 -#define SLAVE_PIMEM_CFG 25 -#define SLAVE_PRNG 26 -#define SLAVE_QDSS_CFG 27 -#define SLAVE_BLSP_2 28 -#define SLAVE_BLSP_1 29 -#define SLAVE_SDCC_2 30 -#define SLAVE_SDCC_4 31 -#define SLAVE_SNOC_CFG 32 -#define SLAVE_SPDM_WRAPPER 33 -#define SLAVE_SPSS_CFG 34 -#define SLAVE_TCSR 35 -#define SLAVE_TLMM_NORTH 36 -#define SLAVE_TLMM_SOUTH 37 -#define SLAVE_TSIF 38 -#define SLAVE_UFS_CARD_CFG 39 -#define SLAVE_UFS_MEM_CFG 40 -#define SLAVE_USB3_0 41 -#define SLAVE_USB3_1 42 -#define SLAVE_VENUS_CFG 43 -#define SLAVE_VSENSE_CTRL_CFG 44 -#define SLAVE_CNOC_A2NOC 45 -#define SLAVE_SERVICE_CNOC 46 - -#define MASTER_CNOC_DC_NOC 0 -#define SLAVE_LLCC_CFG 1 -#define SLAVE_MEM_NOC_CFG 2 - -#define MASTER_APPSS_PROC 0 -#define MASTER_GNOC_CFG 1 -#define SLAVE_GNOC_SNOC 2 -#define SLAVE_GNOC_MEM_NOC 3 -#define SLAVE_SERVICE_GNOC 4 - -#define MASTER_TCU_0 0 -#define MASTER_MEM_NOC_CFG 1 -#define MASTER_GNOC_MEM_NOC 2 -#define MASTER_MNOC_HF_MEM_NOC 3 -#define MASTER_MNOC_SF_MEM_NOC 4 -#define MASTER_SNOC_GC_MEM_NOC 5 -#define MASTER_SNOC_SF_MEM_NOC 6 -#define MASTER_GFX3D 7 -#define SLAVE_MSS_PROC_MS_MPU_CFG 8 -#define SLAVE_MEM_NOC_GNOC 9 -#define SLAVE_LLCC 10 -#define SLAVE_MEM_NOC_SNOC 11 -#define SLAVE_SERVICE_MEM_NOC 12 -#define MASTER_LLCC 13 -#define SLAVE_EBI1 14 - -#define MASTER_CNOC_MNOC_CFG 0 -#define MASTER_CAMNOC_HF0 1 -#define MASTER_CAMNOC_HF1 2 -#define MASTER_CAMNOC_SF 3 -#define MASTER_MDP0 4 -#define MASTER_MDP1 5 -#define MASTER_ROTATOR 6 -#define MASTER_VIDEO_P0 7 -#define MASTER_VIDEO_P1 8 -#define MASTER_VIDEO_PROC 9 -#define SLAVE_MNOC_SF_MEM_NOC 10 -#define SLAVE_MNOC_HF_MEM_NOC 11 -#define SLAVE_SERVICE_MNOC 12 -#define MASTER_CAMNOC_HF0_UNCOMP 13 -#define MASTER_CAMNOC_HF1_UNCOMP 14 -#define MASTER_CAMNOC_SF_UNCOMP 15 -#define SLAVE_CAMNOC_UNCOMP 16 - -#define MASTER_SNOC_CFG 0 -#define MASTER_A1NOC_SNOC 1 -#define MASTER_A2NOC_SNOC 2 -#define MASTER_GNOC_SNOC 3 -#define MASTER_MEM_NOC_SNOC 4 -#define MASTER_ANOC_PCIE_SNOC 5 -#define MASTER_PIMEM 6 -#define MASTER_GIC 7 -#define SLAVE_APPSS 8 -#define SLAVE_SNOC_CNOC 9 -#define SLAVE_SNOC_MEM_NOC_GC 10 -#define SLAVE_SNOC_MEM_NOC_SF 11 -#define SLAVE_IMEM 12 -#define SLAVE_PCIE_0 13 -#define SLAVE_PCIE_1 14 -#define SLAVE_PIMEM 15 -#define SLAVE_SERVICE_SNOC 16 -#define SLAVE_QDSS_STM 17 -#define SLAVE_TCU 18 - -#endif diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h deleted file mode 100644 index 35b6f69b7db..00000000000 --- a/include/dt-bindings/interrupt-controller/arm-gic.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR MIT */ -/* - * This header provides constants for the ARM GIC. - */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H - -#include <dt-bindings/interrupt-controller/irq.h> - -/* interrupt specifier cell 0 */ - -#define GIC_SPI 0 -#define GIC_PPI 1 - -/* - * Interrupt specifier cell 2. - * The flags in irq.h are valid, plus those below. - */ -#define GIC_CPU_MASK_RAW(x) ((x) << 8) -#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) - -#endif diff --git a/include/dt-bindings/phy/phy-qcom-qmp.h b/include/dt-bindings/phy/phy-qcom-qmp.h deleted file mode 100644 index 4edec4c5b22..00000000000 --- a/include/dt-bindings/phy/phy-qcom-qmp.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ -/* - * Qualcomm QMP PHY constants - * - * Copyright (C) 2022 Linaro Limited - */ - -#ifndef _DT_BINDINGS_PHY_QMP -#define _DT_BINDINGS_PHY_QMP - -/* QMP USB4-USB3-DP clocks */ -#define QMP_USB43DP_USB3_PIPE_CLK 0 -#define QMP_USB43DP_DP_LINK_CLK 1 -#define QMP_USB43DP_DP_VCO_DIV_CLK 2 - -/* QMP USB4-USB3-DP PHYs */ -#define QMP_USB43DP_USB3_PHY 0 -#define QMP_USB43DP_DP_PHY 1 - -#endif /* _DT_BINDINGS_PHY_QMP */ diff --git a/include/dt-bindings/phy/phy-qcom-qusb2.h b/include/dt-bindings/phy/phy-qcom-qusb2.h deleted file mode 100644 index 5c5e4d800ca..00000000000 --- a/include/dt-bindings/phy/phy-qcom-qusb2.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_QCOM_PHY_QUSB2_H_ -#define _DT_BINDINGS_QCOM_PHY_QUSB2_H_ - -/* PHY HSTX TRIM bit values (24mA to 15mA) */ -#define QUSB2_V2_HSTX_TRIM_24_0_MA 0x0 -#define QUSB2_V2_HSTX_TRIM_23_4_MA 0x1 -#define QUSB2_V2_HSTX_TRIM_22_8_MA 0x2 -#define QUSB2_V2_HSTX_TRIM_22_2_MA 0x3 -#define QUSB2_V2_HSTX_TRIM_21_6_MA 0x4 -#define QUSB2_V2_HSTX_TRIM_21_0_MA 0x5 -#define QUSB2_V2_HSTX_TRIM_20_4_MA 0x6 -#define QUSB2_V2_HSTX_TRIM_19_8_MA 0x7 -#define QUSB2_V2_HSTX_TRIM_19_2_MA 0x8 -#define QUSB2_V2_HSTX_TRIM_18_6_MA 0x9 -#define QUSB2_V2_HSTX_TRIM_18_0_MA 0xa -#define QUSB2_V2_HSTX_TRIM_17_4_MA 0xb -#define QUSB2_V2_HSTX_TRIM_16_8_MA 0xc -#define QUSB2_V2_HSTX_TRIM_16_2_MA 0xd -#define QUSB2_V2_HSTX_TRIM_15_6_MA 0xe -#define QUSB2_V2_HSTX_TRIM_15_0_MA 0xf - -/* PHY PREEMPHASIS bit values */ -#define QUSB2_V2_PREEMPHASIS_NONE 0 -#define QUSB2_V2_PREEMPHASIS_5_PERCENT 1 -#define QUSB2_V2_PREEMPHASIS_10_PERCENT 2 -#define QUSB2_V2_PREEMPHASIS_15_PERCENT 3 - -/* PHY PREEMPHASIS-WIDTH bit values */ -#define QUSB2_V2_PREEMPHASIS_WIDTH_FULL_BIT 0 -#define QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT 1 - -#endif diff --git a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h deleted file mode 100644 index e5df5ce45a0..00000000000 --- a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h +++ /dev/null @@ -1,164 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the Qualcomm PMIC GPIO binding. - */ - -#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H -#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H - -#define PMIC_GPIO_PULL_UP_30 0 -#define PMIC_GPIO_PULL_UP_1P5 1 -#define PMIC_GPIO_PULL_UP_31P5 2 -#define PMIC_GPIO_PULL_UP_1P5_30 3 - -#define PMIC_GPIO_STRENGTH_NO 0 -#define PMIC_GPIO_STRENGTH_HIGH 1 -#define PMIC_GPIO_STRENGTH_MED 2 -#define PMIC_GPIO_STRENGTH_LOW 3 - -/* - * Note: PM8018 GPIO3 and GPIO4 are supporting - * only S3 and L2 options (1.8V) - */ -#define PM8018_GPIO_L6 0 -#define PM8018_GPIO_L5 1 -#define PM8018_GPIO_S3 2 -#define PM8018_GPIO_L14 3 -#define PM8018_GPIO_L2 4 -#define PM8018_GPIO_L4 5 -#define PM8018_GPIO_VDD 6 - -/* - * Note: PM8038 GPIO7 and GPIO8 are supporting - * only L11 and L4 options (1.8V) - */ -#define PM8038_GPIO_VPH 0 -#define PM8038_GPIO_BB 1 -#define PM8038_GPIO_L11 2 -#define PM8038_GPIO_L15 3 -#define PM8038_GPIO_L4 4 -#define PM8038_GPIO_L3 5 -#define PM8038_GPIO_L17 6 - -#define PM8058_GPIO_VPH 0 -#define PM8058_GPIO_BB 1 -#define PM8058_GPIO_S3 2 -#define PM8058_GPIO_L3 3 -#define PM8058_GPIO_L7 4 -#define PM8058_GPIO_L6 5 -#define PM8058_GPIO_L5 6 -#define PM8058_GPIO_L2 7 - -/* - * Note: PM8916 GPIO1 and GPIO2 are supporting - * only L2(1.15V) and L5(1.8V) options - */ -#define PM8916_GPIO_VPH 0 -#define PM8916_GPIO_L2 2 -#define PM8916_GPIO_L5 3 - -#define PM8917_GPIO_VPH 0 -#define PM8917_GPIO_S4 2 -#define PM8917_GPIO_L15 3 -#define PM8917_GPIO_L4 4 -#define PM8917_GPIO_L3 5 -#define PM8917_GPIO_L17 6 - -#define PM8921_GPIO_VPH 0 -#define PM8921_GPIO_BB 1 -#define PM8921_GPIO_S4 2 -#define PM8921_GPIO_L15 3 -#define PM8921_GPIO_L4 4 -#define PM8921_GPIO_L3 5 -#define PM8921_GPIO_L17 6 - -/* - * Note: PM8941 gpios from 15 to 18 are supporting - * only S3 and L6 options (1.8V) - */ -#define PM8941_GPIO_VPH 0 -#define PM8941_GPIO_L1 1 -#define PM8941_GPIO_S3 2 -#define PM8941_GPIO_L6 3 - -/* - * Note: PMA8084 gpios from 15 to 18 are supporting - * only S4 and L6 options (1.8V) - */ -#define PMA8084_GPIO_VPH 0 -#define PMA8084_GPIO_L1 1 -#define PMA8084_GPIO_S4 2 -#define PMA8084_GPIO_L6 3 - -#define PM8994_GPIO_VPH 0 -#define PM8994_GPIO_S4 2 -#define PM8994_GPIO_L12 3 - -/* To be used with "function" */ -#define PMIC_GPIO_FUNC_NORMAL "normal" -#define PMIC_GPIO_FUNC_PAIRED "paired" -#define PMIC_GPIO_FUNC_FUNC1 "func1" -#define PMIC_GPIO_FUNC_FUNC2 "func2" -#define PMIC_GPIO_FUNC_FUNC3 "func3" -#define PMIC_GPIO_FUNC_FUNC4 "func4" -#define PMIC_GPIO_FUNC_DTEST1 "dtest1" -#define PMIC_GPIO_FUNC_DTEST2 "dtest2" -#define PMIC_GPIO_FUNC_DTEST3 "dtest3" -#define PMIC_GPIO_FUNC_DTEST4 "dtest4" - -#define PM8038_GPIO1_2_LPG_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO3_5V_BOOST_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO4_SSBI_ALT_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO5_6_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO10_11_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO6_7_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO9_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO6_12_KYPD_DRV PMIC_GPIO_FUNC_FUNC2 - -#define PM8058_GPIO7_8_MP3_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO7_8_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO9_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO24_26_LPG_DRV PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO33_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO34_35_MP3_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO36_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO37_UPL_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO37_UART_M_RX PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO38_39_CLK_32KHZ PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO39_MP3_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO40_EXT_BB_EN PMIC_GPIO_FUNC_FUNC1 - -#define PM8916_GPIO1_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8916_GPIO1_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 -#define PM8916_GPIO2_DIV_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8916_GPIO2_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 -#define PM8916_GPIO3_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8916_GPIO4_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 - -#define PM8917_GPIO9_18_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO20_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 -#define PM8917_GPIO25_26_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO37_38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO37_38_MP3_CLK PMIC_GPIO_FUNC_FUNC2 - -#define PM8941_GPIO9_14_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 -#define PM8941_GPIO23_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO23_26_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 -#define PM8941_GPIO31_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO33_36_LPG_DRV_3D PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO33_36_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 - -#define PMA8084_GPIO4_5_LPG_DRV PMIC_GPIO_FUNC_FUNC1 -#define PMA8084_GPIO7_10_LPG_DRV PMIC_GPIO_FUNC_FUNC1 -#define PMA8084_GPIO5_14_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 -#define PMA8084_GPIO19_21_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 -#define PMA8084_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 -#define PMA8084_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 -#define PMA8084_GPIO22_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 - -#endif diff --git a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h deleted file mode 100644 index 32e66ee7e83..00000000000 --- a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the Qualcomm PMIC's - * Multi-Purpose Pin binding. - */ - -#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H -#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H - -/* power-source */ - -/* Digital Input/Output: level [PM8058] */ -#define PM8058_MPP_VPH 0 -#define PM8058_MPP_S3 1 -#define PM8058_MPP_L2 2 -#define PM8058_MPP_L3 3 - -/* Digital Input/Output: level [PM8901] */ -#define PM8901_MPP_MSMIO 0 -#define PM8901_MPP_DIG 1 -#define PM8901_MPP_L5 2 -#define PM8901_MPP_S4 3 -#define PM8901_MPP_VPH 4 - -/* Digital Input/Output: level [PM8921] */ -#define PM8921_MPP_S4 1 -#define PM8921_MPP_L15 3 -#define PM8921_MPP_L17 4 -#define PM8921_MPP_VPH 7 - -/* Digital Input/Output: level [PM8821] */ -#define PM8821_MPP_1P8 0 -#define PM8821_MPP_VPH 7 - -/* Digital Input/Output: level [PM8018] */ -#define PM8018_MPP_L4 0 -#define PM8018_MPP_L14 1 -#define PM8018_MPP_S3 2 -#define PM8018_MPP_L6 3 -#define PM8018_MPP_L2 4 -#define PM8018_MPP_L5 5 -#define PM8018_MPP_VPH 7 - -/* Digital Input/Output: level [PM8038] */ -#define PM8038_MPP_L20 0 -#define PM8038_MPP_L11 1 -#define PM8038_MPP_L5 2 -#define PM8038_MPP_L15 3 -#define PM8038_MPP_L17 4 -#define PM8038_MPP_VPH 7 - -#define PM8841_MPP_VPH 0 -#define PM8841_MPP_S3 2 - -#define PM8916_MPP_VPH 0 -#define PM8916_MPP_L2 2 -#define PM8916_MPP_L5 3 - -#define PM8941_MPP_VPH 0 -#define PM8941_MPP_L1 1 -#define PM8941_MPP_S3 2 -#define PM8941_MPP_L6 3 - -#define PMA8084_MPP_VPH 0 -#define PMA8084_MPP_L1 1 -#define PMA8084_MPP_S4 2 -#define PMA8084_MPP_L6 3 - -#define PM8994_MPP_VPH 0 -/* Only supported for MPP_05-MPP_08 */ -#define PM8994_MPP_L19 1 -#define PM8994_MPP_S4 2 -#define PM8994_MPP_L12 3 - -/* - * Analog Input - Set the source for analog input. - * To be used with "qcom,amux-route" property - */ -#define PMIC_MPP_AMUX_ROUTE_CH5 0 -#define PMIC_MPP_AMUX_ROUTE_CH6 1 -#define PMIC_MPP_AMUX_ROUTE_CH7 2 -#define PMIC_MPP_AMUX_ROUTE_CH8 3 -#define PMIC_MPP_AMUX_ROUTE_ABUS1 4 -#define PMIC_MPP_AMUX_ROUTE_ABUS2 5 -#define PMIC_MPP_AMUX_ROUTE_ABUS3 6 -#define PMIC_MPP_AMUX_ROUTE_ABUS4 7 - -/* Analog Output: level */ -#define PMIC_MPP_AOUT_LVL_1V25 0 -#define PMIC_MPP_AOUT_LVL_1V25_2 1 -#define PMIC_MPP_AOUT_LVL_0V625 2 -#define PMIC_MPP_AOUT_LVL_0V3125 3 -#define PMIC_MPP_AOUT_LVL_MPP 4 -#define PMIC_MPP_AOUT_LVL_ABUS1 5 -#define PMIC_MPP_AOUT_LVL_ABUS2 6 -#define PMIC_MPP_AOUT_LVL_ABUS3 7 - -/* To be used with "function" */ -#define PMIC_MPP_FUNC_NORMAL "normal" -#define PMIC_MPP_FUNC_PAIRED "paired" -#define PMIC_MPP_FUNC_DTEST1 "dtest1" -#define PMIC_MPP_FUNC_DTEST2 "dtest2" -#define PMIC_MPP_FUNC_DTEST3 "dtest3" -#define PMIC_MPP_FUNC_DTEST4 "dtest4" - -#endif diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h deleted file mode 100644 index 8e39dfc0b62..00000000000 --- a/include/dt-bindings/power/meson-a1-power.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2023 SberDevices, Inc. - * Author: Alexey Romanov <avromanov@sberdevices.ru> - */ - -#ifndef _DT_BINDINGS_MESON_A1_POWER_H -#define _DT_BINDINGS_MESON_A1_POWER_H - -#define PWRC_DSPA_ID 8 -#define PWRC_DSPB_ID 9 -#define PWRC_UART_ID 10 -#define PWRC_DMC_ID 11 -#define PWRC_I2C_ID 12 -#define PWRC_PSRAM_ID 13 -#define PWRC_ACODEC_ID 14 -#define PWRC_AUDIO_ID 15 -#define PWRC_OTP_ID 16 -#define PWRC_DMA_ID 17 -#define PWRC_SD_EMMC_ID 18 -#define PWRC_RAMA_ID 19 -#define PWRC_RAMB_ID 20 -#define PWRC_IR_ID 21 -#define PWRC_SPICC_ID 22 -#define PWRC_SPIFC_ID 23 -#define PWRC_USB_ID 24 -#define PWRC_NIC_ID 25 -#define PWRC_PDMIN_ID 26 -#define PWRC_RSA_ID 27 -#define PWRC_MAX_ID 28 - -#endif diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h deleted file mode 100644 index 7f4e2983a4c..00000000000 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ /dev/null @@ -1,412 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ - -#ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H -#define _DT_BINDINGS_POWER_QCOM_RPMPD_H - -/* SA8775P Power Domain Indexes */ -#define SA8775P_CX 0 -#define SA8775P_CX_AO 1 -#define SA8775P_DDR 2 -#define SA8775P_EBI 3 -#define SA8775P_GFX 4 -#define SA8775P_LCX 5 -#define SA8775P_LMX 6 -#define SA8775P_MMCX 7 -#define SA8775P_MMCX_AO 8 -#define SA8775P_MSS 9 -#define SA8775P_MX 10 -#define SA8775P_MX_AO 11 -#define SA8775P_MXC 12 -#define SA8775P_MXC_AO 13 -#define SA8775P_NSP0 14 -#define SA8775P_NSP1 15 -#define SA8775P_XO 16 - -/* SDM670 Power Domain Indexes */ -#define SDM670_MX 0 -#define SDM670_MX_AO 1 -#define SDM670_CX 2 -#define SDM670_CX_AO 3 -#define SDM670_LMX 4 -#define SDM670_LCX 5 -#define SDM670_GFX 6 -#define SDM670_MSS 7 - -/* SDM845 Power Domain Indexes */ -#define SDM845_EBI 0 -#define SDM845_MX 1 -#define SDM845_MX_AO 2 -#define SDM845_CX 3 -#define SDM845_CX_AO 4 -#define SDM845_LMX 5 -#define SDM845_LCX 6 -#define SDM845_GFX 7 -#define SDM845_MSS 8 - -/* SDX55 Power Domain Indexes */ -#define SDX55_MSS 0 -#define SDX55_MX 1 -#define SDX55_CX 2 - -/* SDX65 Power Domain Indexes */ -#define SDX65_MSS 0 -#define SDX65_MX 1 -#define SDX65_MX_AO 2 -#define SDX65_CX 3 -#define SDX65_CX_AO 4 -#define SDX65_MXC 5 - -/* SM6350 Power Domain Indexes */ -#define SM6350_CX 0 -#define SM6350_GFX 1 -#define SM6350_LCX 2 -#define SM6350_LMX 3 -#define SM6350_MSS 4 -#define SM6350_MX 5 - -/* SM6350 Power Domain Indexes */ -#define SM6375_VDDCX 0 -#define SM6375_VDDCX_AO 1 -#define SM6375_VDDCX_VFL 2 -#define SM6375_VDDMX 3 -#define SM6375_VDDMX_AO 4 -#define SM6375_VDDMX_VFL 5 -#define SM6375_VDDGX 6 -#define SM6375_VDDGX_AO 7 -#define SM6375_VDD_LPI_CX 8 -#define SM6375_VDD_LPI_MX 9 - -/* SM8150 Power Domain Indexes */ -#define SM8150_MSS 0 -#define SM8150_EBI 1 -#define SM8150_LMX 2 -#define SM8150_LCX 3 -#define SM8150_GFX 4 -#define SM8150_MX 5 -#define SM8150_MX_AO 6 -#define SM8150_CX 7 -#define SM8150_CX_AO 8 -#define SM8150_MMCX 9 -#define SM8150_MMCX_AO 10 - -/* SA8155P is a special case, kept for backwards compatibility */ -#define SA8155P_CX SM8150_CX -#define SA8155P_CX_AO SM8150_CX_AO -#define SA8155P_EBI SM8150_EBI -#define SA8155P_GFX SM8150_GFX -#define SA8155P_MSS SM8150_MSS -#define SA8155P_MX SM8150_MX -#define SA8155P_MX_AO SM8150_MX_AO - -/* SM8250 Power Domain Indexes */ -#define SM8250_CX 0 -#define SM8250_CX_AO 1 -#define SM8250_EBI 2 -#define SM8250_GFX 3 -#define SM8250_LCX 4 -#define SM8250_LMX 5 -#define SM8250_MMCX 6 -#define SM8250_MMCX_AO 7 -#define SM8250_MX 8 -#define SM8250_MX_AO 9 - -/* SM8350 Power Domain Indexes */ -#define SM8350_CX 0 -#define SM8350_CX_AO 1 -#define SM8350_EBI 2 -#define SM8350_GFX 3 -#define SM8350_LCX 4 -#define SM8350_LMX 5 -#define SM8350_MMCX 6 -#define SM8350_MMCX_AO 7 -#define SM8350_MX 8 -#define SM8350_MX_AO 9 -#define SM8350_MXC 10 -#define SM8350_MXC_AO 11 -#define SM8350_MSS 12 - -/* SM8450 Power Domain Indexes */ -#define SM8450_CX 0 -#define SM8450_CX_AO 1 -#define SM8450_EBI 2 -#define SM8450_GFX 3 -#define SM8450_LCX 4 -#define SM8450_LMX 5 -#define SM8450_MMCX 6 -#define SM8450_MMCX_AO 7 -#define SM8450_MX 8 -#define SM8450_MX_AO 9 -#define SM8450_MXC 10 -#define SM8450_MXC_AO 11 -#define SM8450_MSS 12 - -/* SM8550 Power Domain Indexes */ -#define SM8550_CX 0 -#define SM8550_CX_AO 1 -#define SM8550_EBI 2 -#define SM8550_GFX 3 -#define SM8550_LCX 4 -#define SM8550_LMX 5 -#define SM8550_MMCX 6 -#define SM8550_MMCX_AO 7 -#define SM8550_MX 8 -#define SM8550_MX_AO 9 -#define SM8550_MXC 10 -#define SM8550_MXC_AO 11 -#define SM8550_MSS 12 -#define SM8550_NSP 13 - -/* QDU1000/QRU1000 Power Domain Indexes */ -#define QDU1000_EBI 0 -#define QDU1000_MSS 1 -#define QDU1000_CX 2 -#define QDU1000_MX 3 - -/* SC7180 Power Domain Indexes */ -#define SC7180_CX 0 -#define SC7180_CX_AO 1 -#define SC7180_GFX 2 -#define SC7180_MX 3 -#define SC7180_MX_AO 4 -#define SC7180_LMX 5 -#define SC7180_LCX 6 -#define SC7180_MSS 7 - -/* SC7280 Power Domain Indexes */ -#define SC7280_CX 0 -#define SC7280_CX_AO 1 -#define SC7280_EBI 2 -#define SC7280_GFX 3 -#define SC7280_MX 4 -#define SC7280_MX_AO 5 -#define SC7280_LMX 6 -#define SC7280_LCX 7 -#define SC7280_MSS 8 - -/* SC8180X Power Domain Indexes */ -#define SC8180X_CX 0 -#define SC8180X_CX_AO 1 -#define SC8180X_EBI 2 -#define SC8180X_GFX 3 -#define SC8180X_LCX 4 -#define SC8180X_LMX 5 -#define SC8180X_MMCX 6 -#define SC8180X_MMCX_AO 7 -#define SC8180X_MSS 8 -#define SC8180X_MX 9 -#define SC8180X_MX_AO 10 - -/* SC8280XP Power Domain Indexes */ -#define SC8280XP_CX 0 -#define SC8280XP_CX_AO 1 -#define SC8280XP_DDR 2 -#define SC8280XP_EBI 3 -#define SC8280XP_GFX 4 -#define SC8280XP_LCX 5 -#define SC8280XP_LMX 6 -#define SC8280XP_MMCX 7 -#define SC8280XP_MMCX_AO 8 -#define SC8280XP_MSS 9 -#define SC8280XP_MX 10 -#define SC8280XP_MXC 12 -#define SC8280XP_MX_AO 11 -#define SC8280XP_NSP 13 -#define SC8280XP_QPHY 14 -#define SC8280XP_XO 15 - -/* SDM845 Power Domain performance levels */ -#define RPMH_REGULATOR_LEVEL_RETENTION 16 -#define RPMH_REGULATOR_LEVEL_MIN_SVS 48 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60 -#define RPMH_REGULATOR_LEVEL_LOW_SVS 64 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96 -#define RPMH_REGULATOR_LEVEL_SVS 128 -#define RPMH_REGULATOR_LEVEL_SVS_L0 144 -#define RPMH_REGULATOR_LEVEL_SVS_L1 192 -#define RPMH_REGULATOR_LEVEL_SVS_L2 224 -#define RPMH_REGULATOR_LEVEL_NOM 256 -#define RPMH_REGULATOR_LEVEL_NOM_L0 288 -#define RPMH_REGULATOR_LEVEL_NOM_L1 320 -#define RPMH_REGULATOR_LEVEL_NOM_L2 336 -#define RPMH_REGULATOR_LEVEL_TURBO 384 -#define RPMH_REGULATOR_LEVEL_TURBO_L0 400 -#define RPMH_REGULATOR_LEVEL_TURBO_L1 416 -#define RPMH_REGULATOR_LEVEL_TURBO_L2 432 -#define RPMH_REGULATOR_LEVEL_TURBO_L3 448 -#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464 -#define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR 480 - -/* MDM9607 Power Domains */ -#define MDM9607_VDDCX 0 -#define MDM9607_VDDCX_AO 1 -#define MDM9607_VDDCX_VFL 2 -#define MDM9607_VDDMX 3 -#define MDM9607_VDDMX_AO 4 -#define MDM9607_VDDMX_VFL 5 - -/* MSM8226 Power Domain Indexes */ -#define MSM8226_VDDCX 0 -#define MSM8226_VDDCX_AO 1 -#define MSM8226_VDDCX_VFC 2 - -/* MSM8939 Power Domains */ -#define MSM8939_VDDMDCX 0 -#define MSM8939_VDDMDCX_AO 1 -#define MSM8939_VDDMDCX_VFC 2 -#define MSM8939_VDDCX 3 -#define MSM8939_VDDCX_AO 4 -#define MSM8939_VDDCX_VFC 5 -#define MSM8939_VDDMX 6 -#define MSM8939_VDDMX_AO 7 - -/* MSM8916 Power Domain Indexes */ -#define MSM8916_VDDCX 0 -#define MSM8916_VDDCX_AO 1 -#define MSM8916_VDDCX_VFC 2 -#define MSM8916_VDDMX 3 -#define MSM8916_VDDMX_AO 4 - -/* MSM8909 Power Domain Indexes */ -#define MSM8909_VDDCX MSM8916_VDDCX -#define MSM8909_VDDCX_AO MSM8916_VDDCX_AO -#define MSM8909_VDDCX_VFC MSM8916_VDDCX_VFC -#define MSM8909_VDDMX MSM8916_VDDMX -#define MSM8909_VDDMX_AO MSM8916_VDDMX_AO - -/* MSM8917 Power Domain Indexes */ -#define MSM8917_VDDCX 0 -#define MSM8917_VDDCX_AO 1 -#define MSM8917_VDDCX_VFL 2 -#define MSM8917_VDDMX 3 -#define MSM8917_VDDMX_AO 4 - -/* MSM8937 Power Domain Indexes */ -#define MSM8937_VDDCX MSM8917_VDDCX -#define MSM8937_VDDCX_AO MSM8917_VDDCX_AO -#define MSM8937_VDDCX_VFL MSM8917_VDDCX_VFL -#define MSM8937_VDDMX MSM8917_VDDMX -#define MSM8937_VDDMX_AO MSM8917_VDDMX_AO - -/* QM215 Power Domain Indexes */ -#define QM215_VDDCX MSM8917_VDDCX -#define QM215_VDDCX_AO MSM8917_VDDCX_AO -#define QM215_VDDCX_VFL MSM8917_VDDCX_VFL -#define QM215_VDDMX MSM8917_VDDMX -#define QM215_VDDMX_AO MSM8917_VDDMX_AO - -/* MSM8953 Power Domain Indexes */ -#define MSM8953_VDDMD 0 -#define MSM8953_VDDMD_AO 1 -#define MSM8953_VDDCX 2 -#define MSM8953_VDDCX_AO 3 -#define MSM8953_VDDCX_VFL 4 -#define MSM8953_VDDMX 5 -#define MSM8953_VDDMX_AO 6 - -/* MSM8976 Power Domain Indexes */ -#define MSM8976_VDDCX 0 -#define MSM8976_VDDCX_AO 1 -#define MSM8976_VDDCX_VFL 2 -#define MSM8976_VDDMX 3 -#define MSM8976_VDDMX_AO 4 -#define MSM8976_VDDMX_VFL 5 - -/* MSM8994 Power Domain Indexes */ -#define MSM8994_VDDCX 0 -#define MSM8994_VDDCX_AO 1 -#define MSM8994_VDDCX_VFC 2 -#define MSM8994_VDDMX 3 -#define MSM8994_VDDMX_AO 4 -#define MSM8994_VDDGFX 5 -#define MSM8994_VDDGFX_VFC 6 - -/* MSM8996 Power Domain Indexes */ -#define MSM8996_VDDCX 0 -#define MSM8996_VDDCX_AO 1 -#define MSM8996_VDDCX_VFC 2 -#define MSM8996_VDDMX 3 -#define MSM8996_VDDMX_AO 4 -#define MSM8996_VDDSSCX 5 -#define MSM8996_VDDSSCX_VFC 6 - -/* MSM8998 Power Domain Indexes */ -#define MSM8998_VDDCX 0 -#define MSM8998_VDDCX_AO 1 -#define MSM8998_VDDCX_VFL 2 -#define MSM8998_VDDMX 3 -#define MSM8998_VDDMX_AO 4 -#define MSM8998_VDDMX_VFL 5 -#define MSM8998_SSCCX 6 -#define MSM8998_SSCCX_VFL 7 -#define MSM8998_SSCMX 8 -#define MSM8998_SSCMX_VFL 9 - -/* QCS404 Power Domains */ -#define QCS404_VDDMX 0 -#define QCS404_VDDMX_AO 1 -#define QCS404_VDDMX_VFL 2 -#define QCS404_LPICX 3 -#define QCS404_LPICX_VFL 4 -#define QCS404_LPIMX 5 -#define QCS404_LPIMX_VFL 6 - -/* SDM660 Power Domains */ -#define SDM660_VDDCX 0 -#define SDM660_VDDCX_AO 1 -#define SDM660_VDDCX_VFL 2 -#define SDM660_VDDMX 3 -#define SDM660_VDDMX_AO 4 -#define SDM660_VDDMX_VFL 5 -#define SDM660_SSCCX 6 -#define SDM660_SSCCX_VFL 7 -#define SDM660_SSCMX 8 -#define SDM660_SSCMX_VFL 9 - -/* SM6115 Power Domains */ -#define SM6115_VDDCX 0 -#define SM6115_VDDCX_AO 1 -#define SM6115_VDDCX_VFL 2 -#define SM6115_VDDMX 3 -#define SM6115_VDDMX_AO 4 -#define SM6115_VDDMX_VFL 5 -#define SM6115_VDD_LPI_CX 6 -#define SM6115_VDD_LPI_MX 7 - -/* SM6125 Power Domains */ -#define SM6125_VDDCX 0 -#define SM6125_VDDCX_AO 1 -#define SM6125_VDDCX_VFL 2 -#define SM6125_VDDMX 3 -#define SM6125_VDDMX_AO 4 -#define SM6125_VDDMX_VFL 5 - -/* QCM2290 Power Domains */ -#define QCM2290_VDDCX 0 -#define QCM2290_VDDCX_AO 1 -#define QCM2290_VDDCX_VFL 2 -#define QCM2290_VDDMX 3 -#define QCM2290_VDDMX_AO 4 -#define QCM2290_VDDMX_VFL 5 -#define QCM2290_VDD_LPI_CX 6 -#define QCM2290_VDD_LPI_MX 7 - -/* RPM SMD Power Domain performance levels */ -#define RPM_SMD_LEVEL_RETENTION 16 -#define RPM_SMD_LEVEL_RETENTION_PLUS 32 -#define RPM_SMD_LEVEL_MIN_SVS 48 -#define RPM_SMD_LEVEL_LOW_SVS 64 -#define RPM_SMD_LEVEL_SVS 128 -#define RPM_SMD_LEVEL_SVS_PLUS 192 -#define RPM_SMD_LEVEL_NOM 256 -#define RPM_SMD_LEVEL_NOM_PLUS 320 -#define RPM_SMD_LEVEL_TURBO 384 -#define RPM_SMD_LEVEL_TURBO_NO_CPR 416 -#define RPM_SMD_LEVEL_TURBO_HIGH 448 -#define RPM_SMD_LEVEL_BINNING 512 - -#endif diff --git a/include/dt-bindings/regulator/qcom,rpmh-regulator.h b/include/dt-bindings/regulator/qcom,rpmh-regulator.h deleted file mode 100644 index 86713dcf9e0..00000000000 --- a/include/dt-bindings/regulator/qcom,rpmh-regulator.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ - -#ifndef __QCOM_RPMH_REGULATOR_H -#define __QCOM_RPMH_REGULATOR_H - -/* - * These mode constants may be used to specify modes for various RPMh regulator - * device tree properties (e.g. regulator-initial-mode). Each type of regulator - * supports a subset of the possible modes. - * - * %RPMH_REGULATOR_MODE_RET: Retention mode in which only an extremely small - * load current is allowed. This mode is supported - * by LDO and SMPS type regulators. - * %RPMH_REGULATOR_MODE_LPM: Low power mode in which a small load current is - * allowed. This mode corresponds to PFM for SMPS - * and BOB type regulators. This mode is supported - * by LDO, HFSMPS, BOB, and PMIC4 FTSMPS type - * regulators. - * %RPMH_REGULATOR_MODE_AUTO: Auto mode in which the regulator hardware - * automatically switches between LPM and HPM based - * upon the real-time load current. This mode is - * supported by HFSMPS, BOB, and PMIC4 FTSMPS type - * regulators. - * %RPMH_REGULATOR_MODE_HPM: High power mode in which the full rated current - * of the regulator is allowed. This mode - * corresponds to PWM for SMPS and BOB type - * regulators. This mode is supported by all types - * of regulators. - */ -#define RPMH_REGULATOR_MODE_RET 0 -#define RPMH_REGULATOR_MODE_LPM 1 -#define RPMH_REGULATOR_MODE_AUTO 2 -#define RPMH_REGULATOR_MODE_HPM 3 - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h deleted file mode 100644 index 2c749c655e1..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-a1-reset.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen <xingyu.chen@amlogic.com> - * - * Copyright (c) 2023, SberDevices, Inc. - * Author: Alexey Romanov <avromanov@salutedevices.com> - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H - -/* RESET0 */ -/* 0 */ -#define RESET_AM2AXI_VAD 1 -/* 2-3 */ -#define RESET_PSRAM 4 -#define RESET_PAD_CTRL 5 -/* 6 */ -#define RESET_TEMP_SENSOR 7 -#define RESET_AM2AXI_DEV 8 -/* 9 */ -#define RESET_SPICC_A 10 -#define RESET_MSR_CLK 11 -#define RESET_AUDIO 12 -#define RESET_ANALOG_CTRL 13 -#define RESET_SAR_ADC 14 -#define RESET_AUDIO_VAD 15 -#define RESET_CEC 16 -#define RESET_PWM_EF 17 -#define RESET_PWM_CD 18 -#define RESET_PWM_AB 19 -/* 20 */ -#define RESET_IR_CTRL 21 -#define RESET_I2C_S_A 22 -/* 23 */ -#define RESET_I2C_M_D 24 -#define RESET_I2C_M_C 25 -#define RESET_I2C_M_B 26 -#define RESET_I2C_M_A 27 -#define RESET_I2C_PROD_AHB 28 -#define RESET_I2C_PROD 29 -/* 30-31 */ - -/* RESET1 */ -#define RESET_ACODEC 32 -#define RESET_DMA 33 -#define RESET_SD_EMMC_A 34 -/* 35 */ -#define RESET_USBCTRL 36 -/* 37 */ -#define RESET_USBPHY 38 -/* 39-41 */ -#define RESET_RSA 42 -#define RESET_DMC 43 -/* 44 */ -#define RESET_IRQ_CTRL 45 -/* 46 */ -#define RESET_NIC_VAD 47 -#define RESET_NIC_AXI 48 -#define RESET_RAMA 49 -#define RESET_RAMB 50 -/* 51-52 */ -#define RESET_ROM 53 -#define RESET_SPIFC 54 -#define RESET_GIC 55 -#define RESET_UART_C 56 -#define RESET_UART_B 57 -#define RESET_UART_A 58 -#define RESET_OSC_RING 59 -/* 60-63 */ - -/* RESET2 */ -/* 64-95 */ - -#endif diff --git a/include/dt-bindings/reset/qcom,gcc-msm8916.h b/include/dt-bindings/reset/qcom,gcc-msm8916.h deleted file mode 100644 index 1f9be10872d..00000000000 --- a/include/dt-bindings/reset/qcom,gcc-msm8916.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2015 Linaro Limited - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H -#define _DT_BINDINGS_RESET_MSM_GCC_8916_H - -#define GCC_BLSP1_BCR 0 -#define GCC_BLSP1_QUP1_BCR 1 -#define GCC_BLSP1_UART1_BCR 2 -#define GCC_BLSP1_QUP2_BCR 3 -#define GCC_BLSP1_UART2_BCR 4 -#define GCC_BLSP1_QUP3_BCR 5 -#define GCC_BLSP1_QUP4_BCR 6 -#define GCC_BLSP1_QUP5_BCR 7 -#define GCC_BLSP1_QUP6_BCR 8 -#define GCC_IMEM_BCR 9 -#define GCC_SMMU_BCR 10 -#define GCC_APSS_TCU_BCR 11 -#define GCC_SMMU_XPU_BCR 12 -#define GCC_PCNOC_TBU_BCR 13 -#define GCC_PRNG_BCR 14 -#define GCC_BOOT_ROM_BCR 15 -#define GCC_CRYPTO_BCR 16 -#define GCC_SEC_CTRL_BCR 17 -#define GCC_AUDIO_CORE_BCR 18 -#define GCC_ULT_AUDIO_BCR 19 -#define GCC_DEHR_BCR 20 -#define GCC_SYSTEM_NOC_BCR 21 -#define GCC_PCNOC_BCR 22 -#define GCC_TCSR_BCR 23 -#define GCC_QDSS_BCR 24 -#define GCC_DCD_BCR 25 -#define GCC_MSG_RAM_BCR 26 -#define GCC_MPM_BCR 27 -#define GCC_SPMI_BCR 28 -#define GCC_SPDM_BCR 29 -#define GCC_MM_SPDM_BCR 30 -#define GCC_BIMC_BCR 31 -#define GCC_RBCPR_BCR 32 -#define GCC_TLMM_BCR 33 -#define GCC_USB_HS_BCR 34 -#define GCC_USB2A_PHY_BCR 35 -#define GCC_SDCC1_BCR 36 -#define GCC_SDCC2_BCR 37 -#define GCC_PDM_BCR 38 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 39 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 40 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 41 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 42 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 43 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 44 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 45 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 46 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 47 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 48 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 49 -#define GCC_MMSS_BCR 50 -#define GCC_VENUS0_BCR 51 -#define GCC_MDSS_BCR 52 -#define GCC_CAMSS_PHY0_BCR 53 -#define GCC_CAMSS_CSI0_BCR 54 -#define GCC_CAMSS_CSI0PHY_BCR 55 -#define GCC_CAMSS_CSI0RDI_BCR 56 -#define GCC_CAMSS_CSI0PIX_BCR 57 -#define GCC_CAMSS_PHY1_BCR 58 -#define GCC_CAMSS_CSI1_BCR 59 -#define GCC_CAMSS_CSI1PHY_BCR 60 -#define GCC_CAMSS_CSI1RDI_BCR 61 -#define GCC_CAMSS_CSI1PIX_BCR 62 -#define GCC_CAMSS_ISPIF_BCR 63 -#define GCC_CAMSS_CCI_BCR 64 -#define GCC_CAMSS_MCLK0_BCR 65 -#define GCC_CAMSS_MCLK1_BCR 66 -#define GCC_CAMSS_GP0_BCR 67 -#define GCC_CAMSS_GP1_BCR 68 -#define GCC_CAMSS_TOP_BCR 69 -#define GCC_CAMSS_MICRO_BCR 70 -#define GCC_CAMSS_JPEG_BCR 71 -#define GCC_CAMSS_VFE_BCR 72 -#define GCC_CAMSS_CSI_VFE0_BCR 73 -#define GCC_OXILI_BCR 74 -#define GCC_GMEM_BCR 75 -#define GCC_CAMSS_AHB_BCR 76 -#define GCC_MDP_TBU_BCR 77 -#define GCC_GFX_TBU_BCR 78 -#define GCC_GFX_TCU_BCR 79 -#define GCC_MSS_TBU_AXI_BCR 80 -#define GCC_MSS_TBU_GSS_AXI_BCR 81 -#define GCC_MSS_TBU_Q6_AXI_BCR 82 -#define GCC_GTCU_AHB_BCR 83 -#define GCC_SMMU_CFG_BCR 84 -#define GCC_VFE_TBU_BCR 85 -#define GCC_VENUS_TBU_BCR 86 -#define GCC_JPEG_TBU_BCR 87 -#define GCC_PRONTO_TBU_BCR 88 -#define GCC_SMMU_CATS_BCR 89 - -#endif diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h deleted file mode 100644 index 476c5fc873b..00000000000 --- a/include/dt-bindings/reset/qcom,sdm845-aoss.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H -#define _DT_BINDINGS_RESET_AOSS_SDM_845_H - -#define AOSS_CC_MSS_RESTART 0 -#define AOSS_CC_CAMSS_RESTART 1 -#define AOSS_CC_VENUS_RESTART 2 -#define AOSS_CC_GPU_RESTART 3 -#define AOSS_CC_DISPSS_RESTART 4 -#define AOSS_CC_WCSS_RESTART 5 -#define AOSS_CC_LPASS_RESTART 6 - -#endif diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h deleted file mode 100644 index 03a0c0eb814..00000000000 --- a/include/dt-bindings/reset/qcom,sdm845-pdc.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H -#define _DT_BINDINGS_RESET_PDC_SDM_845_H - -#define PDC_APPS_SYNC_RESET 0 -#define PDC_SP_SYNC_RESET 1 -#define PDC_AUDIO_SYNC_RESET 2 -#define PDC_SENSORS_SYNC_RESET 3 -#define PDC_AOP_SYNC_RESET 4 -#define PDC_DEBUG_SYNC_RESET 5 -#define PDC_GPU_SYNC_RESET 6 -#define PDC_DISPLAY_SYNC_RESET 7 -#define PDC_COMPUTE_SYNC_RESET 8 -#define PDC_MODEM_SYNC_RESET 9 -#define PDC_WLAN_RF_SYNC_RESET 10 -#define PDC_WPSS_SYNC_RESET 11 - -#endif diff --git a/include/dt-bindings/soc/qcom,apr.h b/include/dt-bindings/soc/qcom,apr.h deleted file mode 100644 index 006362400c0..00000000000 --- a/include/dt-bindings/soc/qcom,apr.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_QCOM_APR_H -#define __DT_BINDINGS_QCOM_APR_H - -/* Domain IDs */ -#define APR_DOMAIN_SIM 0x1 -#define APR_DOMAIN_PC 0x2 -#define APR_DOMAIN_MODEM 0x3 -#define APR_DOMAIN_ADSP 0x4 -#define APR_DOMAIN_APPS 0x5 -#define APR_DOMAIN_MAX 0x6 - -/* ADSP service IDs */ -#define APR_SVC_ADSP_CORE 0x3 -#define APR_SVC_AFE 0x4 -#define APR_SVC_VSM 0x5 -#define APR_SVC_VPM 0x6 -#define APR_SVC_ASM 0x7 -#define APR_SVC_ADM 0x8 -#define APR_SVC_ADSP_MVM 0x09 -#define APR_SVC_ADSP_CVS 0x0A -#define APR_SVC_ADSP_CVP 0x0B -#define APR_SVC_USM 0x0C -#define APR_SVC_LSM 0x0D -#define APR_SVC_VIDC 0x16 -#define APR_SVC_MAX 0x17 - -#endif /* __DT_BINDINGS_QCOM_APR_H */ diff --git a/include/dt-bindings/soc/qcom,rpmh-rsc.h b/include/dt-bindings/soc/qcom,rpmh-rsc.h deleted file mode 100644 index 868f998ea99..00000000000 --- a/include/dt-bindings/soc/qcom,rpmh-rsc.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - */ - -#ifndef __DT_QCOM_RPMH_RSC_H__ -#define __DT_QCOM_RPMH_RSC_H__ - -#define SLEEP_TCS 0 -#define WAKE_TCS 1 -#define ACTIVE_TCS 2 -#define CONTROL_TCS 3 - -#endif /* __DT_QCOM_RPMH_RSC_H__ */ diff --git a/include/dt-bindings/sound/qcom,lpass.h b/include/dt-bindings/sound/qcom,lpass.h deleted file mode 100644 index a9404c3b888..00000000000 --- a/include/dt-bindings/sound/qcom,lpass.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_QCOM_LPASS_H -#define __DT_QCOM_LPASS_H - -#define MI2S_PRIMARY 0 -#define MI2S_SECONDARY 1 -#define MI2S_TERTIARY 2 -#define MI2S_QUATERNARY 3 -#define MI2S_QUINARY 4 - -#define LPASS_DP_RX 5 - -#define LPASS_CDC_DMA_RX0 6 -#define LPASS_CDC_DMA_RX1 7 -#define LPASS_CDC_DMA_RX2 8 -#define LPASS_CDC_DMA_RX3 9 -#define LPASS_CDC_DMA_RX4 10 -#define LPASS_CDC_DMA_RX5 11 -#define LPASS_CDC_DMA_RX6 12 -#define LPASS_CDC_DMA_RX7 13 -#define LPASS_CDC_DMA_RX8 14 -#define LPASS_CDC_DMA_RX9 15 - -#define LPASS_CDC_DMA_TX0 16 -#define LPASS_CDC_DMA_TX1 17 -#define LPASS_CDC_DMA_TX2 18 -#define LPASS_CDC_DMA_TX3 19 -#define LPASS_CDC_DMA_TX4 20 -#define LPASS_CDC_DMA_TX5 21 -#define LPASS_CDC_DMA_TX6 22 -#define LPASS_CDC_DMA_TX7 23 -#define LPASS_CDC_DMA_TX8 24 - -#define LPASS_CDC_DMA_VA_TX0 25 -#define LPASS_CDC_DMA_VA_TX1 26 -#define LPASS_CDC_DMA_VA_TX2 27 -#define LPASS_CDC_DMA_VA_TX3 28 -#define LPASS_CDC_DMA_VA_TX4 29 -#define LPASS_CDC_DMA_VA_TX5 30 -#define LPASS_CDC_DMA_VA_TX6 31 -#define LPASS_CDC_DMA_VA_TX7 32 -#define LPASS_CDC_DMA_VA_TX8 33 - -#define LPASS_MCLK0 0 - -#endif /* __DT_QCOM_LPASS_H */ diff --git a/include/dt-bindings/sound/qcom,q6afe.h b/include/dt-bindings/sound/qcom,q6afe.h deleted file mode 100644 index 9d5d89cfabc..00000000000 --- a/include/dt-bindings/sound/qcom,q6afe.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_Q6_AFE_H__ -#define __DT_BINDINGS_Q6_AFE_H__ - -/* This file exists due to backward compatibility reasons, Please do not DELETE! */ - -#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> - -#endif /* __DT_BINDINGS_Q6_AFE_H__ */ diff --git a/include/dt-bindings/sound/qcom,q6asm.h b/include/dt-bindings/sound/qcom,q6asm.h deleted file mode 100644 index f59d74f1439..00000000000 --- a/include/dt-bindings/sound/qcom,q6asm.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_Q6_ASM_H__ -#define __DT_BINDINGS_Q6_ASM_H__ - -#define MSM_FRONTEND_DAI_MULTIMEDIA1 0 -#define MSM_FRONTEND_DAI_MULTIMEDIA2 1 -#define MSM_FRONTEND_DAI_MULTIMEDIA3 2 -#define MSM_FRONTEND_DAI_MULTIMEDIA4 3 -#define MSM_FRONTEND_DAI_MULTIMEDIA5 4 -#define MSM_FRONTEND_DAI_MULTIMEDIA6 5 -#define MSM_FRONTEND_DAI_MULTIMEDIA7 6 -#define MSM_FRONTEND_DAI_MULTIMEDIA8 7 -#define MSM_FRONTEND_DAI_MULTIMEDIA9 8 -#define MSM_FRONTEND_DAI_MULTIMEDIA10 9 -#define MSM_FRONTEND_DAI_MULTIMEDIA11 10 -#define MSM_FRONTEND_DAI_MULTIMEDIA12 11 -#define MSM_FRONTEND_DAI_MULTIMEDIA13 12 -#define MSM_FRONTEND_DAI_MULTIMEDIA14 13 -#define MSM_FRONTEND_DAI_MULTIMEDIA15 14 -#define MSM_FRONTEND_DAI_MULTIMEDIA16 15 - -#define Q6ASM_DAI_TX_RX 0 -#define Q6ASM_DAI_TX 1 -#define Q6ASM_DAI_RX 2 - -#endif /* __DT_BINDINGS_Q6_ASM_H__ */ diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h deleted file mode 100644 index 39f203256c4..00000000000 --- a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h +++ /dev/null @@ -1,234 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__ -#define __DT_BINDINGS_Q6_AUDIO_PORTS_H__ - -/* LPASS Audio virtual ports IDs */ -#define HDMI_RX 1 -#define SLIMBUS_0_RX 2 -#define SLIMBUS_0_TX 3 -#define SLIMBUS_1_RX 4 -#define SLIMBUS_1_TX 5 -#define SLIMBUS_2_RX 6 -#define SLIMBUS_2_TX 7 -#define SLIMBUS_3_RX 8 -#define SLIMBUS_3_TX 9 -#define SLIMBUS_4_RX 10 -#define SLIMBUS_4_TX 11 -#define SLIMBUS_5_RX 12 -#define SLIMBUS_5_TX 13 -#define SLIMBUS_6_RX 14 -#define SLIMBUS_6_TX 15 -#define PRIMARY_MI2S_RX 16 -#define PRIMARY_MI2S_TX 17 -#define SECONDARY_MI2S_RX 18 -#define SECONDARY_MI2S_TX 19 -#define TERTIARY_MI2S_RX 20 -#define TERTIARY_MI2S_TX 21 -#define QUATERNARY_MI2S_RX 22 -#define QUATERNARY_MI2S_TX 23 -#define PRIMARY_TDM_RX_0 24 -#define PRIMARY_TDM_TX_0 25 -#define PRIMARY_TDM_RX_1 26 -#define PRIMARY_TDM_TX_1 27 -#define PRIMARY_TDM_RX_2 28 -#define PRIMARY_TDM_TX_2 29 -#define PRIMARY_TDM_RX_3 30 -#define PRIMARY_TDM_TX_3 31 -#define PRIMARY_TDM_RX_4 32 -#define PRIMARY_TDM_TX_4 33 -#define PRIMARY_TDM_RX_5 34 -#define PRIMARY_TDM_TX_5 35 -#define PRIMARY_TDM_RX_6 36 -#define PRIMARY_TDM_TX_6 37 -#define PRIMARY_TDM_RX_7 38 -#define PRIMARY_TDM_TX_7 39 -#define SECONDARY_TDM_RX_0 40 -#define SECONDARY_TDM_TX_0 41 -#define SECONDARY_TDM_RX_1 42 -#define SECONDARY_TDM_TX_1 43 -#define SECONDARY_TDM_RX_2 44 -#define SECONDARY_TDM_TX_2 45 -#define SECONDARY_TDM_RX_3 46 -#define SECONDARY_TDM_TX_3 47 -#define SECONDARY_TDM_RX_4 48 -#define SECONDARY_TDM_TX_4 49 -#define SECONDARY_TDM_RX_5 50 -#define SECONDARY_TDM_TX_5 51 -#define SECONDARY_TDM_RX_6 52 -#define SECONDARY_TDM_TX_6 53 -#define SECONDARY_TDM_RX_7 54 -#define SECONDARY_TDM_TX_7 55 -#define TERTIARY_TDM_RX_0 56 -#define TERTIARY_TDM_TX_0 57 -#define TERTIARY_TDM_RX_1 58 -#define TERTIARY_TDM_TX_1 59 -#define TERTIARY_TDM_RX_2 60 -#define TERTIARY_TDM_TX_2 61 -#define TERTIARY_TDM_RX_3 62 -#define TERTIARY_TDM_TX_3 63 -#define TERTIARY_TDM_RX_4 64 -#define TERTIARY_TDM_TX_4 65 -#define TERTIARY_TDM_RX_5 66 -#define TERTIARY_TDM_TX_5 67 -#define TERTIARY_TDM_RX_6 68 -#define TERTIARY_TDM_TX_6 69 -#define TERTIARY_TDM_RX_7 70 -#define TERTIARY_TDM_TX_7 71 -#define QUATERNARY_TDM_RX_0 72 -#define QUATERNARY_TDM_TX_0 73 -#define QUATERNARY_TDM_RX_1 74 -#define QUATERNARY_TDM_TX_1 75 -#define QUATERNARY_TDM_RX_2 76 -#define QUATERNARY_TDM_TX_2 77 -#define QUATERNARY_TDM_RX_3 78 -#define QUATERNARY_TDM_TX_3 79 -#define QUATERNARY_TDM_RX_4 80 -#define QUATERNARY_TDM_TX_4 81 -#define QUATERNARY_TDM_RX_5 82 -#define QUATERNARY_TDM_TX_5 83 -#define QUATERNARY_TDM_RX_6 84 -#define QUATERNARY_TDM_TX_6 85 -#define QUATERNARY_TDM_RX_7 86 -#define QUATERNARY_TDM_TX_7 87 -#define QUINARY_TDM_RX_0 88 -#define QUINARY_TDM_TX_0 89 -#define QUINARY_TDM_RX_1 90 -#define QUINARY_TDM_TX_1 91 -#define QUINARY_TDM_RX_2 92 -#define QUINARY_TDM_TX_2 93 -#define QUINARY_TDM_RX_3 94 -#define QUINARY_TDM_TX_3 95 -#define QUINARY_TDM_RX_4 96 -#define QUINARY_TDM_TX_4 97 -#define QUINARY_TDM_RX_5 98 -#define QUINARY_TDM_TX_5 99 -#define QUINARY_TDM_RX_6 100 -#define QUINARY_TDM_TX_6 101 -#define QUINARY_TDM_RX_7 102 -#define QUINARY_TDM_TX_7 103 -#define DISPLAY_PORT_RX 104 -#define WSA_CODEC_DMA_RX_0 105 -#define WSA_CODEC_DMA_TX_0 106 -#define WSA_CODEC_DMA_RX_1 107 -#define WSA_CODEC_DMA_TX_1 108 -#define WSA_CODEC_DMA_TX_2 109 -#define VA_CODEC_DMA_TX_0 110 -#define VA_CODEC_DMA_TX_1 111 -#define VA_CODEC_DMA_TX_2 112 -#define RX_CODEC_DMA_RX_0 113 -#define TX_CODEC_DMA_TX_0 114 -#define RX_CODEC_DMA_RX_1 115 -#define TX_CODEC_DMA_TX_1 116 -#define RX_CODEC_DMA_RX_2 117 -#define TX_CODEC_DMA_TX_2 118 -#define RX_CODEC_DMA_RX_3 119 -#define TX_CODEC_DMA_TX_3 120 -#define RX_CODEC_DMA_RX_4 121 -#define TX_CODEC_DMA_TX_4 122 -#define RX_CODEC_DMA_RX_5 123 -#define TX_CODEC_DMA_TX_5 124 -#define RX_CODEC_DMA_RX_6 125 -#define RX_CODEC_DMA_RX_7 126 -#define QUINARY_MI2S_RX 127 -#define QUINARY_MI2S_TX 128 -#define DISPLAY_PORT_RX_0 DISPLAY_PORT_RX -#define DISPLAY_PORT_RX_1 129 -#define DISPLAY_PORT_RX_2 130 -#define DISPLAY_PORT_RX_3 131 -#define DISPLAY_PORT_RX_4 132 -#define DISPLAY_PORT_RX_5 133 -#define DISPLAY_PORT_RX_6 134 -#define DISPLAY_PORT_RX_7 135 - -#define LPASS_CLK_ID_PRI_MI2S_IBIT 1 -#define LPASS_CLK_ID_PRI_MI2S_EBIT 2 -#define LPASS_CLK_ID_SEC_MI2S_IBIT 3 -#define LPASS_CLK_ID_SEC_MI2S_EBIT 4 -#define LPASS_CLK_ID_TER_MI2S_IBIT 5 -#define LPASS_CLK_ID_TER_MI2S_EBIT 6 -#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 -#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 -#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 -#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 -#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 -#define LPASS_CLK_ID_QUI_MI2S_IBIT 12 -#define LPASS_CLK_ID_QUI_MI2S_EBIT 13 -#define LPASS_CLK_ID_SEN_MI2S_IBIT 14 -#define LPASS_CLK_ID_SEN_MI2S_EBIT 15 -#define LPASS_CLK_ID_INT0_MI2S_IBIT 16 -#define LPASS_CLK_ID_INT1_MI2S_IBIT 17 -#define LPASS_CLK_ID_INT2_MI2S_IBIT 18 -#define LPASS_CLK_ID_INT3_MI2S_IBIT 19 -#define LPASS_CLK_ID_INT4_MI2S_IBIT 20 -#define LPASS_CLK_ID_INT5_MI2S_IBIT 21 -#define LPASS_CLK_ID_INT6_MI2S_IBIT 22 -#define LPASS_CLK_ID_QUI_MI2S_OSR 23 -#define LPASS_CLK_ID_PRI_PCM_IBIT 24 -#define LPASS_CLK_ID_PRI_PCM_EBIT 25 -#define LPASS_CLK_ID_SEC_PCM_IBIT 26 -#define LPASS_CLK_ID_SEC_PCM_EBIT 27 -#define LPASS_CLK_ID_TER_PCM_IBIT 28 -#define LPASS_CLK_ID_TER_PCM_EBIT 29 -#define LPASS_CLK_ID_QUAD_PCM_IBIT 30 -#define LPASS_CLK_ID_QUAD_PCM_EBIT 31 -#define LPASS_CLK_ID_QUIN_PCM_IBIT 32 -#define LPASS_CLK_ID_QUIN_PCM_EBIT 33 -#define LPASS_CLK_ID_QUI_PCM_OSR 34 -#define LPASS_CLK_ID_PRI_TDM_IBIT 35 -#define LPASS_CLK_ID_PRI_TDM_EBIT 36 -#define LPASS_CLK_ID_SEC_TDM_IBIT 37 -#define LPASS_CLK_ID_SEC_TDM_EBIT 38 -#define LPASS_CLK_ID_TER_TDM_IBIT 39 -#define LPASS_CLK_ID_TER_TDM_EBIT 40 -#define LPASS_CLK_ID_QUAD_TDM_IBIT 41 -#define LPASS_CLK_ID_QUAD_TDM_EBIT 42 -#define LPASS_CLK_ID_QUIN_TDM_IBIT 43 -#define LPASS_CLK_ID_QUIN_TDM_EBIT 44 -#define LPASS_CLK_ID_QUIN_TDM_OSR 45 -#define LPASS_CLK_ID_MCLK_1 46 -#define LPASS_CLK_ID_MCLK_2 47 -#define LPASS_CLK_ID_MCLK_3 48 -#define LPASS_CLK_ID_MCLK_4 49 -#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 -#define LPASS_CLK_ID_INT_MCLK_0 51 -#define LPASS_CLK_ID_INT_MCLK_1 52 -#define LPASS_CLK_ID_MCLK_5 53 -#define LPASS_CLK_ID_WSA_CORE_MCLK 54 -#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 -#define LPASS_CLK_ID_VA_CORE_MCLK 56 -#define LPASS_CLK_ID_TX_CORE_MCLK 57 -#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 -#define LPASS_CLK_ID_RX_CORE_MCLK 59 -#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 -#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 -/* Clock ID for MCLK for WSA2 core */ -#define LPASS_CLK_ID_WSA2_CORE_MCLK 62 -/* Clock ID for NPL MCLK for WSA2 core */ -#define LPASS_CLK_ID_WSA2_CORE_2X_MCLK 63 -/* Clock ID for RX Core TX MCLK */ -#define LPASS_CLK_ID_RX_CORE_TX_MCLK 64 -/* Clock ID for RX CORE TX 2X MCLK */ -#define LPASS_CLK_ID_RX_CORE_TX_2X_MCLK 65 -/* Clock ID for WSA core TX MCLK */ -#define LPASS_CLK_ID_WSA_CORE_TX_MCLK 66 -/* Clock ID for WSA core TX 2X MCLK */ -#define LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK 67 -/* Clock ID for WSA2 core TX MCLK */ -#define LPASS_CLK_ID_WSA2_CORE_TX_MCLK 68 -/* Clock ID for WSA2 core TX 2X MCLK */ -#define LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 69 -/* Clock ID for RX CORE MCLK2 2X MCLK */ -#define LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 70 - -#define LPASS_HW_AVTIMER_VOTE 101 -#define LPASS_HW_MACRO_VOTE 102 -#define LPASS_HW_DCODEC_VOTE 103 - -#define Q6AFE_MAX_CLK_ID 104 - -#define LPASS_CLK_ATTRIBUTE_INVALID 0x0 -#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 -#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 -#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 - -#endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */ diff --git a/include/dt-bindings/sound/qcom,wcd9335.h b/include/dt-bindings/sound/qcom,wcd9335.h deleted file mode 100644 index f5e9f1db091..00000000000 --- a/include/dt-bindings/sound/qcom,wcd9335.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ - -#ifndef __DT_SOUND_QCOM_WCD9335_H -#define __DT_SOUND_QCOM_WCD9335_H - -#define AIF1_PB 0 -#define AIF1_CAP 1 -#define AIF2_PB 2 -#define AIF2_CAP 3 -#define AIF3_PB 4 -#define AIF3_CAP 5 -#define AIF4_PB 6 -#define NUM_CODEC_DAIS 7 - -#endif diff --git a/include/efi_api.h b/include/efi_api.h index f07d074f93b..61c4eda8f8a 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -616,6 +616,7 @@ struct efi_device_path_acpi_path { # define DEVICE_PATH_SUB_TYPE_MSG_SCSI 0x02 # define DEVICE_PATH_SUB_TYPE_MSG_USB 0x05 # define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR 0x0b +# define DEVICE_PATH_SUB_TYPE_MSG_IPV4 0x0c # define DEVICE_PATH_SUB_TYPE_MSG_UART 0x0e # define DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS 0x0f # define DEVICE_PATH_SUB_TYPE_MSG_USB_WWI 0x10 @@ -691,6 +692,22 @@ struct efi_device_path_uri { u8 uri[]; } __packed; +struct efi_ipv4_address { + u8 ip_addr[4]; +}; + +struct efi_device_path_ipv4 { + struct efi_device_path dp; + struct efi_ipv4_address local_ip_address; + struct efi_ipv4_address remote_ip_address; + u16 local_port; + u16 remote_port; + u16 protocol; + u8 static_ip_address; + struct efi_ipv4_address gateway_ip_address; + struct efi_ipv4_address subnet_mask; +} __packed; + #define DEVICE_PATH_TYPE_MEDIA_DEVICE 0x04 # define DEVICE_PATH_SUB_TYPE_HARD_DRIVE_PATH 0x01 # define DEVICE_PATH_SUB_TYPE_CDROM_PATH 0x02 @@ -1708,6 +1725,209 @@ struct efi_pxe_base_code_protocol { struct efi_pxe_mode *mode; }; +#define EFI_IP4_CONFIG2_PROTOCOL_GUID \ + EFI_GUID(0x5b446ed1, 0xe30b, 0x4faa, \ + 0x87, 0x1a, 0x36, 0x54, 0xec, 0xa3, 0x60, 0x80) + +enum efi_ip4_config2_data_type { + EFI_IP4_CONFIG2_DATA_TYPE_INTERFACEINFO, + EFI_IP4_CONFIG2_DATA_TYPE_POLICY, + EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS, + EFI_IP4_CONFIG2_DATA_TYPE_GATEWAY, + EFI_IP4_CONFIG2_DATA_TYPE_DNSSERVER, + EFI_IP4_CONFIG2_DATA_TYPE_MAXIMUM, +}; + +struct efi_ip4_config2_protocol { + efi_status_t (EFIAPI * set_data)(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + efi_uintn_t data_size, + void *data); + efi_status_t (EFIAPI * get_data)(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + efi_uintn_t *data_size, + void *data); + efi_status_t (EFIAPI * register_data_notify)(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + struct efi_event *event); + efi_status_t (EFIAPI * unregister_data_notify)(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + struct efi_event *event); +}; + +struct efi_ip4_route_table { + struct efi_ipv4_address subnet_address; + struct efi_ipv4_address subnet_mask; + struct efi_ipv4_address gateway_address; +}; + +#define EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE 32 + +struct efi_ip4_config2_interface_info { + u16 name[EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE]; + u8 if_type; + u32 hw_address_size; + struct efi_mac_address hw_address; + struct efi_ipv4_address station_address; + struct efi_ipv4_address subnet_mask; + u32 route_table_size; + struct efi_ip4_route_table *route_table; +}; + +enum efi_ip4_config2_policy { + EFI_IP4_CONFIG2_POLICY_STATIC, + EFI_IP4_CONFIG2_POLICY_DHCP, + EFI_IP4_CONFIG2_POLICY_MAX +}; + +struct efi_ip4_config2_manual_address { + struct efi_ipv4_address address; + struct efi_ipv4_address subnet_mask; +}; + +#define EFI_HTTP_SERVICE_BINDING_PROTOCOL_GUID \ + EFI_GUID(0xbdc8e6af, 0xd9bc, 0x4379, \ + 0xa7, 0x2a, 0xe0, 0xc4, 0xe7, 0x5d, 0xae, 0x1c) + +struct efi_service_binding_protocol { + efi_status_t (EFIAPI * create_child)(struct efi_service_binding_protocol *this, + efi_handle_t *child_handle); + efi_status_t (EFIAPI * destroy_child)(struct efi_service_binding_protocol *this, + efi_handle_t child_handle); +}; + +#define EFI_HTTP_PROTOCOL_GUID \ + EFI_GUID(0x7A59B29B, 0x910B, 0x4171, \ + 0x82, 0x42, 0xA8, 0x5A, 0x0D, 0xF2, 0x5B, 0x5B) + +enum efi_http_version { + HTTPVERSION10, + HTTPVERSION11, + HTTPVERSIONUNSUPPORTED +}; + +struct efi_httpv4_access_point { + bool use_default_address; + struct efi_ipv4_address local_address; + struct efi_ipv4_address local_subnet; + u16 local_port; +}; + +union efi_http_access_point { + struct efi_httpv4_access_point *ipv4_node; + struct efi_httpv6_access_point *ipv6_node; +}; + +struct efi_http_config_data { + enum efi_http_version http_version; + u32 timeout; + bool is_ipv6; + union efi_http_access_point access_point; +}; + +enum efi_http_method { + HTTP_METHOD_GET, + HTTP_METHOD_POST, + HTTP_METHOD_PATCH, + HTTP_METHOD_OPTIONS, + HTTP_METHOD_CONNECT, + HTTP_METHOD_HEAD, + HTTP_METHOD_PUT, + HTTP_METHOD_DELETE, + HTTP_METHOD_TRACE, + HTTP_METHOD_MAX +}; + +enum efi_http_status_code { + HTTP_STATUS_UNSUPPORTED_STATUS = 0, + HTTP_STATUS_100_CONTINUE, + HTTP_STATUS_101_SWITCHING_PROTOCOLS, + HTTP_STATUS_200_OK, + HTTP_STATUS_201_CREATED, + HTTP_STATUS_202_ACCEPTED, + HTTP_STATUS_203_NON_AUTHORITATIVE_INFORMATION, + HTTP_STATUS_204_NO_CONTENT, + HTTP_STATUS_205_RESET_CONTENT, + HTTP_STATUS_206_PARTIAL_CONTENT, + HTTP_STATUS_300_MULTIPLE_CHOICES, + HTTP_STATUS_301_MOVED_PERMANENTLY, + HTTP_STATUS_302_FOUND, + HTTP_STATUS_303_SEE_OTHER, + HTTP_STATUS_304_NOT_MODIFIED, + HTTP_STATUS_305_USE_PROXY, + HTTP_STATUS_307_TEMPORARY_REDIRECT, + HTTP_STATUS_400_BAD_REQUEST, + HTTP_STATUS_401_UNAUTHORIZED, + HTTP_STATUS_402_PAYMENT_REQUIRED, + HTTP_STATUS_403_FORBIDDEN, + HTTP_STATUS_404_NOT_FOUND, + HTTP_STATUS_405_METHOD_NOT_ALLOWED, + HTTP_STATUS_406_NOT_ACCEPTABLE, + HTTP_STATUS_407_PROXY_AUTHENTICATION_REQUIRED, + HTTP_STATUS_408_REQUEST_TIME_OUT, + HTTP_STATUS_409_CONFLICT, + HTTP_STATUS_410_GONE, + HTTP_STATUS_411_LENGTH_REQUIRED, + HTTP_STATUS_412_PRECONDITION_FAILED, + HTTP_STATUS_413_REQUEST_ENTITY_TOO_LARGE, + HTTP_STATUS_414_REQUEST_URI_TOO_LARGE, + HTTP_STATUS_415_UNSUPPORTED_MEDIA_TYPE, + HTTP_STATUS_416_REQUESTED_RANGE_NOT_SATISFIED, + HTTP_STATUS_417_EXPECTATION_FAILED, + HTTP_STATUS_500_INTERNAL_SERVER_ERROR, + HTTP_STATUS_501_NOT_IMPLEMENTED, + HTTP_STATUS_502_BAD_GATEWAY, + HTTP_STATUS_503_SERVICE_UNAVAILABLE, + HTTP_STATUS_504_GATEWAY_TIME_OUT, + HTTP_STATUS_505_HTTP_VERSION_NOT_SUPPORTED, + HTTP_STATUS_308_PERMANENT_REDIRECT +}; + +struct efi_http_request_data { + enum efi_http_method method; + u16 *url; +}; + +struct efi_http_response_data { + enum efi_http_status_code status_code; +}; + +struct efi_http_header { + char *field_name; + char *field_value; +}; + +struct efi_http_message { + union { + struct efi_http_request_data *request; + struct efi_http_response_data *response; + } data; + efi_uintn_t header_count; + struct efi_http_header *headers; + efi_uintn_t body_length; + void *body; +}; + +struct efi_http_token { + struct efi_event *event; + efi_status_t status; + struct efi_http_message *message; +}; + +struct efi_http_protocol { + efi_status_t (EFIAPI * get_mode_data)(struct efi_http_protocol *this, + struct efi_http_config_data *data); + efi_status_t (EFIAPI * configure)(struct efi_http_protocol *this, + struct efi_http_config_data *data); + efi_status_t (EFIAPI * request)(struct efi_http_protocol *this, + struct efi_http_token *token); + efi_status_t (EFIAPI * cancel)(struct efi_http_protocol *this, + struct efi_http_token *token); + efi_status_t (EFIAPI * response)(struct efi_http_protocol *this, + struct efi_http_token *token); + efi_status_t (EFIAPI * poll)(struct efi_http_protocol *this); +}; + #define EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID \ EFI_GUID(0x964e5b22, 0x6459, 0x11d2, \ 0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b) diff --git a/include/efi_loader.h b/include/efi_loader.h index 39809eac1bc..9afbec35ebf 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -16,6 +16,7 @@ #include <image.h> #include <pe.h> #include <linux/list.h> +#include <linux/sizes.h> #include <linux/oid_registry.h> struct blk_desc; @@ -125,6 +126,39 @@ static inline void efi_set_bootdev(const char *dev, const char *devnr, size_t buffer_size) { } #endif +#if CONFIG_IS_ENABLED(NETDEVICES) && CONFIG_IS_ENABLED(EFI_LOADER) +/* Call this to update the current device path of the efi net device */ +efi_status_t efi_net_set_dp(const char *dev, const char *server); +/* Call this to get the current device path of the efi net device */ +void efi_net_get_dp(struct efi_device_path **dp); +void efi_net_get_addr(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *gw); +void efi_net_set_addr(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *gw); +efi_status_t efi_net_do_request(u8 *url, enum efi_http_method method, void **buffer, + u32 *status_code, ulong *file_size, char *headers_buffer); +#define MAX_HTTP_HEADERS_SIZE SZ_64K +#define MAX_HTTP_HEADERS 100 +#define MAX_HTTP_HEADER_NAME 128 +#define MAX_HTTP_HEADER_VALUE 512 +struct http_header { + uchar name[MAX_HTTP_HEADER_NAME]; + uchar value[MAX_HTTP_HEADER_VALUE]; +}; + +void efi_net_parse_headers(ulong *num_headers, struct http_header *headers); +#else +static inline void efi_net_get_dp(struct efi_device_path **dp) { } +static inline void efi_net_get_addr(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *gw) { } +static inline void efi_net_set_addr(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *gw) { } +#endif + /* Maximum number of configuration tables */ #define EFI_MAX_CONFIGURATION_TABLES 16 @@ -592,6 +626,12 @@ int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc, efi_status_t efi_gop_register(void); /* Called by bootefi to make the network interface available */ efi_status_t efi_net_register(void); +/* Called by efi_net_register to make the ip4 config2 protocol available */ +efi_status_t efi_ipconfig_register(const efi_handle_t handle, + struct efi_ip4_config2_protocol *ip4config); +/* Called by efi_net_register to make the http protocol available */ +efi_status_t efi_http_register(const efi_handle_t handle, + struct efi_service_binding_protocol *http_service_binding); /* Called by bootefi to make the watchdog available */ efi_status_t efi_watchdog_register(void); efi_status_t efi_initrd_register(void); @@ -856,6 +896,7 @@ struct efi_device_path *efi_dp_part_node(struct blk_desc *desc, int part); struct efi_device_path *efi_dp_from_file(const struct efi_device_path *dp, const char *path); struct efi_device_path *efi_dp_from_eth(void); +struct efi_device_path *efi_dp_from_http(const char *server); struct efi_device_path *efi_dp_from_mem(uint32_t mem_type, uint64_t start_address, size_t size); diff --git a/include/env_callback.h b/include/env_callback.h index bc8ff1923e1..47a31f6cf52 100644 --- a/include/env_callback.h +++ b/include/env_callback.h @@ -14,11 +14,6 @@ #define ENV_CALLBACK_VAR ".callbacks" -/* Board configs can define additional static callback bindings */ -#ifndef CFG_ENV_CALLBACK_LIST_STATIC -#define CFG_ENV_CALLBACK_LIST_STATIC -#endif - #ifdef CONFIG_SILENT_CONSOLE #define SILENT_CALLBACK "silent:silent," #else @@ -90,7 +85,7 @@ SILENT_CALLBACK \ "stdin:console,stdout:console,stderr:console," \ "serial#:serialno," \ - CFG_ENV_CALLBACK_LIST_STATIC + CONFIG_ENV_CALLBACK_LIST_STATIC #ifndef CONFIG_XPL_BUILD void env_callback_init(struct env_entry *var_entry); diff --git a/include/firmware/imx/sci/rpc.h b/include/firmware/imx/sci/rpc.h index 28adec2a8e1..04acc7ff95b 100644 --- a/include/firmware/imx/sci/rpc.h +++ b/include/firmware/imx/sci/rpc.h @@ -231,4 +231,7 @@ struct sc_rpc_msg_s { #define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */ #define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */ +/* Siemens specific API extension */ +#define TIMER_FUNC_CTRL_SIEMENS_PMIC_WDOG 20U /*!< Index for sc_timer_ctrl_pmic_wdog() RPC call */ + #endif /* SC_RPC_H */ diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h index 7d8499f070a..588f3671103 100644 --- a/include/firmware/imx/sci/sci.h +++ b/include/firmware/imx/sci/sci.h @@ -123,6 +123,7 @@ int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid); /* Timer API */ int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window); +int sc_timer_control_siemens_pmic_wdog(sc_ipc_t ipc, u8 cmd); /* SECO API */ int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, diff --git a/include/fs.h b/include/fs.h index 63727567ccc..2474880385d 100644 --- a/include/fs.h +++ b/include/fs.h @@ -325,7 +325,7 @@ int do_fs_types(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]); * * @fname: Filename to read * @size: Size of file to read (must be correct!) - * @align: Alignment to use for memory allocation (0 for default) + * @align: Alignment to use for memory allocation (0 for default: ARCH_DMA_MINALIGN) * @bufp: On success, returns the allocated buffer with the nul-terminated file * in it * Return: 0 if OK, -ENOMEM if out of memory, -EIO if read failed diff --git a/include/image.h b/include/image.h index c52fced9b40..9be5acd8158 100644 --- a/include/image.h +++ b/include/image.h @@ -1802,6 +1802,30 @@ struct cipher_algo *image_get_cipher_algo(const char *full_name); struct andr_image_data; /** + * android_image_get_bootimg_size() - Extract size of Android boot image + * + * This is used to extract the size of an Android boot image + * from boot image header. + * + * @hdr: Pointer to boot image header + * @boot_img_size: On exit returns the size in bytes of the boot image + * Return: true if succeeded, false otherwise + */ +bool android_image_get_bootimg_size(const void *hdr, u32 *boot_img_size); + +/** + * android_image_get_vendor_bootimg_size() - Extract size of Android vendor-boot image + * + * This is used to extract the size of an Android vendor-boot image + * from vendor-boot image header. + * + * @hdr: Pointer to vendor-boot image header + * @vendor_boot_img_size: On exit returns the size in bytes of the vendor-boot image + * Return: true if succeeded, false otherwise + */ +bool android_image_get_vendor_bootimg_size(const void *hdr, u32 *vendor_boot_img_size); + +/** * android_image_get_data() - Parse Android boot images * * This is used to parse boot and vendor-boot header into diff --git a/include/k3-avs.h b/include/k3-avs.h index 1014d5d114d..5a973e4ed45 100644 --- a/include/k3-avs.h +++ b/include/k3-avs.h @@ -20,11 +20,13 @@ #define NUM_OPPS 4 +#define AM6_OPP_LOW 0 #define AM6_OPP_NOM 1 #define AM6_OPP_OD 2 #define AM6_OPP_TURBO 3 int k3_avs_set_opp(struct udevice *dev, int vdd_id, int opp_id); int k3_avs_notify_freq(int dev_id, int clk_id, u32 freq); +int k3_avs_check_opp(struct udevice *dev, int vdd_id, int opp_id); #endif diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 6751fb52c5a..3ffcd40807d 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -339,7 +339,7 @@ static inline void mtd_set_ofnode(struct mtd_info *mtd, ofnode node) dev_set_ofnode(mtd->dev, node); } -static inline const ofnode mtd_get_ofnode(struct mtd_info *mtd) +static inline ofnode mtd_get_ofnode(struct mtd_info *mtd) { return dev_ofnode(mtd->dev); } diff --git a/include/memtop.h b/include/memtop.h new file mode 100644 index 00000000000..28f62e24ea7 --- /dev/null +++ b/include/memtop.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024, Linaro Limited + */ + +/** + * get_mem_top() - Compute the value of ram_top + * @ram_start: Start of RAM + * @ram_size: RAM size + * @size: Minimum RAM size requested + * @fdt: FDT blob + * + * The function computes the top address of RAM memory that can be + * used by U-Boot. This is being done by going through the list of + * reserved memory regions specified in the devicetree blob passed + * to the function. The logic used here is derived from the lmb + * allocation function. + * + * Return: address of ram top on success, 0 on failure + */ +phys_addr_t get_mem_top(phys_addr_t ram_start, phys_size_t ram_size, + phys_size_t size, void *fdt); diff --git a/include/net-common.h b/include/net-common.h index 524ed4ad131..8fc1bac47f5 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -8,6 +8,7 @@ #include <env.h> #include <hexdump.h> #include <linux/if_ether.h> +#include <linux/sizes.h> #include <linux/types.h> #include <rand.h> #include <time.h> @@ -425,6 +426,16 @@ void string_to_enetaddr(const char *addr, uint8_t *enetaddr); */ struct in_addr string_to_ip(const char *s); +/** + * ip_to_string() - Convert a string to ip address + * + * Implemented in lib/net_utils.c (built unconditionally) + * + * @x: Input ip to parse + * @s: string containing the parsed ip address + */ +void ip_to_string(struct in_addr x, char *s); + /* copy a filename (allow for "..." notation, limit length) */ void copy_filename(char *dst, const char *src, int size); @@ -490,13 +501,16 @@ int dhcp_run(ulong addr, const char *fname, bool autoload); int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); /** - * wget_with_dns() - runs dns host IP address resulution before wget + * wget_do_request() - sends a wget request + * + * Sends a wget request, if DNS resolution is enabled it resolves the + * given uri. * * @dst_addr: destination address to download the file * @uri: uri string of target file of wget - * Return: downloaded file size, negative if failed + * Return: zero on success, negative if failed */ -int wget_with_dns(ulong dst_addr, char *uri); +int wget_do_request(ulong dst_addr, char *uri); /** * wget_validate_uri() - varidate the uri * @@ -506,4 +520,55 @@ int wget_with_dns(ulong dst_addr, char *uri); bool wget_validate_uri(char *uri); //int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]); +/** + * enum wget_http_method - http method + */ +enum wget_http_method { + WGET_HTTP_METHOD_GET, + WGET_HTTP_METHOD_POST, + WGET_HTTP_METHOD_PATCH, + WGET_HTTP_METHOD_OPTIONS, + WGET_HTTP_METHOD_CONNECT, + WGET_HTTP_METHOD_HEAD, + WGET_HTTP_METHOD_PUT, + WGET_HTTP_METHOD_DELETE, + WGET_HTTP_METHOD_TRACE, + WGET_HTTP_METHOD_MAX +}; + +/** + * define MAX_HTTP_HEADERS_SIZE - maximum headers buffer size + * + * When receiving http headers, wget fills a buffer with up + * to MAX_HTTP_HEADERS_SIZE bytes of header information. + */ +#define MAX_HTTP_HEADERS_SIZE SZ_64K + +/** + * struct wget_http_info - wget parameters + * @method: HTTP Method. Filled by client. + * @status_code: HTTP status code. Filled by wget. + * @file_size: download size. Filled by wget. + * @buffer_size: size of client-provided buffer. Filled by client. + * @set_bootdev: set boot device with download. Filled by client. + * @check_buffer_size: check download does not exceed buffer size. + * Filled by client. + * @hdr_cont_len: content length according to headers. Filled by wget + * @headers: buffer for headers. Filled by wget. + */ +struct wget_http_info { + enum wget_http_method method; + u32 status_code; + ulong file_size; + ulong buffer_size; + bool set_bootdev; + bool check_buffer_size; + u32 hdr_cont_len; + char *headers; +}; + +extern struct wget_http_info default_wget_info; +extern struct wget_http_info *wget_info; +int wget_request(ulong dst_addr, char *uri, struct wget_http_info *info); + #endif /* __NET_COMMON_H__ */ diff --git a/include/net-lwip.h b/include/net-lwip.h index 1c3583f82a1..4d7f9387d1d 100644 --- a/include/net-lwip.h +++ b/include/net-lwip.h @@ -17,15 +17,6 @@ struct netif *net_lwip_get_netif(void); int net_lwip_rx(struct udevice *udev, struct netif *netif); /** - * wget_with_dns() - runs dns host IP address resulution before wget - * - * @dst_addr: destination address to download the file - * @uri: uri string of target file of wget - * Return: downloaded file size, negative if failed - */ - -int wget_with_dns(ulong dst_addr, char *uri); -/** * wget_validate_uri() - varidate the uri * * @uri: uri string of target file of wget diff --git a/include/netdev.h b/include/netdev.h index 2a06d9a261b..949245ecdec 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -117,7 +117,7 @@ static inline int pci_eth_init(struct bd_info *bis) return num; } -struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id); +struct mii_dev *fec_get_miibus(struct udevice *dev, ulong base_addr, int dev_id); #ifdef CONFIG_PHYLIB struct phy_device; diff --git a/include/part.h b/include/part.h index 92662677551..fcb3c13dea4 100644 --- a/include/part.h +++ b/include/part.h @@ -74,6 +74,7 @@ struct disk_partition { * PART_EFI_SYSTEM_PARTITION the partition is an EFI system partition */ int bootable; + u16 type_flags; /* top 16 bits of GPT partition attributes */ #if CONFIG_IS_ENABLED(PARTITION_UUIDS) char uuid[UUID_STR_LEN + 1]; /* filesystem UUID as string, if exists */ #endif diff --git a/include/sysinfo.h b/include/sysinfo.h index 8a77ef44856..027a463dc33 100644 --- a/include/sysinfo.h +++ b/include/sysinfo.h @@ -40,29 +40,29 @@ struct udevice; /** enum sysinfo_id - Standard IDs defined by U-Boot */ enum sysinfo_id { - SYSINFO_ID_NONE, + SYSID_NONE, /* For SMBIOS tables */ - SYSINFO_ID_SMBIOS_SYSTEM_MANUFACTURER, - SYSINFO_ID_SMBIOS_SYSTEM_PRODUCT, - SYSINFO_ID_SMBIOS_SYSTEM_VERSION, - SYSINFO_ID_SMBIOS_SYSTEM_SERIAL, - SYSINFO_ID_SMBIOS_SYSTEM_SKU, - SYSINFO_ID_SMBIOS_SYSTEM_FAMILY, - SYSINFO_ID_SMBIOS_BASEBOARD_MANUFACTURER, - SYSINFO_ID_SMBIOS_BASEBOARD_PRODUCT, - SYSINFO_ID_SMBIOS_BASEBOARD_VERSION, - SYSINFO_ID_SMBIOS_BASEBOARD_SERIAL, - SYSINFO_ID_SMBIOS_BASEBOARD_ASSET_TAG, + SYSID_SM_SYSTEM_MANUFACTURER, + SYSID_SM_SYSTEM_PRODUCT, + SYSID_SM_SYSTEM_VERSION, + SYSID_SM_SYSTEM_SERIAL, + SYSID_SM_SYSTEM_SKU, + SYSID_SM_SYSTEM_FAMILY, + SYSID_SM_BASEBOARD_MANUFACTURER, + SYSID_SM_BASEBOARD_PRODUCT, + SYSID_SM_BASEBOARD_VERSION, + SYSID_SM_BASEBOARD_SERIAL, + SYSID_SM_BASEBOARD_ASSET_TAG, /* For show_board_info() */ - SYSINFO_ID_BOARD_MODEL, - SYSINFO_ID_BOARD_MANUFACTURER, - SYSINFO_ID_PRIOR_STAGE_VERSION, - SYSINFO_ID_PRIOR_STAGE_DATE, + SYSID_BOARD_MODEL, + SYSID_BOARD_MANUFACTURER, + SYSID_PRIOR_STAGE_VERSION, + SYSID_PRIOR_STAGE_DATE, /* First value available for downstream/board used */ - SYSINFO_ID_USER = 0x1000, + SYSID_USER = 0x1000, }; struct sysinfo_ops { diff --git a/lib/Kconfig b/lib/Kconfig index 56ffdfa1839..0b089814d14 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -45,6 +45,15 @@ config BINMAN_FDT locate entries in the firmware image. See binman.h for the available functionality. +config BINMAN_DTB + string "binman DTB description" + depends on BINMAN + help + This enables option to point to different DTB file with binman node which + is outside of DTB used by the firmware. Use this option if information + about generated images shouldn't be the part of target binary. Or on system + with limited storage. + config CC_OPTIMIZE_LIBS_FOR_SPEED bool "Optimize libraries for speed" help diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 58d49789f12..c46ffe3a9d8 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -2,7 +2,7 @@ menu "UEFI Support" config EFI_LOADER bool "Support running UEFI applications" - depends on OF_LIBFDT && ( \ + depends on ( \ ARM && (SYS_CPU = arm1136 || \ SYS_CPU = arm1176 || \ SYS_CPU = armv7 || \ @@ -21,6 +21,7 @@ config EFI_LOADER select EVENT_DYNAMIC select LIB_UUID select LMB + select OF_LIBFDT imply PARTITION_UUIDS select REGEX imply FAT @@ -476,12 +477,28 @@ config EFI_RISCV_BOOT_PROTOCOL replace the transfer via the device-tree. The latter is not possible on systems using ACPI. +config EFI_IP4_CONFIG2_PROTOCOL + bool "EFI_IP4_CONFIG2_PROTOCOL support" + default y if ARCH_QEMU || SANDBOX + depends on NET || NET_LWIP + help + Provides an implementation of the EFI_IP4_CONFIG2_PROTOCOL, this + protocol can be used to set and get the current ip address and + other network information. + +config EFI_HTTP_PROTOCOL + bool "EFI_HTTP_PROTOCOL support" + default y if ARCH_QEMU || SANDBOX + depends on WGET + help + Provides an EFI HTTP driver implementing the EFI_HTTP_PROTOCOL. and + EFI_HTTP_SERVICE_BINDING_PROTOCOL. + endmenu menu "Misc options" config EFI_LOADER_BOUNCE_BUFFER bool "EFI Applications use bounce buffers for DMA operations" - depends on ARM64 help Some hardware does not support DMA to full 64bit addresses. For this hardware we can create a bounce buffer so that payloads don't have to diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 87131ab911d..2a0b4172bd7 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -59,6 +59,8 @@ obj-$(CONFIG_EFI_ESRT) += efi_esrt.o obj-$(CONFIG_VIDEO) += efi_gop.o obj-$(CONFIG_BLK) += efi_disk.o obj-$(CONFIG_NETDEVICES) += efi_net.o +obj-$(CONFIG_EFI_IP4_CONFIG2_PROTOCOL) += efi_ipconfig.o +obj-$(CONFIG_EFI_HTTP_PROTOCOL) += efi_http.o obj-$(CONFIG_ACPI) += efi_acpi.o obj-$(CONFIG_SMBIOS) += efi_smbios.o obj-$(CONFIG_EFI_RNG_PROTOCOL) += efi_rng.o diff --git a/lib/efi_loader/efi_bootbin.c b/lib/efi_loader/efi_bootbin.c index a87006b3c0e..b677bbc3124 100644 --- a/lib/efi_loader/efi_bootbin.c +++ b/lib/efi_loader/efi_bootbin.c @@ -93,24 +93,34 @@ void efi_set_bootdev(const char *dev, const char *devnr, const char *path, image_addr = buffer; image_size = buffer_size; +#if IS_ENABLED(CONFIG_NETDEVICES) + if (!strcmp(dev, "Net") || !strcmp(dev, "Http")) { + ret = efi_net_set_dp(dev, devnr); + if (ret != EFI_SUCCESS) + goto error; + } +#endif + ret = efi_dp_from_name(dev, devnr, path, &device, &image); - if (ret == EFI_SUCCESS) { - bootefi_device_path = device; - if (image) { - /* FIXME: image should not contain device */ - struct efi_device_path *image_tmp = image; - - efi_dp_split_file_path(image, &device, &image); - efi_free_pool(image_tmp); - } - bootefi_image_path = image; - log_debug("- boot device %pD\n", device); - if (image) - log_debug("- image %pD\n", image); - } else { - log_debug("- efi_dp_from_name() failed, err=%lx\n", ret); - efi_clear_bootdev(); + if (ret != EFI_SUCCESS) + goto error; + + bootefi_device_path = device; + if (image) { + /* FIXME: image should not contain device */ + struct efi_device_path *image_tmp = image; + + efi_dp_split_file_path(image, &device, &image); + efi_free_pool(image_tmp); } + bootefi_image_path = image; + log_debug("- boot device %pD\n", device); + if (image) + log_debug("- image %pD\n", image); + return; +error: + log_debug("- efi_dp_from_name() failed, err=%lx\n", ret); + efi_clear_bootdev(); } /** diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c index 8c51a6ef2ed..c6124c590d9 100644 --- a/lib/efi_loader/efi_bootmgr.c +++ b/lib/efi_loader/efi_bootmgr.c @@ -479,7 +479,7 @@ static efi_status_t try_load_from_uri_path(struct efi_device_path_uri *uridp, } image_addr = hextoul(s, NULL); - err = wget_with_dns(image_addr, uridp->uri); + err = wget_do_request(image_addr, uridp->uri); if (err < 0) { ret = EFI_INVALID_PARAMETER; goto err; diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 4f52284b4c6..080e7f78ae3 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -2234,7 +2234,7 @@ static efi_status_t EFIAPI efi_exit_boot_services(efi_handle_t image_handle, if (IS_ENABLED(CONFIG_USB_DEVICE)) udc_disconnect(); board_quiesce_devices(); - dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); + dm_remove_devices_active(); } /* Patch out unsupported runtime function */ diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index ee387e1dfd4..c0633a736b6 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -974,6 +974,116 @@ struct efi_device_path __maybe_unused *efi_dp_from_eth(void) return start; } +/** + * efi_dp_from_ipv4() - set device path from IPv4 address + * + * Set the device path to an ethernet device path as provided by + * efi_dp_from_eth() concatenated with a device path of subtype + * DEVICE_PATH_SUB_TYPE_MSG_IPV4, and an END node. + * + * @ip: IPv4 local address + * @mask: network mask + * @srv: IPv4 remote/server address + * Return: pointer to device path, NULL on error + */ +static struct efi_device_path *efi_dp_from_ipv4(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *srv) +{ + struct efi_device_path *dp1, *dp2, *pos; + struct { + struct efi_device_path_ipv4 ipv4dp; + struct efi_device_path end; + } dp; + + memset(&dp.ipv4dp, 0, sizeof(dp.ipv4dp)); + dp.ipv4dp.dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE; + dp.ipv4dp.dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_IPV4; + dp.ipv4dp.dp.length = sizeof(dp.ipv4dp); + dp.ipv4dp.protocol = 6; + if (ip) + memcpy(&dp.ipv4dp.local_ip_address, ip, sizeof(*ip)); + if (mask) + memcpy(&dp.ipv4dp.subnet_mask, mask, sizeof(*mask)); + if (srv) + memcpy(&dp.ipv4dp.remote_ip_address, srv, sizeof(*srv)); + pos = &dp.end; + memcpy(pos, &END, sizeof(END)); + + dp1 = efi_dp_from_eth(); + if (!dp1) + return NULL; + + dp2 = efi_dp_concat(dp1, (const struct efi_device_path *)&dp, 0); + + efi_free_pool(dp1); + + return dp2; +} + +/** + * efi_dp_from_http() - set device path from http + * + * Set the device path to an IPv4 path as provided by efi_dp_from_ipv4 + * concatenated with a device path of subtype DEVICE_PATH_SUB_TYPE_MSG_URI, + * and an END node. + * + * @server: URI of remote server + * Return: pointer to HTTP device path, NULL on error + */ +struct efi_device_path *efi_dp_from_http(const char *server) +{ + struct efi_device_path *dp1, *dp2; + struct efi_device_path_uri *uridp; + efi_uintn_t uridp_len; + char *pos; + char tmp[128]; + struct efi_ipv4_address ip; + struct efi_ipv4_address mask; + + if ((server && strlen("http://") + strlen(server) + 1 > sizeof(tmp)) || + (!server && IS_ENABLED(CONFIG_NET_LWIP))) + return NULL; + + efi_net_get_addr(&ip, &mask, NULL); + + dp1 = efi_dp_from_ipv4(&ip, &mask, NULL); + if (!dp1) + return NULL; + + strcpy(tmp, "http://"); + + if (server) { + strlcat(tmp, server, sizeof(tmp)); +#if !IS_ENABLED(CONFIG_NET_LWIP) + } else { + ip_to_string(net_server_ip, tmp + strlen("http://")); +#endif + } + + uridp_len = sizeof(struct efi_device_path) + strlen(tmp) + 1; + uridp = efi_alloc(uridp_len + sizeof(END)); + if (!uridp) { + log_err("Out of memory\n"); + return NULL; + } + uridp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE; + uridp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_URI; + uridp->dp.length = uridp_len; + debug("device path: setting uri device path to %s\n", tmp); + memcpy(uridp->uri, tmp, strlen(tmp) + 1); + + pos = (char *)uridp + uridp_len; + memcpy(pos, &END, sizeof(END)); + + dp2 = efi_dp_concat(dp1, (const struct efi_device_path *)uridp, 0); + + efi_free_pool(uridp); + efi_free_pool(dp1); + + return dp2; +} + /* Construct a device-path for memory-mapped image */ struct efi_device_path *efi_dp_from_mem(uint32_t memory_type, uint64_t start_address, @@ -1074,8 +1184,9 @@ efi_status_t efi_dp_from_name(const char *dev, const char *devnr, dp = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, (uintptr_t)image_addr, image_size); - } else if (IS_ENABLED(CONFIG_NETDEVICES) && !strcmp(dev, "Net")) { - dp = efi_dp_from_eth(); + } else if (IS_ENABLED(CONFIG_NETDEVICES) && + (!strcmp(dev, "Net") || !strcmp(dev, "Http"))) { + efi_net_get_dp(&dp); } else if (!strcmp(dev, "Uart")) { dp = efi_dp_from_uart(); } else { diff --git a/lib/efi_loader/efi_device_path_to_text.c b/lib/efi_loader/efi_device_path_to_text.c index 0c7b30a26e7..481a9712d9d 100644 --- a/lib/efi_loader/efi_device_path_to_text.c +++ b/lib/efi_loader/efi_device_path_to_text.c @@ -8,6 +8,7 @@ #include <blk.h> #include <efi_loader.h> #include <malloc.h> +#include <net.h> #define MAC_OUTPUT_LEN 22 #define UNKNOWN_OUTPUT_LEN 23 @@ -170,6 +171,28 @@ static char *dp_msging(char *s, struct efi_device_path *dp) break; } + case DEVICE_PATH_SUB_TYPE_MSG_IPV4: { + struct efi_device_path_ipv4 *idp = + (struct efi_device_path_ipv4 *)dp; + + s += sprintf(s, "IPv4(%pI4,", &idp->remote_ip_address); + switch (idp->protocol) { + case IPPROTO_TCP: + s += sprintf(s, "TCP,"); + case IPPROTO_UDP: + s += sprintf(s, "UDP,"); + default: + s += sprintf(s, "0x%x,", idp->protocol); + } + s += sprintf(s, idp->static_ip_address ? "Static" : "DHCP"); + s += sprintf(s, ",%pI4", &idp->local_ip_address); + if (idp->dp.length == sizeof(struct efi_device_path_ipv4)) + s += sprintf(s, ",%pI4,%pI4", &idp->gateway_ip_address, + &idp->subnet_mask); + s += sprintf(s, ")"); + + break; + } case DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS: { struct efi_device_path_usb_class *ucdp = (struct efi_device_path_usb_class *)dp; diff --git a/lib/efi_loader/efi_http.c b/lib/efi_loader/efi_http.c new file mode 100644 index 00000000000..694e1993418 --- /dev/null +++ b/lib/efi_loader/efi_http.c @@ -0,0 +1,548 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * An HTTP driver + * + * HTTP_PROTOCOL + * HTTP_SERVICE_BINDING_PROTOCOL + * IP4_CONFIG2_PROTOCOL + */ + +#include <charset.h> +#include <efi_loader.h> +#include <image.h> +#include <malloc.h> +#include <mapmem.h> +#include <net.h> + +static const efi_guid_t efi_http_service_binding_guid = EFI_HTTP_SERVICE_BINDING_PROTOCOL_GUID; +static const efi_guid_t efi_http_guid = EFI_HTTP_PROTOCOL_GUID; + +/** + * struct efi_http_instance - EFI object representing an HTTP protocol instance + * + * @http: EFI_HTTP_PROTOCOL interface + * @handle: handle to efi object + * @configured: configuration status + * @http_load_addr: data buffer + * @file_size: size of data + * @current_offset: offset in data buffer + * @status_code: HTTP status code + * @num_headers: number of received headers + * @headers: array of headers + * @headers_buffer: raw buffer with headers + */ +struct efi_http_instance { + struct efi_http_protocol http; + efi_handle_t handle; + bool configured; + void *http_load_addr; + ulong file_size; + ulong current_offset; + u32 status_code; + ulong num_headers; + struct http_header headers[MAX_HTTP_HEADERS]; + char headers_buffer[MAX_HTTP_HEADERS_SIZE]; +}; + +static int num_instances; + +/* + * efi_u32_to_httpstatus() - convert u32 to status + * + */ +enum efi_http_status_code efi_u32_to_httpstatus(u32 status); + +/* + * efi_http_send_data() - sends data to client + * + * + * @client_buffer: client buffer to send data to + * @client_buffer_size: size of the client buffer + * @inst: HTTP instance for which to send data + * + * Return: status code + */ +static efi_status_t efi_http_send_data(void *client_buffer, + efi_uintn_t *client_buffer_size, + struct efi_http_instance *inst) +{ + efi_status_t ret = EFI_SUCCESS; + ulong total_size, transfer_size; + uchar *ptr; + + // Amount of data left; + total_size = inst->file_size; + transfer_size = total_size - inst->current_offset; + debug("efi_http: sending data to client, total size %lu\n", total_size); + // Amount of data the client is willing to receive + if (transfer_size > *client_buffer_size) + transfer_size = *client_buffer_size; + else + *client_buffer_size = transfer_size; + debug("efi_http: transfer size %lu\n", transfer_size); + if (!transfer_size) // Ok, only headers + goto out; + + if (!client_buffer) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + + // Send data + ptr = (uchar *)inst->http_load_addr + inst->current_offset; + memcpy(client_buffer, ptr, transfer_size); + + inst->current_offset += transfer_size; + + // Whole file served, clean the buffer: + if (inst->current_offset == inst->file_size) { + efi_free_pool(inst->http_load_addr); + inst->http_load_addr = NULL; + inst->current_offset = 0; + inst->file_size = 0; + } + +out: + return ret; +} + +/* EFI_HTTP_PROTOCOL */ + +/* + * efi_http_get_mode_data() - Gets the current operational status. + * + * This function implements EFI_HTTP_PROTOCOL.GetModeData(). + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @data: pointer to the buffer for operational parameters + * of this HTTP instance + * Return: status code + */ +static efi_status_t EFIAPI efi_http_get_mode_data(struct efi_http_protocol *this, + struct efi_http_config_data *data) +{ + EFI_ENTRY("%p, %p", this, data); + + efi_status_t ret = EFI_UNSUPPORTED; + + return EFI_EXIT(ret); +} + +/* + * efi_http_configure() - Initializes operational status for this + * EFI HTTP instance. + * + * This function implements EFI_HTTP_PROTOCOL.Configure(). + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @data: pointer to the buffer for operational parameters of + * this HTTP instance + * Return: status code + */ +static efi_status_t EFIAPI efi_http_configure(struct efi_http_protocol *this, + struct efi_http_config_data *data) +{ + EFI_ENTRY("%p, %p", this, data); + + efi_status_t ret = EFI_SUCCESS; + enum efi_http_version http_version; + struct efi_httpv4_access_point *ipv4_node; + struct efi_http_instance *http_instance; + + if (!this) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + + http_instance = (struct efi_http_instance *)this; + + if (!data) { + efi_free_pool(http_instance->http_load_addr); + http_instance->http_load_addr = NULL; + http_instance->current_offset = 0; + http_instance->configured = false; + + goto out; + } + + if (http_instance->configured) { + ret = EFI_ALREADY_STARTED; + goto out; + } + + http_version = data->http_version; + ipv4_node = data->access_point.ipv4_node; + + if ((http_version != HTTPVERSION10 && + http_version != HTTPVERSION11) || + data->is_ipv6 || !ipv4_node) { /* Only support ipv4 */ + ret = EFI_UNSUPPORTED; + goto out; + } + + if (!ipv4_node->use_default_address) { + efi_net_set_addr((struct efi_ipv4_address *)&ipv4_node->local_address, + (struct efi_ipv4_address *)&ipv4_node->local_subnet, NULL); + } + + http_instance->current_offset = 0; + http_instance->configured = true; + +out: + return EFI_EXIT(ret); +} + +/* + * efi_http_request() - Queues an HTTP request to this HTTP instance + * + * This function implements EFI_HTTP_PROTOCOL.Request(). + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @token: pointer to storage containing HTTP request token + * Return: status code + */ +static efi_status_t EFIAPI efi_http_request(struct efi_http_protocol *this, + struct efi_http_token *token) +{ + EFI_ENTRY("%p, %p", this, token); + + efi_status_t ret = EFI_SUCCESS; + u8 *tmp; + u8 url_8[1024]; + u16 *url_16; + enum efi_http_method current_method; + struct efi_http_instance *http_instance; + + if (!token || !this || !token->message || + !token->message->data.request) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + + http_instance = (struct efi_http_instance *)this; + + if (!http_instance->configured) { + ret = EFI_NOT_STARTED; + goto out; + } + + current_method = token->message->data.request->method; + url_16 = token->message->data.request->url; + + /* Parse URL. It comes in UCS-2 encoding and follows RFC3986 */ + tmp = url_8; + utf16_utf8_strncpy((char **)&tmp, url_16, 1024); + + ret = efi_net_do_request(url_8, current_method, &http_instance->http_load_addr, + &http_instance->status_code, &http_instance->file_size, + http_instance->headers_buffer); + if (ret != EFI_SUCCESS) + goto out; + + // We have a successful request + efi_net_parse_headers(&http_instance->num_headers, http_instance->headers); + http_instance->current_offset = 0; + token->status = EFI_SUCCESS; + goto out_signal; + +out_signal: + efi_signal_event(token->event); +out: + return EFI_EXIT(ret); +} + +/* + * efi_http_cancel() - Abort an asynchronous HTTP request or response token + * + * This function implements EFI_HTTP_PROTOCOL.Cancel(). + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @token: pointer to storage containing HTTP request token + * Return: status code + */ +static efi_status_t EFIAPI efi_http_cancel(struct efi_http_protocol *this, + struct efi_http_token *token) +{ + EFI_ENTRY("%p, %p", this, token); + + efi_status_t ret = EFI_UNSUPPORTED; + + return EFI_EXIT(ret); +} + +/* + * efi_http_response() - Queues an HTTP response to this HTTP instance + * + * This function implements EFI_HTTP_PROTOCOL.Response(). + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @token: pointer to storage containing HTTP request token + * Return: status code + */ +static efi_status_t EFIAPI efi_http_response(struct efi_http_protocol *this, + struct efi_http_token *token) +{ + EFI_ENTRY("%p, %p", this, token); + + efi_status_t ret = EFI_SUCCESS; + struct efi_http_instance *http_instance; + struct efi_http_header **client_headers; + struct efi_http_response_data *response; + + if (!token || !this || !token->message) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + + http_instance = (struct efi_http_instance *)this; + + // Set HTTP status code + if (token->message->data.response) { // TODO extra check, see spec. + response = token->message->data.response; + response->status_code = efi_u32_to_httpstatus(http_instance->status_code); + } + + client_headers = &token->message->headers; + + ret = efi_allocate_pool(EFI_BOOT_SERVICES_DATA, + (http_instance->num_headers) * sizeof(struct efi_http_header), + (void **)client_headers); // This is deallocated by the client. + if (ret != EFI_SUCCESS) + goto out_bad_signal; + + // Send headers + token->message->header_count = http_instance->num_headers; + for (int i = 0; i < http_instance->num_headers; i++) { + (*client_headers)[i].field_name = http_instance->headers[i].name; + (*client_headers)[i].field_value = http_instance->headers[i].value; + } + + ret = efi_http_send_data(token->message->body, &token->message->body_length, http_instance); + if (ret != EFI_SUCCESS) + goto out_bad_signal; + + token->status = EFI_SUCCESS; + goto out_signal; + +out_bad_signal: + token->status = EFI_ABORTED; +out_signal: + efi_signal_event(token->event); +out: + return EFI_EXIT(ret); +} + +/* + * efi_http_poll() - Polls for incoming data packets and processes outgoing data packets + * + * This function implements EFI_HTTP_PROTOCOL.Poll(). + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @token: pointer to storage containing HTTP request token + * Return: status code + */ +static efi_status_t EFIAPI efi_http_poll(struct efi_http_protocol *this) +{ + EFI_ENTRY("%p", this); + + efi_status_t ret = EFI_UNSUPPORTED; + + return EFI_EXIT(ret); +} + +/* EFI_HTTP_SERVICE_BINDING_PROTOCOL */ + +/* + * efi_http_service_binding_create_child() - Creates a child handle + * and installs a protocol + * + * This function implements EFI_HTTP_SERVICE_BINDING.CreateChild(). + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @child_handle: pointer to child handle + * Return: status code + */ +static efi_status_t EFIAPI efi_http_service_binding_create_child( + struct efi_service_binding_protocol *this, + efi_handle_t *child_handle) +{ + EFI_ENTRY("%p, %p", this, child_handle); + + efi_status_t ret = EFI_SUCCESS; + struct efi_http_instance *new_instance; + + if (!child_handle) + return EFI_EXIT(EFI_INVALID_PARAMETER); + + new_instance = calloc(1, sizeof(struct efi_http_instance)); + if (!new_instance) { + ret = EFI_OUT_OF_RESOURCES; + goto failure_to_add_protocol; + } + + if (*child_handle) { + new_instance->handle = *child_handle; + goto install; + } + + new_instance->handle = calloc(1, sizeof(struct efi_object)); + if (!new_instance->handle) { + efi_free_pool((void *)new_instance); + ret = EFI_OUT_OF_RESOURCES; + goto failure_to_add_protocol; + } + + efi_add_handle(new_instance->handle); + *child_handle = new_instance->handle; + +install: + ret = efi_add_protocol(new_instance->handle, &efi_http_guid, + &new_instance->http); + if (ret != EFI_SUCCESS) + goto failure_to_add_protocol; + + new_instance->http.get_mode_data = efi_http_get_mode_data; + new_instance->http.configure = efi_http_configure; + new_instance->http.request = efi_http_request; + new_instance->http.cancel = efi_http_cancel; + new_instance->http.response = efi_http_response; + new_instance->http.poll = efi_http_poll; + ++num_instances; + + return EFI_EXIT(EFI_SUCCESS); + +failure_to_add_protocol: + return EFI_EXIT(ret); +} + +/* + * efi_http_service_binding_destroy_child() - Destroys a child handle with + * a protocol installed on it + * + * This function implements EFI_HTTP_SERVICE_BINDING.DestroyChild(). + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @child_handle: child handle + * Return: status code + */ +static efi_status_t EFIAPI efi_http_service_binding_destroy_child( + struct efi_service_binding_protocol *this, + efi_handle_t child_handle) +{ + EFI_ENTRY("%p, %p", this, child_handle); + efi_status_t ret = EFI_SUCCESS; + struct efi_http_instance *http_instance; + struct efi_handler *phandler; + void *protocol_interface; + + if (num_instances == 0) + return EFI_EXIT(EFI_NOT_FOUND); + + if (!child_handle) + return EFI_EXIT(EFI_INVALID_PARAMETER); + + efi_search_protocol(child_handle, &efi_http_guid, &phandler); + + if (phandler) + protocol_interface = phandler->protocol_interface; + + ret = efi_delete_handle(child_handle); + if (ret != EFI_SUCCESS) + return EFI_EXIT(ret); + + http_instance = (struct efi_http_instance *)protocol_interface; + efi_free_pool(http_instance->http_load_addr); + http_instance->http_load_addr = NULL; + + free(protocol_interface); + + num_instances--; + + return EFI_EXIT(EFI_SUCCESS); +} + +/** + * efi_http_register() - register the http protocol + * + */ +efi_status_t efi_http_register(const efi_handle_t handle, + struct efi_service_binding_protocol *http_service_binding) +{ + efi_status_t r = EFI_SUCCESS; + + r = efi_add_protocol(handle, &efi_http_service_binding_guid, + http_service_binding); + if (r != EFI_SUCCESS) + goto failure_to_add_protocol; + + http_service_binding->create_child = efi_http_service_binding_create_child; + http_service_binding->destroy_child = efi_http_service_binding_destroy_child; + + return EFI_SUCCESS; +failure_to_add_protocol: + return r; +} + +enum efi_http_status_code efi_u32_to_httpstatus(u32 status) +{ + switch (status) { + case 100: return HTTP_STATUS_100_CONTINUE; + case 101: return HTTP_STATUS_101_SWITCHING_PROTOCOLS; + case 200: return HTTP_STATUS_200_OK; + case 201: return HTTP_STATUS_201_CREATED; + case 202: return HTTP_STATUS_202_ACCEPTED; + case 203: return HTTP_STATUS_203_NON_AUTHORITATIVE_INFORMATION; + case 204: return HTTP_STATUS_204_NO_CONTENT; + case 205: return HTTP_STATUS_205_RESET_CONTENT; + case 206: return HTTP_STATUS_206_PARTIAL_CONTENT; + case 300: return HTTP_STATUS_300_MULTIPLE_CHOICES; + case 301: return HTTP_STATUS_301_MOVED_PERMANENTLY; + case 302: return HTTP_STATUS_302_FOUND; + case 303: return HTTP_STATUS_303_SEE_OTHER; + case 304: return HTTP_STATUS_304_NOT_MODIFIED; + case 305: return HTTP_STATUS_305_USE_PROXY; + case 307: return HTTP_STATUS_307_TEMPORARY_REDIRECT; + case 400: return HTTP_STATUS_400_BAD_REQUEST; + case 401: return HTTP_STATUS_401_UNAUTHORIZED; + case 402: return HTTP_STATUS_402_PAYMENT_REQUIRED; + case 403: return HTTP_STATUS_403_FORBIDDEN; + case 404: return HTTP_STATUS_404_NOT_FOUND; + case 405: return HTTP_STATUS_405_METHOD_NOT_ALLOWED; + case 406: return HTTP_STATUS_406_NOT_ACCEPTABLE; + case 407: return HTTP_STATUS_407_PROXY_AUTHENTICATION_REQUIRED; + case 408: return HTTP_STATUS_408_REQUEST_TIME_OUT; + case 409: return HTTP_STATUS_409_CONFLICT; + case 410: return HTTP_STATUS_410_GONE; + case 411: return HTTP_STATUS_411_LENGTH_REQUIRED; + case 412: return HTTP_STATUS_412_PRECONDITION_FAILED; + case 413: return HTTP_STATUS_413_REQUEST_ENTITY_TOO_LARGE; + case 414: return HTTP_STATUS_414_REQUEST_URI_TOO_LARGE; + case 415: return HTTP_STATUS_415_UNSUPPORTED_MEDIA_TYPE; + case 416: return HTTP_STATUS_416_REQUESTED_RANGE_NOT_SATISFIED; + case 417: return HTTP_STATUS_417_EXPECTATION_FAILED; + case 500: return HTTP_STATUS_500_INTERNAL_SERVER_ERROR; + case 501: return HTTP_STATUS_501_NOT_IMPLEMENTED; + case 502: return HTTP_STATUS_502_BAD_GATEWAY; + case 503: return HTTP_STATUS_503_SERVICE_UNAVAILABLE; + case 504: return HTTP_STATUS_504_GATEWAY_TIME_OUT; + case 505: return HTTP_STATUS_505_HTTP_VERSION_NOT_SUPPORTED; + case 308: return HTTP_STATUS_308_PERMANENT_REDIRECT; + default: return HTTP_STATUS_UNSUPPORTED_STATUS; + } +} diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index 0ddf69a0918..bb58cf1badb 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -13,6 +13,7 @@ #include <efi_loader.h> #include <log.h> #include <malloc.h> +#include <mapmem.h> #include <pe.h> #include <sort.h> #include <crypto/mscode.h> @@ -977,7 +978,7 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, } /* Flush cache */ - flush_cache((ulong)efi_reloc, + flush_cache(map_to_sysmem(efi_reloc), ALIGN(virt_size, EFI_CACHELINE_SIZE)); /* diff --git a/lib/efi_loader/efi_ipconfig.c b/lib/efi_loader/efi_ipconfig.c new file mode 100644 index 00000000000..0b247a4c028 --- /dev/null +++ b/lib/efi_loader/efi_ipconfig.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Implementation of EFI_IP4_CONFIG2_PROTOCOL + * + */ + +#include <efi_loader.h> +#include <image.h> +#include <malloc.h> +#include <mapmem.h> +#include <net.h> + +static const efi_guid_t efi_ip4_config2_guid = EFI_IP4_CONFIG2_PROTOCOL_GUID; + +struct efi_ip4_config2_manual_address current_http_ip; +static enum efi_ip4_config2_policy current_policy; +static char current_mac_addr[32]; + +/* EFI_IP4_CONFIG2_PROTOCOL */ + +/* + * efi_ip4_config2_set_data() - Set the configuration for the EFI IPv4 network + * stack running on the communication device + * + * This function implements EFI_IP4_CONFIG2_PROTOCOL.SetData() + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @data_type: the type of data to set + * @data_size: size of the buffer pointed to by data in bytes + * @data: the data buffer to set + * Return: status code + */ +static efi_status_t EFIAPI efi_ip4_config2_set_data(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + efi_uintn_t data_size, + void *data) +{ + EFI_ENTRY("%p, %d, %zu, %p", this, data_type, data_size, data); + efi_status_t ret = EFI_SUCCESS; + + if (!this || (data && !data_size) || (!data && data_size)) + return EFI_EXIT(EFI_INVALID_PARAMETER); + + switch (data_type) { + case EFI_IP4_CONFIG2_DATA_TYPE_INTERFACEINFO: + return EFI_EXIT(EFI_WRITE_PROTECTED); + case EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS: + if (current_policy != EFI_IP4_CONFIG2_POLICY_STATIC) + return EFI_EXIT(EFI_WRITE_PROTECTED); + if (!data_size && !data) { + memset((void *)¤t_http_ip, 0, + sizeof(current_http_ip)); + return EFI_EXIT(EFI_SUCCESS); + } + if (data && data_size == sizeof(struct efi_ip4_config2_manual_address)) { + memcpy((void *)¤t_http_ip, data, + sizeof(struct efi_ip4_config2_manual_address)); + efi_net_set_addr(¤t_http_ip.address, + ¤t_http_ip.subnet_mask, NULL); + return EFI_EXIT(EFI_SUCCESS); + } + return EFI_EXIT(EFI_BAD_BUFFER_SIZE); + case EFI_IP4_CONFIG2_DATA_TYPE_POLICY: + if (data && data_size == sizeof(enum efi_ip4_config2_policy)) { + current_policy = *(enum efi_ip4_config2_policy *)data; + return EFI_EXIT(EFI_SUCCESS); + } + return EFI_EXIT(EFI_BAD_BUFFER_SIZE); + + default: + return EFI_EXIT(EFI_UNSUPPORTED); + } + + return EFI_EXIT(ret); +} + +/* + * efi_ip4_config2_get_data() - Get the configuration for the EFI IPv4 network + * stack running on the communication device + * + * This function implements EFI_IP4_CONFIG2_PROTOCOL.GetData() + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @data_type: the type of data to get + * @data_size: size + * @data: the data buffer + * Return: status code + */ +static efi_status_t EFIAPI efi_ip4_config2_get_data(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + efi_uintn_t *data_size, + void *data) +{ + EFI_ENTRY("%p, %d, %p, %p", this, data_type, data_size, data); + + efi_status_t ret = EFI_SUCCESS; + struct efi_ip4_config2_interface_info *info; + int tmp; + + if (!this || !data_size) + return EFI_EXIT(EFI_INVALID_PARAMETER); + + if (*data_size && !data) + return EFI_EXIT(EFI_INVALID_PARAMETER); + + tmp = sizeof(struct efi_ip4_config2_interface_info) + sizeof(struct efi_ip4_route_table); + + switch (data_type) { + case EFI_IP4_CONFIG2_DATA_TYPE_INTERFACEINFO: + if (*data_size < tmp) { + *data_size = tmp; + return EFI_EXIT(EFI_BUFFER_TOO_SMALL); + } + + info = (struct efi_ip4_config2_interface_info *)data; + memset(info, 0, sizeof(*info)); + + info->hw_address_size = 6; + memcpy(info->hw_address.mac_addr, current_mac_addr, 6); + // Set the route table size + + info->route_table_size = 0; + break; + case EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS: + if (*data_size < sizeof(struct efi_ip4_config2_manual_address)) { + *data_size = sizeof(struct efi_ip4_config2_manual_address); + return EFI_EXIT(EFI_BUFFER_TOO_SMALL); + } + + efi_net_get_addr(¤t_http_ip.address, ¤t_http_ip.subnet_mask, NULL); + memcpy(data, (void *)¤t_http_ip, + sizeof(struct efi_ip4_config2_manual_address)); + + break; + default: + return EFI_EXIT(EFI_NOT_FOUND); + } + return EFI_EXIT(ret); +} + +/* + * efi_ip4_config2_register_notify() - Register an event that is to be signaled whenever + * a configuration process on the specified configuration + * data is done + * + * This function implements EFI_IP4_CONFIG2_PROTOCOL.RegisterDataNotify() + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @data_type: the type of data to register the event for + * @event: the event to register + * Return: status code + */ +static efi_status_t EFIAPI efi_ip4_config2_register_notify(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + struct efi_event *event) +{ + EFI_ENTRY("%p, %d, %p", this, data_type, event); + + return EFI_EXIT(EFI_UNSUPPORTED); +} + +/* + * efi_ip4_config2_unregister_notify() - Remove a previously registered eventfor + * the specified configuration data + * + * This function implements EFI_IP4_CONFIG2_PROTOCOL.UnregisterDataNotify() + * See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @data_type: the type of data to remove the event for + * @event: the event to unregister + * Return: status code + */ +static efi_status_t EFIAPI efi_ip4_config2_unregister_notify(struct efi_ip4_config2_protocol *this, + enum efi_ip4_config2_data_type data_type, + struct efi_event *event) +{ + EFI_ENTRY("%p, %d, %p", this, data_type, event); + + return EFI_EXIT(EFI_UNSUPPORTED); +} + +/** + * efi_ipconfig_register() - register the ip4_config2 protocol + * + */ +efi_status_t efi_ipconfig_register(const efi_handle_t handle, + struct efi_ip4_config2_protocol *ip4config) +{ + efi_status_t r = EFI_SUCCESS; + + r = efi_add_protocol(handle, &efi_ip4_config2_guid, + ip4config); + if (r != EFI_SUCCESS) { + log_err("ERROR: Failure to add protocol\n"); + return r; + } + + memcpy(current_mac_addr, eth_get_ethaddr(), 6); + + ip4config->set_data = efi_ip4_config2_set_data; + ip4config->get_data = efi_ip4_config2_get_data; + ip4config->register_data_notify = efi_ip4_config2_register_notify; + ip4config->unregister_data_notify = efi_ip4_config2_unregister_notify; + + return EFI_SUCCESS; +} diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index d2f5d563f2a..e493934c713 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -451,7 +451,7 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type, enum efi_memory_type memory_type, efi_uintn_t pages, uint64_t *memory) { - u64 len; + u64 efi_addr, len; uint flags; efi_status_t ret; phys_addr_t addr; @@ -499,14 +499,17 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type, return EFI_INVALID_PARAMETER; } - addr = (u64)(uintptr_t)map_sysmem(addr, 0); + efi_addr = (u64)(uintptr_t)map_sysmem(addr, 0); /* Reserve that map in our memory maps */ - ret = efi_add_memory_map_pg(addr, pages, memory_type, true); - if (ret != EFI_SUCCESS) + ret = efi_add_memory_map_pg(efi_addr, pages, memory_type, true); + if (ret != EFI_SUCCESS) { /* Map would overlap, bail out */ + lmb_free_flags(addr, (u64)pages << EFI_PAGE_SHIFT, flags); + unmap_sysmem((void *)(uintptr_t)efi_addr); return EFI_OUT_OF_RESOURCES; + } - *memory = addr; + *memory = efi_addr; return EFI_SUCCESS; } @@ -546,6 +549,8 @@ efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages) if (status) return EFI_NOT_FOUND; + unmap_sysmem((void *)(uintptr_t)memory); + return ret; } diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c index 7cd536705f4..67593ef50c0 100644 --- a/lib/efi_loader/efi_net.c +++ b/lib/efi_loader/efi_net.c @@ -16,7 +16,10 @@ */ #include <efi_loader.h> +#include <dm.h> +#include <linux/sizes.h> #include <malloc.h> +#include <vsprintf.h> #include <net.h> static const efi_guid_t efi_net_guid = EFI_SIMPLE_NETWORK_PROTOCOL_GUID; @@ -32,6 +35,19 @@ static int rx_packet_num; static struct efi_net_obj *netobj; /* + * The current network device path. This device path is updated when a new + * bootfile is downloaded from the network. If then the bootfile is loaded + * as an efi image, net_dp is passed as the device path of the loaded image. + */ +static struct efi_device_path *net_dp; + +static struct wget_http_info efi_wget_info = { + .set_bootdev = false, + .check_buffer_size = true, + +}; + +/* * The notification function of this event is called in every timer cycle * to check if a new network packet has been received. */ @@ -44,11 +60,13 @@ static struct efi_event *wait_for_packet; /** * struct efi_net_obj - EFI object representing a network interface * - * @header: EFI object header - * @net: simple network protocol interface - * @net_mode: status of the network interface - * @pxe: PXE base code protocol interface - * @pxe_mode: status of the PXE base code protocol + * @header: EFI object header + * @net: simple network protocol interface + * @net_mode: status of the network interface + * @pxe: PXE base code protocol interface + * @pxe_mode: status of the PXE base code protocol + * @ip4_config2: IP4 Config2 protocol interface + * @http_service_binding: Http service binding protocol interface */ struct efi_net_obj { struct efi_object header; @@ -56,6 +74,12 @@ struct efi_net_obj { struct efi_simple_network_mode net_mode; struct efi_pxe_base_code_protocol pxe; struct efi_pxe_mode pxe_mode; +#if IS_ENABLED(CONFIG_EFI_IP4_CONFIG2_PROTOCOL) + struct efi_ip4_config2_protocol ip4_config2; +#endif +#if IS_ENABLED(CONFIG_EFI_HTTP_PROTOCOL) + struct efi_service_binding_protocol http_service_binding; +#endif }; /* @@ -901,8 +925,10 @@ efi_status_t efi_net_register(void) &netobj->net); if (r != EFI_SUCCESS) goto failure_to_add_protocol; + if (!net_dp) + efi_net_set_dp("Net", NULL); r = efi_add_protocol(&netobj->header, &efi_guid_device_path, - efi_dp_from_eth()); + net_dp); if (r != EFI_SUCCESS) goto failure_to_add_protocol; r = efi_add_protocol(&netobj->header, &efi_pxe_base_code_protocol_guid, @@ -981,6 +1007,25 @@ efi_status_t efi_net_register(void) return r; } +#if IS_ENABLED(CONFIG_EFI_IP4_CONFIG2_PROTOCOL) + r = efi_ipconfig_register(&netobj->header, &netobj->ip4_config2); + if (r != EFI_SUCCESS) + goto failure_to_add_protocol; +#endif + +#ifdef CONFIG_EFI_HTTP_PROTOCOL + r = efi_http_register(&netobj->header, &netobj->http_service_binding); + if (r != EFI_SUCCESS) + goto failure_to_add_protocol; + /* + * No harm on doing the following. If the PXE handle is present, the client could + * find it and try to get its IP address from it. In here the PXE handle is present + * but the PXE protocol is not yet implmenented, so we add this in the meantime. + */ + efi_net_get_addr((struct efi_ipv4_address *)&netobj->pxe_mode.station_ip, + (struct efi_ipv4_address *)&netobj->pxe_mode.subnet_mask, NULL); +#endif + return EFI_SUCCESS; failure_to_add_protocol: printf("ERROR: Failure to add protocol\n"); @@ -997,3 +1042,317 @@ out_of_resources: printf("ERROR: Out of memory\n"); return EFI_OUT_OF_RESOURCES; } + +/** + * efi_net_set_dp() - set device path of efi net device + * + * This gets called to update the device path when a new boot + * file is downloaded + * + * @dev: dev to set the device path from + * @server: remote server address + * Return: status code + */ +efi_status_t efi_net_set_dp(const char *dev, const char *server) +{ + efi_free_pool(net_dp); + + net_dp = NULL; + if (!strcmp(dev, "Net")) + net_dp = efi_dp_from_eth(); + else if (!strcmp(dev, "Http")) + net_dp = efi_dp_from_http(server); + + if (!net_dp) + return EFI_OUT_OF_RESOURCES; + + return EFI_SUCCESS; +} + +/** + * efi_net_get_dp() - get device path of efi net device + * + * Produce a copy of the current device path + * + * @dp: copy of the current device path, or NULL on error + */ +void efi_net_get_dp(struct efi_device_path **dp) +{ + if (!dp) + return; + if (!net_dp) + efi_net_set_dp("Net", NULL); + if (net_dp) + *dp = efi_dp_dup(net_dp); +} + +/** + * efi_net_get_addr() - get IP address information + * + * Copy the current IP address, mask, and gateway into the + * efi_ipv4_address structs pointed to by ip, mask and gw, + * respectively. + * + * @ip: pointer to an efi_ipv4_address struct to + * be filled with the current IP address + * @mask: pointer to an efi_ipv4_address struct to + * be filled with the current network mask + * @gw: pointer to an efi_ipv4_address struct to be + * filled with the current network gateway + */ +void efi_net_get_addr(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *gw) +{ +#ifdef CONFIG_NET_LWIP + char ipstr[] = "ipaddr\0\0"; + char maskstr[] = "netmask\0\0"; + char gwstr[] = "gatewayip\0\0"; + int idx; + struct in_addr tmp; + char *env; + + idx = dev_seq(eth_get_dev()); + + if (idx < 0 || idx > 99) { + log_err("unexpected idx %d\n", idx); + return; + } + + if (idx) { + sprintf(ipstr, "ipaddr%d", idx); + sprintf(maskstr, "netmask%d", idx); + sprintf(gwstr, "gatewayip%d", idx); + } + + env = env_get(ipstr); + if (env && ip) { + tmp = string_to_ip(env); + memcpy(ip, &tmp, sizeof(tmp)); + } + + env = env_get(maskstr); + if (env && mask) { + tmp = string_to_ip(env); + memcpy(mask, &tmp, sizeof(tmp)); + } + env = env_get(gwstr); + if (env && gw) { + tmp = string_to_ip(env); + memcpy(gw, &tmp, sizeof(tmp)); + } +#else + if (ip) + memcpy(ip, &net_ip, sizeof(net_ip)); + if (mask) + memcpy(mask, &net_netmask, sizeof(net_netmask)); +#endif +} + +/** + * efi_net_set_addr() - set IP address information + * + * Set the current IP address, mask, and gateway to the + * efi_ipv4_address structs pointed to by ip, mask and gw, + * respectively. + * + * @ip: pointer to new IP address + * @mask: pointer to new network mask to set + * @gw: pointer to new network gateway + */ +void efi_net_set_addr(struct efi_ipv4_address *ip, + struct efi_ipv4_address *mask, + struct efi_ipv4_address *gw) +{ +#ifdef CONFIG_NET_LWIP + char ipstr[] = "ipaddr\0\0"; + char maskstr[] = "netmask\0\0"; + char gwstr[] = "gatewayip\0\0"; + int idx; + struct in_addr *addr; + char tmp[46]; + + idx = dev_seq(eth_get_dev()); + + if (idx < 0 || idx > 99) { + log_err("unexpected idx %d\n", idx); + return; + } + + if (idx) { + sprintf(ipstr, "ipaddr%d", idx); + sprintf(maskstr, "netmask%d", idx); + sprintf(gwstr, "gatewayip%d", idx); + } + + if (ip) { + addr = (struct in_addr *)ip; + ip_to_string(*addr, tmp); + env_set(ipstr, tmp); + } + + if (mask) { + addr = (struct in_addr *)mask; + ip_to_string(*addr, tmp); + env_set(maskstr, tmp); + } + + if (gw) { + addr = (struct in_addr *)gw; + ip_to_string(*addr, tmp); + env_set(gwstr, tmp); + } +#else + if (ip) + memcpy(&net_ip, ip, sizeof(*ip)); + if (mask) + memcpy(&net_netmask, mask, sizeof(*mask)); +#endif +} + +/** + * efi_net_set_buffer() - allocate a buffer of min 64K + * + * @buffer: allocated buffer + * @size: desired buffer size + * Return: status code + */ +static efi_status_t efi_net_set_buffer(void **buffer, size_t size) +{ + efi_status_t ret = EFI_SUCCESS; + + if (size < SZ_64K) + size = SZ_64K; + + *buffer = efi_alloc(size); + if (!*buffer) + ret = EFI_OUT_OF_RESOURCES; + + efi_wget_info.buffer_size = (ulong)size; + + return ret; +} + +/** + * efi_net_parse_headers() - parse HTTP headers + * + * Parses the raw buffer efi_wget_info.headers into an array headers + * of efi structs http_headers. The array should be at least + * MAX_HTTP_HEADERS long. + * + * @num_headers: number of headers + * @headers: caller provided array of struct http_headers + */ +void efi_net_parse_headers(ulong *num_headers, struct http_header *headers) +{ + if (!num_headers || !headers) + return; + + // Populate info with http headers. + *num_headers = 0; + const uchar *line_start = efi_wget_info.headers; + const uchar *line_end; + ulong count; + struct http_header *current_header; + const uchar *separator; + size_t name_length, value_length; + + // Skip the first line (request or status line) + line_end = strstr(line_start, "\r\n"); + + if (line_end) + line_start = line_end + 2; + + while ((line_end = strstr(line_start, "\r\n")) != NULL) { + count = *num_headers; + if (line_start == line_end || count >= MAX_HTTP_HEADERS) + break; + current_header = headers + count; + separator = strchr(line_start, ':'); + if (separator) { + name_length = separator - line_start; + ++separator; + while (*separator == ' ') + ++separator; + value_length = line_end - separator; + if (name_length < MAX_HTTP_HEADER_NAME && + value_length < MAX_HTTP_HEADER_VALUE) { + strncpy(current_header->name, line_start, name_length); + current_header->name[name_length] = '\0'; + strncpy(current_header->value, separator, value_length); + current_header->value[value_length] = '\0'; + (*num_headers)++; + } + } + line_start = line_end + 2; + } +} + +/** + * efi_net_do_request() - issue an HTTP request using wget + * + * @url: url + * @method: HTTP method + * @buffer: data buffer + * @status_code: HTTP status code + * @file_size: file size in bytes + * @headers_buffer: headers buffer + * Return: status code + */ +efi_status_t efi_net_do_request(u8 *url, enum efi_http_method method, void **buffer, + u32 *status_code, ulong *file_size, char *headers_buffer) +{ + efi_status_t ret = EFI_SUCCESS; + int wget_ret; + static bool last_head; + + if (!buffer || !file_size) + return EFI_ABORTED; + + efi_wget_info.method = (enum wget_http_method)method; + efi_wget_info.headers = headers_buffer; + + switch (method) { + case HTTP_METHOD_GET: + ret = efi_net_set_buffer(buffer, last_head ? (size_t)efi_wget_info.hdr_cont_len : 0); + if (ret != EFI_SUCCESS) + goto out; + wget_ret = wget_request((ulong)*buffer, url, &efi_wget_info); + if ((ulong)efi_wget_info.hdr_cont_len > efi_wget_info.buffer_size) { + // Try again with updated buffer size + efi_free_pool(*buffer); + ret = efi_net_set_buffer(buffer, (size_t)efi_wget_info.hdr_cont_len); + if (ret != EFI_SUCCESS) + goto out; + if (wget_request((ulong)*buffer, url, &efi_wget_info)) { + efi_free_pool(*buffer); + ret = EFI_DEVICE_ERROR; + goto out; + } + } else if (wget_ret) { + efi_free_pool(*buffer); + ret = EFI_DEVICE_ERROR; + goto out; + } + // Pass the actual number of received bytes to the application + *file_size = efi_wget_info.file_size; + *status_code = efi_wget_info.status_code; + last_head = false; + break; + case HTTP_METHOD_HEAD: + ret = efi_net_set_buffer(buffer, 0); + if (ret != EFI_SUCCESS) + goto out; + wget_request((ulong)*buffer, url, &efi_wget_info); + *file_size = 0; + *status_code = efi_wget_info.status_code; + last_head = true; + break; + default: + ret = EFI_UNSUPPORTED; + break; + } + +out: + return ret; +} diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c index 866a529857e..572c6b5bf63 100644 --- a/lib/efi_loader/efi_tcg2.c +++ b/lib/efi_loader/efi_tcg2.c @@ -607,12 +607,9 @@ efi_tcg2_hash_log_extend_event(struct efi_tcg2_protocol *this, u64 flags, * Format" */ if (flags & PE_COFF_IMAGE) { - IMAGE_NT_HEADERS32 *nt; - ret = efi_check_pe((void *)(uintptr_t)data_to_hash, - data_to_hash_len, (void **)&nt); + data_to_hash_len, NULL); if (ret != EFI_SUCCESS) { - log_err("Not a valid PE-COFF file\n"); ret = EFI_UNSUPPORTED; goto out; } diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile index 414701893f6..17fbfad116f 100644 --- a/lib/efi_selftest/Makefile +++ b/lib/efi_selftest/Makefile @@ -52,6 +52,8 @@ efi_selftest_watchdog.o obj-$(CONFIG_EFI_ECPT) += efi_selftest_ecpt.o obj-$(CONFIG_NETDEVICES) += efi_selftest_snp.o +obj-$(CONFIG_EFI_HTTP_PROTOCOL) += efi_selftest_http.o +obj-$(CONFIG_EFI_HTTP_PROTOCOL) += efi_selftest_ipconfig.o obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_selftest_devicepath.o obj-$(CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2) += \ diff --git a/lib/efi_selftest/efi_selftest_http.c b/lib/efi_selftest/efi_selftest_http.c new file mode 100644 index 00000000000..b63c401f055 --- /dev/null +++ b/lib/efi_selftest/efi_selftest_http.c @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * efi_selftest_http + * + * This unit test covers the IPv4 Config2 Protocol, Http Service Binding Protocol, + * and Http Protocol. + * + * An Http HEAD and an Http GET request are sent to the same destination. The test + * is successful if the HEAD request gets a response with a valid Content-Length header + * and the subsequent GET request receives the amount of bytes informed by the previous + * Content-Length header. + * + */ + +#include <efi_selftest.h> +#include <charset.h> +#include <net.h> + +static struct efi_boot_services *boottime; + +static struct efi_http_protocol *http; +static struct efi_service_binding_protocol *http_service; +static struct efi_ip4_config2_protocol *ip4_config2; +static efi_handle_t http_protocol_handle; + +static const efi_guid_t efi_http_guid = EFI_HTTP_PROTOCOL_GUID; +static const efi_guid_t efi_http_service_binding_guid = EFI_HTTP_SERVICE_BINDING_PROTOCOL_GUID; +static const efi_guid_t efi_ip4_config2_guid = EFI_IP4_CONFIG2_PROTOCOL_GUID; +static int callback_done; + +/* + * Setup unit test. + * + * + * @handle: handle of the loaded image + * @systable: system table + * Return: EFI_ST_SUCCESS for success + */ +static int setup(const efi_handle_t handle, + const struct efi_system_table *systable) +{ + efi_status_t ret; + efi_handle_t *net_handle; + efi_uintn_t num_handles; + efi_handle_t *handles; + struct efi_http_config_data http_config; + struct efi_httpv4_access_point ipv4_node; + + boottime = systable->boottime; + + num_handles = 0; + boottime->locate_handle_buffer(BY_PROTOCOL, &efi_ip4_config2_guid, + NULL, &num_handles, &handles); + + if (!num_handles) { + efi_st_error("Failed to locate ipv4 config2 protocol\n"); + return EFI_ST_FAILURE; + } + + for (net_handle = handles; num_handles--; net_handle++) { + ret = boottime->open_protocol(*net_handle, &efi_ip4_config2_guid, + (void **)&ip4_config2, 0, 0, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (ret != EFI_SUCCESS || !ip4_config2) + continue; + ret = boottime->open_protocol(*net_handle, + &efi_http_service_binding_guid, + (void **)&http_service, 0, 0, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (ret != EFI_SUCCESS || !http_service) + continue; + break; // Get first handle that supports both protocols + } + + if (!ip4_config2 || !http_service) { + efi_st_error("Failed to open ipv4 config2 or http service binding protocol\n"); + return EFI_ST_FAILURE; + } + + http_protocol_handle = NULL; + ret = http_service->create_child(http_service, &http_protocol_handle); + if (ret != EFI_SUCCESS || !http_protocol_handle) { + efi_st_error("Failed to create an http service instance\n"); + return EFI_ST_FAILURE; + } + + ret = boottime->open_protocol(http_protocol_handle, &efi_http_guid, + (void **)&http, 0, 0, EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (ret != EFI_SUCCESS || !http) { + efi_st_error("Failed to open http protocol\n"); + return EFI_ST_FAILURE; + } + efi_st_printf("HTTP Service Binding: child created successfully\n"); + + http_config.http_version = HTTPVERSION11; + http_config.is_ipv6 = false; + http_config.access_point.ipv4_node = &ipv4_node; + ipv4_node.use_default_address = true; + + ret = http->configure(http, &http_config); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed to configure http instance\n"); + return EFI_ST_FAILURE; + } + + return EFI_ST_SUCCESS; +} + +void EFIAPI efi_test_http_callback(struct efi_event *event, void *context) +{ + callback_done = 1; +} + +/* + * Execute unit test. + * + * + * Return: EFI_ST_SUCCESS for success + */ +static int execute(void) +{ + efi_status_t ret; + struct efi_http_request_data request_data; + struct efi_http_message request_message; + struct efi_http_token request_token; + struct efi_http_response_data response_data; + struct efi_http_message response_message; + struct efi_http_token response_token; + enum efi_http_status_code status_code; + void *response_buffer; + efi_uintn_t len, sum; + char *url = "http://example.com/"; + u16 url_16[64]; + u16 *tmp; + + /* Setup may have failed */ + if (!ip4_config2 || !http) { + efi_st_error("Cannot proceed with test after setup failure\n"); + return EFI_ST_FAILURE; + } + + tmp = url_16; + utf8_utf16_strcpy(&tmp, url); + request_data.url = url_16; + request_data.method = HTTP_METHOD_GET; + + request_message.data.request = &request_data; + request_message.header_count = 3; + request_message.body_length = 0; + request_message.body = NULL; + + /* request token */ + request_token.event = NULL; + request_token.status = EFI_NOT_READY; + request_token.message = &request_message; + callback_done = 0; + ret = boottime->create_event(EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + efi_test_http_callback, + NULL, + &request_token.event); + + if (ret != EFI_SUCCESS) { + efi_st_error("Failed to create request event\n"); + return EFI_ST_FAILURE; + } + + ret = http->request(http, &request_token); + + if (ret != EFI_SUCCESS) { + boottime->close_event(request_token.event); + efi_st_printf("Failed to proceed with the http request\n"); + return EFI_ST_SUCCESS; + } + + while (!callback_done) + http->poll(http); + + response_data.status_code = HTTP_STATUS_UNSUPPORTED_STATUS; + response_message.data.response = &response_data; + response_message.header_count = 0; + response_message.headers = NULL; + response_message.body_length = 0; + response_message.body = NULL; + response_token.event = NULL; + + ret = boottime->create_event(EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + efi_test_http_callback, + NULL, + &response_token.event); + + if (ret != EFI_SUCCESS) { + boottime->close_event(request_token.event); + efi_st_error("Failed to create response event\n"); + return EFI_ST_FAILURE; + } + + response_token.status = EFI_SUCCESS; + response_token.message = &response_message; + + callback_done = 0; + ret = http->response(http, &response_token); + + if (ret != EFI_SUCCESS) { + efi_st_error("Failed http first response\n"); + goto fail; + } + + while (!callback_done) + http->poll(http); + + if (response_message.data.response->status_code != HTTP_STATUS_200_OK) { + status_code = response_message.data.response->status_code; + if (status_code == HTTP_STATUS_404_NOT_FOUND) { + efi_st_error("File not found\n"); + } else { + efi_st_error("Bad http status %d\n", + response_message.data.response->status_code); + } + goto fail_free_hdr; + } + + ret = boottime->allocate_pool(EFI_LOADER_CODE, response_message.body_length, + &response_buffer); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed allocating response buffer\n"); + goto fail_free_hdr; + } + + len = response_message.body_length; + sum = 0; + while (len) { + response_message.data.response = NULL; + response_message.header_count = 0; + response_message.headers = NULL; + response_message.body_length = len; + response_message.body = response_buffer + sum; + + response_token.message = &response_message; + response_token.status = EFI_NOT_READY; + + callback_done = 0; + ret = http->response(http, &response_token); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed http second response\n"); + goto fail_free_buf; + } + + while (!callback_done) + http->poll(http); + + if (!response_message.body_length) + break; + + len -= response_message.body_length; + sum += response_message.body_length; + } + + if (len) + goto fail_free_buf; + + boottime->free_pool(response_buffer); + if (response_message.headers) + boottime->free_pool(response_message.headers); + boottime->close_event(request_token.event); + boottime->close_event(response_token.event); + efi_st_printf("Efi Http request executed successfully\n"); + return EFI_ST_SUCCESS; + +fail_free_buf: + boottime->free_pool(response_buffer); +fail_free_hdr: + if (response_message.headers) + boottime->free_pool(response_message.headers); +fail: + boottime->close_event(request_token.event); + boottime->close_event(response_token.event); + return EFI_ST_FAILURE; +} + +/* + * Tear down unit test. + * + * Return: EFI_ST_SUCCESS for success + */ +static int teardown(void) +{ + efi_status_t ret; + int exit_status = EFI_ST_SUCCESS; + + if (!http_service || !http_protocol_handle) { + efi_st_error("No handles to destroy http instance"); + exit_status = EFI_ST_FAILURE; + } else { + ret = http_service->destroy_child(http_service, http_protocol_handle); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed to destroy http instance"); + exit_status = EFI_ST_FAILURE; + } + efi_st_printf("HTTP Service Binding: child destroyed successfully\n"); + } + + return exit_status; +} + +EFI_UNIT_TEST(http) = { + .name = "http protocol", + .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT, + .setup = setup, + .execute = execute, + .teardown = teardown, +#ifdef CONFIG_SANDBOX + /* + * Running this test on the sandbox requires setting environment + * variable ethact to a network interface connected to a DHCP server and + * ethrotate to 'no'. + */ + .on_request = true, +#endif +}; diff --git a/lib/efi_selftest/efi_selftest_ipconfig.c b/lib/efi_selftest/efi_selftest_ipconfig.c new file mode 100644 index 00000000000..8d594f5e193 --- /dev/null +++ b/lib/efi_selftest/efi_selftest_ipconfig.c @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * efi_selftest_ipconfig + * + * This unit test covers the IPv4 Config2 Protocol. + * + */ + +#include <efi_selftest.h> +#include <charset.h> +#include <net.h> + +static struct efi_boot_services *boottime; + +static struct efi_ip4_config2_protocol *ip4_config2; +static const efi_guid_t efi_ip4_config2_guid = EFI_IP4_CONFIG2_PROTOCOL_GUID; + +/* + * Setup unit test. + * + * Open IPv4 Config2 protocol + * + * @handle: handle of the loaded image + * @systable: system table + * Return: EFI_ST_SUCCESS for success + */ +static int setup(const efi_handle_t handle, + const struct efi_system_table *systable) +{ + efi_status_t ret; + efi_handle_t *net_handle; + efi_uintn_t num_handles; + efi_handle_t *handles; + + boottime = systable->boottime; + + num_handles = 0; + boottime->locate_handle_buffer(BY_PROTOCOL, &efi_ip4_config2_guid, + NULL, &num_handles, &handles); + + if (!num_handles) { + efi_st_error("Failed to locate ipv4 config2 protocol\n"); + return EFI_ST_FAILURE; + } + + for (net_handle = handles; num_handles--; net_handle++) { + ret = boottime->open_protocol(*net_handle, &efi_ip4_config2_guid, + (void **)&ip4_config2, 0, 0, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (ret != EFI_SUCCESS || !ip4_config2) + continue; + break; // Get first handle that supports ipv4 + } + + if (!ip4_config2) { + efi_st_error("Failed to open ipv4 config2 protocol\n"); + return EFI_ST_FAILURE; + } + + return EFI_ST_SUCCESS; +} + +/* + * Execute unit test. + * + * + * Return: EFI_ST_SUCCESS for success + */ +static int execute(void) +{ + efi_status_t ret; + enum efi_ip4_config2_policy policy; + efi_uintn_t data_size; + struct efi_ip4_config2_manual_address manual_address; + struct efi_ip4_config2_manual_address orig_address; + u8 netmask[] = {255, 255, 255, 0}; + u8 ip[] = {10, 0, 0, 1}; + + /* Setup may have failed */ + if (!ip4_config2) { + efi_st_error("Setup failure, cannot proceed with test\n"); + return EFI_ST_FAILURE; + } + + /* Set policy to static */ + policy = EFI_IP4_CONFIG2_POLICY_STATIC; + ret = ip4_config2->set_data(ip4_config2, EFI_IP4_CONFIG2_DATA_TYPE_POLICY, + sizeof(policy), (void *)&policy); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed to set policy\n"); + return EFI_ST_FAILURE; + } + + /* Save original ip address and netmask */ + data_size = sizeof(manual_address); + ret = ip4_config2->get_data(ip4_config2, EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS, + &data_size, &orig_address); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed to save original ip address and netmask\n"); + return EFI_ST_FAILURE; + } + + /* Set static ip and netmask */ + memcpy(&manual_address.address, ip, + sizeof(struct efi_ipv4_address)); + memcpy(&manual_address.subnet_mask, netmask, + sizeof(struct efi_ipv4_address)); + ret = ip4_config2->set_data(ip4_config2, EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS, + sizeof(manual_address), &manual_address); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed to get ip address and netmask\n"); + return EFI_ST_FAILURE; + } + + /* Try to set interface info, this should fail */ + ret = ip4_config2->set_data(ip4_config2, EFI_IP4_CONFIG2_DATA_TYPE_INTERFACEINFO, 0, NULL); + if (ret == EFI_SUCCESS) { + efi_st_error("Interface info is read-only\n"); + return EFI_ST_FAILURE; + } + + /* Get ip address and netmask and check that they match with the previously set ones */ + data_size = sizeof(manual_address); + ret = ip4_config2->get_data(ip4_config2, EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS, + &data_size, &manual_address); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed to get ip address and netmask\n"); + return EFI_ST_FAILURE; + } + if (memcmp(ip, &manual_address.address, + sizeof(struct efi_ipv4_address)) || + memcmp(netmask, &manual_address.subnet_mask, + sizeof(struct efi_ipv4_address))) { + efi_st_error("Ip address mismatch\n"); + return EFI_ST_FAILURE; + } + + /* Restore original ip address and netmask */ + ret = ip4_config2->set_data(ip4_config2, EFI_IP4_CONFIG2_DATA_TYPE_MANUAL_ADDRESS, + sizeof(orig_address), &orig_address); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed to restore original ip address and netmask\n"); + return EFI_ST_FAILURE; + } + + efi_st_printf("Efi ipconfig test execute succeeded\n"); + return EFI_ST_SUCCESS; +} + +/* + * Tear down unit test. + * + * Return: EFI_ST_SUCCESS for success + */ +static int teardown(void) +{ + int exit_status = EFI_ST_SUCCESS; + + return exit_status; +} + +EFI_UNIT_TEST(ipconfig) = { + .name = "IPv4 config2 protocol", + .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT, + .setup = setup, + .execute = execute, + .teardown = teardown, +#ifdef CONFIG_SANDBOX + /* + * Running this test on the sandbox requires setting environment + * variable ethact to a network interface connected to a DHCP server and + * ethrotate to 'no'. + */ + .on_request = true, +#endif +}; diff --git a/lib/net_utils.c b/lib/net_utils.c index c70fef0d991..621f6512b62 100644 --- a/lib/net_utils.c +++ b/lib/net_utils.c @@ -152,6 +152,17 @@ out_err: } #endif +void ip_to_string(struct in_addr x, char *s) +{ + x.s_addr = ntohl(x.s_addr); + sprintf(s, "%d.%d.%d.%d", + (int) ((x.s_addr >> 24) & 0xff), + (int) ((x.s_addr >> 16) & 0xff), + (int) ((x.s_addr >> 8) & 0xff), + (int) ((x.s_addr >> 0) & 0xff) + ); +} + void string_to_enetaddr(const char *addr, uint8_t *enetaddr) { char *end; diff --git a/lib/smbios.c b/lib/smbios.c index 7c24ea129eb..a36d4b4e54a 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -270,7 +270,7 @@ static int smbios_add_prop_si(struct smbios_ctx *ctx, const char *prop, static int smbios_add_prop(struct smbios_ctx *ctx, const char *prop, const char *dval) { - return smbios_add_prop_si(ctx, prop, SYSINFO_ID_NONE, dval); + return smbios_add_prop_si(ctx, prop, SYSID_NONE, dval); } static void smbios_set_eos(struct smbios_ctx *ctx, char *eos) @@ -393,27 +393,27 @@ static int smbios_write_type1(ulong *current, int handle, fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle); smbios_set_eos(ctx, t->eos); t->manufacturer = smbios_add_prop_si(ctx, "manufacturer", - SYSINFO_ID_SMBIOS_SYSTEM_MANUFACTURER, + SYSID_SM_SYSTEM_MANUFACTURER, NULL); t->product_name = smbios_add_prop_si(ctx, "product", - SYSINFO_ID_SMBIOS_SYSTEM_PRODUCT, + SYSID_SM_SYSTEM_PRODUCT, NULL); t->version = smbios_add_prop_si(ctx, "version", - SYSINFO_ID_SMBIOS_SYSTEM_VERSION, + SYSID_SM_SYSTEM_VERSION, NULL); if (serial_str) { t->serial_number = smbios_add_prop(ctx, NULL, serial_str); strncpy((char *)t->uuid, serial_str, sizeof(t->uuid)); } else { t->serial_number = smbios_add_prop_si(ctx, "serial", - SYSINFO_ID_SMBIOS_SYSTEM_SERIAL, + SYSID_SM_SYSTEM_SERIAL, NULL); } t->wakeup_type = SMBIOS_WAKEUP_TYPE_UNKNOWN; t->sku_number = smbios_add_prop_si(ctx, "sku", - SYSINFO_ID_SMBIOS_SYSTEM_SKU, NULL); + SYSID_SM_SYSTEM_SKU, NULL); t->family = smbios_add_prop_si(ctx, "family", - SYSINFO_ID_SMBIOS_SYSTEM_FAMILY, NULL); + SYSID_SM_SYSTEM_FAMILY, NULL); len = t->length + smbios_string_table_len(ctx); *current += len; @@ -433,20 +433,20 @@ static int smbios_write_type2(ulong *current, int handle, fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle); smbios_set_eos(ctx, t->eos); t->manufacturer = smbios_add_prop_si(ctx, "manufacturer", - SYSINFO_ID_SMBIOS_BASEBOARD_MANUFACTURER, + SYSID_SM_BASEBOARD_MANUFACTURER, NULL); t->product_name = smbios_add_prop_si(ctx, "product", - SYSINFO_ID_SMBIOS_BASEBOARD_PRODUCT, + SYSID_SM_BASEBOARD_PRODUCT, NULL); t->version = smbios_add_prop_si(ctx, "version", - SYSINFO_ID_SMBIOS_BASEBOARD_VERSION, + SYSID_SM_BASEBOARD_VERSION, NULL); t->serial_number = smbios_add_prop_si(ctx, "serial", - SYSINFO_ID_SMBIOS_BASEBOARD_SERIAL, + SYSID_SM_BASEBOARD_SERIAL, NULL); t->asset_tag_number = smbios_add_prop_si(ctx, "asset-tag", - SYSINFO_ID_SMBIOS_BASEBOARD_ASSET_TAG, + SYSID_SM_BASEBOARD_ASSET_TAG, NULL); t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING; t->board_type = SMBIOS_BOARD_MOTHERBOARD; diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c index cc1dfe61cf7..0503c17341f 100644 --- a/lib/tiny-printf.c +++ b/lib/tiny-printf.c @@ -312,7 +312,7 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va) *info->bf = 0; info->bf = p; - while (*info->bf++ && width > 0) + while (width > 0 && info->bf && *info->bf++) width--; while (width-- > 0) info->putc(info, lz ? '0' : ' '); diff --git a/lib/uuid.c b/lib/uuid.c index 538a1ba6aa8..97388f597a6 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -175,6 +175,20 @@ static const struct { "Firmware Management", EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GUID }, +#if IS_ENABLED(CONFIG_EFI_HTTP_PROTOCOL) + { + "HTTP", + EFI_HTTP_PROTOCOL_GUID, + }, + { + "HTTP Service Binding", + EFI_HTTP_SERVICE_BINDING_PROTOCOL_GUID, + }, + { + "IPv4 Config2", + EFI_IP4_CONFIG2_PROTOCOL_GUID, + }, +#endif /* Configuration table GUIDs */ { "ACPI table", diff --git a/net/Kconfig b/net/Kconfig index 76ab7d91eeb..b4bb68dd613 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -244,6 +244,15 @@ config NET_RANDOM_ETHADDR generated. It will be saved to the appropriate environment variable, too. +config WGET + bool "Enable wget" + select PROT_TCP if NET + select PROT_TCP_LWIP if NET_LWIP + select PROT_DNS_LWIP if NET_LWIP + help + Selecting this will enable wget, an interface to send HTTP requests + via the network stack. + config TFTP_BLOCKSIZE int "TFTP block size" default 1468 diff --git a/net/Makefile b/net/Makefile index 209377aeb26..7c917b318c0 100644 --- a/net/Makefile +++ b/net/Makefile @@ -29,7 +29,7 @@ obj-$(CONFIG_$(PHASE_)TCP_FUNCTION_FASTBOOT) += fastboot_tcp.o obj-$(CONFIG_CMD_WOL) += wol.o obj-$(CONFIG_PROT_UDP) += udp.o obj-$(CONFIG_PROT_TCP) += tcp.o -obj-$(CONFIG_CMD_WGET) += wget.o +obj-$(CONFIG_WGET) += wget.o # Disable this warning as it is triggered by: # sprintf(buf, index ? "foo%d" : "foo", index) diff --git a/net/lwip/Kconfig b/net/lwip/Kconfig index a9ae9bf7fa2..40345ced9c9 100644 --- a/net/lwip/Kconfig +++ b/net/lwip/Kconfig @@ -6,9 +6,16 @@ if NET_LWIP config LWIP_DEBUG bool "Enable debug traces in the lwIP library" + help + Prints messages to the console regarding network packets that go in + and out of the lwIP library. config LWIP_ASSERT bool "Enable assertions in the lwIP library" + help + Compiles additional error checking code into the lwIP library. These + checks are related to conditions that should not happen in typical + use, but may be helpful to debug new features. config PROT_DHCP_LWIP bool diff --git a/net/lwip/Makefile b/net/lwip/Makefile index f2558f8763a..79dd6b3fb50 100644 --- a/net/lwip/Makefile +++ b/net/lwip/Makefile @@ -5,4 +5,4 @@ obj-$(CONFIG_CMD_DHCP) += dhcp.o obj-$(CONFIG_CMD_DNS) += dns.o obj-$(CONFIG_CMD_PING) += ping.o obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o -obj-$(CONFIG_CMD_WGET) += wget.o +obj-$(CONFIG_WGET) += wget.o diff --git a/net/lwip/dhcp.c b/net/lwip/dhcp.c index 23b56226921..9b882cf5b87 100644 --- a/net/lwip/dhcp.c +++ b/net/lwip/dhcp.c @@ -27,9 +27,9 @@ static void call_lwip_dhcp_fine_tmr(void *ctx) static int dhcp_loop(struct udevice *udev) { - char *ipstr = "ipaddr\0\0"; - char *maskstr = "netmask\0\0"; - char *gwstr = "gatewayip\0\0"; + char ipstr[] = "ipaddr\0\0"; + char maskstr[] = "netmask\0\0"; + char gwstr[] = "gatewayip\0\0"; unsigned long start; struct netif *netif; struct dhcp *dhcp; @@ -111,9 +111,21 @@ static int dhcp_loop(struct udevice *udev) int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + int ret; + eth_set_current(); - return dhcp_loop(eth_get_dev()); + ret = dhcp_loop(eth_get_dev()); + if (ret) + return ret; + + if (argc > 1) { + struct cmd_tbl cmdtp = {}; + + return do_tftpb(&cmdtp, 0, argc, argv); + } + + return CMD_RET_SUCCESS; } int dhcp_run(ulong addr, const char *fname, bool autoload) diff --git a/net/lwip/net-lwip.c b/net/lwip/net-lwip.c index 470217781a4..b863047f598 100644 --- a/net/lwip/net-lwip.c +++ b/net/lwip/net-lwip.c @@ -91,9 +91,9 @@ struct netif *net_lwip_get_netif(void) static int get_udev_ipv4_info(struct udevice *dev, ip4_addr_t *ip, ip4_addr_t *mask, ip4_addr_t *gw) { - char *ipstr = "ipaddr\0\0"; - char *maskstr = "netmask\0\0"; - char *gwstr = "gatewayip\0\0"; + char ipstr[] = "ipaddr\0\0"; + char maskstr[] = "netmask\0\0"; + char gwstr[] = "gatewayip\0\0"; int idx = dev_seq(dev); char *env; diff --git a/net/lwip/wget.c b/net/lwip/wget.c index 26086edd192..c23f0640ec6 100644 --- a/net/lwip/wget.c +++ b/net/lwip/wget.c @@ -15,7 +15,7 @@ #include <time.h> #include <dm/uclass.h> -#define SERVER_NAME_SIZE 200 +#define SERVER_NAME_SIZE 254 #define HTTP_PORT_DEFAULT 80 #define HTTPS_PORT_DEFAULT 443 #define PROGRESS_PRINT_STEP_BYTES (100 * 1024) @@ -27,6 +27,8 @@ enum done_state { }; struct wget_ctx { + char server_name[SERVER_NAME_SIZE]; + u16 port; char *path; ulong daddr; ulong saved_daddr; @@ -36,13 +38,29 @@ struct wget_ctx { enum done_state done; }; +static void wget_lwip_fill_info(struct pbuf *hdr, u16_t hdr_len, u32_t hdr_cont_len) +{ + if (wget_info->headers) { + if (hdr_len < MAX_HTTP_HEADERS_SIZE) + pbuf_copy_partial(hdr, (void *)wget_info->headers, hdr_len, 0); + else + hdr_len = 0; + wget_info->headers[hdr_len] = 0; + } + wget_info->hdr_cont_len = (u32)hdr_cont_len; +} + +static void wget_lwip_set_file_size(u32_t rx_content_len) +{ + wget_info->file_size = (ulong)rx_content_len; +} + bool wget_validate_uri(char *uri); int mbedtls_hardware_poll(void *data, unsigned char *output, size_t len, size_t *olen) { struct udevice *dev; - u64 rng = 0; int ret; *olen = 0; @@ -52,12 +70,11 @@ int mbedtls_hardware_poll(void *data, unsigned char *output, size_t len, log_err("Failed to get an rng: %d\n", ret); return ret; } - ret = dm_rng_read(dev, &rng, sizeof(rng)); + ret = dm_rng_read(dev, output, len); if (ret) return ret; - memcpy(output, &rng, len); - *olen = sizeof(rng); + *olen = len; return 0; } @@ -217,6 +234,13 @@ static void httpc_result_cb(void *arg, httpc_result_t httpc_result, struct wget_ctx *ctx = arg; ulong elapsed; + wget_info->status_code = (u32)srv_res; + + if (err == ERR_BUF) { + ctx->done = FAILURE; + return; + } + if (httpc_result != HTTPC_RESULT_OK) { log_err("\nHTTP client error %d\n", httpc_result); ctx->done = FAILURE; @@ -236,8 +260,10 @@ static void httpc_result_cb(void *arg, httpc_result_t httpc_result, printf("%u bytes transferred in %lu ms (", rx_content_len, elapsed); print_size(rx_content_len / elapsed * 1000, "/s)\n"); printf("Bytes transferred = %lu (%lx hex)\n", ctx->size, ctx->size); - efi_set_bootdev("Net", "", ctx->path, map_sysmem(ctx->saved_daddr, 0), - rx_content_len); + if (wget_info->set_bootdev) + efi_set_bootdev("Http", ctx->server_name, ctx->path, map_sysmem(ctx->saved_daddr, 0), + rx_content_len); + wget_lwip_set_file_size(rx_content_len); if (env_set_hex("filesize", rx_content_len) || env_set_hex("fileaddr", ctx->saved_daddr)) { log_err("Could not set filesize or fileaddr\n"); @@ -248,9 +274,19 @@ static void httpc_result_cb(void *arg, httpc_result_t httpc_result, ctx->done = SUCCESS; } +static err_t httpc_headers_done_cb(httpc_state_t *connection, void *arg, struct pbuf *hdr, + u16_t hdr_len, u32_t content_len) +{ + wget_lwip_fill_info(hdr, hdr_len, content_len); + + if (wget_info->check_buffer_size && (ulong)content_len > wget_info->buffer_size) + return ERR_BUF; + + return ERR_OK; +} + static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri) { - char server_name[SERVER_NAME_SIZE]; #if defined CONFIG_WGET_HTTPS altcp_allocator_t tls_allocator; #endif @@ -259,7 +295,6 @@ static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri) struct netif *netif; struct wget_ctx ctx; char *path; - u16 port; bool is_https; ctx.daddr = dst_addr; @@ -269,7 +304,7 @@ static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri) ctx.prevsize = 0; ctx.start_time = 0; - if (parse_url(uri, server_name, &port, &path, &is_https)) + if (parse_url(uri, ctx.server_name, &ctx.port, &path, &is_https)) return CMD_RET_USAGE; netif = net_lwip_new_netif(udev); @@ -281,7 +316,7 @@ static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri) if (is_https) { tls_allocator.alloc = &altcp_tls_alloc; tls_allocator.arg = - altcp_tls_create_config_client(NULL, 0, server_name); + altcp_tls_create_config_client(NULL, 0, ctx.server_name); if (!tls_allocator.arg) { log_err("error: Cannot create a TLS connection\n"); @@ -294,8 +329,9 @@ static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri) #endif conn.result_fn = httpc_result_cb; + conn.headers_done_fn = httpc_headers_done_cb; ctx.path = path; - if (httpc_get_file_dns(server_name, port, path, &conn, httpc_recv_cb, + if (httpc_get_file_dns(ctx.server_name, ctx.port, path, &conn, httpc_recv_cb, &ctx, &state)) { net_lwip_remove_netif(netif); return CMD_RET_FAILURE; @@ -316,10 +352,13 @@ static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri) return -1; } -int wget_with_dns(ulong dst_addr, char *uri) +int wget_do_request(ulong dst_addr, char *uri) { eth_set_current(); + if (!wget_info) + wget_info = &default_wget_info; + return wget_loop(eth_get_dev(), dst_addr, uri); } @@ -346,7 +385,8 @@ int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) if (parse_legacy_arg(url, nurl, sizeof(nurl))) return CMD_RET_FAILURE; - if (wget_with_dns(dst_addr, nurl)) + wget_info = &default_wget_info; + if (wget_do_request(dst_addr, nurl)) return CMD_RET_FAILURE; return CMD_RET_SUCCESS; diff --git a/net/net-common.c b/net/net-common.c index a7f767d5e9c..e01b0da7d7b 100644 --- a/net/net-common.c +++ b/net/net-common.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include <net-common.h> void copy_filename(char *dst, const char *src, int size) { @@ -11,3 +12,16 @@ void copy_filename(char *dst, const char *src, int size) *dst++ = *src++; *dst = '\0'; } + +struct wget_http_info default_wget_info = { + .method = WGET_HTTP_METHOD_GET, + .set_bootdev = true, +}; + +struct wget_http_info *wget_info; + +int wget_request(ulong dst_addr, char *uri, struct wget_http_info *info) +{ + wget_info = info ? info : &default_wget_info; + return wget_do_request(dst_addr, uri); +} diff --git a/net/net.c b/net/net.c index f47e9fbe33a..ca35704f661 100644 --- a/net/net.c +++ b/net/net.c @@ -1723,17 +1723,6 @@ int net_parse_bootfile(struct in_addr *ipaddr, char *filename, int max_len) return 1; } -void ip_to_string(struct in_addr x, char *s) -{ - x.s_addr = ntohl(x.s_addr); - sprintf(s, "%d.%d.%d.%d", - (int) ((x.s_addr >> 24) & 0xff), - (int) ((x.s_addr >> 16) & 0xff), - (int) ((x.s_addr >> 8) & 0xff), - (int) ((x.s_addr >> 0) & 0xff) - ); -} - void vlan_to_string(ushort x, char *s) { x = ntohs(x); diff --git a/net/wget.c b/net/wget.c index 361817ace65..d338eaf4ef3 100644 --- a/net/wget.c +++ b/net/wget.c @@ -22,10 +22,11 @@ DECLARE_GLOBAL_DATA_PTR; /* The default, change with environment variable 'httpdstp' */ #define SERVER_PORT 80 -static const char bootfile1[] = "GET "; +static const char bootfileGET[] = "GET "; +static const char bootfileHEAD[] = "HEAD "; static const char bootfile3[] = " HTTP/1.0\r\n\r\n"; static const char http_eom[] = "\r\n\r\n"; -static const char http_ok[] = "200"; +static const char content_len[] = "Content-Length"; static const char linefeed[] = "\r\n"; static struct in_addr web_server_ip; static int our_port; @@ -45,6 +46,7 @@ struct pkt_qd { #define PKTQ_SZ (PKTBUFSRX / 4) static struct pkt_qd pkt_q[PKTQ_SZ]; static int pkt_q_idx; +static unsigned long content_length; static unsigned int packets; static unsigned int initial_data_seq_num; @@ -75,7 +77,7 @@ static inline int store_block(uchar *src, unsigned int offset, unsigned int len) ulong newsize = offset + len; uchar *ptr; - if (CONFIG_IS_ENABLED(LMB)) { + if (CONFIG_IS_ENABLED(LMB) && wget_info->set_bootdev) { if (store_addr < image_load_addr || lmb_read_check(store_addr, len)) { printf("\nwget error: "); @@ -130,8 +132,17 @@ static void wget_send_stored(void) IP_TCP_HDR_SIZE + TCP_TSOPT_SIZE + 2; offset = ptr; - memcpy(offset, &bootfile1, strlen(bootfile1)); - offset += strlen(bootfile1); + switch (wget_info->method) { + case WGET_HTTP_METHOD_HEAD: + memcpy(offset, &bootfileHEAD, strlen(bootfileHEAD)); + offset += strlen(bootfileHEAD); + break; + case WGET_HTTP_METHOD_GET: + default: + memcpy(offset, &bootfileGET, strlen(bootfileGET)); + offset += strlen(bootfileGET); + break; + } memcpy(offset, image_url, strlen(image_url)); offset += strlen(image_url); @@ -191,6 +202,52 @@ static void wget_timeout_handler(void) #define PKT_QUEUE_OFFSET 0x20000 #define PKT_QUEUE_PACKET_SIZE 0x800 +static void wget_fill_info(const uchar *pkt, int hlen) +{ + const char *first_space; + const char *second_space; + char *pos, *end; + + if (wget_info->headers) { + if (hlen < MAX_HTTP_HEADERS_SIZE) + strncpy(wget_info->headers, pkt, hlen); + else + hlen = 0; + wget_info->headers[hlen] = 0; + } + + //Get status code + first_space = strchr(pkt, ' '); + if (!first_space) { + wget_info->status_code = -1; + return; + } + + second_space = strchr(first_space + 1, ' '); + if (!second_space) { + wget_info->status_code = -1; + return; + } + + wget_info->status_code = (u32)simple_strtoul(first_space + 1, &end, 10); + + if (second_space != end) + wget_info->status_code = -1; + + pos = strstr((char *)pkt, content_len); + + if (pos) { + pos += sizeof(content_len) + 1; + while (*pos == ' ') + pos++; + content_length = simple_strtoul(pos, &end, 10); + debug_cond(DEBUG_WGET, + "wget: Connected Len %lu\n", + content_length); + wget_info->hdr_cont_len = content_length; + } +} + static void wget_connected(uchar *pkt, unsigned int tcp_seq_num, u8 action, unsigned int tcp_ack_num, unsigned int len) { @@ -239,7 +296,11 @@ static void wget_connected(uchar *pkt, unsigned int tcp_seq_num, initial_data_seq_num = tcp_seq_num + hlen; next_data_seq_num = tcp_seq_num + len; - if (strstr((char *)pkt, http_ok) == 0) { + wget_fill_info(pkt, hlen); + debug_cond(DEBUG_WGET, + "wget: HTTP Status Code %d\n", wget_info->status_code); + + if (wget_info->status_code != 200) { debug_cond(DEBUG_WGET, "wget: Connected Bad Xfer\n"); wget_loop_state = NETLOOP_FAIL; @@ -384,10 +445,13 @@ static void wget_handler(uchar *pkt, u16 dport, case WGET_TRANSFERRED: printf("Packets received %d, Transfer Successful\n", packets); net_set_state(wget_loop_state); - efi_set_bootdev("Net", "", image_url, - map_sysmem(image_load_addr, 0), - net_boot_file_size); - env_set_hex("filesize", net_boot_file_size); + wget_info->file_size = net_boot_file_size; + if (wget_info->method == WGET_HTTP_METHOD_GET && wget_info->set_bootdev) { + efi_set_bootdev("Http", NULL, image_url, + map_sysmem(image_load_addr, 0), + net_boot_file_size); + env_set_hex("filesize", net_boot_file_size); + } break; } } @@ -412,6 +476,9 @@ static unsigned int random_port(void) void wget_start(void) { + if (!wget_info) + wget_info = &default_wget_info; + image_url = strchr(net_boot_file_name, ':'); if (image_url > 0) { web_server_ip = string_to_ip(net_boot_file_name); @@ -468,8 +535,7 @@ void wget_start(void) wget_send(TCP_SYN, 0, 0, 0); } -#if (IS_ENABLED(CONFIG_CMD_DNS)) -int wget_with_dns(ulong dst_addr, char *uri) +int wget_do_request(ulong dst_addr, char *uri) { int ret; char *s, *host_name, *file_name, *str_copy; @@ -488,24 +554,32 @@ int wget_with_dns(ulong dst_addr, char *uri) s = str_copy + strlen("http://"); host_name = strsep(&s, "/"); if (!s) { - log_err("Error: invalied uri, no file path\n"); ret = -EINVAL; goto out; } file_name = s; - /* TODO: If the given uri has ip address for the http server, skip dns */ - net_dns_resolve = host_name; - net_dns_env_var = "httpserverip"; - if (net_loop(DNS) < 0) { - log_err("Error: dns lookup of %s failed, check setup\n", net_dns_resolve); - ret = -EINVAL; - goto out; - } - s = env_get("httpserverip"); - if (!s) { + host_name = strsep(&host_name, ":"); + + if (string_to_ip(host_name).s_addr) { + s = host_name; + } else { +#if IS_ENABLED(CONFIG_CMD_DNS) + net_dns_resolve = host_name; + net_dns_env_var = "httpserverip"; + if (net_loop(DNS) < 0) { + ret = -EINVAL; + goto out; + } + s = env_get("httpserverip"); + if (!s) { + ret = -EINVAL; + goto out; + } +#else ret = -EINVAL; goto out; +#endif } strlcpy(net_boot_file_name, s, sizeof(net_boot_file_name)); @@ -517,9 +591,8 @@ int wget_with_dns(ulong dst_addr, char *uri) out: free(str_copy); - return ret; + return ret < 0 ? ret : 0; } -#endif /** * wget_validate_uri() - validate the uri for wget diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index 9397328609d..e33b08aa8cd 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -1197,10 +1197,10 @@ static int bootflow_cros(struct unit_test_state *uts) return 0; } -BOOTSTD_TEST(bootflow_cros, UTF_CONSOLE); +BOOTSTD_TEST(bootflow_cros, UTF_CONSOLE | UTF_DM | UTF_SCAN_FDT); -/* Test Android bootmeth */ -static int bootflow_android(struct unit_test_state *uts) +/* Test Android bootmeth with boot image version 4 */ +static int bootflow_android_image_v4(struct unit_test_state *uts) { if (!IS_ENABLED(CONFIG_BOOTMETH_ANDROID)) return -EAGAIN; @@ -1220,7 +1220,30 @@ static int bootflow_android(struct unit_test_state *uts) return 0; } -BOOTSTD_TEST(bootflow_android, UTF_CONSOLE); +BOOTSTD_TEST(bootflow_android_image_v4, UTF_CONSOLE | UTF_DM | UTF_SCAN_FDT); + +/* Test Android bootmeth with boot image version 2 */ +static int bootflow_android_image_v2(struct unit_test_state *uts) +{ + if (!IS_ENABLED(CONFIG_BOOTMETH_ANDROID)) + return -EAGAIN; + + ut_assertok(scan_mmc_android_bootdev(uts, "mmc8")); + ut_assertok(run_command("bootflow list", 0)); + + ut_assert_nextlinen("Showing all"); + ut_assert_nextlinen("Seq"); + ut_assert_nextlinen("---"); + ut_assert_nextlinen(" 0 extlinux"); + ut_assert_nextlinen(" 1 android ready mmc 0 mmc8.bootdev.whole "); + ut_assert_nextlinen("---"); + ut_assert_skip_to_line("(2 bootflows, 2 valid)"); + + ut_assert_console_end(); + + return 0; +} +BOOTSTD_TEST(bootflow_android_image_v2, UTF_CONSOLE | UTF_DM | UTF_SCAN_FDT); /* Test EFI bootmeth */ static int bootflow_efi(struct unit_test_state *uts) diff --git a/test/boot/bootm.c b/test/boot/bootm.c index 52b83f149cb..9455f44884c 100644 --- a/test/boot/bootm.c +++ b/test/boot/bootm.c @@ -28,6 +28,7 @@ static int bootm_test_nop(struct unit_test_state *uts) /* This tests relies on GD_FLG_SILENT not being set */ gd->flags &= ~GD_FLG_SILENT; + env_set("silent_linux", NULL); *buf = '\0'; ut_assertok(bootm_process_cmdline(buf, BUF_SIZE, BOOTM_CL_ALL)); @@ -183,6 +184,7 @@ static int bootm_test_subst(struct unit_test_state *uts) ut_asserteq(0, bootm_process_cmdline(buf, 22, BOOTM_CL_SUBST)); /* Check multiple substitutions */ + ut_assertok(env_set("bvar", NULL)); ut_assertok(env_set("var", "abc")); strcpy(buf, "some${var}thing${bvar}else"); ut_asserteq(0, bootm_process_cmdline(buf, BUF_SIZE, BOOTM_CL_SUBST)); @@ -201,6 +203,7 @@ BOOTM_TEST(bootm_test_subst, 0); /* Test silent processing in the bootargs variable */ static int bootm_test_silent_var(struct unit_test_state *uts) { + ut_assertok(env_set("var", NULL)); env_set("bootargs", NULL); ut_assertok(bootm_process_cmdline_env(BOOTM_CL_SUBST)); ut_assertnull(env_get("bootargs")); diff --git a/test/cmd/hash.c b/test/cmd/hash.c index 2fcec9cadcd..296dd762b31 100644 --- a/test/cmd/hash.c +++ b/test/cmd/hash.c @@ -33,11 +33,13 @@ static int dm_test_cmd_hash_md5(struct unit_test_state *uts) strstr(uts->actual_str, "md5 for ")); ut_assert(strstr(uts->actual_str, "d41d8cd98f00b204e9800998ecf8427e")); - ut_check_console_line(uts, "d41d8cd98f00b204e9800998ecf8427e"); + ut_assertok(ut_check_console_line(uts, + "d41d8cd98f00b204e9800998ecf8427e")); if (!CONFIG_IS_ENABLED(HASH_VERIFY)) { ut_assert(run_command("hash -v sha256 $loadaddr 0 foo", 0)); - ut_check_console_line(uts, "hash - compute hash message digest"); + ut_assertok(ut_check_console_line( + uts, "hash - compute hash message digest")); return 0; } @@ -77,12 +79,13 @@ static int dm_test_cmd_hash_sha256(struct unit_test_state *uts) strstr(uts->actual_str, "sha256 for ")); ut_assert(strstr(uts->actual_str, "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855")); - ut_check_console_line(uts, - "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855"); + ut_assertok(ut_check_console_line( + uts, "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855")); if (!CONFIG_IS_ENABLED(HASH_VERIFY)) { ut_assert(run_command("hash -v sha256 $loadaddr 0 foo", 0)); - ut_check_console_line(uts, "hash - compute hash message digest"); + ut_assertok(ut_check_console_line( + uts, "hash - compute hash message digest")); return 0; } diff --git a/test/common/print.c b/test/common/print.c index 464e425edee..e3711b10809 100644 --- a/test/common/print.c +++ b/test/common/print.c @@ -241,7 +241,7 @@ COMMON_TEST(print_display_buffer, UTF_CONSOLE); static int print_hexdump_line(struct unit_test_state *uts) { - char *linebuf; + u8 *linebuf; u8 *buf; int i; @@ -254,10 +254,10 @@ static int print_hexdump_line(struct unit_test_state *uts) linebuf = map_sysmem(0x400, BUF_SIZE); memset(linebuf, '\xff', BUF_SIZE); ut_asserteq(-ENOSPC, hexdump_line(0, buf, 1, 0x10, 0, linebuf, 75)); - ut_asserteq(-1, linebuf[0]); + ut_asserteq(0xff, linebuf[0]); ut_asserteq(0x10, hexdump_line(0, buf, 1, 0x10, 0, linebuf, 76)); - ut_asserteq(0, linebuf[75]); - ut_asserteq(-1, linebuf[76]); + ut_asserteq('\0', linebuf[75]); + ut_asserteq(0xff, linebuf[76]); unmap_sysmem(buf); diff --git a/test/dm/core.c b/test/dm/core.c index 7371d3ff426..c59ffc6f611 100644 --- a/test/dm/core.c +++ b/test/dm/core.c @@ -999,6 +999,56 @@ static int dm_test_remove_vital(struct unit_test_state *uts) } DM_TEST(dm_test_remove_vital, 0); +/* Test removal of 'active' devices */ +static int dm_test_remove_active(struct unit_test_state *uts) +{ + struct udevice *normal, *dma, *vital, *dma_vital; + + /* Skip the behaviour in test_post_probe() */ + uts->skip_post_probe = 1; + + ut_assertok(device_bind_by_name(uts->root, false, &driver_info_manual, + &normal)); + ut_assertnonnull(normal); + + ut_assertok(device_bind_by_name(uts->root, false, &driver_info_act_dma, + &dma)); + ut_assertnonnull(dma); + + ut_assertok(device_bind_by_name(uts->root, false, + &driver_info_vital_clk, &vital)); + ut_assertnonnull(vital); + + ut_assertok(device_bind_by_name(uts->root, false, + &driver_info_act_dma_vital_clk, + &dma_vital)); + ut_assertnonnull(dma_vital); + + /* Probe the devices */ + ut_assertok(device_probe(normal)); + ut_assertok(device_probe(dma)); + ut_assertok(device_probe(vital)); + ut_assertok(device_probe(dma_vital)); + + /* Check that devices are active right now */ + ut_asserteq(true, device_active(normal)); + ut_asserteq(true, device_active(dma)); + ut_asserteq(true, device_active(vital)); + ut_asserteq(true, device_active(dma_vital)); + + /* Remove active devices in an ordered way */ + dm_remove_devices_active(); + + /* Check that all devices are inactive right now */ + ut_asserteq(true, device_active(normal)); + ut_asserteq(false, device_active(dma)); + ut_asserteq(true, device_active(vital)); + ut_asserteq(false, device_active(dma_vital)); + + return 0; +} +DM_TEST(dm_test_remove_active, 0); + static int dm_test_uclass_before_ready(struct unit_test_state *uts) { struct uclass *uc; diff --git a/test/dm/led.c b/test/dm/led.c index 884f6410b70..e5b86326c3a 100644 --- a/test/dm/led.c +++ b/test/dm/led.c @@ -144,7 +144,7 @@ static int dm_test_led_boot(struct unit_test_state *uts) { struct udevice *dev - /* options/u-boot/boot-led is set to "sandbox:green" */ + /* options/u-boot/boot-led is set to phandle to "sandbox:green" */ ut_assertok(led_get_by_label("sandbox:green", &dev)); ut_asserteq(LEDST_OFF, led_get_state(dev)); ut_assertok(led_boot_on()); @@ -154,14 +154,15 @@ static int dm_test_led_boot(struct unit_test_state *uts) return 0; } +DM_TEST(dm_test_led_boot, UTF_SCAN_PDATA | UTF_SCAN_FDT); /* Test LED boot blink fallback */ #ifndef CONFIG_LED_BLINK -static int dm_test_led_boot(struct unit_test_state *uts) +static int dm_test_led_boot_blink(struct unit_test_state *uts) { struct udevice *dev - /* options/u-boot/boot-led is set to "sandbox:green" */ + /* options/u-boot/boot-led is set to phandle to "sandbox:green" */ ut_assertok(led_get_by_label("sandbox:green", &dev)); ut_asserteq(LEDST_OFF, led_get_state(dev)); ut_assertok(led_boot_blink()); @@ -171,16 +172,17 @@ static int dm_test_led_boot(struct unit_test_state *uts) return 0; } +DM_TEST(dm_test_led_boot_blink, UTF_SCAN_PDATA | UTF_SCAN_FDT); #endif #endif /* Test LED activity */ #ifdef CONFIG_LED_ACTIVITY -static int dm_test_led_boot(struct unit_test_state *uts) +static int dm_test_led_activity(struct unit_test_state *uts) { struct udevice *dev - /* options/u-boot/activity-led is set to "sandbox:red" */ + /* options/u-boot/activity-led is set to phandle to "sandbox:red" */ ut_assertok(led_get_by_label("sandbox:red", &dev)); ut_asserteq(LEDST_OFF, led_get_state(dev)); ut_assertok(led_activity_on()); @@ -190,14 +192,15 @@ static int dm_test_led_boot(struct unit_test_state *uts) return 0; } +DM_TEST(dm_test_led_activity, UTF_SCAN_PDATA | UTF_SCAN_FDT); /* Test LED activity blink fallback */ #ifndef CONFIG_LED_BLINK -static int dm_test_led_boot(struct unit_test_state *uts) +static int dm_test_led_activityt_blink(struct unit_test_state *uts) { struct udevice *dev - /* options/u-boot/activity-led is set to "sandbox:red" */ + /* options/u-boot/activity-led is set to phandle to "sandbox:red" */ ut_assertok(led_get_by_label("sandbox:red", &dev)); ut_asserteq(LEDST_OFF, led_get_state(dev)); ut_assertok(led_activity_blink()); @@ -207,5 +210,6 @@ static int dm_test_led_boot(struct unit_test_state *uts) return 0; } +DM_TEST(dm_test_led_activityt_blink, UTF_SCAN_PDATA | UTF_SCAN_FDT); #endif #endif diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c index ce996567c3c..f16b643fa3f 100644 --- a/test/dm/ofnode.c +++ b/test/dm/ofnode.c @@ -141,9 +141,16 @@ static int dm_test_ofnode_get_by_phandle_ot(struct unit_test_state *uts) { oftree otree = get_other_oftree(uts); ofnode node; + u32 idx; + int ret; - ut_assert(ofnode_valid(oftree_get_by_phandle(oftree_default(), 1))); - node = oftree_get_by_phandle(otree, 1); + node = oftree_path(otree, "/node"); + ut_assert(ofnode_valid(node)); + + ret = ofnode_read_u32(node, "other-phandle", &idx); + ut_assertok(ret); + + node = oftree_get_by_phandle(otree, idx); ut_assert(ofnode_valid(node)); ut_asserteq_str("target", ofnode_get_name(node)); @@ -273,15 +280,16 @@ static int dm_test_ofnode_read_ot(struct unit_test_state *uts) } DM_TEST(dm_test_ofnode_read_ot, UTF_SCAN_FDT | UTF_OTHER_FDT); -/* test ofnode_count_/parse_phandle_with_args() */ +/* test ofnode_count_/parse/_phandle_with_args() */ static int dm_test_ofnode_phandle(struct unit_test_state *uts) { struct ofnode_phandle_args args; - ofnode node; + ofnode node, phandle, target; int ret; const char prop[] = "test-gpios"; const char cell[] = "#gpio-cells"; const char prop2[] = "phandle-value"; + const char prop3[] = "phandle-nodes"; node = ofnode_path("/a-test"); ut_assert(ofnode_valid(node)); @@ -345,34 +353,117 @@ static int dm_test_ofnode_phandle(struct unit_test_state *uts) ret = ofnode_parse_phandle_with_args(node, prop2, NULL, 1, 3, &args); ut_asserteq(-ENOENT, ret); + /* Test ofnode_parse_phandle */ + phandle = ofnode_parse_phandle(node, "missing", 0); + ut_assert(ofnode_equal(ofnode_null(), phandle)); + + target = ofnode_path("/phandle-node-1"); + ut_assert(ofnode_valid(target)); + phandle = ofnode_parse_phandle(node, prop3, 0); + ut_assert(ofnode_equal(target, phandle)); + + target = ofnode_path("/phandle-node-2"); + ut_assert(ofnode_valid(target)); + phandle = ofnode_parse_phandle(node, prop3, 1); + ut_assert(ofnode_equal(target, phandle)); + + phandle = ofnode_parse_phandle(node, prop3, 3); + ut_assert(ofnode_equal(ofnode_null(), phandle)); + return 0; } DM_TEST(dm_test_ofnode_phandle, UTF_SCAN_PDATA | UTF_SCAN_FDT); -/* test ofnode_count_/parse_phandle_with_args() with 'other' tree */ +/* test oftree_count_/parse/_phandle_with_args() with 'other' tree */ static int dm_test_ofnode_phandle_ot(struct unit_test_state *uts) { oftree otree = get_other_oftree(uts); struct ofnode_phandle_args args; - ofnode node; + ofnode node, phandle, target; int ret; + const char prop[] = "other-test-gpios"; + const char cell[] = "#gpio-cells"; + const char prop2[] = "other-phandle-value"; + const char prop3[] = "other-phandle-nodes"; - node = oftree_path(otree, "/node"); + node = oftree_path(otree, "/other-a-test"); + ut_assert(ofnode_valid(node)); - /* Test ofnode_count_phandle_with_args with cell name */ - ret = ofnode_count_phandle_with_args(node, "missing", "#gpio-cells", 0); + /* Test oftree_count_phandle_with_args with cell name */ + ret = oftree_count_phandle_with_args(otree, node, "missing", cell, 0); + ut_asserteq(-ENOENT, ret); + ret = oftree_count_phandle_with_args(otree, node, prop, "#invalid", 0); + ut_asserteq(-EINVAL, ret); + ret = oftree_count_phandle_with_args(otree, node, prop, cell, 0); + ut_asserteq(5, ret); + + /* Test oftree_parse_phandle_with_args with cell name */ + ret = oftree_parse_phandle_with_args(otree, node, "missing", cell, 0, 0, + &args); ut_asserteq(-ENOENT, ret); - ret = ofnode_count_phandle_with_args(node, "target", "#invalid", 0); + ret = oftree_parse_phandle_with_args(otree, node, prop, "#invalid", 0, 0, + &args); ut_asserteq(-EINVAL, ret); - ret = ofnode_count_phandle_with_args(node, "target", "#gpio-cells", 0); - ut_asserteq(1, ret); + ret = oftree_parse_phandle_with_args(otree, node, prop, cell, 0, 0, &args); + ut_assertok(ret); + ut_asserteq(1, args.args_count); + ut_asserteq(1, args.args[0]); + ret = oftree_parse_phandle_with_args(otree, node, prop, cell, 0, 1, &args); + ut_assertok(ret); + ut_asserteq(1, args.args_count); + ut_asserteq(4, args.args[0]); + ret = oftree_parse_phandle_with_args(otree, node, prop, cell, 0, 2, &args); + ut_assertok(ret); + ut_asserteq(5, args.args_count); + ut_asserteq(5, args.args[0]); + ut_asserteq(1, args.args[4]); + ret = oftree_parse_phandle_with_args(otree, node, prop, cell, 0, 3, &args); + ut_asserteq(-ENOENT, ret); + ret = oftree_parse_phandle_with_args(otree, node, prop, cell, 0, 4, &args); + ut_assertok(ret); + ut_asserteq(1, args.args_count); + ut_asserteq(12, args.args[0]); + ret = oftree_parse_phandle_with_args(otree, node, prop, cell, 0, 5, &args); + ut_asserteq(-ENOENT, ret); + + /* Test oftree_count_phandle_with_args with cell count */ + ret = oftree_count_phandle_with_args(otree, node, "missing", NULL, 2); + ut_asserteq(-ENOENT, ret); + ret = oftree_count_phandle_with_args(otree, node, prop2, NULL, 1); + ut_asserteq(3, ret); - ret = ofnode_parse_phandle_with_args(node, "target", "#gpio-cells", 0, - 0, &args); + /* Test oftree_parse_phandle_with_args with cell count */ + ret = oftree_parse_phandle_with_args(otree, node, prop2, NULL, 1, 0, &args); ut_assertok(ret); - ut_asserteq(2, args.args_count); - ut_asserteq(3, args.args[0]); - ut_asserteq(4, args.args[1]); + ut_asserteq(1, ofnode_valid(args.node)); + ut_asserteq(1, args.args_count); + ut_asserteq(10, args.args[0]); + ret = oftree_parse_phandle_with_args(otree, node, prop2, NULL, 1, 1, &args); + ut_asserteq(-EINVAL, ret); + ret = oftree_parse_phandle_with_args(otree, node, prop2, NULL, 1, 2, &args); + ut_assertok(ret); + ut_asserteq(1, ofnode_valid(args.node)); + ut_asserteq(1, args.args_count); + ut_asserteq(30, args.args[0]); + ret = oftree_parse_phandle_with_args(otree, node, prop2, NULL, 1, 3, &args); + ut_asserteq(-ENOENT, ret); + + /* Test oftree_parse_phandle */ + phandle = oftree_parse_phandle(otree, node, "missing", 0); + ut_assert(ofnode_equal(ofnode_null(), phandle)); + + target = oftree_path(otree, "/other-phandle-node-1"); + ut_assert(ofnode_valid(target)); + phandle = oftree_parse_phandle(otree, node, prop3, 0); + ut_assert(ofnode_equal(target, phandle)); + + target = oftree_path(otree, "/other-phandle-node-2"); + ut_assert(ofnode_valid(target)); + phandle = oftree_parse_phandle(otree, node, prop3, 1); + ut_assert(ofnode_equal(target, phandle)); + + phandle = oftree_parse_phandle(otree, node, prop3, 3); + ut_assert(ofnode_equal(ofnode_null(), phandle)); return 0; } @@ -613,6 +704,10 @@ static int dm_test_ofnode_options(struct unit_test_state *uts) { u64 bootscr_address, bootscr_offset; u64 bootscr_flash_offset, bootscr_flash_size; + ofnode node, phandle_node, target; + + node = ofnode_path("/options/u-boot"); + ut_assert(ofnode_valid(node)); ut_assert(!ofnode_options_read_bool("missing")); ut_assert(ofnode_options_read_bool("testing-bool")); @@ -623,6 +718,13 @@ static int dm_test_ofnode_options(struct unit_test_state *uts) ut_assertnull(ofnode_options_read_str("missing")); ut_asserteq_str("testing", ofnode_options_read_str("testing-str")); + ut_asserteq(-EINVAL, ofnode_options_get_by_phandle("missing", &phandle_node)); + + target = ofnode_path("/phandle-node-1"); + ut_assert(ofnode_valid(target)); + ut_assertok(ofnode_options_get_by_phandle("testing-phandle", &phandle_node)); + ut_assert(ofnode_equal(target, phandle_node)); + ut_assertok(ofnode_read_bootscript_address(&bootscr_address, &bootscr_offset)); ut_asserteq_64(0, bootscr_address); diff --git a/test/dm/sysinfo-gpio.c b/test/dm/sysinfo-gpio.c index 155da3b6344..de9483c4291 100644 --- a/test/dm/sysinfo-gpio.c +++ b/test/dm/sysinfo-gpio.c @@ -29,9 +29,9 @@ static int dm_test_sysinfo_gpio(struct unit_test_state *uts) sandbox_gpio_set_flags(gpio, 16, GPIOD_EXT_PULL_DOWN); sandbox_gpio_set_flags(gpio, 17, 0); ut_assertok(sysinfo_detect(sysinfo)); - ut_assertok(sysinfo_get_int(sysinfo, SYSINFO_ID_BOARD_MODEL, &val)); + ut_assertok(sysinfo_get_int(sysinfo, SYSID_BOARD_MODEL, &val)); ut_asserteq(19, val); - ut_assertok(sysinfo_get_str(sysinfo, SYSINFO_ID_BOARD_MODEL, sizeof(buf), + ut_assertok(sysinfo_get_str(sysinfo, SYSID_BOARD_MODEL, sizeof(buf), buf)); ut_asserteq_str("rev_a", buf); @@ -43,9 +43,9 @@ static int dm_test_sysinfo_gpio(struct unit_test_state *uts) sandbox_gpio_set_flags(gpio, 16, GPIOD_EXT_PULL_UP); sandbox_gpio_set_flags(gpio, 17, GPIOD_EXT_PULL_DOWN); ut_assertok(sysinfo_detect(sysinfo)); - ut_assertok(sysinfo_get_int(sysinfo, SYSINFO_ID_BOARD_MODEL, &val)); + ut_assertok(sysinfo_get_int(sysinfo, SYSID_BOARD_MODEL, &val)); ut_asserteq(5, val); - ut_assertok(sysinfo_get_str(sysinfo, SYSINFO_ID_BOARD_MODEL, sizeof(buf), + ut_assertok(sysinfo_get_str(sysinfo, SYSID_BOARD_MODEL, sizeof(buf), buf)); ut_asserteq_str("foo", buf); @@ -57,9 +57,9 @@ static int dm_test_sysinfo_gpio(struct unit_test_state *uts) sandbox_gpio_set_flags(gpio, 16, 0); sandbox_gpio_set_flags(gpio, 17, GPIOD_EXT_PULL_UP); ut_assertok(sysinfo_detect(sysinfo)); - ut_assertok(sysinfo_get_int(sysinfo, SYSINFO_ID_BOARD_MODEL, &val)); + ut_assertok(sysinfo_get_int(sysinfo, SYSID_BOARD_MODEL, &val)); ut_asserteq(15, val); - ut_assertok(sysinfo_get_str(sysinfo, SYSINFO_ID_BOARD_MODEL, sizeof(buf), + ut_assertok(sysinfo_get_str(sysinfo, SYSID_BOARD_MODEL, sizeof(buf), buf)); ut_asserteq_str("unknown", buf); diff --git a/test/env/cmd_ut_env.c b/test/env/cmd_ut_env.c index 4af05764fb8..9f16a978f2a 100644 --- a/test/env/cmd_ut_env.c +++ b/test/env/cmd_ut_env.c @@ -14,16 +14,54 @@ static int env_test_env_cmd(struct unit_test_state *uts) ut_assertok(run_command("setenv non_default_var1 1", 0)); ut_assert_console_end(); - ut_assertok(run_command("setenv non_default_var2 1", 0)); + ut_assertok(run_command("setenv non_default_var2 2", 0)); ut_assert_console_end(); ut_assertok(run_command("env print non_default_var1", 0)); ut_assert_nextline("non_default_var1=1"); ut_assert_console_end(); - ut_assertok(run_command("env default non_default_var1 non_default_var2", 0)); + ut_assertok(run_command("env default non_default_var1", 0)); ut_assert_nextline("WARNING: 'non_default_var1' not in imported env, deleting it!"); - ut_assert_nextline("WARNING: 'non_default_var2' not in imported env, deleting it!"); + ut_assert_console_end(); + + ut_asserteq(1, run_command("env exists non_default_var1", 0)); + ut_assert_console_end(); + + ut_asserteq(0, run_command("env exists non_default_var2", 0)); + ut_assert_console_end(); + + ut_assertok(run_command("setenv non_default_var1 3", 0)); + ut_assert_console_end(); + + ut_assertok(run_command("env default -k non_default_var1", 0)); + ut_assert_console_end(); + + ut_asserteq(0, run_command("env exists non_default_var1", 0)); + ut_assert_console_end(); + + ut_asserteq(0, run_command("env exists non_default_var2", 0)); + ut_assert_console_end(); + + ut_assertok(run_command("env default -k -a -f", 0)); + ut_assert_nextline("## Resetting to default environment"); + ut_assert_console_end(); + + ut_asserteq(0, run_command("env exists non_default_var1", 0)); + ut_assert_console_end(); + + ut_asserteq(0, run_command("env exists non_default_var2", 0)); + ut_assert_console_end(); + + /* + * While the following test of "env default -a" by itself + * works, it unfortunately causes an unrelated test case, + * env_test_fdt_import(), to fail, because the "from_fdt" + * variable would be removed. + */ +#if 0 + ut_assertok(run_command("env default -a", 0)); + ut_assert_nextline("## Resetting to default environment"); ut_assert_console_end(); ut_asserteq(1, run_command("env exists non_default_var1", 0)); @@ -31,6 +69,7 @@ static int env_test_env_cmd(struct unit_test_state *uts) ut_asserteq(1, run_command("env exists non_default_var2", 0)); ut_assert_console_end(); +#endif return 0; } diff --git a/test/lib/str.c b/test/lib/str.c index 3cc9dfea6aa..e62045318c0 100644 --- a/test/lib/str.c +++ b/test/lib/str.c @@ -18,6 +18,8 @@ static const char str4[] = "1234567890123 I lost closer friends"; static const char str5[] = "0x9876543210the last time I was deloused"; static const char str6[] = "0778octal is seldom used"; static const char str7[] = "707it is a piece of computing history"; +static const char str8[] = "0x887e2561352d80fa"; +static const char str9[] = "614FF7EAA63009DA"; static int str_upper(struct unit_test_state *uts) { @@ -186,6 +188,22 @@ static int str_hextoul(struct unit_test_state *uts) } LIB_TEST(str_hextoul, 0); +static int str_hextoull(struct unit_test_state *uts) +{ + char *endp; + + /* Just a simple test, since we know this uses simple_strtoull() */ + ut_asserteq_64(0x887e2561352d80faULL, hextoull(str8, &endp)); + ut_asserteq_64(0x12, endp - str8); + ut_asserteq_64(0x614ff7eaa63009daULL, hextoull(str9, &endp)); + ut_asserteq_64(0x10, endp - str9); + ut_asserteq_64(0x887e2561352d80faULL, hextoull(str8, NULL)); + ut_asserteq_64(0x614ff7eaa63009daULL, hextoull(str9, NULL)); + + return 0; +} +LIB_TEST(str_hextoull, 0); + static int str_dectoul(struct unit_test_state *uts) { char *endp; diff --git a/test/lib/time.c b/test/lib/time.c index b99e738c500..2095bef7589 100644 --- a/test/lib/time.c +++ b/test/lib/time.c @@ -22,7 +22,11 @@ static int test_get_timer(struct unit_test_state *uts) next = get_timer(0); } while (start == next); - ut_asserteq(start + 1, next); + if (start + 1 != next) { + printf("%s: iter=%d, start=%lu, next=%lu, expected a difference of 1\n", + __func__, iter, start, next); + return -EINVAL; + } start++; } @@ -31,7 +35,11 @@ static int test_get_timer(struct unit_test_state *uts) * an extra millisecond may have passed. */ diff = get_timer(base); - ut_assert(diff == iter || diff == iter + 1); + if (diff != iter && diff != iter + 1) { + printf("%s: expected get_timer(base) to match elapsed time: diff=%lu, expected=%d\n", + __func__, diff, iter); + return -EINVAL; + } return 0; } @@ -49,8 +57,11 @@ static int test_timer_get_us(struct unit_test_state *uts) next = timer_get_us(); if (next != prev) { delta = next - prev; - ut_assert(delta >= 0); - if (delta) { + if (delta < 0) { + printf("%s: timer_get_us() went backwards from %lu to %lu\n", + __func__, prev, next); + return -EINVAL; + } else if (delta != 0) { if (delta < min) min = delta; prev = next; @@ -59,7 +70,11 @@ static int test_timer_get_us(struct unit_test_state *uts) } } - ut_asserteq(1, min); + if (min != 1) { + printf("%s: Minimum microsecond delta should be 1 but is %lu\n", + __func__, min); + return -EINVAL; + } return 0; } @@ -80,7 +95,8 @@ static int test_time_comparison(struct unit_test_state *uts) error = delta_us - 1000000; printf("%s: Microsecond time for 1 second: %lu, error = %ld\n", __func__, delta_us, error); - ut_assert(abs(error) <= 1000); + if (abs(error) > 1000) + return -EINVAL; return 0; } @@ -99,7 +115,8 @@ static int test_udelay(struct unit_test_state *uts) error = delta - 1000; printf("%s: Delay time for 1000 udelay(1000): %lu ms, error = %ld\n", __func__, delta, error); - ut_assert(abs(error) <= 100); + if (abs(error) > 100) + return -EINVAL; return 0; } diff --git a/test/py/tests/bootstd/flash1.img.xz b/test/py/tests/bootstd/flash1.img.xz Binary files differdeleted file mode 100644 index 29b78c62a9b..00000000000 --- a/test/py/tests/bootstd/flash1.img.xz +++ /dev/null diff --git a/test/py/tests/bootstd/mmc1.img.xz b/test/py/tests/bootstd/mmc1.img.xz Binary files differdeleted file mode 100644 index cebf7b9c53b..00000000000 --- a/test/py/tests/bootstd/mmc1.img.xz +++ /dev/null diff --git a/test/py/tests/bootstd/mmc4.img.xz b/test/py/tests/bootstd/mmc4.img.xz Binary files differdeleted file mode 100644 index f4db011969f..00000000000 --- a/test/py/tests/bootstd/mmc4.img.xz +++ /dev/null diff --git a/test/py/tests/fs_helper.py b/test/py/tests/fs_helper.py index 380f4c4dca3..ccfc0201a49 100644 --- a/test/py/tests/fs_helper.py +++ b/test/py/tests/fs_helper.py @@ -9,7 +9,7 @@ import re import os from subprocess import call, check_call, check_output, CalledProcessError -def mk_fs(config, fs_type, size, prefix, size_gran = 0x100000): +def mk_fs(config, fs_type, size, prefix, src_dir=None, size_gran = 0x100000): """Create a file system volume Args: @@ -17,6 +17,7 @@ def mk_fs(config, fs_type, size, prefix, size_gran = 0x100000): fs_type (str): File system type, e.g. 'ext4' size (int): Size of file system in bytes prefix (str): Prefix string of volume's file name + src_dir (str): Root directory to use, or None for none size_gran (int): Size granularity of file system image in bytes Raises: @@ -39,6 +40,12 @@ def mk_fs(config, fs_type, size, prefix, size_gran = 0x100000): else: fs_lnxtype = fs_type + if src_dir: + if fs_lnxtype == 'ext4': + mkfs_opt = mkfs_opt + ' -d ' + src_dir + elif fs_lnxtype != 'vfat': + raise ValueError(f'src_dir not implemented for fs {fs_lnxtype}') + count = (size + size_gran - 1) // size_gran # Some distributions do not add /sbin to the default PATH, where mkfs lives @@ -55,6 +62,8 @@ def mk_fs(config, fs_type, size, prefix, size_gran = 0x100000): shell=True).decode() if 'metadata_csum' in sb_content: check_call(f'tune2fs -O ^metadata_csum {fs_img}', shell=True) + elif fs_lnxtype == 'vfat' and src_dir: + check_call(f'mcopy -i {fs_img} -vsmpQ {src_dir}/* ::/', shell=True) return fs_img except CalledProcessError: call(f'rm -f {fs_img}', shell=True) diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py index fca54488374..af2adaf1645 100644 --- a/test/py/tests/test_fs/conftest.py +++ b/test/py/tests/test_fs/conftest.py @@ -156,64 +156,6 @@ def tool_is_in_path(tool): return True return False -fuse_mounted = False - -def mount_fs(fs_type, device, mount_point): - """Mount a volume. - - Args: - fs_type: File system type. - device: Volume's file name. - mount_point: Mount point. - - Return: - Nothing. - """ - global fuse_mounted - - try: - check_call('guestmount --pid-file guestmount.pid -a %s -m /dev/sda %s' - % (device, mount_point), shell=True) - fuse_mounted = True - return - except CalledProcessError: - fuse_mounted = False - - mount_opt = 'loop,rw' - if re.match('fat', fs_type): - mount_opt += ',umask=0000' - - check_call('sudo mount -o %s %s %s' - % (mount_opt, device, mount_point), shell=True) - - # may not be effective for some file systems - check_call('sudo chmod a+rw %s' % mount_point, shell=True) - -def umount_fs(mount_point): - """Unmount a volume. - - Args: - mount_point: Mount point. - - Return: - Nothing. - """ - if fuse_mounted: - call('sync') - call('guestunmount %s' % mount_point, shell=True) - - try: - with open("guestmount.pid", "r") as pidfile: - pid = int(pidfile.read()) - util.waitpid(pid, kill=True) - os.remove("guestmount.pid") - - except FileNotFoundError: - pass - - else: - call('sudo umount %s' % mount_point, shell=True) - # # Fixture for basic fs test # derived from test/fs/fs-test.sh @@ -236,38 +178,21 @@ def fs_obj_basic(request, u_boot_config): fs_ubtype = fstype_to_ubname(fs_type) check_ubconfig(u_boot_config, fs_ubtype) - mount_dir = u_boot_config.persistent_data_dir + '/mnt' - - small_file = mount_dir + '/' + SMALL_FILE - big_file = mount_dir + '/' + BIG_FILE + scratch_dir = u_boot_config.persistent_data_dir + '/scratch' - try: - - # 3GiB volume - fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0xc0000000, '3GB') - except CalledProcessError as err: - pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err)) - return + small_file = scratch_dir + '/' + SMALL_FILE + big_file = scratch_dir + '/' + BIG_FILE try: - check_call('mkdir -p %s' % mount_dir, shell=True) + check_call('mkdir -p %s' % scratch_dir, shell=True) except CalledProcessError as err: pytest.skip('Preparing mount folder failed for filesystem: ' + fs_type + '. {}'.format(err)) call('rm -f %s' % fs_img, shell=True) return try: - # Mount the image so we can populate it. - mount_fs(fs_type, fs_img, mount_dir) - except CalledProcessError as err: - pytest.skip('Mounting to folder failed for filesystem: ' + fs_type + '. {}'.format(err)) - call('rmdir %s' % mount_dir, shell=True) - call('rm -f %s' % fs_img, shell=True) - return - - try: # Create a subdirectory. - check_call('mkdir %s/SUBDIR' % mount_dir, shell=True) + check_call('mkdir %s/SUBDIR' % scratch_dir, shell=True) # Create big file in this image. # Note that we work only on the start 1MB, couple MBs in the 2GB range @@ -326,15 +251,20 @@ def fs_obj_basic(request, u_boot_config): % big_file, shell=True).decode() md5val.append(out.split()[0]) + try: + # 3GiB volume + fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0xc0000000, '3GB', scratch_dir) + except CalledProcessError as err: + pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err)) + return + except CalledProcessError as err: pytest.skip('Setup failed for filesystem: ' + fs_type + '. {}'.format(err)) - umount_fs(mount_dir) return else: - umount_fs(mount_dir) yield [fs_ubtype, fs_img, md5val] finally: - call('rmdir %s' % mount_dir, shell=True) + call('rm -rf %s' % scratch_dir, shell=True) call('rm -f %s' % fs_img, shell=True) # @@ -358,38 +288,21 @@ def fs_obj_ext(request, u_boot_config): fs_ubtype = fstype_to_ubname(fs_type) check_ubconfig(u_boot_config, fs_ubtype) - mount_dir = u_boot_config.persistent_data_dir + '/mnt' - - min_file = mount_dir + '/' + MIN_FILE - tmp_file = mount_dir + '/tmpfile' + scratch_dir = u_boot_config.persistent_data_dir + '/scratch' - try: - - # 128MiB volume - fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x8000000, '128MB') - except CalledProcessError as err: - pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err)) - return + min_file = scratch_dir + '/' + MIN_FILE + tmp_file = scratch_dir + '/tmpfile' try: - check_call('mkdir -p %s' % mount_dir, shell=True) + check_call('mkdir -p %s' % scratch_dir, shell=True) except CalledProcessError as err: pytest.skip('Preparing mount folder failed for filesystem: ' + fs_type + '. {}'.format(err)) call('rm -f %s' % fs_img, shell=True) return try: - # Mount the image so we can populate it. - mount_fs(fs_type, fs_img, mount_dir) - except CalledProcessError as err: - pytest.skip('Mounting to folder failed for filesystem: ' + fs_type + '. {}'.format(err)) - call('rmdir %s' % mount_dir, shell=True) - call('rm -f %s' % fs_img, shell=True) - return - - try: # Create a test directory - check_call('mkdir %s/dir1' % mount_dir, shell=True) + check_call('mkdir %s/dir1' % scratch_dir, shell=True) # Create a small file and calculate md5 check_call('dd if=/dev/urandom of=%s bs=1K count=20' @@ -427,15 +340,21 @@ def fs_obj_ext(request, u_boot_config): md5val.append(out.split()[0]) check_call('rm %s' % tmp_file, shell=True) + + try: + # 128MiB volume + fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x8000000, '128MB', scratch_dir) + except CalledProcessError as err: + pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err)) + return + except CalledProcessError: pytest.skip('Setup failed for filesystem: ' + fs_type) - umount_fs(mount_dir) return else: - umount_fs(mount_dir) yield [fs_ubtype, fs_img, md5val] finally: - call('rmdir %s' % mount_dir, shell=True) + call('rm -rf %s' % scratch_dir, shell=True) call('rm -f %s' % fs_img, shell=True) # @@ -461,7 +380,7 @@ def fs_obj_mkdir(request, u_boot_config): try: # 128MiB volume - fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x8000000, '128MB') + fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x8000000, '128MB', None) except: pytest.skip('Setup failed for filesystem: ' + fs_type) return @@ -490,63 +409,51 @@ def fs_obj_unlink(request, u_boot_config): fs_ubtype = fstype_to_ubname(fs_type) check_ubconfig(u_boot_config, fs_ubtype) - mount_dir = u_boot_config.persistent_data_dir + '/mnt' - - try: - - # 128MiB volume - fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x8000000, '128MB') - except CalledProcessError as err: - pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err)) - return + scratch_dir = u_boot_config.persistent_data_dir + '/scratch' try: - check_call('mkdir -p %s' % mount_dir, shell=True) + check_call('mkdir -p %s' % scratch_dir, shell=True) except CalledProcessError as err: pytest.skip('Preparing mount folder failed for filesystem: ' + fs_type + '. {}'.format(err)) call('rm -f %s' % fs_img, shell=True) return try: - # Mount the image so we can populate it. - mount_fs(fs_type, fs_img, mount_dir) - except CalledProcessError as err: - pytest.skip('Mounting to folder failed for filesystem: ' + fs_type + '. {}'.format(err)) - call('rmdir %s' % mount_dir, shell=True) - call('rm -f %s' % fs_img, shell=True) - return - - try: # Test Case 1 & 3 - check_call('mkdir %s/dir1' % mount_dir, shell=True) + check_call('mkdir %s/dir1' % scratch_dir, shell=True) check_call('dd if=/dev/urandom of=%s/dir1/file1 bs=1K count=1' - % mount_dir, shell=True) + % scratch_dir, shell=True) check_call('dd if=/dev/urandom of=%s/dir1/file2 bs=1K count=1' - % mount_dir, shell=True) + % scratch_dir, shell=True) # Test Case 2 - check_call('mkdir %s/dir2' % mount_dir, shell=True) + check_call('mkdir %s/dir2' % scratch_dir, shell=True) for i in range(0, 20): check_call('mkdir %s/dir2/0123456789abcdef%02x' - % (mount_dir, i), shell=True) + % (scratch_dir, i), shell=True) # Test Case 4 - check_call('mkdir %s/dir4' % mount_dir, shell=True) + check_call('mkdir %s/dir4' % scratch_dir, shell=True) # Test Case 5, 6 & 7 - check_call('mkdir %s/dir5' % mount_dir, shell=True) + check_call('mkdir %s/dir5' % scratch_dir, shell=True) check_call('dd if=/dev/urandom of=%s/dir5/file1 bs=1K count=1' - % mount_dir, shell=True) + % scratch_dir, shell=True) + + try: + # 128MiB volume + fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x8000000, '128MB', scratch_dir) + except CalledProcessError as err: + pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err)) + return except CalledProcessError: pytest.skip('Setup failed for filesystem: ' + fs_type) - umount_fs(mount_dir) return else: - umount_fs(mount_dir) yield [fs_ubtype, fs_img] finally: - call('rmdir %s' % mount_dir, shell=True) + call('rm -rf %s' % scratch_dir, shell=True) call('rm -f %s' % fs_img, shell=True) # @@ -570,38 +477,21 @@ def fs_obj_symlink(request, u_boot_config): fs_ubtype = fstype_to_ubname(fs_type) check_ubconfig(u_boot_config, fs_ubtype) - mount_dir = u_boot_config.persistent_data_dir + '/mnt' - - small_file = mount_dir + '/' + SMALL_FILE - medium_file = mount_dir + '/' + MEDIUM_FILE - - try: + scratch_dir = u_boot_config.persistent_data_dir + '/scratch' - # 1GiB volume - fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x40000000, '1GB') - except CalledProcessError as err: - pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err)) - return + small_file = scratch_dir + '/' + SMALL_FILE + medium_file = scratch_dir + '/' + MEDIUM_FILE try: - check_call('mkdir -p %s' % mount_dir, shell=True) + check_call('mkdir -p %s' % scratch_dir, shell=True) except CalledProcessError as err: pytest.skip('Preparing mount folder failed for filesystem: ' + fs_type + '. {}'.format(err)) call('rm -f %s' % fs_img, shell=True) return try: - # Mount the image so we can populate it. - mount_fs(fs_type, fs_img, mount_dir) - except CalledProcessError as err: - pytest.skip('Mounting to folder failed for filesystem: ' + fs_type + '. {}'.format(err)) - call('rmdir %s' % mount_dir, shell=True) - call('rm -f %s' % fs_img, shell=True) - return - - try: # Create a subdirectory. - check_call('mkdir %s/SUBDIR' % mount_dir, shell=True) + check_call('mkdir %s/SUBDIR' % scratch_dir, shell=True) # Create a small file in this image. check_call('dd if=/dev/urandom of=%s bs=1M count=1' @@ -621,15 +511,20 @@ def fs_obj_symlink(request, u_boot_config): % medium_file, shell=True).decode() md5val.extend([out.split()[0]]) + try: + # 1GiB volume + fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x40000000, '1GB', scratch_dir) + except CalledProcessError as err: + pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err)) + return + except CalledProcessError: pytest.skip('Setup failed for filesystem: ' + fs_type) - umount_fs(mount_dir) return else: - umount_fs(mount_dir) yield [fs_ubtype, fs_img, md5val] finally: - call('rmdir %s' % mount_dir, shell=True) + call('rm -rf %s' % scratch_dir, shell=True) call('rm -f %s' % fs_img, shell=True) # @@ -665,7 +560,7 @@ def fs_obj_fat(request, u_boot_config): try: # the volume size depends on the filesystem - fs_img = fs_helper.mk_fs(u_boot_config, fs_type, fs_size, f'{fs_size}', 1024) + fs_img = fs_helper.mk_fs(u_boot_config, fs_type, fs_size, f'{fs_size}', None, 1024) except: pytest.skip('Setup failed for filesystem: ' + fs_type) return diff --git a/test/py/tests/test_mmc.py b/test/py/tests/test_mmc.py index a96c4e8fd89..46240433884 100644 --- a/test/py/tests/test_mmc.py +++ b/test/py/tests/test_mmc.py @@ -18,16 +18,55 @@ For example: # Setup env__mmc_device_test_skip to not skipping the test. By default, its # value is set to True. Set it to False to run all tests for MMC device. env__mmc_device_test_skip = False + +# Setup env__mmc_device to set the supported mmc modes to be tested +env__mmc_device { + 'mmc_modes': ['MMC_LEGACY', 'SD_HS'], +} + """ mmc_set_up = False controllers = 0 devices = {} +mmc_modes_name = [] +mmc_modes = [] + +def setup_mmc_modes(cons): + global mmc_modes, mmc_modes_name + f = cons.config.env.get('env__mmc_device', None) + if f: + mmc_modes_name = f.get('mmc_modes', None) + + # Set mmc mode to default mode (legacy), if speed mode config isn't enabled + if cons.config.buildconfig.get('config_mmc_speed_mode_set', 'n') != 'y': + mmc_modes = [0] + return + + if mmc_modes_name: + mmc_help = cons.run_command('mmc -help') + m = re.search(r"\[MMC_LEGACY(.*\n.+])", mmc_help) + modes = [ + x.strip() + for x in m.group() + .replace('\n', '') + .replace('[', '') + .replace(']', '') + .split(',') + ] + + for mode in mmc_modes_name: + mmc_modes += [modes.index(mode)] + else: + # Set mmc mode to default mode (legacy), if it is not defined in env + mmc_modes = [0] def setup_mmc(u_boot_console): if u_boot_console.config.env.get('env__mmc_device_test_skip', True): pytest.skip('MMC device test is not enabled') + setup_mmc_modes(u_boot_console) + @pytest.mark.buildconfigspec('cmd_mmc') def test_mmc_list(u_boot_console): setup_mmc(u_boot_console) @@ -58,21 +97,22 @@ def test_mmc_dev(u_boot_console): fail = 0 for x in range(0, controllers): devices[x]['detected'] = 'yes' - output = u_boot_console.run_command('mmc dev %d' % x) - # Some sort of switch here - if 'Card did not respond to voltage select' in output: - fail = 1 - devices[x]['detected'] = 'no' + for y in mmc_modes: + output = u_boot_console.run_command('mmc dev %d 0 %d' % x, y) - if 'no mmc device at slot' in output: - devices[x]['detected'] = 'no' + if 'Card did not respond to voltage select' in output: + fail = 1 + devices[x]['detected'] = 'no' - if 'MMC: no card present' in output: - devices[x]['detected'] = 'no' + if 'no mmc device at slot' in output: + devices[x]['detected'] = 'no' - if fail: - pytest.fail('Card not present') + if 'MMC: no card present' in output: + devices[x]['detected'] = 'no' + + if fail: + pytest.fail('Card not present') @pytest.mark.buildconfigspec('cmd_mmc') def test_mmcinfo(u_boot_console): @@ -81,19 +121,22 @@ def test_mmcinfo(u_boot_console): for x in range(0, controllers): if devices[x]['detected'] == 'yes': - u_boot_console.run_command('mmc dev %d' % x) - output = u_boot_console.run_command('mmcinfo') - if 'busy timeout' in output: - pytest.skip('No SD/MMC/eMMC device present') + for y in mmc_modes: + u_boot_console.run_command('mmc dev %d 0 %d' % x, y) + output = u_boot_console.run_command('mmcinfo') + if 'busy timeout' in output: + pytest.skip('No SD/MMC/eMMC device present') - obj = re.search(r'Capacity: (\d+|\d+[\.]?\d)', output) - try: - capacity = float(obj.groups()[0]) - print(capacity) - devices[x]['capacity'] = capacity - print('Capacity of dev %d is: %g GiB' % (x, capacity)) - except ValueError: - pytest.fail('MMC capacity not recognized') + assert mmc_modes_name[mmc_modes.index(y)] in output + + obj = re.search(r'Capacity: (\d+|\d+[\.]?\d)', output) + try: + capacity = float(obj.groups()[0]) + print(capacity) + devices[x]['capacity'] = capacity + print('Capacity of dev %d is: %g GiB' % (x, capacity)) + except ValueError: + pytest.fail('MMC capacity not recognized') @pytest.mark.buildconfigspec('cmd_mmc') def test_mmc_info(u_boot_console): @@ -102,19 +145,21 @@ def test_mmc_info(u_boot_console): for x in range(0, controllers): if devices[x]['detected'] == 'yes': - u_boot_console.run_command('mmc dev %d' % x) + for y in mmc_modes: + u_boot_console.run_command('mmc dev %d 0 %d' % x, y) - output = u_boot_console.run_command('mmc info') + output = u_boot_console.run_command('mmc info') + assert mmc_modes_name[mmc_modes.index(y)] in output - obj = re.search(r'Capacity: (\d+|\d+[\.]?\d)', output) - try: - capacity = float(obj.groups()[0]) - print(capacity) - if devices[x]['capacity'] != capacity: - pytest.fail("MMC capacity doesn't match mmcinfo") + obj = re.search(r'Capacity: (\d+|\d+[\.]?\d)', output) + try: + capacity = float(obj.groups()[0]) + print(capacity) + if devices[x]['capacity'] != capacity: + pytest.fail("MMC capacity doesn't match mmcinfo") - except ValueError: - pytest.fail('MMC capacity not recognized') + except ValueError: + pytest.fail('MMC capacity not recognized') @pytest.mark.buildconfigspec('cmd_mmc') def test_mmc_rescan(u_boot_console): @@ -126,12 +171,13 @@ def test_mmc_rescan(u_boot_console): for x in range(0, controllers): if devices[x]['detected'] == 'yes': - u_boot_console.run_command('mmc dev %d' % x) - output = u_boot_console.run_command('mmc rescan') - if output: - pytest.fail('mmc rescan has something to check') - output = u_boot_console.run_command('echo $?') - assert output.endswith('0') + for y in mmc_modes: + u_boot_console.run_command('mmc dev %d 0 %d' % x, y) + output = u_boot_console.run_command('mmc rescan') + if output: + pytest.fail('mmc rescan has something to check') + output = u_boot_console.run_command('echo $?') + assert output.endswith('0') @pytest.mark.buildconfigspec('cmd_mmc') def test_mmc_part(u_boot_console): @@ -148,7 +194,8 @@ def test_mmc_part(u_boot_console): lines = output.split('\n') part_fat = [] - part_ext = [] + part_ext2 = [] + part_ext4 = [] for line in lines: obj = re.search( r'(\d)\s+\d+\s+\d+\s+\w+\d+\w+-\d+\s+(\d+\w+)', line) @@ -161,15 +208,21 @@ def test_mmc_part(u_boot_console): print('Fat detected') part_fat.append(part_id) elif part_type == '83': - print('ext detected') - part_ext.append(part_id) + print('ext(2/4) detected') + output = u_boot_console.run_command( + 'fstype mmc %d:%d' % x, part_id + ) + if 'ext2' in output: + part_ext2.append(part_id) + elif 'ext4' in output: + part_ext4.append(part_id) else: pytest.fail('Unsupported Filesystem on device %d' % x) - devices[x]['ext4'] = part_ext - devices[x]['ext2'] = part_ext + devices[x]['ext4'] = part_ext4 + devices[x]['ext2'] = part_ext2 devices[x]['fat'] = part_fat - if not part_ext and not part_fat: + if not part_ext2 and not part_ext4 and not part_fat: pytest.fail('No partition detected on device %d' % x) @pytest.mark.buildconfigspec('cmd_mmc') @@ -185,7 +238,6 @@ def test_mmc_fatls_fatinfo(u_boot_console): fs = 'fat' for x in range(0, controllers): if devices[x]['detected'] == 'yes': - u_boot_console.run_command('mmc dev %d' % x) try: partitions = devices[x][fs] except: @@ -193,20 +245,22 @@ def test_mmc_fatls_fatinfo(u_boot_console): continue for part in partitions: - output = u_boot_console.run_command( - 'fatls mmc %d:%s' % (x, part)) - if 'Unrecognized filesystem type' in output: - partitions.remove(part) - pytest.fail('Unrecognized filesystem') - - if not re.search(r'\d file\(s\), \d dir\(s\)', output): - pytest.fail('%s read failed on device %d' % (fs.upper, x)) - output = u_boot_console.run_command( - 'fatinfo mmc %d:%s' % (x, part)) - string = 'Filesystem: %s' % fs.upper - if re.search(string, output): - pytest.fail('%s FS failed on device %d' % (fs.upper(), x)) - part_detect = 1 + for y in mmc_modes: + u_boot_console.run_command('mmc dev %d %d %d' % x, part, y) + output = u_boot_console.run_command( + 'fatls mmc %d:%s' % (x, part)) + if 'Unrecognized filesystem type' in output: + partitions.remove(part) + pytest.fail('Unrecognized filesystem') + + if not re.search(r'\d file\(s\), \d dir\(s\)', output): + pytest.fail('%s read failed on device %d' % (fs.upper, x)) + output = u_boot_console.run_command( + 'fatinfo mmc %d:%s' % (x, part)) + string = 'Filesystem: %s' % fs.upper + if re.search(string, output): + pytest.fail('%s FS failed on device %d' % (fs.upper(), x)) + part_detect = 1 if not part_detect: pytest.skip('No %s partition detected' % fs.upper()) @@ -226,7 +280,6 @@ def test_mmc_fatload_fatwrite(u_boot_console): fs = 'fat' for x in range(0, controllers): if devices[x]['detected'] == 'yes': - u_boot_console.run_command('mmc dev %d' % x) try: partitions = devices[x][fs] except: @@ -234,49 +287,51 @@ def test_mmc_fatload_fatwrite(u_boot_console): continue for part in partitions: - part_detect = 1 - addr = u_boot_utils.find_ram_base(u_boot_console) - devices[x]['addr_%d' % part] = addr - size = random.randint(4, 1 * 1024 * 1024) - devices[x]['size_%d' % part] = size - # count CRC32 - output = u_boot_console.run_command('crc32 %x %x' % (addr, size)) - m = re.search('==> (.+?)', output) - if not m: - pytest.fail('CRC32 failed') - expected_crc32 = m.group(1) - devices[x]['expected_crc32_%d' % part] = expected_crc32 - # do write - file = '%s_%d' % ('uboot_test', size) - devices[x]['file_%d' % part] = file - output = u_boot_console.run_command( - '%swrite mmc %d:%s %x %s %x' % (fs, x, part, addr, file, size) - ) - assert 'Unable to write' not in output - assert 'Error' not in output - assert 'overflow' not in output - expected_text = '%d bytes written' % size - assert expected_text in output - - alignment = int( - u_boot_console.config.buildconfig.get( - 'config_sys_cacheline_size', 128 + for y in mmc_modes: + u_boot_console.run_command('mmc dev %d %d %d' % x, part, y) + part_detect = 1 + addr = u_boot_utils.find_ram_base(u_boot_console) + devices[x]['addr_%d' % part] = addr + size = random.randint(4, 1 * 1024 * 1024) + devices[x]['size_%d' % part] = size + # count CRC32 + output = u_boot_console.run_command('crc32 %x %x' % (addr, size)) + m = re.search('==> (.+?)', output) + if not m: + pytest.fail('CRC32 failed') + expected_crc32 = m.group(1) + devices[x]['expected_crc32_%d' % part] = expected_crc32 + # do write + file = '%s_%d' % ('uboot_test', size) + devices[x]['file_%d' % part] = file + output = u_boot_console.run_command( + '%swrite mmc %d:%s %x %s %x' % (fs, x, part, addr, file, size) ) - ) - offset = random.randrange(alignment, 1024, alignment) - output = u_boot_console.run_command( - '%sload mmc %d:%s %x %s' % (fs, x, part, addr + offset, file) - ) - assert 'Invalid FAT entry' not in output - assert 'Unable to read file' not in output - assert 'Misaligned buffer address' not in output - expected_text = '%d bytes read' % size - assert expected_text in output - - output = u_boot_console.run_command( - 'crc32 %x $filesize' % (addr + offset) - ) - assert expected_crc32 in output + assert 'Unable to write' not in output + assert 'Error' not in output + assert 'overflow' not in output + expected_text = '%d bytes written' % size + assert expected_text in output + + alignment = int( + u_boot_console.config.buildconfig.get( + 'config_sys_cacheline_size', 128 + ) + ) + offset = random.randrange(alignment, 1024, alignment) + output = u_boot_console.run_command( + '%sload mmc %d:%s %x %s' % (fs, x, part, addr + offset, file) + ) + assert 'Invalid FAT entry' not in output + assert 'Unable to read file' not in output + assert 'Misaligned buffer address' not in output + expected_text = '%d bytes read' % size + assert expected_text in output + + output = u_boot_console.run_command( + 'crc32 %x $filesize' % (addr + offset) + ) + assert expected_crc32 in output if not part_detect: pytest.skip('No %s partition detected' % fs.upper()) @@ -300,13 +355,16 @@ def test_mmc_ext4ls(u_boot_console): print('No %s table on this device' % fs.upper()) continue - u_boot_console.run_command('mmc dev %d' % x) for part in partitions: - output = u_boot_console.run_command('%sls mmc %d:%s' % (fs, x, part)) - if 'Unrecognized filesystem type' in output: - partitions.remove(part) - pytest.fail('Unrecognized filesystem') - part_detect = 1 + for y in mmc_modes: + u_boot_console.run_command('mmc dev %d %d %d' % x, part, y) + output = u_boot_console.run_command( + '%sls mmc %d:%s' % (fs, x, part) + ) + if 'Unrecognized filesystem type' in output: + partitions.remove(part) + pytest.fail('Unrecognized filesystem') + part_detect = 1 if not part_detect: pytest.skip('No %s partition detected' % fs.upper()) @@ -326,7 +384,6 @@ def test_mmc_ext4load_ext4write(u_boot_console): fs = 'ext4' for x in range(0, controllers): if devices[x]['detected'] == 'yes': - u_boot_console.run_command('mmc dev %d' % x) try: partitions = devices[x][fs] except: @@ -334,42 +391,44 @@ def test_mmc_ext4load_ext4write(u_boot_console): continue for part in partitions: - part_detect = 1 - addr = u_boot_utils.find_ram_base(u_boot_console) - devices[x]['addr_%d' % part] = addr - size = random.randint(4, 1 * 1024 * 1024) - devices[x]['size_%d' % part] = size - # count CRC32 - output = u_boot_console.run_command('crc32 %x %x' % (addr, size)) - m = re.search('==> (.+?)', output) - if not m: - pytest.fail('CRC32 failed') - expected_crc32 = m.group(1) - devices[x]['expected_crc32_%d' % part] = expected_crc32 - # do write - - file = '%s_%d' % ('uboot_test', size) - devices[x]['file_%d' % part] = file - output = u_boot_console.run_command( - '%swrite mmc %d:%s %x /%s %x' % (fs, x, part, addr, file, size) - ) - assert 'Unable to write' not in output - assert 'Error' not in output - assert 'overflow' not in output - expected_text = '%d bytes written' % size - assert expected_text in output - - offset = random.randrange(128, 1024, 128) - output = u_boot_console.run_command( - '%sload mmc %d:%s %x /%s' % (fs, x, part, addr + offset, file) - ) - expected_text = '%d bytes read' % size - assert expected_text in output - - output = u_boot_console.run_command( - 'crc32 %x $filesize' % (addr + offset) - ) - assert expected_crc32 in output + for y in mmc_modes: + u_boot_console.run_command('mmc dev %d %d %d' % x, part, y) + part_detect = 1 + addr = u_boot_utils.find_ram_base(u_boot_console) + devices[x]['addr_%d' % part] = addr + size = random.randint(4, 1 * 1024 * 1024) + devices[x]['size_%d' % part] = size + # count CRC32 + output = u_boot_console.run_command('crc32 %x %x' % (addr, size)) + m = re.search('==> (.+?)', output) + if not m: + pytest.fail('CRC32 failed') + expected_crc32 = m.group(1) + devices[x]['expected_crc32_%d' % part] = expected_crc32 + + # do write + file = '%s_%d' % ('uboot_test', size) + devices[x]['file_%d' % part] = file + output = u_boot_console.run_command( + '%swrite mmc %d:%s %x /%s %x' % (fs, x, part, addr, file, size) + ) + assert 'Unable to write' not in output + assert 'Error' not in output + assert 'overflow' not in output + expected_text = '%d bytes written' % size + assert expected_text in output + + offset = random.randrange(128, 1024, 128) + output = u_boot_console.run_command( + '%sload mmc %d:%s %x /%s' % (fs, x, part, addr + offset, file) + ) + expected_text = '%d bytes read' % size + assert expected_text in output + + output = u_boot_console.run_command( + 'crc32 %x $filesize' % (addr + offset) + ) + assert expected_crc32 in output if not part_detect: pytest.skip('No %s partition detected' % fs.upper()) @@ -387,7 +446,6 @@ def test_mmc_ext2ls(u_boot_console): fs = 'ext2' for x in range(0, controllers): if devices[x]['detected'] == 'yes': - u_boot_console.run_command('mmc dev %d' % x) try: partitions = devices[x][fs] except: @@ -395,12 +453,16 @@ def test_mmc_ext2ls(u_boot_console): continue for part in partitions: - part_detect = 1 - output = u_boot_console.run_command('%sls mmc %d:%s' % (fs, x, part)) - if 'Unrecognized filesystem type' in output: - partitions.remove(part) - pytest.fail('Unrecognized filesystem') - part_detect = 1 + for y in mmc_modes: + u_boot_console.run_command('mmc dev %d %d %d' % x, part, y) + part_detect = 1 + output = u_boot_console.run_command( + '%sls mmc %d:%s' % (fs, x, part) + ) + if 'Unrecognized filesystem type' in output: + partitions.remove(part) + pytest.fail('Unrecognized filesystem') + part_detect = 1 if not part_detect: pytest.skip('No %s partition detected' % fs.upper()) @@ -421,7 +483,6 @@ def test_mmc_ext2load(u_boot_console): fs = 'ext2' for x in range(0, controllers): if devices[x]['detected'] == 'yes': - u_boot_console.run_command('mmc dev %d' % x) try: partitions = devices[x][fs] except: @@ -429,23 +490,25 @@ def test_mmc_ext2load(u_boot_console): continue for part in partitions: - part_detect = 1 - addr = devices[x]['addr_%d' % part] - size = devices[x]['size_%d' % part] - expected_crc32 = devices[x]['expected_crc32_%d' % part] - file = devices[x]['file_%d' % part] - - offset = random.randrange(128, 1024, 128) - output = u_boot_console.run_command( - '%sload mmc %d:%s %x /%s' % (fs, x, part, addr + offset, file) - ) - expected_text = '%d bytes read' % size - assert expected_text in output - - output = u_boot_console.run_command( - 'crc32 %x $filesize' % (addr + offset) - ) - assert expected_crc32 in output + for y in mmc_modes: + u_boot_console.run_command('mmc dev %d %d %d' % x, part, y) + part_detect = 1 + addr = devices[x]['addr_%d' % part] + size = devices[x]['size_%d' % part] + expected_crc32 = devices[x]['expected_crc32_%d' % part] + file = devices[x]['file_%d' % part] + + offset = random.randrange(128, 1024, 128) + output = u_boot_console.run_command( + '%sload mmc %d:%s %x /%s' % (fs, x, part, addr + offset, file) + ) + expected_text = '%d bytes read' % size + assert expected_text in output + + output = u_boot_console.run_command( + 'crc32 %x $filesize' % (addr + offset) + ) + assert expected_crc32 in output if not part_detect: pytest.skip('No %s partition detected' % fs.upper()) @@ -462,8 +525,7 @@ def test_mmc_ls(u_boot_console): part_detect = 0 for x in range(0, controllers): if devices[x]['detected'] == 'yes': - u_boot_console.run_command('mmc dev %d' % x) - for fs in ['fat', 'ext4']: + for fs in ['fat', 'ext4', 'ext2']: try: partitions = devices[x][fs] except: @@ -471,12 +533,14 @@ def test_mmc_ls(u_boot_console): continue for part in partitions: - part_detect = 1 - output = u_boot_console.run_command('ls mmc %d:%s' % (x, part)) - if re.search(r'No \w+ table on this device', output): - pytest.fail( - '%s: Partition table not found %d' % (fs.upper(), x) - ) + for y in mmc_modes: + u_boot_console.run_command('mmc dev %d %d %d' % x, part, y) + part_detect = 1 + output = u_boot_console.run_command('ls mmc %d:%s' % (x, part)) + if re.search(r'No \w+ table on this device', output): + pytest.fail( + '%s: Partition table not found %d' % (fs.upper(), x) + ) if not part_detect: pytest.skip('No partition detected') @@ -493,8 +557,7 @@ def test_mmc_load(u_boot_console): part_detect = 0 for x in range(0, controllers): if devices[x]['detected'] == 'yes': - u_boot_console.run_command('mmc dev %d' % x) - for fs in ['fat', 'ext4']: + for fs in ['fat', 'ext4', 'ext2']: try: partitions = devices[x][fs] except: @@ -502,23 +565,25 @@ def test_mmc_load(u_boot_console): continue for part in partitions: - part_detect = 1 - addr = devices[x]['addr_%d' % part] - size = devices[x]['size_%d' % part] - expected_crc32 = devices[x]['expected_crc32_%d' % part] - file = devices[x]['file_%d' % part] - - offset = random.randrange(128, 1024, 128) - output = u_boot_console.run_command( - 'load mmc %d:%s %x /%s' % (x, part, addr + offset, file) - ) - expected_text = '%d bytes read' % size - assert expected_text in output + for y in mmc_modes: + u_boot_console.run_command('mmc dev %d %d %d' % x, part, y) + part_detect = 1 + addr = devices[x]['addr_%d' % part] + size = devices[x]['size_%d' % part] + expected_crc32 = devices[x]['expected_crc32_%d' % part] + file = devices[x]['file_%d' % part] + + offset = random.randrange(128, 1024, 128) + output = u_boot_console.run_command( + 'load mmc %d:%s %x /%s' % (x, part, addr + offset, file) + ) + expected_text = '%d bytes read' % size + assert expected_text in output - output = u_boot_console.run_command( - 'crc32 %x $filesize' % (addr + offset) - ) - assert expected_crc32 in output + output = u_boot_console.run_command( + 'crc32 %x $filesize' % (addr + offset) + ) + assert expected_crc32 in output if not part_detect: pytest.skip('No partition detected') @@ -535,8 +600,7 @@ def test_mmc_save(u_boot_console): part_detect = 0 for x in range(0, controllers): if devices[x]['detected'] == 'yes': - u_boot_console.run_command('mmc dev %d' % x) - for fs in ['fat', 'ext4']: + for fs in ['fat', 'ext4', 'ext2']: try: partitions = devices[x][fs] except: @@ -544,18 +608,20 @@ def test_mmc_save(u_boot_console): continue for part in partitions: - part_detect = 1 - addr = devices[x]['addr_%d' % part] - size = 0 - file = devices[x]['file_%d' % part] - - offset = random.randrange(128, 1024, 128) - output = u_boot_console.run_command( - 'save mmc %d:%s %x /%s %d' - % (x, part, addr + offset, file, size) - ) - expected_text = '%d bytes written' % size - assert expected_text in output + for y in mmc_modes: + u_boot_console.run_command('mmc dev %d %d %d' % x, part, y) + part_detect = 1 + addr = devices[x]['addr_%d' % part] + size = 0 + file = devices[x]['file_%d' % part] + + offset = random.randrange(128, 1024, 128) + output = u_boot_console.run_command( + 'save mmc %d:%s %x /%s %d' + % (x, part, addr + offset, file, size) + ) + expected_text = '%d bytes written' % size + assert expected_text in output if not part_detect: pytest.skip('No partition detected') @@ -582,7 +648,6 @@ def test_mmc_fat_read_write_files(u_boot_console): for x in range(0, controllers): if devices[x]['detected'] == 'yes': - u_boot_console.run_command('mmc dev %d' % x) try: partitions = devices[x][fs] except: @@ -590,82 +655,86 @@ def test_mmc_fat_read_write_files(u_boot_console): continue for part in partitions: - part_detect = 1 - addr = u_boot_utils.find_ram_base(u_boot_console) - count_f = 0 - addr_l = [] - size_l = [] - file_l = [] - crc32_l = [] - offset_l = [] - addr_l.append(addr) - - while count_f < num_files: - size_l.append(random.randint(4, 1 * 1024 * 1024)) - - # CRC32 count - output = u_boot_console.run_command( - 'crc32 %x %x' % (addr_l[count_f], size_l[count_f]) - ) - m = re.search('==> (.+?)', output) - if not m: - pytest.fail('CRC32 failed') - crc32_l.append(m.group(1)) - - # Write operation - file_l.append('%s_%d_%d' % ('uboot_test', count_f, size_l[count_f])) - output = u_boot_console.run_command( - '%swrite mmc %d:%s %x %s %x' - % ( - fs, - x, - part, - addr_l[count_f], - file_l[count_f], - size_l[count_f], + for y in mmc_modes: + u_boot_console.run_command('mmc dev %d %d %d' % x, part, y) + part_detect = 1 + addr = u_boot_utils.find_ram_base(u_boot_console) + count_f = 0 + addr_l = [] + size_l = [] + file_l = [] + crc32_l = [] + offset_l = [] + addr_l.append(addr) + + while count_f < num_files: + size_l.append(random.randint(4, 1 * 1024 * 1024)) + + # CRC32 count + output = u_boot_console.run_command( + 'crc32 %x %x' % (addr_l[count_f], size_l[count_f]) ) - ) - assert 'Unable to write' not in output - assert 'Error' not in output - assert 'overflow' not in output - expected_text = '%d bytes written' % size_l[count_f] - assert expected_text in output - - addr_l.append(addr_l[count_f] + size_l[count_f] + 1048576) - count_f += 1 - - count_f = 0 - while count_f < num_files: - alignment = int( - u_boot_console.config.buildconfig.get( - 'config_sys_cacheline_size', 128 + m = re.search('==> (.+?)', output) + if not m: + pytest.fail('CRC32 failed') + crc32_l.append(m.group(1)) + + # Write operation + file_l.append( + '%s_%d_%d' % ('uboot_test', count_f, size_l[count_f]) ) - ) - offset_l.append(random.randrange(alignment, 1024, alignment)) - - # Read operation - output = u_boot_console.run_command( - '%sload mmc %d:%s %x %s' - % ( - fs, - x, - part, - addr_l[count_f] + offset_l[count_f], - file_l[count_f], + output = u_boot_console.run_command( + '%swrite mmc %d:%s %x %s %x' + % ( + fs, + x, + part, + addr_l[count_f], + file_l[count_f], + size_l[count_f], + ) ) - ) - assert 'Invalid FAT entry' not in output - assert 'Unable to read file' not in output - assert 'Misaligned buffer address' not in output - expected_text = '%d bytes read' % size_l[count_f] - assert expected_text in output - - output = u_boot_console.run_command( - 'crc32 %x $filesize' % (addr_l[count_f] + offset_l[count_f]) - ) - assert crc32_l[count_f] in output + assert 'Unable to write' not in output + assert 'Error' not in output + assert 'overflow' not in output + expected_text = '%d bytes written' % size_l[count_f] + assert expected_text in output + + addr_l.append(addr_l[count_f] + size_l[count_f] + 1048576) + count_f += 1 + + count_f = 0 + while count_f < num_files: + alignment = int( + u_boot_console.config.buildconfig.get( + 'config_sys_cacheline_size', 128 + ) + ) + offset_l.append(random.randrange(alignment, 1024, alignment)) + + # Read operation + output = u_boot_console.run_command( + '%sload mmc %d:%s %x %s' + % ( + fs, + x, + part, + addr_l[count_f] + offset_l[count_f], + file_l[count_f], + ) + ) + assert 'Invalid FAT entry' not in output + assert 'Unable to read file' not in output + assert 'Misaligned buffer address' not in output + expected_text = '%d bytes read' % size_l[count_f] + assert expected_text in output + + output = u_boot_console.run_command( + 'crc32 %x $filesize' % (addr_l[count_f] + offset_l[count_f]) + ) + assert crc32_l[count_f] in output - count_f += 1 + count_f += 1 if not part_detect: pytest.skip('No %s partition detected' % fs.upper()) diff --git a/test/py/tests/test_usb.py b/test/py/tests/test_usb.py index 2397fd3c2e7..e1f203b5cbc 100644 --- a/test/py/tests/test_usb.py +++ b/test/py/tests/test_usb.py @@ -227,7 +227,8 @@ def test_usb_part(u_boot_console): lines = output.split('\n') part_fat = [] - part_ext = [] + part_ext2 = [] + part_ext4 = [] for line in lines: obj = re.search(r'(\d)\s+\d+\s+\d+\s+\w+\d+\w+-\d+\s+(\d+\w+)', line) if obj: @@ -239,15 +240,21 @@ def test_usb_part(u_boot_console): print('Fat detected') part_fat.append(part_id) elif part_type == '83': - print('ext detected') - part_ext.append(part_id) + print('ext(2/4) detected') + output = u_boot_console.run_command( + 'fstype usb %d:%d' % i, part_id + ) + if 'ext2' in output: + part_ext2.append(part_id) + elif 'ext4' in output: + part_ext4.append(part_id) else: pytest.fail('Unsupported Filesystem on device %d' % i) - devices[i]['ext4'] = part_ext - devices[i]['ext2'] = part_ext + devices[i]['ext4'] = part_ext4 + devices[i]['ext2'] = part_ext2 devices[i]['fat'] = part_fat - if not part_ext and not part_fat: + if not part_ext2 and not part_ext4 and not part_fat: pytest.fail('No partition detected on device %d' % i) return devices, controllers, storage_device @@ -497,7 +504,7 @@ def test_usb_ext2load(u_boot_console): for part in partitions: part_detect = 1 file, size, expected_crc32 = \ - usb_ext4load_ext4write(u_boot_console, 'ext4', x, part) + usb_ext4load_ext4write(u_boot_console, fs, x, part) addr = u_boot_utils.find_ram_base(u_boot_console) offset = random.randrange(128, 1024, 128) @@ -526,7 +533,7 @@ def test_usb_ls(u_boot_console): for x in range(0, int(storage_device)): if devices[x]['detected'] == 'yes': u_boot_console.run_command('usb dev %d' % x) - for fs in ['fat', 'ext4']: + for fs in ['fat', 'ext2', 'ext4']: try: partitions = devices[x][fs] except: @@ -556,7 +563,7 @@ def test_usb_load(u_boot_console): for x in range(0, int(storage_device)): if devices[x]['detected'] == 'yes': u_boot_console.run_command('usb dev %d' % x) - for fs in ['fat', 'ext4']: + for fs in ['fat', 'ext2', 'ext4']: try: partitions = devices[x][fs] except: @@ -570,7 +577,7 @@ def test_usb_load(u_boot_console): if fs == 'fat': file, size, expected_crc32 = \ usb_fatload_fatwrite(u_boot_console, fs, x, part) - elif fs == 'ext4': + elif fs in ['ext4', 'ext2']: file, size, expected_crc32 = \ usb_ext4load_ext4write(u_boot_console, fs, x, part) @@ -600,7 +607,7 @@ def test_usb_save(u_boot_console): for x in range(0, int(storage_device)): if devices[x]['detected'] == 'yes': u_boot_console.run_command('usb dev %d' % x) - for fs in ['fat', 'ext4']: + for fs in ['fat', 'ext2', 'ext4']: try: partitions = devices[x][fs] except: diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py index 6d44191976b..10ec7e582e0 100644 --- a/test/py/tests/test_ut.py +++ b/test/py/tests/test_ut.py @@ -8,7 +8,6 @@ test one at a time, as well setting up some files needed by the tests. # Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. """ import collections -import getpass import gzip import os import os.path @@ -28,70 +27,36 @@ def mkdir_cond(dirname): if not os.path.exists(dirname): os.mkdir(dirname) -def setup_image(cons, devnum, part_type, second_part=False, basename='mmc'): - """Create a 20MB disk image with a single partition +def setup_image(cons, devnum, part_type, img_size=20, second_part=False, + basename='mmc'): + """Create a disk image with a single partition Args: cons (ConsoleBase): Console to use devnum (int): Device number to use, e.g. 1 part_type (int): Partition type, e.g. 0xc for FAT32 + img_size (int): Image size in MiB second_part (bool): True to contain a small second partition basename (str): Base name to use in the filename, e.g. 'mmc' Returns: tuple: str: Filename of MMC image - str: Directory name of 'mnt' directory + str: Directory name of scratch directory """ fname = os.path.join(cons.config.source_dir, f'{basename}{devnum}.img') - mnt = os.path.join(cons.config.persistent_data_dir, 'mnt') + mnt = os.path.join(cons.config.persistent_data_dir, 'scratch') mkdir_cond(mnt) - spec = f'type={part_type:x}, size=18M, bootable' + spec = f'type={part_type:x}, size={img_size - 2}M, start=1M, bootable' if second_part: spec += '\ntype=c' u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M') - u_boot_utils.run_and_log(cons, f'sudo sfdisk {fname}', + u_boot_utils.run_and_log(cons, f'sfdisk {fname}', stdin=spec.encode('utf-8')) return fname, mnt -def mount_image(cons, fname, mnt, fstype): - """Create a filesystem and mount it on partition 1 - - Args: - cons (ConsoleBase): Console to use - fname (str): Filename of MMC image - mnt (str): Directory name of 'mnt' directory - fstype (str): Filesystem type ('vfat' or 'ext4') - - Returns: - str: Name of loop device used - """ - out = u_boot_utils.run_and_log(cons, f'sudo losetup --show -f -P {fname}') - loop = out.strip() - part = f'{loop}p1' - u_boot_utils.run_and_log(cons, f'sudo mkfs.{fstype} {part}') - opts = '' - if fstype == 'vfat': - opts += f' -o uid={os.getuid()},gid={os.getgid()}' - u_boot_utils.run_and_log(cons, f'sudo mount -o loop {part} {mnt}{opts}') - u_boot_utils.run_and_log(cons, f'sudo chown {getpass.getuser()} {mnt}') - return loop - -def copy_prepared_image(cons, devnum, fname, basename='mmc'): - """Use a prepared image since we cannot create one - - Args: - cons (ConsoleBase): Console touse - devnum (int): device number - fname (str): Filename of MMC image - basename (str): Base name to use in the filename, e.g. 'mmc' - """ - infname = os.path.join(cons.config.source_dir, - f'test/py/tests/bootstd/{basename}{devnum}.img.xz') - u_boot_utils.run_and_log(cons, ['sh', '-c', f'xz -dc {infname} >{fname}']) - def setup_bootmenu_image(cons): """Create a 20MB disk image with a single ext4 partition @@ -100,14 +65,7 @@ def setup_bootmenu_image(cons): mmc_dev = 4 fname, mnt = setup_image(cons, mmc_dev, 0x83) - loop = None - mounted = False - complete = False - try: - loop = mount_image(cons, fname, mnt, 'ext4') - mounted = True - - script = '''# DO NOT EDIT THIS FILE + script = '''# DO NOT EDIT THIS FILE # # Please edit /boot/armbianEnv.txt to set supported parameters # @@ -181,64 +139,52 @@ booti ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r} # Recompile with: # mkimage -C none -A arm -T script -d /boot/boot.cmd /boot/boot.scr ''' - bootdir = os.path.join(mnt, 'boot') - mkdir_cond(bootdir) - cmd_fname = os.path.join(bootdir, 'boot.cmd') - scr_fname = os.path.join(bootdir, 'boot.scr') - with open(cmd_fname, 'w', encoding='ascii') as outf: - print(script, file=outf) - - infname = os.path.join(cons.config.source_dir, - 'test/py/tests/bootstd/armbian.bmp.xz') - bmp_file = os.path.join(bootdir, 'boot.bmp') - u_boot_utils.run_and_log( - cons, - ['sh', '-c', f'xz -dc {infname} >{bmp_file}']) + bootdir = os.path.join(mnt, 'boot') + mkdir_cond(bootdir) + cmd_fname = os.path.join(bootdir, 'boot.cmd') + scr_fname = os.path.join(bootdir, 'boot.scr') + with open(cmd_fname, 'w', encoding='ascii') as outf: + print(script, file=outf) - u_boot_utils.run_and_log( - cons, f'mkimage -C none -A arm -T script -d {cmd_fname} {scr_fname}') - - kernel = 'vmlinuz-5.15.63-rockchip64' - target = os.path.join(bootdir, kernel) - with open(target, 'wb') as outf: - print('kernel', outf) + infname = os.path.join(cons.config.source_dir, + 'test/py/tests/bootstd/armbian.bmp.xz') + bmp_file = os.path.join(bootdir, 'boot.bmp') + u_boot_utils.run_and_log( + cons, + ['sh', '-c', f'xz -dc {infname} >{bmp_file}']) - symlink = os.path.join(bootdir, 'Image') - if os.path.exists(symlink): - os.remove(symlink) - u_boot_utils.run_and_log( - cons, f'echo here {kernel} {symlink}') - os.symlink(kernel, symlink) + mkimage = cons.config.build_dir + '/tools/mkimage' + u_boot_utils.run_and_log( + cons, f'{mkimage} -C none -A arm -T script -d {cmd_fname} {scr_fname}') - complete = True + kernel = 'vmlinuz-5.15.63-rockchip64' + target = os.path.join(bootdir, kernel) + with open(target, 'wb') as outf: + print('kernel', outf) - except ValueError as exc: - print(f'Falled to create image, failing back to prepared copy: {exc}') - finally: - if mounted: - u_boot_utils.run_and_log(cons, f'sudo umount --lazy {mnt}') - if loop: - u_boot_utils.run_and_log(cons, f'sudo losetup -d {loop}') + symlink = os.path.join(bootdir, 'Image') + if os.path.exists(symlink): + os.remove(symlink) + u_boot_utils.run_and_log( + cons, f'echo here {kernel} {symlink}') + os.symlink(kernel, symlink) - if not complete: - copy_prepared_image(cons, mmc_dev, fname) + fsfile = 'ext18M.img' + u_boot_utils.run_and_log(cons, f'fallocate -l 18M {fsfile}') + u_boot_utils.run_and_log(cons, f'mkfs.ext4 {fsfile} -d {mnt}') + u_boot_utils.run_and_log(cons, f'dd if={fsfile} of={fname} bs=1M seek=1') + u_boot_utils.run_and_log(cons, f'rm -rf {mnt}') + u_boot_utils.run_and_log(cons, f'rm -f {fsfile}') def setup_bootflow_image(cons): """Create a 20MB disk image with a single FAT partition""" mmc_dev = 1 fname, mnt = setup_image(cons, mmc_dev, 0xc, second_part=True) - loop = None - mounted = False - complete = False - try: - loop = mount_image(cons, fname, mnt, 'vfat') - mounted = True - - vmlinux = 'vmlinuz-5.3.7-301.fc31.armv7hl' - initrd = 'initramfs-5.3.7-301.fc31.armv7hl.img' - dtbdir = 'dtb-5.3.7-301.fc31.armv7hl' - script = '''# extlinux.conf generated by appliance-creator + vmlinux = 'vmlinuz-5.3.7-301.fc31.armv7hl' + initrd = 'initramfs-5.3.7-301.fc31.armv7hl.img' + dtbdir = 'dtb-5.3.7-301.fc31.armv7hl' + script = '''# extlinux.conf generated by appliance-creator ui menu.c32 menu autoboot Welcome to Fedora-Workstation-armhfp-31-1.9. Automatic boot in # second{,s}. Press a key for options. menu title Fedora-Workstation-armhfp-31-1.9 Boot Options. @@ -251,39 +197,36 @@ label Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl) append ro root=UUID=9732b35b-4cd5-458b-9b91-80f7047e0b8a rhgb quiet LANG=en_US.UTF-8 cma=192MB cma=256MB fdtdir /%s/ initrd /%s''' % (vmlinux, dtbdir, initrd) - ext = os.path.join(mnt, 'extlinux') - mkdir_cond(ext) + ext = os.path.join(mnt, 'extlinux') + mkdir_cond(ext) - conf = os.path.join(ext, 'extlinux.conf') - with open(conf, 'w', encoding='ascii') as fd: - print(script, file=fd) - - inf = os.path.join(cons.config.persistent_data_dir, 'inf') - with open(inf, 'wb') as fd: - fd.write(gzip.compress(b'vmlinux')) - u_boot_utils.run_and_log( - cons, f'mkimage -f auto -d {inf} {os.path.join(mnt, vmlinux)}') + conf = os.path.join(ext, 'extlinux.conf') + with open(conf, 'w', encoding='ascii') as fd: + print(script, file=fd) - with open(os.path.join(mnt, initrd), 'w', encoding='ascii') as fd: - print('initrd', file=fd) + inf = os.path.join(cons.config.persistent_data_dir, 'inf') + with open(inf, 'wb') as fd: + fd.write(gzip.compress(b'vmlinux')) + mkimage = cons.config.build_dir + '/tools/mkimage' + u_boot_utils.run_and_log( + cons, f'{mkimage} -f auto -d {inf} {os.path.join(mnt, vmlinux)}') - mkdir_cond(os.path.join(mnt, dtbdir)) + with open(os.path.join(mnt, initrd), 'w', encoding='ascii') as fd: + print('initrd', file=fd) - dtb_file = os.path.join(mnt, f'{dtbdir}/sandbox.dtb') - u_boot_utils.run_and_log( - cons, f'dtc -o {dtb_file}', stdin=b'/dts-v1/; / {};') - complete = True - except ValueError as exc: - print(f'Falled to create image, failing back to prepared copy: {exc}') - finally: - if mounted: - u_boot_utils.run_and_log(cons, f'sudo umount --lazy {mnt}') - if loop: - u_boot_utils.run_and_log(cons, f'sudo losetup -d {loop}') + mkdir_cond(os.path.join(mnt, dtbdir)) - if not complete: - copy_prepared_image(cons, mmc_dev, fname) + dtb_file = os.path.join(mnt, f'{dtbdir}/sandbox.dtb') + u_boot_utils.run_and_log( + cons, f'dtc -o {dtb_file}', stdin=b'/dts-v1/; / {};') + fsfile = 'vfat18M.img' + u_boot_utils.run_and_log(cons, f'fallocate -l 18M {fsfile}') + u_boot_utils.run_and_log(cons, f'mkfs.vfat {fsfile}') + u_boot_utils.run_and_log(cons, ['sh', '-c', f'mcopy -i {fsfile} {mnt}/* ::/']) + u_boot_utils.run_and_log(cons, f'dd if={fsfile} of={fname} bs=1M seek=1') + u_boot_utils.run_and_log(cons, f'rm -rf {mnt}') + u_boot_utils.run_and_log(cons, f'rm -f {fsfile}') def setup_cros_image(cons): """Create a 20MB disk image with ChromiumOS partitions""" @@ -334,8 +277,6 @@ def setup_cros_image(cons): mmc_dev = 5 fname = os.path.join(cons.config.source_dir, f'mmc{mmc_dev}.img') u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M') - #mnt = os.path.join(cons.config.persistent_data_dir, 'mnt') - #mkdir_cond(mnt) u_boot_utils.run_and_log(cons, f'cgpt create {fname}') uuid_state = 'ebd0a0a2-b9e5-4433-87c0-68b6b72699c7' @@ -501,6 +442,55 @@ def setup_android_image(cons): print(f'wrote to {fname}') + mmc_dev = 8 + fname = os.path.join(cons.config.source_dir, f'mmc{mmc_dev}.img') + u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M') + u_boot_utils.run_and_log(cons, f'cgpt create {fname}') + + ptr = 40 + + # Number of sectors in 1MB + sect_size = 512 + sect_1mb = (1 << 20) // sect_size + + required_parts = [ + {'num': 1, 'label':'misc', 'size': '1M'}, + {'num': 2, 'label':'boot_a', 'size': '4M'}, + {'num': 3, 'label':'boot_b', 'size': '4M'}, + ] + + for part in required_parts: + size_str = part['size'] + if 'M' in size_str: + size = int(size_str[:-1]) * sect_1mb + else: + size = int(size_str) + u_boot_utils.run_and_log( + cons, + f"cgpt add -i {part['num']} -b {ptr} -s {size} -l {part['label']} -t basicdata {fname}") + ptr += size + + u_boot_utils.run_and_log(cons, f'cgpt boot -p {fname}') + out = u_boot_utils.run_and_log(cons, f'cgpt show -q {fname}') + + # Create a dict (indexed by partition number) containing the above info + for line in out.splitlines(): + start, size, num, name = line.split(maxsplit=3) + parts[int(num)] = Partition(int(start), int(size), name) + + with open(fname, 'rb') as inf: + disk_data = inf.read() + + test_abootimg.AbootimgTestDiskImage(cons, 'boot.img', test_abootimg.img_hex) + boot_img = os.path.join(cons.config.result_dir, 'boot.img') + with open(boot_img, 'rb') as inf: + set_part_data(2, inf.read()) + + with open(fname, 'wb') as outf: + outf.write(disk_data) + + print(f'wrote to {fname}') + return fname def setup_cedit_file(cons): @@ -540,8 +530,8 @@ def test_ut_dm_init(u_boot_console): u_boot_utils.run_and_log( u_boot_console, f'sfdisk {fn}', stdin=b'type=83') - fs_helper.mk_fs(u_boot_console.config, 'ext2', 0x200000, '2MB') - fs_helper.mk_fs(u_boot_console.config, 'fat32', 0x100000, '1MB') + fs_helper.mk_fs(u_boot_console.config, 'ext2', 0x200000, '2MB', None) + fs_helper.mk_fs(u_boot_console.config, 'fat32', 0x100000, '1MB', None) mmc_dev = 6 fn = os.path.join(u_boot_console.config.source_dir, f'mmc{mmc_dev}.img') @@ -557,35 +547,23 @@ def setup_efi_image(cons): fname, mnt = setup_image(cons, devnum, 0xc, second_part=True, basename=basename) - loop = None - mounted = False - complete = False - try: - loop = mount_image(cons, fname, mnt, 'ext4') - mounted = True - efi_dir = os.path.join(mnt, 'EFI') - mkdir_cond(efi_dir) - bootdir = os.path.join(efi_dir, 'BOOT') - mkdir_cond(bootdir) - efi_src = os.path.join(cons.config.build_dir, - f'lib/efi_loader/testapp.efi') - efi_dst = os.path.join(bootdir, 'BOOTSBOX.EFI') - with open(efi_src, 'rb') as inf: - with open(efi_dst, 'wb') as outf: - outf.write(inf.read()) - complete = True - except ValueError as exc: - print(f'Falled to create image, failing back to prepared copy: {exc}') - - finally: - if mounted: - u_boot_utils.run_and_log(cons, 'sudo umount --lazy %s' % mnt) - if loop: - u_boot_utils.run_and_log(cons, 'sudo losetup -d %s' % loop) - - if not complete: - copy_prepared_image(cons, devnum, fname, basename) - + efi_dir = os.path.join(mnt, 'EFI') + mkdir_cond(efi_dir) + bootdir = os.path.join(efi_dir, 'BOOT') + mkdir_cond(bootdir) + efi_src = os.path.join(cons.config.build_dir, + 'lib/efi_loader/testapp.efi') + efi_dst = os.path.join(bootdir, 'BOOTSBOX.EFI') + with open(efi_src, 'rb') as inf: + with open(efi_dst, 'wb') as outf: + outf.write(inf.read()) + fsfile = 'vfat18M.img' + u_boot_utils.run_and_log(cons, f'fallocate -l 18M {fsfile}') + u_boot_utils.run_and_log(cons, f'mkfs.vfat {fsfile}') + u_boot_utils.run_and_log(cons, ['sh', '-c', f'mcopy -vs -i {fsfile} {mnt}/* ::/']) + u_boot_utils.run_and_log(cons, f'dd if={fsfile} of={fname} bs=1M seek=1') + u_boot_utils.run_and_log(cons, f'rm -rf {mnt}') + u_boot_utils.run_and_log(cons, f'rm -f {fsfile}') @pytest.mark.buildconfigspec('cmd_bootflow') @pytest.mark.buildconfigspec('sandbox') diff --git a/test/py/tests/test_zynqmp_rpu.py b/test/py/tests/test_zynqmp_rpu.py index 479a612b4ec..22f687dd6d3 100644 --- a/test/py/tests/test_zynqmp_rpu.py +++ b/test/py/tests/test_zynqmp_rpu.py @@ -70,7 +70,7 @@ def ret_code(u_boot_console): # Initialize tcm def tcminit(u_boot_console, rpu_mode): - output = u_boot_console.run_command('zynqmp tcminit %s' % rpu_mode) + output = u_boot_console.run_command(f'zynqmp tcminit {rpu_mode}') assert 'Initializing TCM overwrites TCM content' in output return ret_code(u_boot_console) @@ -89,6 +89,13 @@ def disable_cpus(u_boot_console, cpu_nums): for num in cpu_nums: u_boot_console.run_command(f'cpu {num} disable') +# Get random RPU mode between string and integer +def get_rpu_mode(rpu_mode): + if rpu_mode == 0 or rpu_mode == 'lockstep': + return random.choice(['lockstep', 0]) + elif rpu_mode == 1 or rpu_mode == 'split': + return random.choice(['split', 1]) + # Load apps on RPU cores def rpu_apps_load(u_boot_console, rpu_mode): apps, procs, cpu_nums, addrs, outputs, tftp_addrs = get_rpu_apps_env( @@ -98,20 +105,20 @@ def rpu_apps_load(u_boot_console, rpu_mode): test_net.test_net_setup_static(u_boot_console) try: - assert tcminit(u_boot_console, rpu_mode).endswith('0') + assert tcminit(u_boot_console, get_rpu_mode(rpu_mode)).endswith('0') for i in range(len(apps)): if rpu_mode == 'lockstep' and procs[i] != 'rpu0': continue load_app_ddr(u_boot_console, tftp_addrs[i], apps[i]) - rel_addr = int(addrs[i] + 0x3C) + rel_addr = hex(int(addrs[i] + 0x3C)) # Release cpu at app load address cpu_num = cpu_nums[i] - cmd = 'cpu %d release %x %s' % (cpu_num, rel_addr, rpu_mode) + cmd = f'cpu {cpu_num} release {rel_addr} {rpu_mode}' output = u_boot_console.run_command(cmd) - exp_op = f'Using TCM jump trampoline for address {hex(rel_addr)}' + exp_op = f'Using TCM jump trampoline for address {rel_addr}' assert exp_op in output assert f'R5 {rpu_mode} mode' in output u_boot_console.wait_for(outputs[i]) @@ -133,16 +140,13 @@ def test_zynqmp_rpu_app_load_negative(u_boot_console): u_boot_console) # Invalid commands - u_boot_console.run_command('zynqmp tcminit mode') - assert ret_code(u_boot_console).endswith('1') - rand_str = ''.join(random.choices(string.ascii_lowercase, k=4)) - u_boot_console.run_command('zynqmp tcminit %s' % rand_str) - assert ret_code(u_boot_console).endswith('1') - rand_num = random.randint(2, 100) - u_boot_console.run_command('zynqmp tcminit %d' % rand_num) - assert ret_code(u_boot_console).endswith('1') + inv_modes = ['mode', rand_str, rand_num, 'splittt', 'locksteppp', '00', 11] + + for mode in inv_modes: + u_boot_console.run_command(f'zynqmp tcminit {mode}') + assert ret_code(u_boot_console).endswith('1') test_net.test_net_dhcp(u_boot_console) if not test_net.net_set_up: @@ -150,56 +154,66 @@ def test_zynqmp_rpu_app_load_negative(u_boot_console): try: rpu_mode = 'split' - assert tcminit(u_boot_console, rpu_mode).endswith('0') + assert tcminit(u_boot_console, get_rpu_mode(rpu_mode)).endswith('0') + inv_modes += [0, 1] for i in range(len(apps)): load_app_ddr(u_boot_console, tftp_addrs[i], apps[i]) # Run in split mode at different load address - rel_addr = int(addrs[i]) + random.randint(200, 1000) + rel_addr = hex(int(addrs[i]) + random.randint(200, 1000)) cpu_num = cpu_nums[i] - cmd = 'cpu %d release %x %s' % (cpu_num, rel_addr, rpu_mode) + cmd = f'cpu {cpu_num} release {rel_addr} {rpu_mode}' output = u_boot_console.run_command(cmd) - exp_op = f'Using TCM jump trampoline for address {hex(rel_addr)}' + exp_op = f'Using TCM jump trampoline for address {rel_addr}' assert exp_op in output assert f'R5 {rpu_mode} mode' in output assert not outputs[i] in output # Invalid rpu mode - rand_str = ''.join(random.choices(string.ascii_lowercase, k=4)) - cmd = 'cpu %d release %x %s' % (cpu_num, rel_addr, rand_str) - output = u_boot_console.run_command(cmd) - assert exp_op in output - assert f'Unsupported mode' in output - assert not ret_code(u_boot_console).endswith('0') + for mode in inv_modes: + cmd = f'cpu {cpu_num} release {rel_addr} {mode}' + output = u_boot_console.run_command(cmd) + assert exp_op in output + assert f'Unsupported mode' in output + assert not ret_code(u_boot_console).endswith('0') # Switch to lockstep mode, without disabling CPUs rpu_mode = 'lockstep' - u_boot_console.run_command('zynqmp tcminit %s' % rpu_mode) - assert not ret_code(u_boot_console).endswith('0') + output = u_boot_console.run_command( + f'zynqmp tcminit {get_rpu_mode(rpu_mode)}' + ) + assert 'ERROR: ' in output # Disable cpus disable_cpus(u_boot_console, cpu_nums) # Switch to lockstep mode, after disabling CPUs - output = u_boot_console.run_command('zynqmp tcminit %s' % rpu_mode) + output = u_boot_console.run_command( + f'zynqmp tcminit {get_rpu_mode(rpu_mode)}' + ) assert 'Initializing TCM overwrites TCM content' in output assert ret_code(u_boot_console).endswith('0') - # Run lockstep mode for RPU1 + # Run lockstep mode for RPU1/RPU0 for i in range(len(apps)): - if procs[i] == 'rpu0': - continue - load_app_ddr(u_boot_console, tftp_addrs[i], apps[i]) - rel_addr = int(addrs[i] + 0x3C) + rel_addr = hex(int(addrs[i] + 0x3C)) cpu_num = cpu_nums[i] - cmd = 'cpu %d release %x %s' % (cpu_num, rel_addr, rpu_mode) + cmd = f'cpu {cpu_num} release {rel_addr} {rpu_mode}' output = u_boot_console.run_command(cmd) - exp_op = f'Using TCM jump trampoline for address {hex(rel_addr)}' + exp_op = f'Using TCM jump trampoline for address {rel_addr}' assert exp_op in output - assert f'R5 {rpu_mode} mode' in output - assert u_boot_console.p.expect([outputs[i]]) + + if procs[i] == 'rpu1': + assert 'Lockstep mode should run on ZYNQMP_CORE_RPU0' in output + assert not ret_code(u_boot_console).endswith('0') + elif procs[i] == 'rpu0': + assert f'R5 {rpu_mode} mode' in output + u_boot_console.wait_for(outputs[i]) + assert ret_code(u_boot_console).endswith('0') + else: + assert False, 'ERROR: Invalid processor!' finally: disable_cpus(u_boot_console, cpu_nums) # This forces the console object to be shutdown, so any subsequent test diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py index fa9cd57b04b..7eaceb39d9d 100644 --- a/test/py/u_boot_console_base.py +++ b/test/py/u_boot_console_base.py @@ -342,11 +342,12 @@ class ConsoleBase(object): # indentation. return self.p.before.strip('\r\n') except Timeout as exc: - handle_exception(self.config, self, self.log, exc, 'Lab failure', - True) + handle_exception(self.config, self, self.log, exc, + f"Lab failure: Timeout executing '{cmd}'", True) raise except BootFail as exc: - handle_exception(self.config, self, self.log, exc, 'Boot fail', + handle_exception(self.config, self, self.log, exc, + f"'Boot fail '{cmd}'", True, self.get_spawn_output()) raise finally: diff --git a/tools/buildman/boards.py b/tools/buildman/boards.py index 3c2822715f3..9e7b486656b 100644 --- a/tools/buildman/boards.py +++ b/tools/buildman/boards.py @@ -19,7 +19,10 @@ import time from buildman import board from buildman import kconfiglib +from u_boot_pylib import command from u_boot_pylib.terminal import print_clear, tprint +from u_boot_pylib import tools +from u_boot_pylib import tout ### constant variables ### OUTPUT_FILE = 'boards.cfg' @@ -202,6 +205,7 @@ class KconfigScanner: os.environ['KCONFIG_OBJDIR'] = '' self._tmpfile = None self._conf = kconfiglib.Kconfig(warn=False) + self._srctree = srctree def __del__(self): """Delete a leftover temporary file before exit. @@ -239,7 +243,26 @@ class KconfigScanner: expect_target, match, rear = leaf.partition('_defconfig') assert match and not rear, f'{leaf} : invalid defconfig' - self._conf.load_config(defconfig) + temp = None + if b'#include' in tools.read_file(defconfig): + cmd = [ + os.getenv('CPP', 'cpp'), + '-nostdinc', '-P', + '-I', self._srctree, + '-undef', + '-x', 'assembler-with-cpp', + defconfig] + result = command.run_pipe([cmd], capture=True, capture_stderr=True) + temp = tempfile.NamedTemporaryFile(prefix='buildman-') + tools.write_file(temp.name, result.stdout, False) + fname = temp.name + tout.info(f'Processing #include to produce {defconfig}') + else: + fname = defconfig + + self._conf.load_config(fname) + if temp: + del temp self._tmpfile = None params = {} diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst index e873611e596..924564b5700 100644 --- a/tools/buildman/buildman.rst +++ b/tools/buildman/buildman.rst @@ -186,23 +186,22 @@ Setting up #. Create ~/.buildman to tell buildman where to find tool chains (see buildman_settings_ for details). As an example:: - # Buildman settings file + # Buildman settings file - [toolchain] - root: / - rest: /toolchains/* - eldk: /opt/eldk-4.2 - arm: /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.08_linux - aarch64: /opt/linaro/gcc-linaro-aarch64-none-elf-4.8-2013.10_linux + [toolchain] + root: / + rest: /toolchains/* + eldk: /opt/eldk-4.2 + arm: /opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.08_linux + aarch64: /opt/linaro/gcc-linaro-aarch64-none-elf-4.8-2013.10_linux - [toolchain-prefix] - arc = /opt/arc/arc_gnu_2021.03_prebuilt_elf32_le_linux_install/bin/arc-elf32- - - [toolchain-alias] - riscv = riscv32 - sh = sh4 - x86: i386 + [toolchain-prefix] + arc = /opt/arc/arc_gnu_2021.03_prebuilt_elf32_le_linux_install/bin/arc-elf32- + [toolchain-alias] + riscv = riscv32 + sh = sh4 + x86: i386 This selects the available toolchain paths. Add the base directory for each of your toolchains here. Buildman will search inside these directories @@ -934,6 +933,18 @@ a set of (tag, value) pairs. For example powerpc-linux-gcc will be noted as a toolchain for 'powerpc' and CROSS_COMPILE will be set to powerpc-linux- when using it. + The tilde character ``~`` is supported in paths, to represent the home + directory. + +'[toolchain-prefix]' section + This can be used to provide the full toolchain-prefix for one or more + architectures. The full CROSS_COMPILE prefix must be provided. These + typically have a higher priority than matches in the '[toolchain]', due to + this prefix. + + The tilde character ``~`` is supported in paths, to represent the home + directory. + '[toolchain-alias]' section This converts toolchain architecture names to U-Boot names. For example, if an x86 toolchains is called i386-linux-gcc it will not normally be @@ -1112,6 +1123,30 @@ The -U option uses the u-boot.env files which are produced by a build. Internally, buildman writes out an out-env file into the build directory for later comparison. +defconfig fragments +------------------- + +Buildman provides some initial support for configuration fragments. It can scan +these when present in defconfig files and handle the resuiting Kconfig +correctly. Thus it is possible to build a board which has a ``#include`` in the +defconfig file. + +For now, Buildman simply includes the files to produce a single output file, +using the C preprocessor. It does not call the ``merge_config.sh`` script. The +redefined/redundant logic in that script could fairly easily be repeated in +Buildman, to detect potential problems. For now it is not clear that this is +useful. + +To specify the C preprocessor to use, set the ``CPP`` environment variable. The +default is ``cpp``. + +Note that Buildman does not support adding fragments to existing boards, e.g. +like:: + + make qemu_riscv64_defconfig acpi.config + +This is partly because there is no way for Buildman to know which fragments are +valid on which boards. Building with clang ------------------- diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py index 0ac9fc7e44f..4e12c671a3d 100644 --- a/tools/buildman/func_test.py +++ b/tools/buildman/func_test.py @@ -2,8 +2,10 @@ # Copyright (c) 2014 Google, Inc # +import io import os from pathlib import Path +import re import shutil import sys import tempfile @@ -373,6 +375,22 @@ class TestFunctional(unittest.TestCase): def _HandleCommandSize(self, args): return command.CommandResult(return_code=0) + def _HandleCommandCpp(self, args): + # args ['-nostdinc', '-P', '-I', '/tmp/tmp7f17xk_o/src', '-undef', + # '-x', 'assembler-with-cpp', fname] + fname = args[7] + buf = io.StringIO() + for line in tools.read_file(fname, False).splitlines(): + if line.startswith('#include'): + # Example: #include <configs/renesas_rcar2.config> + m_incfname = re.match('#include <(.*)>', line) + data = tools.read_file(m_incfname.group(1), False) + for line in data.splitlines(): + print(line, file=buf) + else: + print(line, file=buf) + return command.CommandResult(stdout=buf.getvalue(), return_code=0) + def _HandleCommand(self, **kwargs): """Handle a command execution. @@ -406,6 +424,8 @@ class TestFunctional(unittest.TestCase): return self._HandleCommandObjcopy(args) elif cmd.endswith( 'size'): return self._HandleCommandSize(args) + elif cmd.endswith( 'cpp'): + return self._HandleCommandCpp(args) if not result: # Not handled, so abort @@ -1067,3 +1087,68 @@ endif result = self._RunControl('--print-arch', 'board0') self.assertEqual('arm\n', stdout.getvalue()) self.assertEqual('', stderr.getvalue()) + + def test_kconfig_scanner(self): + """Test using the kconfig scanner to determine important values + + Note that there is already a test_scan_defconfigs() which checks the + higher-level scan_defconfigs() function. This test checks just the + scanner itself + """ + src = self._git_dir + scanner = boards.KconfigScanner(src) + + # First do a simple sanity check + norm = os.path.join(src, 'board0_defconfig') + tools.write_file(norm, 'CONFIG_TARGET_BOARD0=y', False) + res = scanner.scan(norm, True) + self.assertEqual(({ + 'arch': 'arm', + 'cpu': 'armv7', + 'soc': '-', + 'vendor': 'Tester', + 'board': 'ARM Board 0', + 'config': 'config0', + 'target': 'board0'}, []), res) + + # Check that the SoC cannot be changed and the filename does not affect + # the resulting board + tools.write_file(norm, '''CONFIG_TARGET_BOARD2=y +CONFIG_SOC="fred" +''', False) + res = scanner.scan(norm, True) + self.assertEqual(({ + 'arch': 'powerpc', + 'cpu': 'ppc', + 'soc': 'mpc85xx', + 'vendor': 'Tester', + 'board': 'PowerPC board 1', + 'config': 'config2', + 'target': 'board0'}, []), res) + + # Check handling of missing information + tools.write_file(norm, '', False) + res = scanner.scan(norm, True) + self.assertEqual(({ + 'arch': '-', + 'cpu': '-', + 'soc': '-', + 'vendor': '-', + 'board': '-', + 'config': '-', + 'target': 'board0'}, + ['WARNING: board0_defconfig: No TARGET_BOARD0 enabled']), res) + + # check handling of #include files; see _HandleCommandCpp() + inc = os.path.join(src, 'common') + tools.write_file(inc, b'CONFIG_TARGET_BOARD0=y\n') + tools.write_file(norm, f'#include <{inc}>', False) + res = scanner.scan(norm, True) + self.assertEqual(({ + 'arch': 'arm', + 'cpu': 'armv7', + 'soc': '-', + 'vendor': 'Tester', + 'board': 'ARM Board 0', + 'config': 'config0', + 'target': 'board0'}, []), res) diff --git a/tools/buildman/main.py b/tools/buildman/main.py index 3cf877e5e68..a948f36d9c0 100755 --- a/tools/buildman/main.py +++ b/tools/buildman/main.py @@ -25,6 +25,7 @@ from buildman import cmdline from buildman import control from u_boot_pylib import test_util from u_boot_pylib import tools +from u_boot_pylib import tout def run_tests(skip_net_tests, debug, verbose, args): """Run the buildman tests @@ -93,8 +94,12 @@ def run_buildman(): # Build selected commits for selected boards else: - bsettings.setup(args.config_file) - ret_code = control.do_buildman(args) + try: + tout.init(tout.INFO if args.verbose else tout.WARNING) + bsettings.setup(args.config_file) + ret_code = control.do_buildman(args) + finally: + tout.uninit() return ret_code diff --git a/tools/buildman/test.py b/tools/buildman/test.py index 15801f6097f..385a34e5254 100644 --- a/tools/buildman/test.py +++ b/tools/buildman/test.py @@ -46,6 +46,16 @@ main: /usr/sbin wrapper = ccache ''' +settings_data_homedir = ''' +# Buildman settings file + +[toolchain] +main = ~/mypath + +[toolchain-prefix] +x86 = ~/mypath-x86- +''' + migration = '''===================== WARNING ====================== This board does not use CONFIG_DM. CONFIG_DM will be compulsory starting with the v2020.01 release. @@ -1030,6 +1040,46 @@ class TestBuild(unittest.TestCase): finally: os.environ['PATH'] = old_path + def testHomedir(self): + """Test using ~ in a toolchain or toolchain-prefix section""" + # Add some test settings + bsettings.setup(None) + bsettings.add_file(settings_data_homedir) + + # Set up the toolchains + home = os.path.expanduser('~') + toolchains = toolchain.Toolchains() + toolchains.GetSettings() + self.assertEqual([f'{home}/mypath'], toolchains.paths) + + # Check scanning + with test_util.capture_sys_output() as (stdout, _): + toolchains.Scan(verbose=True, raise_on_error=False) + lines = iter(stdout.getvalue().splitlines() + ['##done']) + self.assertEqual('Scanning for tool chains', next(lines)) + self.assertEqual(f" - scanning prefix '{home}/mypath-x86-'", + next(lines)) + self.assertEqual( + f"Error: No tool chain found for prefix '{home}/mypath-x86-gcc'", + next(lines)) + self.assertEqual(f" - scanning path '{home}/mypath'", next(lines)) + self.assertEqual(f" - looking in '{home}/mypath/.'", next(lines)) + self.assertEqual(f" - looking in '{home}/mypath/bin'", next(lines)) + self.assertEqual(f" - looking in '{home}/mypath/usr/bin'", + next(lines)) + self.assertEqual('##done', next(lines)) + + # Check adding a toolchain + with test_util.capture_sys_output() as (stdout, _): + toolchains.Add('~/aarch64-linux-gcc', test=True, verbose=True) + lines = iter(stdout.getvalue().splitlines() + ['##done']) + self.assertEqual('Tool chain test: BAD', next(lines)) + self.assertEqual(f'Command: {home}/aarch64-linux-gcc --version', + next(lines)) + self.assertEqual('', next(lines)) + self.assertEqual('', next(lines)) + self.assertEqual('##done', next(lines)) + if __name__ == "__main__": unittest.main() diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index 0c8a4fa16eb..958f36f9f61 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -65,12 +65,13 @@ class Toolchain: """Create a new toolchain object. Args: - fname: Filename of the gcc component + fname: Filename of the gcc component, possibly with ~ or $HOME in it test: True to run the toolchain to test it verbose: True to print out the information priority: Priority to use for this toolchain, or PRIORITY_CALC to calculate it """ + fname = os.path.expanduser(fname) self.gcc = fname self.path = os.path.dirname(fname) self.override_toolchain = override_toolchain @@ -109,7 +110,7 @@ class Toolchain: self.priority)) else: print('BAD') - print('Command: ', cmd) + print(f"Command: {' '.join(cmd)}") print(result.stdout) print(result.stderr) else: @@ -296,10 +297,11 @@ class Toolchains: paths = [] for name, value in toolchains: + fname = os.path.expanduser(value) if '*' in value: - paths += glob.glob(value) + paths += glob.glob(fname) else: - paths.append(value) + paths.append(fname) return paths def GetSettings(self, show_warning=True): @@ -327,16 +329,17 @@ class Toolchains: toolchain = Toolchain(fname, test, verbose, priority, arch, self.override_toolchain) add_it = toolchain.ok - if toolchain.arch in self.toolchains: - add_it = (toolchain.priority < - self.toolchains[toolchain.arch].priority) if add_it: - self.toolchains[toolchain.arch] = toolchain - elif verbose: - print(("Toolchain '%s' at priority %d will be ignored because " - "another toolchain for arch '%s' has priority %d" % - (toolchain.gcc, toolchain.priority, toolchain.arch, - self.toolchains[toolchain.arch].priority))) + if toolchain.arch in self.toolchains: + add_it = (toolchain.priority < + self.toolchains[toolchain.arch].priority) + if add_it: + self.toolchains[toolchain.arch] = toolchain + elif verbose: + print(("Toolchain '%s' at priority %d will be ignored because " + "another toolchain for arch '%s' has priority %d" % + (toolchain.gcc, toolchain.priority, toolchain.arch, + self.toolchains[toolchain.arch].priority))) def ScanPath(self, path, verbose): """Scan a path for a valid toolchain @@ -372,7 +375,7 @@ class Toolchains: pathname_list.append(pathname) return pathname_list - def Scan(self, verbose): + def Scan(self, verbose, raise_on_error=True): """Scan for available toolchains and select the best for each arch. We look for all the toolchains we can file, figure out the @@ -384,11 +387,12 @@ class Toolchains: """ if verbose: print('Scanning for tool chains') for name, value in self.prefixes: - if verbose: print(" - scanning prefix '%s'" % value) - if os.path.exists(value): - self.Add(value, True, verbose, PRIORITY_FULL_PREFIX, name) + fname = os.path.expanduser(value) + if verbose: print(" - scanning prefix '%s'" % fname) + if os.path.exists(fname): + self.Add(fname, True, verbose, PRIORITY_FULL_PREFIX, name) continue - fname = value + 'gcc' + fname += 'gcc' if os.path.exists(fname): self.Add(fname, True, verbose, PRIORITY_PREFIX_GCC, name) continue @@ -396,8 +400,11 @@ class Toolchains: for f in fname_list: self.Add(f, True, verbose, PRIORITY_PREFIX_GCC_PATH, name) if not fname_list: - raise ValueError("No tool chain found for prefix '%s'" % - value) + msg = f"No tool chain found for prefix '{fname}'" + if raise_on_error: + raise ValueError(msg) + else: + print(f'Error: {msg}') for path in self.paths: if verbose: print(" - scanning path '%s'" % path) fnames = self.ScanPath(path, verbose) diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index 967ac89fbde..ce1ad7cb23a 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -6,33 +6,58 @@ FROM ubuntu:jammy-20240808 LABEL org.opencontainers.image.authors="Tom Rini <trini@konsulko.com>" LABEL org.opencontainers.image.description=" This image is for building U-Boot inside a container" +# Used by docker to set the target platform: valid values are linux/arm64/v8 +# and linux/amd64 +ARG TARGETPLATFORM + +# Used by docker to set the build platform: the only valid value is linux/amd64 +ARG BUILDPLATFORM + # Make sure apt is happy ENV DEBIAN_FRONTEND=noninteractive +# Set architectures to build for (leaving out ARM which is an exception) +ENV ARCHS="aarch64 arc i386 m68k mips microblaze nios2 powerpc riscv64 riscv32 sh2 x86_64" + +# Mirror containing the toolchains +ENV MIRROR=https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin + +# Toolchain version +ENV TCVER=13.2.0 + +RUN echo "Building on $BUILDPLATFORM, for target $TARGETPLATFORM" + # Add LLVM repository -RUN apt-get update && apt-get install -y gnupg2 wget xz-utils && rm -rf /var/lib/apt/lists/* +RUN --mount=type=cache,target=/var/cache/apt,sharing=locked \ + --mount=type=cache,target=/var/lib/apt,sharing=locked \ + apt-get update && apt-get install -y gnupg2 wget xz-utils RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add - RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-17 main | tee /etc/apt/sources.list.d/llvm.list -# Manually install the kernel.org "Crosstool" based toolchains for gcc-13.2.0 -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-arc-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-arm-linux-gnueabi.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-i386-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-m68k-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-mips-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-microblaze-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-nios2-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-powerpc-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-riscv64-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-riscv32-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-sh2-linux.tar.xz | tar -C /opt -xJ +# Create a list of URLs to process, then pass them into a 'while read' loop +RUN if [ "$TARGETPLATFORM" = "linux/amd64" ]; then HOSTARCH=x86_64; else HOSTARCH=arm64; fi; ( \ + # Manually install the kernel.org "Crosstool"-based toolchains + for arch in $ARCHS; do \ + echo $MIRROR/$HOSTARCH/$TCVER/${HOSTARCH}-gcc-$TCVER-nolibc-${arch}-linux.tar.xz; \ + done; \ + \ + # Deal with ARM, which has a 'gnueabi' suffix + echo $MIRROR/${HOSTARCH}/$TCVER/${HOSTARCH}-gcc-$TCVER-nolibc-arm-linux-gnueabi.tar.xz; \ + \ + ) | while read url; do \ + # Read the URL and unpack it into /opt + wget -O - $url | tar -C /opt -xJ; \ + done # Manually install other toolchains -RUN wget -O - https://github.com/foss-xtensa/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc233c-elf.tar.gz | tar -C /opt -xz +RUN if [ "$TARGETPLATFORM" = "linux/amd64" ]; then \ + wget -O - https://github.com/foss-xtensa/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc233c-elf.tar.gz | tar -C /opt -xz; \ + fi # Update and install things from apt now -RUN apt-get update && apt-get install -y \ +RUN --mount=type=cache,target=/var/cache/apt,sharing=locked \ + --mount=type=cache,target=/var/lib/apt,sharing=locked \ + apt-get update && apt-get install -y \ automake \ autopoint \ bc \ @@ -54,17 +79,15 @@ RUN apt-get update && apt-get install -y \ flex \ gawk \ gdisk \ + gettext \ git \ gnu-efi \ gnutls-dev \ graphviz \ - grub-efi-amd64-bin \ - grub-efi-ia32-bin \ help2man \ iasl \ imagemagick \ iputils-ping \ - libc6-i386 \ libconfuse-dev \ libgit2-dev \ libjson-glib-dev \ @@ -82,7 +105,7 @@ RUN apt-get update && apt-get install -y \ libtool \ libudev-dev \ libusb-1.0-0-dev \ - linux-image-kvm \ + linux-image-generic \ lzma-alone \ lzop \ mount \ @@ -118,8 +141,7 @@ RUN apt-get update && apt-get install -y \ vboot-utils \ xilinx-bootgen \ xxd \ - zip \ - && rm -rf /var/lib/apt/lists/* + zip # Make kernels readable for libguestfs tools to work correctly RUN chmod +r /boot/vmlinu* @@ -127,11 +149,9 @@ RUN chmod +r /boot/vmlinu* # Build GRUB UEFI targets for ARM & RISC-V, 32-bit and 64-bit RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ cd /tmp/grub && \ - git checkout grub-2.06 && \ + git checkout grub-2.12 && \ git config --global user.name "GitLab CI Runner" && \ git config --global user.email trini@konsulko.com && \ - git cherry-pick 049efdd72eb7baa7b2bf8884391ee7fe650da5a0 && \ - git cherry-pick 403d6540cd608b2706cfa0cb4713f7e4b490ff45 && \ ./bootstrap && \ mkdir -p /opt/grub && \ ./configure --target=aarch64 --with-platform=efi \ @@ -141,7 +161,7 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ TARGET_STRIP=/opt/gcc-13.2.0-nolibc/aarch64-linux/bin/aarch64-linux-strip \ TARGET_NM=/opt/gcc-13.2.0-nolibc/aarch64-linux/bin/aarch64-linux-nm \ TARGET_RANLIB=/opt/gcc-13.2.0-nolibc/aarch64-linux/bin/aarch64-linux-ranlib && \ - make && \ + make -j$(nproc) && \ ./grub-mkimage -O arm64-efi -o /opt/grub/grubaa64.efi --prefix= -d \ grub-core cat chain configfile echo efinet ext2 fat halt help linux \ lsefisystab loadenv lvm minicmd normal part_msdos part_gpt reboot \ @@ -155,7 +175,7 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ TARGET_STRIP=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-strip \ TARGET_NM=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-nm \ TARGET_RANLIB=/opt/gcc-13.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ranlib && \ - make && \ + make -j$(nproc) && \ ./grub-mkimage -O arm-efi -o /opt/grub/grubarm.efi --prefix= -d \ grub-core cat chain configfile echo efinet ext2 fat halt help linux \ lsefisystab loadenv lvm minicmd normal part_msdos part_gpt reboot \ @@ -169,12 +189,34 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ TARGET_STRIP=/opt/gcc-13.2.0-nolibc/riscv64-linux/bin/riscv64-linux-strip \ TARGET_NM=/opt/gcc-13.2.0-nolibc/riscv64-linux/bin/riscv64-linux-nm \ TARGET_RANLIB=/opt/gcc-13.2.0-nolibc/riscv64-linux/bin/riscv64-linux-ranlib && \ - make && \ + make -j$(nproc) && \ ./grub-mkimage -O riscv64-efi -o /opt/grub/grubriscv64.efi --prefix= -d \ grub-core cat chain configfile echo efinet ext2 fat halt help linux \ lsefisystab loadenv lvm minicmd normal part_msdos part_gpt reboot \ search search_fs_file search_fs_uuid search_label serial sleep test \ true && \ + make clean && \ + ./configure --target=i386 --with-platform=efi \ + CC=gcc \ + TARGET_CC=/opt/gcc-13.2.0-nolibc/i386-linux/bin/i386-linux-gcc \ + TARGET_OBJCOPY=/opt/gcc-13.2.0-nolibc/i386-linux/bin/i386-linux-objcopy \ + TARGET_STRIP=/opt/gcc-13.2.0-nolibc/i386-linux/bin/i386-linux-strip \ + TARGET_NM=/opt/gcc-13.2.0-nolibc/i386-linux/bin/i386-linux-nm \ + TARGET_RANLIB=/opt/gcc-13.2.0-nolibc/i386-linux/bin/i386-linux-ranlib && \ + make -j$(nproc) && \ + ./grub-mkimage -O i386-efi -o /opt/grub/grub_x86.efi --prefix= -d \ + grub-core normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd && \ + make clean && \ + ./configure --target=x86_64 --with-platform=efi \ + CC=gcc \ + TARGET_CC=/opt/gcc-13.2.0-nolibc/x86_64-linux/bin/x86_64-linux-gcc \ + TARGET_OBJCOPY=/opt/gcc-13.2.0-nolibc/x86_64-linux/bin/x86_64-linux-objcopy \ + TARGET_STRIP=/opt/gcc-13.2.0-nolibc/x86_64-linux/bin/x86_64-linux-strip \ + TARGET_NM=/opt/gcc-13.2.0-nolibc/x86_64-linux/bin/x86_64-linux-nm \ + TARGET_RANLIB=/opt/gcc-13.2.0-nolibc/x86_64-linux/bin/x86_64-linux-ranlib && \ + make -j$(nproc) && \ + ./grub-mkimage -O x86_64-efi -o /opt/grub/grub_x64.efi --prefix= -d \ + grub-core normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd && \ rm -rf /tmp/grub RUN git clone https://gitlab.com/qemu-project/qemu.git /tmp/qemu && \ @@ -195,7 +237,7 @@ RUN git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git /tmp/t cd /tmp/tf-a/ && \ git checkout v2.10.0 && \ cd tools/fiptool && \ - make && \ + make -j$(nproc) && \ mkdir -p /usr/local/bin && \ cp fiptool /usr/local/bin && \ rm -rf /tmp/tf-a @@ -280,9 +322,8 @@ RUN /bin/echo -e "[toolchain]\nroot = /usr" > ~/.buildman RUN /bin/echo -e "kernelorg = /opt/gcc-13.2.0-nolibc/*" >> ~/.buildman RUN /bin/echo -e "\n[toolchain-prefix]\nxtensa = /opt/2020.07/xtensa-dc233c-elf/bin/xtensa-dc233c-elf-" >> ~/.buildman; RUN /bin/echo -e "\n[toolchain-alias]\nsh = sh2" >> ~/.buildman -RUN /bin/echo -e "\nsandbox = x86_64" >> ~/.buildman RUN /bin/echo -e "\nx86 = i386" >> ~/.buildman; # Add mkbootimg tool RUN git clone https://android.googlesource.com/platform/system/tools/mkbootimg /home/uboot/mkbootimg -ENV PYTHONPATH "${PYTHONPATH}:/home/uboot/mkbootimg" +ENV PYTHONPATH="${PYTHONPATH}:/home/uboot/mkbootimg" diff --git a/tools/imx8image.c b/tools/imx8image.c index 7a060811c7e..15510d3e712 100644 --- a/tools/imx8image.c +++ b/tools/imx8image.c @@ -734,7 +734,7 @@ static int get_container_image_start_pos(image_t *image_stack, uint32_t align) fclose(fd); if (header.tag != IVT_HEADER_TAG_B0) { - fprintf(stderr, "header tag mismatched \n"); + fprintf(stderr, "header tag mismatched file %s\n", img_sp->filename); exit(EXIT_FAILURE); } else { file_off += diff --git a/tools/imx_cntr_image.sh b/tools/imx_cntr_image.sh index 972b95ccbee..07acd385631 100755 --- a/tools/imx_cntr_image.sh +++ b/tools/imx_cntr_image.sh @@ -14,6 +14,10 @@ for f in $blobs; do continue fi + if [ $f = "spl/u-boot-spl.bin" ]; then + continue + fi + if [ -f $f ]; then continue fi |